ahd_pci.c revision 105202
1/*
2 * FreeBSD, PCI product support functions
3 *
4 * Copyright (c) 1995-2001 Justin T. Gibbs
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions, and the following disclaimer,
12 *    without modification, immediately at the beginning of the file.
13 * 2. The name of the author may not be used to endorse or promote products
14 *    derived from this software without specific prior written permission.
15 *
16 * Alternatively, this software may be distributed under the terms of the
17 * GNU Public License ("GPL").
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/ahd_pci.c#7 $
32 *
33 * $FreeBSD: head/sys/dev/aic7xxx/ahd_pci.c 105202 2002-10-16 02:59:03Z gibbs $
34 */
35
36#include <dev/aic7xxx/aic79xx_osm.h>
37
38#define	AHD_PCI_IOADDR0 PCIR_MAPS	/* Primary I/O BAR */
39#define	AHD_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
40#define	AHD_PCI_IOADDR1 (PCIR_MAPS + 12)/* Secondary I/O BAR */
41
42static int ahd_pci_probe(device_t dev);
43static int ahd_pci_attach(device_t dev);
44
45static device_method_t ahd_pci_device_methods[] = {
46	/* Device interface */
47	DEVMETHOD(device_probe,		ahd_pci_probe),
48	DEVMETHOD(device_attach,	ahd_pci_attach),
49	DEVMETHOD(device_detach,	ahd_detach),
50	{ 0, 0 }
51};
52
53static driver_t ahd_pci_driver = {
54	"ahd",
55	ahd_pci_device_methods,
56	sizeof(struct ahd_softc)
57};
58
59static devclass_t ahd_devclass;
60
61DRIVER_MODULE(ahd, pci, ahd_pci_driver, ahd_devclass, 0, 0);
62DRIVER_MODULE(ahd, cardbus, ahd_pci_driver, ahd_devclass, 0, 0);
63MODULE_DEPEND(ahd_pci, ahd, 1, 1, 1);
64MODULE_VERSION(ahd_pci, 1);
65
66static int
67ahd_pci_probe(device_t dev)
68{
69	struct	ahd_pci_identity *entry;
70
71	entry = ahd_find_pci_device(dev);
72	if (entry != NULL) {
73		device_set_desc(dev, entry->name);
74		return (0);
75	}
76	return (ENXIO);
77}
78
79static int
80ahd_pci_attach(device_t dev)
81{
82	struct	 ahd_pci_identity *entry;
83	struct	 ahd_softc *ahd;
84	char	*name;
85	int	 error;
86
87	entry = ahd_find_pci_device(dev);
88	if (entry == NULL)
89		return (ENXIO);
90
91	/*
92	 * Allocate a softc for this card and
93	 * set it up for attachment by our
94	 * common detect routine.
95	 */
96	name = malloc(strlen(device_get_nameunit(dev)) + 1, M_DEVBUF, M_NOWAIT);
97	if (name == NULL)
98		return (ENOMEM);
99	strcpy(name, device_get_nameunit(dev));
100	ahd = ahd_alloc(dev, name);
101	if (ahd == NULL)
102		return (ENOMEM);
103
104	ahd_set_unit(ahd, device_get_unit(dev));
105
106	/*
107	 * Should we bother disabling 39Bit addressing
108	 * based on installed memory?
109	 */
110	if (sizeof(bus_addr_t) > 4)
111                ahd->flags |= AHD_39BIT_ADDRESSING;
112
113	/* Allocate a dmatag for our SCB DMA maps */
114	/* XXX Should be a child of the PCI bus dma tag */
115	error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
116				   /*boundary*/0,
117				   (ahd->flags & AHD_39BIT_ADDRESSING)
118				   ? 0x7FFFFFFFFF
119				   : BUS_SPACE_MAXADDR_32BIT,
120				   /*highaddr*/BUS_SPACE_MAXADDR,
121				   /*filter*/NULL, /*filterarg*/NULL,
122				   /*maxsize*/MAXBSIZE, /*nsegments*/AHD_NSEG,
123				   /*maxsegsz*/AHD_MAXTRANSFER_SIZE,
124				   /*flags*/BUS_DMA_ALLOCNOW,
125				   &ahd->parent_dmat);
126
127	if (error != 0) {
128		printf("ahd_pci_attach: Could not allocate DMA tag "
129		       "- error %d\n", error);
130		ahd_free(ahd);
131		return (ENOMEM);
132	}
133	ahd->dev_softc = dev;
134	error = ahd_pci_config(ahd, entry);
135	if (error != 0) {
136		ahd_free(ahd);
137		return (error);
138	}
139
140	ahd_attach(ahd);
141	return (0);
142}
143
144int
145ahd_pci_map_registers(struct ahd_softc *ahd)
146{
147	struct	resource *regs;
148	struct	resource *regs2;
149	u_int	command;
150	int	regs_type;
151	int	regs_id;
152	int	regs_id2;
153
154	command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1);
155	regs = NULL;
156	regs2 = NULL;
157	regs_type = 0;
158	regs_id = 0;
159	if ((command & PCIM_CMD_MEMEN) != 0
160	 && ((ahd->chip & AHD_BUS_MASK) != AHD_PCIX
161	  || (ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0)) {
162
163		regs_type = SYS_RES_MEMORY;
164		regs_id = AHD_PCI_MEMADDR;
165		regs = bus_alloc_resource(ahd->dev_softc, regs_type,
166					  &regs_id, 0, ~0, 1, RF_ACTIVE);
167		if (regs != NULL) {
168			int error;
169
170			ahd->tags[0] = rman_get_bustag(regs);
171			ahd->bshs[0] = rman_get_bushandle(regs);
172			ahd->tags[1] = ahd->tags[0];
173			error = bus_space_subregion(ahd->tags[0], ahd->bshs[0],
174						    /*offset*/0x100,
175						    /*size*/0x100,
176						    &ahd->bshs[1]);
177			/*
178			 * Do a quick test to see if memory mapped
179			 * I/O is functioning correctly.
180			 */
181			if (error != 0 || ahd_inb(ahd, HCNTRL) == 0xFF) {
182				device_printf(ahd->dev_softc,
183				       "PCI Device %d:%d:%d failed memory "
184				       "mapped test.  Using PIO.\n",
185				       ahd_get_pci_bus(ahd->dev_softc),
186				       ahd_get_pci_slot(ahd->dev_softc),
187				       ahd_get_pci_function(ahd->dev_softc));
188				bus_release_resource(ahd->dev_softc, regs_type,
189						     regs_id, regs);
190				regs = NULL;
191			} else {
192				command &= ~PCIM_CMD_PORTEN;
193				ahd_pci_write_config(ahd->dev_softc,
194						     PCIR_COMMAND,
195						     command, /*bytes*/1);
196			}
197		}
198	}
199	if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
200		regs_type = SYS_RES_IOPORT;
201		regs_id = AHD_PCI_IOADDR0;
202		regs = bus_alloc_resource(ahd->dev_softc, regs_type,
203					  &regs_id, 0, ~0, 1, RF_ACTIVE);
204		if (regs == NULL) {
205			device_printf(ahd->dev_softc,
206				      "can't allocate register resources\n");
207			return (ENOMEM);
208		}
209		ahd->tags[0] = rman_get_bustag(regs);
210		ahd->bshs[0] = rman_get_bushandle(regs);
211
212		/* And now the second BAR */
213		regs_id2 = AHD_PCI_IOADDR1;
214		regs2 = bus_alloc_resource(ahd->dev_softc, regs_type,
215					   &regs_id2, 0, ~0, 1, RF_ACTIVE);
216		if (regs2 == NULL) {
217			device_printf(ahd->dev_softc,
218				      "can't allocate register resources\n");
219			return (ENOMEM);
220		}
221		ahd->tags[1] = rman_get_bustag(regs2);
222		ahd->bshs[1] = rman_get_bushandle(regs2);
223		command &= ~PCIM_CMD_MEMEN;
224		ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
225				     command, /*bytes*/1);
226		ahd->platform_data->regs_res_type[1] = regs_type;
227		ahd->platform_data->regs_res_id[1] = regs_id2;
228		ahd->platform_data->regs[1] = regs2;
229	}
230	ahd->platform_data->regs_res_type[0] = regs_type;
231	ahd->platform_data->regs_res_id[0] = regs_id;
232	ahd->platform_data->regs[0] = regs;
233	return (0);
234}
235
236int
237ahd_pci_map_int(struct ahd_softc *ahd)
238{
239	int zero;
240
241	zero = 0;
242	ahd->platform_data->irq =
243	    bus_alloc_resource(ahd->dev_softc, SYS_RES_IRQ, &zero,
244			       0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
245	if (ahd->platform_data->irq == NULL)
246		return (ENOMEM);
247	ahd->platform_data->irq_res_type = SYS_RES_IRQ;
248	return (ahd_map_int(ahd));
249}
250
251void
252ahd_power_state_change(struct ahd_softc *ahd, ahd_power_state new_state)
253{
254	uint32_t cap;
255	u_int cap_offset;
256
257	/*
258	 * Traverse the capability list looking for
259	 * the power management capability.
260	 */
261	cap = 0;
262	cap_offset = ahd_pci_read_config(ahd->dev_softc,
263					 PCIR_CAP_PTR, /*bytes*/1);
264	while (cap_offset != 0) {
265
266		cap = ahd_pci_read_config(ahd->dev_softc,
267					  cap_offset, /*bytes*/4);
268		if ((cap & 0xFF) == 1
269		 && ((cap >> 16) & 0x3) > 0) {
270			uint32_t pm_control;
271
272			pm_control = ahd_pci_read_config(ahd->dev_softc,
273							 cap_offset + 4,
274							 /*bytes*/2);
275			pm_control &= ~0x3;
276			pm_control |= new_state;
277			ahd_pci_write_config(ahd->dev_softc,
278					     cap_offset + 4,
279					     pm_control, /*bytes*/2);
280			break;
281		}
282		cap_offset = (cap >> 8) & 0xFF;
283	}
284}
285