ahc_pci.c revision 55580
1/* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: head/sys/dev/aic7xxx/ahc_pci.c 55580 2000-01-07 22:53:37Z gibbs $ 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/bus.h> 45 46#include <pci/pcireg.h> 47#include <pci/pcivar.h> 48 49#include <machine/bus_memio.h> 50#include <machine/bus_pio.h> 51#include <machine/bus.h> 52#include <machine/resource.h> 53#include <machine/clock.h> 54#include <sys/rman.h> 55 56#include <cam/cam.h> 57#include <cam/cam_ccb.h> 58#include <cam/cam_sim.h> 59#include <cam/cam_xpt_sim.h> 60 61#include <cam/scsi/scsi_all.h> 62 63#include <dev/aic7xxx/aic7xxx.h> 64#include <dev/aic7xxx/93cx6.h> 65 66#include <aic7xxx_reg.h> 67 68#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 69#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 70 71static __inline u_int64_t 72ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 73{ 74 u_int64_t id; 75 76 id = subvendor 77 | (subdevice << 16) 78 | ((u_int64_t)vendor << 32) 79 | ((u_int64_t)device << 48); 80 81 return (id); 82} 83 84#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 85#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 86#define ID_AIC7850 0x5078900400000000ull 87#define ID_AHA_2910_15_20_30C 0x5078900478509004ull 88#define ID_AIC7855 0x5578900400000000ull 89#define ID_AIC7859 0x3860900400000000ull 90#define ID_AHA_2930CU 0x3860900438699004ull 91#define ID_AIC7860 0x6078900400000000ull 92#define ID_AIC7860C 0x6078900478609004ull 93#define ID_AHA_2940AU_0 0x6178900400000000ull 94#define ID_AHA_2940AU_1 0x6178900478619004ull 95#define ID_AHA_2940AU_CN 0x2178900478219004ull 96#define ID_AHA_2930C_VAR 0x6038900438689004ull 97 98#define ID_AIC7870 0x7078900400000000ull 99#define ID_AHA_2940 0x7178900400000000ull 100#define ID_AHA_3940 0x7278900400000000ull 101#define ID_AHA_398X 0x7378900400000000ull 102#define ID_AHA_2944 0x7478900400000000ull 103#define ID_AHA_3944 0x7578900400000000ull 104 105#define ID_AIC7880 0x8078900400000000ull 106#define ID_AIC7880_B 0x8078900478809004ull 107#define ID_AHA_2940U 0x8178900400000000ull 108#define ID_AHA_3940U 0x8278900400000000ull 109#define ID_AHA_2944U 0x8478900400000000ull 110#define ID_AHA_3944U 0x8578900400000000ull 111#define ID_AHA_398XU 0x8378900400000000ull 112#define ID_AHA_4944U 0x8678900400000000ull 113#define ID_AHA_2940UB 0x8178900478819004ull 114#define ID_AHA_2930U 0x8878900478889004ull 115#define ID_AHA_2940U_PRO 0x8778900478879004ull 116#define ID_AHA_2940U_CN 0x0078900478009004ull 117 118#define ID_AIC7895 0x7895900478959004ull 119#define ID_AIC7895_RAID_PORT 0x7893900478939004ull 120#define ID_AHA_2940U_DUAL 0x7895900478919004ull 121#define ID_AHA_3940AU 0x7895900478929004ull 122#define ID_AHA_3944AU 0x7895900478949004ull 123 124#define ID_AIC7890 0x001F9005000F9005ull 125#define ID_AHA_2930U2 0x0011900501819005ull 126#define ID_AHA_2940U2B 0x00109005A1009005ull 127#define ID_AHA_2940U2_OEM 0x0010900521809005ull 128#define ID_AHA_2940U2 0x00109005A1809005ull 129#define ID_AHA_2950U2B 0x00109005E1009005ull 130 131#define ID_AIC7892 0x008F9005FFFF9005ull 132#define ID_AHA_29160 0x00809005E2A09005ull 133#define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 134#define ID_AHA_29160N 0x0080900562A09005ull 135#define ID_AHA_29160B 0x00809005E2209005ull 136#define ID_AHA_19160B 0x0081900562A19005ull 137 138#define ID_AIC7896 0x005F9005FFFF9005ull 139#define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 140#define ID_AHA_3950U2B_1 0x00509005F5009005ull 141#define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 142#define ID_AHA_3950U2D_1 0x00519005B5009005ull 143 144#define ID_AIC7899 0x00CF9005FFFF9005ull 145#define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ 146#define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 147 148#define ID_AIC7810 0x1078900400000000ull 149#define ID_AIC7815 0x1578900400000000ull 150 151typedef int (ahc_device_setup_t)(device_t, char *, ahc_chip *, 152 ahc_feature *, ahc_flag *); 153 154static ahc_device_setup_t ahc_aic7850_setup; 155static ahc_device_setup_t ahc_aic7855_setup; 156static ahc_device_setup_t ahc_aic7859_setup; 157static ahc_device_setup_t ahc_aic7860_setup; 158static ahc_device_setup_t ahc_aic7870_setup; 159static ahc_device_setup_t ahc_aha394X_setup; 160static ahc_device_setup_t ahc_aha398X_setup; 161static ahc_device_setup_t ahc_aic7880_setup; 162static ahc_device_setup_t ahc_2940Pro_setup; 163static ahc_device_setup_t ahc_aha394XU_setup; 164static ahc_device_setup_t ahc_aha398XU_setup; 165static ahc_device_setup_t ahc_aic7890_setup; 166static ahc_device_setup_t ahc_aic7892_setup; 167static ahc_device_setup_t ahc_aic7895_setup; 168static ahc_device_setup_t ahc_aic7896_setup; 169static ahc_device_setup_t ahc_aic7899_setup; 170static ahc_device_setup_t ahc_raid_setup; 171static ahc_device_setup_t ahc_aha394XX_setup; 172static ahc_device_setup_t ahc_aha398XX_setup; 173 174struct ahc_pci_identity { 175 u_int64_t full_id; 176 u_int64_t id_mask; 177 char *name; 178 ahc_device_setup_t *setup; 179}; 180 181struct ahc_pci_identity ahc_pci_ident_table [] = 182{ 183 /* aic7850 based controllers */ 184 { 185 ID_AHA_2910_15_20_30C, 186 ID_ALL_MASK, 187 "Adaptec 2910/15/20/30C SCSI adapter", 188 ahc_aic7850_setup 189 }, 190 /* aic7859 based controllers */ 191 { 192 ID_AHA_2930CU, 193 ID_ALL_MASK, 194 "Adaptec 2930CU SCSI adapter", 195 ahc_aic7859_setup 196 }, 197 /* aic7860 based controllers */ 198 { 199 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 200 ID_DEV_VENDOR_MASK, 201 "Adaptec 2940A Ultra SCSI adapter", 202 ahc_aic7860_setup 203 }, 204 { 205 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 206 ID_DEV_VENDOR_MASK, 207 "Adaptec 2940A/CN Ultra SCSI adapter", 208 ahc_aic7860_setup 209 }, 210 { 211 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 212 ID_DEV_VENDOR_MASK, 213 "Adaptec 2930C SCSI adapter (VAR)", 214 ahc_aic7860_setup 215 }, 216 /* aic7870 based controllers */ 217 { 218 ID_AHA_2940, 219 ID_ALL_MASK, 220 "Adaptec 2940 SCSI adapter", 221 ahc_aic7870_setup 222 }, 223 { 224 ID_AHA_3940, 225 ID_ALL_MASK, 226 "Adaptec 3940 SCSI adapter", 227 ahc_aha394X_setup 228 }, 229 { 230 ID_AHA_398X, 231 ID_ALL_MASK, 232 "Adaptec 398X SCSI RAID adapter", 233 ahc_aha398X_setup 234 }, 235 { 236 ID_AHA_2944, 237 ID_ALL_MASK, 238 "Adaptec 2944 SCSI adapter", 239 ahc_aic7870_setup 240 }, 241 { 242 ID_AHA_3944, 243 ID_ALL_MASK, 244 "Adaptec 3944 SCSI adapter", 245 ahc_aha394X_setup 246 }, 247 /* aic7880 based controllers */ 248 { 249 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 250 ID_DEV_VENDOR_MASK, 251 "Adaptec 2940 Ultra SCSI adapter", 252 ahc_aic7880_setup 253 }, 254 { 255 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 256 ID_DEV_VENDOR_MASK, 257 "Adaptec 3940 Ultra SCSI adapter", 258 ahc_aha394XU_setup 259 }, 260 { 261 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 262 ID_DEV_VENDOR_MASK, 263 "Adaptec 2944 Ultra SCSI adapter", 264 ahc_aic7880_setup 265 }, 266 { 267 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 268 ID_DEV_VENDOR_MASK, 269 "Adaptec 3944 Ultra SCSI adapter", 270 ahc_aha394XU_setup 271 }, 272 { 273 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 274 ID_DEV_VENDOR_MASK, 275 "Adaptec 398X Ultra SCSI RAID adapter", 276 ahc_aha398XU_setup 277 }, 278 { 279 /* 280 * XXX Don't know the slot numbers 281 * so we can't identify channels 282 */ 283 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 284 ID_DEV_VENDOR_MASK, 285 "Adaptec 4944 Ultra SCSI adapter", 286 ahc_aic7880_setup 287 }, 288 { 289 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 290 ID_DEV_VENDOR_MASK, 291 "Adaptec 2930 Ultra SCSI adapter", 292 ahc_aic7880_setup 293 }, 294 { 295 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 296 ID_DEV_VENDOR_MASK, 297 "Adaptec 2940 Pro Ultra SCSI adapter", 298 ahc_2940Pro_setup 299 }, 300 { 301 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 302 ID_DEV_VENDOR_MASK, 303 "Adaptec 2940/CN Ultra SCSI adapter", 304 ahc_aic7880_setup 305 }, 306 /* aic7890 based controllers */ 307 { 308 ID_AHA_2930U2, 309 ID_ALL_MASK, 310 "Adaptec 2930 Ultra2 SCSI adapter", 311 ahc_aic7890_setup 312 }, 313 { 314 ID_AHA_2940U2B, 315 ID_ALL_MASK, 316 "Adaptec 2940B Ultra2 SCSI adapter", 317 ahc_aic7890_setup 318 }, 319 { 320 ID_AHA_2940U2_OEM, 321 ID_ALL_MASK, 322 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 323 ahc_aic7890_setup 324 }, 325 { 326 ID_AHA_2940U2, 327 ID_ALL_MASK, 328 "Adaptec 2940 Ultra2 SCSI adapter", 329 ahc_aic7890_setup 330 }, 331 { 332 ID_AHA_2950U2B, 333 ID_ALL_MASK, 334 "Adaptec 2950 Ultra2 SCSI adapter", 335 ahc_aic7890_setup 336 }, 337 /* aic7892 based controllers */ 338 { 339 ID_AHA_29160, 340 ID_ALL_MASK, 341 "Adaptec 29160 Ultra160 SCSI adapter", 342 ahc_aic7892_setup 343 }, 344 { 345 ID_AHA_29160_CPQ, 346 ID_ALL_MASK, 347 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 348 ahc_aic7892_setup 349 }, 350 { 351 ID_AHA_29160N, 352 ID_ALL_MASK, 353 "Adaptec 29160N Ultra160 SCSI adapter", 354 ahc_aic7892_setup 355 }, 356 { 357 ID_AHA_29160B, 358 ID_ALL_MASK, 359 "Adaptec 29160B Ultra160 SCSI adapter", 360 ahc_aic7892_setup 361 }, 362 { 363 ID_AHA_19160B, 364 ID_ALL_MASK, 365 "Adaptec 19160B Ultra160 SCSI adapter", 366 ahc_aic7892_setup 367 }, 368 /* aic7895 based controllers */ 369 { 370 ID_AHA_2940U_DUAL, 371 ID_ALL_MASK, 372 "Adaptec 2940/DUAL Ultra SCSI adapter", 373 ahc_aic7895_setup 374 }, 375 { 376 ID_AHA_3940AU, 377 ID_ALL_MASK, 378 "Adaptec 3940A Ultra SCSI adapter", 379 ahc_aic7895_setup 380 }, 381 { 382 ID_AHA_3944AU, 383 ID_ALL_MASK, 384 "Adaptec 3944A Ultra SCSI adapter", 385 ahc_aic7895_setup 386 }, 387 /* aic7896/97 based controllers */ 388 { 389 ID_AHA_3950U2B_0, 390 ID_ALL_MASK, 391 "Adaptec 3950B Ultra2 SCSI adapter", 392 ahc_aic7896_setup 393 }, 394 { 395 ID_AHA_3950U2B_1, 396 ID_ALL_MASK, 397 "Adaptec 3950B Ultra2 SCSI adapter", 398 ahc_aic7896_setup 399 }, 400 { 401 ID_AHA_3950U2D_0, 402 ID_ALL_MASK, 403 "Adaptec 3950D Ultra2 SCSI adapter", 404 ahc_aic7896_setup 405 }, 406 { 407 ID_AHA_3950U2D_1, 408 ID_ALL_MASK, 409 "Adaptec 3950D Ultra2 SCSI adapter", 410 ahc_aic7896_setup 411 }, 412 /* aic7899 based controllers */ 413 { 414 ID_AHA_3960D, 415 ID_ALL_MASK, 416 "Adaptec 3960D Ultra160 SCSI adapter", 417 ahc_aic7899_setup 418 }, 419 { 420 ID_AHA_3960D_CPQ, 421 ID_ALL_MASK, 422 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 423 ahc_aic7899_setup 424 }, 425 /* Generic chip probes for devices we don't know 'exactly' */ 426 { 427 ID_AIC7850 & ID_DEV_VENDOR_MASK, 428 ID_DEV_VENDOR_MASK, 429 "Adaptec aic7850 SCSI adapter", 430 ahc_aic7850_setup 431 }, 432 { 433 ID_AIC7855 & ID_DEV_VENDOR_MASK, 434 ID_DEV_VENDOR_MASK, 435 "Adaptec aic7855 SCSI adapter", 436 ahc_aic7855_setup 437 }, 438 { 439 ID_AIC7859 & ID_DEV_VENDOR_MASK, 440 ID_DEV_VENDOR_MASK, 441 "Adaptec aic7859 SCSI adapter", 442 ahc_aic7859_setup 443 }, 444 { 445 ID_AIC7860 & ID_DEV_VENDOR_MASK, 446 ID_DEV_VENDOR_MASK, 447 "Adaptec aic7860 SCSI adapter", 448 ahc_aic7860_setup 449 }, 450 { 451 ID_AIC7870 & ID_DEV_VENDOR_MASK, 452 ID_DEV_VENDOR_MASK, 453 "Adaptec aic7870 SCSI adapter", 454 ahc_aic7870_setup 455 }, 456 { 457 ID_AIC7880 & ID_DEV_VENDOR_MASK, 458 ID_DEV_VENDOR_MASK, 459 "Adaptec aic7880 Ultra SCSI adapter", 460 ahc_aic7880_setup 461 }, 462 { 463 ID_AIC7890 & ID_DEV_VENDOR_MASK, 464 ID_DEV_VENDOR_MASK, 465 "Adaptec aic7890/91 Ultra2 SCSI adapter", 466 ahc_aic7890_setup 467 }, 468 { 469 ID_AIC7892 & ID_DEV_VENDOR_MASK, 470 ID_DEV_VENDOR_MASK, 471 "Adaptec aic7892 Ultra160 SCSI adapter", 472 ahc_aic7892_setup 473 }, 474 { 475 ID_AIC7895 & ID_DEV_VENDOR_MASK, 476 ID_DEV_VENDOR_MASK, 477 "Adaptec aic7895 Ultra SCSI adapter", 478 ahc_aic7895_setup 479 }, 480 { 481 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 482 ID_DEV_VENDOR_MASK, 483 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 484 ahc_aic7895_setup 485 }, 486 { 487 ID_AIC7896 & ID_DEV_VENDOR_MASK, 488 ID_DEV_VENDOR_MASK, 489 "Adaptec aic7896/97 Ultra2 SCSI adapter", 490 ahc_aic7896_setup 491 }, 492 { 493 ID_AIC7899 & ID_DEV_VENDOR_MASK, 494 ID_DEV_VENDOR_MASK, 495 "Adaptec aic7899 Ultra160 SCSI adapter", 496 ahc_aic7899_setup 497 }, 498 { 499 ID_AIC7810 & ID_DEV_VENDOR_MASK, 500 ID_DEV_VENDOR_MASK, 501 "Adaptec aic7810 RAID memory controller", 502 ahc_raid_setup 503 }, 504 { 505 ID_AIC7815 & ID_DEV_VENDOR_MASK, 506 ID_DEV_VENDOR_MASK, 507 "Adaptec aic7815 RAID memory controller", 508 ahc_raid_setup 509 } 510}; 511 512static const int ahc_num_pci_devs = 513 sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); 514 515#define AHC_394X_SLOT_CHANNEL_A 4 516#define AHC_394X_SLOT_CHANNEL_B 5 517 518#define AHC_398X_SLOT_CHANNEL_A 4 519#define AHC_398X_SLOT_CHANNEL_B 8 520#define AHC_398X_SLOT_CHANNEL_C 12 521 522#define DEVCONFIG 0x40 523#define SCBSIZE32 0x00010000ul /* aic789X only */ 524#define MPORTMODE 0x00000400ul /* aic7870 only */ 525#define RAMPSM 0x00000200ul /* aic7870 only */ 526#define VOLSENSE 0x00000100ul 527#define SCBRAMSEL 0x00000080ul 528#define MRDCEN 0x00000040ul 529#define EXTSCBTIME 0x00000020ul /* aic7870 only */ 530#define EXTSCBPEN 0x00000010ul /* aic7870 only */ 531#define BERREN 0x00000008ul 532#define DACEN 0x00000004ul 533#define STPWLEVEL 0x00000002ul 534#define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 535 536#define CSIZE_LATTIME 0x0c 537#define CACHESIZE 0x0000003ful /* only 5 bits */ 538#define LATTIME 0x0000ff00ul 539 540static struct ahc_pci_identity *ahc_find_pci_device(device_t dev); 541static int ahc_ext_scbram_present(struct ahc_softc *ahc); 542static void ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, 543 int pcheck, int fast); 544static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 545static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 546static void configure_termination(struct ahc_softc *ahc, 547 struct seeprom_descriptor *sd, 548 u_int adapter_control, 549 u_int *sxfrctl1); 550 551static void ahc_new_term_detect(struct ahc_softc *ahc, 552 int *enableSEC_low, 553 int *enableSEC_high, 554 int *enablePRI_low, 555 int *enablePRI_high, 556 int *eeprom_present); 557static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 558 int *internal68_present, 559 int *externalcable_present, 560 int *eeprom_present); 561static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 562 int *externalcable_present, 563 int *eeprom_present); 564static int acquire_seeprom(struct ahc_softc *ahc, 565 struct seeprom_descriptor *sd); 566static void release_seeprom(struct seeprom_descriptor *sd); 567static void write_brdctl(struct ahc_softc *ahc, u_int8_t value); 568static u_int8_t read_brdctl(struct ahc_softc *ahc); 569 570static struct ahc_softc *first_398X; 571 572static int ahc_pci_probe(device_t dev); 573static int ahc_pci_attach(device_t dev); 574 575/* Exported for use in the ahc_intr routine */ 576void ahc_pci_intr(struct ahc_softc *ahc); 577 578static device_method_t ahc_pci_methods[] = { 579 /* Device interface */ 580 DEVMETHOD(device_probe, ahc_pci_probe), 581 DEVMETHOD(device_attach, ahc_pci_attach), 582 { 0, 0 } 583}; 584 585static driver_t ahc_pci_driver = { 586 "ahc", 587 ahc_pci_methods, 588 sizeof(struct ahc_softc) 589}; 590 591static devclass_t ahc_devclass; 592 593DRIVER_MODULE(ahc, pci, ahc_pci_driver, ahc_devclass, 0, 0); 594 595static struct ahc_pci_identity * 596ahc_find_pci_device(device_t dev) 597{ 598 u_int64_t full_id; 599 struct ahc_pci_identity *entry; 600 u_int i; 601 602 full_id = ahc_compose_id(pci_get_device(dev), 603 pci_get_vendor(dev), 604 pci_get_subdevice(dev), 605 pci_get_subvendor(dev)); 606 607 for (i = 0; i < ahc_num_pci_devs; i++) { 608 entry = &ahc_pci_ident_table[i]; 609 if (entry->full_id == (full_id & entry->id_mask)) 610 return (entry); 611 } 612 return (NULL); 613} 614 615static int 616ahc_pci_probe(device_t dev) 617{ 618 struct ahc_pci_identity *entry; 619 620 entry = ahc_find_pci_device(dev); 621 if (entry != NULL) { 622 device_set_desc(dev, entry->name); 623 return (0); 624 } 625 return (ENXIO); 626} 627 628static int 629ahc_pci_attach(device_t dev) 630{ 631 bus_dma_tag_t parent_dmat; 632 struct ahc_pci_identity *entry; 633 struct resource *regs; 634 struct ahc_softc *ahc; 635 u_int command; 636 struct scb_data *shared_scb_data; 637 ahc_chip ahc_t = AHC_NONE; 638 ahc_feature ahc_fe = AHC_FENONE; 639 ahc_flag ahc_f = AHC_FNONE; 640 int regs_type; 641 int regs_id; 642 u_int our_id = 0; 643 u_int sxfrctl1; 644 u_int scsiseq; 645 int error; 646 int zero; 647 char channel; 648 649 shared_scb_data = NULL; 650 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 651 entry = ahc_find_pci_device(dev); 652 if (entry == NULL) 653 return (ENXIO); 654 error = entry->setup(dev, &channel, &ahc_t, &ahc_fe, &ahc_f); 655 if (error != 0) 656 return (error); 657 658 regs = NULL; 659 regs_type = 0; 660 regs_id = 0; 661#ifdef AHC_ALLOW_MEMIO 662 if ((command & PCIM_CMD_MEMEN) != 0) { 663 regs_type = SYS_RES_MEMORY; 664 regs_id = AHC_PCI_MEMADDR; 665 regs = bus_alloc_resource(dev, regs_type, 666 ®s_id, 0, ~0, 1, RF_ACTIVE); 667 } 668#endif 669 if (regs == NULL && (command & PCI_COMMAND_IO_ENABLE) != 0) { 670 regs_type = SYS_RES_IOPORT; 671 regs_id = AHC_PCI_IOADDR; 672 regs = bus_alloc_resource(dev, regs_type, 673 ®s_id, 0, ~0, 1, RF_ACTIVE); 674 } 675 676 if (regs == NULL) { 677 device_printf(dev, "can't allocate register resources\n"); 678 return (ENOMEM); 679 } 680 681 /* Ensure busmastering is enabled */ 682 command |= PCIM_CMD_BUSMASTEREN; 683 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 684 685 /* Allocate a dmatag for our SCB DMA maps */ 686 /* XXX Should be a child of the PCI bus dma tag */ 687 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, 688 /*boundary*/0, 689 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 690 /*highaddr*/BUS_SPACE_MAXADDR, 691 /*filter*/NULL, /*filterarg*/NULL, 692 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, 693 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 694 /*flags*/BUS_DMA_ALLOCNOW, &parent_dmat); 695 696 if (error != 0) { 697 printf("ahc_pci_attach: Could not allocate DMA tag " 698 "- error %d\n", error); 699 return (ENOMEM); 700 } 701 702 /* On all PCI adapters, we allow SCB paging */ 703 ahc_f |= AHC_PAGESCBS; 704 if ((ahc = ahc_alloc(dev, regs, regs_type, regs_id, parent_dmat, 705 ahc_t|AHC_PCI, ahc_fe, ahc_f, 706 shared_scb_data)) == NULL) 707 return (ENOMEM); 708 709 ahc->channel = channel; 710 711 /* Store our PCI bus information for use in our PCI error handler */ 712 ahc->device = dev; 713 714 /* Remeber how the card was setup in case there is no SEEPROM */ 715 ahc_outb(ahc, HCNTRL, ahc->pause); 716 if ((ahc->features & AHC_ULTRA2) != 0) 717 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 718 else 719 our_id = ahc_inb(ahc, SCSIID) & OID; 720 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 721 scsiseq = ahc_inb(ahc, SCSISEQ); 722 723 if (ahc_reset(ahc) != 0) { 724 /* Failed */ 725 ahc_free(ahc); 726 return (ENXIO); 727 } 728 729 /* 730 * Take a look to see if we have external SRAM. 731 * We currently do not attempt to use SRAM that is 732 * shared among multiple controllers. 733 */ 734 ahc_probe_ext_scbram(ahc); 735 736 if ((ahc->features & AHC_DT) != 0) { 737 u_int optionmode; 738 u_int sfunct; 739 740 /* Perform ALT-Mode Setup */ 741 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 742 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 743 optionmode = ahc_inb(ahc, OPTIONMODE); 744 printf("OptionMode = %x\n", optionmode); 745 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 746 /* Send CRC info in target mode every 4K */ 747 ahc_outb(ahc, TARGCRCCNT, 0); 748 ahc_outb(ahc, TARGCRCCNT + 1, 0x10); 749 ahc_outb(ahc, SFUNCT, sfunct); 750 751 /* Normal mode setup */ 752 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 753 |TARGCRCENDEN|TARGCRCCNTEN); 754 } 755 zero = 0; 756 ahc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 757 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 758 if (ahc->irq == NULL) { 759 ahc_free(ahc); 760 return (ENOMEM); 761 } 762 763 ahc->irq_res_type = SYS_RES_IRQ; 764 765 /* 766 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 767 */ 768 { 769 u_int8_t sblkctl; 770 771 if ((ahc->features & AHC_ULTRA2) != 0) { 772 u_int dscommand0; 773 774 /* 775 * DPARCKEN doesn't work correctly on 776 * some MBs so don't use it. 777 */ 778 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 779 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 780 dscommand0 |= CACHETHEN|MPARCKEN; 781 ahc_outb(ahc, DSCOMMAND0, dscommand0); 782 } 783 784 /* See if we have an SEEPROM and perform auto-term */ 785 check_extport(ahc, &sxfrctl1); 786 787 /* 788 * Take the LED out of diagnostic mode 789 */ 790 sblkctl = ahc_inb(ahc, SBLKCTL); 791 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 792 793 /* 794 * I don't know where this is set in the SEEPROM or by the 795 * BIOS, so we default to 100% on Ultra or slower controllers 796 * and 75% on ULTRA2 controllers. 797 */ 798 if ((ahc->features & AHC_ULTRA2) != 0) { 799 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 800 } else { 801 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 802 } 803 804 if (ahc->flags & AHC_USEDEFAULTS) { 805 /* 806 * PCI Adapter default setup 807 * Should only be used if the adapter does not have 808 * an SEEPROM. 809 */ 810 /* See if someone else set us up already */ 811 if (scsiseq != 0) { 812 printf("%s: Using left over BIOS settings\n", 813 ahc_name(ahc)); 814 ahc->flags &= ~AHC_USEDEFAULTS; 815 } else { 816 /* 817 * Assume only one connector and always turn 818 * on termination. 819 */ 820 our_id = 0x07; 821 sxfrctl1 = STPWEN; 822 } 823 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 824 825 ahc->our_id = our_id; 826 } 827 828 printf("%s: %s ", ahc_name(ahc), 829 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 830 } 831 832 /* 833 * Record our termination setting for the 834 * generic initialization routine. 835 */ 836 if ((sxfrctl1 & STPWEN) != 0) 837 ahc->flags |= AHC_TERM_ENB_A; 838 839 if (ahc_init(ahc)) { 840 ahc_free(ahc); 841 return (ENOMEM); 842 } 843 844 /* XXX Crude hack - fix sometime */ 845 if (ahc->flags & AHC_SHARED_SRAM) { 846 /* Only set this once we've successfully probed */ 847 if (shared_scb_data == NULL) 848 first_398X = ahc; 849 } 850 851 ahc_attach(ahc); 852 return (0); 853} 854 855/* 856 * Test for the presense of external sram in an 857 * "unshared" configuration. 858 */ 859static int 860ahc_ext_scbram_present(struct ahc_softc *ahc) 861{ 862 int ramps; 863 int single_user; 864 u_int32_t devconfig; 865 866 devconfig = pci_read_config(ahc->device, DEVCONFIG, /*bytes*/4); 867 single_user = (devconfig & MPORTMODE) != 0; 868 869 if ((ahc->features & AHC_ULTRA2) != 0) 870 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 871 else 872 ramps = (devconfig & RAMPSM) != 0; 873 874 if (ramps && single_user) 875 return (1); 876 return (0); 877} 878 879/* 880 * Enable external scbram. 881 */ 882static void 883ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, int fast) 884{ 885 u_int32_t devconfig; 886 887 if (ahc->features & AHC_MULTI_FUNC) { 888 /* 889 * Set the SCB Base addr (highest address bit) 890 * depending on which channel we are. 891 */ 892 ahc_outb(ahc, SCBBADDR, pci_get_function(ahc->device)); 893 } 894 895 devconfig = pci_read_config(ahc->device, DEVCONFIG, /*bytes*/4); 896 if ((ahc->features & AHC_ULTRA2) != 0) { 897 u_int dscommand0; 898 899 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 900 if (enable) 901 dscommand0 |= INTSCBRAMSEL; 902 else 903 dscommand0 &= ~INTSCBRAMSEL; 904 ahc_outb(ahc, DSCOMMAND0, dscommand0); 905 } else { 906 if (fast) 907 devconfig &= ~EXTSCBTIME; 908 else 909 devconfig |= EXTSCBTIME; 910 if (enable) 911 devconfig &= ~SCBRAMSEL; 912 else 913 devconfig |= SCBRAMSEL; 914 } 915 if (pcheck) 916 devconfig |= EXTSCBPEN; 917 else 918 devconfig &= ~EXTSCBPEN; 919 920 pci_write_config(ahc->device, DEVCONFIG, devconfig, /*bytes*/4); 921} 922 923/* 924 * Take a look to see if we have external SRAM. 925 * We currently do not attempt to use SRAM that is 926 * shared among multiple controllers. 927 */ 928static void 929ahc_probe_ext_scbram(struct ahc_softc *ahc) 930{ 931 int num_scbs; 932 int test_num_scbs; 933 int enable; 934 int pcheck; 935 int fast; 936 937 if (ahc_ext_scbram_present(ahc) == 0) 938 return; 939 940 /* 941 * Probe for the best parameters to use. 942 */ 943 enable = FALSE; 944 pcheck = FALSE; 945 fast = FALSE; 946 ahc_ext_scbram_config(ahc, /*enable*/TRUE, pcheck, fast); 947 num_scbs = ahc_probe_scbs(ahc); 948 if (num_scbs == 0) { 949 /* The SRAM wasn't really present. */ 950 goto done; 951 } 952 enable = TRUE; 953 954 /* Now see if we can do parity */ 955 ahc_ext_scbram_config(ahc, enable, /*pcheck*/TRUE, fast); 956 num_scbs = ahc_probe_scbs(ahc); 957 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 958 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 959 pcheck = TRUE; 960 961 /* Now see if we can do fast timing */ 962 ahc_ext_scbram_config(ahc, enable, pcheck, /*fast*/TRUE); 963 test_num_scbs = ahc_probe_scbs(ahc); 964 if (test_num_scbs == num_scbs 965 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 966 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 967 fast = TRUE; 968done: 969 if (bootverbose && enable) { 970 printf("%s: External SRAM, %dns access%s\n", 971 ahc_name(ahc), fast ? 10 : 20, 972 pcheck ? ", parity checking enabled" : ""); 973 974 } 975 ahc_ext_scbram_config(ahc, enable, pcheck, fast); 976} 977 978/* 979 * Check the external port logic for a serial eeprom 980 * and termination/cable detection contrls. 981 */ 982static void 983check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 984{ 985 struct seeprom_descriptor sd; 986 struct seeprom_config sc; 987 u_int scsi_conf; 988 u_int adapter_control; 989 int have_seeprom; 990 int have_autoterm; 991 992 sd.sd_tag = ahc->tag; 993 sd.sd_bsh = ahc->bsh; 994 sd.sd_control_offset = SEECTL; 995 sd.sd_status_offset = SEECTL; 996 sd.sd_dataout_offset = SEECTL; 997 998 /* 999 * For some multi-channel devices, the c46 is simply too 1000 * small to work. For the other controller types, we can 1001 * get our information from either SEEPROM type. Set the 1002 * type to start our probe with accordingly. 1003 */ 1004 if (ahc->flags & AHC_LARGE_SEEPROM) 1005 sd.sd_chip = C56_66; 1006 else 1007 sd.sd_chip = C46; 1008 1009 sd.sd_MS = SEEMS; 1010 sd.sd_RDY = SEERDY; 1011 sd.sd_CS = SEECS; 1012 sd.sd_CK = SEECK; 1013 sd.sd_DO = SEEDO; 1014 sd.sd_DI = SEEDI; 1015 1016 have_seeprom = acquire_seeprom(ahc, &sd); 1017 if (have_seeprom) { 1018 1019 if (bootverbose) 1020 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1021 1022 for (;;) { 1023 bus_size_t start_addr; 1024 1025 start_addr = 32 * (ahc->channel - 'A'); 1026 1027 have_seeprom = read_seeprom(&sd, (u_int16_t *)&sc, 1028 start_addr, sizeof(sc)/2); 1029 1030 if (have_seeprom) { 1031 /* Check checksum */ 1032 int i; 1033 int maxaddr; 1034 u_int32_t checksum; 1035 u_int16_t *scarray; 1036 1037 maxaddr = (sizeof(sc)/2) - 1; 1038 checksum = 0; 1039 scarray = (u_int16_t *)≻ 1040 1041 for (i = 0; i < maxaddr; i++) 1042 checksum = checksum + scarray[i]; 1043 if (checksum == 0 1044 || (checksum & 0xFFFF) != sc.checksum) { 1045 if (bootverbose && sd.sd_chip == C56_66) 1046 printf ("checksum error\n"); 1047 have_seeprom = 0; 1048 } else { 1049 if (bootverbose) 1050 printf("done.\n"); 1051 break; 1052 } 1053 } 1054 1055 if (sd.sd_chip == C56_66) 1056 break; 1057 sd.sd_chip = C56_66; 1058 } 1059 } 1060 1061 if (!have_seeprom) { 1062 if (bootverbose) 1063 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1064 ahc->flags |= AHC_USEDEFAULTS; 1065 } else { 1066 /* 1067 * Put the data we've collected down into SRAM 1068 * where ahc_init will find it. 1069 */ 1070 int i; 1071 int max_targ = sc.max_targets & CFMAXTARG; 1072 u_int16_t discenable; 1073 u_int16_t ultraenb; 1074 1075 discenable = 0; 1076 ultraenb = 0; 1077 if ((sc.adapter_control & CFULTRAEN) != 0) { 1078 /* 1079 * Determine if this adapter has a "newstyle" 1080 * SEEPROM format. 1081 */ 1082 for (i = 0; i < max_targ; i++) { 1083 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 1084 ahc->flags |= AHC_NEWEEPROM_FMT; 1085 break; 1086 } 1087 } 1088 } 1089 1090 for (i = 0; i < max_targ; i++) { 1091 u_int scsirate; 1092 u_int16_t target_mask; 1093 1094 target_mask = 0x01 << i; 1095 if (sc.device_flags[i] & CFDISC) 1096 discenable |= target_mask; 1097 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1098 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1099 ultraenb |= target_mask; 1100 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1101 ultraenb |= target_mask; 1102 } 1103 if ((sc.device_flags[i] & CFXFER) == 0x04 1104 && (ultraenb & target_mask) != 0) { 1105 /* Treat 10MHz as a non-ultra speed */ 1106 sc.device_flags[i] &= ~CFXFER; 1107 ultraenb &= ~target_mask; 1108 } 1109 if ((ahc->features & AHC_ULTRA2) != 0) { 1110 u_int offset; 1111 1112 if (sc.device_flags[i] & CFSYNCH) 1113 offset = MAX_OFFSET_ULTRA2; 1114 else 1115 offset = 0; 1116 ahc_outb(ahc, TARG_OFFSET + i, offset); 1117 1118 scsirate = (sc.device_flags[i] & CFXFER) 1119 | ((ultraenb & target_mask) 1120 ? 0x8 : 0x0); 1121 if (sc.device_flags[i] & CFWIDEB) 1122 scsirate |= WIDEXFER; 1123 } else { 1124 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1125 if (sc.device_flags[i] & CFSYNCH) 1126 scsirate |= SOFS; 1127 if (sc.device_flags[i] & CFWIDEB) 1128 scsirate |= WIDEXFER; 1129 } 1130 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1131 } 1132 ahc->our_id = sc.brtime_id & CFSCSIID; 1133 1134 scsi_conf = (ahc->our_id & 0x7); 1135 if (sc.adapter_control & CFSPARITY) 1136 scsi_conf |= ENSPCHK; 1137 if (sc.adapter_control & CFRESETB) 1138 scsi_conf |= RESET_SCSI; 1139 1140 if (sc.bios_control & CFEXTEND) 1141 ahc->flags |= AHC_EXTENDED_TRANS_A; 1142 if (ahc->features & AHC_ULTRA 1143 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1144 /* Should we enable Ultra mode? */ 1145 if (!(sc.adapter_control & CFULTRAEN)) 1146 /* Treat us as a non-ultra card */ 1147 ultraenb = 0; 1148 } 1149 /* Set SCSICONF info */ 1150 ahc_outb(ahc, SCSICONF, scsi_conf); 1151 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1152 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1153 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1154 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1155 } 1156 1157 /* 1158 * Cards that have the external logic necessary to talk to 1159 * a SEEPROM, are almost certain to have the remaining logic 1160 * necessary for auto-termination control. This assumption 1161 * hasn't failed yet... 1162 */ 1163 have_autoterm = have_seeprom; 1164 if (have_seeprom) 1165 adapter_control = sc.adapter_control; 1166 else 1167 adapter_control = CFAUTOTERM; 1168 1169 /* 1170 * Some low-cost chips have SEEPROM and auto-term control built 1171 * in, instead of using a GAL. They can tell us directly 1172 * if the termination logic is enabled. 1173 */ 1174 if ((ahc->features & AHC_SPIOCAP) != 0) { 1175 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1176 have_autoterm = TRUE; 1177 else 1178 have_autoterm = FALSE; 1179 } 1180 1181 if (have_autoterm) 1182 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1183 1184 release_seeprom(&sd); 1185} 1186 1187static void 1188configure_termination(struct ahc_softc *ahc, 1189 struct seeprom_descriptor *sd, 1190 u_int adapter_control, 1191 u_int *sxfrctl1) 1192{ 1193 u_int8_t brddat; 1194 1195 brddat = 0; 1196 1197 /* 1198 * Update the settings in sxfrctl1 to match the 1199 * termination settings 1200 */ 1201 *sxfrctl1 = 0; 1202 1203 /* 1204 * SEECS must be on for the GALS to latch 1205 * the data properly. Be sure to leave MS 1206 * on or we will release the seeprom. 1207 */ 1208 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1209 if ((adapter_control & CFAUTOTERM) != 0 1210 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1211 int internal50_present; 1212 int internal68_present; 1213 int externalcable_present; 1214 int eeprom_present; 1215 int enableSEC_low; 1216 int enableSEC_high; 1217 int enablePRI_low; 1218 int enablePRI_high; 1219 1220 enableSEC_low = 0; 1221 enableSEC_high = 0; 1222 enablePRI_low = 0; 1223 enablePRI_high = 0; 1224 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1225 ahc_new_term_detect(ahc, &enableSEC_low, 1226 &enableSEC_high, 1227 &enablePRI_low, 1228 &enablePRI_high, 1229 &eeprom_present); 1230 if ((adapter_control & CFSEAUTOTERM) == 0) { 1231 if (bootverbose) 1232 printf("%s: Manual SE Termination\n", 1233 ahc_name(ahc)); 1234 enableSEC_low = (adapter_control & CFSTERM); 1235 enableSEC_high = (adapter_control & CFWSTERM); 1236 } 1237 if ((adapter_control & CFAUTOTERM) == 0) { 1238 if (bootverbose) 1239 printf("%s: Manual LVD Termination\n", 1240 ahc_name(ahc)); 1241 enablePRI_low = enablePRI_high = 1242 (adapter_control & CFLVDSTERM); 1243 } 1244 /* Make the table calculations below happy */ 1245 internal50_present = 0; 1246 internal68_present = 1; 1247 externalcable_present = 1; 1248 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1249 aic785X_cable_detect(ahc, &internal50_present, 1250 &externalcable_present, 1251 &eeprom_present); 1252 } else { 1253 aic787X_cable_detect(ahc, &internal50_present, 1254 &internal68_present, 1255 &externalcable_present, 1256 &eeprom_present); 1257 } 1258 1259 if ((ahc->features & AHC_WIDE) == 0) 1260 internal68_present = 0; 1261 1262 if (bootverbose) { 1263 if ((ahc->features & AHC_ULTRA2) == 0) { 1264 printf("%s: internal 50 cable %s present, " 1265 "internal 68 cable %s present\n", 1266 ahc_name(ahc), 1267 internal50_present ? "is":"not", 1268 internal68_present ? "is":"not"); 1269 1270 printf("%s: external cable %s present\n", 1271 ahc_name(ahc), 1272 externalcable_present ? "is":"not"); 1273 } 1274 printf("%s: BIOS eeprom %s present\n", 1275 ahc_name(ahc), eeprom_present ? "is" : "not"); 1276 } 1277 1278 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1279 /* 1280 * The 50 pin connector is a separate bus, 1281 * so force it to always be terminated. 1282 * In the future, perform current sensing 1283 * to determine if we are in the middle of 1284 * a properly terminated bus. 1285 */ 1286 internal50_present = 0; 1287 } 1288 1289 /* 1290 * Now set the termination based on what 1291 * we found. 1292 * Flash Enable = BRDDAT7 1293 * Secondary High Term Enable = BRDDAT6 1294 * Secondary Low Term Enable = BRDDAT5 (7890) 1295 * Primary High Term Enable = BRDDAT4 (7890) 1296 */ 1297 if ((ahc->features & AHC_ULTRA2) == 0 1298 && (internal50_present != 0) 1299 && (internal68_present != 0) 1300 && (externalcable_present != 0)) { 1301 printf("%s: Illegal cable configuration!!. " 1302 "Only two connectors on the " 1303 "adapter may be used at a " 1304 "time!\n", ahc_name(ahc)); 1305 } 1306 1307 if ((ahc->features & AHC_WIDE) != 0 1308 && ((externalcable_present == 0) 1309 || (internal68_present == 0) 1310 || (enableSEC_high != 0))) { 1311 brddat |= BRDDAT6; 1312 if (bootverbose) { 1313 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1314 printf("%s: 68 pin termination " 1315 "Enabled\n", ahc_name(ahc)); 1316 else 1317 printf("%s: %sHigh byte termination " 1318 "Enabled\n", ahc_name(ahc), 1319 enableSEC_high ? "Secondary " 1320 : ""); 1321 } 1322 } 1323 1324 if (((internal50_present ? 1 : 0) 1325 + (internal68_present ? 1 : 0) 1326 + (externalcable_present ? 1 : 0)) <= 1 1327 || (enableSEC_low != 0)) { 1328 if ((ahc->features & AHC_ULTRA2) != 0) 1329 brddat |= BRDDAT5; 1330 else 1331 *sxfrctl1 |= STPWEN; 1332 if (bootverbose) { 1333 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1334 printf("%s: 50 pin termination " 1335 "Enabled\n", ahc_name(ahc)); 1336 else 1337 printf("%s: %sLow byte termination " 1338 "Enabled\n", ahc_name(ahc), 1339 enableSEC_low ? "Secondary " 1340 : ""); 1341 } 1342 } 1343 1344 if (enablePRI_low != 0) { 1345 *sxfrctl1 |= STPWEN; 1346 if (bootverbose) 1347 printf("%s: Primary Low Byte termination " 1348 "Enabled\n", ahc_name(ahc)); 1349 } 1350 1351 /* 1352 * Setup STPWEN before setting up the rest of 1353 * the termination per the tech note on the U160 cards. 1354 */ 1355 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1356 1357 if (enablePRI_high != 0) { 1358 brddat |= BRDDAT4; 1359 if (bootverbose) 1360 printf("%s: Primary High Byte " 1361 "termination Enabled\n", 1362 ahc_name(ahc)); 1363 } 1364 1365 write_brdctl(ahc, brddat); 1366 1367 } else { 1368 if ((adapter_control & CFSTERM) != 0) { 1369 *sxfrctl1 |= STPWEN; 1370 1371 if (bootverbose) 1372 printf("%s: %sLow byte termination Enabled\n", 1373 ahc_name(ahc), 1374 (ahc->features & AHC_ULTRA2) ? "Primary " 1375 : ""); 1376 } 1377 1378 if ((adapter_control & CFWSTERM) != 0) { 1379 brddat |= BRDDAT6; 1380 if (bootverbose) 1381 printf("%s: %sHigh byte termination Enabled\n", 1382 ahc_name(ahc), 1383 (ahc->features & AHC_ULTRA2) 1384 ? "Secondary " : ""); 1385 } 1386 1387 /* 1388 * Setup STPWEN before setting up the rest of 1389 * the termination per the tech note on the U160 cards. 1390 */ 1391 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1392 1393 write_brdctl(ahc, brddat); 1394 } 1395 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1396} 1397 1398static void 1399ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1400 int *enableSEC_high, int *enablePRI_low, 1401 int *enablePRI_high, int *eeprom_present) 1402{ 1403 u_int8_t brdctl; 1404 1405 /* 1406 * BRDDAT7 = Eeprom 1407 * BRDDAT6 = Enable Secondary High Byte termination 1408 * BRDDAT5 = Enable Secondary Low Byte termination 1409 * BRDDAT4 = Enable Primary high byte termination 1410 * BRDDAT3 = Enable Primary low byte termination 1411 */ 1412 brdctl = read_brdctl(ahc); 1413 *eeprom_present = brdctl & BRDDAT7; 1414 *enableSEC_high = (brdctl & BRDDAT6); 1415 *enableSEC_low = (brdctl & BRDDAT5); 1416 *enablePRI_high = (brdctl & BRDDAT4); 1417 *enablePRI_low = (brdctl & BRDDAT3); 1418} 1419 1420static void 1421aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1422 int *internal68_present, int *externalcable_present, 1423 int *eeprom_present) 1424{ 1425 u_int8_t brdctl; 1426 1427 /* 1428 * First read the status of our cables. 1429 * Set the rom bank to 0 since the 1430 * bank setting serves as a multiplexor 1431 * for the cable detection logic. 1432 * BRDDAT5 controls the bank switch. 1433 */ 1434 write_brdctl(ahc, 0); 1435 1436 /* 1437 * Now read the state of the internal 1438 * connectors. BRDDAT6 is INT50 and 1439 * BRDDAT7 is INT68. 1440 */ 1441 brdctl = read_brdctl(ahc); 1442 *internal50_present = !(brdctl & BRDDAT6); 1443 *internal68_present = !(brdctl & BRDDAT7); 1444 1445 /* 1446 * Set the rom bank to 1 and determine 1447 * the other signals. 1448 */ 1449 write_brdctl(ahc, BRDDAT5); 1450 1451 /* 1452 * Now read the state of the external 1453 * connectors. BRDDAT6 is EXT68 and 1454 * BRDDAT7 is EPROMPS. 1455 */ 1456 brdctl = read_brdctl(ahc); 1457 *externalcable_present = !(brdctl & BRDDAT6); 1458 *eeprom_present = brdctl & BRDDAT7; 1459} 1460 1461static void 1462aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1463 int *externalcable_present, int *eeprom_present) 1464{ 1465 u_int8_t brdctl; 1466 1467 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1468 ahc_outb(ahc, BRDCTL, 0); 1469 brdctl = ahc_inb(ahc, BRDCTL); 1470 *internal50_present = !(brdctl & BRDDAT5); 1471 *externalcable_present = !(brdctl & BRDDAT6); 1472 1473 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 1474} 1475 1476static int 1477acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1478{ 1479 int wait; 1480 1481 if ((ahc->features & AHC_SPIOCAP) != 0 1482 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1483 return (0); 1484 1485 /* 1486 * Request access of the memory port. When access is 1487 * granted, SEERDY will go high. We use a 1 second 1488 * timeout which should be near 1 second more than 1489 * is needed. Reason: after the chip reset, there 1490 * should be no contention. 1491 */ 1492 SEEPROM_OUTB(sd, sd->sd_MS); 1493 wait = 1000; /* 1 second timeout in msec */ 1494 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1495 DELAY(1000); /* delay 1 msec */ 1496 } 1497 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1498 SEEPROM_OUTB(sd, 0); 1499 return (0); 1500 } 1501 return(1); 1502} 1503 1504static void 1505release_seeprom(sd) 1506 struct seeprom_descriptor *sd; 1507{ 1508 /* Release access to the memory port and the serial EEPROM. */ 1509 SEEPROM_OUTB(sd, 0); 1510} 1511 1512static void 1513write_brdctl(ahc, value) 1514 struct ahc_softc *ahc; 1515 u_int8_t value; 1516{ 1517 u_int8_t brdctl; 1518 1519 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1520 brdctl = BRDSTB; 1521 if (ahc->channel == 'B') 1522 brdctl |= BRDCS; 1523 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1524 brdctl = 0; 1525 } else { 1526 brdctl = BRDSTB|BRDCS; 1527 } 1528 ahc_outb(ahc, BRDCTL, brdctl); 1529 DELAY(20); 1530 brdctl |= value; 1531 ahc_outb(ahc, BRDCTL, brdctl); 1532 DELAY(20); 1533 if ((ahc->features & AHC_ULTRA2) != 0) 1534 brdctl |= BRDSTB_ULTRA2; 1535 else 1536 brdctl &= ~BRDSTB; 1537 ahc_outb(ahc, BRDCTL, brdctl); 1538 DELAY(20); 1539 if ((ahc->features & AHC_ULTRA2) != 0) 1540 brdctl = 0; 1541 else 1542 brdctl &= ~BRDCS; 1543 ahc_outb(ahc, BRDCTL, brdctl); 1544} 1545 1546static u_int8_t 1547read_brdctl(ahc) 1548 struct ahc_softc *ahc; 1549{ 1550 u_int8_t brdctl; 1551 u_int8_t value; 1552 1553 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1554 brdctl = BRDRW; 1555 if (ahc->channel == 'B') 1556 brdctl |= BRDCS; 1557 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1558 brdctl = BRDRW_ULTRA2; 1559 } else { 1560 brdctl = BRDRW|BRDCS; 1561 } 1562 ahc_outb(ahc, BRDCTL, brdctl); 1563 DELAY(20); 1564 value = ahc_inb(ahc, BRDCTL); 1565 ahc_outb(ahc, BRDCTL, 0); 1566 return (value); 1567} 1568 1569#define DPE 0x80 1570#define SSE 0x40 1571#define RMA 0x20 1572#define RTA 0x10 1573#define STA 0x08 1574#define DPR 0x01 1575 1576void 1577ahc_pci_intr(struct ahc_softc *ahc) 1578{ 1579 u_int8_t status1; 1580 1581 status1 = pci_read_config(ahc->device, PCIR_STATUS + 1, /*bytes*/1); 1582 1583 if (status1 & DPE) { 1584 printf("%s: Data Parity Error Detected during address " 1585 "or write data phase\n", ahc_name(ahc)); 1586 } 1587 if (status1 & SSE) { 1588 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1589 } 1590 if (status1 & RMA) { 1591 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1592 } 1593 if (status1 & RTA) { 1594 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1595 } 1596 if (status1 & STA) { 1597 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1598 } 1599 if (status1 & DPR) { 1600 printf("%s: Data Parity Error has been reported via PERR#\n", 1601 ahc_name(ahc)); 1602 } 1603 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1604 printf("%s: Latched PCIERR interrupt with " 1605 "no status bits set\n", ahc_name(ahc)); 1606 } 1607 pci_write_config(ahc->device, PCIR_STATUS + 1, status1, /*bytes*/1); 1608 1609 if (status1 & (DPR|RMA|RTA)) { 1610 ahc_outb(ahc, CLRINT, CLRPARERR); 1611 } 1612} 1613 1614static int 1615ahc_aic7850_setup(device_t dev, char *channel, ahc_chip *chip, 1616 ahc_feature *features, ahc_flag *flags) 1617{ 1618 *channel = 'A'; 1619 *chip = AHC_AIC7850; 1620 *features = AHC_AIC7850_FE; 1621 return (0); 1622} 1623 1624static int 1625ahc_aic7855_setup(device_t dev, char *channel, ahc_chip *chip, 1626 ahc_feature *features, ahc_flag *flags) 1627{ 1628 *channel = 'A'; 1629 *chip = AHC_AIC7855; 1630 *features = AHC_AIC7855_FE; 1631 return (0); 1632} 1633 1634static int 1635ahc_aic7859_setup(device_t dev, char *channel, ahc_chip *chip, 1636 ahc_feature *features, ahc_flag *flags) 1637{ 1638 *channel = 'A'; 1639 *chip = AHC_AIC7859; 1640 *features = AHC_AIC7859_FE; 1641 return (0); 1642} 1643 1644static int 1645ahc_aic7860_setup(device_t dev, char *channel, ahc_chip *chip, 1646 ahc_feature *features, ahc_flag *flags) 1647{ 1648 *channel = 'A'; 1649 *chip = AHC_AIC7860; 1650 *features = AHC_AIC7860_FE; 1651 return (0); 1652} 1653 1654static int 1655ahc_aic7870_setup(device_t dev, char *channel, ahc_chip *chip, 1656 ahc_feature *features, ahc_flag *flags) 1657{ 1658 *channel = 'A'; 1659 *chip = AHC_AIC7870; 1660 *features = AHC_AIC7870_FE; 1661 return (0); 1662} 1663 1664static int 1665ahc_aha394X_setup(device_t dev, char *channel, ahc_chip *chip, 1666 ahc_feature *features, ahc_flag *flags) 1667{ 1668 int error; 1669 1670 error = ahc_aic7870_setup(dev, channel, chip, features, flags); 1671 if (error == 0) 1672 error = ahc_aha394XX_setup(dev, channel, chip, features, flags); 1673 return (error); 1674} 1675 1676static int 1677ahc_aha398X_setup(device_t dev, char *channel, ahc_chip *chip, 1678 ahc_feature *features, ahc_flag *flags) 1679{ 1680 int error; 1681 1682 error = ahc_aic7870_setup(dev, channel, chip, features, flags); 1683 if (error == 0) 1684 error = ahc_aha398XX_setup(dev, channel, chip, features, flags); 1685 return (error); 1686} 1687 1688static int 1689ahc_aic7880_setup(device_t dev, char *channel, ahc_chip *chip, 1690 ahc_feature *features, ahc_flag *flags) 1691{ 1692 *channel = 'A'; 1693 *chip = AHC_AIC7880; 1694 *features = AHC_AIC7880_FE; 1695 return (0); 1696} 1697 1698static int 1699ahc_2940Pro_setup(device_t dev, char *channel, ahc_chip *chip, 1700 ahc_feature *features, ahc_flag *flags) 1701{ 1702 int error; 1703 1704 *flags |= AHC_INT50_SPEEDFLEX; 1705 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1706 return (0); 1707} 1708 1709static int 1710ahc_aha394XU_setup(device_t dev, char *channel, ahc_chip *chip, 1711 ahc_feature *features, ahc_flag *flags) 1712{ 1713 int error; 1714 1715 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1716 if (error == 0) 1717 error = ahc_aha394XX_setup(dev, channel, chip, features, flags); 1718 return (error); 1719} 1720 1721static int 1722ahc_aha398XU_setup(device_t dev, char *channel, ahc_chip *chip, 1723 ahc_feature *features, ahc_flag *flags) 1724{ 1725 int error; 1726 1727 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1728 if (error == 0) 1729 error = ahc_aha398XX_setup(dev, channel, chip, features, flags); 1730 return (error); 1731} 1732 1733static int 1734ahc_aic7890_setup(device_t dev, char *channel, ahc_chip *chip, 1735 ahc_feature *features, ahc_flag *flags) 1736{ 1737 *channel = 'A'; 1738 *chip = AHC_AIC7890; 1739 *features = AHC_AIC7890_FE; 1740 *flags |= AHC_NEWEEPROM_FMT; 1741 return (0); 1742} 1743 1744static int 1745ahc_aic7892_setup(device_t dev, char *channel, ahc_chip *chip, 1746 ahc_feature *features, ahc_flag *flags) 1747{ 1748 *channel = 'A'; 1749 *chip = AHC_AIC7892; 1750 *features = AHC_AIC7892_FE; 1751 *flags |= AHC_NEWEEPROM_FMT; 1752 return (0); 1753} 1754 1755static int 1756ahc_aic7895_setup(device_t dev, char *channel, ahc_chip *chip, 1757 ahc_feature *features, ahc_flag *flags) 1758{ 1759 u_int32_t devconfig; 1760 1761 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1762 *chip = AHC_AIC7895; 1763 /* The 'C' revision of the aic7895 has a few additional features */ 1764 if (pci_get_revid(dev) >= 4) 1765 *features = AHC_AIC7895C_FE; 1766 else 1767 *features = AHC_AIC7895_FE; 1768 *flags |= AHC_NEWEEPROM_FMT; 1769 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 1770 devconfig &= ~SCBSIZE32; 1771 pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4); 1772 return (0); 1773} 1774 1775static int 1776ahc_aic7896_setup(device_t dev, char *channel, ahc_chip *chip, 1777 ahc_feature *features, ahc_flag *flags) 1778{ 1779 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1780 *chip = AHC_AIC7896; 1781 *features = AHC_AIC7896_FE; 1782 *flags |= AHC_NEWEEPROM_FMT; 1783 return (0); 1784} 1785 1786static int 1787ahc_aic7899_setup(device_t dev, char *channel, ahc_chip *chip, 1788 ahc_feature *features, ahc_flag *flags) 1789{ 1790 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1791 *chip = AHC_AIC7899; 1792 *features = AHC_AIC7899_FE; 1793 *flags |= AHC_NEWEEPROM_FMT; 1794 return (0); 1795} 1796 1797static int 1798ahc_raid_setup(device_t dev, char *channel, ahc_chip *chip, 1799 ahc_feature *features, ahc_flag *flags) 1800{ 1801 printf("RAID functionality unsupported\n"); 1802 return (ENXIO); 1803} 1804 1805static int 1806ahc_aha394XX_setup(device_t dev, char *channel, ahc_chip *chip, 1807 ahc_feature *features, ahc_flag *flags) 1808{ 1809 switch (pci_get_slot(dev)) { 1810 case AHC_394X_SLOT_CHANNEL_A: 1811 *channel = 'A'; 1812 break; 1813 case AHC_394X_SLOT_CHANNEL_B: 1814 *channel = 'B'; 1815 break; 1816 default: 1817 printf("adapter at unexpected slot %d\n" 1818 "unable to map to a channel\n", 1819 pci_get_slot(dev)); 1820 *channel = 'A'; 1821 } 1822 return (0); 1823} 1824 1825static int 1826ahc_aha398XX_setup(device_t dev, char *channel, ahc_chip *chip, 1827 ahc_feature *features, ahc_flag *flags) 1828{ 1829 switch (pci_get_slot(dev)) { 1830 case AHC_398X_SLOT_CHANNEL_A: 1831 *channel = 'A'; 1832 break; 1833 case AHC_398X_SLOT_CHANNEL_B: 1834 *channel = 'B'; 1835 break; 1836 case AHC_398X_SLOT_CHANNEL_C: 1837 *channel = 'C'; 1838 break; 1839 default: 1840 printf("adapter at unexpected slot %d\n" 1841 "unable to map to a channel\n", 1842 pci_get_slot(dev)); 1843 *channel = 'A'; 1844 } 1845 *flags |= AHC_LARGE_SEEPROM; 1846 return (0); 1847} 1848