ahci.c revision 271523
1/*- 2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/10/sys/dev/ahci/ahci.c 271523 2014-09-13 16:02:43Z mav $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/conf.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <machine/stdarg.h> 41#include <machine/resource.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include "ahci.h" 47 48#include <cam/cam.h> 49#include <cam/cam_ccb.h> 50#include <cam/cam_sim.h> 51#include <cam/cam_xpt_sim.h> 52#include <cam/cam_debug.h> 53 54/* local prototypes */ 55static int ahci_setup_interrupt(device_t dev); 56static void ahci_intr(void *data); 57static void ahci_intr_one(void *data); 58static void ahci_intr_one_edge(void *data); 59static int ahci_suspend(device_t dev); 60static int ahci_resume(device_t dev); 61static int ahci_ch_init(device_t dev); 62static int ahci_ch_deinit(device_t dev); 63static int ahci_ch_suspend(device_t dev); 64static int ahci_ch_resume(device_t dev); 65static void ahci_ch_pm(void *arg); 66static void ahci_ch_intr(void *arg); 67static void ahci_ch_intr_direct(void *arg); 68static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus); 69static int ahci_ctlr_reset(device_t dev); 70static int ahci_ctlr_setup(device_t dev); 71static void ahci_begin_transaction(device_t dev, union ccb *ccb); 72static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 73static void ahci_execute_transaction(struct ahci_slot *slot); 74static void ahci_timeout(struct ahci_slot *slot); 75static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 76static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 77static void ahci_dmainit(device_t dev); 78static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 79static void ahci_dmafini(device_t dev); 80static void ahci_slotsalloc(device_t dev); 81static void ahci_slotsfree(device_t dev); 82static void ahci_reset(device_t dev); 83static void ahci_start(device_t dev, int fbs); 84static void ahci_stop(device_t dev); 85static void ahci_clo(device_t dev); 86static void ahci_start_fr(device_t dev); 87static void ahci_stop_fr(device_t dev); 88 89static int ahci_sata_connect(struct ahci_channel *ch); 90static int ahci_sata_phy_reset(device_t dev); 91static int ahci_wait_ready(device_t dev, int t, int t0); 92 93static void ahci_issue_recovery(device_t dev); 94static void ahci_process_read_log(device_t dev, union ccb *ccb); 95static void ahci_process_request_sense(device_t dev, union ccb *ccb); 96 97static void ahciaction(struct cam_sim *sim, union ccb *ccb); 98static void ahcipoll(struct cam_sim *sim); 99 100static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 101 102static struct { 103 uint32_t id; 104 uint8_t rev; 105 const char *name; 106 int quirks; 107#define AHCI_Q_NOFORCE 1 108#define AHCI_Q_NOPMP 2 109#define AHCI_Q_NONCQ 4 110#define AHCI_Q_1CH 8 111#define AHCI_Q_2CH 16 112#define AHCI_Q_4CH 32 113#define AHCI_Q_EDGEIS 64 114#define AHCI_Q_SATA2 128 115#define AHCI_Q_NOBSYRES 256 116#define AHCI_Q_NOAA 512 117#define AHCI_Q_NOCOUNT 1024 118#define AHCI_Q_ALTSIG 2048 119#define AHCI_Q_NOMSI 4096 120 121#define AHCI_Q_BIT_STRING \ 122 "\020" \ 123 "\001NOFORCE" \ 124 "\002NOPMP" \ 125 "\003NONCQ" \ 126 "\0041CH" \ 127 "\0052CH" \ 128 "\0064CH" \ 129 "\007EDGEIS" \ 130 "\010SATA2" \ 131 "\011NOBSYRES" \ 132 "\012NOAA" \ 133 "\013NOCOUNT" \ 134 "\014ALTSIG" \ 135 "\015NOMSI" 136} ahci_ids[] = { 137 {0x43801002, 0x00, "AMD SB600", AHCI_Q_NOMSI}, 138 {0x43901002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 139 {0x43911002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 140 {0x43921002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 141 {0x43931002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 142 {0x43941002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 143 {0x43951002, 0x00, "AMD SB8x0/SB9x0", 0}, 144 {0x78001022, 0x00, "AMD Hudson-2", 0}, 145 {0x78011022, 0x00, "AMD Hudson-2", 0}, 146 {0x78021022, 0x00, "AMD Hudson-2", 0}, 147 {0x78031022, 0x00, "AMD Hudson-2", 0}, 148 {0x78041022, 0x00, "AMD Hudson-2", 0}, 149 {0x06111b21, 0x00, "ASMedia ASM2106", 0}, 150 {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 151 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 152 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 153 {0x26818086, 0x00, "Intel ESB2", 0}, 154 {0x26828086, 0x00, "Intel ESB2", 0}, 155 {0x26838086, 0x00, "Intel ESB2", 0}, 156 {0x27c18086, 0x00, "Intel ICH7", 0}, 157 {0x27c38086, 0x00, "Intel ICH7", 0}, 158 {0x27c58086, 0x00, "Intel ICH7M", 0}, 159 {0x27c68086, 0x00, "Intel ICH7M", 0}, 160 {0x28218086, 0x00, "Intel ICH8", 0}, 161 {0x28228086, 0x00, "Intel ICH8", 0}, 162 {0x28248086, 0x00, "Intel ICH8", 0}, 163 {0x28298086, 0x00, "Intel ICH8M", 0}, 164 {0x282a8086, 0x00, "Intel ICH8M", 0}, 165 {0x29228086, 0x00, "Intel ICH9", 0}, 166 {0x29238086, 0x00, "Intel ICH9", 0}, 167 {0x29248086, 0x00, "Intel ICH9", 0}, 168 {0x29258086, 0x00, "Intel ICH9", 0}, 169 {0x29278086, 0x00, "Intel ICH9", 0}, 170 {0x29298086, 0x00, "Intel ICH9M", 0}, 171 {0x292a8086, 0x00, "Intel ICH9M", 0}, 172 {0x292b8086, 0x00, "Intel ICH9M", 0}, 173 {0x292c8086, 0x00, "Intel ICH9M", 0}, 174 {0x292f8086, 0x00, "Intel ICH9M", 0}, 175 {0x294d8086, 0x00, "Intel ICH9", 0}, 176 {0x294e8086, 0x00, "Intel ICH9M", 0}, 177 {0x3a058086, 0x00, "Intel ICH10", 0}, 178 {0x3a228086, 0x00, "Intel ICH10", 0}, 179 {0x3a258086, 0x00, "Intel ICH10", 0}, 180 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 181 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 182 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 183 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 184 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 185 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 186 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 187 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 188 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 189 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 190 {0x1d028086, 0x00, "Intel Patsburg", 0}, 191 {0x1d048086, 0x00, "Intel Patsburg", 0}, 192 {0x1d068086, 0x00, "Intel Patsburg", 0}, 193 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0}, 194 {0x1e028086, 0x00, "Intel Panther Point", 0}, 195 {0x1e038086, 0x00, "Intel Panther Point", 0}, 196 {0x1e048086, 0x00, "Intel Panther Point (RAID)", 0}, 197 {0x1e058086, 0x00, "Intel Panther Point (RAID)", 0}, 198 {0x1e068086, 0x00, "Intel Panther Point (RAID)", 0}, 199 {0x1e078086, 0x00, "Intel Panther Point (RAID)", 0}, 200 {0x1e0e8086, 0x00, "Intel Panther Point (RAID)", 0}, 201 {0x1e0f8086, 0x00, "Intel Panther Point (RAID)", 0}, 202 {0x1f228086, 0x00, "Intel Avoton", 0}, 203 {0x1f238086, 0x00, "Intel Avoton", 0}, 204 {0x1f248086, 0x00, "Intel Avoton (RAID)", 0}, 205 {0x1f258086, 0x00, "Intel Avoton (RAID)", 0}, 206 {0x1f268086, 0x00, "Intel Avoton (RAID)", 0}, 207 {0x1f278086, 0x00, "Intel Avoton (RAID)", 0}, 208 {0x1f2e8086, 0x00, "Intel Avoton (RAID)", 0}, 209 {0x1f2f8086, 0x00, "Intel Avoton (RAID)", 0}, 210 {0x1f328086, 0x00, "Intel Avoton", 0}, 211 {0x1f338086, 0x00, "Intel Avoton", 0}, 212 {0x1f348086, 0x00, "Intel Avoton (RAID)", 0}, 213 {0x1f358086, 0x00, "Intel Avoton (RAID)", 0}, 214 {0x1f368086, 0x00, "Intel Avoton (RAID)", 0}, 215 {0x1f378086, 0x00, "Intel Avoton (RAID)", 0}, 216 {0x1f3e8086, 0x00, "Intel Avoton (RAID)", 0}, 217 {0x1f3f8086, 0x00, "Intel Avoton (RAID)", 0}, 218 {0x23a38086, 0x00, "Intel Coleto Creek", 0}, 219 {0x28238086, 0x00, "Intel Wellsburg (RAID)", 0}, 220 {0x28278086, 0x00, "Intel Wellsburg (RAID)", 0}, 221 {0x8c028086, 0x00, "Intel Lynx Point", 0}, 222 {0x8c038086, 0x00, "Intel Lynx Point", 0}, 223 {0x8c048086, 0x00, "Intel Lynx Point (RAID)", 0}, 224 {0x8c058086, 0x00, "Intel Lynx Point (RAID)", 0}, 225 {0x8c068086, 0x00, "Intel Lynx Point (RAID)", 0}, 226 {0x8c078086, 0x00, "Intel Lynx Point (RAID)", 0}, 227 {0x8c0e8086, 0x00, "Intel Lynx Point (RAID)", 0}, 228 {0x8c0f8086, 0x00, "Intel Lynx Point (RAID)", 0}, 229 {0x8d028086, 0x00, "Intel Wellsburg", 0}, 230 {0x8d048086, 0x00, "Intel Wellsburg (RAID)", 0}, 231 {0x8d068086, 0x00, "Intel Wellsburg (RAID)", 0}, 232 {0x8d628086, 0x00, "Intel Wellsburg", 0}, 233 {0x8d648086, 0x00, "Intel Wellsburg (RAID)", 0}, 234 {0x8d668086, 0x00, "Intel Wellsburg (RAID)", 0}, 235 {0x8d6e8086, 0x00, "Intel Wellsburg (RAID)", 0}, 236 {0x9c028086, 0x00, "Intel Lynx Point-LP", 0}, 237 {0x9c038086, 0x00, "Intel Lynx Point-LP", 0}, 238 {0x9c048086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 239 {0x9c058086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 240 {0x9c068086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 241 {0x9c078086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 242 {0x9c0e8086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 243 {0x9c0f8086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 244 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 245 {0x2360197b, 0x00, "JMicron JMB360", 0}, 246 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 247 {0x2362197b, 0x00, "JMicron JMB362", 0}, 248 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 249 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 250 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 251 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 252 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 253 AHCI_Q_EDGEIS}, 254 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 255 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 256 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 257 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 258 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 259 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 260 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS}, 261 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_ALTSIG}, 262 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2}, 263 {0x91251b4b, 0x00, "Marvell 88SE9125", 0}, 264 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_ALTSIG}, 265 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_ALTSIG}, 266 {0x91721b4b, 0x00, "Marvell 88SE9172", 0}, 267 {0x91821b4b, 0x00, "Marvell 88SE9182", 0}, 268 {0x91831b4b, 0x00, "Marvell 88SS9183", 0}, 269 {0x91a01b4b, 0x00, "Marvell 88SE91Ax", 0}, 270 {0x92151b4b, 0x00, "Marvell 88SE9215", 0}, 271 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_ALTSIG}, 272 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_ALTSIG}, 273 {0x92351b4b, 0x00, "Marvell 88SE9235", 0}, 274 {0x06201103, 0x00, "HighPoint RocketRAID 620", 0}, 275 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", 0}, 276 {0x06221103, 0x00, "HighPoint RocketRAID 622", 0}, 277 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", 0}, 278 {0x06401103, 0x00, "HighPoint RocketRAID 640", 0}, 279 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", 0}, 280 {0x06441103, 0x00, "HighPoint RocketRAID 644", 0}, 281 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", 0}, 282 {0x06411103, 0x00, "HighPoint RocketRAID 640L", 0}, 283 {0x06421103, 0x00, "HighPoint RocketRAID 642L", 0}, 284 {0x06451103, 0x00, "HighPoint RocketRAID 644L", 0}, 285 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 286 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 287 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 288 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 289 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 290 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 291 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 292 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 293 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 294 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 295 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 296 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 297 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 298 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 299 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 300 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 301 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 302 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 303 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 304 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 305 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 306 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 307 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 308 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 309 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 310 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 311 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 312 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 313 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 314 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 315 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 316 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 317 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 318 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 319 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 320 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 321 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 322 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 323 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 324 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 325 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 326 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 327 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 328 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 329 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 330 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 331 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 332 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 333 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 334 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 335 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 336 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 337 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 338 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 339 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 340 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 341 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 342 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 343 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 344 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 345 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 346 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 347 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 348 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 349 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 350 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 351 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 352 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 353 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 354 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 355 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 356 {0x11841039, 0x00, "SiS 966", 0}, 357 {0x11851039, 0x00, "SiS 968", 0}, 358 {0x01861039, 0x00, "SiS 968", 0}, 359 {0x00000000, 0x00, NULL, 0} 360}; 361 362#define recovery_type spriv_field0 363#define RECOVERY_NONE 0 364#define RECOVERY_READ_LOG 1 365#define RECOVERY_REQUEST_SENSE 2 366#define recovery_slot spriv_field1 367 368static int force_ahci = 1; 369TUNABLE_INT("hw.ahci.force", &force_ahci); 370 371static int 372ahci_probe(device_t dev) 373{ 374 char buf[64]; 375 int i, valid = 0; 376 uint32_t devid = pci_get_devid(dev); 377 uint8_t revid = pci_get_revid(dev); 378 379 /* 380 * Ensure it is not a PCI bridge (some vendors use 381 * the same PID and VID in PCI bridge and AHCI cards). 382 */ 383 if (pci_get_class(dev) == PCIC_BRIDGE) 384 return (ENXIO); 385 386 /* Is this a possible AHCI candidate? */ 387 if (pci_get_class(dev) == PCIC_STORAGE && 388 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 389 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 390 valid = 1; 391 /* Is this a known AHCI chip? */ 392 for (i = 0; ahci_ids[i].id != 0; i++) { 393 if (ahci_ids[i].id == devid && 394 ahci_ids[i].rev <= revid && 395 (valid || (force_ahci == 1 && 396 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) { 397 /* Do not attach JMicrons with single PCI function. */ 398 if (pci_get_vendor(dev) == 0x197b && 399 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 400 return (ENXIO); 401 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 402 ahci_ids[i].name); 403 device_set_desc_copy(dev, buf); 404 return (BUS_PROBE_VENDOR); 405 } 406 } 407 if (!valid) 408 return (ENXIO); 409 device_set_desc_copy(dev, "AHCI SATA controller"); 410 return (BUS_PROBE_VENDOR); 411} 412 413static int 414ahci_ata_probe(device_t dev) 415{ 416 char buf[64]; 417 int i; 418 uint32_t devid = pci_get_devid(dev); 419 uint8_t revid = pci_get_revid(dev); 420 421 if ((intptr_t)device_get_ivars(dev) >= 0) 422 return (ENXIO); 423 /* Is this a known AHCI chip? */ 424 for (i = 0; ahci_ids[i].id != 0; i++) { 425 if (ahci_ids[i].id == devid && 426 ahci_ids[i].rev <= revid) { 427 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 428 ahci_ids[i].name); 429 device_set_desc_copy(dev, buf); 430 return (BUS_PROBE_VENDOR); 431 } 432 } 433 device_set_desc_copy(dev, "AHCI SATA controller"); 434 return (BUS_PROBE_VENDOR); 435} 436 437static int 438ahci_attach(device_t dev) 439{ 440 struct ahci_controller *ctlr = device_get_softc(dev); 441 device_t child; 442 int error, unit, speed, i; 443 u_int u; 444 uint32_t devid = pci_get_devid(dev); 445 uint8_t revid = pci_get_revid(dev); 446 u_int32_t version; 447 448 ctlr->dev = dev; 449 i = 0; 450 while (ahci_ids[i].id != 0 && 451 (ahci_ids[i].id != devid || 452 ahci_ids[i].rev > revid)) 453 i++; 454 ctlr->quirks = ahci_ids[i].quirks; 455 resource_int_value(device_get_name(dev), 456 device_get_unit(dev), "ccc", &ctlr->ccc); 457 /* if we have a memory BAR(5) we are likely on an AHCI part */ 458 ctlr->r_rid = PCIR_BAR(5); 459 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 460 &ctlr->r_rid, RF_ACTIVE))) 461 return ENXIO; 462 /* Setup our own memory management for channels. */ 463 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 464 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 465 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 466 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 467 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 468 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 469 return (error); 470 } 471 if ((error = rman_manage_region(&ctlr->sc_iomem, 472 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 473 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 474 rman_fini(&ctlr->sc_iomem); 475 return (error); 476 } 477 pci_enable_busmaster(dev); 478 /* Reset controller */ 479 if ((error = ahci_ctlr_reset(dev)) != 0) { 480 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 481 rman_fini(&ctlr->sc_iomem); 482 return (error); 483 }; 484 /* Get the HW capabilities */ 485 version = ATA_INL(ctlr->r_mem, AHCI_VS); 486 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 487 if (version >= 0x00010200) 488 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 489 if (ctlr->caps & AHCI_CAP_EMS) 490 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 491 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 492 493 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 494 if ((ctlr->quirks & AHCI_Q_ALTSIG) && 495 (ctlr->caps & AHCI_CAP_SPM) == 0) 496 ctlr->quirks |= AHCI_Q_NOBSYRES; 497 498 if (ctlr->quirks & AHCI_Q_1CH) { 499 ctlr->caps &= ~AHCI_CAP_NPMASK; 500 ctlr->ichannels &= 0x01; 501 } 502 if (ctlr->quirks & AHCI_Q_2CH) { 503 ctlr->caps &= ~AHCI_CAP_NPMASK; 504 ctlr->caps |= 1; 505 ctlr->ichannels &= 0x03; 506 } 507 if (ctlr->quirks & AHCI_Q_4CH) { 508 ctlr->caps &= ~AHCI_CAP_NPMASK; 509 ctlr->caps |= 3; 510 ctlr->ichannels &= 0x0f; 511 } 512 ctlr->channels = MAX(flsl(ctlr->ichannels), 513 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 514 if (ctlr->quirks & AHCI_Q_NOPMP) 515 ctlr->caps &= ~AHCI_CAP_SPM; 516 if (ctlr->quirks & AHCI_Q_NONCQ) 517 ctlr->caps &= ~AHCI_CAP_SNCQ; 518 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 519 ctlr->ccc = 0; 520 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 521 522 /* Create controller-wide DMA tag. */ 523 if (bus_dma_tag_create(bus_get_dma_tag(dev), 0, 0, 524 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR : 525 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 526 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 527 0, NULL, NULL, &ctlr->dma_tag)) { 528 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 529 ctlr->r_mem); 530 rman_fini(&ctlr->sc_iomem); 531 return ENXIO; 532 } 533 534 ahci_ctlr_setup(dev); 535 /* Setup interrupts. */ 536 if (ahci_setup_interrupt(dev)) { 537 bus_dma_tag_destroy(ctlr->dma_tag); 538 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 539 rman_fini(&ctlr->sc_iomem); 540 return ENXIO; 541 } 542 i = 0; 543 for (u = ctlr->ichannels; u != 0; u >>= 1) 544 i += (u & 1); 545 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3)); 546 resource_int_value(device_get_name(dev), device_get_unit(dev), 547 "direct", &ctlr->direct); 548 /* Announce HW capabilities. */ 549 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 550 device_printf(dev, 551 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 552 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 553 ((version >> 4) & 0xf0) + (version & 0x0f), 554 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 555 ((speed == 1) ? "1.5":((speed == 2) ? "3": 556 ((speed == 3) ? "6":"?"))), 557 (ctlr->caps & AHCI_CAP_SPM) ? 558 "supported" : "not supported", 559 (ctlr->caps & AHCI_CAP_FBSS) ? 560 " with FBS" : ""); 561 if (ctlr->quirks != 0) { 562 device_printf(dev, "quirks=0x%b\n", ctlr->quirks, 563 AHCI_Q_BIT_STRING); 564 } 565 if (bootverbose) { 566 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 567 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 568 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 569 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 570 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 571 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 572 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 573 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 574 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 575 ((speed == 1) ? "1.5":((speed == 2) ? "3": 576 ((speed == 3) ? "6":"?")))); 577 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 578 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 579 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 580 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 581 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 582 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 583 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 584 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 585 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 586 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 587 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 588 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 589 } 590 if (bootverbose && version >= 0x00010200) { 591 device_printf(dev, "Caps2:%s%s%s%s%s%s\n", 592 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"", 593 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"", 594 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"", 595 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 596 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 597 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 598 } 599 /* Attach all channels on this controller */ 600 for (unit = 0; unit < ctlr->channels; unit++) { 601 child = device_add_child(dev, "ahcich", -1); 602 if (child == NULL) { 603 device_printf(dev, "failed to add channel device\n"); 604 continue; 605 } 606 device_set_ivars(child, (void *)(intptr_t)unit); 607 if ((ctlr->ichannels & (1 << unit)) == 0) 608 device_disable(child); 609 } 610 if (ctlr->caps & AHCI_CAP_EMS) { 611 child = device_add_child(dev, "ahciem", -1); 612 if (child == NULL) 613 device_printf(dev, "failed to add enclosure device\n"); 614 else 615 device_set_ivars(child, (void *)(intptr_t)-1); 616 } 617 bus_generic_attach(dev); 618 return 0; 619} 620 621static int 622ahci_detach(device_t dev) 623{ 624 struct ahci_controller *ctlr = device_get_softc(dev); 625 int i; 626 627 /* Detach & delete all children */ 628 device_delete_children(dev); 629 630 /* Free interrupts. */ 631 for (i = 0; i < ctlr->numirqs; i++) { 632 if (ctlr->irqs[i].r_irq) { 633 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 634 ctlr->irqs[i].handle); 635 bus_release_resource(dev, SYS_RES_IRQ, 636 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 637 } 638 } 639 pci_release_msi(dev); 640 bus_dma_tag_destroy(ctlr->dma_tag); 641 /* Free memory. */ 642 rman_fini(&ctlr->sc_iomem); 643 if (ctlr->r_mem) 644 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 645 return (0); 646} 647 648static int 649ahci_ctlr_reset(device_t dev) 650{ 651 struct ahci_controller *ctlr = device_get_softc(dev); 652 int timeout; 653 654 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 && 655 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 656 pci_write_config(dev, 0x92, 0x01, 1); 657 /* Enable AHCI mode */ 658 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 659 /* Reset AHCI controller */ 660 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 661 for (timeout = 1000; timeout > 0; timeout--) { 662 DELAY(1000); 663 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 664 break; 665 } 666 if (timeout == 0) { 667 device_printf(dev, "AHCI controller reset failure\n"); 668 return ENXIO; 669 } 670 /* Reenable AHCI mode */ 671 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 672 return (0); 673} 674 675static int 676ahci_ctlr_setup(device_t dev) 677{ 678 struct ahci_controller *ctlr = device_get_softc(dev); 679 /* Clear interrupts */ 680 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 681 /* Configure CCC */ 682 if (ctlr->ccc) { 683 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 684 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 685 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 686 (4 << AHCI_CCCC_CC_SHIFT) | 687 AHCI_CCCC_EN); 688 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 689 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 690 if (bootverbose) { 691 device_printf(dev, 692 "CCC with %dms/4cmd enabled on vector %d\n", 693 ctlr->ccc, ctlr->cccv); 694 } 695 } 696 /* Enable AHCI interrupts */ 697 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 698 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 699 return (0); 700} 701 702static int 703ahci_suspend(device_t dev) 704{ 705 struct ahci_controller *ctlr = device_get_softc(dev); 706 707 bus_generic_suspend(dev); 708 /* Disable interupts, so the state change(s) doesn't trigger */ 709 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 710 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 711 return 0; 712} 713 714static int 715ahci_resume(device_t dev) 716{ 717 int res; 718 719 if ((res = ahci_ctlr_reset(dev)) != 0) 720 return (res); 721 ahci_ctlr_setup(dev); 722 return (bus_generic_resume(dev)); 723} 724 725static int 726ahci_setup_interrupt(device_t dev) 727{ 728 struct ahci_controller *ctlr = device_get_softc(dev); 729 int i; 730 731 ctlr->msi = 2; 732 /* Process hints. */ 733 if (ctlr->quirks & AHCI_Q_NOMSI) 734 ctlr->msi = 0; 735 resource_int_value(device_get_name(dev), 736 device_get_unit(dev), "msi", &ctlr->msi); 737 ctlr->numirqs = 1; 738 if (ctlr->msi < 0) 739 ctlr->msi = 0; 740 else if (ctlr->msi == 1) 741 ctlr->msi = min(1, pci_msi_count(dev)); 742 else if (ctlr->msi > 1) { 743 ctlr->msi = 2; 744 ctlr->numirqs = pci_msi_count(dev); 745 } 746 /* Allocate MSI if needed/present. */ 747 if (ctlr->msi && pci_alloc_msi(dev, &ctlr->numirqs) != 0) { 748 ctlr->msi = 0; 749 ctlr->numirqs = 1; 750 } 751 /* Check for single MSI vector fallback. */ 752 if (ctlr->numirqs > 1 && 753 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 754 device_printf(dev, "Falling back to one MSI\n"); 755 ctlr->numirqs = 1; 756 } 757 /* Allocate all IRQs. */ 758 for (i = 0; i < ctlr->numirqs; i++) { 759 ctlr->irqs[i].ctlr = ctlr; 760 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0); 761 if (ctlr->numirqs == 1 || i >= ctlr->channels || 762 (ctlr->ccc && i == ctlr->cccv)) 763 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 764 else if (i == ctlr->numirqs - 1) 765 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 766 else 767 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 768 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 769 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 770 device_printf(dev, "unable to map interrupt\n"); 771 return ENXIO; 772 } 773 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 774 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr : 775 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge : 776 ahci_intr_one), 777 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 778 /* SOS XXX release r_irq */ 779 device_printf(dev, "unable to setup interrupt\n"); 780 return ENXIO; 781 } 782 if (ctlr->numirqs > 1) { 783 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 784 ctlr->irqs[i].handle, 785 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 786 "ch%d" : "%d", i); 787 } 788 } 789 return (0); 790} 791 792/* 793 * Common case interrupt handler. 794 */ 795static void 796ahci_intr(void *data) 797{ 798 struct ahci_controller_irq *irq = data; 799 struct ahci_controller *ctlr = irq->ctlr; 800 u_int32_t is, ise = 0; 801 void *arg; 802 int unit; 803 804 if (irq->mode == AHCI_IRQ_MODE_ALL) { 805 unit = 0; 806 if (ctlr->ccc) 807 is = ctlr->ichannels; 808 else 809 is = ATA_INL(ctlr->r_mem, AHCI_IS); 810 } else { /* AHCI_IRQ_MODE_AFTER */ 811 unit = irq->r_irq_rid - 1; 812 is = ATA_INL(ctlr->r_mem, AHCI_IS); 813 } 814 /* CCC interrupt is edge triggered. */ 815 if (ctlr->ccc) 816 ise = 1 << ctlr->cccv; 817 /* Some controllers have edge triggered IS. */ 818 if (ctlr->quirks & AHCI_Q_EDGEIS) 819 ise |= is; 820 if (ise != 0) 821 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 822 for (; unit < ctlr->channels; unit++) { 823 if ((is & (1 << unit)) != 0 && 824 (arg = ctlr->interrupt[unit].argument)) { 825 ctlr->interrupt[unit].function(arg); 826 } 827 } 828 /* AHCI declares level triggered IS. */ 829 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 830 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 831} 832 833/* 834 * Simplified interrupt handler for multivector MSI mode. 835 */ 836static void 837ahci_intr_one(void *data) 838{ 839 struct ahci_controller_irq *irq = data; 840 struct ahci_controller *ctlr = irq->ctlr; 841 void *arg; 842 int unit; 843 844 unit = irq->r_irq_rid - 1; 845 if ((arg = ctlr->interrupt[unit].argument)) 846 ctlr->interrupt[unit].function(arg); 847 /* AHCI declares level triggered IS. */ 848 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 849} 850 851static void 852ahci_intr_one_edge(void *data) 853{ 854 struct ahci_controller_irq *irq = data; 855 struct ahci_controller *ctlr = irq->ctlr; 856 void *arg; 857 int unit; 858 859 unit = irq->r_irq_rid - 1; 860 /* Some controllers have edge triggered IS. */ 861 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 862 if ((arg = ctlr->interrupt[unit].argument)) 863 ctlr->interrupt[unit].function(arg); 864} 865 866static struct resource * 867ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 868 u_long start, u_long end, u_long count, u_int flags) 869{ 870 struct ahci_controller *ctlr = device_get_softc(dev); 871 struct resource *res; 872 long st; 873 int offset, size, unit; 874 875 unit = (intptr_t)device_get_ivars(child); 876 res = NULL; 877 switch (type) { 878 case SYS_RES_MEMORY: 879 if (unit >= 0) { 880 offset = AHCI_OFFSET + (unit << 7); 881 size = 128; 882 } else if (*rid == 0) { 883 offset = AHCI_EM_CTL; 884 size = 4; 885 } else { 886 offset = (ctlr->emloc & 0xffff0000) >> 14; 887 size = (ctlr->emloc & 0x0000ffff) << 2; 888 if (*rid != 1) { 889 if (*rid == 2 && (ctlr->capsem & 890 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 891 offset += size; 892 else 893 break; 894 } 895 } 896 st = rman_get_start(ctlr->r_mem); 897 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 898 st + offset + size - 1, size, RF_ACTIVE, child); 899 if (res) { 900 bus_space_handle_t bsh; 901 bus_space_tag_t bst; 902 bsh = rman_get_bushandle(ctlr->r_mem); 903 bst = rman_get_bustag(ctlr->r_mem); 904 bus_space_subregion(bst, bsh, offset, 128, &bsh); 905 rman_set_bushandle(res, bsh); 906 rman_set_bustag(res, bst); 907 } 908 break; 909 case SYS_RES_IRQ: 910 if (*rid == ATA_IRQ_RID) 911 res = ctlr->irqs[0].r_irq; 912 break; 913 } 914 return (res); 915} 916 917static int 918ahci_release_resource(device_t dev, device_t child, int type, int rid, 919 struct resource *r) 920{ 921 922 switch (type) { 923 case SYS_RES_MEMORY: 924 rman_release_resource(r); 925 return (0); 926 case SYS_RES_IRQ: 927 if (rid != ATA_IRQ_RID) 928 return ENOENT; 929 return (0); 930 } 931 return (EINVAL); 932} 933 934static int 935ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 936 int flags, driver_filter_t *filter, driver_intr_t *function, 937 void *argument, void **cookiep) 938{ 939 struct ahci_controller *ctlr = device_get_softc(dev); 940 int unit = (intptr_t)device_get_ivars(child); 941 942 if (filter != NULL) { 943 printf("ahci.c: we cannot use a filter here\n"); 944 return (EINVAL); 945 } 946 ctlr->interrupt[unit].function = function; 947 ctlr->interrupt[unit].argument = argument; 948 return (0); 949} 950 951static int 952ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 953 void *cookie) 954{ 955 struct ahci_controller *ctlr = device_get_softc(dev); 956 int unit = (intptr_t)device_get_ivars(child); 957 958 ctlr->interrupt[unit].function = NULL; 959 ctlr->interrupt[unit].argument = NULL; 960 return (0); 961} 962 963static int 964ahci_print_child(device_t dev, device_t child) 965{ 966 int retval, channel; 967 968 retval = bus_print_child_header(dev, child); 969 channel = (int)(intptr_t)device_get_ivars(child); 970 if (channel >= 0) 971 retval += printf(" at channel %d", channel); 972 retval += bus_print_child_footer(dev, child); 973 return (retval); 974} 975 976static int 977ahci_child_location_str(device_t dev, device_t child, char *buf, 978 size_t buflen) 979{ 980 int channel; 981 982 channel = (int)(intptr_t)device_get_ivars(child); 983 if (channel >= 0) 984 snprintf(buf, buflen, "channel=%d", channel); 985 return (0); 986} 987 988static bus_dma_tag_t 989ahci_get_dma_tag(device_t dev, device_t child) 990{ 991 struct ahci_controller *ctlr = device_get_softc(dev); 992 993 return (ctlr->dma_tag); 994} 995 996devclass_t ahci_devclass; 997static device_method_t ahci_methods[] = { 998 DEVMETHOD(device_probe, ahci_probe), 999 DEVMETHOD(device_attach, ahci_attach), 1000 DEVMETHOD(device_detach, ahci_detach), 1001 DEVMETHOD(device_suspend, ahci_suspend), 1002 DEVMETHOD(device_resume, ahci_resume), 1003 DEVMETHOD(bus_print_child, ahci_print_child), 1004 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 1005 DEVMETHOD(bus_release_resource, ahci_release_resource), 1006 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 1007 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 1008 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 1009 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag), 1010 { 0, 0 } 1011}; 1012static driver_t ahci_driver = { 1013 "ahci", 1014 ahci_methods, 1015 sizeof(struct ahci_controller) 1016}; 1017DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 1018static device_method_t ahci_ata_methods[] = { 1019 DEVMETHOD(device_probe, ahci_ata_probe), 1020 DEVMETHOD(device_attach, ahci_attach), 1021 DEVMETHOD(device_detach, ahci_detach), 1022 DEVMETHOD(device_suspend, ahci_suspend), 1023 DEVMETHOD(device_resume, ahci_resume), 1024 DEVMETHOD(bus_print_child, ahci_print_child), 1025 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 1026 DEVMETHOD(bus_release_resource, ahci_release_resource), 1027 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 1028 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 1029 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 1030 { 0, 0 } 1031}; 1032static driver_t ahci_ata_driver = { 1033 "ahci", 1034 ahci_ata_methods, 1035 sizeof(struct ahci_controller) 1036}; 1037DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 1038MODULE_VERSION(ahci, 1); 1039MODULE_DEPEND(ahci, cam, 1, 1, 1); 1040 1041static int 1042ahci_ch_probe(device_t dev) 1043{ 1044 1045 device_set_desc_copy(dev, "AHCI channel"); 1046 return (0); 1047} 1048 1049static int 1050ahci_ch_attach(device_t dev) 1051{ 1052 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1053 struct ahci_channel *ch = device_get_softc(dev); 1054 struct cam_devq *devq; 1055 int rid, error, i, sata_rev = 0; 1056 u_int32_t version; 1057 1058 ch->dev = dev; 1059 ch->unit = (intptr_t)device_get_ivars(dev); 1060 ch->caps = ctlr->caps; 1061 ch->caps2 = ctlr->caps2; 1062 ch->quirks = ctlr->quirks; 1063 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 1064 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 1065 resource_int_value(device_get_name(dev), 1066 device_get_unit(dev), "pm_level", &ch->pm_level); 1067 STAILQ_INIT(&ch->doneq); 1068 if (ch->pm_level > 3) 1069 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 1070 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 1071 /* Limit speed for my onboard JMicron external port. 1072 * It is not eSATA really. */ 1073 if (pci_get_devid(ctlr->dev) == 0x2363197b && 1074 pci_get_subvendor(ctlr->dev) == 0x1043 && 1075 pci_get_subdevice(ctlr->dev) == 0x81e4 && 1076 ch->unit == 0) 1077 sata_rev = 1; 1078 if (ch->quirks & AHCI_Q_SATA2) 1079 sata_rev = 2; 1080 resource_int_value(device_get_name(dev), 1081 device_get_unit(dev), "sata_rev", &sata_rev); 1082 for (i = 0; i < 16; i++) { 1083 ch->user[i].revision = sata_rev; 1084 ch->user[i].mode = 0; 1085 ch->user[i].bytecount = 8192; 1086 ch->user[i].tags = ch->numslots; 1087 ch->user[i].caps = 0; 1088 ch->curr[i] = ch->user[i]; 1089 if (ch->pm_level) { 1090 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 1091 CTS_SATA_CAPS_H_APST | 1092 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 1093 } 1094 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 1095 CTS_SATA_CAPS_H_AN; 1096 } 1097 rid = 0; 1098 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1099 &rid, RF_ACTIVE))) 1100 return (ENXIO); 1101 ahci_dmainit(dev); 1102 ahci_slotsalloc(dev); 1103 ahci_ch_init(dev); 1104 mtx_lock(&ch->mtx); 1105 rid = ATA_IRQ_RID; 1106 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1107 &rid, RF_SHAREABLE | RF_ACTIVE))) { 1108 device_printf(dev, "Unable to map interrupt\n"); 1109 error = ENXIO; 1110 goto err0; 1111 } 1112 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 1113 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr, 1114 dev, &ch->ih))) { 1115 device_printf(dev, "Unable to setup interrupt\n"); 1116 error = ENXIO; 1117 goto err1; 1118 } 1119 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 1120 version = ATA_INL(ctlr->r_mem, AHCI_VS); 1121 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 1122 ch->chcaps |= AHCI_P_CMD_FBSCP; 1123 if (ch->caps2 & AHCI_CAP2_SDS) 1124 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP); 1125 if (bootverbose) { 1126 device_printf(dev, "Caps:%s%s%s%s%s%s\n", 1127 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 1128 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 1129 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 1130 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 1131 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"", 1132 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":""); 1133 } 1134 /* Create the device queue for our SIM. */ 1135 devq = cam_simq_alloc(ch->numslots); 1136 if (devq == NULL) { 1137 device_printf(dev, "Unable to allocate simq\n"); 1138 error = ENOMEM; 1139 goto err1; 1140 } 1141 /* Construct SIM entry */ 1142 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 1143 device_get_unit(dev), &ch->mtx, 1144 min(2, ch->numslots), 1145 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 1146 devq); 1147 if (ch->sim == NULL) { 1148 cam_simq_free(devq); 1149 device_printf(dev, "unable to allocate sim\n"); 1150 error = ENOMEM; 1151 goto err1; 1152 } 1153 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1154 device_printf(dev, "unable to register xpt bus\n"); 1155 error = ENXIO; 1156 goto err2; 1157 } 1158 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1159 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1160 device_printf(dev, "unable to create path\n"); 1161 error = ENXIO; 1162 goto err3; 1163 } 1164 if (ch->pm_level > 3) { 1165 callout_reset(&ch->pm_timer, 1166 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1167 ahci_ch_pm, dev); 1168 } 1169 mtx_unlock(&ch->mtx); 1170 return (0); 1171 1172err3: 1173 xpt_bus_deregister(cam_sim_path(ch->sim)); 1174err2: 1175 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1176err1: 1177 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1178err0: 1179 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1180 mtx_unlock(&ch->mtx); 1181 mtx_destroy(&ch->mtx); 1182 return (error); 1183} 1184 1185static int 1186ahci_ch_detach(device_t dev) 1187{ 1188 struct ahci_channel *ch = device_get_softc(dev); 1189 1190 mtx_lock(&ch->mtx); 1191 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1192 /* Forget about reset. */ 1193 if (ch->resetting) { 1194 ch->resetting = 0; 1195 xpt_release_simq(ch->sim, TRUE); 1196 } 1197 xpt_free_path(ch->path); 1198 xpt_bus_deregister(cam_sim_path(ch->sim)); 1199 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1200 mtx_unlock(&ch->mtx); 1201 1202 if (ch->pm_level > 3) 1203 callout_drain(&ch->pm_timer); 1204 callout_drain(&ch->reset_timer); 1205 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1206 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1207 1208 ahci_ch_deinit(dev); 1209 ahci_slotsfree(dev); 1210 ahci_dmafini(dev); 1211 1212 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1213 mtx_destroy(&ch->mtx); 1214 return (0); 1215} 1216 1217static int 1218ahci_ch_init(device_t dev) 1219{ 1220 struct ahci_channel *ch = device_get_softc(dev); 1221 uint64_t work; 1222 1223 /* Disable port interrupts */ 1224 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1225 /* Setup work areas */ 1226 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1227 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1228 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1229 work = ch->dma.rfis_bus; 1230 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1231 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1232 /* Activate the channel and power/spin up device */ 1233 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1234 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1235 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1236 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1237 ahci_start_fr(dev); 1238 ahci_start(dev, 1); 1239 return (0); 1240} 1241 1242static int 1243ahci_ch_deinit(device_t dev) 1244{ 1245 struct ahci_channel *ch = device_get_softc(dev); 1246 1247 /* Disable port interrupts. */ 1248 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1249 /* Reset command register. */ 1250 ahci_stop(dev); 1251 ahci_stop_fr(dev); 1252 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1253 /* Allow everything, including partial and slumber modes. */ 1254 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1255 /* Request slumber mode transition and give some time to get there. */ 1256 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1257 DELAY(100); 1258 /* Disable PHY. */ 1259 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1260 return (0); 1261} 1262 1263static int 1264ahci_ch_suspend(device_t dev) 1265{ 1266 struct ahci_channel *ch = device_get_softc(dev); 1267 1268 mtx_lock(&ch->mtx); 1269 xpt_freeze_simq(ch->sim, 1); 1270 /* Forget about reset. */ 1271 if (ch->resetting) { 1272 ch->resetting = 0; 1273 callout_stop(&ch->reset_timer); 1274 xpt_release_simq(ch->sim, TRUE); 1275 } 1276 while (ch->oslots) 1277 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1278 ahci_ch_deinit(dev); 1279 mtx_unlock(&ch->mtx); 1280 return (0); 1281} 1282 1283static int 1284ahci_ch_resume(device_t dev) 1285{ 1286 struct ahci_channel *ch = device_get_softc(dev); 1287 1288 mtx_lock(&ch->mtx); 1289 ahci_ch_init(dev); 1290 ahci_reset(dev); 1291 xpt_release_simq(ch->sim, TRUE); 1292 mtx_unlock(&ch->mtx); 1293 return (0); 1294} 1295 1296devclass_t ahcich_devclass; 1297static device_method_t ahcich_methods[] = { 1298 DEVMETHOD(device_probe, ahci_ch_probe), 1299 DEVMETHOD(device_attach, ahci_ch_attach), 1300 DEVMETHOD(device_detach, ahci_ch_detach), 1301 DEVMETHOD(device_suspend, ahci_ch_suspend), 1302 DEVMETHOD(device_resume, ahci_ch_resume), 1303 { 0, 0 } 1304}; 1305static driver_t ahcich_driver = { 1306 "ahcich", 1307 ahcich_methods, 1308 sizeof(struct ahci_channel) 1309}; 1310DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1311 1312struct ahci_dc_cb_args { 1313 bus_addr_t maddr; 1314 int error; 1315}; 1316 1317static void 1318ahci_dmainit(device_t dev) 1319{ 1320 struct ahci_channel *ch = device_get_softc(dev); 1321 struct ahci_dc_cb_args dcba; 1322 size_t rfsize; 1323 1324 /* Command area. */ 1325 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1326 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1327 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1328 0, NULL, NULL, &ch->dma.work_tag)) 1329 goto error; 1330 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 1331 BUS_DMA_ZERO, &ch->dma.work_map)) 1332 goto error; 1333 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1334 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1335 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1336 goto error; 1337 } 1338 ch->dma.work_bus = dcba.maddr; 1339 /* FIS receive area. */ 1340 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1341 rfsize = 4096; 1342 else 1343 rfsize = 256; 1344 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1345 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1346 NULL, NULL, rfsize, 1, rfsize, 1347 0, NULL, NULL, &ch->dma.rfis_tag)) 1348 goto error; 1349 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1350 &ch->dma.rfis_map)) 1351 goto error; 1352 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1353 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1354 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1355 goto error; 1356 } 1357 ch->dma.rfis_bus = dcba.maddr; 1358 /* Data area. */ 1359 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1360 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1361 NULL, NULL, 1362 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1363 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1364 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1365 goto error; 1366 } 1367 return; 1368 1369error: 1370 device_printf(dev, "WARNING - DMA initialization failed\n"); 1371 ahci_dmafini(dev); 1372} 1373 1374static void 1375ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1376{ 1377 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1378 1379 if (!(dcba->error = error)) 1380 dcba->maddr = segs[0].ds_addr; 1381} 1382 1383static void 1384ahci_dmafini(device_t dev) 1385{ 1386 struct ahci_channel *ch = device_get_softc(dev); 1387 1388 if (ch->dma.data_tag) { 1389 bus_dma_tag_destroy(ch->dma.data_tag); 1390 ch->dma.data_tag = NULL; 1391 } 1392 if (ch->dma.rfis_bus) { 1393 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1394 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1395 ch->dma.rfis_bus = 0; 1396 ch->dma.rfis_map = NULL; 1397 ch->dma.rfis = NULL; 1398 } 1399 if (ch->dma.work_bus) { 1400 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1401 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1402 ch->dma.work_bus = 0; 1403 ch->dma.work_map = NULL; 1404 ch->dma.work = NULL; 1405 } 1406 if (ch->dma.work_tag) { 1407 bus_dma_tag_destroy(ch->dma.work_tag); 1408 ch->dma.work_tag = NULL; 1409 } 1410} 1411 1412static void 1413ahci_slotsalloc(device_t dev) 1414{ 1415 struct ahci_channel *ch = device_get_softc(dev); 1416 int i; 1417 1418 /* Alloc and setup command/dma slots */ 1419 bzero(ch->slot, sizeof(ch->slot)); 1420 for (i = 0; i < ch->numslots; i++) { 1421 struct ahci_slot *slot = &ch->slot[i]; 1422 1423 slot->dev = dev; 1424 slot->slot = i; 1425 slot->state = AHCI_SLOT_EMPTY; 1426 slot->ccb = NULL; 1427 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1428 1429 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1430 device_printf(ch->dev, "FAILURE - create data_map\n"); 1431 } 1432} 1433 1434static void 1435ahci_slotsfree(device_t dev) 1436{ 1437 struct ahci_channel *ch = device_get_softc(dev); 1438 int i; 1439 1440 /* Free all dma slots */ 1441 for (i = 0; i < ch->numslots; i++) { 1442 struct ahci_slot *slot = &ch->slot[i]; 1443 1444 callout_drain(&slot->timeout); 1445 if (slot->dma.data_map) { 1446 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1447 slot->dma.data_map = NULL; 1448 } 1449 } 1450} 1451 1452static int 1453ahci_phy_check_events(device_t dev, u_int32_t serr) 1454{ 1455 struct ahci_channel *ch = device_get_softc(dev); 1456 1457 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1458 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1459 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1460 union ccb *ccb; 1461 1462 if (bootverbose) { 1463 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1464 device_printf(dev, "CONNECT requested\n"); 1465 else 1466 device_printf(dev, "DISCONNECT requested\n"); 1467 } 1468 ahci_reset(dev); 1469 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1470 return (0); 1471 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1472 cam_sim_path(ch->sim), 1473 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1474 xpt_free_ccb(ccb); 1475 return (0); 1476 } 1477 xpt_rescan(ccb); 1478 return (1); 1479 } 1480 return (0); 1481} 1482 1483static void 1484ahci_cpd_check_events(device_t dev) 1485{ 1486 struct ahci_channel *ch = device_get_softc(dev); 1487 u_int32_t status; 1488 union ccb *ccb; 1489 1490 if (ch->pm_level == 0) 1491 return; 1492 1493 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1494 if ((status & AHCI_P_CMD_CPD) == 0) 1495 return; 1496 1497 if (bootverbose) { 1498 if (status & AHCI_P_CMD_CPS) { 1499 device_printf(dev, "COLD CONNECT requested\n"); 1500 } else 1501 device_printf(dev, "COLD DISCONNECT requested\n"); 1502 } 1503 ahci_reset(dev); 1504 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1505 return; 1506 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1507 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1508 xpt_free_ccb(ccb); 1509 return; 1510 } 1511 xpt_rescan(ccb); 1512} 1513 1514static void 1515ahci_notify_events(device_t dev, u_int32_t status) 1516{ 1517 struct ahci_channel *ch = device_get_softc(dev); 1518 struct cam_path *dpath; 1519 int i; 1520 1521 if (ch->caps & AHCI_CAP_SSNTF) 1522 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1523 if (bootverbose) 1524 device_printf(dev, "SNTF 0x%04x\n", status); 1525 for (i = 0; i < 16; i++) { 1526 if ((status & (1 << i)) == 0) 1527 continue; 1528 if (xpt_create_path(&dpath, NULL, 1529 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1530 xpt_async(AC_SCSI_AEN, dpath, NULL); 1531 xpt_free_path(dpath); 1532 } 1533 } 1534} 1535 1536static void 1537ahci_done(struct ahci_channel *ch, union ccb *ccb) 1538{ 1539 1540 mtx_assert(&ch->mtx, MA_OWNED); 1541 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 || 1542 ch->batch == 0) { 1543 xpt_done(ccb); 1544 return; 1545 } 1546 1547 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe); 1548} 1549 1550static void 1551ahci_ch_intr(void *arg) 1552{ 1553 device_t dev = (device_t)arg; 1554 struct ahci_channel *ch = device_get_softc(dev); 1555 uint32_t istatus; 1556 1557 /* Read interrupt statuses. */ 1558 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1559 if (istatus == 0) 1560 return; 1561 1562 mtx_lock(&ch->mtx); 1563 ahci_ch_intr_main(ch, istatus); 1564 mtx_unlock(&ch->mtx); 1565} 1566 1567static void 1568ahci_ch_intr_direct(void *arg) 1569{ 1570 device_t dev = (device_t)arg; 1571 struct ahci_channel *ch = device_get_softc(dev); 1572 struct ccb_hdr *ccb_h; 1573 uint32_t istatus; 1574 1575 /* Read interrupt statuses. */ 1576 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1577 if (istatus == 0) 1578 return; 1579 1580 mtx_lock(&ch->mtx); 1581 ch->batch = 1; 1582 ahci_ch_intr_main(ch, istatus); 1583 ch->batch = 0; 1584 mtx_unlock(&ch->mtx); 1585 while ((ccb_h = STAILQ_FIRST(&ch->doneq)) != NULL) { 1586 STAILQ_REMOVE_HEAD(&ch->doneq, sim_links.stqe); 1587 xpt_done_direct((union ccb *)ccb_h); 1588 } 1589} 1590 1591static void 1592ahci_ch_pm(void *arg) 1593{ 1594 device_t dev = (device_t)arg; 1595 struct ahci_channel *ch = device_get_softc(dev); 1596 uint32_t work; 1597 1598 if (ch->numrslots != 0) 1599 return; 1600 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1601 if (ch->pm_level == 4) 1602 work |= AHCI_P_CMD_PARTIAL; 1603 else 1604 work |= AHCI_P_CMD_SLUMBER; 1605 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1606} 1607 1608static void 1609ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus) 1610{ 1611 device_t dev = ch->dev; 1612 uint32_t cstatus, serr = 0, sntf = 0, ok, err; 1613 enum ahci_err_type et; 1614 int i, ccs, port, reset = 0; 1615 1616 /* Clear interrupt statuses. */ 1617 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1618 /* Read command statuses. */ 1619 if (ch->numtslots != 0) 1620 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1621 else 1622 cstatus = 0; 1623 if (ch->numrslots != ch->numtslots) 1624 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI); 1625 /* Read SNTF in one of possible ways. */ 1626 if ((istatus & AHCI_P_IX_SDB) && 1627 (ch->pm_present || ch->curr[0].atapi != 0)) { 1628 if (ch->caps & AHCI_CAP_SSNTF) 1629 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1630 else if (ch->fbs_enabled) { 1631 u_int8_t *fis = ch->dma.rfis + 0x58; 1632 1633 for (i = 0; i < 16; i++) { 1634 if (fis[1] & 0x80) { 1635 fis[1] &= 0x7f; 1636 sntf |= 1 << i; 1637 } 1638 fis += 256; 1639 } 1640 } else { 1641 u_int8_t *fis = ch->dma.rfis + 0x58; 1642 1643 if (fis[1] & 0x80) 1644 sntf = (1 << (fis[1] & 0x0f)); 1645 } 1646 } 1647 /* Process PHY events */ 1648 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1649 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1650 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1651 if (serr) { 1652 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1653 reset = ahci_phy_check_events(dev, serr); 1654 } 1655 } 1656 /* Process cold presence detection events */ 1657 if ((istatus & AHCI_P_IX_CPD) && !reset) 1658 ahci_cpd_check_events(dev); 1659 /* Process command errors */ 1660 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1661 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1662 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1663 >> AHCI_P_CMD_CCS_SHIFT; 1664//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1665// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1666// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1667 port = -1; 1668 if (ch->fbs_enabled) { 1669 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1670 if (fbs & AHCI_P_FBS_SDE) { 1671 port = (fbs & AHCI_P_FBS_DWE) 1672 >> AHCI_P_FBS_DWE_SHIFT; 1673 } else { 1674 for (i = 0; i < 16; i++) { 1675 if (ch->numrslotspd[i] == 0) 1676 continue; 1677 if (port == -1) 1678 port = i; 1679 else if (port != i) { 1680 port = -2; 1681 break; 1682 } 1683 } 1684 } 1685 } 1686 err = ch->rslots & cstatus; 1687 } else { 1688 ccs = 0; 1689 err = 0; 1690 port = -1; 1691 } 1692 /* Complete all successfull commands. */ 1693 ok = ch->rslots & ~cstatus; 1694 for (i = 0; i < ch->numslots; i++) { 1695 if ((ok >> i) & 1) 1696 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1697 } 1698 /* On error, complete the rest of commands with error statuses. */ 1699 if (err) { 1700 if (ch->frozen) { 1701 union ccb *fccb = ch->frozen; 1702 ch->frozen = NULL; 1703 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1704 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1705 xpt_freeze_devq(fccb->ccb_h.path, 1); 1706 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1707 } 1708 ahci_done(ch, fccb); 1709 } 1710 for (i = 0; i < ch->numslots; i++) { 1711 /* XXX: reqests in loading state. */ 1712 if (((err >> i) & 1) == 0) 1713 continue; 1714 if (port >= 0 && 1715 ch->slot[i].ccb->ccb_h.target_id != port) 1716 continue; 1717 if (istatus & AHCI_P_IX_TFE) { 1718 if (port != -2) { 1719 /* Task File Error */ 1720 if (ch->numtslotspd[ 1721 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1722 /* Untagged operation. */ 1723 if (i == ccs) 1724 et = AHCI_ERR_TFE; 1725 else 1726 et = AHCI_ERR_INNOCENT; 1727 } else { 1728 /* Tagged operation. */ 1729 et = AHCI_ERR_NCQ; 1730 } 1731 } else { 1732 et = AHCI_ERR_TFE; 1733 ch->fatalerr = 1; 1734 } 1735 } else if (istatus & AHCI_P_IX_IF) { 1736 if (ch->numtslots == 0 && i != ccs && port != -2) 1737 et = AHCI_ERR_INNOCENT; 1738 else 1739 et = AHCI_ERR_SATA; 1740 } else 1741 et = AHCI_ERR_INVALID; 1742 ahci_end_transaction(&ch->slot[i], et); 1743 } 1744 /* 1745 * We can't reinit port if there are some other 1746 * commands active, use resume to complete them. 1747 */ 1748 if (ch->rslots != 0 && !ch->recoverycmd) 1749 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1750 } 1751 /* Process NOTIFY events */ 1752 if (sntf) 1753 ahci_notify_events(dev, sntf); 1754} 1755 1756/* Must be called with channel locked. */ 1757static int 1758ahci_check_collision(device_t dev, union ccb *ccb) 1759{ 1760 struct ahci_channel *ch = device_get_softc(dev); 1761 int t = ccb->ccb_h.target_id; 1762 1763 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1764 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1765 /* Tagged command while we have no supported tag free. */ 1766 if (((~ch->oslots) & (0xffffffff >> (32 - 1767 ch->curr[t].tags))) == 0) 1768 return (1); 1769 /* If we have FBS */ 1770 if (ch->fbs_enabled) { 1771 /* Tagged command while untagged are active. */ 1772 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1773 return (1); 1774 } else { 1775 /* Tagged command while untagged are active. */ 1776 if (ch->numrslots != 0 && ch->numtslots == 0) 1777 return (1); 1778 /* Tagged command while tagged to other target is active. */ 1779 if (ch->numtslots != 0 && 1780 ch->taggedtarget != ccb->ccb_h.target_id) 1781 return (1); 1782 } 1783 } else { 1784 /* If we have FBS */ 1785 if (ch->fbs_enabled) { 1786 /* Untagged command while tagged are active. */ 1787 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1788 return (1); 1789 } else { 1790 /* Untagged command while tagged are active. */ 1791 if (ch->numrslots != 0 && ch->numtslots != 0) 1792 return (1); 1793 } 1794 } 1795 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1796 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1797 /* Atomic command while anything active. */ 1798 if (ch->numrslots != 0) 1799 return (1); 1800 } 1801 /* We have some atomic command running. */ 1802 if (ch->aslots != 0) 1803 return (1); 1804 return (0); 1805} 1806 1807/* Must be called with channel locked. */ 1808static void 1809ahci_begin_transaction(device_t dev, union ccb *ccb) 1810{ 1811 struct ahci_channel *ch = device_get_softc(dev); 1812 struct ahci_slot *slot; 1813 int tag, tags; 1814 1815 /* Choose empty slot. */ 1816 tags = ch->numslots; 1817 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1818 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1819 tags = ch->curr[ccb->ccb_h.target_id].tags; 1820 tag = ch->lastslot; 1821 while (1) { 1822 if (tag >= tags) 1823 tag = 0; 1824 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1825 break; 1826 tag++; 1827 }; 1828 ch->lastslot = tag; 1829 /* Occupy chosen slot. */ 1830 slot = &ch->slot[tag]; 1831 slot->ccb = ccb; 1832 /* Stop PM timer. */ 1833 if (ch->numrslots == 0 && ch->pm_level > 3) 1834 callout_stop(&ch->pm_timer); 1835 /* Update channel stats. */ 1836 ch->oslots |= (1 << slot->slot); 1837 ch->numrslots++; 1838 ch->numrslotspd[ccb->ccb_h.target_id]++; 1839 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1840 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1841 ch->numtslots++; 1842 ch->numtslotspd[ccb->ccb_h.target_id]++; 1843 ch->taggedtarget = ccb->ccb_h.target_id; 1844 } 1845 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1846 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1847 ch->aslots |= (1 << slot->slot); 1848 slot->dma.nsegs = 0; 1849 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1850 slot->state = AHCI_SLOT_LOADING; 1851 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 1852 ahci_dmasetprd, slot, 0); 1853 } else 1854 ahci_execute_transaction(slot); 1855} 1856 1857/* Locked by busdma engine. */ 1858static void 1859ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1860{ 1861 struct ahci_slot *slot = arg; 1862 struct ahci_channel *ch = device_get_softc(slot->dev); 1863 struct ahci_cmd_tab *ctp; 1864 struct ahci_dma_prd *prd; 1865 int i; 1866 1867 if (error) { 1868 device_printf(slot->dev, "DMA load error\n"); 1869 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1870 return; 1871 } 1872 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1873 /* Get a piece of the workspace for this request */ 1874 ctp = (struct ahci_cmd_tab *) 1875 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1876 /* Fill S/G table */ 1877 prd = &ctp->prd_tab[0]; 1878 for (i = 0; i < nsegs; i++) { 1879 prd[i].dba = htole64(segs[i].ds_addr); 1880 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1881 } 1882 slot->dma.nsegs = nsegs; 1883 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1884 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1885 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1886 ahci_execute_transaction(slot); 1887} 1888 1889/* Must be called with channel locked. */ 1890static void 1891ahci_execute_transaction(struct ahci_slot *slot) 1892{ 1893 device_t dev = slot->dev; 1894 struct ahci_channel *ch = device_get_softc(dev); 1895 struct ahci_cmd_tab *ctp; 1896 struct ahci_cmd_list *clp; 1897 union ccb *ccb = slot->ccb; 1898 int port = ccb->ccb_h.target_id & 0x0f; 1899 int fis_size, i, softreset; 1900 uint8_t *fis = ch->dma.rfis + 0x40; 1901 uint8_t val; 1902 1903 /* Get a piece of the workspace for this request */ 1904 ctp = (struct ahci_cmd_tab *) 1905 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1906 /* Setup the FIS for this request */ 1907 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1908 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1909 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1910 return; 1911 } 1912 /* Setup the command list entry */ 1913 clp = (struct ahci_cmd_list *) 1914 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1915 clp->cmd_flags = htole16( 1916 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1917 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1918 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1919 (fis_size / sizeof(u_int32_t)) | 1920 (port << 12)); 1921 clp->prd_length = htole16(slot->dma.nsegs); 1922 /* Special handling for Soft Reset command. */ 1923 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1924 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1925 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1926 softreset = 1; 1927 /* Kick controller into sane state */ 1928 ahci_stop(dev); 1929 ahci_clo(dev); 1930 ahci_start(dev, 0); 1931 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1932 } else { 1933 softreset = 2; 1934 /* Prepare FIS receive area for check. */ 1935 for (i = 0; i < 20; i++) 1936 fis[i] = 0xff; 1937 } 1938 } else 1939 softreset = 0; 1940 clp->bytecount = 0; 1941 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1942 (AHCI_CT_SIZE * slot->slot)); 1943 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1944 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1945 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1946 BUS_DMASYNC_PREREAD); 1947 /* Set ACTIVE bit for NCQ commands. */ 1948 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1949 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1950 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1951 } 1952 /* If FBS is enabled, set PMP port. */ 1953 if (ch->fbs_enabled) { 1954 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1955 (port << AHCI_P_FBS_DEV_SHIFT)); 1956 } 1957 /* Issue command to the controller. */ 1958 slot->state = AHCI_SLOT_RUNNING; 1959 ch->rslots |= (1 << slot->slot); 1960 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1961 /* Device reset commands doesn't interrupt. Poll them. */ 1962 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1963 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1964 int count, timeout = ccb->ccb_h.timeout * 100; 1965 enum ahci_err_type et = AHCI_ERR_NONE; 1966 1967 for (count = 0; count < timeout; count++) { 1968 DELAY(10); 1969 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1970 break; 1971 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1972 softreset != 1) { 1973#if 0 1974 device_printf(ch->dev, 1975 "Poll error on slot %d, TFD: %04x\n", 1976 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1977#endif 1978 et = AHCI_ERR_TFE; 1979 break; 1980 } 1981 /* Workaround for ATI SB600/SB700 chipsets. */ 1982 if (ccb->ccb_h.target_id == 15 && 1983 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1984 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1985 et = AHCI_ERR_TIMEOUT; 1986 break; 1987 } 1988 } 1989 1990 /* 1991 * Marvell HBAs with non-RAID firmware do not wait for 1992 * readiness after soft reset, so we have to wait here. 1993 * Marvell RAIDs do not have this problem, but instead 1994 * sometimes forget to update FIS receive area, breaking 1995 * this wait. 1996 */ 1997 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 && 1998 softreset == 2 && et == AHCI_ERR_NONE) { 1999 while ((val = fis[2]) & ATA_S_BUSY) { 2000 DELAY(10); 2001 if (count++ >= timeout) 2002 break; 2003 } 2004 } 2005 2006 if (timeout && (count >= timeout)) { 2007 device_printf(dev, "Poll timeout on slot %d port %d\n", 2008 slot->slot, port); 2009 device_printf(dev, "is %08x cs %08x ss %08x " 2010 "rs %08x tfd %02x serr %08x cmd %08x\n", 2011 ATA_INL(ch->r_mem, AHCI_P_IS), 2012 ATA_INL(ch->r_mem, AHCI_P_CI), 2013 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 2014 ATA_INL(ch->r_mem, AHCI_P_TFD), 2015 ATA_INL(ch->r_mem, AHCI_P_SERR), 2016 ATA_INL(ch->r_mem, AHCI_P_CMD)); 2017 et = AHCI_ERR_TIMEOUT; 2018 } 2019 2020 /* Kick controller into sane state and enable FBS. */ 2021 if (softreset == 2) 2022 ch->eslots |= (1 << slot->slot); 2023 ahci_end_transaction(slot, et); 2024 return; 2025 } 2026 /* Start command execution timeout */ 2027 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 2028 (timeout_t*)ahci_timeout, slot); 2029 return; 2030} 2031 2032/* Must be called with channel locked. */ 2033static void 2034ahci_process_timeout(device_t dev) 2035{ 2036 struct ahci_channel *ch = device_get_softc(dev); 2037 int i; 2038 2039 mtx_assert(&ch->mtx, MA_OWNED); 2040 /* Handle the rest of commands. */ 2041 for (i = 0; i < ch->numslots; i++) { 2042 /* Do we have a running request on slot? */ 2043 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2044 continue; 2045 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 2046 } 2047} 2048 2049/* Must be called with channel locked. */ 2050static void 2051ahci_rearm_timeout(device_t dev) 2052{ 2053 struct ahci_channel *ch = device_get_softc(dev); 2054 int i; 2055 2056 mtx_assert(&ch->mtx, MA_OWNED); 2057 for (i = 0; i < ch->numslots; i++) { 2058 struct ahci_slot *slot = &ch->slot[i]; 2059 2060 /* Do we have a running request on slot? */ 2061 if (slot->state < AHCI_SLOT_RUNNING) 2062 continue; 2063 if ((ch->toslots & (1 << i)) == 0) 2064 continue; 2065 callout_reset(&slot->timeout, 2066 (int)slot->ccb->ccb_h.timeout * hz / 2000, 2067 (timeout_t*)ahci_timeout, slot); 2068 } 2069} 2070 2071/* Locked by callout mechanism. */ 2072static void 2073ahci_timeout(struct ahci_slot *slot) 2074{ 2075 device_t dev = slot->dev; 2076 struct ahci_channel *ch = device_get_softc(dev); 2077 uint32_t sstatus; 2078 int ccs; 2079 int i; 2080 2081 /* Check for stale timeout. */ 2082 if (slot->state < AHCI_SLOT_RUNNING) 2083 return; 2084 2085 /* Check if slot was not being executed last time we checked. */ 2086 if (slot->state < AHCI_SLOT_EXECUTING) { 2087 /* Check if slot started executing. */ 2088 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 2089 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 2090 >> AHCI_P_CMD_CCS_SHIFT; 2091 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 2092 ch->fbs_enabled || ch->wrongccs) 2093 slot->state = AHCI_SLOT_EXECUTING; 2094 else if ((ch->rslots & (1 << ccs)) == 0) { 2095 ch->wrongccs = 1; 2096 slot->state = AHCI_SLOT_EXECUTING; 2097 } 2098 2099 callout_reset(&slot->timeout, 2100 (int)slot->ccb->ccb_h.timeout * hz / 2000, 2101 (timeout_t*)ahci_timeout, slot); 2102 return; 2103 } 2104 2105 device_printf(dev, "Timeout on slot %d port %d\n", 2106 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 2107 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 2108 "serr %08x cmd %08x\n", 2109 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 2110 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 2111 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 2112 ATA_INL(ch->r_mem, AHCI_P_CMD)); 2113 2114 /* Handle frozen command. */ 2115 if (ch->frozen) { 2116 union ccb *fccb = ch->frozen; 2117 ch->frozen = NULL; 2118 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2119 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2120 xpt_freeze_devq(fccb->ccb_h.path, 1); 2121 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2122 } 2123 ahci_done(ch, fccb); 2124 } 2125 if (!ch->fbs_enabled && !ch->wrongccs) { 2126 /* Without FBS we know real timeout source. */ 2127 ch->fatalerr = 1; 2128 /* Handle command with timeout. */ 2129 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 2130 /* Handle the rest of commands. */ 2131 for (i = 0; i < ch->numslots; i++) { 2132 /* Do we have a running request on slot? */ 2133 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2134 continue; 2135 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2136 } 2137 } else { 2138 /* With FBS we wait for other commands timeout and pray. */ 2139 if (ch->toslots == 0) 2140 xpt_freeze_simq(ch->sim, 1); 2141 ch->toslots |= (1 << slot->slot); 2142 if ((ch->rslots & ~ch->toslots) == 0) 2143 ahci_process_timeout(dev); 2144 else 2145 device_printf(dev, " ... waiting for slots %08x\n", 2146 ch->rslots & ~ch->toslots); 2147 } 2148} 2149 2150/* Must be called with channel locked. */ 2151static void 2152ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 2153{ 2154 device_t dev = slot->dev; 2155 struct ahci_channel *ch = device_get_softc(dev); 2156 union ccb *ccb = slot->ccb; 2157 struct ahci_cmd_list *clp; 2158 int lastto; 2159 uint32_t sig; 2160 2161 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 2162 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2163 clp = (struct ahci_cmd_list *) 2164 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 2165 /* Read result registers to the result struct 2166 * May be incorrect if several commands finished same time, 2167 * so read only when sure or have to. 2168 */ 2169 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2170 struct ata_res *res = &ccb->ataio.res; 2171 2172 if ((et == AHCI_ERR_TFE) || 2173 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 2174 u_int8_t *fis = ch->dma.rfis + 0x40; 2175 2176 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2177 BUS_DMASYNC_POSTREAD); 2178 if (ch->fbs_enabled) { 2179 fis += ccb->ccb_h.target_id * 256; 2180 res->status = fis[2]; 2181 res->error = fis[3]; 2182 } else { 2183 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2184 2185 res->status = tfd; 2186 res->error = tfd >> 8; 2187 } 2188 res->lba_low = fis[4]; 2189 res->lba_mid = fis[5]; 2190 res->lba_high = fis[6]; 2191 res->device = fis[7]; 2192 res->lba_low_exp = fis[8]; 2193 res->lba_mid_exp = fis[9]; 2194 res->lba_high_exp = fis[10]; 2195 res->sector_count = fis[12]; 2196 res->sector_count_exp = fis[13]; 2197 2198 /* 2199 * Some weird controllers do not return signature in 2200 * FIS receive area. Read it from PxSIG register. 2201 */ 2202 if ((ch->quirks & AHCI_Q_ALTSIG) && 2203 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2204 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2205 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2206 res->lba_high = sig >> 24; 2207 res->lba_mid = sig >> 16; 2208 res->lba_low = sig >> 8; 2209 res->sector_count = sig; 2210 } 2211 } else 2212 bzero(res, sizeof(*res)); 2213 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2214 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2215 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2216 ccb->ataio.resid = 2217 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2218 } 2219 } else { 2220 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2221 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2222 ccb->csio.resid = 2223 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2224 } 2225 } 2226 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2227 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2228 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2229 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2230 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2231 } 2232 if (et != AHCI_ERR_NONE) 2233 ch->eslots |= (1 << slot->slot); 2234 /* In case of error, freeze device for proper recovery. */ 2235 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2236 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2237 xpt_freeze_devq(ccb->ccb_h.path, 1); 2238 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2239 } 2240 /* Set proper result status. */ 2241 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2242 switch (et) { 2243 case AHCI_ERR_NONE: 2244 ccb->ccb_h.status |= CAM_REQ_CMP; 2245 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2246 ccb->csio.scsi_status = SCSI_STATUS_OK; 2247 break; 2248 case AHCI_ERR_INVALID: 2249 ch->fatalerr = 1; 2250 ccb->ccb_h.status |= CAM_REQ_INVALID; 2251 break; 2252 case AHCI_ERR_INNOCENT: 2253 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2254 break; 2255 case AHCI_ERR_TFE: 2256 case AHCI_ERR_NCQ: 2257 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2258 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2259 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2260 } else { 2261 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2262 } 2263 break; 2264 case AHCI_ERR_SATA: 2265 ch->fatalerr = 1; 2266 if (!ch->recoverycmd) { 2267 xpt_freeze_simq(ch->sim, 1); 2268 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2269 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2270 } 2271 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2272 break; 2273 case AHCI_ERR_TIMEOUT: 2274 if (!ch->recoverycmd) { 2275 xpt_freeze_simq(ch->sim, 1); 2276 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2277 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2278 } 2279 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2280 break; 2281 default: 2282 ch->fatalerr = 1; 2283 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2284 } 2285 /* Free slot. */ 2286 ch->oslots &= ~(1 << slot->slot); 2287 ch->rslots &= ~(1 << slot->slot); 2288 ch->aslots &= ~(1 << slot->slot); 2289 slot->state = AHCI_SLOT_EMPTY; 2290 slot->ccb = NULL; 2291 /* Update channel stats. */ 2292 ch->numrslots--; 2293 ch->numrslotspd[ccb->ccb_h.target_id]--; 2294 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2295 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2296 ch->numtslots--; 2297 ch->numtslotspd[ccb->ccb_h.target_id]--; 2298 } 2299 /* Cancel timeout state if request completed normally. */ 2300 if (et != AHCI_ERR_TIMEOUT) { 2301 lastto = (ch->toslots == (1 << slot->slot)); 2302 ch->toslots &= ~(1 << slot->slot); 2303 if (lastto) 2304 xpt_release_simq(ch->sim, TRUE); 2305 } 2306 /* If it was first request of reset sequence and there is no error, 2307 * proceed to second request. */ 2308 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2309 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2310 (ccb->ataio.cmd.control & ATA_A_RESET) && 2311 et == AHCI_ERR_NONE) { 2312 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2313 ahci_begin_transaction(dev, ccb); 2314 return; 2315 } 2316 /* If it was our READ LOG command - process it. */ 2317 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2318 ahci_process_read_log(dev, ccb); 2319 /* If it was our REQUEST SENSE command - process it. */ 2320 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2321 ahci_process_request_sense(dev, ccb); 2322 /* If it was NCQ or ATAPI command error, put result on hold. */ 2323 } else if (et == AHCI_ERR_NCQ || 2324 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2325 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2326 ch->hold[slot->slot] = ccb; 2327 ch->numhslots++; 2328 } else 2329 ahci_done(ch, ccb); 2330 /* If we have no other active commands, ... */ 2331 if (ch->rslots == 0) { 2332 /* if there was fatal error - reset port. */ 2333 if (ch->toslots != 0 || ch->fatalerr) { 2334 ahci_reset(dev); 2335 } else { 2336 /* if we have slots in error, we can reinit port. */ 2337 if (ch->eslots != 0) { 2338 ahci_stop(dev); 2339 ahci_clo(dev); 2340 ahci_start(dev, 1); 2341 } 2342 /* if there commands on hold, we can do READ LOG. */ 2343 if (!ch->recoverycmd && ch->numhslots) 2344 ahci_issue_recovery(dev); 2345 } 2346 /* If all the rest of commands are in timeout - give them chance. */ 2347 } else if ((ch->rslots & ~ch->toslots) == 0 && 2348 et != AHCI_ERR_TIMEOUT) 2349 ahci_rearm_timeout(dev); 2350 /* Unfreeze frozen command. */ 2351 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2352 union ccb *fccb = ch->frozen; 2353 ch->frozen = NULL; 2354 ahci_begin_transaction(dev, fccb); 2355 xpt_release_simq(ch->sim, TRUE); 2356 } 2357 /* Start PM timer. */ 2358 if (ch->numrslots == 0 && ch->pm_level > 3 && 2359 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2360 callout_schedule(&ch->pm_timer, 2361 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2362 } 2363} 2364 2365static void 2366ahci_issue_recovery(device_t dev) 2367{ 2368 struct ahci_channel *ch = device_get_softc(dev); 2369 union ccb *ccb; 2370 struct ccb_ataio *ataio; 2371 struct ccb_scsiio *csio; 2372 int i; 2373 2374 /* Find some held command. */ 2375 for (i = 0; i < ch->numslots; i++) { 2376 if (ch->hold[i]) 2377 break; 2378 } 2379 ccb = xpt_alloc_ccb_nowait(); 2380 if (ccb == NULL) { 2381 device_printf(dev, "Unable to allocate recovery command\n"); 2382completeall: 2383 /* We can't do anything -- complete held commands. */ 2384 for (i = 0; i < ch->numslots; i++) { 2385 if (ch->hold[i] == NULL) 2386 continue; 2387 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2388 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2389 ahci_done(ch, ch->hold[i]); 2390 ch->hold[i] = NULL; 2391 ch->numhslots--; 2392 } 2393 ahci_reset(dev); 2394 return; 2395 } 2396 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2397 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2398 /* READ LOG */ 2399 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2400 ccb->ccb_h.func_code = XPT_ATA_IO; 2401 ccb->ccb_h.flags = CAM_DIR_IN; 2402 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2403 ataio = &ccb->ataio; 2404 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2405 if (ataio->data_ptr == NULL) { 2406 xpt_free_ccb(ccb); 2407 device_printf(dev, 2408 "Unable to allocate memory for READ LOG command\n"); 2409 goto completeall; 2410 } 2411 ataio->dxfer_len = 512; 2412 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2413 ataio->cmd.flags = CAM_ATAIO_48BIT; 2414 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2415 ataio->cmd.sector_count = 1; 2416 ataio->cmd.sector_count_exp = 0; 2417 ataio->cmd.lba_low = 0x10; 2418 ataio->cmd.lba_mid = 0; 2419 ataio->cmd.lba_mid_exp = 0; 2420 } else { 2421 /* REQUEST SENSE */ 2422 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2423 ccb->ccb_h.recovery_slot = i; 2424 ccb->ccb_h.func_code = XPT_SCSI_IO; 2425 ccb->ccb_h.flags = CAM_DIR_IN; 2426 ccb->ccb_h.status = 0; 2427 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2428 csio = &ccb->csio; 2429 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2430 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2431 csio->cdb_len = 6; 2432 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2433 csio->cdb_io.cdb_bytes[0] = 0x03; 2434 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2435 } 2436 /* Freeze SIM while doing recovery. */ 2437 ch->recoverycmd = 1; 2438 xpt_freeze_simq(ch->sim, 1); 2439 ahci_begin_transaction(dev, ccb); 2440} 2441 2442static void 2443ahci_process_read_log(device_t dev, union ccb *ccb) 2444{ 2445 struct ahci_channel *ch = device_get_softc(dev); 2446 uint8_t *data; 2447 struct ata_res *res; 2448 int i; 2449 2450 ch->recoverycmd = 0; 2451 2452 data = ccb->ataio.data_ptr; 2453 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2454 (data[0] & 0x80) == 0) { 2455 for (i = 0; i < ch->numslots; i++) { 2456 if (!ch->hold[i]) 2457 continue; 2458 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2459 continue; 2460 if ((data[0] & 0x1F) == i) { 2461 res = &ch->hold[i]->ataio.res; 2462 res->status = data[2]; 2463 res->error = data[3]; 2464 res->lba_low = data[4]; 2465 res->lba_mid = data[5]; 2466 res->lba_high = data[6]; 2467 res->device = data[7]; 2468 res->lba_low_exp = data[8]; 2469 res->lba_mid_exp = data[9]; 2470 res->lba_high_exp = data[10]; 2471 res->sector_count = data[12]; 2472 res->sector_count_exp = data[13]; 2473 } else { 2474 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2475 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2476 } 2477 ahci_done(ch, ch->hold[i]); 2478 ch->hold[i] = NULL; 2479 ch->numhslots--; 2480 } 2481 } else { 2482 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2483 device_printf(dev, "Error while READ LOG EXT\n"); 2484 else if ((data[0] & 0x80) == 0) { 2485 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2486 } 2487 for (i = 0; i < ch->numslots; i++) { 2488 if (!ch->hold[i]) 2489 continue; 2490 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2491 continue; 2492 ahci_done(ch, ch->hold[i]); 2493 ch->hold[i] = NULL; 2494 ch->numhslots--; 2495 } 2496 } 2497 free(ccb->ataio.data_ptr, M_AHCI); 2498 xpt_free_ccb(ccb); 2499 xpt_release_simq(ch->sim, TRUE); 2500} 2501 2502static void 2503ahci_process_request_sense(device_t dev, union ccb *ccb) 2504{ 2505 struct ahci_channel *ch = device_get_softc(dev); 2506 int i; 2507 2508 ch->recoverycmd = 0; 2509 2510 i = ccb->ccb_h.recovery_slot; 2511 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2512 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2513 } else { 2514 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2515 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2516 } 2517 ahci_done(ch, ch->hold[i]); 2518 ch->hold[i] = NULL; 2519 ch->numhslots--; 2520 xpt_free_ccb(ccb); 2521 xpt_release_simq(ch->sim, TRUE); 2522} 2523 2524static void 2525ahci_start(device_t dev, int fbs) 2526{ 2527 struct ahci_channel *ch = device_get_softc(dev); 2528 u_int32_t cmd; 2529 2530 /* Clear SATA error register */ 2531 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2532 /* Clear any interrupts pending on this channel */ 2533 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2534 /* Configure FIS-based switching if supported. */ 2535 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2536 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2537 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2538 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2539 } 2540 /* Start operations on this channel */ 2541 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2542 cmd &= ~AHCI_P_CMD_PMA; 2543 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2544 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2545} 2546 2547static void 2548ahci_stop(device_t dev) 2549{ 2550 struct ahci_channel *ch = device_get_softc(dev); 2551 u_int32_t cmd; 2552 int timeout; 2553 2554 /* Kill all activity on this channel */ 2555 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2556 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2557 /* Wait for activity stop. */ 2558 timeout = 0; 2559 do { 2560 DELAY(10); 2561 if (timeout++ > 50000) { 2562 device_printf(dev, "stopping AHCI engine failed\n"); 2563 break; 2564 } 2565 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2566 ch->eslots = 0; 2567} 2568 2569static void 2570ahci_clo(device_t dev) 2571{ 2572 struct ahci_channel *ch = device_get_softc(dev); 2573 u_int32_t cmd; 2574 int timeout; 2575 2576 /* Issue Command List Override if supported */ 2577 if (ch->caps & AHCI_CAP_SCLO) { 2578 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2579 cmd |= AHCI_P_CMD_CLO; 2580 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2581 timeout = 0; 2582 do { 2583 DELAY(10); 2584 if (timeout++ > 50000) { 2585 device_printf(dev, "executing CLO failed\n"); 2586 break; 2587 } 2588 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2589 } 2590} 2591 2592static void 2593ahci_stop_fr(device_t dev) 2594{ 2595 struct ahci_channel *ch = device_get_softc(dev); 2596 u_int32_t cmd; 2597 int timeout; 2598 2599 /* Kill all FIS reception on this channel */ 2600 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2601 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2602 /* Wait for FIS reception stop. */ 2603 timeout = 0; 2604 do { 2605 DELAY(10); 2606 if (timeout++ > 50000) { 2607 device_printf(dev, "stopping AHCI FR engine failed\n"); 2608 break; 2609 } 2610 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2611} 2612 2613static void 2614ahci_start_fr(device_t dev) 2615{ 2616 struct ahci_channel *ch = device_get_softc(dev); 2617 u_int32_t cmd; 2618 2619 /* Start FIS reception on this channel */ 2620 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2621 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2622} 2623 2624static int 2625ahci_wait_ready(device_t dev, int t, int t0) 2626{ 2627 struct ahci_channel *ch = device_get_softc(dev); 2628 int timeout = 0; 2629 uint32_t val; 2630 2631 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2632 (ATA_S_BUSY | ATA_S_DRQ)) { 2633 if (timeout > t) { 2634 if (t != 0) { 2635 device_printf(dev, 2636 "AHCI reset: device not ready after %dms " 2637 "(tfd = %08x)\n", 2638 MAX(t, 0) + t0, val); 2639 } 2640 return (EBUSY); 2641 } 2642 DELAY(1000); 2643 timeout++; 2644 } 2645 if (bootverbose) 2646 device_printf(dev, "AHCI reset: device ready after %dms\n", 2647 timeout + t0); 2648 return (0); 2649} 2650 2651static void 2652ahci_reset_to(void *arg) 2653{ 2654 device_t dev = arg; 2655 struct ahci_channel *ch = device_get_softc(dev); 2656 2657 if (ch->resetting == 0) 2658 return; 2659 ch->resetting--; 2660 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2661 (310 - ch->resetting) * 100) == 0) { 2662 ch->resetting = 0; 2663 ahci_start(dev, 1); 2664 xpt_release_simq(ch->sim, TRUE); 2665 return; 2666 } 2667 if (ch->resetting == 0) { 2668 ahci_clo(dev); 2669 ahci_start(dev, 1); 2670 xpt_release_simq(ch->sim, TRUE); 2671 return; 2672 } 2673 callout_schedule(&ch->reset_timer, hz / 10); 2674} 2675 2676static void 2677ahci_reset(device_t dev) 2678{ 2679 struct ahci_channel *ch = device_get_softc(dev); 2680 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2681 int i; 2682 2683 xpt_freeze_simq(ch->sim, 1); 2684 if (bootverbose) 2685 device_printf(dev, "AHCI reset...\n"); 2686 /* Forget about previous reset. */ 2687 if (ch->resetting) { 2688 ch->resetting = 0; 2689 callout_stop(&ch->reset_timer); 2690 xpt_release_simq(ch->sim, TRUE); 2691 } 2692 /* Requeue freezed command. */ 2693 if (ch->frozen) { 2694 union ccb *fccb = ch->frozen; 2695 ch->frozen = NULL; 2696 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2697 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2698 xpt_freeze_devq(fccb->ccb_h.path, 1); 2699 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2700 } 2701 ahci_done(ch, fccb); 2702 } 2703 /* Kill the engine and requeue all running commands. */ 2704 ahci_stop(dev); 2705 for (i = 0; i < ch->numslots; i++) { 2706 /* Do we have a running request on slot? */ 2707 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2708 continue; 2709 /* XXX; Commands in loading state. */ 2710 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2711 } 2712 for (i = 0; i < ch->numslots; i++) { 2713 if (!ch->hold[i]) 2714 continue; 2715 ahci_done(ch, ch->hold[i]); 2716 ch->hold[i] = NULL; 2717 ch->numhslots--; 2718 } 2719 if (ch->toslots != 0) 2720 xpt_release_simq(ch->sim, TRUE); 2721 ch->eslots = 0; 2722 ch->toslots = 0; 2723 ch->wrongccs = 0; 2724 ch->fatalerr = 0; 2725 /* Tell the XPT about the event */ 2726 xpt_async(AC_BUS_RESET, ch->path, NULL); 2727 /* Disable port interrupts */ 2728 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2729 /* Reset and reconnect PHY, */ 2730 if (!ahci_sata_phy_reset(dev)) { 2731 if (bootverbose) 2732 device_printf(dev, 2733 "AHCI reset: device not found\n"); 2734 ch->devices = 0; 2735 /* Enable wanted port interrupts */ 2736 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2737 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2738 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2739 xpt_release_simq(ch->sim, TRUE); 2740 return; 2741 } 2742 if (bootverbose) 2743 device_printf(dev, "AHCI reset: device found\n"); 2744 /* Wait for clearing busy status. */ 2745 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2746 if (dumping) 2747 ahci_clo(dev); 2748 else 2749 ch->resetting = 310; 2750 } 2751 ch->devices = 1; 2752 /* Enable wanted port interrupts */ 2753 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2754 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2755 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2756 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2757 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2758 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2759 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2760 if (ch->resetting) 2761 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2762 else { 2763 ahci_start(dev, 1); 2764 xpt_release_simq(ch->sim, TRUE); 2765 } 2766} 2767 2768static int 2769ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2770{ 2771 struct ahci_channel *ch = device_get_softc(dev); 2772 u_int8_t *fis = &ctp->cfis[0]; 2773 2774 bzero(ctp->cfis, 16); 2775 fis[0] = 0x27; /* host to device */ 2776 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2777 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2778 fis[1] |= 0x80; 2779 fis[2] = ATA_PACKET_CMD; 2780 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2781 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2782 fis[3] = ATA_F_DMA; 2783 else { 2784 fis[5] = ccb->csio.dxfer_len; 2785 fis[6] = ccb->csio.dxfer_len >> 8; 2786 } 2787 fis[7] = ATA_D_LBA; 2788 fis[15] = ATA_A_4BIT; 2789 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2790 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2791 ctp->acmd, ccb->csio.cdb_len); 2792 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 2793 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2794 fis[1] |= 0x80; 2795 fis[2] = ccb->ataio.cmd.command; 2796 fis[3] = ccb->ataio.cmd.features; 2797 fis[4] = ccb->ataio.cmd.lba_low; 2798 fis[5] = ccb->ataio.cmd.lba_mid; 2799 fis[6] = ccb->ataio.cmd.lba_high; 2800 fis[7] = ccb->ataio.cmd.device; 2801 fis[8] = ccb->ataio.cmd.lba_low_exp; 2802 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2803 fis[10] = ccb->ataio.cmd.lba_high_exp; 2804 fis[11] = ccb->ataio.cmd.features_exp; 2805 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2806 fis[12] = tag << 3; 2807 fis[13] = 0; 2808 } else { 2809 fis[12] = ccb->ataio.cmd.sector_count; 2810 fis[13] = ccb->ataio.cmd.sector_count_exp; 2811 } 2812 fis[15] = ATA_A_4BIT; 2813 } else { 2814 fis[15] = ccb->ataio.cmd.control; 2815 } 2816 return (20); 2817} 2818 2819static int 2820ahci_sata_connect(struct ahci_channel *ch) 2821{ 2822 u_int32_t status; 2823 int timeout, found = 0; 2824 2825 /* Wait up to 100ms for "connect well" */ 2826 for (timeout = 0; timeout < 1000 ; timeout++) { 2827 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2828 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2829 found = 1; 2830 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2831 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2832 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2833 break; 2834 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2835 if (bootverbose) { 2836 device_printf(ch->dev, "SATA offline status=%08x\n", 2837 status); 2838 } 2839 return (0); 2840 } 2841 if (found == 0 && timeout >= 100) 2842 break; 2843 DELAY(100); 2844 } 2845 if (timeout >= 1000 || !found) { 2846 if (bootverbose) { 2847 device_printf(ch->dev, 2848 "SATA connect timeout time=%dus status=%08x\n", 2849 timeout * 100, status); 2850 } 2851 return (0); 2852 } 2853 if (bootverbose) { 2854 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2855 timeout * 100, status); 2856 } 2857 /* Clear SATA error register */ 2858 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2859 return (1); 2860} 2861 2862static int 2863ahci_sata_phy_reset(device_t dev) 2864{ 2865 struct ahci_channel *ch = device_get_softc(dev); 2866 int sata_rev; 2867 uint32_t val; 2868 2869 if (ch->listening) { 2870 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2871 val |= AHCI_P_CMD_SUD; 2872 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2873 ch->listening = 0; 2874 } 2875 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2876 if (sata_rev == 1) 2877 val = ATA_SC_SPD_SPEED_GEN1; 2878 else if (sata_rev == 2) 2879 val = ATA_SC_SPD_SPEED_GEN2; 2880 else if (sata_rev == 3) 2881 val = ATA_SC_SPD_SPEED_GEN3; 2882 else 2883 val = 0; 2884 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2885 ATA_SC_DET_RESET | val | 2886 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2887 DELAY(1000); 2888 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2889 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2890 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2891 if (!ahci_sata_connect(ch)) { 2892 if (ch->caps & AHCI_CAP_SSS) { 2893 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2894 val &= ~AHCI_P_CMD_SUD; 2895 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2896 ch->listening = 1; 2897 } else if (ch->pm_level > 0) 2898 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2899 return (0); 2900 } 2901 return (1); 2902} 2903 2904static int 2905ahci_check_ids(device_t dev, union ccb *ccb) 2906{ 2907 struct ahci_channel *ch = device_get_softc(dev); 2908 2909 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2910 ccb->ccb_h.status = CAM_TID_INVALID; 2911 ahci_done(ch, ccb); 2912 return (-1); 2913 } 2914 if (ccb->ccb_h.target_lun != 0) { 2915 ccb->ccb_h.status = CAM_LUN_INVALID; 2916 ahci_done(ch, ccb); 2917 return (-1); 2918 } 2919 return (0); 2920} 2921 2922static void 2923ahciaction(struct cam_sim *sim, union ccb *ccb) 2924{ 2925 device_t dev, parent; 2926 struct ahci_channel *ch; 2927 2928 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2929 ccb->ccb_h.func_code)); 2930 2931 ch = (struct ahci_channel *)cam_sim_softc(sim); 2932 dev = ch->dev; 2933 switch (ccb->ccb_h.func_code) { 2934 /* Common cases first */ 2935 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2936 case XPT_SCSI_IO: 2937 if (ahci_check_ids(dev, ccb)) 2938 return; 2939 if (ch->devices == 0 || 2940 (ch->pm_present == 0 && 2941 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2942 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2943 break; 2944 } 2945 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2946 /* Check for command collision. */ 2947 if (ahci_check_collision(dev, ccb)) { 2948 /* Freeze command. */ 2949 ch->frozen = ccb; 2950 /* We have only one frozen slot, so freeze simq also. */ 2951 xpt_freeze_simq(ch->sim, 1); 2952 return; 2953 } 2954 ahci_begin_transaction(dev, ccb); 2955 return; 2956 case XPT_EN_LUN: /* Enable LUN as a target */ 2957 case XPT_TARGET_IO: /* Execute target I/O request */ 2958 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2959 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2960 case XPT_ABORT: /* Abort the specified CCB */ 2961 /* XXX Implement */ 2962 ccb->ccb_h.status = CAM_REQ_INVALID; 2963 break; 2964 case XPT_SET_TRAN_SETTINGS: 2965 { 2966 struct ccb_trans_settings *cts = &ccb->cts; 2967 struct ahci_device *d; 2968 2969 if (ahci_check_ids(dev, ccb)) 2970 return; 2971 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2972 d = &ch->curr[ccb->ccb_h.target_id]; 2973 else 2974 d = &ch->user[ccb->ccb_h.target_id]; 2975 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2976 d->revision = cts->xport_specific.sata.revision; 2977 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2978 d->mode = cts->xport_specific.sata.mode; 2979 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2980 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2981 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2982 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2983 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2984 ch->pm_present = cts->xport_specific.sata.pm_present; 2985 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2986 d->atapi = cts->xport_specific.sata.atapi; 2987 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2988 d->caps = cts->xport_specific.sata.caps; 2989 ccb->ccb_h.status = CAM_REQ_CMP; 2990 break; 2991 } 2992 case XPT_GET_TRAN_SETTINGS: 2993 /* Get default/user set transfer settings for the target */ 2994 { 2995 struct ccb_trans_settings *cts = &ccb->cts; 2996 struct ahci_device *d; 2997 uint32_t status; 2998 2999 if (ahci_check_ids(dev, ccb)) 3000 return; 3001 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 3002 d = &ch->curr[ccb->ccb_h.target_id]; 3003 else 3004 d = &ch->user[ccb->ccb_h.target_id]; 3005 cts->protocol = PROTO_UNSPECIFIED; 3006 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 3007 cts->transport = XPORT_SATA; 3008 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 3009 cts->proto_specific.valid = 0; 3010 cts->xport_specific.sata.valid = 0; 3011 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 3012 (ccb->ccb_h.target_id == 15 || 3013 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 3014 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 3015 if (status & 0x0f0) { 3016 cts->xport_specific.sata.revision = 3017 (status & 0x0f0) >> 4; 3018 cts->xport_specific.sata.valid |= 3019 CTS_SATA_VALID_REVISION; 3020 } 3021 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 3022 if (ch->pm_level) { 3023 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 3024 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 3025 if (ch->caps2 & AHCI_CAP2_APST) 3026 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 3027 } 3028 if ((ch->caps & AHCI_CAP_SNCQ) && 3029 (ch->quirks & AHCI_Q_NOAA) == 0) 3030 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 3031 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 3032 cts->xport_specific.sata.caps &= 3033 ch->user[ccb->ccb_h.target_id].caps; 3034 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 3035 } else { 3036 cts->xport_specific.sata.revision = d->revision; 3037 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 3038 cts->xport_specific.sata.caps = d->caps; 3039 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 3040 } 3041 cts->xport_specific.sata.mode = d->mode; 3042 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 3043 cts->xport_specific.sata.bytecount = d->bytecount; 3044 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 3045 cts->xport_specific.sata.pm_present = ch->pm_present; 3046 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 3047 cts->xport_specific.sata.tags = d->tags; 3048 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 3049 cts->xport_specific.sata.atapi = d->atapi; 3050 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 3051 ccb->ccb_h.status = CAM_REQ_CMP; 3052 break; 3053 } 3054 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 3055 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 3056 ahci_reset(dev); 3057 ccb->ccb_h.status = CAM_REQ_CMP; 3058 break; 3059 case XPT_TERM_IO: /* Terminate the I/O process */ 3060 /* XXX Implement */ 3061 ccb->ccb_h.status = CAM_REQ_INVALID; 3062 break; 3063 case XPT_PATH_INQ: /* Path routing inquiry */ 3064 { 3065 struct ccb_pathinq *cpi = &ccb->cpi; 3066 3067 parent = device_get_parent(dev); 3068 cpi->version_num = 1; /* XXX??? */ 3069 cpi->hba_inquiry = PI_SDTR_ABLE; 3070 if (ch->caps & AHCI_CAP_SNCQ) 3071 cpi->hba_inquiry |= PI_TAG_ABLE; 3072 if (ch->caps & AHCI_CAP_SPM) 3073 cpi->hba_inquiry |= PI_SATAPM; 3074 cpi->target_sprt = 0; 3075 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 3076 cpi->hba_eng_cnt = 0; 3077 if (ch->caps & AHCI_CAP_SPM) 3078 cpi->max_target = 15; 3079 else 3080 cpi->max_target = 0; 3081 cpi->max_lun = 0; 3082 cpi->initiator_id = 0; 3083 cpi->bus_id = cam_sim_bus(sim); 3084 cpi->base_transfer_speed = 150000; 3085 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3086 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 3087 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 3088 cpi->unit_number = cam_sim_unit(sim); 3089 cpi->transport = XPORT_SATA; 3090 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 3091 cpi->protocol = PROTO_ATA; 3092 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 3093 cpi->maxio = MAXPHYS; 3094 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 3095 if (pci_get_devid(parent) == 0x43801002) 3096 cpi->maxio = min(cpi->maxio, 128 * 512); 3097 cpi->hba_vendor = pci_get_vendor(parent); 3098 cpi->hba_device = pci_get_device(parent); 3099 cpi->hba_subvendor = pci_get_subvendor(parent); 3100 cpi->hba_subdevice = pci_get_subdevice(parent); 3101 cpi->ccb_h.status = CAM_REQ_CMP; 3102 break; 3103 } 3104 default: 3105 ccb->ccb_h.status = CAM_REQ_INVALID; 3106 break; 3107 } 3108 ahci_done(ch, ccb); 3109} 3110 3111static void 3112ahcipoll(struct cam_sim *sim) 3113{ 3114 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 3115 uint32_t istatus; 3116 3117 /* Read interrupt statuses and process if any. */ 3118 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 3119 if (istatus != 0) 3120 ahci_ch_intr_main(ch, istatus); 3121 if (ch->resetting != 0 && 3122 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 3123 ch->resetpolldiv = 1000; 3124 ahci_reset_to(ch->dev); 3125 } 3126} 3127