if_age.c revision 219902
1/*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/age/if_age.c 219902 2011-03-23 13:10:15Z jhb $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/malloc.h> 39#include <sys/mbuf.h> 40#include <sys/rman.h> 41#include <sys/module.h> 42#include <sys/queue.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <sys/taskqueue.h> 47 48#include <net/bpf.h> 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55#include <net/if_vlan_var.h> 56 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/ip.h> 60#include <netinet/tcp.h> 61 62#include <dev/mii/mii.h> 63#include <dev/mii/miivar.h> 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67 68#include <machine/bus.h> 69#include <machine/in_cksum.h> 70 71#include <dev/age/if_agereg.h> 72#include <dev/age/if_agevar.h> 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77#define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 78 79MODULE_DEPEND(age, pci, 1, 1, 1); 80MODULE_DEPEND(age, ether, 1, 1, 1); 81MODULE_DEPEND(age, miibus, 1, 1, 1); 82 83/* Tunables. */ 84static int msi_disable = 0; 85static int msix_disable = 0; 86TUNABLE_INT("hw.age.msi_disable", &msi_disable); 87TUNABLE_INT("hw.age.msix_disable", &msix_disable); 88 89/* 90 * Devices supported by this driver. 91 */ 92static struct age_dev { 93 uint16_t age_vendorid; 94 uint16_t age_deviceid; 95 const char *age_name; 96} age_devs[] = { 97 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 98 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 99}; 100 101static int age_miibus_readreg(device_t, int, int); 102static int age_miibus_writereg(device_t, int, int, int); 103static void age_miibus_statchg(device_t); 104static void age_mediastatus(struct ifnet *, struct ifmediareq *); 105static int age_mediachange(struct ifnet *); 106static int age_probe(device_t); 107static void age_get_macaddr(struct age_softc *); 108static void age_phy_reset(struct age_softc *); 109static int age_attach(device_t); 110static int age_detach(device_t); 111static void age_sysctl_node(struct age_softc *); 112static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113static int age_check_boundary(struct age_softc *); 114static int age_dma_alloc(struct age_softc *); 115static void age_dma_free(struct age_softc *); 116static int age_shutdown(device_t); 117static void age_setwol(struct age_softc *); 118static int age_suspend(device_t); 119static int age_resume(device_t); 120static int age_encap(struct age_softc *, struct mbuf **); 121static void age_start(struct ifnet *); 122static void age_start_locked(struct ifnet *); 123static void age_watchdog(struct age_softc *); 124static int age_ioctl(struct ifnet *, u_long, caddr_t); 125static void age_mac_config(struct age_softc *); 126static void age_link_task(void *, int); 127static void age_stats_update(struct age_softc *); 128static int age_intr(void *); 129static void age_int_task(void *, int); 130static void age_txintr(struct age_softc *, int); 131static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 132static int age_rxintr(struct age_softc *, int, int); 133static void age_tick(void *); 134static void age_reset(struct age_softc *); 135static void age_init(void *); 136static void age_init_locked(struct age_softc *); 137static void age_stop(struct age_softc *); 138static void age_stop_txmac(struct age_softc *); 139static void age_stop_rxmac(struct age_softc *); 140static void age_init_tx_ring(struct age_softc *); 141static int age_init_rx_ring(struct age_softc *); 142static void age_init_rr_ring(struct age_softc *); 143static void age_init_cmb_block(struct age_softc *); 144static void age_init_smb_block(struct age_softc *); 145static int age_newbuf(struct age_softc *, struct age_rxdesc *); 146static void age_rxvlan(struct age_softc *); 147static void age_rxfilter(struct age_softc *); 148static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 149static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 151static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 152 153 154static device_method_t age_methods[] = { 155 /* Device interface. */ 156 DEVMETHOD(device_probe, age_probe), 157 DEVMETHOD(device_attach, age_attach), 158 DEVMETHOD(device_detach, age_detach), 159 DEVMETHOD(device_shutdown, age_shutdown), 160 DEVMETHOD(device_suspend, age_suspend), 161 DEVMETHOD(device_resume, age_resume), 162 163 /* MII interface. */ 164 DEVMETHOD(miibus_readreg, age_miibus_readreg), 165 DEVMETHOD(miibus_writereg, age_miibus_writereg), 166 DEVMETHOD(miibus_statchg, age_miibus_statchg), 167 168 { NULL, NULL } 169}; 170 171static driver_t age_driver = { 172 "age", 173 age_methods, 174 sizeof(struct age_softc) 175}; 176 177static devclass_t age_devclass; 178 179DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0); 180DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); 181 182static struct resource_spec age_res_spec_mem[] = { 183 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 184 { -1, 0, 0 } 185}; 186 187static struct resource_spec age_irq_spec_legacy[] = { 188 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 189 { -1, 0, 0 } 190}; 191 192static struct resource_spec age_irq_spec_msi[] = { 193 { SYS_RES_IRQ, 1, RF_ACTIVE }, 194 { -1, 0, 0 } 195}; 196 197static struct resource_spec age_irq_spec_msix[] = { 198 { SYS_RES_IRQ, 1, RF_ACTIVE }, 199 { -1, 0, 0 } 200}; 201 202/* 203 * Read a PHY register on the MII of the L1. 204 */ 205static int 206age_miibus_readreg(device_t dev, int phy, int reg) 207{ 208 struct age_softc *sc; 209 uint32_t v; 210 int i; 211 212 sc = device_get_softc(dev); 213 214 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 215 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 216 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 217 DELAY(1); 218 v = CSR_READ_4(sc, AGE_MDIO); 219 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 220 break; 221 } 222 223 if (i == 0) { 224 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 225 return (0); 226 } 227 228 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 229} 230 231/* 232 * Write a PHY register on the MII of the L1. 233 */ 234static int 235age_miibus_writereg(device_t dev, int phy, int reg, int val) 236{ 237 struct age_softc *sc; 238 uint32_t v; 239 int i; 240 241 sc = device_get_softc(dev); 242 243 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 244 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 245 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 246 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 247 DELAY(1); 248 v = CSR_READ_4(sc, AGE_MDIO); 249 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 250 break; 251 } 252 253 if (i == 0) 254 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 255 256 return (0); 257} 258 259/* 260 * Callback from MII layer when media changes. 261 */ 262static void 263age_miibus_statchg(device_t dev) 264{ 265 struct age_softc *sc; 266 267 sc = device_get_softc(dev); 268 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 269} 270 271/* 272 * Get the current interface media status. 273 */ 274static void 275age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 276{ 277 struct age_softc *sc; 278 struct mii_data *mii; 279 280 sc = ifp->if_softc; 281 AGE_LOCK(sc); 282 mii = device_get_softc(sc->age_miibus); 283 284 mii_pollstat(mii); 285 AGE_UNLOCK(sc); 286 ifmr->ifm_status = mii->mii_media_status; 287 ifmr->ifm_active = mii->mii_media_active; 288} 289 290/* 291 * Set hardware to newly-selected media. 292 */ 293static int 294age_mediachange(struct ifnet *ifp) 295{ 296 struct age_softc *sc; 297 struct mii_data *mii; 298 struct mii_softc *miisc; 299 int error; 300 301 sc = ifp->if_softc; 302 AGE_LOCK(sc); 303 mii = device_get_softc(sc->age_miibus); 304 if (mii->mii_instance != 0) { 305 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 306 mii_phy_reset(miisc); 307 } 308 error = mii_mediachg(mii); 309 AGE_UNLOCK(sc); 310 311 return (error); 312} 313 314static int 315age_probe(device_t dev) 316{ 317 struct age_dev *sp; 318 int i; 319 uint16_t vendor, devid; 320 321 vendor = pci_get_vendor(dev); 322 devid = pci_get_device(dev); 323 sp = age_devs; 324 for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]); 325 i++, sp++) { 326 if (vendor == sp->age_vendorid && 327 devid == sp->age_deviceid) { 328 device_set_desc(dev, sp->age_name); 329 return (BUS_PROBE_DEFAULT); 330 } 331 } 332 333 return (ENXIO); 334} 335 336static void 337age_get_macaddr(struct age_softc *sc) 338{ 339 uint32_t ea[2], reg; 340 int i, vpdc; 341 342 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 343 if ((reg & SPI_VPD_ENB) != 0) { 344 /* Get VPD stored in TWSI EEPROM. */ 345 reg &= ~SPI_VPD_ENB; 346 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 347 } 348 349 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 350 /* 351 * PCI VPD capability found, let TWSI reload EEPROM. 352 * This will set ethernet address of controller. 353 */ 354 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 355 TWSI_CTRL_SW_LD_START); 356 for (i = 100; i > 0; i--) { 357 DELAY(1000); 358 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 359 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 360 break; 361 } 362 if (i == 0) 363 device_printf(sc->age_dev, 364 "reloading EEPROM timeout!\n"); 365 } else { 366 if (bootverbose) 367 device_printf(sc->age_dev, 368 "PCI VPD capability not found!\n"); 369 } 370 371 ea[0] = CSR_READ_4(sc, AGE_PAR0); 372 ea[1] = CSR_READ_4(sc, AGE_PAR1); 373 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 374 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 375 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 376 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 377 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 378 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 379} 380 381static void 382age_phy_reset(struct age_softc *sc) 383{ 384 uint16_t reg, pn; 385 int i, linkup; 386 387 /* Reset PHY. */ 388 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 389 DELAY(2000); 390 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 391 DELAY(2000); 392 393#define ATPHY_DBG_ADDR 0x1D 394#define ATPHY_DBG_DATA 0x1E 395#define ATPHY_CDTC 0x16 396#define PHY_CDTC_ENB 0x0001 397#define PHY_CDTC_POFF 8 398#define ATPHY_CDTS 0x1C 399#define PHY_CDTS_STAT_OK 0x0000 400#define PHY_CDTS_STAT_SHORT 0x0100 401#define PHY_CDTS_STAT_OPEN 0x0200 402#define PHY_CDTS_STAT_INVAL 0x0300 403#define PHY_CDTS_STAT_MASK 0x0300 404 405 /* Check power saving mode. Magic from Linux. */ 406 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 407 for (linkup = 0, pn = 0; pn < 4; pn++) { 408 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 409 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 410 for (i = 200; i > 0; i--) { 411 DELAY(1000); 412 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 413 ATPHY_CDTC); 414 if ((reg & PHY_CDTC_ENB) == 0) 415 break; 416 } 417 DELAY(1000); 418 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 419 ATPHY_CDTS); 420 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 421 linkup++; 422 break; 423 } 424 } 425 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 426 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 427 if (linkup == 0) { 428 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 429 ATPHY_DBG_ADDR, 0); 430 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 431 ATPHY_DBG_DATA, 0x124E); 432 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 433 ATPHY_DBG_ADDR, 1); 434 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 435 ATPHY_DBG_DATA); 436 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 437 ATPHY_DBG_DATA, reg | 0x03); 438 /* XXX */ 439 DELAY(1500 * 1000); 440 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 441 ATPHY_DBG_ADDR, 0); 442 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 443 ATPHY_DBG_DATA, 0x024E); 444 } 445 446#undef ATPHY_DBG_ADDR 447#undef ATPHY_DBG_DATA 448#undef ATPHY_CDTC 449#undef PHY_CDTC_ENB 450#undef PHY_CDTC_POFF 451#undef ATPHY_CDTS 452#undef PHY_CDTS_STAT_OK 453#undef PHY_CDTS_STAT_SHORT 454#undef PHY_CDTS_STAT_OPEN 455#undef PHY_CDTS_STAT_INVAL 456#undef PHY_CDTS_STAT_MASK 457} 458 459static int 460age_attach(device_t dev) 461{ 462 struct age_softc *sc; 463 struct ifnet *ifp; 464 uint16_t burst; 465 int error, i, msic, msixc, pmc; 466 467 error = 0; 468 sc = device_get_softc(dev); 469 sc->age_dev = dev; 470 471 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 472 MTX_DEF); 473 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 474 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 475 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 476 477 /* Map the device. */ 478 pci_enable_busmaster(dev); 479 sc->age_res_spec = age_res_spec_mem; 480 sc->age_irq_spec = age_irq_spec_legacy; 481 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 482 if (error != 0) { 483 device_printf(dev, "cannot allocate memory resources.\n"); 484 goto fail; 485 } 486 487 /* Set PHY address. */ 488 sc->age_phyaddr = AGE_PHY_ADDR; 489 490 /* Reset PHY. */ 491 age_phy_reset(sc); 492 493 /* Reset the ethernet controller. */ 494 age_reset(sc); 495 496 /* Get PCI and chip id/revision. */ 497 sc->age_rev = pci_get_revid(dev); 498 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 499 MASTER_CHIP_REV_SHIFT; 500 if (bootverbose) { 501 device_printf(dev, "PCI device revision : 0x%04x\n", 502 sc->age_rev); 503 device_printf(dev, "Chip id/revision : 0x%04x\n", 504 sc->age_chip_rev); 505 } 506 507 /* 508 * XXX 509 * Unintialized hardware returns an invalid chip id/revision 510 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 511 * unplugged cable results in putting hardware into automatic 512 * power down mode which in turn returns invalld chip revision. 513 */ 514 if (sc->age_chip_rev == 0xFFFF) { 515 device_printf(dev,"invalid chip revision : 0x%04x -- " 516 "not initialized?\n", sc->age_chip_rev); 517 error = ENXIO; 518 goto fail; 519 } 520 521 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 522 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 523 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 524 525 /* Allocate IRQ resources. */ 526 msixc = pci_msix_count(dev); 527 msic = pci_msi_count(dev); 528 if (bootverbose) { 529 device_printf(dev, "MSIX count : %d\n", msixc); 530 device_printf(dev, "MSI count : %d\n", msic); 531 } 532 533 /* Prefer MSIX over MSI. */ 534 if (msix_disable == 0 || msi_disable == 0) { 535 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 536 pci_alloc_msix(dev, &msixc) == 0) { 537 if (msic == AGE_MSIX_MESSAGES) { 538 device_printf(dev, "Using %d MSIX messages.\n", 539 msixc); 540 sc->age_flags |= AGE_FLAG_MSIX; 541 sc->age_irq_spec = age_irq_spec_msix; 542 } else 543 pci_release_msi(dev); 544 } 545 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 546 msic == AGE_MSI_MESSAGES && 547 pci_alloc_msi(dev, &msic) == 0) { 548 if (msic == AGE_MSI_MESSAGES) { 549 device_printf(dev, "Using %d MSI messages.\n", 550 msic); 551 sc->age_flags |= AGE_FLAG_MSI; 552 sc->age_irq_spec = age_irq_spec_msi; 553 } else 554 pci_release_msi(dev); 555 } 556 } 557 558 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 559 if (error != 0) { 560 device_printf(dev, "cannot allocate IRQ resources.\n"); 561 goto fail; 562 } 563 564 565 /* Get DMA parameters from PCIe device control register. */ 566 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 567 sc->age_flags |= AGE_FLAG_PCIE; 568 burst = pci_read_config(dev, i + 0x08, 2); 569 /* Max read request size. */ 570 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 571 DMA_CFG_RD_BURST_SHIFT; 572 /* Max payload size. */ 573 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 574 DMA_CFG_WR_BURST_SHIFT; 575 if (bootverbose) { 576 device_printf(dev, "Read request size : %d bytes.\n", 577 128 << ((burst >> 12) & 0x07)); 578 device_printf(dev, "TLP payload size : %d bytes.\n", 579 128 << ((burst >> 5) & 0x07)); 580 } 581 } else { 582 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 583 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 584 } 585 586 /* Create device sysctl node. */ 587 age_sysctl_node(sc); 588 589 if ((error = age_dma_alloc(sc) != 0)) 590 goto fail; 591 592 /* Load station address. */ 593 age_get_macaddr(sc); 594 595 ifp = sc->age_ifp = if_alloc(IFT_ETHER); 596 if (ifp == NULL) { 597 device_printf(dev, "cannot allocate ifnet structure.\n"); 598 error = ENXIO; 599 goto fail; 600 } 601 602 ifp->if_softc = sc; 603 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 604 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 605 ifp->if_ioctl = age_ioctl; 606 ifp->if_start = age_start; 607 ifp->if_init = age_init; 608 ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1; 609 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 610 IFQ_SET_READY(&ifp->if_snd); 611 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 612 ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; 613 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 614 sc->age_flags |= AGE_FLAG_PMCAP; 615 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 616 } 617 ifp->if_capenable = ifp->if_capabilities; 618 619 /* Set up MII bus. */ 620 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange, 621 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY, 622 0); 623 if (error != 0) { 624 device_printf(dev, "attaching PHYs failed\n"); 625 goto fail; 626 } 627 628 ether_ifattach(ifp, sc->age_eaddr); 629 630 /* VLAN capability setup. */ 631 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 632 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 633 ifp->if_capenable = ifp->if_capabilities; 634 635 /* Tell the upper layer(s) we support long frames. */ 636 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 637 638 /* Create local taskq. */ 639 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 640 taskqueue_thread_enqueue, &sc->age_tq); 641 if (sc->age_tq == NULL) { 642 device_printf(dev, "could not create taskqueue.\n"); 643 ether_ifdetach(ifp); 644 error = ENXIO; 645 goto fail; 646 } 647 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 648 device_get_nameunit(sc->age_dev)); 649 650 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 651 msic = AGE_MSIX_MESSAGES; 652 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 653 msic = AGE_MSI_MESSAGES; 654 else 655 msic = 1; 656 for (i = 0; i < msic; i++) { 657 error = bus_setup_intr(dev, sc->age_irq[i], 658 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 659 &sc->age_intrhand[i]); 660 if (error != 0) 661 break; 662 } 663 if (error != 0) { 664 device_printf(dev, "could not set up interrupt handler.\n"); 665 taskqueue_free(sc->age_tq); 666 sc->age_tq = NULL; 667 ether_ifdetach(ifp); 668 goto fail; 669 } 670 671fail: 672 if (error != 0) 673 age_detach(dev); 674 675 return (error); 676} 677 678static int 679age_detach(device_t dev) 680{ 681 struct age_softc *sc; 682 struct ifnet *ifp; 683 int i, msic; 684 685 sc = device_get_softc(dev); 686 687 ifp = sc->age_ifp; 688 if (device_is_attached(dev)) { 689 AGE_LOCK(sc); 690 sc->age_flags |= AGE_FLAG_DETACH; 691 age_stop(sc); 692 AGE_UNLOCK(sc); 693 callout_drain(&sc->age_tick_ch); 694 taskqueue_drain(sc->age_tq, &sc->age_int_task); 695 taskqueue_drain(taskqueue_swi, &sc->age_link_task); 696 ether_ifdetach(ifp); 697 } 698 699 if (sc->age_tq != NULL) { 700 taskqueue_drain(sc->age_tq, &sc->age_int_task); 701 taskqueue_free(sc->age_tq); 702 sc->age_tq = NULL; 703 } 704 705 if (sc->age_miibus != NULL) { 706 device_delete_child(dev, sc->age_miibus); 707 sc->age_miibus = NULL; 708 } 709 bus_generic_detach(dev); 710 age_dma_free(sc); 711 712 if (ifp != NULL) { 713 if_free(ifp); 714 sc->age_ifp = NULL; 715 } 716 717 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 718 msic = AGE_MSIX_MESSAGES; 719 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 720 msic = AGE_MSI_MESSAGES; 721 else 722 msic = 1; 723 for (i = 0; i < msic; i++) { 724 if (sc->age_intrhand[i] != NULL) { 725 bus_teardown_intr(dev, sc->age_irq[i], 726 sc->age_intrhand[i]); 727 sc->age_intrhand[i] = NULL; 728 } 729 } 730 731 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 732 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 733 pci_release_msi(dev); 734 bus_release_resources(dev, sc->age_res_spec, sc->age_res); 735 mtx_destroy(&sc->age_mtx); 736 737 return (0); 738} 739 740static void 741age_sysctl_node(struct age_softc *sc) 742{ 743 int error; 744 745 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 746 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 747 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats, 748 "I", "Statistics"); 749 750 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 751 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 752 "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0, 753 sysctl_hw_age_int_mod, "I", "age interrupt moderation"); 754 755 /* Pull in device tunables. */ 756 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 757 error = resource_int_value(device_get_name(sc->age_dev), 758 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 759 if (error == 0) { 760 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 761 sc->age_int_mod > AGE_IM_TIMER_MAX) { 762 device_printf(sc->age_dev, 763 "int_mod value out of range; using default: %d\n", 764 AGE_IM_TIMER_DEFAULT); 765 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 766 } 767 } 768 769 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 770 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 771 "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit, 772 0, sysctl_hw_age_proc_limit, "I", 773 "max number of Rx events to process"); 774 775 /* Pull in device tunables. */ 776 sc->age_process_limit = AGE_PROC_DEFAULT; 777 error = resource_int_value(device_get_name(sc->age_dev), 778 device_get_unit(sc->age_dev), "process_limit", 779 &sc->age_process_limit); 780 if (error == 0) { 781 if (sc->age_process_limit < AGE_PROC_MIN || 782 sc->age_process_limit > AGE_PROC_MAX) { 783 device_printf(sc->age_dev, 784 "process_limit value out of range; " 785 "using default: %d\n", AGE_PROC_DEFAULT); 786 sc->age_process_limit = AGE_PROC_DEFAULT; 787 } 788 } 789} 790 791struct age_dmamap_arg { 792 bus_addr_t age_busaddr; 793}; 794 795static void 796age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 797{ 798 struct age_dmamap_arg *ctx; 799 800 if (error != 0) 801 return; 802 803 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 804 805 ctx = (struct age_dmamap_arg *)arg; 806 ctx->age_busaddr = segs[0].ds_addr; 807} 808 809/* 810 * Attansic L1 controller have single register to specify high 811 * address part of DMA blocks. So all descriptor structures and 812 * DMA memory blocks should have the same high address of given 813 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 814 */ 815static int 816age_check_boundary(struct age_softc *sc) 817{ 818 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 819 bus_addr_t cmb_block_end, smb_block_end; 820 821 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 822 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 823 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 824 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 825 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 826 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 827 828 if ((AGE_ADDR_HI(tx_ring_end) != 829 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 830 (AGE_ADDR_HI(rx_ring_end) != 831 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 832 (AGE_ADDR_HI(rr_ring_end) != 833 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 834 (AGE_ADDR_HI(cmb_block_end) != 835 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 836 (AGE_ADDR_HI(smb_block_end) != 837 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 838 return (EFBIG); 839 840 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 841 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 842 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 843 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 844 return (EFBIG); 845 846 return (0); 847} 848 849static int 850age_dma_alloc(struct age_softc *sc) 851{ 852 struct age_txdesc *txd; 853 struct age_rxdesc *rxd; 854 bus_addr_t lowaddr; 855 struct age_dmamap_arg ctx; 856 int error, i; 857 858 lowaddr = BUS_SPACE_MAXADDR; 859 860again: 861 /* Create parent ring/DMA block tag. */ 862 error = bus_dma_tag_create( 863 bus_get_dma_tag(sc->age_dev), /* parent */ 864 1, 0, /* alignment, boundary */ 865 lowaddr, /* lowaddr */ 866 BUS_SPACE_MAXADDR, /* highaddr */ 867 NULL, NULL, /* filter, filterarg */ 868 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 869 0, /* nsegments */ 870 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 871 0, /* flags */ 872 NULL, NULL, /* lockfunc, lockarg */ 873 &sc->age_cdata.age_parent_tag); 874 if (error != 0) { 875 device_printf(sc->age_dev, 876 "could not create parent DMA tag.\n"); 877 goto fail; 878 } 879 880 /* Create tag for Tx ring. */ 881 error = bus_dma_tag_create( 882 sc->age_cdata.age_parent_tag, /* parent */ 883 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 884 BUS_SPACE_MAXADDR, /* lowaddr */ 885 BUS_SPACE_MAXADDR, /* highaddr */ 886 NULL, NULL, /* filter, filterarg */ 887 AGE_TX_RING_SZ, /* maxsize */ 888 1, /* nsegments */ 889 AGE_TX_RING_SZ, /* maxsegsize */ 890 0, /* flags */ 891 NULL, NULL, /* lockfunc, lockarg */ 892 &sc->age_cdata.age_tx_ring_tag); 893 if (error != 0) { 894 device_printf(sc->age_dev, 895 "could not create Tx ring DMA tag.\n"); 896 goto fail; 897 } 898 899 /* Create tag for Rx ring. */ 900 error = bus_dma_tag_create( 901 sc->age_cdata.age_parent_tag, /* parent */ 902 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 903 BUS_SPACE_MAXADDR, /* lowaddr */ 904 BUS_SPACE_MAXADDR, /* highaddr */ 905 NULL, NULL, /* filter, filterarg */ 906 AGE_RX_RING_SZ, /* maxsize */ 907 1, /* nsegments */ 908 AGE_RX_RING_SZ, /* maxsegsize */ 909 0, /* flags */ 910 NULL, NULL, /* lockfunc, lockarg */ 911 &sc->age_cdata.age_rx_ring_tag); 912 if (error != 0) { 913 device_printf(sc->age_dev, 914 "could not create Rx ring DMA tag.\n"); 915 goto fail; 916 } 917 918 /* Create tag for Rx return ring. */ 919 error = bus_dma_tag_create( 920 sc->age_cdata.age_parent_tag, /* parent */ 921 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 922 BUS_SPACE_MAXADDR, /* lowaddr */ 923 BUS_SPACE_MAXADDR, /* highaddr */ 924 NULL, NULL, /* filter, filterarg */ 925 AGE_RR_RING_SZ, /* maxsize */ 926 1, /* nsegments */ 927 AGE_RR_RING_SZ, /* maxsegsize */ 928 0, /* flags */ 929 NULL, NULL, /* lockfunc, lockarg */ 930 &sc->age_cdata.age_rr_ring_tag); 931 if (error != 0) { 932 device_printf(sc->age_dev, 933 "could not create Rx return ring DMA tag.\n"); 934 goto fail; 935 } 936 937 /* Create tag for coalesing message block. */ 938 error = bus_dma_tag_create( 939 sc->age_cdata.age_parent_tag, /* parent */ 940 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 941 BUS_SPACE_MAXADDR, /* lowaddr */ 942 BUS_SPACE_MAXADDR, /* highaddr */ 943 NULL, NULL, /* filter, filterarg */ 944 AGE_CMB_BLOCK_SZ, /* maxsize */ 945 1, /* nsegments */ 946 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 947 0, /* flags */ 948 NULL, NULL, /* lockfunc, lockarg */ 949 &sc->age_cdata.age_cmb_block_tag); 950 if (error != 0) { 951 device_printf(sc->age_dev, 952 "could not create CMB DMA tag.\n"); 953 goto fail; 954 } 955 956 /* Create tag for statistics message block. */ 957 error = bus_dma_tag_create( 958 sc->age_cdata.age_parent_tag, /* parent */ 959 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 960 BUS_SPACE_MAXADDR, /* lowaddr */ 961 BUS_SPACE_MAXADDR, /* highaddr */ 962 NULL, NULL, /* filter, filterarg */ 963 AGE_SMB_BLOCK_SZ, /* maxsize */ 964 1, /* nsegments */ 965 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 966 0, /* flags */ 967 NULL, NULL, /* lockfunc, lockarg */ 968 &sc->age_cdata.age_smb_block_tag); 969 if (error != 0) { 970 device_printf(sc->age_dev, 971 "could not create SMB DMA tag.\n"); 972 goto fail; 973 } 974 975 /* Allocate DMA'able memory and load the DMA map. */ 976 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 977 (void **)&sc->age_rdata.age_tx_ring, 978 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 979 &sc->age_cdata.age_tx_ring_map); 980 if (error != 0) { 981 device_printf(sc->age_dev, 982 "could not allocate DMA'able memory for Tx ring.\n"); 983 goto fail; 984 } 985 ctx.age_busaddr = 0; 986 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 987 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 988 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 989 if (error != 0 || ctx.age_busaddr == 0) { 990 device_printf(sc->age_dev, 991 "could not load DMA'able memory for Tx ring.\n"); 992 goto fail; 993 } 994 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 995 /* Rx ring */ 996 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 997 (void **)&sc->age_rdata.age_rx_ring, 998 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 999 &sc->age_cdata.age_rx_ring_map); 1000 if (error != 0) { 1001 device_printf(sc->age_dev, 1002 "could not allocate DMA'able memory for Rx ring.\n"); 1003 goto fail; 1004 } 1005 ctx.age_busaddr = 0; 1006 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1007 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1008 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1009 if (error != 0 || ctx.age_busaddr == 0) { 1010 device_printf(sc->age_dev, 1011 "could not load DMA'able memory for Rx ring.\n"); 1012 goto fail; 1013 } 1014 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1015 /* Rx return ring */ 1016 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1017 (void **)&sc->age_rdata.age_rr_ring, 1018 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1019 &sc->age_cdata.age_rr_ring_map); 1020 if (error != 0) { 1021 device_printf(sc->age_dev, 1022 "could not allocate DMA'able memory for Rx return ring.\n"); 1023 goto fail; 1024 } 1025 ctx.age_busaddr = 0; 1026 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1027 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1028 AGE_RR_RING_SZ, age_dmamap_cb, 1029 &ctx, 0); 1030 if (error != 0 || ctx.age_busaddr == 0) { 1031 device_printf(sc->age_dev, 1032 "could not load DMA'able memory for Rx return ring.\n"); 1033 goto fail; 1034 } 1035 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1036 /* CMB block */ 1037 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1038 (void **)&sc->age_rdata.age_cmb_block, 1039 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1040 &sc->age_cdata.age_cmb_block_map); 1041 if (error != 0) { 1042 device_printf(sc->age_dev, 1043 "could not allocate DMA'able memory for CMB block.\n"); 1044 goto fail; 1045 } 1046 ctx.age_busaddr = 0; 1047 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1048 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1049 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1050 if (error != 0 || ctx.age_busaddr == 0) { 1051 device_printf(sc->age_dev, 1052 "could not load DMA'able memory for CMB block.\n"); 1053 goto fail; 1054 } 1055 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1056 /* SMB block */ 1057 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1058 (void **)&sc->age_rdata.age_smb_block, 1059 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1060 &sc->age_cdata.age_smb_block_map); 1061 if (error != 0) { 1062 device_printf(sc->age_dev, 1063 "could not allocate DMA'able memory for SMB block.\n"); 1064 goto fail; 1065 } 1066 ctx.age_busaddr = 0; 1067 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1068 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1069 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1070 if (error != 0 || ctx.age_busaddr == 0) { 1071 device_printf(sc->age_dev, 1072 "could not load DMA'able memory for SMB block.\n"); 1073 goto fail; 1074 } 1075 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1076 1077 /* 1078 * All ring buffer and DMA blocks should have the same 1079 * high address part of 64bit DMA address space. 1080 */ 1081 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1082 (error = age_check_boundary(sc)) != 0) { 1083 device_printf(sc->age_dev, "4GB boundary crossed, " 1084 "switching to 32bit DMA addressing mode.\n"); 1085 age_dma_free(sc); 1086 /* Limit DMA address space to 32bit and try again. */ 1087 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1088 goto again; 1089 } 1090 1091 /* 1092 * Create Tx/Rx buffer parent tag. 1093 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1094 * so it needs separate parent DMA tag. 1095 */ 1096 error = bus_dma_tag_create( 1097 bus_get_dma_tag(sc->age_dev), /* parent */ 1098 1, 0, /* alignment, boundary */ 1099 BUS_SPACE_MAXADDR, /* lowaddr */ 1100 BUS_SPACE_MAXADDR, /* highaddr */ 1101 NULL, NULL, /* filter, filterarg */ 1102 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1103 0, /* nsegments */ 1104 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1105 0, /* flags */ 1106 NULL, NULL, /* lockfunc, lockarg */ 1107 &sc->age_cdata.age_buffer_tag); 1108 if (error != 0) { 1109 device_printf(sc->age_dev, 1110 "could not create parent buffer DMA tag.\n"); 1111 goto fail; 1112 } 1113 1114 /* Create tag for Tx buffers. */ 1115 error = bus_dma_tag_create( 1116 sc->age_cdata.age_buffer_tag, /* parent */ 1117 1, 0, /* alignment, boundary */ 1118 BUS_SPACE_MAXADDR, /* lowaddr */ 1119 BUS_SPACE_MAXADDR, /* highaddr */ 1120 NULL, NULL, /* filter, filterarg */ 1121 AGE_TSO_MAXSIZE, /* maxsize */ 1122 AGE_MAXTXSEGS, /* nsegments */ 1123 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1124 0, /* flags */ 1125 NULL, NULL, /* lockfunc, lockarg */ 1126 &sc->age_cdata.age_tx_tag); 1127 if (error != 0) { 1128 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1129 goto fail; 1130 } 1131 1132 /* Create tag for Rx buffers. */ 1133 error = bus_dma_tag_create( 1134 sc->age_cdata.age_buffer_tag, /* parent */ 1135 1, 0, /* alignment, boundary */ 1136 BUS_SPACE_MAXADDR, /* lowaddr */ 1137 BUS_SPACE_MAXADDR, /* highaddr */ 1138 NULL, NULL, /* filter, filterarg */ 1139 MCLBYTES, /* maxsize */ 1140 1, /* nsegments */ 1141 MCLBYTES, /* maxsegsize */ 1142 0, /* flags */ 1143 NULL, NULL, /* lockfunc, lockarg */ 1144 &sc->age_cdata.age_rx_tag); 1145 if (error != 0) { 1146 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1147 goto fail; 1148 } 1149 1150 /* Create DMA maps for Tx buffers. */ 1151 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1152 txd = &sc->age_cdata.age_txdesc[i]; 1153 txd->tx_m = NULL; 1154 txd->tx_dmamap = NULL; 1155 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1156 &txd->tx_dmamap); 1157 if (error != 0) { 1158 device_printf(sc->age_dev, 1159 "could not create Tx dmamap.\n"); 1160 goto fail; 1161 } 1162 } 1163 /* Create DMA maps for Rx buffers. */ 1164 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1165 &sc->age_cdata.age_rx_sparemap)) != 0) { 1166 device_printf(sc->age_dev, 1167 "could not create spare Rx dmamap.\n"); 1168 goto fail; 1169 } 1170 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1171 rxd = &sc->age_cdata.age_rxdesc[i]; 1172 rxd->rx_m = NULL; 1173 rxd->rx_dmamap = NULL; 1174 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1175 &rxd->rx_dmamap); 1176 if (error != 0) { 1177 device_printf(sc->age_dev, 1178 "could not create Rx dmamap.\n"); 1179 goto fail; 1180 } 1181 } 1182 1183fail: 1184 return (error); 1185} 1186 1187static void 1188age_dma_free(struct age_softc *sc) 1189{ 1190 struct age_txdesc *txd; 1191 struct age_rxdesc *rxd; 1192 int i; 1193 1194 /* Tx buffers */ 1195 if (sc->age_cdata.age_tx_tag != NULL) { 1196 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1197 txd = &sc->age_cdata.age_txdesc[i]; 1198 if (txd->tx_dmamap != NULL) { 1199 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1200 txd->tx_dmamap); 1201 txd->tx_dmamap = NULL; 1202 } 1203 } 1204 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1205 sc->age_cdata.age_tx_tag = NULL; 1206 } 1207 /* Rx buffers */ 1208 if (sc->age_cdata.age_rx_tag != NULL) { 1209 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1210 rxd = &sc->age_cdata.age_rxdesc[i]; 1211 if (rxd->rx_dmamap != NULL) { 1212 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1213 rxd->rx_dmamap); 1214 rxd->rx_dmamap = NULL; 1215 } 1216 } 1217 if (sc->age_cdata.age_rx_sparemap != NULL) { 1218 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1219 sc->age_cdata.age_rx_sparemap); 1220 sc->age_cdata.age_rx_sparemap = NULL; 1221 } 1222 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1223 sc->age_cdata.age_rx_tag = NULL; 1224 } 1225 /* Tx ring. */ 1226 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1227 if (sc->age_cdata.age_tx_ring_map != NULL) 1228 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1229 sc->age_cdata.age_tx_ring_map); 1230 if (sc->age_cdata.age_tx_ring_map != NULL && 1231 sc->age_rdata.age_tx_ring != NULL) 1232 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1233 sc->age_rdata.age_tx_ring, 1234 sc->age_cdata.age_tx_ring_map); 1235 sc->age_rdata.age_tx_ring = NULL; 1236 sc->age_cdata.age_tx_ring_map = NULL; 1237 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1238 sc->age_cdata.age_tx_ring_tag = NULL; 1239 } 1240 /* Rx ring. */ 1241 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1242 if (sc->age_cdata.age_rx_ring_map != NULL) 1243 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1244 sc->age_cdata.age_rx_ring_map); 1245 if (sc->age_cdata.age_rx_ring_map != NULL && 1246 sc->age_rdata.age_rx_ring != NULL) 1247 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1248 sc->age_rdata.age_rx_ring, 1249 sc->age_cdata.age_rx_ring_map); 1250 sc->age_rdata.age_rx_ring = NULL; 1251 sc->age_cdata.age_rx_ring_map = NULL; 1252 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1253 sc->age_cdata.age_rx_ring_tag = NULL; 1254 } 1255 /* Rx return ring. */ 1256 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1257 if (sc->age_cdata.age_rr_ring_map != NULL) 1258 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1259 sc->age_cdata.age_rr_ring_map); 1260 if (sc->age_cdata.age_rr_ring_map != NULL && 1261 sc->age_rdata.age_rr_ring != NULL) 1262 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1263 sc->age_rdata.age_rr_ring, 1264 sc->age_cdata.age_rr_ring_map); 1265 sc->age_rdata.age_rr_ring = NULL; 1266 sc->age_cdata.age_rr_ring_map = NULL; 1267 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1268 sc->age_cdata.age_rr_ring_tag = NULL; 1269 } 1270 /* CMB block */ 1271 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1272 if (sc->age_cdata.age_cmb_block_map != NULL) 1273 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1274 sc->age_cdata.age_cmb_block_map); 1275 if (sc->age_cdata.age_cmb_block_map != NULL && 1276 sc->age_rdata.age_cmb_block != NULL) 1277 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1278 sc->age_rdata.age_cmb_block, 1279 sc->age_cdata.age_cmb_block_map); 1280 sc->age_rdata.age_cmb_block = NULL; 1281 sc->age_cdata.age_cmb_block_map = NULL; 1282 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1283 sc->age_cdata.age_cmb_block_tag = NULL; 1284 } 1285 /* SMB block */ 1286 if (sc->age_cdata.age_smb_block_tag != NULL) { 1287 if (sc->age_cdata.age_smb_block_map != NULL) 1288 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1289 sc->age_cdata.age_smb_block_map); 1290 if (sc->age_cdata.age_smb_block_map != NULL && 1291 sc->age_rdata.age_smb_block != NULL) 1292 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1293 sc->age_rdata.age_smb_block, 1294 sc->age_cdata.age_smb_block_map); 1295 sc->age_rdata.age_smb_block = NULL; 1296 sc->age_cdata.age_smb_block_map = NULL; 1297 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1298 sc->age_cdata.age_smb_block_tag = NULL; 1299 } 1300 1301 if (sc->age_cdata.age_buffer_tag != NULL) { 1302 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1303 sc->age_cdata.age_buffer_tag = NULL; 1304 } 1305 if (sc->age_cdata.age_parent_tag != NULL) { 1306 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1307 sc->age_cdata.age_parent_tag = NULL; 1308 } 1309} 1310 1311/* 1312 * Make sure the interface is stopped at reboot time. 1313 */ 1314static int 1315age_shutdown(device_t dev) 1316{ 1317 1318 return (age_suspend(dev)); 1319} 1320 1321static void 1322age_setwol(struct age_softc *sc) 1323{ 1324 struct ifnet *ifp; 1325 struct mii_data *mii; 1326 uint32_t reg, pmcs; 1327 uint16_t pmstat; 1328 int aneg, i, pmc; 1329 1330 AGE_LOCK_ASSERT(sc); 1331 1332 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1333 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1334 /* 1335 * No PME capability, PHY power down. 1336 * XXX 1337 * Due to an unknown reason powering down PHY resulted 1338 * in unexpected results such as inaccessbility of 1339 * hardware of freshly rebooted system. Disable 1340 * powering down PHY until I got more information for 1341 * Attansic/Atheros PHY hardwares. 1342 */ 1343#ifdef notyet 1344 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1345 MII_BMCR, BMCR_PDOWN); 1346#endif 1347 return; 1348 } 1349 1350 ifp = sc->age_ifp; 1351 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1352 /* 1353 * Note, this driver resets the link speed to 10/100Mbps with 1354 * auto-negotiation but we don't know whether that operation 1355 * would succeed or not as it have no control after powering 1356 * off. If the renegotiation fail WOL may not work. Running 1357 * at 1Gbps will draw more power than 375mA at 3.3V which is 1358 * specified in PCI specification and that would result in 1359 * complete shutdowning power to ethernet controller. 1360 * 1361 * TODO 1362 * Save current negotiated media speed/duplex/flow-control 1363 * to softc and restore the same link again after resuming. 1364 * PHY handling such as power down/resetting to 100Mbps 1365 * may be better handled in suspend method in phy driver. 1366 */ 1367 mii = device_get_softc(sc->age_miibus); 1368 mii_pollstat(mii); 1369 aneg = 0; 1370 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1371 switch IFM_SUBTYPE(mii->mii_media_active) { 1372 case IFM_10_T: 1373 case IFM_100_TX: 1374 goto got_link; 1375 case IFM_1000_T: 1376 aneg++; 1377 default: 1378 break; 1379 } 1380 } 1381 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1382 MII_100T2CR, 0); 1383 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1384 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1385 ANAR_10 | ANAR_CSMA); 1386 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1387 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1388 DELAY(1000); 1389 if (aneg != 0) { 1390 /* Poll link state until age(4) get a 10/100 link. */ 1391 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1392 mii_pollstat(mii); 1393 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1394 switch (IFM_SUBTYPE( 1395 mii->mii_media_active)) { 1396 case IFM_10_T: 1397 case IFM_100_TX: 1398 age_mac_config(sc); 1399 goto got_link; 1400 default: 1401 break; 1402 } 1403 } 1404 AGE_UNLOCK(sc); 1405 pause("agelnk", hz); 1406 AGE_LOCK(sc); 1407 } 1408 if (i == MII_ANEGTICKS_GIGE) 1409 device_printf(sc->age_dev, 1410 "establishing link failed, " 1411 "WOL may not work!"); 1412 } 1413 /* 1414 * No link, force MAC to have 100Mbps, full-duplex link. 1415 * This is the last resort and may/may not work. 1416 */ 1417 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1418 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1419 age_mac_config(sc); 1420 } 1421 1422got_link: 1423 pmcs = 0; 1424 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1425 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1426 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1427 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1428 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1429 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1430 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1431 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1432 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1433 reg |= MAC_CFG_RX_ENB; 1434 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1435 } 1436 1437 /* Request PME. */ 1438 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1439 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1440 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1441 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1442 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1443#ifdef notyet 1444 /* See above for powering down PHY issues. */ 1445 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1446 /* No WOL, PHY power down. */ 1447 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1448 MII_BMCR, BMCR_PDOWN); 1449 } 1450#endif 1451} 1452 1453static int 1454age_suspend(device_t dev) 1455{ 1456 struct age_softc *sc; 1457 1458 sc = device_get_softc(dev); 1459 1460 AGE_LOCK(sc); 1461 age_stop(sc); 1462 age_setwol(sc); 1463 AGE_UNLOCK(sc); 1464 1465 return (0); 1466} 1467 1468static int 1469age_resume(device_t dev) 1470{ 1471 struct age_softc *sc; 1472 struct ifnet *ifp; 1473 1474 sc = device_get_softc(dev); 1475 1476 AGE_LOCK(sc); 1477 age_phy_reset(sc); 1478 ifp = sc->age_ifp; 1479 if ((ifp->if_flags & IFF_UP) != 0) 1480 age_init_locked(sc); 1481 1482 AGE_UNLOCK(sc); 1483 1484 return (0); 1485} 1486 1487static int 1488age_encap(struct age_softc *sc, struct mbuf **m_head) 1489{ 1490 struct age_txdesc *txd, *txd_last; 1491 struct tx_desc *desc; 1492 struct mbuf *m; 1493 struct ip *ip; 1494 struct tcphdr *tcp; 1495 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1496 bus_dmamap_t map; 1497 uint32_t cflags, ip_off, poff, vtag; 1498 int error, i, nsegs, prod, si; 1499 1500 AGE_LOCK_ASSERT(sc); 1501 1502 M_ASSERTPKTHDR((*m_head)); 1503 1504 m = *m_head; 1505 ip = NULL; 1506 tcp = NULL; 1507 cflags = vtag = 0; 1508 ip_off = poff = 0; 1509 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1510 /* 1511 * L1 requires offset of TCP/UDP payload in its Tx 1512 * descriptor to perform hardware Tx checksum offload. 1513 * Additionally, TSO requires IP/TCP header size and 1514 * modification of IP/TCP header in order to make TSO 1515 * engine work. This kind of operation takes many CPU 1516 * cycles on FreeBSD so fast host CPU is needed to get 1517 * smooth TSO performance. 1518 */ 1519 struct ether_header *eh; 1520 1521 if (M_WRITABLE(m) == 0) { 1522 /* Get a writable copy. */ 1523 m = m_dup(*m_head, M_DONTWAIT); 1524 /* Release original mbufs. */ 1525 m_freem(*m_head); 1526 if (m == NULL) { 1527 *m_head = NULL; 1528 return (ENOBUFS); 1529 } 1530 *m_head = m; 1531 } 1532 ip_off = sizeof(struct ether_header); 1533 m = m_pullup(m, ip_off); 1534 if (m == NULL) { 1535 *m_head = NULL; 1536 return (ENOBUFS); 1537 } 1538 eh = mtod(m, struct ether_header *); 1539 /* 1540 * Check if hardware VLAN insertion is off. 1541 * Additional check for LLC/SNAP frame? 1542 */ 1543 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1544 ip_off = sizeof(struct ether_vlan_header); 1545 m = m_pullup(m, ip_off); 1546 if (m == NULL) { 1547 *m_head = NULL; 1548 return (ENOBUFS); 1549 } 1550 } 1551 m = m_pullup(m, ip_off + sizeof(struct ip)); 1552 if (m == NULL) { 1553 *m_head = NULL; 1554 return (ENOBUFS); 1555 } 1556 ip = (struct ip *)(mtod(m, char *) + ip_off); 1557 poff = ip_off + (ip->ip_hl << 2); 1558 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1559 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1560 if (m == NULL) { 1561 *m_head = NULL; 1562 return (ENOBUFS); 1563 } 1564 ip = (struct ip *)(mtod(m, char *) + ip_off); 1565 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1566 /* 1567 * L1 requires IP/TCP header size and offset as 1568 * well as TCP pseudo checksum which complicates 1569 * TSO configuration. I guess this comes from the 1570 * adherence to Microsoft NDIS Large Send 1571 * specification which requires insertion of 1572 * pseudo checksum by upper stack. The pseudo 1573 * checksum that NDIS refers to doesn't include 1574 * TCP payload length so age(4) should recompute 1575 * the pseudo checksum here. Hopefully this wouldn't 1576 * be much burden on modern CPUs. 1577 * Reset IP checksum and recompute TCP pseudo 1578 * checksum as NDIS specification said. 1579 */ 1580 ip->ip_sum = 0; 1581 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) 1582 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1583 ip->ip_dst.s_addr, 1584 htons((tcp->th_off << 2) + IPPROTO_TCP)); 1585 else 1586 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1587 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1588 } 1589 *m_head = m; 1590 } 1591 1592 si = prod = sc->age_cdata.age_tx_prod; 1593 txd = &sc->age_cdata.age_txdesc[prod]; 1594 txd_last = txd; 1595 map = txd->tx_dmamap; 1596 1597 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1598 *m_head, txsegs, &nsegs, 0); 1599 if (error == EFBIG) { 1600 m = m_collapse(*m_head, M_DONTWAIT, AGE_MAXTXSEGS); 1601 if (m == NULL) { 1602 m_freem(*m_head); 1603 *m_head = NULL; 1604 return (ENOMEM); 1605 } 1606 *m_head = m; 1607 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1608 *m_head, txsegs, &nsegs, 0); 1609 if (error != 0) { 1610 m_freem(*m_head); 1611 *m_head = NULL; 1612 return (error); 1613 } 1614 } else if (error != 0) 1615 return (error); 1616 if (nsegs == 0) { 1617 m_freem(*m_head); 1618 *m_head = NULL; 1619 return (EIO); 1620 } 1621 1622 /* Check descriptor overrun. */ 1623 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1624 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1625 return (ENOBUFS); 1626 } 1627 1628 m = *m_head; 1629 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1630 /* Configure TSO. */ 1631 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1632 /* Not TSO but IP/TCP checksum offload. */ 1633 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1634 /* Clear TSO in order not to set AGE_TD_TSO_HDR. */ 1635 m->m_pkthdr.csum_flags &= ~CSUM_TSO; 1636 } else { 1637 /* Request TSO and set MSS. */ 1638 cflags |= AGE_TD_TSO_IPV4; 1639 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1640 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1641 AGE_TD_TSO_MSS_SHIFT); 1642 } 1643 /* Set IP/TCP header size. */ 1644 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1645 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1646 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1647 /* Configure Tx IP/TCP/UDP checksum offload. */ 1648 cflags |= AGE_TD_CSUM; 1649 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1650 cflags |= AGE_TD_TCPCSUM; 1651 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1652 cflags |= AGE_TD_UDPCSUM; 1653 /* Set checksum start offset. */ 1654 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1655 /* Set checksum insertion position of TCP/UDP. */ 1656 cflags |= ((poff + m->m_pkthdr.csum_data) << 1657 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1658 } 1659 1660 /* Configure VLAN hardware tag insertion. */ 1661 if ((m->m_flags & M_VLANTAG) != 0) { 1662 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1663 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1664 cflags |= AGE_TD_INSERT_VLAN_TAG; 1665 } 1666 1667 desc = NULL; 1668 for (i = 0; i < nsegs; i++) { 1669 desc = &sc->age_rdata.age_tx_ring[prod]; 1670 desc->addr = htole64(txsegs[i].ds_addr); 1671 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1672 desc->flags = htole32(cflags); 1673 sc->age_cdata.age_tx_cnt++; 1674 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1675 } 1676 /* Update producer index. */ 1677 sc->age_cdata.age_tx_prod = prod; 1678 1679 /* Set EOP on the last descriptor. */ 1680 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1681 desc = &sc->age_rdata.age_tx_ring[prod]; 1682 desc->flags |= htole32(AGE_TD_EOP); 1683 1684 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1685 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1686 desc = &sc->age_rdata.age_tx_ring[si]; 1687 desc->flags |= htole32(AGE_TD_TSO_HDR); 1688 } 1689 1690 /* Swap dmamap of the first and the last. */ 1691 txd = &sc->age_cdata.age_txdesc[prod]; 1692 map = txd_last->tx_dmamap; 1693 txd_last->tx_dmamap = txd->tx_dmamap; 1694 txd->tx_dmamap = map; 1695 txd->tx_m = m; 1696 1697 /* Sync descriptors. */ 1698 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1699 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1700 sc->age_cdata.age_tx_ring_map, 1701 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1702 1703 return (0); 1704} 1705 1706static void 1707age_start(struct ifnet *ifp) 1708{ 1709 struct age_softc *sc; 1710 1711 sc = ifp->if_softc; 1712 AGE_LOCK(sc); 1713 age_start_locked(ifp); 1714 AGE_UNLOCK(sc); 1715} 1716 1717static void 1718age_start_locked(struct ifnet *ifp) 1719{ 1720 struct age_softc *sc; 1721 struct mbuf *m_head; 1722 int enq; 1723 1724 sc = ifp->if_softc; 1725 1726 AGE_LOCK_ASSERT(sc); 1727 1728 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1729 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) 1730 return; 1731 1732 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1733 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1734 if (m_head == NULL) 1735 break; 1736 /* 1737 * Pack the data into the transmit ring. If we 1738 * don't have room, set the OACTIVE flag and wait 1739 * for the NIC to drain the ring. 1740 */ 1741 if (age_encap(sc, &m_head)) { 1742 if (m_head == NULL) 1743 break; 1744 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1745 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1746 break; 1747 } 1748 1749 enq++; 1750 /* 1751 * If there's a BPF listener, bounce a copy of this frame 1752 * to him. 1753 */ 1754 ETHER_BPF_MTAP(ifp, m_head); 1755 } 1756 1757 if (enq > 0) { 1758 /* Update mbox. */ 1759 AGE_COMMIT_MBOX(sc); 1760 /* Set a timeout in case the chip goes out to lunch. */ 1761 sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1762 } 1763} 1764 1765static void 1766age_watchdog(struct age_softc *sc) 1767{ 1768 struct ifnet *ifp; 1769 1770 AGE_LOCK_ASSERT(sc); 1771 1772 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1773 return; 1774 1775 ifp = sc->age_ifp; 1776 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1777 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1778 ifp->if_oerrors++; 1779 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1780 age_init_locked(sc); 1781 return; 1782 } 1783 if (sc->age_cdata.age_tx_cnt == 0) { 1784 if_printf(sc->age_ifp, 1785 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1786 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1787 age_start_locked(ifp); 1788 return; 1789 } 1790 if_printf(sc->age_ifp, "watchdog timeout\n"); 1791 ifp->if_oerrors++; 1792 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1793 age_init_locked(sc); 1794 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1795 age_start_locked(ifp); 1796} 1797 1798static int 1799age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1800{ 1801 struct age_softc *sc; 1802 struct ifreq *ifr; 1803 struct mii_data *mii; 1804 uint32_t reg; 1805 int error, mask; 1806 1807 sc = ifp->if_softc; 1808 ifr = (struct ifreq *)data; 1809 error = 0; 1810 switch (cmd) { 1811 case SIOCSIFMTU: 1812 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1813 error = EINVAL; 1814 else if (ifp->if_mtu != ifr->ifr_mtu) { 1815 AGE_LOCK(sc); 1816 ifp->if_mtu = ifr->ifr_mtu; 1817 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1818 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1819 age_init_locked(sc); 1820 } 1821 AGE_UNLOCK(sc); 1822 } 1823 break; 1824 case SIOCSIFFLAGS: 1825 AGE_LOCK(sc); 1826 if ((ifp->if_flags & IFF_UP) != 0) { 1827 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1828 if (((ifp->if_flags ^ sc->age_if_flags) 1829 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1830 age_rxfilter(sc); 1831 } else { 1832 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1833 age_init_locked(sc); 1834 } 1835 } else { 1836 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1837 age_stop(sc); 1838 } 1839 sc->age_if_flags = ifp->if_flags; 1840 AGE_UNLOCK(sc); 1841 break; 1842 case SIOCADDMULTI: 1843 case SIOCDELMULTI: 1844 AGE_LOCK(sc); 1845 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1846 age_rxfilter(sc); 1847 AGE_UNLOCK(sc); 1848 break; 1849 case SIOCSIFMEDIA: 1850 case SIOCGIFMEDIA: 1851 mii = device_get_softc(sc->age_miibus); 1852 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1853 break; 1854 case SIOCSIFCAP: 1855 AGE_LOCK(sc); 1856 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1857 if ((mask & IFCAP_TXCSUM) != 0 && 1858 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1859 ifp->if_capenable ^= IFCAP_TXCSUM; 1860 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1861 ifp->if_hwassist |= AGE_CSUM_FEATURES; 1862 else 1863 ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1864 } 1865 if ((mask & IFCAP_RXCSUM) != 0 && 1866 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1867 ifp->if_capenable ^= IFCAP_RXCSUM; 1868 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1869 reg &= ~MAC_CFG_RXCSUM_ENB; 1870 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1871 reg |= MAC_CFG_RXCSUM_ENB; 1872 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1873 } 1874 if ((mask & IFCAP_TSO4) != 0 && 1875 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1876 ifp->if_capenable ^= IFCAP_TSO4; 1877 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1878 ifp->if_hwassist |= CSUM_TSO; 1879 else 1880 ifp->if_hwassist &= ~CSUM_TSO; 1881 } 1882 1883 if ((mask & IFCAP_WOL_MCAST) != 0 && 1884 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1885 ifp->if_capenable ^= IFCAP_WOL_MCAST; 1886 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1887 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1888 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1889 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1890 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1891 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1892 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1893 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1894 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1895 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1896 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1897 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1898 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1899 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1900 age_rxvlan(sc); 1901 } 1902 AGE_UNLOCK(sc); 1903 VLAN_CAPABILITIES(ifp); 1904 break; 1905 default: 1906 error = ether_ioctl(ifp, cmd, data); 1907 break; 1908 } 1909 1910 return (error); 1911} 1912 1913static void 1914age_mac_config(struct age_softc *sc) 1915{ 1916 struct mii_data *mii; 1917 uint32_t reg; 1918 1919 AGE_LOCK_ASSERT(sc); 1920 1921 mii = device_get_softc(sc->age_miibus); 1922 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1923 reg &= ~MAC_CFG_FULL_DUPLEX; 1924 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1925 reg &= ~MAC_CFG_SPEED_MASK; 1926 /* Reprogram MAC with resolved speed/duplex. */ 1927 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1928 case IFM_10_T: 1929 case IFM_100_TX: 1930 reg |= MAC_CFG_SPEED_10_100; 1931 break; 1932 case IFM_1000_T: 1933 reg |= MAC_CFG_SPEED_1000; 1934 break; 1935 } 1936 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1937 reg |= MAC_CFG_FULL_DUPLEX; 1938#ifdef notyet 1939 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1940 reg |= MAC_CFG_TX_FC; 1941 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1942 reg |= MAC_CFG_RX_FC; 1943#endif 1944 } 1945 1946 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1947} 1948 1949static void 1950age_link_task(void *arg, int pending) 1951{ 1952 struct age_softc *sc; 1953 struct mii_data *mii; 1954 struct ifnet *ifp; 1955 uint32_t reg; 1956 1957 sc = (struct age_softc *)arg; 1958 1959 AGE_LOCK(sc); 1960 mii = device_get_softc(sc->age_miibus); 1961 ifp = sc->age_ifp; 1962 if (mii == NULL || ifp == NULL || 1963 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1964 AGE_UNLOCK(sc); 1965 return; 1966 } 1967 1968 sc->age_flags &= ~AGE_FLAG_LINK; 1969 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1970 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1971 case IFM_10_T: 1972 case IFM_100_TX: 1973 case IFM_1000_T: 1974 sc->age_flags |= AGE_FLAG_LINK; 1975 break; 1976 default: 1977 break; 1978 } 1979 } 1980 1981 /* Stop Rx/Tx MACs. */ 1982 age_stop_rxmac(sc); 1983 age_stop_txmac(sc); 1984 1985 /* Program MACs with resolved speed/duplex/flow-control. */ 1986 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 1987 age_mac_config(sc); 1988 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1989 /* Restart DMA engine and Tx/Rx MAC. */ 1990 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 1991 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 1992 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1993 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1994 } 1995 1996 AGE_UNLOCK(sc); 1997} 1998 1999static void 2000age_stats_update(struct age_softc *sc) 2001{ 2002 struct age_stats *stat; 2003 struct smb *smb; 2004 struct ifnet *ifp; 2005 2006 AGE_LOCK_ASSERT(sc); 2007 2008 stat = &sc->age_stat; 2009 2010 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2011 sc->age_cdata.age_smb_block_map, 2012 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2013 2014 smb = sc->age_rdata.age_smb_block; 2015 if (smb->updated == 0) 2016 return; 2017 2018 ifp = sc->age_ifp; 2019 /* Rx stats. */ 2020 stat->rx_frames += smb->rx_frames; 2021 stat->rx_bcast_frames += smb->rx_bcast_frames; 2022 stat->rx_mcast_frames += smb->rx_mcast_frames; 2023 stat->rx_pause_frames += smb->rx_pause_frames; 2024 stat->rx_control_frames += smb->rx_control_frames; 2025 stat->rx_crcerrs += smb->rx_crcerrs; 2026 stat->rx_lenerrs += smb->rx_lenerrs; 2027 stat->rx_bytes += smb->rx_bytes; 2028 stat->rx_runts += smb->rx_runts; 2029 stat->rx_fragments += smb->rx_fragments; 2030 stat->rx_pkts_64 += smb->rx_pkts_64; 2031 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2032 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2033 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2034 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2035 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2036 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2037 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2038 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2039 stat->rx_desc_oflows += smb->rx_desc_oflows; 2040 stat->rx_alignerrs += smb->rx_alignerrs; 2041 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2042 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2043 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2044 2045 /* Tx stats. */ 2046 stat->tx_frames += smb->tx_frames; 2047 stat->tx_bcast_frames += smb->tx_bcast_frames; 2048 stat->tx_mcast_frames += smb->tx_mcast_frames; 2049 stat->tx_pause_frames += smb->tx_pause_frames; 2050 stat->tx_excess_defer += smb->tx_excess_defer; 2051 stat->tx_control_frames += smb->tx_control_frames; 2052 stat->tx_deferred += smb->tx_deferred; 2053 stat->tx_bytes += smb->tx_bytes; 2054 stat->tx_pkts_64 += smb->tx_pkts_64; 2055 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2056 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2057 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2058 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2059 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2060 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2061 stat->tx_single_colls += smb->tx_single_colls; 2062 stat->tx_multi_colls += smb->tx_multi_colls; 2063 stat->tx_late_colls += smb->tx_late_colls; 2064 stat->tx_excess_colls += smb->tx_excess_colls; 2065 stat->tx_underrun += smb->tx_underrun; 2066 stat->tx_desc_underrun += smb->tx_desc_underrun; 2067 stat->tx_lenerrs += smb->tx_lenerrs; 2068 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2069 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2070 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2071 2072 /* Update counters in ifnet. */ 2073 ifp->if_opackets += smb->tx_frames; 2074 2075 ifp->if_collisions += smb->tx_single_colls + 2076 smb->tx_multi_colls + smb->tx_late_colls + 2077 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2078 2079 ifp->if_oerrors += smb->tx_excess_colls + 2080 smb->tx_late_colls + smb->tx_underrun + 2081 smb->tx_pkts_truncated; 2082 2083 ifp->if_ipackets += smb->rx_frames; 2084 2085 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2086 smb->rx_runts + smb->rx_pkts_truncated + 2087 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2088 smb->rx_alignerrs; 2089 2090 /* Update done, clear. */ 2091 smb->updated = 0; 2092 2093 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2094 sc->age_cdata.age_smb_block_map, 2095 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2096} 2097 2098static int 2099age_intr(void *arg) 2100{ 2101 struct age_softc *sc; 2102 uint32_t status; 2103 2104 sc = (struct age_softc *)arg; 2105 2106 status = CSR_READ_4(sc, AGE_INTR_STATUS); 2107 if (status == 0 || (status & AGE_INTRS) == 0) 2108 return (FILTER_STRAY); 2109 /* Disable interrupts. */ 2110 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2111 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2112 2113 return (FILTER_HANDLED); 2114} 2115 2116static void 2117age_int_task(void *arg, int pending) 2118{ 2119 struct age_softc *sc; 2120 struct ifnet *ifp; 2121 struct cmb *cmb; 2122 uint32_t status; 2123 2124 sc = (struct age_softc *)arg; 2125 2126 AGE_LOCK(sc); 2127 2128 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2129 sc->age_cdata.age_cmb_block_map, 2130 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2131 cmb = sc->age_rdata.age_cmb_block; 2132 status = le32toh(cmb->intr_status); 2133 if (sc->age_morework != 0) 2134 status |= INTR_CMB_RX; 2135 if ((status & AGE_INTRS) == 0) 2136 goto done; 2137 2138 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2139 TPD_CONS_SHIFT; 2140 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2141 RRD_PROD_SHIFT; 2142 /* Let hardware know CMB was served. */ 2143 cmb->intr_status = 0; 2144 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2145 sc->age_cdata.age_cmb_block_map, 2146 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2147 2148#if 0 2149 printf("INTR: 0x%08x\n", status); 2150 status &= ~INTR_DIS_DMA; 2151 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2152#endif 2153 ifp = sc->age_ifp; 2154 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2155 if ((status & INTR_CMB_RX) != 0) 2156 sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2157 sc->age_process_limit); 2158 if ((status & INTR_CMB_TX) != 0) 2159 age_txintr(sc, sc->age_tpd_cons); 2160 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2161 if ((status & INTR_DMA_RD_TO_RST) != 0) 2162 device_printf(sc->age_dev, 2163 "DMA read error! -- resetting\n"); 2164 if ((status & INTR_DMA_WR_TO_RST) != 0) 2165 device_printf(sc->age_dev, 2166 "DMA write error! -- resetting\n"); 2167 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2168 age_init_locked(sc); 2169 } 2170 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2171 age_start_locked(ifp); 2172 if ((status & INTR_SMB) != 0) 2173 age_stats_update(sc); 2174 } 2175 2176 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2177 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2178 sc->age_cdata.age_cmb_block_map, 2179 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2180 status = le32toh(cmb->intr_status); 2181 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2182 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2183 AGE_UNLOCK(sc); 2184 return; 2185 } 2186 2187done: 2188 /* Re-enable interrupts. */ 2189 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2190 AGE_UNLOCK(sc); 2191} 2192 2193static void 2194age_txintr(struct age_softc *sc, int tpd_cons) 2195{ 2196 struct ifnet *ifp; 2197 struct age_txdesc *txd; 2198 int cons, prog; 2199 2200 AGE_LOCK_ASSERT(sc); 2201 2202 ifp = sc->age_ifp; 2203 2204 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2205 sc->age_cdata.age_tx_ring_map, 2206 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2207 2208 /* 2209 * Go through our Tx list and free mbufs for those 2210 * frames which have been transmitted. 2211 */ 2212 cons = sc->age_cdata.age_tx_cons; 2213 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2214 if (sc->age_cdata.age_tx_cnt <= 0) 2215 break; 2216 prog++; 2217 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2218 sc->age_cdata.age_tx_cnt--; 2219 txd = &sc->age_cdata.age_txdesc[cons]; 2220 /* 2221 * Clear Tx descriptors, it's not required but would 2222 * help debugging in case of Tx issues. 2223 */ 2224 txd->tx_desc->addr = 0; 2225 txd->tx_desc->len = 0; 2226 txd->tx_desc->flags = 0; 2227 2228 if (txd->tx_m == NULL) 2229 continue; 2230 /* Reclaim transmitted mbufs. */ 2231 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2232 BUS_DMASYNC_POSTWRITE); 2233 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2234 m_freem(txd->tx_m); 2235 txd->tx_m = NULL; 2236 } 2237 2238 if (prog > 0) { 2239 sc->age_cdata.age_tx_cons = cons; 2240 2241 /* 2242 * Unarm watchdog timer only when there are no pending 2243 * Tx descriptors in queue. 2244 */ 2245 if (sc->age_cdata.age_tx_cnt == 0) 2246 sc->age_watchdog_timer = 0; 2247 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2248 sc->age_cdata.age_tx_ring_map, 2249 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2250 } 2251} 2252 2253/* Receive a frame. */ 2254static void 2255age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2256{ 2257 struct age_rxdesc *rxd; 2258 struct rx_desc *desc; 2259 struct ifnet *ifp; 2260 struct mbuf *mp, *m; 2261 uint32_t status, index, vtag; 2262 int count, nsegs, pktlen; 2263 int rx_cons; 2264 2265 AGE_LOCK_ASSERT(sc); 2266 2267 ifp = sc->age_ifp; 2268 status = le32toh(rxrd->flags); 2269 index = le32toh(rxrd->index); 2270 rx_cons = AGE_RX_CONS(index); 2271 nsegs = AGE_RX_NSEGS(index); 2272 2273 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2274 if ((status & AGE_RRD_ERROR) != 0 && 2275 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2276 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 2277 /* 2278 * We want to pass the following frames to upper 2279 * layer regardless of error status of Rx return 2280 * ring. 2281 * 2282 * o IP/TCP/UDP checksum is bad. 2283 * o frame length and protocol specific length 2284 * does not match. 2285 */ 2286 sc->age_cdata.age_rx_cons += nsegs; 2287 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2288 return; 2289 } 2290 2291 pktlen = 0; 2292 for (count = 0; count < nsegs; count++, 2293 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2294 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2295 mp = rxd->rx_m; 2296 desc = rxd->rx_desc; 2297 /* Add a new receive buffer to the ring. */ 2298 if (age_newbuf(sc, rxd) != 0) { 2299 ifp->if_iqdrops++; 2300 /* Reuse Rx buffers. */ 2301 if (sc->age_cdata.age_rxhead != NULL) { 2302 m_freem(sc->age_cdata.age_rxhead); 2303 AGE_RXCHAIN_RESET(sc); 2304 } 2305 break; 2306 } 2307 2308 /* The length of the first mbuf is computed last. */ 2309 if (count != 0) { 2310 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 2311 pktlen += mp->m_len; 2312 } 2313 2314 /* Chain received mbufs. */ 2315 if (sc->age_cdata.age_rxhead == NULL) { 2316 sc->age_cdata.age_rxhead = mp; 2317 sc->age_cdata.age_rxtail = mp; 2318 } else { 2319 mp->m_flags &= ~M_PKTHDR; 2320 sc->age_cdata.age_rxprev_tail = 2321 sc->age_cdata.age_rxtail; 2322 sc->age_cdata.age_rxtail->m_next = mp; 2323 sc->age_cdata.age_rxtail = mp; 2324 } 2325 2326 if (count == nsegs - 1) { 2327 /* 2328 * It seems that L1 controller has no way 2329 * to tell hardware to strip CRC bytes. 2330 */ 2331 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 2332 if (nsegs > 1) { 2333 /* Remove the CRC bytes in chained mbufs. */ 2334 pktlen -= ETHER_CRC_LEN; 2335 if (mp->m_len <= ETHER_CRC_LEN) { 2336 sc->age_cdata.age_rxtail = 2337 sc->age_cdata.age_rxprev_tail; 2338 sc->age_cdata.age_rxtail->m_len -= 2339 (ETHER_CRC_LEN - mp->m_len); 2340 sc->age_cdata.age_rxtail->m_next = NULL; 2341 m_freem(mp); 2342 } else { 2343 mp->m_len -= ETHER_CRC_LEN; 2344 } 2345 } 2346 2347 m = sc->age_cdata.age_rxhead; 2348 m->m_flags |= M_PKTHDR; 2349 m->m_pkthdr.rcvif = ifp; 2350 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 2351 /* Set the first mbuf length. */ 2352 m->m_len = sc->age_cdata.age_rxlen - pktlen; 2353 2354 /* 2355 * Set checksum information. 2356 * It seems that L1 controller can compute partial 2357 * checksum. The partial checksum value can be used 2358 * to accelerate checksum computation for fragmented 2359 * TCP/UDP packets. Upper network stack already 2360 * takes advantage of the partial checksum value in 2361 * IP reassembly stage. But I'm not sure the 2362 * correctness of the partial hardware checksum 2363 * assistance due to lack of data sheet. If it is 2364 * proven to work on L1 I'll enable it. 2365 */ 2366 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2367 (status & AGE_RRD_IPV4) != 0) { 2368 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2369 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2370 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2371 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2372 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2373 m->m_pkthdr.csum_flags |= 2374 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2375 m->m_pkthdr.csum_data = 0xffff; 2376 } 2377 /* 2378 * Don't mark bad checksum for TCP/UDP frames 2379 * as fragmented frames may always have set 2380 * bad checksummed bit of descriptor status. 2381 */ 2382 } 2383 2384 /* Check for VLAN tagged frames. */ 2385 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2386 (status & AGE_RRD_VLAN) != 0) { 2387 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2388 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2389 m->m_flags |= M_VLANTAG; 2390 } 2391 2392 /* Pass it on. */ 2393 AGE_UNLOCK(sc); 2394 (*ifp->if_input)(ifp, m); 2395 AGE_LOCK(sc); 2396 2397 /* Reset mbuf chains. */ 2398 AGE_RXCHAIN_RESET(sc); 2399 } 2400 } 2401 2402 if (count != nsegs) { 2403 sc->age_cdata.age_rx_cons += nsegs; 2404 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2405 } else 2406 sc->age_cdata.age_rx_cons = rx_cons; 2407} 2408 2409static int 2410age_rxintr(struct age_softc *sc, int rr_prod, int count) 2411{ 2412 struct rx_rdesc *rxrd; 2413 int rr_cons, nsegs, pktlen, prog; 2414 2415 AGE_LOCK_ASSERT(sc); 2416 2417 rr_cons = sc->age_cdata.age_rr_cons; 2418 if (rr_cons == rr_prod) 2419 return (0); 2420 2421 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2422 sc->age_cdata.age_rr_ring_map, 2423 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2424 2425 for (prog = 0; rr_cons != rr_prod; prog++) { 2426 if (count <= 0) 2427 break; 2428 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2429 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2430 if (nsegs == 0) 2431 break; 2432 /* 2433 * Check number of segments against received bytes. 2434 * Non-matching value would indicate that hardware 2435 * is still trying to update Rx return descriptors. 2436 * I'm not sure whether this check is really needed. 2437 */ 2438 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2439 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 2440 (MCLBYTES - ETHER_ALIGN))) 2441 break; 2442 2443 prog++; 2444 /* Received a frame. */ 2445 age_rxeof(sc, rxrd); 2446 /* Clear return ring. */ 2447 rxrd->index = 0; 2448 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2449 } 2450 2451 if (prog > 0) { 2452 /* Update the consumer index. */ 2453 sc->age_cdata.age_rr_cons = rr_cons; 2454 2455 /* Sync descriptors. */ 2456 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2457 sc->age_cdata.age_rr_ring_map, 2458 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2459 2460 /* Notify hardware availability of new Rx buffers. */ 2461 AGE_COMMIT_MBOX(sc); 2462 } 2463 2464 return (count > 0 ? 0 : EAGAIN); 2465} 2466 2467static void 2468age_tick(void *arg) 2469{ 2470 struct age_softc *sc; 2471 struct mii_data *mii; 2472 2473 sc = (struct age_softc *)arg; 2474 2475 AGE_LOCK_ASSERT(sc); 2476 2477 mii = device_get_softc(sc->age_miibus); 2478 mii_tick(mii); 2479 age_watchdog(sc); 2480 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2481} 2482 2483static void 2484age_reset(struct age_softc *sc) 2485{ 2486 uint32_t reg; 2487 int i; 2488 2489 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2490 CSR_READ_4(sc, AGE_MASTER_CFG); 2491 DELAY(1000); 2492 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2493 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2494 break; 2495 DELAY(10); 2496 } 2497 2498 if (i == 0) 2499 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2500 /* Initialize PCIe module. From Linux. */ 2501 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2502 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2503} 2504 2505static void 2506age_init(void *xsc) 2507{ 2508 struct age_softc *sc; 2509 2510 sc = (struct age_softc *)xsc; 2511 AGE_LOCK(sc); 2512 age_init_locked(sc); 2513 AGE_UNLOCK(sc); 2514} 2515 2516static void 2517age_init_locked(struct age_softc *sc) 2518{ 2519 struct ifnet *ifp; 2520 struct mii_data *mii; 2521 uint8_t eaddr[ETHER_ADDR_LEN]; 2522 bus_addr_t paddr; 2523 uint32_t reg, fsize; 2524 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2525 int error; 2526 2527 AGE_LOCK_ASSERT(sc); 2528 2529 ifp = sc->age_ifp; 2530 mii = device_get_softc(sc->age_miibus); 2531 2532 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2533 return; 2534 2535 /* 2536 * Cancel any pending I/O. 2537 */ 2538 age_stop(sc); 2539 2540 /* 2541 * Reset the chip to a known state. 2542 */ 2543 age_reset(sc); 2544 2545 /* Initialize descriptors. */ 2546 error = age_init_rx_ring(sc); 2547 if (error != 0) { 2548 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2549 age_stop(sc); 2550 return; 2551 } 2552 age_init_rr_ring(sc); 2553 age_init_tx_ring(sc); 2554 age_init_cmb_block(sc); 2555 age_init_smb_block(sc); 2556 2557 /* Reprogram the station address. */ 2558 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2559 CSR_WRITE_4(sc, AGE_PAR0, 2560 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2561 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2562 2563 /* Set descriptor base addresses. */ 2564 paddr = sc->age_rdata.age_tx_ring_paddr; 2565 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2566 paddr = sc->age_rdata.age_rx_ring_paddr; 2567 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2568 paddr = sc->age_rdata.age_rr_ring_paddr; 2569 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2570 paddr = sc->age_rdata.age_tx_ring_paddr; 2571 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2572 paddr = sc->age_rdata.age_cmb_block_paddr; 2573 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2574 paddr = sc->age_rdata.age_smb_block_paddr; 2575 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2576 /* Set Rx/Rx return descriptor counter. */ 2577 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2578 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2579 DESC_RRD_CNT_MASK) | 2580 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2581 /* Set Tx descriptor counter. */ 2582 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2583 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2584 2585 /* Tell hardware that we're ready to load descriptors. */ 2586 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2587 2588 /* 2589 * Initialize mailbox register. 2590 * Updated producer/consumer index information is exchanged 2591 * through this mailbox register. However Tx producer and 2592 * Rx return consumer/Rx producer are all shared such that 2593 * it's hard to separate code path between Tx and Rx without 2594 * locking. If L1 hardware have a separate mail box register 2595 * for Tx and Rx consumer/producer management we could have 2596 * indepent Tx/Rx handler which in turn Rx handler could have 2597 * been run without any locking. 2598 */ 2599 AGE_COMMIT_MBOX(sc); 2600 2601 /* Configure IPG/IFG parameters. */ 2602 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2603 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2604 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2605 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2606 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2607 2608 /* Set parameters for half-duplex media. */ 2609 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2610 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2611 HDPX_CFG_LCOL_MASK) | 2612 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2613 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2614 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2615 HDPX_CFG_ABEBT_MASK) | 2616 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2617 HDPX_CFG_JAMIPG_MASK)); 2618 2619 /* Configure interrupt moderation timer. */ 2620 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2621 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2622 reg &= ~MASTER_MTIMER_ENB; 2623 if (AGE_USECS(sc->age_int_mod) == 0) 2624 reg &= ~MASTER_ITIMER_ENB; 2625 else 2626 reg |= MASTER_ITIMER_ENB; 2627 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2628 if (bootverbose) 2629 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2630 sc->age_int_mod); 2631 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2632 2633 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2634 if (ifp->if_mtu < ETHERMTU) 2635 sc->age_max_frame_size = ETHERMTU; 2636 else 2637 sc->age_max_frame_size = ifp->if_mtu; 2638 sc->age_max_frame_size += ETHER_HDR_LEN + 2639 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2640 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2641 /* Configure jumbo frame. */ 2642 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2643 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2644 (((fsize / sizeof(uint64_t)) << 2645 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2646 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2647 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2648 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2649 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2650 2651 /* Configure flow-control parameters. From Linux. */ 2652 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2653 /* 2654 * Magic workaround for old-L1. 2655 * Don't know which hw revision requires this magic. 2656 */ 2657 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2658 /* 2659 * Another magic workaround for flow-control mode 2660 * change. From Linux. 2661 */ 2662 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2663 } 2664 /* 2665 * TODO 2666 * Should understand pause parameter relationships between FIFO 2667 * size and number of Rx descriptors and Rx return descriptors. 2668 * 2669 * Magic parameters came from Linux. 2670 */ 2671 switch (sc->age_chip_rev) { 2672 case 0x8001: 2673 case 0x9001: 2674 case 0x9002: 2675 case 0x9003: 2676 rxf_hi = AGE_RX_RING_CNT / 16; 2677 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2678 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2679 rrd_lo = AGE_RR_RING_CNT / 16; 2680 break; 2681 default: 2682 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2683 rxf_lo = reg / 16; 2684 if (rxf_lo < 192) 2685 rxf_lo = 192; 2686 rxf_hi = (reg * 7) / 8; 2687 if (rxf_hi < rxf_lo) 2688 rxf_hi = rxf_lo + 16; 2689 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2690 rrd_lo = reg / 8; 2691 rrd_hi = (reg * 7) / 8; 2692 if (rrd_lo < 2) 2693 rrd_lo = 2; 2694 if (rrd_hi < rrd_lo) 2695 rrd_hi = rrd_lo + 3; 2696 break; 2697 } 2698 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2699 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2700 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2701 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2702 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2703 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2704 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2705 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2706 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2707 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2708 2709 /* Configure RxQ. */ 2710 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2711 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2712 RXQ_CFG_RD_BURST_MASK) | 2713 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2714 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2715 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2716 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2717 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2718 2719 /* Configure TxQ. */ 2720 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2721 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2722 TXQ_CFG_TPD_BURST_MASK) | 2723 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2724 TXQ_CFG_TX_FIFO_BURST_MASK) | 2725 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2726 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2727 TXQ_CFG_ENB); 2728 2729 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2730 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2731 TX_JUMBO_TPD_TH_MASK) | 2732 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2733 TX_JUMBO_TPD_IPG_MASK)); 2734 /* Configure DMA parameters. */ 2735 CSR_WRITE_4(sc, AGE_DMA_CFG, 2736 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2737 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2738 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2739 2740 /* Configure CMB DMA write threshold. */ 2741 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2742 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2743 CMB_WR_THRESH_RRD_MASK) | 2744 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2745 CMB_WR_THRESH_TPD_MASK)); 2746 2747 /* Set CMB/SMB timer and enable them. */ 2748 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2749 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2750 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2751 /* Request SMB updates for every seconds. */ 2752 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2753 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2754 2755 /* 2756 * Disable all WOL bits as WOL can interfere normal Rx 2757 * operation. 2758 */ 2759 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2760 2761 /* 2762 * Configure Tx/Rx MACs. 2763 * - Auto-padding for short frames. 2764 * - Enable CRC generation. 2765 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2766 * of MAC is followed after link establishment. 2767 */ 2768 CSR_WRITE_4(sc, AGE_MAC_CFG, 2769 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2770 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2771 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2772 MAC_CFG_PREAMBLE_MASK)); 2773 /* Set up the receive filter. */ 2774 age_rxfilter(sc); 2775 age_rxvlan(sc); 2776 2777 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2778 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2779 reg |= MAC_CFG_RXCSUM_ENB; 2780 2781 /* Ack all pending interrupts and clear it. */ 2782 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2783 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2784 2785 /* Finally enable Tx/Rx MAC. */ 2786 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2787 2788 sc->age_flags &= ~AGE_FLAG_LINK; 2789 /* Switch to the current media. */ 2790 mii_mediachg(mii); 2791 2792 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2793 2794 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2795 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2796} 2797 2798static void 2799age_stop(struct age_softc *sc) 2800{ 2801 struct ifnet *ifp; 2802 struct age_txdesc *txd; 2803 struct age_rxdesc *rxd; 2804 uint32_t reg; 2805 int i; 2806 2807 AGE_LOCK_ASSERT(sc); 2808 /* 2809 * Mark the interface down and cancel the watchdog timer. 2810 */ 2811 ifp = sc->age_ifp; 2812 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2813 sc->age_flags &= ~AGE_FLAG_LINK; 2814 callout_stop(&sc->age_tick_ch); 2815 sc->age_watchdog_timer = 0; 2816 2817 /* 2818 * Disable interrupts. 2819 */ 2820 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2821 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2822 /* Stop CMB/SMB updates. */ 2823 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2824 /* Stop Rx/Tx MAC. */ 2825 age_stop_rxmac(sc); 2826 age_stop_txmac(sc); 2827 /* Stop DMA. */ 2828 CSR_WRITE_4(sc, AGE_DMA_CFG, 2829 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2830 /* Stop TxQ/RxQ. */ 2831 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2832 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2833 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2834 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2835 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2836 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2837 break; 2838 DELAY(10); 2839 } 2840 if (i == 0) 2841 device_printf(sc->age_dev, 2842 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2843 2844 /* Reclaim Rx buffers that have been processed. */ 2845 if (sc->age_cdata.age_rxhead != NULL) 2846 m_freem(sc->age_cdata.age_rxhead); 2847 AGE_RXCHAIN_RESET(sc); 2848 /* 2849 * Free RX and TX mbufs still in the queues. 2850 */ 2851 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2852 rxd = &sc->age_cdata.age_rxdesc[i]; 2853 if (rxd->rx_m != NULL) { 2854 bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2855 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2856 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2857 rxd->rx_dmamap); 2858 m_freem(rxd->rx_m); 2859 rxd->rx_m = NULL; 2860 } 2861 } 2862 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2863 txd = &sc->age_cdata.age_txdesc[i]; 2864 if (txd->tx_m != NULL) { 2865 bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2866 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2867 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2868 txd->tx_dmamap); 2869 m_freem(txd->tx_m); 2870 txd->tx_m = NULL; 2871 } 2872 } 2873} 2874 2875static void 2876age_stop_txmac(struct age_softc *sc) 2877{ 2878 uint32_t reg; 2879 int i; 2880 2881 AGE_LOCK_ASSERT(sc); 2882 2883 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2884 if ((reg & MAC_CFG_TX_ENB) != 0) { 2885 reg &= ~MAC_CFG_TX_ENB; 2886 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2887 } 2888 /* Stop Tx DMA engine. */ 2889 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2890 if ((reg & DMA_CFG_RD_ENB) != 0) { 2891 reg &= ~DMA_CFG_RD_ENB; 2892 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2893 } 2894 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2895 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2896 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2897 break; 2898 DELAY(10); 2899 } 2900 if (i == 0) 2901 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2902} 2903 2904static void 2905age_stop_rxmac(struct age_softc *sc) 2906{ 2907 uint32_t reg; 2908 int i; 2909 2910 AGE_LOCK_ASSERT(sc); 2911 2912 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2913 if ((reg & MAC_CFG_RX_ENB) != 0) { 2914 reg &= ~MAC_CFG_RX_ENB; 2915 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2916 } 2917 /* Stop Rx DMA engine. */ 2918 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2919 if ((reg & DMA_CFG_WR_ENB) != 0) { 2920 reg &= ~DMA_CFG_WR_ENB; 2921 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2922 } 2923 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2924 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2925 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2926 break; 2927 DELAY(10); 2928 } 2929 if (i == 0) 2930 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2931} 2932 2933static void 2934age_init_tx_ring(struct age_softc *sc) 2935{ 2936 struct age_ring_data *rd; 2937 struct age_txdesc *txd; 2938 int i; 2939 2940 AGE_LOCK_ASSERT(sc); 2941 2942 sc->age_cdata.age_tx_prod = 0; 2943 sc->age_cdata.age_tx_cons = 0; 2944 sc->age_cdata.age_tx_cnt = 0; 2945 2946 rd = &sc->age_rdata; 2947 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2948 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2949 txd = &sc->age_cdata.age_txdesc[i]; 2950 txd->tx_desc = &rd->age_tx_ring[i]; 2951 txd->tx_m = NULL; 2952 } 2953 2954 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2955 sc->age_cdata.age_tx_ring_map, 2956 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2957} 2958 2959static int 2960age_init_rx_ring(struct age_softc *sc) 2961{ 2962 struct age_ring_data *rd; 2963 struct age_rxdesc *rxd; 2964 int i; 2965 2966 AGE_LOCK_ASSERT(sc); 2967 2968 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2969 sc->age_morework = 0; 2970 rd = &sc->age_rdata; 2971 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2972 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2973 rxd = &sc->age_cdata.age_rxdesc[i]; 2974 rxd->rx_m = NULL; 2975 rxd->rx_desc = &rd->age_rx_ring[i]; 2976 if (age_newbuf(sc, rxd) != 0) 2977 return (ENOBUFS); 2978 } 2979 2980 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2981 sc->age_cdata.age_rx_ring_map, 2982 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2983 2984 return (0); 2985} 2986 2987static void 2988age_init_rr_ring(struct age_softc *sc) 2989{ 2990 struct age_ring_data *rd; 2991 2992 AGE_LOCK_ASSERT(sc); 2993 2994 sc->age_cdata.age_rr_cons = 0; 2995 AGE_RXCHAIN_RESET(sc); 2996 2997 rd = &sc->age_rdata; 2998 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 2999 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3000 sc->age_cdata.age_rr_ring_map, 3001 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3002} 3003 3004static void 3005age_init_cmb_block(struct age_softc *sc) 3006{ 3007 struct age_ring_data *rd; 3008 3009 AGE_LOCK_ASSERT(sc); 3010 3011 rd = &sc->age_rdata; 3012 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3013 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3014 sc->age_cdata.age_cmb_block_map, 3015 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3016} 3017 3018static void 3019age_init_smb_block(struct age_softc *sc) 3020{ 3021 struct age_ring_data *rd; 3022 3023 AGE_LOCK_ASSERT(sc); 3024 3025 rd = &sc->age_rdata; 3026 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3027 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3028 sc->age_cdata.age_smb_block_map, 3029 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3030} 3031 3032static int 3033age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3034{ 3035 struct rx_desc *desc; 3036 struct mbuf *m; 3037 bus_dma_segment_t segs[1]; 3038 bus_dmamap_t map; 3039 int nsegs; 3040 3041 AGE_LOCK_ASSERT(sc); 3042 3043 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3044 if (m == NULL) 3045 return (ENOBUFS); 3046 m->m_len = m->m_pkthdr.len = MCLBYTES; 3047 m_adj(m, ETHER_ALIGN); 3048 3049 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3050 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3051 m_freem(m); 3052 return (ENOBUFS); 3053 } 3054 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3055 3056 if (rxd->rx_m != NULL) { 3057 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3058 BUS_DMASYNC_POSTREAD); 3059 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3060 } 3061 map = rxd->rx_dmamap; 3062 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3063 sc->age_cdata.age_rx_sparemap = map; 3064 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3065 BUS_DMASYNC_PREREAD); 3066 rxd->rx_m = m; 3067 3068 desc = rxd->rx_desc; 3069 desc->addr = htole64(segs[0].ds_addr); 3070 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3071 AGE_RD_LEN_SHIFT); 3072 return (0); 3073} 3074 3075static void 3076age_rxvlan(struct age_softc *sc) 3077{ 3078 struct ifnet *ifp; 3079 uint32_t reg; 3080 3081 AGE_LOCK_ASSERT(sc); 3082 3083 ifp = sc->age_ifp; 3084 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3085 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3086 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3087 reg |= MAC_CFG_VLAN_TAG_STRIP; 3088 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3089} 3090 3091static void 3092age_rxfilter(struct age_softc *sc) 3093{ 3094 struct ifnet *ifp; 3095 struct ifmultiaddr *ifma; 3096 uint32_t crc; 3097 uint32_t mchash[2]; 3098 uint32_t rxcfg; 3099 3100 AGE_LOCK_ASSERT(sc); 3101 3102 ifp = sc->age_ifp; 3103 3104 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3105 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3106 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3107 rxcfg |= MAC_CFG_BCAST; 3108 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3109 if ((ifp->if_flags & IFF_PROMISC) != 0) 3110 rxcfg |= MAC_CFG_PROMISC; 3111 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3112 rxcfg |= MAC_CFG_ALLMULTI; 3113 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3114 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3115 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3116 return; 3117 } 3118 3119 /* Program new filter. */ 3120 bzero(mchash, sizeof(mchash)); 3121 3122 if_maddr_rlock(ifp); 3123 TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) { 3124 if (ifma->ifma_addr->sa_family != AF_LINK) 3125 continue; 3126 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3127 ifma->ifma_addr), ETHER_ADDR_LEN); 3128 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3129 } 3130 if_maddr_runlock(ifp); 3131 3132 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3133 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3134 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3135} 3136 3137static int 3138sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3139{ 3140 struct age_softc *sc; 3141 struct age_stats *stats; 3142 int error, result; 3143 3144 result = -1; 3145 error = sysctl_handle_int(oidp, &result, 0, req); 3146 3147 if (error != 0 || req->newptr == NULL) 3148 return (error); 3149 3150 if (result != 1) 3151 return (error); 3152 3153 sc = (struct age_softc *)arg1; 3154 stats = &sc->age_stat; 3155 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3156 printf("Transmit good frames : %ju\n", 3157 (uintmax_t)stats->tx_frames); 3158 printf("Transmit good broadcast frames : %ju\n", 3159 (uintmax_t)stats->tx_bcast_frames); 3160 printf("Transmit good multicast frames : %ju\n", 3161 (uintmax_t)stats->tx_mcast_frames); 3162 printf("Transmit pause control frames : %u\n", 3163 stats->tx_pause_frames); 3164 printf("Transmit control frames : %u\n", 3165 stats->tx_control_frames); 3166 printf("Transmit frames with excessive deferrals : %u\n", 3167 stats->tx_excess_defer); 3168 printf("Transmit deferrals : %u\n", 3169 stats->tx_deferred); 3170 printf("Transmit good octets : %ju\n", 3171 (uintmax_t)stats->tx_bytes); 3172 printf("Transmit good broadcast octets : %ju\n", 3173 (uintmax_t)stats->tx_bcast_bytes); 3174 printf("Transmit good multicast octets : %ju\n", 3175 (uintmax_t)stats->tx_mcast_bytes); 3176 printf("Transmit frames 64 bytes : %ju\n", 3177 (uintmax_t)stats->tx_pkts_64); 3178 printf("Transmit frames 65 to 127 bytes : %ju\n", 3179 (uintmax_t)stats->tx_pkts_65_127); 3180 printf("Transmit frames 128 to 255 bytes : %ju\n", 3181 (uintmax_t)stats->tx_pkts_128_255); 3182 printf("Transmit frames 256 to 511 bytes : %ju\n", 3183 (uintmax_t)stats->tx_pkts_256_511); 3184 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3185 (uintmax_t)stats->tx_pkts_512_1023); 3186 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3187 (uintmax_t)stats->tx_pkts_1024_1518); 3188 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3189 (uintmax_t)stats->tx_pkts_1519_max); 3190 printf("Transmit single collisions : %u\n", 3191 stats->tx_single_colls); 3192 printf("Transmit multiple collisions : %u\n", 3193 stats->tx_multi_colls); 3194 printf("Transmit late collisions : %u\n", 3195 stats->tx_late_colls); 3196 printf("Transmit abort due to excessive collisions : %u\n", 3197 stats->tx_excess_colls); 3198 printf("Transmit underruns due to FIFO underruns : %u\n", 3199 stats->tx_underrun); 3200 printf("Transmit descriptor write-back errors : %u\n", 3201 stats->tx_desc_underrun); 3202 printf("Transmit frames with length mismatched frame size : %u\n", 3203 stats->tx_lenerrs); 3204 printf("Transmit frames with truncated due to MTU size : %u\n", 3205 stats->tx_lenerrs); 3206 3207 printf("Receive good frames : %ju\n", 3208 (uintmax_t)stats->rx_frames); 3209 printf("Receive good broadcast frames : %ju\n", 3210 (uintmax_t)stats->rx_bcast_frames); 3211 printf("Receive good multicast frames : %ju\n", 3212 (uintmax_t)stats->rx_mcast_frames); 3213 printf("Receive pause control frames : %u\n", 3214 stats->rx_pause_frames); 3215 printf("Receive control frames : %u\n", 3216 stats->rx_control_frames); 3217 printf("Receive CRC errors : %u\n", 3218 stats->rx_crcerrs); 3219 printf("Receive frames with length errors : %u\n", 3220 stats->rx_lenerrs); 3221 printf("Receive good octets : %ju\n", 3222 (uintmax_t)stats->rx_bytes); 3223 printf("Receive good broadcast octets : %ju\n", 3224 (uintmax_t)stats->rx_bcast_bytes); 3225 printf("Receive good multicast octets : %ju\n", 3226 (uintmax_t)stats->rx_mcast_bytes); 3227 printf("Receive frames too short : %u\n", 3228 stats->rx_runts); 3229 printf("Receive fragmented frames : %ju\n", 3230 (uintmax_t)stats->rx_fragments); 3231 printf("Receive frames 64 bytes : %ju\n", 3232 (uintmax_t)stats->rx_pkts_64); 3233 printf("Receive frames 65 to 127 bytes : %ju\n", 3234 (uintmax_t)stats->rx_pkts_65_127); 3235 printf("Receive frames 128 to 255 bytes : %ju\n", 3236 (uintmax_t)stats->rx_pkts_128_255); 3237 printf("Receive frames 256 to 511 bytes : %ju\n", 3238 (uintmax_t)stats->rx_pkts_256_511); 3239 printf("Receive frames 512 to 1024 bytes : %ju\n", 3240 (uintmax_t)stats->rx_pkts_512_1023); 3241 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3242 (uintmax_t)stats->rx_pkts_1024_1518); 3243 printf("Receive frames 1519 to MTU bytes : %ju\n", 3244 (uintmax_t)stats->rx_pkts_1519_max); 3245 printf("Receive frames too long : %ju\n", 3246 (uint64_t)stats->rx_pkts_truncated); 3247 printf("Receive frames with FIFO overflow : %u\n", 3248 stats->rx_fifo_oflows); 3249 printf("Receive frames with return descriptor overflow : %u\n", 3250 stats->rx_desc_oflows); 3251 printf("Receive frames with alignment errors : %u\n", 3252 stats->rx_alignerrs); 3253 printf("Receive frames dropped due to address filtering : %ju\n", 3254 (uint64_t)stats->rx_pkts_filtered); 3255 3256 return (error); 3257} 3258 3259static int 3260sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3261{ 3262 int error, value; 3263 3264 if (arg1 == NULL) 3265 return (EINVAL); 3266 value = *(int *)arg1; 3267 error = sysctl_handle_int(oidp, &value, 0, req); 3268 if (error || req->newptr == NULL) 3269 return (error); 3270 if (value < low || value > high) 3271 return (EINVAL); 3272 *(int *)arg1 = value; 3273 3274 return (0); 3275} 3276 3277static int 3278sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3279{ 3280 return (sysctl_int_range(oidp, arg1, arg2, req, 3281 AGE_PROC_MIN, AGE_PROC_MAX)); 3282} 3283 3284static int 3285sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3286{ 3287 3288 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3289 AGE_IM_TIMER_MAX)); 3290} 3291