if_age.c revision 180580
1132904Spjd/*- 2132904Spjd * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3132904Spjd * All rights reserved. 4132904Spjd * 5132904Spjd * Redistribution and use in source and binary forms, with or without 6132904Spjd * modification, are permitted provided that the following conditions 7132904Spjd * are met: 8132904Spjd * 1. Redistributions of source code must retain the above copyright 9132904Spjd * notice unmodified, this list of conditions, and the following 10132904Spjd * disclaimer. 11132904Spjd * 2. Redistributions in binary form must reproduce the above copyright 12132904Spjd * notice, this list of conditions and the following disclaimer in the 13132904Spjd * documentation and/or other materials provided with the distribution. 14132904Spjd * 15132904Spjd * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16132904Spjd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17132904Spjd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18132904Spjd * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19132904Spjd * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20132904Spjd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21132904Spjd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22132904Spjd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23132904Spjd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24132904Spjd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25132904Spjd * SUCH DAMAGE. 26132904Spjd */ 27132904Spjd 28132904Spjd/* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 29132904Spjd 30132904Spjd#include <sys/cdefs.h> 31132904Spjd__FBSDID("$FreeBSD: head/sys/dev/age/if_age.c 180580 2008-07-18 01:00:54Z yongari $"); 32132904Spjd 33132904Spjd#include <sys/param.h> 34132904Spjd#include <sys/systm.h> 35132904Spjd#include <sys/bus.h> 36132904Spjd#include <sys/endian.h> 37132904Spjd#include <sys/kernel.h> 38132904Spjd#include <sys/malloc.h> 39132904Spjd#include <sys/mbuf.h> 40132904Spjd#include <sys/rman.h> 41132904Spjd#include <sys/module.h> 42132904Spjd#include <sys/queue.h> 43132904Spjd#include <sys/socket.h> 44132904Spjd#include <sys/sockio.h> 45132904Spjd#include <sys/sysctl.h> 46132904Spjd#include <sys/taskqueue.h> 47132904Spjd 48132904Spjd#include <net/bpf.h> 49132904Spjd#include <net/if.h> 50132904Spjd#include <net/if_arp.h> 51132904Spjd#include <net/ethernet.h> 52132904Spjd#include <net/if_dl.h> 53132904Spjd#include <net/if_media.h> 54132904Spjd#include <net/if_types.h> 55132904Spjd#include <net/if_vlan_var.h> 56132904Spjd 57132904Spjd#include <netinet/in.h> 58132904Spjd#include <netinet/in_systm.h> 59132904Spjd#include <netinet/ip.h> 60132904Spjd#include <netinet/tcp.h> 61132904Spjd 62132904Spjd#include <dev/mii/mii.h> 63132904Spjd#include <dev/mii/miivar.h> 64132904Spjd 65132904Spjd#include <dev/pci/pcireg.h> 66132904Spjd#include <dev/pci/pcivar.h> 67132904Spjd 68132904Spjd#include <machine/bus.h> 69132904Spjd#include <machine/in_cksum.h> 70132904Spjd 71132904Spjd#include <dev/age/if_agereg.h> 72132904Spjd#include <dev/age/if_agevar.h> 73132904Spjd 74132904Spjd/* "device miibus" required. See GENERIC if you get errors here. */ 75132904Spjd#include "miibus_if.h" 76132904Spjd 77132904Spjd#ifndef IFCAP_VLAN_HWTSO 78132904Spjd#define IFCAP_VLAN_HWTSO 0 79132904Spjd#endif 80132904Spjd#define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81132904Spjd 82132904SpjdMODULE_DEPEND(age, pci, 1, 1, 1); 83132904SpjdMODULE_DEPEND(age, ether, 1, 1, 1); 84132904SpjdMODULE_DEPEND(age, miibus, 1, 1, 1); 85132904Spjd 86132904Spjd/* Tunables. */ 87132904Spjdstatic int msi_disable = 0; 88132904Spjdstatic int msix_disable = 0; 89132904SpjdTUNABLE_INT("hw.age.msi_disable", &msi_disable); 90132904SpjdTUNABLE_INT("hw.age.msix_disable", &msix_disable); 91132904Spjd 92132904Spjd/* 93132904Spjd * Devices supported by this driver. 94132904Spjd */ 95132904Spjdstatic struct age_dev { 96132904Spjd uint16_t age_vendorid; 97132904Spjd uint16_t age_deviceid; 98132904Spjd const char *age_name; 99132904Spjd} age_devs[] = { 100132904Spjd { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 101132904Spjd "Attansic Technology Corp, L1 Gigabit Ethernet" }, 102132904Spjd}; 103132904Spjd 104132904Spjdstatic int age_miibus_readreg(device_t, int, int); 105132904Spjdstatic int age_miibus_writereg(device_t, int, int, int); 106132904Spjdstatic void age_miibus_statchg(device_t); 107132904Spjdstatic void age_mediastatus(struct ifnet *, struct ifmediareq *); 108132904Spjdstatic int age_mediachange(struct ifnet *); 109132904Spjdstatic int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, 110132904Spjd uint32_t *); 111132904Spjdstatic int age_probe(device_t); 112132904Spjdstatic void age_get_macaddr(struct age_softc *); 113132904Spjdstatic void age_phy_reset(struct age_softc *); 114132904Spjdstatic int age_attach(device_t); 115132904Spjdstatic int age_detach(device_t); 116132904Spjdstatic void age_sysctl_node(struct age_softc *); 117132904Spjdstatic void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 118132904Spjdstatic int age_check_boundary(struct age_softc *); 119132904Spjdstatic int age_dma_alloc(struct age_softc *); 120132904Spjdstatic void age_dma_free(struct age_softc *); 121132904Spjdstatic int age_shutdown(device_t); 122132904Spjdstatic void age_setwol(struct age_softc *); 123132904Spjdstatic int age_suspend(device_t); 124132904Spjdstatic int age_resume(device_t); 125132904Spjdstatic int age_encap(struct age_softc *, struct mbuf **); 126132904Spjdstatic void age_tx_task(void *, int); 127132904Spjdstatic void age_start(struct ifnet *); 128132904Spjdstatic void age_watchdog(struct age_softc *); 129132904Spjdstatic int age_ioctl(struct ifnet *, u_long, caddr_t); 130132904Spjdstatic void age_mac_config(struct age_softc *); 131132904Spjdstatic void age_link_task(void *, int); 132132904Spjdstatic void age_stats_update(struct age_softc *); 133132904Spjdstatic int age_intr(void *); 134132904Spjdstatic void age_int_task(void *, int); 135132904Spjdstatic void age_txintr(struct age_softc *, int); 136132904Spjdstatic void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 137132904Spjdstatic int age_rxintr(struct age_softc *, int, int); 138132904Spjdstatic void age_tick(void *); 139132904Spjdstatic void age_reset(struct age_softc *); 140132904Spjdstatic void age_init(void *); 141132904Spjdstatic void age_init_locked(struct age_softc *); 142132904Spjdstatic void age_stop(struct age_softc *); 143132904Spjdstatic void age_stop_txmac(struct age_softc *); 144132904Spjdstatic void age_stop_rxmac(struct age_softc *); 145132904Spjdstatic void age_init_tx_ring(struct age_softc *); 146132904Spjdstatic int age_init_rx_ring(struct age_softc *); 147132904Spjdstatic void age_init_rr_ring(struct age_softc *); 148132904Spjdstatic void age_init_cmb_block(struct age_softc *); 149132904Spjdstatic void age_init_smb_block(struct age_softc *); 150132904Spjdstatic int age_newbuf(struct age_softc *, struct age_rxdesc *); 151132904Spjdstatic void age_rxvlan(struct age_softc *); 152132904Spjdstatic void age_rxfilter(struct age_softc *); 153132904Spjdstatic int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 154132904Spjdstatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 155132904Spjdstatic int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 156132904Spjdstatic int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 157132904Spjd 158132904Spjd 159132904Spjdstatic device_method_t age_methods[] = { 160132904Spjd /* Device interface. */ 161132904Spjd DEVMETHOD(device_probe, age_probe), 162132904Spjd DEVMETHOD(device_attach, age_attach), 163132904Spjd DEVMETHOD(device_detach, age_detach), 164132904Spjd DEVMETHOD(device_shutdown, age_shutdown), 165132904Spjd DEVMETHOD(device_suspend, age_suspend), 166132904Spjd DEVMETHOD(device_resume, age_resume), 167132904Spjd 168132904Spjd /* MII interface. */ 169132904Spjd DEVMETHOD(miibus_readreg, age_miibus_readreg), 170132904Spjd DEVMETHOD(miibus_writereg, age_miibus_writereg), 171132904Spjd DEVMETHOD(miibus_statchg, age_miibus_statchg), 172132904Spjd 173132904Spjd { NULL, NULL } 174132904Spjd}; 175132904Spjd 176132904Spjdstatic driver_t age_driver = { 177132904Spjd "age", 178132904Spjd age_methods, 179132904Spjd sizeof(struct age_softc) 180132904Spjd}; 181132904Spjd 182132904Spjdstatic devclass_t age_devclass; 183132904Spjd 184132904SpjdDRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0); 185132904SpjdDRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); 186132904Spjd 187132904Spjdstatic struct resource_spec age_res_spec_mem[] = { 188132904Spjd { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 189132904Spjd { -1, 0, 0 } 190132904Spjd}; 191132904Spjd 192132904Spjdstatic struct resource_spec age_irq_spec_legacy[] = { 193132904Spjd { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 194132904Spjd { -1, 0, 0 } 195132904Spjd}; 196132904Spjd 197132904Spjdstatic struct resource_spec age_irq_spec_msi[] = { 198132904Spjd { SYS_RES_IRQ, 1, RF_ACTIVE }, 199132904Spjd { -1, 0, 0 } 200132904Spjd}; 201132904Spjd 202132904Spjdstatic struct resource_spec age_irq_spec_msix[] = { 203132904Spjd { SYS_RES_IRQ, 1, RF_ACTIVE }, 204132904Spjd { -1, 0, 0 } 205132904Spjd}; 206132904Spjd 207132904Spjd/* 208132904Spjd * Read a PHY register on the MII of the L1. 209132904Spjd */ 210132904Spjdstatic int 211132904Spjdage_miibus_readreg(device_t dev, int phy, int reg) 212132904Spjd{ 213132904Spjd struct age_softc *sc; 214132904Spjd uint32_t v; 215132904Spjd int i; 216132904Spjd 217132904Spjd sc = device_get_softc(dev); 218132904Spjd if (phy != sc->age_phyaddr) 219132904Spjd return (0); 220132904Spjd 221132904Spjd CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 222132904Spjd MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 223132904Spjd for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 224132904Spjd DELAY(1); 225132904Spjd v = CSR_READ_4(sc, AGE_MDIO); 226132904Spjd if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 227132904Spjd break; 228132904Spjd } 229132904Spjd 230132904Spjd if (i == 0) { 231132904Spjd device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 232132904Spjd return (0); 233132904Spjd } 234132904Spjd 235132904Spjd return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 236132904Spjd} 237132904Spjd 238132904Spjd/* 239132904Spjd * Write a PHY register on the MII of the L1. 240132904Spjd */ 241132904Spjdstatic int 242132904Spjdage_miibus_writereg(device_t dev, int phy, int reg, int val) 243132904Spjd{ 244132904Spjd struct age_softc *sc; 245132904Spjd uint32_t v; 246132904Spjd int i; 247132904Spjd 248132904Spjd sc = device_get_softc(dev); 249132904Spjd if (phy != sc->age_phyaddr) 250132904Spjd return (0); 251132904Spjd 252132904Spjd CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 253132904Spjd (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 254132904Spjd MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 255132904Spjd for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 256132904Spjd DELAY(1); 257132904Spjd v = CSR_READ_4(sc, AGE_MDIO); 258132904Spjd if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 259132904Spjd break; 260132904Spjd } 261132904Spjd 262132904Spjd if (i == 0) 263132904Spjd device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 264132904Spjd 265132904Spjd return (0); 266132904Spjd} 267132904Spjd 268132904Spjd/* 269132904Spjd * Callback from MII layer when media changes. 270132904Spjd */ 271132904Spjdstatic void 272132904Spjdage_miibus_statchg(device_t dev) 273132904Spjd{ 274132904Spjd struct age_softc *sc; 275132904Spjd 276132904Spjd sc = device_get_softc(dev); 277132904Spjd taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 278132904Spjd} 279132904Spjd 280132904Spjd/* 281132904Spjd * Get the current interface media status. 282132904Spjd */ 283132904Spjdstatic void 284132904Spjdage_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 285132904Spjd{ 286132904Spjd struct age_softc *sc; 287132904Spjd struct mii_data *mii; 288132904Spjd 289132904Spjd sc = ifp->if_softc; 290132904Spjd AGE_LOCK(sc); 291132904Spjd mii = device_get_softc(sc->age_miibus); 292132904Spjd 293132904Spjd mii_pollstat(mii); 294132904Spjd AGE_UNLOCK(sc); 295132904Spjd ifmr->ifm_status = mii->mii_media_status; 296132904Spjd ifmr->ifm_active = mii->mii_media_active; 297132904Spjd} 298132904Spjd 299132904Spjd/* 300132904Spjd * Set hardware to newly-selected media. 301132904Spjd */ 302132904Spjdstatic int 303132904Spjdage_mediachange(struct ifnet *ifp) 304132904Spjd{ 305132904Spjd struct age_softc *sc; 306132904Spjd struct mii_data *mii; 307132904Spjd struct mii_softc *miisc; 308132904Spjd int error; 309132904Spjd 310132904Spjd sc = ifp->if_softc; 311132904Spjd AGE_LOCK(sc); 312132904Spjd mii = device_get_softc(sc->age_miibus); 313132904Spjd if (mii->mii_instance != 0) { 314132904Spjd LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 315132904Spjd mii_phy_reset(miisc); 316132904Spjd } 317132904Spjd error = mii_mediachg(mii); 318132904Spjd AGE_UNLOCK(sc); 319132904Spjd 320132904Spjd return (error); 321132904Spjd} 322132904Spjd 323132904Spjdstatic int 324132904Spjdage_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 325132904Spjd uint32_t *word) 326132904Spjd{ 327132904Spjd int i; 328132904Spjd 329132904Spjd pci_write_config(sc->age_dev, vpdc + PCIR_VPD_ADDR, offset, 2); 330132904Spjd for (i = AGE_TIMEOUT; i > 0; i--) { 331132904Spjd DELAY(10); 332132904Spjd if ((pci_read_config(sc->age_dev, vpdc + PCIR_VPD_ADDR, 2) & 333132904Spjd 0x8000) == 0x8000) 334132904Spjd break; 335132904Spjd } 336132904Spjd if (i == 0) { 337132904Spjd device_printf(sc->age_dev, "VPD read timeout!\n"); 338132904Spjd *word = 0; 339132904Spjd return (ETIMEDOUT); 340132904Spjd } 341132904Spjd 342132904Spjd *word = pci_read_config(sc->age_dev, vpdc + PCIR_VPD_DATA, 4); 343132904Spjd return (0); 344132904Spjd} 345132904Spjd 346132904Spjdstatic int 347132904Spjdage_probe(device_t dev) 348132904Spjd{ 349132904Spjd struct age_dev *sp; 350132904Spjd int i; 351132904Spjd uint16_t vendor, devid; 352132904Spjd 353132904Spjd vendor = pci_get_vendor(dev); 354132904Spjd devid = pci_get_device(dev); 355132904Spjd sp = age_devs; 356132904Spjd for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]); 357132904Spjd i++, sp++) { 358132904Spjd if (vendor == sp->age_vendorid && 359132904Spjd devid == sp->age_deviceid) { 360132904Spjd device_set_desc(dev, sp->age_name); 361132904Spjd return (BUS_PROBE_DEFAULT); 362132904Spjd } 363132904Spjd } 364132904Spjd 365132904Spjd return (ENXIO); 366132904Spjd} 367132904Spjd 368132904Spjdstatic void 369132904Spjdage_get_macaddr(struct age_softc *sc) 370132904Spjd{ 371132904Spjd uint32_t ea[2], off, reg, word; 372132904Spjd int vpd_error, match, vpdc; 373132904Spjd 374132904Spjd reg = CSR_READ_4(sc, AGE_SPI_CTRL); 375132904Spjd if ((reg & SPI_VPD_ENB) != 0) { 376132904Spjd /* Get VPD stored in TWSI EEPROM. */ 377132904Spjd reg &= ~SPI_VPD_ENB; 378132904Spjd CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 379132904Spjd } 380132904Spjd 381132904Spjd vpd_error = 0; 382132904Spjd ea[0] = ea[1] = 0; 383132904Spjd if ((vpd_error = pci_find_extcap(sc->age_dev, PCIY_VPD, &vpdc)) == 0) { 384132904Spjd /* 385132904Spjd * PCI VPD capability exists, but it seems that it's 386132904Spjd * not in the standard form as stated in PCI VPD 387132904Spjd * specification such that driver could not use 388132904Spjd * pci_get_vpd_readonly(9) with keyword 'NA'. 389132904Spjd * Search VPD data starting at address 0x0100. The data 390132904Spjd * should be used as initializers to set AGE_PAR0, 391132904Spjd * AGE_PAR1 register including other PCI configuration 392132904Spjd * registers. 393132904Spjd */ 394132904Spjd word = 0; 395132904Spjd match = 0; 396132904Spjd reg = 0; 397132904Spjd for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 398132904Spjd off += sizeof(uint32_t)) { 399132904Spjd vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 400132904Spjd if (vpd_error != 0) 401132904Spjd break; 402132904Spjd if (match != 0) { 403132904Spjd switch (reg) { 404132904Spjd case AGE_PAR0: 405132904Spjd ea[0] = word; 406132904Spjd break; 407132904Spjd case AGE_PAR1: 408132904Spjd ea[1] = word; 409132904Spjd break; 410132904Spjd default: 411132904Spjd break; 412132904Spjd } 413132904Spjd match = 0; 414132904Spjd } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 415132904Spjd match = 1; 416132904Spjd reg = word >> 16; 417132904Spjd } else 418132904Spjd break; 419132904Spjd } 420133114Spjd if (off >= AGE_VPD_REG_CONF_END) 421133114Spjd vpd_error = ENOENT; 422132904Spjd if (vpd_error == 0) { 423132904Spjd /* 424132904Spjd * Don't blindly trust ethernet address obtained 425132904Spjd * from VPD. Check whether ethernet address is 426132904Spjd * valid one. Otherwise fall-back to reading 427132904Spjd * PAR register. 428132904Spjd */ 429132904Spjd ea[1] &= 0xFFFF; 430132904Spjd if ((ea[0] == 0 && ea[1] == 0) || 431132904Spjd (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 432132904Spjd if (1 || bootverbose) 433132904Spjd device_printf(sc->age_dev, 434132904Spjd "invalid ethernet address " 435132904Spjd "returned from VPD.\n"); 436132922Spjd vpd_error = EINVAL; 437132904Spjd } 438132904Spjd } 439132904Spjd if (vpd_error != 0 && (1 || bootverbose)) 440132904Spjd device_printf(sc->age_dev, "VPD access failure!\n"); 441132904Spjd } else { 442132904Spjd if (1 || bootverbose) 443132904Spjd device_printf(sc->age_dev, 444132904Spjd "PCI VPD capability not found!\n"); 445132904Spjd } 446132904Spjd 447132904Spjd /* 448132904Spjd * It seems that L1 also provides a way to extract ethernet 449132904Spjd * address via SPI flash interface. Because SPI flash memory 450132904Spjd * device of different vendors vary in their instruction 451132904Spjd * codes for read ID instruction, it's very hard to get 452132904Spjd * instructions codes without detailed information for the 453132904Spjd * flash memory device used on ethernet controller. To simplify 454132904Spjd * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 455132904Spjd * address which is supposed to be set by hardware during 456132904Spjd * power on reset. 457132904Spjd */ 458132904Spjd if (vpd_error != 0) { 459132904Spjd /* 460132904Spjd * VPD is mapped to SPI flash memory or BIOS set it. 461132904Spjd */ 462132922Spjd ea[0] = CSR_READ_4(sc, AGE_PAR0); 463132922Spjd ea[1] = CSR_READ_4(sc, AGE_PAR1); 464132922Spjd } 465132922Spjd 466132922Spjd ea[1] &= 0xFFFF; 467132922Spjd if ((ea[0] == 0 && ea[1] == 0) || 468132922Spjd (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 469132922Spjd device_printf(sc->age_dev, 470132922Spjd "generating fake ethernet address.\n"); 471132922Spjd ea[0] = arc4random(); 472132904Spjd /* Set OUI to ASUSTek COMPUTER INC. */ 473132904Spjd sc->age_eaddr[0] = 0x00; 474132904Spjd sc->age_eaddr[1] = 0x1B; 475132904Spjd sc->age_eaddr[2] = 0xFC; 476132904Spjd sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 477132904Spjd sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 478132904Spjd sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 479132904Spjd } else { 480132904Spjd sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 481132904Spjd sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 482132904Spjd sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 483132904Spjd sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 484132904Spjd sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 485132904Spjd sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 486132904Spjd } 487132904Spjd} 488132904Spjd 489132904Spjdstatic void 490132904Spjdage_phy_reset(struct age_softc *sc) 491132904Spjd{ 492132904Spjd 493132938Spjd /* Reset PHY. */ 494132938Spjd CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 495132938Spjd DELAY(1000); 496132938Spjd CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 497132938Spjd DELAY(1000); 498132938Spjd} 499132938Spjd 500132938Spjdstatic int 501132938Spjdage_attach(device_t dev) 502132938Spjd{ 503132938Spjd struct age_softc *sc; 504132938Spjd struct ifnet *ifp; 505132938Spjd uint16_t burst; 506132938Spjd int error, i, msic, msixc, pmc; 507132938Spjd 508132904Spjd error = 0; 509132904Spjd sc = device_get_softc(dev); 510132904Spjd sc->age_dev = dev; 511132904Spjd 512132904Spjd mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 513132904Spjd MTX_DEF); 514132904Spjd callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 515132904Spjd TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 516132904Spjd TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 517132904Spjd 518132904Spjd /* Map the device. */ 519132904Spjd pci_enable_busmaster(dev); 520132904Spjd sc->age_res_spec = age_res_spec_mem; 521132904Spjd sc->age_irq_spec = age_irq_spec_legacy; 522132904Spjd error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 523132904Spjd if (error != 0) { 524132904Spjd device_printf(dev, "cannot allocate memory resources.\n"); 525132904Spjd goto fail; 526132904Spjd } 527132904Spjd 528132904Spjd /* Set PHY address. */ 529132904Spjd sc->age_phyaddr = AGE_PHY_ADDR; 530132904Spjd 531132904Spjd /* Reset PHY. */ 532132904Spjd age_phy_reset(sc); 533132904Spjd 534132904Spjd /* Reset the ethernet controller. */ 535132904Spjd age_reset(sc); 536132904Spjd 537132904Spjd /* Get PCI and chip id/revision. */ 538132904Spjd sc->age_rev = pci_get_revid(dev); 539132904Spjd sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 540132904Spjd MASTER_CHIP_REV_SHIFT; 541132904Spjd if (1 || bootverbose) { 542132904Spjd device_printf(dev, "PCI device revision : 0x%04x\n", sc->age_rev); 543132904Spjd device_printf(dev, "Chip id/revision : 0x%04x\n", 544132904Spjd sc->age_chip_rev); 545132904Spjd } 546132904Spjd 547132904Spjd /* 548132904Spjd * XXX 549132904Spjd * Unintialized hardware returns an invalid chip id/revision 550132904Spjd * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 551132904Spjd * unplugged cable results in putting hardware into automatic 552132904Spjd * power down mode which in turn returns invalld chip revision. 553132904Spjd */ 554132904Spjd if (sc->age_chip_rev == 0xFFFF) { 555132904Spjd device_printf(dev,"invalid chip revision : 0x%04x -- " 556132904Spjd "not initialized?\n", sc->age_chip_rev); 557132904Spjd error = ENXIO; 558132904Spjd goto fail; 559132904Spjd } 560132904Spjd 561132904Spjd device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 562132904Spjd CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 563132904Spjd CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 564132904Spjd 565132904Spjd /* Allocate IRQ resources. */ 566132904Spjd msixc = pci_msix_count(dev); 567132904Spjd msic = pci_msi_count(dev); 568132904Spjd if (1 || bootverbose) { 569132904Spjd device_printf(dev, "MSIX count : %d\n", msixc); 570132904Spjd device_printf(dev, "MSI count : %d\n", msic); 571132904Spjd } 572132904Spjd 573132904Spjd /* Prefer MSIX over MSI. */ 574132904Spjd if (msix_disable == 0 || msi_disable == 0) { 575132904Spjd if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 576132904Spjd pci_alloc_msix(dev, &msixc) == 0) { 577132904Spjd if (msic == AGE_MSIX_MESSAGES) { 578132904Spjd device_printf(dev, "Using %d MSIX messages.\n", 579132904Spjd msixc); 580132904Spjd sc->age_flags |= AGE_FLAG_MSIX; 581132904Spjd sc->age_irq_spec = age_irq_spec_msix; 582132904Spjd } else 583132904Spjd pci_release_msi(dev); 584132904Spjd } 585132904Spjd if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 586132904Spjd msic == AGE_MSI_MESSAGES && 587132904Spjd pci_alloc_msi(dev, &msic) == 0) { 588132904Spjd if (msic == AGE_MSI_MESSAGES) { 589132904Spjd device_printf(dev, "Using %d MSI messages.\n", 590132904Spjd msic); 591132904Spjd sc->age_flags |= AGE_FLAG_MSI; 592132904Spjd sc->age_irq_spec = age_irq_spec_msi; 593132904Spjd } else 594132904Spjd pci_release_msi(dev); 595132904Spjd } 596132904Spjd } 597132904Spjd 598132904Spjd error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 599132904Spjd if (error != 0) { 600132904Spjd device_printf(dev, "cannot allocate IRQ resources.\n"); 601132904Spjd goto fail; 602132904Spjd } 603132904Spjd 604132904Spjd 605132904Spjd /* Get DMA parameters from PCIe device control register. */ 606132904Spjd if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 607132904Spjd sc->age_flags |= AGE_FLAG_PCIE; 608132904Spjd burst = pci_read_config(dev, i + 0x08, 2); 609132904Spjd /* Max read request size. */ 610132904Spjd sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 611132904Spjd DMA_CFG_RD_BURST_SHIFT; 612132904Spjd /* Max payload size. */ 613132904Spjd sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 614132904Spjd DMA_CFG_WR_BURST_SHIFT; 615132904Spjd if (1 || bootverbose) { 616132904Spjd device_printf(dev, "Read request size : %d bytes.\n", 617132904Spjd 128 << ((burst >> 12) & 0x07)); 618132904Spjd device_printf(dev, "TLP payload size : %d bytes.\n", 619132904Spjd 128 << ((burst >> 5) & 0x07)); 620132904Spjd } 621132904Spjd } else { 622132904Spjd sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 623132904Spjd sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 624132904Spjd } 625132904Spjd 626132904Spjd /* Create device sysctl node. */ 627132904Spjd age_sysctl_node(sc); 628132904Spjd 629132904Spjd if ((error = age_dma_alloc(sc) != 0)) 630132904Spjd goto fail; 631132904Spjd 632132904Spjd /* Load station address. */ 633132904Spjd age_get_macaddr(sc); 634132904Spjd 635132904Spjd ifp = sc->age_ifp = if_alloc(IFT_ETHER); 636132904Spjd if (ifp == NULL) { 637132904Spjd device_printf(dev, "cannot allocate ifnet structure.\n"); 638132904Spjd error = ENXIO; 639132904Spjd goto fail; 640132904Spjd } 641132904Spjd 642132904Spjd ifp->if_softc = sc; 643132904Spjd if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 644132904Spjd ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 645132904Spjd ifp->if_ioctl = age_ioctl; 646132904Spjd ifp->if_start = age_start; 647132904Spjd ifp->if_init = age_init; 648132904Spjd ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1; 649132904Spjd IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 650132904Spjd IFQ_SET_READY(&ifp->if_snd); 651132904Spjd ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 652132904Spjd ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; 653132904Spjd if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 654132904Spjd sc->age_flags |= AGE_FLAG_PMCAP; 655132904Spjd ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 656132904Spjd } 657132904Spjd ifp->if_capenable = ifp->if_capabilities; 658132904Spjd 659132904Spjd /* Set up MII bus. */ 660132904Spjd if ((error = mii_phy_probe(dev, &sc->age_miibus, age_mediachange, 661132904Spjd age_mediastatus)) != 0) { 662132904Spjd device_printf(dev, "no PHY found!\n"); 663132904Spjd goto fail; 664132904Spjd } 665132904Spjd 666132904Spjd ether_ifattach(ifp, sc->age_eaddr); 667132904Spjd 668132904Spjd /* VLAN capability setup. */ 669132904Spjd ifp->if_capabilities |= IFCAP_VLAN_MTU; 670132904Spjd ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 671132904Spjd ifp->if_capenable = ifp->if_capabilities; 672132904Spjd 673132904Spjd /* Tell the upper layer(s) we support long frames. */ 674132904Spjd ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 675132904Spjd 676132904Spjd /* Create local taskq. */ 677132904Spjd TASK_INIT(&sc->age_tx_task, 1, age_tx_task, ifp); 678132904Spjd sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 679132904Spjd taskqueue_thread_enqueue, &sc->age_tq); 680132904Spjd if (sc->age_tq == NULL) { 681132904Spjd device_printf(dev, "could not create taskqueue.\n"); 682132904Spjd ether_ifdetach(ifp); 683132904Spjd error = ENXIO; 684132904Spjd goto fail; 685132904Spjd } 686132904Spjd taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 687132904Spjd device_get_nameunit(sc->age_dev)); 688132904Spjd 689132904Spjd if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 690132904Spjd msic = AGE_MSIX_MESSAGES; 691132904Spjd else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 692132904Spjd msic = AGE_MSI_MESSAGES; 693132904Spjd else 694132904Spjd msic = 1; 695132904Spjd for (i = 0; i < msic; i++) { 696132904Spjd error = bus_setup_intr(dev, sc->age_irq[i], 697132904Spjd INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 698132904Spjd &sc->age_intrhand[i]); 699132904Spjd if (error != 0) 700132904Spjd break; 701132904Spjd } 702132904Spjd if (error != 0) { 703132904Spjd device_printf(dev, "could not set up interrupt handler.\n"); 704132904Spjd taskqueue_free(sc->age_tq); 705132904Spjd sc->age_tq = NULL; 706132904Spjd ether_ifdetach(ifp); 707132904Spjd goto fail; 708132904Spjd } 709132904Spjd 710132904Spjdfail: 711132904Spjd if (error != 0) 712132904Spjd age_detach(dev); 713132954Spjd 714132954Spjd return (error); 715132904Spjd} 716132904Spjd 717132904Spjdstatic int 718132904Spjdage_detach(device_t dev) 719132904Spjd{ 720132904Spjd struct age_softc *sc; 721132904Spjd struct ifnet *ifp; 722132904Spjd int i, msic; 723132904Spjd 724132904Spjd sc = device_get_softc(dev); 725132904Spjd 726132904Spjd ifp = sc->age_ifp; 727132904Spjd if (device_is_attached(dev)) { 728132904Spjd AGE_LOCK(sc); 729132904Spjd sc->age_flags |= AGE_FLAG_DETACH; 730132904Spjd age_stop(sc); 731132904Spjd AGE_UNLOCK(sc); 732132904Spjd callout_drain(&sc->age_tick_ch); 733132904Spjd taskqueue_drain(sc->age_tq, &sc->age_int_task); 734132904Spjd taskqueue_drain(sc->age_tq, &sc->age_tx_task); 735132904Spjd taskqueue_drain(taskqueue_swi, &sc->age_link_task); 736132904Spjd ether_ifdetach(ifp); 737132904Spjd } 738132904Spjd 739132904Spjd if (sc->age_tq != NULL) { 740132904Spjd taskqueue_drain(sc->age_tq, &sc->age_int_task); 741132904Spjd taskqueue_free(sc->age_tq); 742132904Spjd sc->age_tq = NULL; 743132904Spjd } 744132904Spjd 745132904Spjd if (sc->age_miibus != NULL) { 746132904Spjd device_delete_child(dev, sc->age_miibus); 747132904Spjd sc->age_miibus = NULL; 748132904Spjd } 749132904Spjd bus_generic_detach(dev); 750132904Spjd age_dma_free(sc); 751132904Spjd 752132904Spjd if (ifp != NULL) { 753132904Spjd if_free(ifp); 754132904Spjd sc->age_ifp = NULL; 755132904Spjd } 756132904Spjd 757132904Spjd if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 758132904Spjd msic = AGE_MSIX_MESSAGES; 759132904Spjd else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 760132904Spjd msic = AGE_MSI_MESSAGES; 761132904Spjd else 762132904Spjd msic = 1; 763132904Spjd for (i = 0; i < msic; i++) { 764132904Spjd if (sc->age_intrhand[i] != NULL) { 765132904Spjd bus_teardown_intr(dev, sc->age_irq[i], 766132904Spjd sc->age_intrhand[i]); 767132904Spjd sc->age_intrhand[i] = NULL; 768132904Spjd } 769132904Spjd } 770132904Spjd 771132904Spjd bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 772132904Spjd if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 773132904Spjd pci_release_msi(dev); 774132904Spjd bus_release_resources(dev, sc->age_res_spec, sc->age_res); 775132904Spjd mtx_destroy(&sc->age_mtx); 776132904Spjd 777132904Spjd return (0); 778132904Spjd} 779132904Spjd 780132904Spjdstatic void 781132904Spjdage_sysctl_node(struct age_softc *sc) 782132904Spjd{ 783132904Spjd int error; 784132904Spjd 785132904Spjd SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 786132904Spjd SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 787132904Spjd "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats, 788132904Spjd "I", "Statistics"); 789132904Spjd 790132904Spjd SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 791132904Spjd SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 792132904Spjd "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0, 793132904Spjd sysctl_hw_age_int_mod, "I", "age interrupt moderation"); 794132904Spjd 795132904Spjd /* Pull in device tunables. */ 796132904Spjd sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 797132904Spjd error = resource_int_value(device_get_name(sc->age_dev), 798132904Spjd device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 799132904Spjd if (error == 0) { 800132904Spjd if (sc->age_int_mod < AGE_IM_TIMER_MIN || 801132904Spjd sc->age_int_mod > AGE_IM_TIMER_MAX) { 802132904Spjd device_printf(sc->age_dev, 803132904Spjd "int_mod value out of range; using default: %d\n", 804132904Spjd AGE_IM_TIMER_DEFAULT); 805132904Spjd sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 806132904Spjd } 807132904Spjd } 808132904Spjd 809132904Spjd SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 810132904Spjd SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 811132904Spjd "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit, 812132904Spjd 0, sysctl_hw_age_proc_limit, "I", 813132904Spjd "max number of Rx events to process"); 814132904Spjd 815132904Spjd /* Pull in device tunables. */ 816132904Spjd sc->age_process_limit = AGE_PROC_DEFAULT; 817132904Spjd error = resource_int_value(device_get_name(sc->age_dev), 818132904Spjd device_get_unit(sc->age_dev), "process_limit", 819132904Spjd &sc->age_process_limit); 820132904Spjd if (error == 0) { 821132904Spjd if (sc->age_process_limit < AGE_PROC_MIN || 822132904Spjd sc->age_process_limit > AGE_PROC_MAX) { 823132904Spjd device_printf(sc->age_dev, 824132904Spjd "process_limit value out of range; " 825132904Spjd "using default: %d\n", AGE_PROC_DEFAULT); 826132904Spjd sc->age_process_limit = AGE_PROC_DEFAULT; 827132904Spjd } 828132904Spjd } 829132904Spjd} 830132904Spjd 831132904Spjdstruct age_dmamap_arg { 832132904Spjd bus_addr_t age_busaddr; 833132904Spjd}; 834132904Spjd 835132904Spjdstatic void 836132904Spjdage_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 837132904Spjd{ 838132904Spjd struct age_dmamap_arg *ctx; 839132904Spjd 840132904Spjd if (error != 0) 841132904Spjd return; 842132904Spjd 843132904Spjd KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 844132904Spjd 845132904Spjd ctx = (struct age_dmamap_arg *)arg; 846132904Spjd ctx->age_busaddr = segs[0].ds_addr; 847132904Spjd} 848132904Spjd 849132904Spjd/* 850132904Spjd * Attansic L1 controller have single register to specify high 851132904Spjd * address part of DMA blocks. So all descriptor structures and 852132904Spjd * DMA memory blocks should have the same high address of given 853132904Spjd * 4GB address space(i.e. crossing 4GB boundary is not allowed). 854132904Spjd */ 855132904Spjdstatic int 856132904Spjdage_check_boundary(struct age_softc *sc) 857132904Spjd{ 858132904Spjd bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 859132904Spjd bus_addr_t cmb_block_end, smb_block_end; 860132904Spjd 861132904Spjd /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 862132904Spjd tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 863132904Spjd rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 864132904Spjd rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 865132904Spjd cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 866132904Spjd smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 867132904Spjd 868132904Spjd if ((AGE_ADDR_HI(tx_ring_end) != 869132904Spjd AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 870132904Spjd (AGE_ADDR_HI(rx_ring_end) != 871132904Spjd AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 872132904Spjd (AGE_ADDR_HI(rr_ring_end) != 873132904Spjd AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 874132904Spjd (AGE_ADDR_HI(cmb_block_end) != 875132904Spjd AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 876132904Spjd (AGE_ADDR_HI(smb_block_end) != 877132904Spjd AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 878132904Spjd return (EFBIG); 879132904Spjd 880132904Spjd if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 881132904Spjd (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 882132904Spjd (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 883132904Spjd (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 884132904Spjd return (EFBIG); 885132904Spjd 886132904Spjd return (0); 887132904Spjd} 888132904Spjd 889132904Spjdstatic int 890132904Spjdage_dma_alloc(struct age_softc *sc) 891132904Spjd{ 892132904Spjd struct age_txdesc *txd; 893132904Spjd struct age_rxdesc *rxd; 894132904Spjd bus_addr_t lowaddr; 895132904Spjd struct age_dmamap_arg ctx; 896132904Spjd int error, i; 897132904Spjd 898132904Spjd lowaddr = BUS_SPACE_MAXADDR; 899132904Spjd 900132904Spjdagain: 901132904Spjd /* Create parent ring/DMA block tag. */ 902132904Spjd error = bus_dma_tag_create( 903132904Spjd bus_get_dma_tag(sc->age_dev), /* parent */ 904132904Spjd 1, 0, /* alignment, boundary */ 905132904Spjd lowaddr, /* lowaddr */ 906132904Spjd BUS_SPACE_MAXADDR, /* highaddr */ 907132904Spjd NULL, NULL, /* filter, filterarg */ 908132904Spjd BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 909132904Spjd 0, /* nsegments */ 910132904Spjd BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 911132904Spjd 0, /* flags */ 912132904Spjd NULL, NULL, /* lockfunc, lockarg */ 913132904Spjd &sc->age_cdata.age_parent_tag); 914132904Spjd if (error != 0) { 915132904Spjd device_printf(sc->age_dev, 916132904Spjd "could not create parent DMA tag.\n"); 917132904Spjd goto fail; 918132904Spjd } 919132904Spjd 920132904Spjd /* Create tag for Tx ring. */ 921132904Spjd error = bus_dma_tag_create( 922132904Spjd sc->age_cdata.age_parent_tag, /* parent */ 923132904Spjd AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 924132904Spjd BUS_SPACE_MAXADDR, /* lowaddr */ 925132904Spjd BUS_SPACE_MAXADDR, /* highaddr */ 926132904Spjd NULL, NULL, /* filter, filterarg */ 927132904Spjd AGE_TX_RING_SZ, /* maxsize */ 928132904Spjd 1, /* nsegments */ 929132904Spjd AGE_TX_RING_SZ, /* maxsegsize */ 930132904Spjd 0, /* flags */ 931132904Spjd NULL, NULL, /* lockfunc, lockarg */ 932132904Spjd &sc->age_cdata.age_tx_ring_tag); 933132904Spjd if (error != 0) { 934132904Spjd device_printf(sc->age_dev, 935132904Spjd "could not create Tx ring DMA tag.\n"); 936132904Spjd goto fail; 937132904Spjd } 938132904Spjd 939132904Spjd /* Create tag for Rx ring. */ 940132904Spjd error = bus_dma_tag_create( 941132904Spjd sc->age_cdata.age_parent_tag, /* parent */ 942132904Spjd AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 943132904Spjd BUS_SPACE_MAXADDR, /* lowaddr */ 944132904Spjd BUS_SPACE_MAXADDR, /* highaddr */ 945132904Spjd NULL, NULL, /* filter, filterarg */ 946132904Spjd AGE_RX_RING_SZ, /* maxsize */ 947132904Spjd 1, /* nsegments */ 948132904Spjd AGE_RX_RING_SZ, /* maxsegsize */ 949132904Spjd 0, /* flags */ 950132904Spjd NULL, NULL, /* lockfunc, lockarg */ 951132904Spjd &sc->age_cdata.age_rx_ring_tag); 952132904Spjd if (error != 0) { 953132904Spjd device_printf(sc->age_dev, 954132904Spjd "could not create Rx ring DMA tag.\n"); 955132904Spjd goto fail; 956132904Spjd } 957132904Spjd 958132904Spjd /* Create tag for Rx return ring. */ 959132904Spjd error = bus_dma_tag_create( 960132904Spjd sc->age_cdata.age_parent_tag, /* parent */ 961132904Spjd AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 962132904Spjd BUS_SPACE_MAXADDR, /* lowaddr */ 963132904Spjd BUS_SPACE_MAXADDR, /* highaddr */ 964132904Spjd NULL, NULL, /* filter, filterarg */ 965132904Spjd AGE_RR_RING_SZ, /* maxsize */ 966132904Spjd 1, /* nsegments */ 967132904Spjd AGE_RR_RING_SZ, /* maxsegsize */ 968132904Spjd 0, /* flags */ 969132904Spjd NULL, NULL, /* lockfunc, lockarg */ 970132904Spjd &sc->age_cdata.age_rr_ring_tag); 971132904Spjd if (error != 0) { 972132904Spjd device_printf(sc->age_dev, 973132904Spjd "could not create Rx return ring DMA tag.\n"); 974132904Spjd goto fail; 975132904Spjd } 976132904Spjd 977132904Spjd /* Create tag for coalesing message block. */ 978132904Spjd error = bus_dma_tag_create( 979132904Spjd sc->age_cdata.age_parent_tag, /* parent */ 980132904Spjd AGE_CMB_ALIGN, 0, /* alignment, boundary */ 981132904Spjd BUS_SPACE_MAXADDR, /* lowaddr */ 982132904Spjd BUS_SPACE_MAXADDR, /* highaddr */ 983132904Spjd NULL, NULL, /* filter, filterarg */ 984132904Spjd AGE_CMB_BLOCK_SZ, /* maxsize */ 985132904Spjd 1, /* nsegments */ 986132904Spjd AGE_CMB_BLOCK_SZ, /* maxsegsize */ 987132904Spjd 0, /* flags */ 988132904Spjd NULL, NULL, /* lockfunc, lockarg */ 989132904Spjd &sc->age_cdata.age_cmb_block_tag); 990132904Spjd if (error != 0) { 991132904Spjd device_printf(sc->age_dev, 992132904Spjd "could not create CMB DMA tag.\n"); 993132904Spjd goto fail; 994132904Spjd } 995132904Spjd 996132904Spjd /* Create tag for statistics message block. */ 997132904Spjd error = bus_dma_tag_create( 998132904Spjd sc->age_cdata.age_parent_tag, /* parent */ 999132904Spjd AGE_SMB_ALIGN, 0, /* alignment, boundary */ 1000132904Spjd BUS_SPACE_MAXADDR, /* lowaddr */ 1001132904Spjd BUS_SPACE_MAXADDR, /* highaddr */ 1002132904Spjd NULL, NULL, /* filter, filterarg */ 1003132904Spjd AGE_SMB_BLOCK_SZ, /* maxsize */ 1004132904Spjd 1, /* nsegments */ 1005132904Spjd AGE_SMB_BLOCK_SZ, /* maxsegsize */ 1006132904Spjd 0, /* flags */ 1007132904Spjd NULL, NULL, /* lockfunc, lockarg */ 1008132904Spjd &sc->age_cdata.age_smb_block_tag); 1009132904Spjd if (error != 0) { 1010132904Spjd device_printf(sc->age_dev, 1011132904Spjd "could not create SMB DMA tag.\n"); 1012132904Spjd goto fail; 1013132904Spjd } 1014132904Spjd 1015132904Spjd /* Allocate DMA'able memory and load the DMA map. */ 1016133115Spjd error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 1017133115Spjd (void **)&sc->age_rdata.age_tx_ring, 1018133115Spjd BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1019133115Spjd &sc->age_cdata.age_tx_ring_map); 1020133115Spjd if (error != 0) { 1021133115Spjd device_printf(sc->age_dev, 1022133115Spjd "could not allocate DMA'able memory for Tx ring.\n"); 1023133115Spjd goto fail; 1024133115Spjd } 1025133115Spjd ctx.age_busaddr = 0; 1026133115Spjd error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 1027133115Spjd sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 1028133115Spjd AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 1029133115Spjd if (error != 0 || ctx.age_busaddr == 0) { 1030133115Spjd device_printf(sc->age_dev, 1031133115Spjd "could not load DMA'able memory for Tx ring.\n"); 1032133115Spjd goto fail; 1033133115Spjd } 1034133115Spjd sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 1035133115Spjd /* Rx ring */ 1036133115Spjd error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 1037133115Spjd (void **)&sc->age_rdata.age_rx_ring, 1038133115Spjd BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1039133115Spjd &sc->age_cdata.age_rx_ring_map); 1040133115Spjd if (error != 0) { 1041133115Spjd device_printf(sc->age_dev, 1042133115Spjd "could not allocate DMA'able memory for Rx ring.\n"); 1043133115Spjd goto fail; 1044133115Spjd } 1045133115Spjd ctx.age_busaddr = 0; 1046133115Spjd error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1047133115Spjd sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1048133115Spjd AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1049133115Spjd if (error != 0 || ctx.age_busaddr == 0) { 1050133115Spjd device_printf(sc->age_dev, 1051133115Spjd "could not load DMA'able memory for Rx ring.\n"); 1052133115Spjd goto fail; 1053132904Spjd } 1054132904Spjd sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1055132904Spjd /* Rx return ring */ 1056132904Spjd error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1057132904Spjd (void **)&sc->age_rdata.age_rr_ring, 1058132904Spjd BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1059132904Spjd &sc->age_cdata.age_rr_ring_map); 1060132904Spjd if (error != 0) { 1061132904Spjd device_printf(sc->age_dev, 1062132904Spjd "could not allocate DMA'able memory for Rx return ring.\n"); 1063132904Spjd goto fail; 1064132904Spjd } 1065132904Spjd ctx.age_busaddr = 0; 1066132904Spjd error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1067132904Spjd sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1068132904Spjd AGE_RR_RING_SZ, age_dmamap_cb, 1069132904Spjd &ctx, 0); 1070132904Spjd if (error != 0 || ctx.age_busaddr == 0) { 1071132904Spjd device_printf(sc->age_dev, 1072132904Spjd "could not load DMA'able memory for Rx return ring.\n"); 1073132904Spjd goto fail; 1074132904Spjd } 1075132904Spjd sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1076132904Spjd /* CMB block */ 1077132904Spjd error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1078132904Spjd (void **)&sc->age_rdata.age_cmb_block, 1079132904Spjd BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1080132904Spjd &sc->age_cdata.age_cmb_block_map); 1081132904Spjd if (error != 0) { 1082132904Spjd device_printf(sc->age_dev, 1083132904Spjd "could not allocate DMA'able memory for CMB block.\n"); 1084132904Spjd goto fail; 1085132904Spjd } 1086132904Spjd ctx.age_busaddr = 0; 1087132904Spjd error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1088132904Spjd sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1089132904Spjd AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1090132904Spjd if (error != 0 || ctx.age_busaddr == 0) { 1091132904Spjd device_printf(sc->age_dev, 1092132904Spjd "could not load DMA'able memory for CMB block.\n"); 1093132904Spjd goto fail; 1094132904Spjd } 1095132904Spjd sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1096132904Spjd /* SMB block */ 1097132904Spjd error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1098132904Spjd (void **)&sc->age_rdata.age_smb_block, 1099132904Spjd BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1100132904Spjd &sc->age_cdata.age_smb_block_map); 1101132904Spjd if (error != 0) { 1102132904Spjd device_printf(sc->age_dev, 1103132904Spjd "could not allocate DMA'able memory for SMB block.\n"); 1104132904Spjd goto fail; 1105132904Spjd } 1106132904Spjd ctx.age_busaddr = 0; 1107132904Spjd error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1108132904Spjd sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1109132904Spjd AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1110132904Spjd if (error != 0 || ctx.age_busaddr == 0) { 1111132904Spjd device_printf(sc->age_dev, 1112132904Spjd "could not load DMA'able memory for SMB block.\n"); 1113132904Spjd goto fail; 1114132904Spjd } 1115132904Spjd sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1116132904Spjd 1117132904Spjd /* 1118132904Spjd * All ring buffer and DMA blocks should have the same 1119132904Spjd * high address part of 64bit DMA address space. 1120132904Spjd */ 1121132904Spjd if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1122132904Spjd (error = age_check_boundary(sc)) != 0) { 1123132904Spjd device_printf(sc->age_dev, "4GB boundary crossed, " 1124132904Spjd "switching to 32bit DMA addressing mode.\n"); 1125132904Spjd age_dma_free(sc); 1126132904Spjd /* Limit DMA address space to 32bit and try again. */ 1127132904Spjd lowaddr = BUS_SPACE_MAXADDR_32BIT; 1128132904Spjd goto again; 1129132904Spjd } 1130132904Spjd 1131132904Spjd /* 1132132904Spjd * Create Tx/Rx buffer parent tag. 1133132904Spjd * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1134132904Spjd * so it needs separate parent DMA tag. 1135132904Spjd */ 1136132904Spjd error = bus_dma_tag_create( 1137132904Spjd bus_get_dma_tag(sc->age_dev), /* parent */ 1138132904Spjd 1, 0, /* alignment, boundary */ 1139132904Spjd BUS_SPACE_MAXADDR, /* lowaddr */ 1140132904Spjd BUS_SPACE_MAXADDR, /* highaddr */ 1141132904Spjd NULL, NULL, /* filter, filterarg */ 1142132904Spjd BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1143132904Spjd 0, /* nsegments */ 1144132904Spjd BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1145132904Spjd 0, /* flags */ 1146132904Spjd NULL, NULL, /* lockfunc, lockarg */ 1147132904Spjd &sc->age_cdata.age_buffer_tag); 1148132904Spjd if (error != 0) { 1149132904Spjd device_printf(sc->age_dev, 1150132904Spjd "could not create parent buffer DMA tag.\n"); 1151132904Spjd goto fail; 1152132904Spjd } 1153132904Spjd 1154132904Spjd /* Create tag for Tx buffers. */ 1155132904Spjd error = bus_dma_tag_create( 1156132904Spjd sc->age_cdata.age_buffer_tag, /* parent */ 1157132904Spjd 1, 0, /* alignment, boundary */ 1158132904Spjd BUS_SPACE_MAXADDR, /* lowaddr */ 1159132904Spjd BUS_SPACE_MAXADDR, /* highaddr */ 1160132904Spjd NULL, NULL, /* filter, filterarg */ 1161132904Spjd AGE_TSO_MAXSIZE, /* maxsize */ 1162132904Spjd AGE_MAXTXSEGS, /* nsegments */ 1163132904Spjd AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1164132904Spjd 0, /* flags */ 1165132904Spjd NULL, NULL, /* lockfunc, lockarg */ 1166132904Spjd &sc->age_cdata.age_tx_tag); 1167132904Spjd if (error != 0) { 1168132904Spjd device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1169132904Spjd goto fail; 1170132904Spjd } 1171132904Spjd 1172132904Spjd /* Create tag for Rx buffers. */ 1173132904Spjd error = bus_dma_tag_create( 1174132904Spjd sc->age_cdata.age_buffer_tag, /* parent */ 1175132904Spjd 1, 0, /* alignment, boundary */ 1176132904Spjd BUS_SPACE_MAXADDR, /* lowaddr */ 1177132904Spjd BUS_SPACE_MAXADDR, /* highaddr */ 1178132904Spjd NULL, NULL, /* filter, filterarg */ 1179132904Spjd MCLBYTES, /* maxsize */ 1180132904Spjd 1, /* nsegments */ 1181132904Spjd MCLBYTES, /* maxsegsize */ 1182132904Spjd 0, /* flags */ 1183132904Spjd NULL, NULL, /* lockfunc, lockarg */ 1184132904Spjd &sc->age_cdata.age_rx_tag); 1185132904Spjd if (error != 0) { 1186132904Spjd device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1187132904Spjd goto fail; 1188132904Spjd } 1189132904Spjd 1190132904Spjd /* Create DMA maps for Tx buffers. */ 1191132904Spjd for (i = 0; i < AGE_TX_RING_CNT; i++) { 1192132904Spjd txd = &sc->age_cdata.age_txdesc[i]; 1193132904Spjd txd->tx_m = NULL; 1194132904Spjd txd->tx_dmamap = NULL; 1195132904Spjd error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1196132904Spjd &txd->tx_dmamap); 1197132904Spjd if (error != 0) { 1198132904Spjd device_printf(sc->age_dev, 1199132904Spjd "could not create Tx dmamap.\n"); 1200132904Spjd goto fail; 1201132904Spjd } 1202132904Spjd } 1203132904Spjd /* Create DMA maps for Rx buffers. */ 1204132904Spjd if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1205132904Spjd &sc->age_cdata.age_rx_sparemap)) != 0) { 1206132904Spjd device_printf(sc->age_dev, 1207132904Spjd "could not create spare Rx dmamap.\n"); 1208132904Spjd goto fail; 1209132904Spjd } 1210132904Spjd for (i = 0; i < AGE_RX_RING_CNT; i++) { 1211133115Spjd rxd = &sc->age_cdata.age_rxdesc[i]; 1212133115Spjd rxd->rx_m = NULL; 1213133115Spjd rxd->rx_dmamap = NULL; 1214133115Spjd error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1215133115Spjd &rxd->rx_dmamap); 1216133115Spjd if (error != 0) { 1217132904Spjd device_printf(sc->age_dev, 1218132904Spjd "could not create Rx dmamap.\n"); 1219132904Spjd goto fail; 1220132904Spjd } 1221132904Spjd } 1222132904Spjd 1223132904Spjdfail: 1224132904Spjd return (error); 1225132904Spjd} 1226132904Spjd 1227132904Spjdstatic void 1228132904Spjdage_dma_free(struct age_softc *sc) 1229132904Spjd{ 1230132904Spjd struct age_txdesc *txd; 1231132904Spjd struct age_rxdesc *rxd; 1232132904Spjd int i; 1233132904Spjd 1234132904Spjd /* Tx buffers */ 1235132904Spjd if (sc->age_cdata.age_tx_tag != NULL) { 1236132904Spjd for (i = 0; i < AGE_TX_RING_CNT; i++) { 1237132904Spjd txd = &sc->age_cdata.age_txdesc[i]; 1238132904Spjd if (txd->tx_dmamap != NULL) { 1239132904Spjd bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1240132904Spjd txd->tx_dmamap); 1241132904Spjd txd->tx_dmamap = NULL; 1242132904Spjd } 1243132904Spjd } 1244132904Spjd bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1245132904Spjd sc->age_cdata.age_tx_tag = NULL; 1246132904Spjd } 1247132904Spjd /* Rx buffers */ 1248132904Spjd if (sc->age_cdata.age_rx_tag != NULL) { 1249132904Spjd for (i = 0; i < AGE_RX_RING_CNT; i++) { 1250132904Spjd rxd = &sc->age_cdata.age_rxdesc[i]; 1251132904Spjd if (rxd->rx_dmamap != NULL) { 1252132904Spjd bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1253132904Spjd rxd->rx_dmamap); 1254132904Spjd rxd->rx_dmamap = NULL; 1255132904Spjd } 1256132904Spjd } 1257132904Spjd if (sc->age_cdata.age_rx_sparemap != NULL) { 1258132904Spjd bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1259132904Spjd sc->age_cdata.age_rx_sparemap); 1260132904Spjd sc->age_cdata.age_rx_sparemap = NULL; 1261132904Spjd } 1262132904Spjd bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1263132904Spjd sc->age_cdata.age_rx_tag = NULL; 1264132904Spjd } 1265132904Spjd /* Tx ring. */ 1266132904Spjd if (sc->age_cdata.age_tx_ring_tag != NULL) { 1267132904Spjd if (sc->age_cdata.age_tx_ring_map != NULL) 1268132904Spjd bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1269132904Spjd sc->age_cdata.age_tx_ring_map); 1270132904Spjd if (sc->age_cdata.age_tx_ring_map != NULL && 1271132904Spjd sc->age_rdata.age_tx_ring != NULL) 1272132904Spjd bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1273132904Spjd sc->age_rdata.age_tx_ring, 1274132904Spjd sc->age_cdata.age_tx_ring_map); 1275132904Spjd sc->age_rdata.age_tx_ring = NULL; 1276132904Spjd sc->age_cdata.age_tx_ring_map = NULL; 1277132904Spjd bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1278132904Spjd sc->age_cdata.age_tx_ring_tag = NULL; 1279132904Spjd } 1280132904Spjd /* Rx ring. */ 1281132904Spjd if (sc->age_cdata.age_rx_ring_tag != NULL) { 1282132904Spjd if (sc->age_cdata.age_rx_ring_map != NULL) 1283132904Spjd bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1284132904Spjd sc->age_cdata.age_rx_ring_map); 1285132904Spjd if (sc->age_cdata.age_rx_ring_map != NULL && 1286132904Spjd sc->age_rdata.age_rx_ring != NULL) 1287132904Spjd bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1288132904Spjd sc->age_rdata.age_rx_ring, 1289132904Spjd sc->age_cdata.age_rx_ring_map); 1290132904Spjd sc->age_rdata.age_rx_ring = NULL; 1291132904Spjd sc->age_cdata.age_rx_ring_map = NULL; 1292132904Spjd bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1293132904Spjd sc->age_cdata.age_rx_ring_tag = NULL; 1294132904Spjd } 1295132904Spjd /* Rx return ring. */ 1296132904Spjd if (sc->age_cdata.age_rr_ring_tag != NULL) { 1297132904Spjd if (sc->age_cdata.age_rr_ring_map != NULL) 1298132904Spjd bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1299132904Spjd sc->age_cdata.age_rr_ring_map); 1300132904Spjd if (sc->age_cdata.age_rr_ring_map != NULL && 1301132904Spjd sc->age_rdata.age_rr_ring != NULL) 1302132904Spjd bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1303132904Spjd sc->age_rdata.age_rr_ring, 1304132904Spjd sc->age_cdata.age_rr_ring_map); 1305132904Spjd sc->age_rdata.age_rr_ring = NULL; 1306132904Spjd sc->age_cdata.age_rr_ring_map = NULL; 1307132904Spjd bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1308132904Spjd sc->age_cdata.age_rr_ring_tag = NULL; 1309132904Spjd } 1310132904Spjd /* CMB block */ 1311132904Spjd if (sc->age_cdata.age_cmb_block_tag != NULL) { 1312132904Spjd if (sc->age_cdata.age_cmb_block_map != NULL) 1313132904Spjd bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1314132904Spjd sc->age_cdata.age_cmb_block_map); 1315132904Spjd if (sc->age_cdata.age_cmb_block_map != NULL && 1316132904Spjd sc->age_rdata.age_cmb_block != NULL) 1317132904Spjd bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1318132904Spjd sc->age_rdata.age_cmb_block, 1319132904Spjd sc->age_cdata.age_cmb_block_map); 1320132904Spjd sc->age_rdata.age_cmb_block = NULL; 1321132904Spjd sc->age_cdata.age_cmb_block_map = NULL; 1322132904Spjd bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1323132904Spjd sc->age_cdata.age_cmb_block_tag = NULL; 1324132904Spjd } 1325132904Spjd /* SMB block */ 1326132904Spjd if (sc->age_cdata.age_smb_block_tag != NULL) { 1327132904Spjd if (sc->age_cdata.age_smb_block_map != NULL) 1328132904Spjd bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1329132904Spjd sc->age_cdata.age_smb_block_map); 1330132904Spjd if (sc->age_cdata.age_smb_block_map != NULL && 1331132904Spjd sc->age_rdata.age_smb_block != NULL) 1332132904Spjd bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1333132904Spjd sc->age_rdata.age_smb_block, 1334132904Spjd sc->age_cdata.age_smb_block_map); 1335132904Spjd sc->age_rdata.age_smb_block = NULL; 1336132904Spjd sc->age_cdata.age_smb_block_map = NULL; 1337132904Spjd bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1338132904Spjd sc->age_cdata.age_smb_block_tag = NULL; 1339132904Spjd } 1340132904Spjd 1341132904Spjd if (sc->age_cdata.age_buffer_tag != NULL) { 1342132904Spjd bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1343132904Spjd sc->age_cdata.age_buffer_tag = NULL; 1344132904Spjd } 1345132904Spjd if (sc->age_cdata.age_parent_tag != NULL) { 1346132904Spjd bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1347132904Spjd sc->age_cdata.age_parent_tag = NULL; 1348132904Spjd } 1349132904Spjd} 1350132904Spjd 1351132904Spjd/* 1352132904Spjd * Make sure the interface is stopped at reboot time. 1353132904Spjd */ 1354132904Spjdstatic int 1355132904Spjdage_shutdown(device_t dev) 1356132904Spjd{ 1357132904Spjd 1358132904Spjd return (age_suspend(dev)); 1359132904Spjd} 1360132904Spjd 1361132904Spjdstatic void 1362132904Spjdage_setwol(struct age_softc *sc) 1363132904Spjd{ 1364132904Spjd struct ifnet *ifp; 1365132904Spjd struct mii_data *mii; 1366132904Spjd uint32_t reg, pmcs; 1367132904Spjd uint16_t pmstat; 1368132904Spjd int aneg, i, pmc; 1369132904Spjd 1370132904Spjd AGE_LOCK_ASSERT(sc); 1371132904Spjd 1372132904Spjd if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) == 0) { 1373132904Spjd CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1374132904Spjd /* 1375132904Spjd * No PME capability, PHY power down. 1376132904Spjd * XXX 1377132904Spjd * Due to an unknown reason powering down PHY resulted 1378132904Spjd * in unexpected results such as inaccessbility of 1379132904Spjd * hardware of freshly rebooted system. Disable 1380132904Spjd * powering down PHY until I got more information for 1381132904Spjd * Attansic/Atheros PHY hardwares. 1382132904Spjd */ 1383132904Spjd#ifdef notyet 1384132904Spjd age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1385132904Spjd MII_BMCR, BMCR_PDOWN); 1386132904Spjd#endif 1387132904Spjd return; 1388132904Spjd } 1389132904Spjd 1390132904Spjd ifp = sc->age_ifp; 1391132904Spjd if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1392132904Spjd /* 1393132904Spjd * Note, this driver resets the link speed to 10/100Mbps with 1394132904Spjd * auto-negotiation but we don't know whether that operation 1395132904Spjd * would succeed or not as it have no control after powering 1396132904Spjd * off. If the renegotiation fail WOL may not work. Running 1397132904Spjd * at 1Gbps will draw more power than 375mA at 3.3V which is 1398132904Spjd * specified in PCI specification and that would result in 1399132904Spjd * complete shutdowning power to ethernet controller. 1400132904Spjd * 1401132904Spjd * TODO 1402132904Spjd * Save current negotiated media speed/duplex/flow-control 1403132904Spjd * to softc and restore the same link again after resuming. 1404132904Spjd * PHY handling such as power down/resetting to 100Mbps 1405132904Spjd * may be better handled in suspend method in phy driver. 1406132904Spjd */ 1407132904Spjd mii = device_get_softc(sc->age_miibus); 1408132904Spjd mii_pollstat(mii); 1409132904Spjd aneg = 0; 1410132904Spjd if ((mii->mii_media_status & IFM_AVALID) != 0) { 1411132904Spjd switch IFM_SUBTYPE(mii->mii_media_active) { 1412132904Spjd case IFM_10_T: 1413132904Spjd case IFM_100_TX: 1414132904Spjd goto got_link; 1415132904Spjd case IFM_1000_T: 1416132904Spjd aneg++; 1417132904Spjd default: 1418132904Spjd break; 1419132904Spjd } 1420132904Spjd } 1421132904Spjd age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1422132904Spjd MII_100T2CR, 0); 1423132904Spjd age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1424132904Spjd MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1425132904Spjd ANAR_10 | ANAR_CSMA); 1426132904Spjd age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1427132904Spjd MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1428132904Spjd DELAY(1000); 1429132904Spjd if (aneg != 0) { 1430132904Spjd /* Poll link state until jme(4) get a 10/100 link. */ 1431132904Spjd for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1432132904Spjd mii_pollstat(mii); 1433132904Spjd if ((mii->mii_media_status & IFM_AVALID) != 0) { 1434132904Spjd switch (IFM_SUBTYPE( 1435132904Spjd mii->mii_media_active)) { 1436132904Spjd case IFM_10_T: 1437132904Spjd case IFM_100_TX: 1438132904Spjd age_mac_config(sc); 1439132904Spjd goto got_link; 1440132904Spjd default: 1441132904Spjd break; 1442132904Spjd } 1443132904Spjd } 1444132904Spjd AGE_UNLOCK(sc); 1445132904Spjd pause("agelnk", hz); 1446132904Spjd AGE_LOCK(sc); 1447132904Spjd } 1448132904Spjd if (i == MII_ANEGTICKS_GIGE) 1449132904Spjd device_printf(sc->age_dev, 1450132904Spjd "establishing link failed, " 1451132904Spjd "WOL may not work!"); 1452132904Spjd } 1453132904Spjd /* 1454132904Spjd * No link, force MAC to have 100Mbps, full-duplex link. 1455132904Spjd * This is the last resort and may/may not work. 1456132904Spjd */ 1457132904Spjd mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1458132904Spjd mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1459132904Spjd age_mac_config(sc); 1460132904Spjd } 1461132904Spjd 1462132904Spjdgot_link: 1463132904Spjd pmcs = 0; 1464132904Spjd if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1465132904Spjd pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1466132904Spjd CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1467132904Spjd reg = CSR_READ_4(sc, AGE_MAC_CFG); 1468132904Spjd reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1469132904Spjd reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1470132904Spjd if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1471132904Spjd reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1472132904Spjd if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1473132904Spjd reg |= MAC_CFG_RX_ENB; 1474132904Spjd CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1475132904Spjd } 1476132904Spjd 1477132904Spjd /* Request PME. */ 1478132904Spjd pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1479132904Spjd pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1480132904Spjd if ((ifp->if_capenable & IFCAP_WOL) != 0) 1481132904Spjd pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1482132904Spjd pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1483132904Spjd#ifdef notyet 1484132904Spjd /* See above for powering down PHY issues. */ 1485132904Spjd if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1486132904Spjd /* No WOL, PHY power down. */ 1487132904Spjd age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1488132904Spjd MII_BMCR, BMCR_PDOWN); 1489132904Spjd } 1490132904Spjd#endif 1491132904Spjd} 1492132904Spjd 1493132904Spjdstatic int 1494132904Spjdage_suspend(device_t dev) 1495132904Spjd{ 1496132904Spjd struct age_softc *sc; 1497132904Spjd 1498132904Spjd sc = device_get_softc(dev); 1499132904Spjd 1500132904Spjd AGE_LOCK(sc); 1501132904Spjd age_stop(sc); 1502132904Spjd age_setwol(sc); 1503132904Spjd AGE_UNLOCK(sc); 1504132904Spjd 1505132904Spjd return (0); 1506132904Spjd} 1507132904Spjd 1508132904Spjdstatic int 1509132904Spjdage_resume(device_t dev) 1510132904Spjd{ 1511132904Spjd struct age_softc *sc; 1512132904Spjd struct ifnet *ifp; 1513132904Spjd uint16_t cmd; 1514132904Spjd 1515132904Spjd sc = device_get_softc(dev); 1516132904Spjd 1517132904Spjd AGE_LOCK(sc); 1518132904Spjd /* 1519132904Spjd * Clear INTx emulation disable for hardwares that 1520132904Spjd * is set in resume event. From Linux. 1521132904Spjd */ 1522132904Spjd cmd = pci_read_config(sc->age_dev, PCIR_COMMAND, 2); 1523132904Spjd if ((cmd & 0x0400) != 0) { 1524132904Spjd cmd &= ~0x0400; 1525132904Spjd pci_write_config(sc->age_dev, PCIR_COMMAND, cmd, 2); 1526132904Spjd } 1527132904Spjd ifp = sc->age_ifp; 1528132904Spjd if ((ifp->if_flags & IFF_UP) != 0) 1529132904Spjd age_init_locked(sc); 1530132904Spjd 1531132904Spjd AGE_UNLOCK(sc); 1532132904Spjd 1533132904Spjd return (0); 1534132904Spjd} 1535132904Spjd 1536132904Spjdstatic int 1537132904Spjdage_encap(struct age_softc *sc, struct mbuf **m_head) 1538132904Spjd{ 1539132904Spjd struct age_txdesc *txd, *txd_last; 1540132904Spjd struct tx_desc *desc; 1541132904Spjd struct mbuf *m; 1542132904Spjd struct ip *ip; 1543132904Spjd struct tcphdr *tcp; 1544132904Spjd bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1545132904Spjd bus_dmamap_t map; 1546132904Spjd uint32_t cflags, ip_off, poff, vtag; 1547132904Spjd int error, i, nsegs, prod, si; 1548132904Spjd 1549132904Spjd AGE_LOCK_ASSERT(sc); 1550132904Spjd 1551132904Spjd M_ASSERTPKTHDR((*m_head)); 1552132904Spjd 1553132904Spjd m = *m_head; 1554132904Spjd ip = NULL; 1555132904Spjd tcp = NULL; 1556132904Spjd cflags = vtag = 0; 1557132904Spjd ip_off = poff = 0; 1558132904Spjd if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1559132904Spjd /* 1560132904Spjd * L1 requires offset of TCP/UDP payload in its Tx 1561132904Spjd * descriptor to perform hardware Tx checksum offload. 1562132904Spjd * Additionally, TSO requires IP/TCP header size and 1563132904Spjd * modification of IP/TCP header in order to make TSO 1564132904Spjd * engine work. This kind of operation takes many CPU 1565132904Spjd * cycles on FreeBSD so fast host CPU is needed to get 1566132904Spjd * smooth TSO performance. 1567132904Spjd */ 1568132904Spjd struct ether_header *eh; 1569132904Spjd 1570132904Spjd if (M_WRITABLE(m) == 0) { 1571132904Spjd /* Get a writable copy. */ 1572132904Spjd m = m_dup(*m_head, M_DONTWAIT); 1573132904Spjd /* Release original mbufs. */ 1574132904Spjd m_freem(*m_head); 1575132904Spjd if (m == NULL) { 1576132904Spjd *m_head = NULL; 1577132904Spjd return (ENOBUFS); 1578132904Spjd } 1579132904Spjd *m_head = m; 1580132904Spjd } 1581132904Spjd ip_off = sizeof(struct ether_header); 1582132904Spjd m = m_pullup(m, ip_off); 1583132904Spjd if (m == NULL) { 1584132904Spjd *m_head = NULL; 1585132904Spjd return (ENOBUFS); 1586132904Spjd } 1587132904Spjd eh = mtod(m, struct ether_header *); 1588132904Spjd /* 1589132904Spjd * Check if hardware VLAN insertion is off. 1590132904Spjd * Additional check for LLC/SNAP frame? 1591132904Spjd */ 1592132904Spjd if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1593132904Spjd ip_off = sizeof(struct ether_vlan_header); 1594132904Spjd m = m_pullup(m, ip_off); 1595132904Spjd if (m == NULL) { 1596132904Spjd *m_head = NULL; 1597132904Spjd return (ENOBUFS); 1598132904Spjd } 1599132904Spjd } 1600132904Spjd m = m_pullup(m, ip_off + sizeof(struct ip)); 1601132904Spjd if (m == NULL) { 1602132904Spjd *m_head = NULL; 1603132904Spjd return (ENOBUFS); 1604132904Spjd } 1605132904Spjd ip = (struct ip *)(mtod(m, char *) + ip_off); 1606132904Spjd poff = ip_off + (ip->ip_hl << 2); 1607132904Spjd if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1608132904Spjd m = m_pullup(m, poff + sizeof(struct tcphdr)); 1609132904Spjd if (m == NULL) { 1610132904Spjd *m_head = NULL; 1611132904Spjd return (ENOBUFS); 1612132904Spjd } 1613132904Spjd tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1614132904Spjd /* 1615132904Spjd * L1 requires IP/TCP header size and offset as 1616132904Spjd * well as TCP pseudo checksum which complicates 1617132904Spjd * TSO configuration. I guess this comes from the 1618132904Spjd * adherence to Microsoft NDIS Large Send 1619132904Spjd * specification which requires insertion of 1620132904Spjd * pseudo checksum by upper stack. The pseudo 1621132904Spjd * checksum that NDIS refers to doesn't include 1622132904Spjd * TCP payload length so age(4) should recompute 1623132904Spjd * the pseudo checksum here. Hopefully this wouldn't 1624132904Spjd * be much burden on modern CPUs. 1625132904Spjd * Reset IP checksum and recompute TCP pseudo 1626132904Spjd * checksum as NDIS specification said. 1627132904Spjd */ 1628132904Spjd ip->ip_sum = 0; 1629132904Spjd if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) 1630132904Spjd tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1631132904Spjd ip->ip_dst.s_addr, 1632132904Spjd htons((tcp->th_off << 2) + IPPROTO_TCP)); 1633132904Spjd else 1634132904Spjd tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1635132904Spjd ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1636132904Spjd } 1637132904Spjd *m_head = m; 1638132904Spjd } 1639132904Spjd 1640132904Spjd si = prod = sc->age_cdata.age_tx_prod; 1641132904Spjd txd = &sc->age_cdata.age_txdesc[prod]; 1642132904Spjd txd_last = txd; 1643132904Spjd map = txd->tx_dmamap; 1644132904Spjd 1645132904Spjd error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1646132904Spjd *m_head, txsegs, &nsegs, 0); 1647132904Spjd if (error == EFBIG) { 1648132904Spjd m = m_collapse(*m_head, M_DONTWAIT, AGE_MAXTXSEGS); 1649132904Spjd if (m == NULL) { 1650132904Spjd m_freem(*m_head); 1651132904Spjd *m_head = NULL; 1652132904Spjd return (ENOMEM); 1653132904Spjd } 1654132904Spjd *m_head = m; 1655132904Spjd error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1656132904Spjd *m_head, txsegs, &nsegs, 0); 1657132904Spjd if (error != 0) { 1658132904Spjd m_freem(*m_head); 1659132904Spjd *m_head = NULL; 1660132904Spjd return (error); 1661132904Spjd } 1662132904Spjd } else if (error != 0) 1663132904Spjd return (error); 1664132904Spjd if (nsegs == 0) { 1665132904Spjd m_freem(*m_head); 1666132904Spjd *m_head = NULL; 1667132904Spjd return (EIO); 1668132904Spjd } 1669132904Spjd 1670132904Spjd /* Check descriptor overrun. */ 1671132904Spjd if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1672132904Spjd bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1673132904Spjd return (ENOBUFS); 1674132904Spjd } 1675132904Spjd 1676132904Spjd m = *m_head; 1677132904Spjd /* Configure Tx IP/TCP/UDP checksum offload. */ 1678132904Spjd if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1679132904Spjd cflags |= AGE_TD_CSUM; 1680132904Spjd if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1681132904Spjd cflags |= AGE_TD_TCPCSUM; 1682132904Spjd if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1683132904Spjd cflags |= AGE_TD_UDPCSUM; 1684132904Spjd /* Set checksum start offset. */ 1685132904Spjd cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1686132904Spjd /* Set checksum insertion position of TCP/UDP. */ 1687132904Spjd cflags |= ((poff + m->m_pkthdr.csum_data) << 1688132904Spjd AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1689132904Spjd } 1690132904Spjd 1691132904Spjd /* Configure TSO. */ 1692132904Spjd if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1693132904Spjd if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1694132904Spjd /* Not TSO but IP/TCP checksum offload. */ 1695132904Spjd cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1696132904Spjd /* Clear TSO in order not to set AGE_TD_TSO_HDR. */ 1697132904Spjd m->m_pkthdr.csum_flags &= ~CSUM_TSO; 1698132904Spjd } else { 1699132904Spjd /* Request TSO and set MSS. */ 1700132904Spjd cflags |= AGE_TD_TSO_IPV4; 1701132904Spjd cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1702132904Spjd cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1703132904Spjd AGE_TD_TSO_MSS_SHIFT); 1704132904Spjd } 1705132904Spjd /* Set IP/TCP header size. */ 1706132904Spjd cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1707132904Spjd cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1708132904Spjd } 1709132904Spjd 1710132904Spjd /* Configure VLAN hardware tag insertion. */ 1711132904Spjd if ((m->m_flags & M_VLANTAG) != 0) { 1712132904Spjd vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1713132904Spjd vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1714132904Spjd cflags |= AGE_TD_INSERT_VLAN_TAG; 1715132904Spjd } 1716132904Spjd 1717132904Spjd desc = NULL; 1718132904Spjd for (i = 0; i < nsegs; i++) { 1719132904Spjd desc = &sc->age_rdata.age_tx_ring[prod]; 1720132904Spjd desc->addr = htole64(txsegs[i].ds_addr); 1721132904Spjd desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1722132904Spjd desc->flags = htole32(cflags); 1723132904Spjd sc->age_cdata.age_tx_cnt++; 1724132904Spjd AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1725132904Spjd } 1726132904Spjd /* Update producer index. */ 1727132904Spjd sc->age_cdata.age_tx_prod = prod; 1728132904Spjd 1729132904Spjd /* Set EOP on the last descriptor. */ 1730132904Spjd prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1731132904Spjd desc = &sc->age_rdata.age_tx_ring[prod]; 1732132904Spjd desc->flags |= htole32(AGE_TD_EOP); 1733132904Spjd 1734132904Spjd /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1735132904Spjd if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1736132904Spjd desc = &sc->age_rdata.age_tx_ring[si]; 1737132904Spjd desc->flags |= htole32(AGE_TD_TSO_HDR); 1738132904Spjd } 1739132904Spjd 1740132904Spjd /* Swap dmamap of the first and the last. */ 1741132904Spjd txd = &sc->age_cdata.age_txdesc[prod]; 1742132904Spjd map = txd_last->tx_dmamap; 1743132904Spjd txd_last->tx_dmamap = txd->tx_dmamap; 1744132904Spjd txd->tx_dmamap = map; 1745132904Spjd txd->tx_m = m; 1746132904Spjd 1747132904Spjd /* Sync descriptors. */ 1748132904Spjd bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1749132904Spjd bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1750132904Spjd sc->age_cdata.age_tx_ring_map, 1751132904Spjd BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1752132904Spjd 1753133079Spjd return (0); 1754133079Spjd} 1755132904Spjd 1756132904Spjdstatic void 1757132904Spjdage_tx_task(void *arg, int pending) 1758132904Spjd{ 1759132904Spjd struct ifnet *ifp; 1760132904Spjd 1761132904Spjd ifp = (struct ifnet *)arg; 1762132904Spjd age_start(ifp); 1763132904Spjd} 1764132941Spjd 1765132941Spjdstatic void 1766132904Spjdage_start(struct ifnet *ifp) 1767132904Spjd{ 1768132904Spjd struct age_softc *sc; 1769132904Spjd struct mbuf *m_head; 1770132904Spjd int enq; 1771132904Spjd 1772132904Spjd sc = ifp->if_softc; 1773132904Spjd 1774132904Spjd AGE_LOCK(sc); 1775132904Spjd 1776132904Spjd if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1777132904Spjd IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) { 1778132904Spjd AGE_UNLOCK(sc); 1779132904Spjd return; 1780132904Spjd } 1781132904Spjd 1782132904Spjd for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1783132904Spjd IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1784132904Spjd if (m_head == NULL) 1785132904Spjd break; 1786132904Spjd /* 1787132904Spjd * Pack the data into the transmit ring. If we 1788132904Spjd * don't have room, set the OACTIVE flag and wait 1789132904Spjd * for the NIC to drain the ring. 1790132904Spjd */ 1791132904Spjd if (age_encap(sc, &m_head)) { 1792132904Spjd if (m_head == NULL) 1793132904Spjd break; 1794132904Spjd IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1795132904Spjd ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1796132904Spjd break; 1797132904Spjd } 1798132904Spjd 1799132904Spjd enq++; 1800132904Spjd /* 1801132904Spjd * If there's a BPF listener, bounce a copy of this frame 1802132904Spjd * to him. 1803132904Spjd */ 1804132904Spjd ETHER_BPF_MTAP(ifp, m_head); 1805132904Spjd } 1806132904Spjd 1807132904Spjd if (enq > 0) { 1808132904Spjd /* Update mbox. */ 1809132904Spjd AGE_COMMIT_MBOX(sc); 1810132904Spjd /* Set a timeout in case the chip goes out to lunch. */ 1811132904Spjd sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1812132904Spjd } 1813132904Spjd 1814132904Spjd AGE_UNLOCK(sc); 1815132904Spjd} 1816132904Spjd 1817132904Spjdstatic void 1818132904Spjdage_watchdog(struct age_softc *sc) 1819132904Spjd{ 1820132904Spjd struct ifnet *ifp; 1821132904Spjd 1822132904Spjd AGE_LOCK_ASSERT(sc); 1823132904Spjd 1824132904Spjd if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1825132904Spjd return; 1826132904Spjd 1827132904Spjd ifp = sc->age_ifp; 1828132904Spjd if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1829132904Spjd if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1830132904Spjd ifp->if_oerrors++; 1831132904Spjd age_init_locked(sc); 1832132904Spjd return; 1833132904Spjd } 1834132904Spjd if (sc->age_cdata.age_tx_cnt == 0) { 1835132904Spjd if_printf(sc->age_ifp, 1836132904Spjd "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1837132904Spjd if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1838132904Spjd taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 1839132904Spjd return; 1840132904Spjd } 1841132904Spjd if_printf(sc->age_ifp, "watchdog timeout\n"); 1842132904Spjd ifp->if_oerrors++; 1843132904Spjd age_init_locked(sc); 1844132904Spjd if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1845132904Spjd taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 1846132904Spjd} 1847132904Spjd 1848132904Spjdstatic int 1849132904Spjdage_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1850132904Spjd{ 1851132904Spjd struct age_softc *sc; 1852132904Spjd struct ifreq *ifr; 1853132904Spjd struct mii_data *mii; 1854132904Spjd uint32_t reg; 1855132904Spjd int error, mask; 1856132904Spjd 1857132904Spjd sc = ifp->if_softc; 1858132904Spjd ifr = (struct ifreq *)data; 1859132904Spjd error = 0; 1860132904Spjd switch (cmd) { 1861132904Spjd case SIOCSIFMTU: 1862132904Spjd if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1863132904Spjd error = EINVAL; 1864132904Spjd else if (ifp->if_mtu != ifr->ifr_mtu) { 1865132904Spjd AGE_LOCK(sc); 1866132904Spjd ifp->if_mtu = ifr->ifr_mtu; 1867132904Spjd if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1868132904Spjd age_init_locked(sc); 1869132904Spjd AGE_UNLOCK(sc); 1870132904Spjd } 1871132904Spjd break; 1872132904Spjd case SIOCSIFFLAGS: 1873132904Spjd AGE_LOCK(sc); 1874132904Spjd if ((ifp->if_flags & IFF_UP) != 0) { 1875132904Spjd if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1876132904Spjd if (((ifp->if_flags ^ sc->age_if_flags) 1877132904Spjd & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1878132904Spjd age_rxfilter(sc); 1879132904Spjd } else { 1880132904Spjd if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1881132904Spjd age_init_locked(sc); 1882132904Spjd } 1883132904Spjd } else { 1884132904Spjd if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1885132904Spjd age_stop(sc); 1886132904Spjd } 1887132904Spjd sc->age_if_flags = ifp->if_flags; 1888132904Spjd AGE_UNLOCK(sc); 1889132904Spjd break; 1890132904Spjd case SIOCADDMULTI: 1891132904Spjd case SIOCDELMULTI: 1892132904Spjd AGE_LOCK(sc); 1893132904Spjd if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1894132904Spjd age_rxfilter(sc); 1895132904Spjd AGE_UNLOCK(sc); 1896132904Spjd break; 1897132904Spjd case SIOCSIFMEDIA: 1898132904Spjd case SIOCGIFMEDIA: 1899132904Spjd mii = device_get_softc(sc->age_miibus); 1900132904Spjd error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1901132904Spjd break; 1902132954Spjd case SIOCSIFCAP: 1903132954Spjd AGE_LOCK(sc); 1904132904Spjd mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1905132904Spjd if ((mask & IFCAP_TXCSUM) != 0 && 1906132904Spjd (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1907132904Spjd ifp->if_capenable ^= IFCAP_TXCSUM; 1908132904Spjd if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1909132904Spjd ifp->if_hwassist |= AGE_CSUM_FEATURES; 1910132904Spjd else 1911132904Spjd ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1912132904Spjd } 1913132904Spjd if ((mask & IFCAP_RXCSUM) != 0 && 1914132904Spjd (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1915132904Spjd ifp->if_capenable ^= IFCAP_RXCSUM; 1916132904Spjd reg = CSR_READ_4(sc, AGE_MAC_CFG); 1917132904Spjd reg &= ~MAC_CFG_RXCSUM_ENB; 1918132904Spjd if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1919132904Spjd reg |= MAC_CFG_RXCSUM_ENB; 1920132904Spjd CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1921132904Spjd } 1922132904Spjd if ((mask & IFCAP_TSO4) != 0 && 1923132904Spjd (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1924132904Spjd ifp->if_capenable ^= IFCAP_TSO4; 1925132904Spjd if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1926132904Spjd ifp->if_hwassist |= CSUM_TSO; 1927132904Spjd else 1928132904Spjd ifp->if_hwassist &= ~CSUM_TSO; 1929132904Spjd } 1930132904Spjd 1931132904Spjd if ((mask & IFCAP_WOL_MCAST) != 0 && 1932132904Spjd (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1933132904Spjd ifp->if_capenable ^= IFCAP_WOL_MCAST; 1934132904Spjd if ((mask & IFCAP_WOL_MAGIC) != 0 && 1935132904Spjd (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1936132904Spjd ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1937132904Spjd 1938132904Spjd if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1939132904Spjd (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1940132904Spjd ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1941132904Spjd age_rxvlan(sc); 1942132904Spjd } 1943132904Spjd if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1944132904Spjd (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1945132904Spjd ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1946132904Spjd if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1947132904Spjd (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1948132904Spjd ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1949132904Spjd /* 1950132904Spjd * VLAN hardware tagging is required to do checksum 1951132904Spjd * offload or TSO on VLAN interface. Checksum offload 1952133115Spjd * on VLAN interface also requires hardware assistance 1953133115Spjd * of parent interface. 1954133115Spjd */ 1955133115Spjd if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 1956133115Spjd ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 1957133115Spjd if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1958133115Spjd ifp->if_capenable &= 1959133115Spjd ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1960133115Spjd AGE_UNLOCK(sc); 1961133115Spjd VLAN_CAPABILITIES(ifp); 1962133115Spjd break; 1963133115Spjd default: 1964133115Spjd error = ether_ioctl(ifp, cmd, data); 1965133115Spjd break; 1966133115Spjd } 1967133115Spjd 1968133115Spjd return (error); 1969132904Spjd} 1970132904Spjd 1971132904Spjdstatic void 1972132904Spjdage_mac_config(struct age_softc *sc) 1973132904Spjd{ 1974132904Spjd struct mii_data *mii; 1975132904Spjd uint32_t reg; 1976132904Spjd 1977132904Spjd AGE_LOCK_ASSERT(sc); 1978132904Spjd 1979132904Spjd mii = device_get_softc(sc->age_miibus); 1980132904Spjd reg = CSR_READ_4(sc, AGE_MAC_CFG); 1981132904Spjd reg &= ~MAC_CFG_FULL_DUPLEX; 1982132904Spjd reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1983132904Spjd reg &= ~MAC_CFG_SPEED_MASK; 1984132904Spjd /* Reprogram MAC with resolved speed/duplex. */ 1985132904Spjd switch (IFM_SUBTYPE(mii->mii_media_active)) { 1986132904Spjd case IFM_10_T: 1987132904Spjd case IFM_100_TX: 1988132904Spjd reg |= MAC_CFG_SPEED_10_100; 1989132904Spjd break; 1990132904Spjd case IFM_1000_T: 1991132904Spjd reg |= MAC_CFG_SPEED_1000; 1992132904Spjd break; 1993132904Spjd } 1994132904Spjd if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1995132904Spjd reg |= MAC_CFG_FULL_DUPLEX; 1996132904Spjd#ifdef notyet 1997132904Spjd if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1998132904Spjd reg |= MAC_CFG_TX_FC; 1999132904Spjd if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2000132904Spjd reg |= MAC_CFG_RX_FC; 2001132904Spjd#endif 2002132904Spjd } 2003132904Spjd 2004132904Spjd CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2005132904Spjd} 2006132904Spjd 2007132904Spjdstatic void 2008132904Spjdage_link_task(void *arg, int pending) 2009132904Spjd{ 2010132904Spjd struct age_softc *sc; 2011132904Spjd struct mii_data *mii; 2012132904Spjd struct ifnet *ifp; 2013132904Spjd uint32_t reg; 2014132904Spjd 2015132904Spjd sc = (struct age_softc *)arg; 2016132904Spjd 2017132904Spjd AGE_LOCK(sc); 2018132904Spjd mii = device_get_softc(sc->age_miibus); 2019132904Spjd ifp = sc->age_ifp; 2020132904Spjd if (mii == NULL || ifp == NULL || 2021132904Spjd (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2022132904Spjd AGE_UNLOCK(sc); 2023132904Spjd return; 2024132904Spjd } 2025132904Spjd 2026132904Spjd sc->age_flags &= ~AGE_FLAG_LINK; 2027132904Spjd if ((mii->mii_media_status & IFM_AVALID) != 0) { 2028132904Spjd switch (IFM_SUBTYPE(mii->mii_media_active)) { 2029132904Spjd case IFM_10_T: 2030132904Spjd case IFM_100_TX: 2031132904Spjd case IFM_1000_T: 2032132904Spjd sc->age_flags |= AGE_FLAG_LINK; 2033132904Spjd break; 2034132904Spjd default: 2035132904Spjd break; 2036132904Spjd } 2037132904Spjd } 2038132904Spjd 2039132904Spjd /* Stop Rx/Tx MACs. */ 2040132904Spjd age_stop_rxmac(sc); 2041132904Spjd age_stop_txmac(sc); 2042132904Spjd 2043132904Spjd /* Program MACs with resolved speed/duplex/flow-control. */ 2044132904Spjd if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 2045132904Spjd age_mac_config(sc); 2046132904Spjd reg = CSR_READ_4(sc, AGE_MAC_CFG); 2047132904Spjd /* Restart DMA engine and Tx/Rx MAC. */ 2048132904Spjd CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 2049132904Spjd DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 2050132904Spjd reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2051132904Spjd CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2052132904Spjd } 2053132904Spjd 2054132904Spjd AGE_UNLOCK(sc); 2055132904Spjd} 2056132904Spjd 2057132904Spjdstatic void 2058132904Spjdage_stats_update(struct age_softc *sc) 2059132904Spjd{ 2060132904Spjd struct age_stats *stat; 2061132904Spjd struct smb *smb; 2062132904Spjd struct ifnet *ifp; 2063132904Spjd 2064132904Spjd AGE_LOCK_ASSERT(sc); 2065132904Spjd 2066132904Spjd stat = &sc->age_stat; 2067132904Spjd 2068132904Spjd bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2069132904Spjd sc->age_cdata.age_smb_block_map, 2070132904Spjd BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2071132904Spjd 2072132904Spjd smb = sc->age_rdata.age_smb_block; 2073132904Spjd if (smb->updated == 0) 2074132904Spjd return; 2075132904Spjd 2076132904Spjd ifp = sc->age_ifp; 2077132904Spjd /* Rx stats. */ 2078132904Spjd stat->rx_frames += smb->rx_frames; 2079132904Spjd stat->rx_bcast_frames += smb->rx_bcast_frames; 2080132904Spjd stat->rx_mcast_frames += smb->rx_mcast_frames; 2081132904Spjd stat->rx_pause_frames += smb->rx_pause_frames; 2082132904Spjd stat->rx_control_frames += smb->rx_control_frames; 2083132904Spjd stat->rx_crcerrs += smb->rx_crcerrs; 2084132904Spjd stat->rx_lenerrs += smb->rx_lenerrs; 2085132904Spjd stat->rx_bytes += smb->rx_bytes; 2086132904Spjd stat->rx_runts += smb->rx_runts; 2087132904Spjd stat->rx_fragments += smb->rx_fragments; 2088132904Spjd stat->rx_pkts_64 += smb->rx_pkts_64; 2089132904Spjd stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2090132904Spjd stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2091132904Spjd stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2092132904Spjd stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2093132904Spjd stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2094132904Spjd stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2095132904Spjd stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2096132904Spjd stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2097132904Spjd stat->rx_desc_oflows += smb->rx_desc_oflows; 2098132904Spjd stat->rx_alignerrs += smb->rx_alignerrs; 2099132904Spjd stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2100132904Spjd stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2101132904Spjd stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2102132904Spjd 2103132904Spjd /* Tx stats. */ 2104132904Spjd stat->tx_frames += smb->tx_frames; 2105132904Spjd stat->tx_bcast_frames += smb->tx_bcast_frames; 2106132904Spjd stat->tx_mcast_frames += smb->tx_mcast_frames; 2107132904Spjd stat->tx_pause_frames += smb->tx_pause_frames; 2108132904Spjd stat->tx_excess_defer += smb->tx_excess_defer; 2109132904Spjd stat->tx_control_frames += smb->tx_control_frames; 2110132904Spjd stat->tx_deferred += smb->tx_deferred; 2111132904Spjd stat->tx_bytes += smb->tx_bytes; 2112132904Spjd stat->tx_pkts_64 += smb->tx_pkts_64; 2113132904Spjd stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2114132904Spjd stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2115132904Spjd stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2116132904Spjd stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2117132904Spjd stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2118132904Spjd stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2119132904Spjd stat->tx_single_colls += smb->tx_single_colls; 2120132904Spjd stat->tx_multi_colls += smb->tx_multi_colls; 2121132904Spjd stat->tx_late_colls += smb->tx_late_colls; 2122132904Spjd stat->tx_excess_colls += smb->tx_excess_colls; 2123132904Spjd stat->tx_underrun += smb->tx_underrun; 2124132904Spjd stat->tx_desc_underrun += smb->tx_desc_underrun; 2125132904Spjd stat->tx_lenerrs += smb->tx_lenerrs; 2126132904Spjd stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2127132904Spjd stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2128132904Spjd stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2129132904Spjd 2130132904Spjd /* Update counters in ifnet. */ 2131132904Spjd ifp->if_opackets += smb->tx_frames; 2132132904Spjd 2133132904Spjd ifp->if_collisions += smb->tx_single_colls + 2134132904Spjd smb->tx_multi_colls + smb->tx_late_colls + 2135132904Spjd smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2136132904Spjd 2137132904Spjd ifp->if_oerrors += smb->tx_excess_colls + 2138132904Spjd smb->tx_late_colls + smb->tx_underrun + 2139132904Spjd smb->tx_pkts_truncated; 2140132904Spjd 2141132904Spjd ifp->if_ipackets += smb->rx_frames; 2142132904Spjd 2143132904Spjd ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2144132904Spjd smb->rx_runts + smb->rx_pkts_truncated + 2145132904Spjd smb->rx_fifo_oflows + smb->rx_desc_oflows + 2146132904Spjd smb->rx_alignerrs; 2147132904Spjd 2148132904Spjd /* Update done, clear. */ 2149132904Spjd smb->updated = 0; 2150132904Spjd 2151132904Spjd bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2152132904Spjd sc->age_cdata.age_smb_block_map, 2153132904Spjd BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2154132904Spjd} 2155132904Spjd 2156132904Spjdstatic int 2157132904Spjdage_intr(void *arg) 2158132904Spjd{ 2159132904Spjd struct age_softc *sc; 2160132904Spjd uint32_t status; 2161132904Spjd 2162132904Spjd sc = (struct age_softc *)arg; 2163132904Spjd 2164132904Spjd status = CSR_READ_4(sc, AGE_INTR_STATUS); 2165132904Spjd if (status == 0 || (status & AGE_INTRS) == 0) 2166132904Spjd return (FILTER_STRAY); 2167132904Spjd /* Disable interrupts. */ 2168132904Spjd CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2169132904Spjd taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2170132904Spjd 2171132904Spjd return (FILTER_HANDLED); 2172132904Spjd} 2173132904Spjd 2174132904Spjdstatic void 2175132904Spjdage_int_task(void *arg, int pending) 2176132904Spjd{ 2177132904Spjd struct age_softc *sc; 2178132904Spjd struct ifnet *ifp; 2179132904Spjd struct cmb *cmb; 2180132904Spjd uint32_t status; 2181132904Spjd 2182132904Spjd sc = (struct age_softc *)arg; 2183132904Spjd 2184132904Spjd AGE_LOCK(sc); 2185132904Spjd 2186132904Spjd bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2187132904Spjd sc->age_cdata.age_cmb_block_map, 2188132904Spjd BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2189132904Spjd cmb = sc->age_rdata.age_cmb_block; 2190132904Spjd status = le32toh(cmb->intr_status); 2191132904Spjd if (sc->age_morework != 0) 2192132904Spjd status |= INTR_CMB_RX; 2193132904Spjd if ((status & AGE_INTRS) == 0) 2194132904Spjd goto done; 2195132904Spjd 2196132904Spjd sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2197132904Spjd TPD_CONS_SHIFT; 2198132904Spjd sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2199132904Spjd RRD_PROD_SHIFT; 2200132904Spjd /* Let hardware know CMB was served. */ 2201132904Spjd cmb->intr_status = 0; 2202132904Spjd bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2203132904Spjd sc->age_cdata.age_cmb_block_map, 2204132904Spjd BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2205132904Spjd 2206132904Spjd#if 0 2207132904Spjd printf("INTR: 0x%08x\n", status); 2208132904Spjd status &= ~INTR_DIS_DMA; 2209132904Spjd CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2210132904Spjd#endif 2211132904Spjd ifp = sc->age_ifp; 2212132904Spjd if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2213132904Spjd if ((status & INTR_CMB_RX) != 0) 2214132904Spjd sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2215132904Spjd sc->age_process_limit); 2216132904Spjd if ((status & INTR_CMB_TX) != 0) 2217132904Spjd age_txintr(sc, sc->age_tpd_cons); 2218132904Spjd if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2219132904Spjd if ((status & INTR_DMA_RD_TO_RST) != 0) 2220132904Spjd device_printf(sc->age_dev, 2221132904Spjd "DMA read error! -- resetting\n"); 2222132904Spjd if ((status & INTR_DMA_WR_TO_RST) != 0) 2223132904Spjd device_printf(sc->age_dev, 2224132904Spjd "DMA write error! -- resetting\n"); 2225132904Spjd age_init_locked(sc); 2226132904Spjd } 2227132904Spjd if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2228132904Spjd taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 2229132904Spjd if ((status & INTR_SMB) != 0) 2230132904Spjd age_stats_update(sc); 2231132904Spjd } 2232132904Spjd 2233132904Spjd /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2234132904Spjd bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2235132904Spjd sc->age_cdata.age_cmb_block_map, 2236132904Spjd BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2237132904Spjd status = le32toh(cmb->intr_status); 2238132904Spjd if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2239132904Spjd taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2240132904Spjd AGE_UNLOCK(sc); 2241132904Spjd return; 2242132904Spjd } 2243132904Spjd 2244132904Spjddone: 2245132904Spjd /* Re-enable interrupts. */ 2246132904Spjd CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2247132904Spjd AGE_UNLOCK(sc); 2248132904Spjd} 2249132904Spjd 2250132904Spjdstatic void 2251132904Spjdage_txintr(struct age_softc *sc, int tpd_cons) 2252132904Spjd{ 2253132904Spjd struct ifnet *ifp; 2254132904Spjd struct age_txdesc *txd; 2255132904Spjd int cons, prog; 2256132904Spjd 2257132904Spjd AGE_LOCK_ASSERT(sc); 2258132904Spjd 2259132904Spjd ifp = sc->age_ifp; 2260132904Spjd 2261132904Spjd bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2262132904Spjd sc->age_cdata.age_tx_ring_map, 2263132904Spjd BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2264132904Spjd 2265132904Spjd /* 2266132904Spjd * Go through our Tx list and free mbufs for those 2267132904Spjd * frames which have been transmitted. 2268132904Spjd */ 2269132904Spjd cons = sc->age_cdata.age_tx_cons; 2270132904Spjd for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2271132904Spjd if (sc->age_cdata.age_tx_cnt <= 0) 2272132904Spjd break; 2273132904Spjd prog++; 2274132904Spjd ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2275132904Spjd sc->age_cdata.age_tx_cnt--; 2276132904Spjd txd = &sc->age_cdata.age_txdesc[cons]; 2277132904Spjd /* 2278132904Spjd * Clear Tx descriptors, it's not required but would 2279132904Spjd * help debugging in case of Tx issues. 2280132904Spjd */ 2281132904Spjd txd->tx_desc->addr = 0; 2282132904Spjd txd->tx_desc->len = 0; 2283132904Spjd txd->tx_desc->flags = 0; 2284132904Spjd 2285132904Spjd if (txd->tx_m == NULL) 2286132904Spjd continue; 2287132904Spjd /* Reclaim transmitted mbufs. */ 2288132904Spjd bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2289132904Spjd BUS_DMASYNC_POSTWRITE); 2290132904Spjd bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2291132904Spjd m_freem(txd->tx_m); 2292132904Spjd txd->tx_m = NULL; 2293132904Spjd } 2294132904Spjd 2295132904Spjd if (prog > 0) { 2296132904Spjd sc->age_cdata.age_tx_cons = cons; 2297132904Spjd 2298132904Spjd /* 2299132904Spjd * Unarm watchdog timer only when there are no pending 2300132904Spjd * Tx descriptors in queue. 2301132904Spjd */ 2302132904Spjd if (sc->age_cdata.age_tx_cnt == 0) 2303132904Spjd sc->age_watchdog_timer = 0; 2304132904Spjd bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2305132904Spjd sc->age_cdata.age_tx_ring_map, 2306132904Spjd BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2307132904Spjd } 2308132904Spjd} 2309132904Spjd 2310132904Spjd/* Receive a frame. */ 2311132904Spjdstatic void 2312132904Spjdage_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2313132904Spjd{ 2314132904Spjd struct age_rxdesc *rxd; 2315132904Spjd struct rx_desc *desc; 2316132904Spjd struct ifnet *ifp; 2317132904Spjd struct mbuf *mp, *m; 2318132904Spjd uint32_t status, index, vtag; 2319132904Spjd int count, nsegs, pktlen; 2320132904Spjd int rx_cons; 2321132904Spjd 2322132904Spjd AGE_LOCK_ASSERT(sc); 2323132904Spjd 2324132904Spjd ifp = sc->age_ifp; 2325132904Spjd status = le32toh(rxrd->flags); 2326132904Spjd index = le32toh(rxrd->index); 2327132904Spjd rx_cons = AGE_RX_CONS(index); 2328132904Spjd nsegs = AGE_RX_NSEGS(index); 2329132904Spjd 2330132904Spjd sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2331132904Spjd if ((status & AGE_RRD_ERROR) != 0 && 2332132904Spjd (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2333132904Spjd AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 2334132904Spjd /* 2335132904Spjd * We want to pass the following frames to upper 2336132904Spjd * layer regardless of error status of Rx return 2337132904Spjd * ring. 2338132904Spjd * 2339132904Spjd * o IP/TCP/UDP checksum is bad. 2340132904Spjd * o frame length and protocol specific length 2341132904Spjd * does not match. 2342132904Spjd */ 2343132904Spjd sc->age_cdata.age_rx_cons += nsegs; 2344132904Spjd sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2345132904Spjd return; 2346132904Spjd } 2347132904Spjd 2348132904Spjd pktlen = 0; 2349132904Spjd for (count = 0; count < nsegs; count++, 2350132904Spjd AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2351132904Spjd rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2352132904Spjd mp = rxd->rx_m; 2353132904Spjd desc = rxd->rx_desc; 2354132904Spjd /* Add a new receive buffer to the ring. */ 2355132904Spjd if (age_newbuf(sc, rxd) != 0) { 2356132904Spjd ifp->if_iqdrops++; 2357132938Spjd /* Reuse Rx buffers. */ 2358132904Spjd if (sc->age_cdata.age_rxhead != NULL) { 2359132904Spjd m_freem(sc->age_cdata.age_rxhead); 2360132904Spjd AGE_RXCHAIN_RESET(sc); 2361132904Spjd } 2362132904Spjd break; 2363132904Spjd } 2364132904Spjd 2365132904Spjd /* The length of the first mbuf is computed last. */ 2366132904Spjd if (count != 0) { 2367132904Spjd mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 2368132904Spjd pktlen += mp->m_len; 2369132904Spjd } 2370132904Spjd 2371132904Spjd /* Chain received mbufs. */ 2372132904Spjd if (sc->age_cdata.age_rxhead == NULL) { 2373132904Spjd sc->age_cdata.age_rxhead = mp; 2374132904Spjd sc->age_cdata.age_rxtail = mp; 2375132904Spjd } else { 2376132904Spjd mp->m_flags &= ~M_PKTHDR; 2377132904Spjd sc->age_cdata.age_rxprev_tail = 2378132904Spjd sc->age_cdata.age_rxtail; 2379132904Spjd sc->age_cdata.age_rxtail->m_next = mp; 2380132904Spjd sc->age_cdata.age_rxtail = mp; 2381132904Spjd } 2382132904Spjd 2383132904Spjd if (count == nsegs - 1) { 2384132904Spjd /* 2385132938Spjd * It seems that L1 controller has no way 2386132904Spjd * to tell hardware to strip CRC bytes. 2387132904Spjd */ 2388132904Spjd sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 2389132904Spjd if (nsegs > 1) { 2390132904Spjd /* Remove the CRC bytes in chained mbufs. */ 2391132904Spjd pktlen -= ETHER_CRC_LEN; 2392132904Spjd if (mp->m_len <= ETHER_CRC_LEN) { 2393132904Spjd sc->age_cdata.age_rxtail = 2394132904Spjd sc->age_cdata.age_rxprev_tail; 2395132904Spjd sc->age_cdata.age_rxtail->m_len -= 2396132904Spjd (ETHER_CRC_LEN - mp->m_len); 2397132904Spjd sc->age_cdata.age_rxtail->m_next = NULL; 2398132904Spjd m_freem(mp); 2399132904Spjd } else { 2400132904Spjd mp->m_len -= ETHER_CRC_LEN; 2401132904Spjd } 2402132904Spjd } 2403132904Spjd 2404132904Spjd m = sc->age_cdata.age_rxhead; 2405132904Spjd m->m_flags |= M_PKTHDR; 2406132904Spjd m->m_pkthdr.rcvif = ifp; 2407132904Spjd m->m_pkthdr.len = sc->age_cdata.age_rxlen; 2408132904Spjd /* Set the first mbuf length. */ 2409132904Spjd m->m_len = sc->age_cdata.age_rxlen - pktlen; 2410132904Spjd 2411132904Spjd /* 2412132904Spjd * Set checksum information. 2413132904Spjd * It seems that L1 controller can compute partial 2414132904Spjd * checksum. The partial checksum value can be used 2415132904Spjd * to accelerate checksum computation for fragmented 2416132904Spjd * TCP/UDP packets. Upper network stack already 2417132904Spjd * takes advantage of the partial checksum value in 2418132904Spjd * IP reassembly stage. But I'm not sure the 2419132904Spjd * correctness of the partial hardware checksum 2420132904Spjd * assistance due to lack of data sheet. If it is 2421132904Spjd * proven to work on L1 I'll enable it. 2422132904Spjd */ 2423132904Spjd if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2424132904Spjd (status & AGE_RRD_IPV4) != 0) { 2425132904Spjd m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2426132904Spjd if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2427132904Spjd m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2428132904Spjd if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2429132904Spjd (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2430132904Spjd m->m_pkthdr.csum_flags |= 2431132904Spjd CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2432132904Spjd m->m_pkthdr.csum_data = 0xffff; 2433132904Spjd } 2434132904Spjd /* 2435132904Spjd * Don't mark bad checksum for TCP/UDP frames 2436132904Spjd * as fragmented frames may always have set 2437132904Spjd * bad checksummed bit of descriptor status. 2438132904Spjd */ 2439132904Spjd } 2440132904Spjd 2441132904Spjd /* Check for VLAN tagged frames. */ 2442132904Spjd if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2443132904Spjd (status & AGE_RRD_VLAN) != 0) { 2444132904Spjd vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2445132904Spjd m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2446132904Spjd m->m_flags |= M_VLANTAG; 2447132904Spjd } 2448132904Spjd 2449132904Spjd /* Pass it on. */ 2450132904Spjd AGE_UNLOCK(sc); 2451132904Spjd (*ifp->if_input)(ifp, m); 2452132904Spjd AGE_LOCK(sc); 2453132904Spjd 2454132904Spjd /* Reset mbuf chains. */ 2455132904Spjd AGE_RXCHAIN_RESET(sc); 2456132904Spjd } 2457132904Spjd } 2458132904Spjd 2459132904Spjd if (count != nsegs) { 2460132904Spjd sc->age_cdata.age_rx_cons += nsegs; 2461132904Spjd sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2462132904Spjd } else 2463132904Spjd sc->age_cdata.age_rx_cons = rx_cons; 2464132904Spjd} 2465132904Spjd 2466132904Spjdstatic int 2467132904Spjdage_rxintr(struct age_softc *sc, int rr_prod, int count) 2468132904Spjd{ 2469132904Spjd struct rx_rdesc *rxrd; 2470132904Spjd int rr_cons, nsegs, pktlen, prog; 2471132904Spjd 2472132904Spjd AGE_LOCK_ASSERT(sc); 2473132904Spjd 2474132904Spjd rr_cons = sc->age_cdata.age_rr_cons; 2475132904Spjd if (rr_cons == rr_prod) 2476132904Spjd return (0); 2477132904Spjd 2478132904Spjd bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2479132904Spjd sc->age_cdata.age_rr_ring_map, 2480132904Spjd BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2481132904Spjd bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2482132904Spjd sc->age_cdata.age_rx_ring_map, 2483132904Spjd BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2484132904Spjd 2485132904Spjd for (prog = 0; rr_cons != rr_prod; prog++) { 2486132904Spjd if (count <= 0) 2487132904Spjd break; 2488132904Spjd rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2489132904Spjd nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2490132904Spjd if (nsegs == 0) 2491132904Spjd break; 2492132904Spjd /* 2493132904Spjd * Check number of segments against received bytes. 2494132904Spjd * Non-matching value would indicate that hardware 2495132904Spjd * is still trying to update Rx return descriptors. 2496132904Spjd * I'm not sure whether this check is really needed. 2497132904Spjd */ 2498132904Spjd pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2499132904Spjd if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 2500132904Spjd (MCLBYTES - ETHER_ALIGN))) 2501132904Spjd break; 2502132904Spjd 2503132904Spjd prog++; 2504132904Spjd /* Received a frame. */ 2505132904Spjd age_rxeof(sc, rxrd); 2506132904Spjd /* Clear return ring. */ 2507132904Spjd rxrd->index = 0; 2508132904Spjd AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2509132904Spjd } 2510132904Spjd 2511132904Spjd if (prog > 0) { 2512132904Spjd /* Update the consumer index. */ 2513132904Spjd sc->age_cdata.age_rr_cons = rr_cons; 2514132904Spjd 2515132904Spjd /* Sync descriptors. */ 2516132904Spjd bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2517132904Spjd sc->age_cdata.age_rx_ring_map, 2518132904Spjd BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2519132904Spjd bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2520132904Spjd sc->age_cdata.age_rr_ring_map, 2521132904Spjd BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2522132904Spjd 2523132904Spjd /* Notify hardware availability of new Rx buffers. */ 2524132976Spjd AGE_COMMIT_MBOX(sc); 2525132904Spjd } 2526132904Spjd 2527132904Spjd return (count > 0 ? 0 : EAGAIN); 2528132904Spjd} 2529132904Spjd 2530132904Spjdstatic void 2531132904Spjdage_tick(void *arg) 2532132904Spjd{ 2533132904Spjd struct age_softc *sc; 2534132904Spjd struct mii_data *mii; 2535132904Spjd 2536132904Spjd sc = (struct age_softc *)arg; 2537132904Spjd 2538132904Spjd AGE_LOCK_ASSERT(sc); 2539132904Spjd 2540132904Spjd mii = device_get_softc(sc->age_miibus); 2541132904Spjd mii_tick(mii); 2542132904Spjd age_watchdog(sc); 2543132904Spjd callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2544132904Spjd} 2545132904Spjd 2546132904Spjdstatic void 2547132904Spjdage_reset(struct age_softc *sc) 2548132904Spjd{ 2549132904Spjd uint32_t reg; 2550132904Spjd int i; 2551132904Spjd 2552132904Spjd CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2553132904Spjd for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2554132904Spjd DELAY(1); 2555132904Spjd if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 2556132904Spjd break; 2557132904Spjd } 2558132904Spjd if (i == 0) 2559132904Spjd device_printf(sc->age_dev, "master reset timeout!\n"); 2560132904Spjd 2561132904Spjd for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2562132904Spjd if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2563132904Spjd break; 2564132904Spjd DELAY(10); 2565132904Spjd } 2566132904Spjd 2567132904Spjd if (i == 0) 2568132904Spjd device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2569132904Spjd /* Initialize PCIe module. From Linux. */ 2570132904Spjd CSR_WRITE_4(sc, 0x12FC, 0x6500); 2571132904Spjd CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2572132904Spjd} 2573132904Spjd 2574132904Spjdstatic void 2575132904Spjdage_init(void *xsc) 2576132904Spjd{ 2577132904Spjd struct age_softc *sc; 2578132904Spjd 2579132904Spjd sc = (struct age_softc *)xsc; 2580132904Spjd AGE_LOCK(sc); 2581132904Spjd age_init_locked(sc); 2582132904Spjd AGE_UNLOCK(sc); 2583132904Spjd} 2584132904Spjd 2585132904Spjdstatic void 2586132904Spjdage_init_locked(struct age_softc *sc) 2587132904Spjd{ 2588132904Spjd struct ifnet *ifp; 2589132904Spjd struct mii_data *mii; 2590132904Spjd uint8_t eaddr[ETHER_ADDR_LEN]; 2591132904Spjd bus_addr_t paddr; 2592132904Spjd uint32_t reg, fsize; 2593132904Spjd uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2594132904Spjd int error; 2595132904Spjd 2596132904Spjd AGE_LOCK_ASSERT(sc); 2597132904Spjd 2598132904Spjd ifp = sc->age_ifp; 2599132904Spjd mii = device_get_softc(sc->age_miibus); 2600132904Spjd 2601132904Spjd /* 2602132904Spjd * Cancel any pending I/O. 2603132904Spjd */ 2604132904Spjd age_stop(sc); 2605132904Spjd 2606132904Spjd /* 2607132904Spjd * Reset the chip to a known state. 2608132904Spjd */ 2609132904Spjd age_reset(sc); 2610132904Spjd 2611132904Spjd /* Initialize descriptors. */ 2612132904Spjd error = age_init_rx_ring(sc); 2613132904Spjd if (error != 0) { 2614132904Spjd device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2615132904Spjd age_stop(sc); 2616132904Spjd return; 2617132904Spjd } 2618132904Spjd age_init_rr_ring(sc); 2619132904Spjd age_init_tx_ring(sc); 2620132904Spjd age_init_cmb_block(sc); 2621132904Spjd age_init_smb_block(sc); 2622132904Spjd 2623132904Spjd /* Reprogram the station address. */ 2624132904Spjd bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2625132904Spjd CSR_WRITE_4(sc, AGE_PAR0, 2626132907Spjd eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2627132904Spjd CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2628132904Spjd 2629132904Spjd /* Set descriptor base addresses. */ 2630132904Spjd paddr = sc->age_rdata.age_tx_ring_paddr; 2631132904Spjd CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2632132904Spjd paddr = sc->age_rdata.age_rx_ring_paddr; 2633132904Spjd CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2634132904Spjd paddr = sc->age_rdata.age_rr_ring_paddr; 2635132904Spjd CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2636132904Spjd paddr = sc->age_rdata.age_tx_ring_paddr; 2637132904Spjd CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2638132904Spjd paddr = sc->age_rdata.age_cmb_block_paddr; 2639132904Spjd CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2640132904Spjd paddr = sc->age_rdata.age_smb_block_paddr; 2641132904Spjd CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2642132904Spjd /* Set Rx/Rx return descriptor counter. */ 2643132904Spjd CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2644132904Spjd ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2645132904Spjd DESC_RRD_CNT_MASK) | 2646132904Spjd ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2647132904Spjd /* Set Tx descriptor counter. */ 2648132904Spjd CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2649132904Spjd (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2650132904Spjd 2651132904Spjd /* Tell hardware that we're ready to load descriptors. */ 2652132904Spjd CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2653132904Spjd 2654132904Spjd /* 2655132904Spjd * Initialize mailbox register. 2656132904Spjd * Updated producer/consumer index information is exchanged 2657132904Spjd * through this mailbox register. However Tx producer and 2658 * Rx return consumer/Rx producer are all shared such that 2659 * it's hard to separate code path between Tx and Rx without 2660 * locking. If L1 hardware have a separate mail box register 2661 * for Tx and Rx consumer/producer management we could have 2662 * indepent Tx/Rx handler which in turn Rx handler could have 2663 * been run without any locking. 2664 */ 2665 AGE_COMMIT_MBOX(sc); 2666 2667 /* Configure IPG/IFG parameters. */ 2668 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2669 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2670 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2671 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2672 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2673 2674 /* Set parameters for half-duplex media. */ 2675 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2676 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2677 HDPX_CFG_LCOL_MASK) | 2678 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2679 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2680 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2681 HDPX_CFG_ABEBT_MASK) | 2682 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2683 HDPX_CFG_JAMIPG_MASK)); 2684 2685 /* Configure interrupt moderation timer. */ 2686 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2687 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2688 reg &= ~MASTER_MTIMER_ENB; 2689 if (AGE_USECS(sc->age_int_mod) == 0) 2690 reg &= ~MASTER_ITIMER_ENB; 2691 else 2692 reg |= MASTER_ITIMER_ENB; 2693 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2694 if (1 || bootverbose) 2695 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2696 sc->age_int_mod); 2697 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2698 2699 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2700 if (ifp->if_mtu < ETHERMTU) 2701 sc->age_max_frame_size = ETHERMTU; 2702 else 2703 sc->age_max_frame_size = ifp->if_mtu; 2704 sc->age_max_frame_size += ETHER_HDR_LEN + 2705 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2706 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2707 /* Configure jumbo frame. */ 2708 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2709 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2710 (((fsize / sizeof(uint64_t)) << 2711 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2712 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2713 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2714 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2715 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2716 2717 /* Configure flow-control parameters. From Linux. */ 2718 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2719 /* 2720 * Magic workaround for old-L1. 2721 * Don't know which hw revision requires this magic. 2722 */ 2723 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2724 /* 2725 * Another magic workaround for flow-control mode 2726 * change. From Linux. 2727 */ 2728 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2729 } 2730 /* 2731 * TODO 2732 * Should understand pause parameter relationships between FIFO 2733 * size and number of Rx descriptors and Rx return descriptors. 2734 * 2735 * Magic parameters came from Linux. 2736 */ 2737 switch (sc->age_chip_rev) { 2738 case 0x8001: 2739 case 0x9001: 2740 case 0x9002: 2741 case 0x9003: 2742 rxf_hi = AGE_RX_RING_CNT / 16; 2743 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2744 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2745 rrd_lo = AGE_RR_RING_CNT / 16; 2746 break; 2747 default: 2748 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2749 rxf_lo = reg / 16; 2750 if (rxf_lo < 192) 2751 rxf_lo = 192; 2752 rxf_hi = (reg * 7) / 8; 2753 if (rxf_hi < rxf_lo) 2754 rxf_hi = rxf_lo + 16; 2755 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2756 rrd_lo = reg / 8; 2757 rrd_hi = (reg * 7) / 8; 2758 if (rrd_lo < 2) 2759 rrd_lo = 2; 2760 if (rrd_hi < rrd_lo) 2761 rrd_hi = rrd_lo + 3; 2762 break; 2763 } 2764 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2765 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2766 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2767 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2768 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2769 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2770 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2771 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2772 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2773 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2774 2775 /* Configure RxQ. */ 2776 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2777 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2778 RXQ_CFG_RD_BURST_MASK) | 2779 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2780 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2781 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2782 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2783 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2784 2785 /* Configure TxQ. */ 2786 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2787 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2788 TXQ_CFG_TPD_BURST_MASK) | 2789 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2790 TXQ_CFG_TX_FIFO_BURST_MASK) | 2791 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2792 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2793 TXQ_CFG_ENB); 2794 2795 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2796 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2797 TX_JUMBO_TPD_TH_MASK) | 2798 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2799 TX_JUMBO_TPD_IPG_MASK)); 2800 /* Configure DMA parameters. */ 2801 CSR_WRITE_4(sc, AGE_DMA_CFG, 2802 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2803 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2804 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2805 2806 /* Configure CMB DMA write threshold. */ 2807 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2808 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2809 CMB_WR_THRESH_RRD_MASK) | 2810 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2811 CMB_WR_THRESH_TPD_MASK)); 2812 2813 /* Set CMB/SMB timer and enable them. */ 2814 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2815 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2816 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2817 /* Request SMB updates for every seconds. */ 2818 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2819 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2820 2821 /* 2822 * Disable all WOL bits as WOL can interfere normal Rx 2823 * operation. 2824 */ 2825 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2826 2827 /* 2828 * Configure Tx/Rx MACs. 2829 * - Auto-padding for short frames. 2830 * - Enable CRC generation. 2831 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2832 * of MAC is followed after link establishment. 2833 */ 2834 CSR_WRITE_4(sc, AGE_MAC_CFG, 2835 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2836 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2837 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2838 MAC_CFG_PREAMBLE_MASK)); 2839 /* Set up the receive filter. */ 2840 age_rxfilter(sc); 2841 age_rxvlan(sc); 2842 2843 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2844 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2845 reg |= MAC_CFG_RXCSUM_ENB; 2846 2847 /* Ack all pending interrupts and clear it. */ 2848 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2849 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2850 2851 /* Finally enable Tx/Rx MAC. */ 2852 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2853 2854 sc->age_flags &= ~AGE_FLAG_LINK; 2855 /* Switch to the current media. */ 2856 mii_mediachg(mii); 2857 2858 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2859 2860 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2861 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2862} 2863 2864static void 2865age_stop(struct age_softc *sc) 2866{ 2867 struct ifnet *ifp; 2868 struct age_txdesc *txd; 2869 struct age_rxdesc *rxd; 2870 uint32_t reg; 2871 int i; 2872 2873 AGE_LOCK_ASSERT(sc); 2874 /* 2875 * Mark the interface down and cancel the watchdog timer. 2876 */ 2877 ifp = sc->age_ifp; 2878 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2879 sc->age_flags &= ~AGE_FLAG_LINK; 2880 callout_stop(&sc->age_tick_ch); 2881 sc->age_watchdog_timer = 0; 2882 2883 /* 2884 * Disable interrupts. 2885 */ 2886 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2887 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2888 /* Stop CMB/SMB updates. */ 2889 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2890 /* Stop Rx/Tx MAC. */ 2891 age_stop_rxmac(sc); 2892 age_stop_txmac(sc); 2893 /* Stop DMA. */ 2894 CSR_WRITE_4(sc, AGE_DMA_CFG, 2895 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2896 /* Stop TxQ/RxQ. */ 2897 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2898 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2899 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2900 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2901 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2902 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2903 break; 2904 DELAY(10); 2905 } 2906 if (i == 0) 2907 device_printf(sc->age_dev, 2908 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2909 2910 /* Reclaim Rx buffers that have been processed. */ 2911 if (sc->age_cdata.age_rxhead != NULL) 2912 m_freem(sc->age_cdata.age_rxhead); 2913 AGE_RXCHAIN_RESET(sc); 2914 /* 2915 * Free RX and TX mbufs still in the queues. 2916 */ 2917 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2918 rxd = &sc->age_cdata.age_rxdesc[i]; 2919 if (rxd->rx_m != NULL) { 2920 bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2921 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2922 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2923 rxd->rx_dmamap); 2924 m_freem(rxd->rx_m); 2925 rxd->rx_m = NULL; 2926 } 2927 } 2928 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2929 txd = &sc->age_cdata.age_txdesc[i]; 2930 if (txd->tx_m != NULL) { 2931 bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2932 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2933 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2934 txd->tx_dmamap); 2935 m_freem(txd->tx_m); 2936 txd->tx_m = NULL; 2937 } 2938 } 2939} 2940 2941static void 2942age_stop_txmac(struct age_softc *sc) 2943{ 2944 uint32_t reg; 2945 int i; 2946 2947 AGE_LOCK_ASSERT(sc); 2948 2949 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2950 if ((reg & MAC_CFG_TX_ENB) != 0) { 2951 reg &= ~MAC_CFG_TX_ENB; 2952 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2953 } 2954 /* Stop Tx DMA engine. */ 2955 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2956 if ((reg & DMA_CFG_RD_ENB) != 0) { 2957 reg &= ~DMA_CFG_RD_ENB; 2958 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2959 } 2960 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2961 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2962 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2963 break; 2964 DELAY(10); 2965 } 2966 if (i == 0) 2967 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2968} 2969 2970static void 2971age_stop_rxmac(struct age_softc *sc) 2972{ 2973 uint32_t reg; 2974 int i; 2975 2976 AGE_LOCK_ASSERT(sc); 2977 2978 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2979 if ((reg & MAC_CFG_RX_ENB) != 0) { 2980 reg &= ~MAC_CFG_RX_ENB; 2981 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2982 } 2983 /* Stop Rx DMA engine. */ 2984 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2985 if ((reg & DMA_CFG_WR_ENB) != 0) { 2986 reg &= ~DMA_CFG_WR_ENB; 2987 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2988 } 2989 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2990 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2991 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2992 break; 2993 DELAY(10); 2994 } 2995 if (i == 0) 2996 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2997} 2998 2999static void 3000age_init_tx_ring(struct age_softc *sc) 3001{ 3002 struct age_ring_data *rd; 3003 struct age_txdesc *txd; 3004 int i; 3005 3006 AGE_LOCK_ASSERT(sc); 3007 3008 sc->age_cdata.age_tx_prod = 0; 3009 sc->age_cdata.age_tx_cons = 0; 3010 sc->age_cdata.age_tx_cnt = 0; 3011 3012 rd = &sc->age_rdata; 3013 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 3014 for (i = 0; i < AGE_TX_RING_CNT; i++) { 3015 txd = &sc->age_cdata.age_txdesc[i]; 3016 txd->tx_desc = &rd->age_tx_ring[i]; 3017 txd->tx_m = NULL; 3018 } 3019 3020 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 3021 sc->age_cdata.age_tx_ring_map, 3022 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3023} 3024 3025static int 3026age_init_rx_ring(struct age_softc *sc) 3027{ 3028 struct age_ring_data *rd; 3029 struct age_rxdesc *rxd; 3030 int i; 3031 3032 AGE_LOCK_ASSERT(sc); 3033 3034 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 3035 sc->age_morework = 0; 3036 rd = &sc->age_rdata; 3037 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 3038 for (i = 0; i < AGE_RX_RING_CNT; i++) { 3039 rxd = &sc->age_cdata.age_rxdesc[i]; 3040 rxd->rx_m = NULL; 3041 rxd->rx_desc = &rd->age_rx_ring[i]; 3042 if (age_newbuf(sc, rxd) != 0) 3043 return (ENOBUFS); 3044 } 3045 3046 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 3047 sc->age_cdata.age_rx_ring_map, 3048 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3049 3050 return (0); 3051} 3052 3053static void 3054age_init_rr_ring(struct age_softc *sc) 3055{ 3056 struct age_ring_data *rd; 3057 3058 AGE_LOCK_ASSERT(sc); 3059 3060 sc->age_cdata.age_rr_cons = 0; 3061 AGE_RXCHAIN_RESET(sc); 3062 3063 rd = &sc->age_rdata; 3064 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3065 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3066 sc->age_cdata.age_rr_ring_map, 3067 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3068} 3069 3070static void 3071age_init_cmb_block(struct age_softc *sc) 3072{ 3073 struct age_ring_data *rd; 3074 3075 AGE_LOCK_ASSERT(sc); 3076 3077 rd = &sc->age_rdata; 3078 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3079 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3080 sc->age_cdata.age_cmb_block_map, 3081 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3082} 3083 3084static void 3085age_init_smb_block(struct age_softc *sc) 3086{ 3087 struct age_ring_data *rd; 3088 3089 AGE_LOCK_ASSERT(sc); 3090 3091 rd = &sc->age_rdata; 3092 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3093 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3094 sc->age_cdata.age_smb_block_map, 3095 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3096} 3097 3098static int 3099age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3100{ 3101 struct rx_desc *desc; 3102 struct mbuf *m; 3103 bus_dma_segment_t segs[1]; 3104 bus_dmamap_t map; 3105 int nsegs; 3106 3107 AGE_LOCK_ASSERT(sc); 3108 3109 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3110 if (m == NULL) 3111 return (ENOBUFS); 3112 m->m_len = m->m_pkthdr.len = MCLBYTES; 3113 m_adj(m, ETHER_ALIGN); 3114 3115 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3116 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3117 m_freem(m); 3118 return (ENOBUFS); 3119 } 3120 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3121 3122 if (rxd->rx_m != NULL) { 3123 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3124 BUS_DMASYNC_POSTREAD); 3125 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3126 } 3127 map = rxd->rx_dmamap; 3128 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3129 sc->age_cdata.age_rx_sparemap = map; 3130 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3131 BUS_DMASYNC_PREREAD); 3132 rxd->rx_m = m; 3133 3134 desc = rxd->rx_desc; 3135 desc->addr = htole64(segs[0].ds_addr); 3136 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3137 AGE_RD_LEN_SHIFT); 3138 return (0); 3139} 3140 3141static void 3142age_rxvlan(struct age_softc *sc) 3143{ 3144 struct ifnet *ifp; 3145 uint32_t reg; 3146 3147 AGE_LOCK_ASSERT(sc); 3148 3149 ifp = sc->age_ifp; 3150 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3151 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3152 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3153 reg |= MAC_CFG_VLAN_TAG_STRIP; 3154 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3155} 3156 3157static void 3158age_rxfilter(struct age_softc *sc) 3159{ 3160 struct ifnet *ifp; 3161 struct ifmultiaddr *ifma; 3162 uint32_t crc; 3163 uint32_t mchash[2]; 3164 uint32_t rxcfg; 3165 3166 AGE_LOCK_ASSERT(sc); 3167 3168 ifp = sc->age_ifp; 3169 3170 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3171 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3172 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3173 rxcfg |= MAC_CFG_BCAST; 3174 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3175 if ((ifp->if_flags & IFF_PROMISC) != 0) 3176 rxcfg |= MAC_CFG_PROMISC; 3177 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3178 rxcfg |= MAC_CFG_ALLMULTI; 3179 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3180 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3181 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3182 return; 3183 } 3184 3185 /* Program new filter. */ 3186 bzero(mchash, sizeof(mchash)); 3187 3188 IF_ADDR_LOCK(ifp); 3189 TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) { 3190 if (ifma->ifma_addr->sa_family != AF_LINK) 3191 continue; 3192 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 3193 ifma->ifma_addr), ETHER_ADDR_LEN); 3194 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3195 } 3196 IF_ADDR_UNLOCK(ifp); 3197 3198 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3199 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3200 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3201} 3202 3203static int 3204sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3205{ 3206 struct age_softc *sc; 3207 struct age_stats *stats; 3208 int error, result; 3209 3210 result = -1; 3211 error = sysctl_handle_int(oidp, &result, 0, req); 3212 3213 if (error != 0 || req->newptr == NULL) 3214 return (error); 3215 3216 if (result != 1) 3217 return (error); 3218 3219 sc = (struct age_softc *)arg1; 3220 stats = &sc->age_stat; 3221 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3222 printf("Transmit good frames : %ju\n", 3223 (uintmax_t)stats->tx_frames); 3224 printf("Transmit good broadcast frames : %ju\n", 3225 (uintmax_t)stats->tx_bcast_frames); 3226 printf("Transmit good multicast frames : %ju\n", 3227 (uintmax_t)stats->tx_mcast_frames); 3228 printf("Transmit pause control frames : %u\n", 3229 stats->tx_pause_frames); 3230 printf("Transmit control frames : %u\n", 3231 stats->tx_control_frames); 3232 printf("Transmit frames with excessive deferrals : %u\n", 3233 stats->tx_excess_defer); 3234 printf("Transmit deferrals : %u\n", 3235 stats->tx_deferred); 3236 printf("Transmit good octets : %ju\n", 3237 (uintmax_t)stats->tx_bytes); 3238 printf("Transmit good broadcast octets : %ju\n", 3239 (uintmax_t)stats->tx_bcast_bytes); 3240 printf("Transmit good multicast octets : %ju\n", 3241 (uintmax_t)stats->tx_mcast_bytes); 3242 printf("Transmit frames 64 bytes : %ju\n", 3243 (uintmax_t)stats->tx_pkts_64); 3244 printf("Transmit frames 65 to 127 bytes : %ju\n", 3245 (uintmax_t)stats->tx_pkts_65_127); 3246 printf("Transmit frames 128 to 255 bytes : %ju\n", 3247 (uintmax_t)stats->tx_pkts_128_255); 3248 printf("Transmit frames 256 to 511 bytes : %ju\n", 3249 (uintmax_t)stats->tx_pkts_256_511); 3250 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3251 (uintmax_t)stats->tx_pkts_512_1023); 3252 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3253 (uintmax_t)stats->tx_pkts_1024_1518); 3254 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3255 (uintmax_t)stats->tx_pkts_1519_max); 3256 printf("Transmit single collisions : %u\n", 3257 stats->tx_single_colls); 3258 printf("Transmit multiple collisions : %u\n", 3259 stats->tx_multi_colls); 3260 printf("Transmit late collisions : %u\n", 3261 stats->tx_late_colls); 3262 printf("Transmit abort due to excessive collisions : %u\n", 3263 stats->tx_excess_colls); 3264 printf("Transmit underruns due to FIFO underruns : %u\n", 3265 stats->tx_underrun); 3266 printf("Transmit descriptor write-back errors : %u\n", 3267 stats->tx_desc_underrun); 3268 printf("Transmit frames with length mismatched frame size : %u\n", 3269 stats->tx_lenerrs); 3270 printf("Transmit frames with truncated due to MTU size : %u\n", 3271 stats->tx_lenerrs); 3272 3273 printf("Receive good frames : %ju\n", 3274 (uintmax_t)stats->rx_frames); 3275 printf("Receive good broadcast frames : %ju\n", 3276 (uintmax_t)stats->rx_bcast_frames); 3277 printf("Receive good multicast frames : %ju\n", 3278 (uintmax_t)stats->rx_mcast_frames); 3279 printf("Receive pause control frames : %u\n", 3280 stats->rx_pause_frames); 3281 printf("Receive control frames : %u\n", 3282 stats->rx_control_frames); 3283 printf("Receive CRC errors : %u\n", 3284 stats->rx_crcerrs); 3285 printf("Receive frames with length errors : %u\n", 3286 stats->rx_lenerrs); 3287 printf("Receive good octets : %ju\n", 3288 (uintmax_t)stats->rx_bytes); 3289 printf("Receive good broadcast octets : %ju\n", 3290 (uintmax_t)stats->rx_bcast_bytes); 3291 printf("Receive good multicast octets : %ju\n", 3292 (uintmax_t)stats->rx_mcast_bytes); 3293 printf("Receive frames too short : %u\n", 3294 stats->rx_runts); 3295 printf("Receive fragmented frames : %ju\n", 3296 (uintmax_t)stats->rx_fragments); 3297 printf("Receive frames 64 bytes : %ju\n", 3298 (uintmax_t)stats->rx_pkts_64); 3299 printf("Receive frames 65 to 127 bytes : %ju\n", 3300 (uintmax_t)stats->rx_pkts_65_127); 3301 printf("Receive frames 128 to 255 bytes : %ju\n", 3302 (uintmax_t)stats->rx_pkts_128_255); 3303 printf("Receive frames 256 to 511 bytes : %ju\n", 3304 (uintmax_t)stats->rx_pkts_256_511); 3305 printf("Receive frames 512 to 1024 bytes : %ju\n", 3306 (uintmax_t)stats->rx_pkts_512_1023); 3307 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3308 (uintmax_t)stats->rx_pkts_1024_1518); 3309 printf("Receive frames 1519 to MTU bytes : %ju\n", 3310 (uintmax_t)stats->rx_pkts_1519_max); 3311 printf("Receive frames too long : %ju\n", 3312 (uint64_t)stats->rx_pkts_truncated); 3313 printf("Receive frames with FIFO overflow : %u\n", 3314 stats->rx_fifo_oflows); 3315 printf("Receive frames with return descriptor overflow : %u\n", 3316 stats->rx_desc_oflows); 3317 printf("Receive frames with alignment errors : %u\n", 3318 stats->rx_alignerrs); 3319 printf("Receive frames dropped due to address filtering : %ju\n", 3320 (uint64_t)stats->rx_pkts_filtered); 3321 3322 return (error); 3323} 3324 3325static int 3326sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3327{ 3328 int error, value; 3329 3330 if (arg1 == NULL) 3331 return (EINVAL); 3332 value = *(int *)arg1; 3333 error = sysctl_handle_int(oidp, &value, 0, req); 3334 if (error || req->newptr == NULL) 3335 return (error); 3336 if (value < low || value > high) 3337 return (EINVAL); 3338 *(int *)arg1 = value; 3339 3340 return (0); 3341} 3342 3343static int 3344sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3345{ 3346 return (sysctl_int_range(oidp, arg1, arg2, req, 3347 AGE_PROC_MIN, AGE_PROC_MAX)); 3348} 3349 3350static int 3351sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3352{ 3353 3354 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3355 AGE_IM_TIMER_MAX)); 3356} 3357