octeon-pci-console.h revision 210286
1/***********************license start*************** 2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 * 23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31 * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33 * 34 * 35 * For any questions regarding licensing please contact marketing@caviumnetworks.com 36 * 37 ***********************license end**************************************/ 38 39 40 41 42 43 44 45#ifndef __OCTEON_PCI_CONSOLE_H__ 46#define __OCTEON_PCI_CONSOLE_H__ 47 48#include "cvmx-platform.h" 49 50/* Current versions */ 51#define OCTEON_PCI_CONSOLE_MAJOR_VERSION 1 52#define OCTEON_PCI_CONSOLE_MINOR_VERSION 0 53 54#define OCTEON_PCI_CONSOLE_BLOCK_NAME "__pci_console" 55 56 57/* Structure that defines a single console. 58 59 60* Note: when read_index == write_index, the buffer is empty. The actual usable size 61* of each console is console_buf_size -1; 62*/ 63typedef struct { 64 uint64_t input_base_addr; 65 uint32_t input_read_index; 66 uint32_t input_write_index; 67 uint64_t output_base_addr; 68 uint32_t output_read_index; 69 uint32_t output_write_index; 70 uint32_t lock; 71 uint32_t buf_size; 72} octeon_pci_console_t; 73 74 75/* This is the main container structure that contains all the information 76about all PCI consoles. The address of this structure is passed to various 77routines that operation on PCI consoles. 78*/ 79typedef struct { 80 uint32_t major_version; 81 uint32_t minor_version; 82 uint32_t lock; 83 uint32_t flags; 84 uint32_t num_consoles; 85 uint32_t pad; 86 /* must be 64 bit aligned here... */ 87 uint64_t console_addr_array[0]; /* Array of addresses of octeon_pci_console_t structures */ 88 /* Implicit storage for console_addr_array */ 89} octeon_pci_console_desc_t; 90 91 92/* Flag definitions for octeon_pci_console_desc_t */ 93enum { 94 OCT_PCI_CON_DESC_FLAG_PERCPU = 1 << 0, /* If set, output from core N will be sent to console N */ 95}; 96 97#if defined(OCTEON_TARGET) && !defined(__linux__) 98/** 99 * This is an internal-only function that is called from within the simple executive 100 * C library, and is not intended for any other use. 101 * 102 * @param fd 103 * @param buf 104 * @param nbytes 105 * 106 * @return 107 */ 108int __cvmx_pci_console_write (int fd, char *buf, int nbytes); 109#endif 110 111 112#ifdef CVMX_BUILD_FOR_UBOOT 113uint64_t octeon_pci_console_init(int num_consoles, int buffer_size); 114#endif 115 116/* Flag definitions for read/write functions */ 117enum { 118 OCT_PCI_CON_FLAG_NONBLOCK = 1 << 0, /* If set, read/write functions won't block waiting for space or data. 119 * For reads, 0 bytes may be read, and for writes not all of the 120 * supplied data may be written.*/ 121}; 122 123#if !defined(__linux__) || defined(__KERNEL__) 124int octeon_pci_console_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int bytes_to_write, uint32_t flags); 125int octeon_pci_console_write_avail(uint64_t console_desc_addr, unsigned int console_num); 126 127int octeon_pci_console_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buffer_size, uint32_t flags); 128int octeon_pci_console_read_avail(uint64_t console_desc_addr, unsigned int console_num); 129#endif 130 131#if !defined(OCTEON_TARGET) && defined(__linux__) && !defined(__KERNEL__) 132int octeon_pci_console_host_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int write_reqest_size, uint32_t flags); 133int octeon_pci_console_host_write_avail(uint64_t console_desc_addr, unsigned int console_num); 134 135int octeon_pci_console_host_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buf_size, uint32_t flags); 136int octeon_pci_console_host_read_avail(uint64_t console_desc_addr, unsigned int console_num); 137#endif 138#endif 139