cvmx-stxx-defs.h revision 256281
1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-stxx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon stxx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_STXX_DEFS_H__ 53#define __CVMX_STXX_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_STXX_ARB_CTL(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 60 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 61 cvmx_warn("CVMX_STXX_ARB_CTL(%lu) is invalid on this chip\n", block_id); 62 return CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull; 63} 64#else 65#define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull) 66#endif 67#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68static inline uint64_t CVMX_STXX_BCKPRS_CNT(unsigned long block_id) 69{ 70 if (!( 71 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 72 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 73 cvmx_warn("CVMX_STXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id); 74 return CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull; 75} 76#else 77#define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull) 78#endif 79#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80static inline uint64_t CVMX_STXX_COM_CTL(unsigned long block_id) 81{ 82 if (!( 83 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 84 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 85 cvmx_warn("CVMX_STXX_COM_CTL(%lu) is invalid on this chip\n", block_id); 86 return CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull; 87} 88#else 89#define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull) 90#endif 91#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 92static inline uint64_t CVMX_STXX_DIP_CNT(unsigned long block_id) 93{ 94 if (!( 95 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 96 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 97 cvmx_warn("CVMX_STXX_DIP_CNT(%lu) is invalid on this chip\n", block_id); 98 return CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull; 99} 100#else 101#define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull) 102#endif 103#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104static inline uint64_t CVMX_STXX_IGN_CAL(unsigned long block_id) 105{ 106 if (!( 107 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 108 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 109 cvmx_warn("CVMX_STXX_IGN_CAL(%lu) is invalid on this chip\n", block_id); 110 return CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull; 111} 112#else 113#define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull) 114#endif 115#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116static inline uint64_t CVMX_STXX_INT_MSK(unsigned long block_id) 117{ 118 if (!( 119 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 120 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 121 cvmx_warn("CVMX_STXX_INT_MSK(%lu) is invalid on this chip\n", block_id); 122 return CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull; 123} 124#else 125#define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull) 126#endif 127#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 128static inline uint64_t CVMX_STXX_INT_REG(unsigned long block_id) 129{ 130 if (!( 131 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 132 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 133 cvmx_warn("CVMX_STXX_INT_REG(%lu) is invalid on this chip\n", block_id); 134 return CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull; 135} 136#else 137#define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull) 138#endif 139#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 140static inline uint64_t CVMX_STXX_INT_SYNC(unsigned long block_id) 141{ 142 if (!( 143 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 144 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 145 cvmx_warn("CVMX_STXX_INT_SYNC(%lu) is invalid on this chip\n", block_id); 146 return CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull; 147} 148#else 149#define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull) 150#endif 151#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 152static inline uint64_t CVMX_STXX_MIN_BST(unsigned long block_id) 153{ 154 if (!( 155 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 156 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 157 cvmx_warn("CVMX_STXX_MIN_BST(%lu) is invalid on this chip\n", block_id); 158 return CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull; 159} 160#else 161#define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull) 162#endif 163#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 164static inline uint64_t CVMX_STXX_SPI4_CALX(unsigned long offset, unsigned long block_id) 165{ 166 if (!( 167 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) || 168 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1)))))) 169 cvmx_warn("CVMX_STXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id); 170 return CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8; 171} 172#else 173#define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) 174#endif 175#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176static inline uint64_t CVMX_STXX_SPI4_DAT(unsigned long block_id) 177{ 178 if (!( 179 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 180 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 181 cvmx_warn("CVMX_STXX_SPI4_DAT(%lu) is invalid on this chip\n", block_id); 182 return CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull; 183} 184#else 185#define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188static inline uint64_t CVMX_STXX_SPI4_STAT(unsigned long block_id) 189{ 190 if (!( 191 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 192 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 193 cvmx_warn("CVMX_STXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id); 194 return CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull; 195} 196#else 197#define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull) 198#endif 199#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 200static inline uint64_t CVMX_STXX_STAT_BYTES_HI(unsigned long block_id) 201{ 202 if (!( 203 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 204 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 205 cvmx_warn("CVMX_STXX_STAT_BYTES_HI(%lu) is invalid on this chip\n", block_id); 206 return CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull; 207} 208#else 209#define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull) 210#endif 211#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212static inline uint64_t CVMX_STXX_STAT_BYTES_LO(unsigned long block_id) 213{ 214 if (!( 215 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 216 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 217 cvmx_warn("CVMX_STXX_STAT_BYTES_LO(%lu) is invalid on this chip\n", block_id); 218 return CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull; 219} 220#else 221#define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull) 222#endif 223#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 224static inline uint64_t CVMX_STXX_STAT_CTL(unsigned long block_id) 225{ 226 if (!( 227 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 228 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 229 cvmx_warn("CVMX_STXX_STAT_CTL(%lu) is invalid on this chip\n", block_id); 230 return CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull; 231} 232#else 233#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull) 234#endif 235#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236static inline uint64_t CVMX_STXX_STAT_PKT_XMT(unsigned long block_id) 237{ 238 if (!( 239 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 240 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 241 cvmx_warn("CVMX_STXX_STAT_PKT_XMT(%lu) is invalid on this chip\n", block_id); 242 return CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull; 243} 244#else 245#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull) 246#endif 247 248/** 249 * cvmx_stx#_arb_ctl 250 * 251 * STX_ARB_CTL - Spi transmit arbitration control 252 * 253 * 254 * Notes: 255 * If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t 256 * parameter will have to be adjusted. Please see the 257 * STX_SPI4_DAT[MAX_T] section for additional information. In 258 * addition, the min_burst can only be guaranteed on the initial data 259 * burst of a given packet (i.e. the first data burst which contains 260 * the SOP tick). All subsequent bursts could be truncated by training 261 * sequences at any point during transmission and could be arbitrarily 262 * small. This mode is only for use in Spi4 mode. 263 */ 264union cvmx_stxx_arb_ctl { 265 uint64_t u64; 266 struct cvmx_stxx_arb_ctl_s { 267#ifdef __BIG_ENDIAN_BITFIELD 268 uint64_t reserved_6_63 : 58; 269 uint64_t mintrn : 1; /**< Hold off training cycles until STX_MIN_BST[MINB] 270 is satisfied */ 271 uint64_t reserved_4_4 : 1; 272 uint64_t igntpa : 1; /**< User switch to ignore any TPA information from the 273 Spi interface. This CSR forces all TPA terms to 274 be masked out. It is only intended as backdoor 275 or debug feature. */ 276 uint64_t reserved_0_2 : 3; 277#else 278 uint64_t reserved_0_2 : 3; 279 uint64_t igntpa : 1; 280 uint64_t reserved_4_4 : 1; 281 uint64_t mintrn : 1; 282 uint64_t reserved_6_63 : 58; 283#endif 284 } s; 285 struct cvmx_stxx_arb_ctl_s cn38xx; 286 struct cvmx_stxx_arb_ctl_s cn38xxp2; 287 struct cvmx_stxx_arb_ctl_s cn58xx; 288 struct cvmx_stxx_arb_ctl_s cn58xxp1; 289}; 290typedef union cvmx_stxx_arb_ctl cvmx_stxx_arb_ctl_t; 291 292/** 293 * cvmx_stx#_bckprs_cnt 294 * 295 * Notes: 296 * This register reports the total number of cycles (STX data clks - 297 * stx_clk) in which the port defined in STX_STAT_CTL[BCKPRS] has lost TPA 298 * or is otherwise receiving backpressure. 299 * 300 * In Spi4 mode, this is defined as a loss of TPA which is indicated when 301 * the receiving device reports SATISFIED for the given port. The calendar 302 * status is brought into N2 on the spi4_tx*_sclk and synchronized into the 303 * N2 Spi TX clock domain which is 1/2 the frequency of the spi4_tx*_dclk 304 * clock (internally, this the stx_clk). The counter will update on the 305 * rising edge in which backpressure is reported. 306 * 307 * This register will be cleared when software writes all '1's to 308 * the STX_BCKPRS_CNT. 309 */ 310union cvmx_stxx_bckprs_cnt { 311 uint64_t u64; 312 struct cvmx_stxx_bckprs_cnt_s { 313#ifdef __BIG_ENDIAN_BITFIELD 314 uint64_t reserved_32_63 : 32; 315 uint64_t cnt : 32; /**< Number of cycles when back-pressure is received 316 for port defined in STX_STAT_CTL[BCKPRS] */ 317#else 318 uint64_t cnt : 32; 319 uint64_t reserved_32_63 : 32; 320#endif 321 } s; 322 struct cvmx_stxx_bckprs_cnt_s cn38xx; 323 struct cvmx_stxx_bckprs_cnt_s cn38xxp2; 324 struct cvmx_stxx_bckprs_cnt_s cn58xx; 325 struct cvmx_stxx_bckprs_cnt_s cn58xxp1; 326}; 327typedef union cvmx_stxx_bckprs_cnt cvmx_stxx_bckprs_cnt_t; 328 329/** 330 * cvmx_stx#_com_ctl 331 * 332 * STX_COM_CTL - TX Common Control Register 333 * 334 * 335 * Notes: 336 * Restrictions: 337 * Both the calendar table and the LEN and M parameters must be 338 * completely setup before writing the Interface enable (INF_EN) and 339 * Status channel enabled (ST_EN) asserted. 340 */ 341union cvmx_stxx_com_ctl { 342 uint64_t u64; 343 struct cvmx_stxx_com_ctl_s { 344#ifdef __BIG_ENDIAN_BITFIELD 345 uint64_t reserved_4_63 : 60; 346 uint64_t st_en : 1; /**< Status channel enabled */ 347 uint64_t reserved_1_2 : 2; 348 uint64_t inf_en : 1; /**< Interface enable */ 349#else 350 uint64_t inf_en : 1; 351 uint64_t reserved_1_2 : 2; 352 uint64_t st_en : 1; 353 uint64_t reserved_4_63 : 60; 354#endif 355 } s; 356 struct cvmx_stxx_com_ctl_s cn38xx; 357 struct cvmx_stxx_com_ctl_s cn38xxp2; 358 struct cvmx_stxx_com_ctl_s cn58xx; 359 struct cvmx_stxx_com_ctl_s cn58xxp1; 360}; 361typedef union cvmx_stxx_com_ctl cvmx_stxx_com_ctl_t; 362 363/** 364 * cvmx_stx#_dip_cnt 365 * 366 * Notes: 367 * * DIPMAX 368 * This counts the number of consecutive DIP2 states in which the the 369 * received DIP2 is bad. The expected range is 1-15 cycles with the 370 * value of 0 meaning disabled. 371 * 372 * * FRMMAX 373 * This counts the number of consecutive unexpected framing patterns (11) 374 * states. The expected range is 1-15 cycles with the value of 0 meaning 375 * disabled. 376 */ 377union cvmx_stxx_dip_cnt { 378 uint64_t u64; 379 struct cvmx_stxx_dip_cnt_s { 380#ifdef __BIG_ENDIAN_BITFIELD 381 uint64_t reserved_8_63 : 56; 382 uint64_t frmmax : 4; /**< Number of consecutive unexpected framing patterns 383 before loss of sync */ 384 uint64_t dipmax : 4; /**< Number of consecutive DIP2 error before loss 385 of sync */ 386#else 387 uint64_t dipmax : 4; 388 uint64_t frmmax : 4; 389 uint64_t reserved_8_63 : 56; 390#endif 391 } s; 392 struct cvmx_stxx_dip_cnt_s cn38xx; 393 struct cvmx_stxx_dip_cnt_s cn38xxp2; 394 struct cvmx_stxx_dip_cnt_s cn58xx; 395 struct cvmx_stxx_dip_cnt_s cn58xxp1; 396}; 397typedef union cvmx_stxx_dip_cnt cvmx_stxx_dip_cnt_t; 398 399/** 400 * cvmx_stx#_ign_cal 401 * 402 * STX_IGN_CAL - Ignore Calendar Status from Spi4 Status Channel 403 * 404 */ 405union cvmx_stxx_ign_cal { 406 uint64_t u64; 407 struct cvmx_stxx_ign_cal_s { 408#ifdef __BIG_ENDIAN_BITFIELD 409 uint64_t reserved_16_63 : 48; 410 uint64_t igntpa : 16; /**< Ignore Calendar Status from Spi4 Status Channel 411 per Spi4 port 412 - 0: Use the status channel info 413 - 1: Grant the given port MAX_BURST1 credits */ 414#else 415 uint64_t igntpa : 16; 416 uint64_t reserved_16_63 : 48; 417#endif 418 } s; 419 struct cvmx_stxx_ign_cal_s cn38xx; 420 struct cvmx_stxx_ign_cal_s cn38xxp2; 421 struct cvmx_stxx_ign_cal_s cn58xx; 422 struct cvmx_stxx_ign_cal_s cn58xxp1; 423}; 424typedef union cvmx_stxx_ign_cal cvmx_stxx_ign_cal_t; 425 426/** 427 * cvmx_stx#_int_msk 428 * 429 * Notes: 430 * If the bit is enabled, then the coresponding exception condition will 431 * result in an interrupt to the system. 432 */ 433union cvmx_stxx_int_msk { 434 uint64_t u64; 435 struct cvmx_stxx_int_msk_s { 436#ifdef __BIG_ENDIAN_BITFIELD 437 uint64_t reserved_8_63 : 56; 438 uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */ 439 uint64_t unxfrm : 1; /**< Unexpected framing sequence */ 440 uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */ 441 uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */ 442 uint64_t datovr : 1; /**< Spi4 FIFO overflow error */ 443 uint64_t ovrbst : 1; /**< Transmit packet burst too big */ 444 uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */ 445 uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */ 446#else 447 uint64_t calpar0 : 1; 448 uint64_t calpar1 : 1; 449 uint64_t ovrbst : 1; 450 uint64_t datovr : 1; 451 uint64_t diperr : 1; 452 uint64_t nosync : 1; 453 uint64_t unxfrm : 1; 454 uint64_t frmerr : 1; 455 uint64_t reserved_8_63 : 56; 456#endif 457 } s; 458 struct cvmx_stxx_int_msk_s cn38xx; 459 struct cvmx_stxx_int_msk_s cn38xxp2; 460 struct cvmx_stxx_int_msk_s cn58xx; 461 struct cvmx_stxx_int_msk_s cn58xxp1; 462}; 463typedef union cvmx_stxx_int_msk cvmx_stxx_int_msk_t; 464 465/** 466 * cvmx_stx#_int_reg 467 * 468 * Notes: 469 * * CALPAR0 470 * This bit indicates that the Spi4 calendar table encountered a parity 471 * error on bank0 of the calendar table memory. This error bit is 472 * associated with the calendar table on the TX interface - the interface 473 * that drives the Spi databus. The calendar table is used in Spi4 mode 474 * when using the status channel. Parity errors can occur during normal 475 * operation when the calendar table is constantly being read for the port 476 * information, or during initialization time, when the user has access. 477 * This errors will force the the status channel to the reset state and 478 * begin driving training sequences. The status channel will also reset. 479 * Software must follow the init sequence to resynch the interface. This 480 * includes toggling INF_EN which will cancel all outstanding accumulated 481 * credits. 482 * 483 * * CALPAR1 484 * Identical to CALPAR0 except that it indicates that the error occured 485 * on bank1 (instead of bank0). 486 * 487 * * OVRBST 488 * STX can track upto a 512KB data burst. Any packet larger than that is 489 * illegal and will cause confusion in the STX state machine. BMI is 490 * responsible for throwing away these out of control packets from the 491 * input and the Execs should never generate them on the output. This is 492 * a fatal error and should have STX_INT_SYNC[OVRBST] set. 493 * 494 * * DATOVR 495 * FIFO where the Spi4 data ramps upto its transmit frequency has 496 * overflowed. This is a fatal error and should have 497 * STX_INT_SYNC[DATOVR] set. 498 * 499 * * DIPERR 500 * This bit will fire if any DIP2 error is caught by the Spi4 status 501 * channel. 502 * 503 * * NOSYNC 504 * This bit indicates that the number of consecutive DIP2 errors exceeds 505 * STX_DIP_CNT[MAXDIP] and that the interface should be taken down. The 506 * datapath will be notified and send continuous training sequences until 507 * software resynchronizes the interface. This error condition should 508 * have STX_INT_SYNC[NOSYNC] set. 509 * 510 * * UNXFRM 511 * Unexpected framing data was seen on the status channel. 512 * 513 * * FRMERR 514 * This bit indicates that the number of consecutive unexpected framing 515 * sequences STX_DIP_CNT[MAXFRM] and that the interface should be taken 516 * down. The datapath will be notified and send continuous training 517 * sequences until software resynchronizes the interface. This error 518 * condition should have STX_INT_SYNC[FRMERR] set. 519 * 520 * * SYNCERR 521 * Indicates that an exception marked in STX_INT_SYNC has occured and the 522 * TX datapath is disabled. It is recommended that the OVRBST, DATOVR, 523 * NOSYNC, and FRMERR error conditions all have their bits set in the 524 * STX_INT_SYNC register. 525 */ 526union cvmx_stxx_int_reg { 527 uint64_t u64; 528 struct cvmx_stxx_int_reg_s { 529#ifdef __BIG_ENDIAN_BITFIELD 530 uint64_t reserved_9_63 : 55; 531 uint64_t syncerr : 1; /**< Interface encountered a fatal error */ 532 uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */ 533 uint64_t unxfrm : 1; /**< Unexpected framing sequence */ 534 uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */ 535 uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */ 536 uint64_t datovr : 1; /**< Spi4 FIFO overflow error */ 537 uint64_t ovrbst : 1; /**< Transmit packet burst too big */ 538 uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */ 539 uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */ 540#else 541 uint64_t calpar0 : 1; 542 uint64_t calpar1 : 1; 543 uint64_t ovrbst : 1; 544 uint64_t datovr : 1; 545 uint64_t diperr : 1; 546 uint64_t nosync : 1; 547 uint64_t unxfrm : 1; 548 uint64_t frmerr : 1; 549 uint64_t syncerr : 1; 550 uint64_t reserved_9_63 : 55; 551#endif 552 } s; 553 struct cvmx_stxx_int_reg_s cn38xx; 554 struct cvmx_stxx_int_reg_s cn38xxp2; 555 struct cvmx_stxx_int_reg_s cn58xx; 556 struct cvmx_stxx_int_reg_s cn58xxp1; 557}; 558typedef union cvmx_stxx_int_reg cvmx_stxx_int_reg_t; 559 560/** 561 * cvmx_stx#_int_sync 562 * 563 * Notes: 564 * If the bit is enabled, then the coresponding exception condition is flagged 565 * to be fatal. In Spi4 mode, the exception condition will result in a loss 566 * of sync condition on the Spi4 interface and the datapath will send 567 * continuous traing sequences. 568 * 569 * It is recommended that software set the OVRBST, DATOVR, NOSYNC, and 570 * FRMERR errors as synchronization events. Software is free to 571 * synchronize the bus on other conditions, but this is the minimum 572 * recommended set. 573 */ 574union cvmx_stxx_int_sync { 575 uint64_t u64; 576 struct cvmx_stxx_int_sync_s { 577#ifdef __BIG_ENDIAN_BITFIELD 578 uint64_t reserved_8_63 : 56; 579 uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */ 580 uint64_t unxfrm : 1; /**< Unexpected framing sequence */ 581 uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */ 582 uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */ 583 uint64_t datovr : 1; /**< Spi4 FIFO overflow error */ 584 uint64_t ovrbst : 1; /**< Transmit packet burst too big */ 585 uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */ 586 uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */ 587#else 588 uint64_t calpar0 : 1; 589 uint64_t calpar1 : 1; 590 uint64_t ovrbst : 1; 591 uint64_t datovr : 1; 592 uint64_t diperr : 1; 593 uint64_t nosync : 1; 594 uint64_t unxfrm : 1; 595 uint64_t frmerr : 1; 596 uint64_t reserved_8_63 : 56; 597#endif 598 } s; 599 struct cvmx_stxx_int_sync_s cn38xx; 600 struct cvmx_stxx_int_sync_s cn38xxp2; 601 struct cvmx_stxx_int_sync_s cn58xx; 602 struct cvmx_stxx_int_sync_s cn58xxp1; 603}; 604typedef union cvmx_stxx_int_sync cvmx_stxx_int_sync_t; 605 606/** 607 * cvmx_stx#_min_bst 608 * 609 * STX_MIN_BST - Min Burst to enforce when inserting training sequence 610 * 611 */ 612union cvmx_stxx_min_bst { 613 uint64_t u64; 614 struct cvmx_stxx_min_bst_s { 615#ifdef __BIG_ENDIAN_BITFIELD 616 uint64_t reserved_9_63 : 55; 617 uint64_t minb : 9; /**< When STX_ARB_CTL[MINTRN] is set, MINB indicates 618 the number of 8B blocks to send before inserting 619 a training sequence. Normally MINB will be set 620 to GMX_TX_SPI_THRESH[THRESH]. MINB should always 621 be set to an even number (ie. multiple of 16B) */ 622#else 623 uint64_t minb : 9; 624 uint64_t reserved_9_63 : 55; 625#endif 626 } s; 627 struct cvmx_stxx_min_bst_s cn38xx; 628 struct cvmx_stxx_min_bst_s cn38xxp2; 629 struct cvmx_stxx_min_bst_s cn58xx; 630 struct cvmx_stxx_min_bst_s cn58xxp1; 631}; 632typedef union cvmx_stxx_min_bst cvmx_stxx_min_bst_t; 633 634/** 635 * cvmx_stx#_spi4_cal# 636 * 637 * specify the RSL base addresses for the block 638 * STX_SPI4_CAL - Spi4 Calender table 639 * direct_calendar_write / direct_calendar_read 640 * 641 * Notes: 642 * There are 32 calendar table CSR's, each containing 4 entries for a 643 * total of 128 entries. In the above definition... 644 * 645 * n = calendar table offset * 4 646 * 647 * Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3 648 * (with n == 0). Offset 0x10 is the 16th entry in the calendar table 649 * and would contain entries (16*4) = 64, 65, 66, and 67. 650 * 651 * Restrictions: 652 * Calendar table entry accesses (read or write) can only occur 653 * if the interface is disabled. All other accesses will be 654 * unpredictable. 655 * 656 * Both the calendar table and the LEN and M parameters must be 657 * completely setup before writing the Interface enable (INF_EN) and 658 * Status channel enabled (ST_EN) asserted. 659 */ 660union cvmx_stxx_spi4_calx { 661 uint64_t u64; 662 struct cvmx_stxx_spi4_calx_s { 663#ifdef __BIG_ENDIAN_BITFIELD 664 uint64_t reserved_17_63 : 47; 665 uint64_t oddpar : 1; /**< Odd parity over STX_SPI4_CAL[15:0] 666 (^STX_SPI4_CAL[16:0] === 1'b1) | $NS NS */ 667 uint64_t prt3 : 4; /**< Status for port n+3 */ 668 uint64_t prt2 : 4; /**< Status for port n+2 */ 669 uint64_t prt1 : 4; /**< Status for port n+1 */ 670 uint64_t prt0 : 4; /**< Status for port n+0 */ 671#else 672 uint64_t prt0 : 4; 673 uint64_t prt1 : 4; 674 uint64_t prt2 : 4; 675 uint64_t prt3 : 4; 676 uint64_t oddpar : 1; 677 uint64_t reserved_17_63 : 47; 678#endif 679 } s; 680 struct cvmx_stxx_spi4_calx_s cn38xx; 681 struct cvmx_stxx_spi4_calx_s cn38xxp2; 682 struct cvmx_stxx_spi4_calx_s cn58xx; 683 struct cvmx_stxx_spi4_calx_s cn58xxp1; 684}; 685typedef union cvmx_stxx_spi4_calx cvmx_stxx_spi4_calx_t; 686 687/** 688 * cvmx_stx#_spi4_dat 689 * 690 * STX_SPI4_DAT - Spi4 datapath channel control register 691 * 692 * 693 * Notes: 694 * Restrictions: 695 * * DATA_MAX_T must be in MOD 4 cycles 696 * 697 * * DATA_MAX_T must at least 0x20 698 * 699 * * DATA_MAX_T == 0 or ALPHA == 0 will disable the training sequnce 700 * 701 * * If STX_ARB_CTL[MINTRN] is set, then training cycles will stall 702 * waiting for min bursts to complete. In the worst case, this will 703 * add the entire min burst transmission time to the interval between 704 * trainging sequence. The observed MAX_T on the Spi4 bus will be... 705 * 706 * STX_SPI4_DAT[MAX_T] + (STX_MIN_BST[MINB] * 4) 707 * 708 * If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t 709 * parameter will have to be adjusted. Please see the 710 * STX_SPI4_DAT[MAX_T] section for additional information. In 711 * addition, the min_burst can only be guaranteed on the initial data 712 * burst of a given packet (i.e. the first data burst which contains 713 * the SOP tick). All subsequent bursts could be truncated by training 714 * sequences at any point during transmission and could be arbitrarily 715 * small. This mode is only for use in Spi4 mode. 716 */ 717union cvmx_stxx_spi4_dat { 718 uint64_t u64; 719 struct cvmx_stxx_spi4_dat_s { 720#ifdef __BIG_ENDIAN_BITFIELD 721 uint64_t reserved_32_63 : 32; 722 uint64_t alpha : 16; /**< alpha (from spi4.2 spec) */ 723 uint64_t max_t : 16; /**< DATA_MAX_T (from spi4.2 spec) */ 724#else 725 uint64_t max_t : 16; 726 uint64_t alpha : 16; 727 uint64_t reserved_32_63 : 32; 728#endif 729 } s; 730 struct cvmx_stxx_spi4_dat_s cn38xx; 731 struct cvmx_stxx_spi4_dat_s cn38xxp2; 732 struct cvmx_stxx_spi4_dat_s cn58xx; 733 struct cvmx_stxx_spi4_dat_s cn58xxp1; 734}; 735typedef union cvmx_stxx_spi4_dat cvmx_stxx_spi4_dat_t; 736 737/** 738 * cvmx_stx#_spi4_stat 739 * 740 * STX_SPI4_STAT - Spi4 status channel control register 741 * 742 * 743 * Notes: 744 * Restrictions: 745 * Both the calendar table and the LEN and M parameters must be 746 * completely setup before writing the Interface enable (INF_EN) and 747 * Status channel enabled (ST_EN) asserted. 748 * 749 * The calendar table will only be enabled when LEN > 0. 750 * 751 * Current rev will only support LVTTL status IO. 752 */ 753union cvmx_stxx_spi4_stat { 754 uint64_t u64; 755 struct cvmx_stxx_spi4_stat_s { 756#ifdef __BIG_ENDIAN_BITFIELD 757 uint64_t reserved_16_63 : 48; 758 uint64_t m : 8; /**< CALENDAR_M (from spi4.2 spec) */ 759 uint64_t reserved_7_7 : 1; 760 uint64_t len : 7; /**< CALENDAR_LEN (from spi4.2 spec) */ 761#else 762 uint64_t len : 7; 763 uint64_t reserved_7_7 : 1; 764 uint64_t m : 8; 765 uint64_t reserved_16_63 : 48; 766#endif 767 } s; 768 struct cvmx_stxx_spi4_stat_s cn38xx; 769 struct cvmx_stxx_spi4_stat_s cn38xxp2; 770 struct cvmx_stxx_spi4_stat_s cn58xx; 771 struct cvmx_stxx_spi4_stat_s cn58xxp1; 772}; 773typedef union cvmx_stxx_spi4_stat cvmx_stxx_spi4_stat_t; 774 775/** 776 * cvmx_stx#_stat_bytes_hi 777 */ 778union cvmx_stxx_stat_bytes_hi { 779 uint64_t u64; 780 struct cvmx_stxx_stat_bytes_hi_s { 781#ifdef __BIG_ENDIAN_BITFIELD 782 uint64_t reserved_32_63 : 32; 783 uint64_t cnt : 32; /**< Number of bytes sent (CNT[63:32]) */ 784#else 785 uint64_t cnt : 32; 786 uint64_t reserved_32_63 : 32; 787#endif 788 } s; 789 struct cvmx_stxx_stat_bytes_hi_s cn38xx; 790 struct cvmx_stxx_stat_bytes_hi_s cn38xxp2; 791 struct cvmx_stxx_stat_bytes_hi_s cn58xx; 792 struct cvmx_stxx_stat_bytes_hi_s cn58xxp1; 793}; 794typedef union cvmx_stxx_stat_bytes_hi cvmx_stxx_stat_bytes_hi_t; 795 796/** 797 * cvmx_stx#_stat_bytes_lo 798 */ 799union cvmx_stxx_stat_bytes_lo { 800 uint64_t u64; 801 struct cvmx_stxx_stat_bytes_lo_s { 802#ifdef __BIG_ENDIAN_BITFIELD 803 uint64_t reserved_32_63 : 32; 804 uint64_t cnt : 32; /**< Number of bytes sent (CNT[31:0]) */ 805#else 806 uint64_t cnt : 32; 807 uint64_t reserved_32_63 : 32; 808#endif 809 } s; 810 struct cvmx_stxx_stat_bytes_lo_s cn38xx; 811 struct cvmx_stxx_stat_bytes_lo_s cn38xxp2; 812 struct cvmx_stxx_stat_bytes_lo_s cn58xx; 813 struct cvmx_stxx_stat_bytes_lo_s cn58xxp1; 814}; 815typedef union cvmx_stxx_stat_bytes_lo cvmx_stxx_stat_bytes_lo_t; 816 817/** 818 * cvmx_stx#_stat_ctl 819 */ 820union cvmx_stxx_stat_ctl { 821 uint64_t u64; 822 struct cvmx_stxx_stat_ctl_s { 823#ifdef __BIG_ENDIAN_BITFIELD 824 uint64_t reserved_5_63 : 59; 825 uint64_t clr : 1; /**< Clear all statistics counters 826 - STX_STAT_PKT_XMT 827 - STX_STAT_BYTES_HI 828 - STX_STAT_BYTES_LO */ 829 uint64_t bckprs : 4; /**< The selected port for STX_BCKPRS_CNT */ 830#else 831 uint64_t bckprs : 4; 832 uint64_t clr : 1; 833 uint64_t reserved_5_63 : 59; 834#endif 835 } s; 836 struct cvmx_stxx_stat_ctl_s cn38xx; 837 struct cvmx_stxx_stat_ctl_s cn38xxp2; 838 struct cvmx_stxx_stat_ctl_s cn58xx; 839 struct cvmx_stxx_stat_ctl_s cn58xxp1; 840}; 841typedef union cvmx_stxx_stat_ctl cvmx_stxx_stat_ctl_t; 842 843/** 844 * cvmx_stx#_stat_pkt_xmt 845 */ 846union cvmx_stxx_stat_pkt_xmt { 847 uint64_t u64; 848 struct cvmx_stxx_stat_pkt_xmt_s { 849#ifdef __BIG_ENDIAN_BITFIELD 850 uint64_t reserved_32_63 : 32; 851 uint64_t cnt : 32; /**< Number of packets sent */ 852#else 853 uint64_t cnt : 32; 854 uint64_t reserved_32_63 : 32; 855#endif 856 } s; 857 struct cvmx_stxx_stat_pkt_xmt_s cn38xx; 858 struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2; 859 struct cvmx_stxx_stat_pkt_xmt_s cn58xx; 860 struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1; 861}; 862typedef union cvmx_stxx_stat_pkt_xmt cvmx_stxx_stat_pkt_xmt_t; 863 864#endif 865