1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-sriox-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon sriox. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_SRIOX_DEFS_H__ 53232812Sjmallett#define __CVMX_SRIOX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_SRIOX_ACC_CTRL(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 60232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 61215976Sjmallett cvmx_warn("CVMX_SRIOX_ACC_CTRL(%lu) is invalid on this chip\n", block_id); 62232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull; 63215976Sjmallett} 64215976Sjmallett#else 65232812Sjmallett#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull) 66215976Sjmallett#endif 67215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68215976Sjmallettstatic inline uint64_t CVMX_SRIOX_ASMBLY_ID(unsigned long block_id) 69215976Sjmallett{ 70215976Sjmallett if (!( 71232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 72232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 73215976Sjmallett cvmx_warn("CVMX_SRIOX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id); 74232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull; 75215976Sjmallett} 76215976Sjmallett#else 77232812Sjmallett#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull) 78215976Sjmallett#endif 79215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80215976Sjmallettstatic inline uint64_t CVMX_SRIOX_ASMBLY_INFO(unsigned long block_id) 81215976Sjmallett{ 82215976Sjmallett if (!( 83232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 84232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 85215976Sjmallett cvmx_warn("CVMX_SRIOX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id); 86232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull; 87215976Sjmallett} 88215976Sjmallett#else 89232812Sjmallett#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull) 90215976Sjmallett#endif 91215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 92215976Sjmallettstatic inline uint64_t CVMX_SRIOX_BELL_RESP_CTRL(unsigned long block_id) 93215976Sjmallett{ 94215976Sjmallett if (!( 95232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 96232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 97215976Sjmallett cvmx_warn("CVMX_SRIOX_BELL_RESP_CTRL(%lu) is invalid on this chip\n", block_id); 98232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull; 99215976Sjmallett} 100215976Sjmallett#else 101232812Sjmallett#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull) 102215976Sjmallett#endif 103215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104215976Sjmallettstatic inline uint64_t CVMX_SRIOX_BIST_STATUS(unsigned long block_id) 105215976Sjmallett{ 106215976Sjmallett if (!( 107232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 108232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 109215976Sjmallett cvmx_warn("CVMX_SRIOX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 110232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull; 111215976Sjmallett} 112215976Sjmallett#else 113232812Sjmallett#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_SRIOX_IMSG_CTRL(unsigned long block_id) 117215976Sjmallett{ 118215976Sjmallett if (!( 119232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 120232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 121215976Sjmallett cvmx_warn("CVMX_SRIOX_IMSG_CTRL(%lu) is invalid on this chip\n", block_id); 122232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull; 123215976Sjmallett} 124215976Sjmallett#else 125232812Sjmallett#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull) 126215976Sjmallett#endif 127215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 128215976Sjmallettstatic inline uint64_t CVMX_SRIOX_IMSG_INST_HDRX(unsigned long offset, unsigned long block_id) 129215976Sjmallett{ 130215976Sjmallett if (!( 131232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) || 132232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) 133215976Sjmallett cvmx_warn("CVMX_SRIOX_IMSG_INST_HDRX(%lu,%lu) is invalid on this chip\n", offset, block_id); 134232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8; 135215976Sjmallett} 136215976Sjmallett#else 137232812Sjmallett#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8) 138215976Sjmallett#endif 139215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 140215976Sjmallettstatic inline uint64_t CVMX_SRIOX_IMSG_QOS_GRPX(unsigned long offset, unsigned long block_id) 141215976Sjmallett{ 142215976Sjmallett if (!( 143232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 31)) && ((block_id <= 1)))) || 144232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 31)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) 145215976Sjmallett cvmx_warn("CVMX_SRIOX_IMSG_QOS_GRPX(%lu,%lu) is invalid on this chip\n", offset, block_id); 146232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8; 147215976Sjmallett} 148215976Sjmallett#else 149232812Sjmallett#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8) 150215976Sjmallett#endif 151215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 152215976Sjmallettstatic inline uint64_t CVMX_SRIOX_IMSG_STATUSX(unsigned long offset, unsigned long block_id) 153215976Sjmallett{ 154215976Sjmallett if (!( 155232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 23)) && ((block_id <= 1)))) || 156232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 23)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) 157215976Sjmallett cvmx_warn("CVMX_SRIOX_IMSG_STATUSX(%lu,%lu) is invalid on this chip\n", offset, block_id); 158232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8; 159215976Sjmallett} 160215976Sjmallett#else 161232812Sjmallett#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8) 162215976Sjmallett#endif 163215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 164215976Sjmallettstatic inline uint64_t CVMX_SRIOX_IMSG_VPORT_THR(unsigned long block_id) 165215976Sjmallett{ 166215976Sjmallett if (!( 167232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 168232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 169215976Sjmallett cvmx_warn("CVMX_SRIOX_IMSG_VPORT_THR(%lu) is invalid on this chip\n", block_id); 170232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull; 171215976Sjmallett} 172215976Sjmallett#else 173232812Sjmallett#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull) 174215976Sjmallett#endif 175215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176232812Sjmallettstatic inline uint64_t CVMX_SRIOX_IMSG_VPORT_THR2(unsigned long block_id) 177232812Sjmallett{ 178232812Sjmallett if (!( 179232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 180232812Sjmallett cvmx_warn("CVMX_SRIOX_IMSG_VPORT_THR2(%lu) is invalid on this chip\n", block_id); 181232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull; 182232812Sjmallett} 183232812Sjmallett#else 184232812Sjmallett#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull) 185232812Sjmallett#endif 186232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 187215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT2_ENABLE(unsigned long block_id) 188215976Sjmallett{ 189215976Sjmallett if (!( 190232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 191232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 192215976Sjmallett cvmx_warn("CVMX_SRIOX_INT2_ENABLE(%lu) is invalid on this chip\n", block_id); 193232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull; 194215976Sjmallett} 195215976Sjmallett#else 196232812Sjmallett#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull) 197215976Sjmallett#endif 198215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT2_REG(unsigned long block_id) 200215976Sjmallett{ 201215976Sjmallett if (!( 202232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 203232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 204215976Sjmallett cvmx_warn("CVMX_SRIOX_INT2_REG(%lu) is invalid on this chip\n", block_id); 205232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull; 206215976Sjmallett} 207215976Sjmallett#else 208232812Sjmallett#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull) 209215976Sjmallett#endif 210215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 211215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT_ENABLE(unsigned long block_id) 212215976Sjmallett{ 213215976Sjmallett if (!( 214232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 215232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 216215976Sjmallett cvmx_warn("CVMX_SRIOX_INT_ENABLE(%lu) is invalid on this chip\n", block_id); 217232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull; 218215976Sjmallett} 219215976Sjmallett#else 220232812Sjmallett#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull) 221215976Sjmallett#endif 222215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 223215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT_INFO0(unsigned long block_id) 224215976Sjmallett{ 225215976Sjmallett if (!( 226232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 227232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 228215976Sjmallett cvmx_warn("CVMX_SRIOX_INT_INFO0(%lu) is invalid on this chip\n", block_id); 229232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull; 230215976Sjmallett} 231215976Sjmallett#else 232232812Sjmallett#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull) 233215976Sjmallett#endif 234215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 235215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT_INFO1(unsigned long block_id) 236215976Sjmallett{ 237215976Sjmallett if (!( 238232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 239232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 240215976Sjmallett cvmx_warn("CVMX_SRIOX_INT_INFO1(%lu) is invalid on this chip\n", block_id); 241232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull; 242215976Sjmallett} 243215976Sjmallett#else 244232812Sjmallett#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull) 245215976Sjmallett#endif 246215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 247215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT_INFO2(unsigned long block_id) 248215976Sjmallett{ 249215976Sjmallett if (!( 250232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 251232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 252215976Sjmallett cvmx_warn("CVMX_SRIOX_INT_INFO2(%lu) is invalid on this chip\n", block_id); 253232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull; 254215976Sjmallett} 255215976Sjmallett#else 256232812Sjmallett#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull) 257215976Sjmallett#endif 258215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 259215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT_INFO3(unsigned long block_id) 260215976Sjmallett{ 261215976Sjmallett if (!( 262232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 263232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 264215976Sjmallett cvmx_warn("CVMX_SRIOX_INT_INFO3(%lu) is invalid on this chip\n", block_id); 265232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull; 266215976Sjmallett} 267215976Sjmallett#else 268232812Sjmallett#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull) 269215976Sjmallett#endif 270215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 271215976Sjmallettstatic inline uint64_t CVMX_SRIOX_INT_REG(unsigned long block_id) 272215976Sjmallett{ 273215976Sjmallett if (!( 274232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 275232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 276215976Sjmallett cvmx_warn("CVMX_SRIOX_INT_REG(%lu) is invalid on this chip\n", block_id); 277232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull; 278215976Sjmallett} 279215976Sjmallett#else 280232812Sjmallett#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull) 281215976Sjmallett#endif 282215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 283215976Sjmallettstatic inline uint64_t CVMX_SRIOX_IP_FEATURE(unsigned long block_id) 284215976Sjmallett{ 285215976Sjmallett if (!( 286232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 287232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 288215976Sjmallett cvmx_warn("CVMX_SRIOX_IP_FEATURE(%lu) is invalid on this chip\n", block_id); 289232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull; 290215976Sjmallett} 291215976Sjmallett#else 292232812Sjmallett#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull) 293215976Sjmallett#endif 294215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 295215976Sjmallettstatic inline uint64_t CVMX_SRIOX_MAC_BUFFERS(unsigned long block_id) 296215976Sjmallett{ 297215976Sjmallett if (!( 298232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 299232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 300215976Sjmallett cvmx_warn("CVMX_SRIOX_MAC_BUFFERS(%lu) is invalid on this chip\n", block_id); 301232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull; 302215976Sjmallett} 303215976Sjmallett#else 304232812Sjmallett#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull) 305215976Sjmallett#endif 306215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 307215976Sjmallettstatic inline uint64_t CVMX_SRIOX_MAINT_OP(unsigned long block_id) 308215976Sjmallett{ 309215976Sjmallett if (!( 310232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 311232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 312215976Sjmallett cvmx_warn("CVMX_SRIOX_MAINT_OP(%lu) is invalid on this chip\n", block_id); 313232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull; 314215976Sjmallett} 315215976Sjmallett#else 316232812Sjmallett#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull) 317215976Sjmallett#endif 318215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 319215976Sjmallettstatic inline uint64_t CVMX_SRIOX_MAINT_RD_DATA(unsigned long block_id) 320215976Sjmallett{ 321215976Sjmallett if (!( 322232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 323232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 324215976Sjmallett cvmx_warn("CVMX_SRIOX_MAINT_RD_DATA(%lu) is invalid on this chip\n", block_id); 325232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull; 326215976Sjmallett} 327215976Sjmallett#else 328232812Sjmallett#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull) 329215976Sjmallett#endif 330215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331215976Sjmallettstatic inline uint64_t CVMX_SRIOX_MCE_TX_CTL(unsigned long block_id) 332215976Sjmallett{ 333215976Sjmallett if (!( 334232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 335232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 336215976Sjmallett cvmx_warn("CVMX_SRIOX_MCE_TX_CTL(%lu) is invalid on this chip\n", block_id); 337232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull; 338215976Sjmallett} 339215976Sjmallett#else 340232812Sjmallett#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull) 341215976Sjmallett#endif 342215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 343215976Sjmallettstatic inline uint64_t CVMX_SRIOX_MEM_OP_CTRL(unsigned long block_id) 344215976Sjmallett{ 345215976Sjmallett if (!( 346232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 347232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 348215976Sjmallett cvmx_warn("CVMX_SRIOX_MEM_OP_CTRL(%lu) is invalid on this chip\n", block_id); 349232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull; 350215976Sjmallett} 351215976Sjmallett#else 352232812Sjmallett#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull) 353215976Sjmallett#endif 354215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 355215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_CTRLX(unsigned long offset, unsigned long block_id) 356215976Sjmallett{ 357215976Sjmallett if (!( 358232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) || 359232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) 360215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_CTRLX(%lu,%lu) is invalid on this chip\n", offset, block_id); 361232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64; 362215976Sjmallett} 363215976Sjmallett#else 364232812Sjmallett#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 365215976Sjmallett#endif 366215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 367215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_DONE_COUNTSX(unsigned long offset, unsigned long block_id) 368215976Sjmallett{ 369215976Sjmallett if (!( 370232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) || 371232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) 372215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_DONE_COUNTSX(%lu,%lu) is invalid on this chip\n", offset, block_id); 373232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64; 374215976Sjmallett} 375215976Sjmallett#else 376232812Sjmallett#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 377215976Sjmallett#endif 378215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 379215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_FMP_MRX(unsigned long offset, unsigned long block_id) 380215976Sjmallett{ 381215976Sjmallett if (!( 382232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) || 383232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) 384215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_FMP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id); 385232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64; 386215976Sjmallett} 387215976Sjmallett#else 388232812Sjmallett#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 389215976Sjmallett#endif 390215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 391215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_NMP_MRX(unsigned long offset, unsigned long block_id) 392215976Sjmallett{ 393215976Sjmallett if (!( 394232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) || 395232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) 396215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_NMP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id); 397232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64; 398215976Sjmallett} 399215976Sjmallett#else 400232812Sjmallett#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 401215976Sjmallett#endif 402215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 403215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_PORTX(unsigned long offset, unsigned long block_id) 404215976Sjmallett{ 405215976Sjmallett if (!( 406232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) || 407232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) 408215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_PORTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 409232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64; 410215976Sjmallett} 411215976Sjmallett#else 412232812Sjmallett#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 413215976Sjmallett#endif 414215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 415215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_SILO_THR(unsigned long block_id) 416215976Sjmallett{ 417215976Sjmallett if (!( 418232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 419232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 420215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_SILO_THR(%lu) is invalid on this chip\n", block_id); 421232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull; 422215976Sjmallett} 423215976Sjmallett#else 424232812Sjmallett#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull) 425215976Sjmallett#endif 426215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 427215976Sjmallettstatic inline uint64_t CVMX_SRIOX_OMSG_SP_MRX(unsigned long offset, unsigned long block_id) 428215976Sjmallett{ 429215976Sjmallett if (!( 430232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) || 431232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) 432215976Sjmallett cvmx_warn("CVMX_SRIOX_OMSG_SP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id); 433232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64; 434215976Sjmallett} 435215976Sjmallett#else 436232812Sjmallett#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 437215976Sjmallett#endif 438215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 439215976Sjmallettstatic inline uint64_t CVMX_SRIOX_PRIOX_IN_USE(unsigned long offset, unsigned long block_id) 440215976Sjmallett{ 441215976Sjmallett if (!( 442232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) || 443232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) 444215976Sjmallett cvmx_warn("CVMX_SRIOX_PRIOX_IN_USE(%lu,%lu) is invalid on this chip\n", offset, block_id); 445232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8; 446215976Sjmallett} 447215976Sjmallett#else 448232812Sjmallett#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) 449215976Sjmallett#endif 450215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 451215976Sjmallettstatic inline uint64_t CVMX_SRIOX_RX_BELL(unsigned long block_id) 452215976Sjmallett{ 453215976Sjmallett if (!( 454232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 455232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 456215976Sjmallett cvmx_warn("CVMX_SRIOX_RX_BELL(%lu) is invalid on this chip\n", block_id); 457232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull; 458215976Sjmallett} 459215976Sjmallett#else 460232812Sjmallett#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull) 461215976Sjmallett#endif 462215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463215976Sjmallettstatic inline uint64_t CVMX_SRIOX_RX_BELL_SEQ(unsigned long block_id) 464215976Sjmallett{ 465215976Sjmallett if (!( 466232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 467232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 468215976Sjmallett cvmx_warn("CVMX_SRIOX_RX_BELL_SEQ(%lu) is invalid on this chip\n", block_id); 469232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull; 470215976Sjmallett} 471215976Sjmallett#else 472232812Sjmallett#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull) 473215976Sjmallett#endif 474215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 475215976Sjmallettstatic inline uint64_t CVMX_SRIOX_RX_STATUS(unsigned long block_id) 476215976Sjmallett{ 477215976Sjmallett if (!( 478232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 479232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 480215976Sjmallett cvmx_warn("CVMX_SRIOX_RX_STATUS(%lu) is invalid on this chip\n", block_id); 481232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull; 482215976Sjmallett} 483215976Sjmallett#else 484232812Sjmallett#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull) 485215976Sjmallett#endif 486215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 487215976Sjmallettstatic inline uint64_t CVMX_SRIOX_S2M_TYPEX(unsigned long offset, unsigned long block_id) 488215976Sjmallett{ 489215976Sjmallett if (!( 490232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))) || 491232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 15)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) 492215976Sjmallett cvmx_warn("CVMX_SRIOX_S2M_TYPEX(%lu,%lu) is invalid on this chip\n", offset, block_id); 493232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8; 494215976Sjmallett} 495215976Sjmallett#else 496232812Sjmallett#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8) 497215976Sjmallett#endif 498215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 499215976Sjmallettstatic inline uint64_t CVMX_SRIOX_SEQ(unsigned long block_id) 500215976Sjmallett{ 501215976Sjmallett if (!( 502232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 503232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 504215976Sjmallett cvmx_warn("CVMX_SRIOX_SEQ(%lu) is invalid on this chip\n", block_id); 505232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull; 506215976Sjmallett} 507215976Sjmallett#else 508232812Sjmallett#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull) 509215976Sjmallett#endif 510215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 511215976Sjmallettstatic inline uint64_t CVMX_SRIOX_STATUS_REG(unsigned long block_id) 512215976Sjmallett{ 513215976Sjmallett if (!( 514232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 515232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 516215976Sjmallett cvmx_warn("CVMX_SRIOX_STATUS_REG(%lu) is invalid on this chip\n", block_id); 517232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull; 518215976Sjmallett} 519215976Sjmallett#else 520232812Sjmallett#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull) 521215976Sjmallett#endif 522215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 523215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TAG_CTRL(unsigned long block_id) 524215976Sjmallett{ 525215976Sjmallett if (!( 526232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 527232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 528215976Sjmallett cvmx_warn("CVMX_SRIOX_TAG_CTRL(%lu) is invalid on this chip\n", block_id); 529232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull; 530215976Sjmallett} 531215976Sjmallett#else 532232812Sjmallett#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull) 533215976Sjmallett#endif 534215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 535215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TLP_CREDITS(unsigned long block_id) 536215976Sjmallett{ 537215976Sjmallett if (!( 538232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 539232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 540215976Sjmallett cvmx_warn("CVMX_SRIOX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id); 541232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull; 542215976Sjmallett} 543215976Sjmallett#else 544232812Sjmallett#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull) 545215976Sjmallett#endif 546215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 547215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TX_BELL(unsigned long block_id) 548215976Sjmallett{ 549215976Sjmallett if (!( 550232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 551232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 552215976Sjmallett cvmx_warn("CVMX_SRIOX_TX_BELL(%lu) is invalid on this chip\n", block_id); 553232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull; 554215976Sjmallett} 555215976Sjmallett#else 556232812Sjmallett#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull) 557215976Sjmallett#endif 558215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 559215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TX_BELL_INFO(unsigned long block_id) 560215976Sjmallett{ 561215976Sjmallett if (!( 562232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 563232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 564215976Sjmallett cvmx_warn("CVMX_SRIOX_TX_BELL_INFO(%lu) is invalid on this chip\n", block_id); 565232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull; 566215976Sjmallett} 567215976Sjmallett#else 568232812Sjmallett#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull) 569215976Sjmallett#endif 570215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 571215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TX_CTRL(unsigned long block_id) 572215976Sjmallett{ 573215976Sjmallett if (!( 574232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 575232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 576215976Sjmallett cvmx_warn("CVMX_SRIOX_TX_CTRL(%lu) is invalid on this chip\n", block_id); 577232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull; 578215976Sjmallett} 579215976Sjmallett#else 580232812Sjmallett#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull) 581215976Sjmallett#endif 582215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 583215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TX_EMPHASIS(unsigned long block_id) 584215976Sjmallett{ 585215976Sjmallett if (!( 586232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 587232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 588215976Sjmallett cvmx_warn("CVMX_SRIOX_TX_EMPHASIS(%lu) is invalid on this chip\n", block_id); 589232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull; 590215976Sjmallett} 591215976Sjmallett#else 592232812Sjmallett#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull) 593215976Sjmallett#endif 594215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 595215976Sjmallettstatic inline uint64_t CVMX_SRIOX_TX_STATUS(unsigned long block_id) 596215976Sjmallett{ 597215976Sjmallett if (!( 598232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 599232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 600215976Sjmallett cvmx_warn("CVMX_SRIOX_TX_STATUS(%lu) is invalid on this chip\n", block_id); 601232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull; 602215976Sjmallett} 603215976Sjmallett#else 604232812Sjmallett#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull) 605215976Sjmallett#endif 606215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 607215976Sjmallettstatic inline uint64_t CVMX_SRIOX_WR_DONE_COUNTS(unsigned long block_id) 608215976Sjmallett{ 609215976Sjmallett if (!( 610232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 611232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 612215976Sjmallett cvmx_warn("CVMX_SRIOX_WR_DONE_COUNTS(%lu) is invalid on this chip\n", block_id); 613232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull; 614215976Sjmallett} 615215976Sjmallett#else 616232812Sjmallett#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull) 617215976Sjmallett#endif 618215976Sjmallett 619215976Sjmallett/** 620215976Sjmallett * cvmx_srio#_acc_ctrl 621215976Sjmallett * 622215976Sjmallett * SRIO_ACC_CTRL = SRIO Access Control 623215976Sjmallett * 624215976Sjmallett * General access control of the incoming BAR registers. 625215976Sjmallett * 626215976Sjmallett * Notes: 627215976Sjmallett * This register controls write access to the BAR registers via SRIO Maintenance Operations. At 628215976Sjmallett * powerup the BAR registers can be accessed via RSL and Maintenance Operations. If the DENY_BAR* 629232812Sjmallett * bits or DENY_ADR* bits are set then Maintenance Writes to the corresponding BAR fields are 630232812Sjmallett * ignored. Setting both the DENY_BAR and DENY_ADR for a corresponding BAR is compatable with the 631232812Sjmallett * operation of the DENY_BAR bit found in 63xx Pass 2 and earlier. This register does not effect 632232812Sjmallett * read operations. Reset values for DENY_BAR[2:0] are typically clear but they are set if 633232812Sjmallett * the chip is operating in Authentik Mode. 634215976Sjmallett * 635232812Sjmallett * Clk_Rst: SRIO(0,2..3)_ACC_CTRL hclk hrst_n 636215976Sjmallett */ 637232812Sjmallettunion cvmx_sriox_acc_ctrl { 638215976Sjmallett uint64_t u64; 639232812Sjmallett struct cvmx_sriox_acc_ctrl_s { 640232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 641232812Sjmallett uint64_t reserved_7_63 : 57; 642232812Sjmallett uint64_t deny_adr2 : 1; /**< Deny SRIO Write Access to SRIO Address Fields in 643232812Sjmallett SRIOMAINT(0,2..3)_BAR2* Registers */ 644232812Sjmallett uint64_t deny_adr1 : 1; /**< Deny SRIO Write Access to SRIO Address Fields in 645232812Sjmallett SRIOMAINT(0,2..3)_BAR1* Registers */ 646232812Sjmallett uint64_t deny_adr0 : 1; /**< Deny SRIO Write Access to SRIO Address Fields in 647232812Sjmallett SRIOMAINT(0,2..3)_BAR0* Registers */ 648232812Sjmallett uint64_t reserved_3_3 : 1; 649232812Sjmallett uint64_t deny_bar2 : 1; /**< Deny SRIO Write Access to non-SRIO Address Fields 650232812Sjmallett in the SRIOMAINT_BAR2 Registers */ 651232812Sjmallett uint64_t deny_bar1 : 1; /**< Deny SRIO Write Access to non-SRIO Address Fields 652232812Sjmallett in the SRIOMAINT_BAR1 Registers */ 653232812Sjmallett uint64_t deny_bar0 : 1; /**< Deny SRIO Write Access to non-SRIO Address Fields 654232812Sjmallett in the SRIOMAINT_BAR0 Registers */ 655232812Sjmallett#else 656232812Sjmallett uint64_t deny_bar0 : 1; 657232812Sjmallett uint64_t deny_bar1 : 1; 658232812Sjmallett uint64_t deny_bar2 : 1; 659232812Sjmallett uint64_t reserved_3_3 : 1; 660232812Sjmallett uint64_t deny_adr0 : 1; 661232812Sjmallett uint64_t deny_adr1 : 1; 662232812Sjmallett uint64_t deny_adr2 : 1; 663232812Sjmallett uint64_t reserved_7_63 : 57; 664232812Sjmallett#endif 665232812Sjmallett } s; 666232812Sjmallett struct cvmx_sriox_acc_ctrl_cn63xx { 667232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 668215976Sjmallett uint64_t reserved_3_63 : 61; 669215976Sjmallett uint64_t deny_bar2 : 1; /**< Deny SRIO Write Access to BAR2 Registers */ 670215976Sjmallett uint64_t deny_bar1 : 1; /**< Deny SRIO Write Access to BAR1 Registers */ 671215976Sjmallett uint64_t deny_bar0 : 1; /**< Deny SRIO Write Access to BAR0 Registers */ 672215976Sjmallett#else 673215976Sjmallett uint64_t deny_bar0 : 1; 674215976Sjmallett uint64_t deny_bar1 : 1; 675215976Sjmallett uint64_t deny_bar2 : 1; 676215976Sjmallett uint64_t reserved_3_63 : 61; 677215976Sjmallett#endif 678232812Sjmallett } cn63xx; 679232812Sjmallett struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1; 680232812Sjmallett struct cvmx_sriox_acc_ctrl_s cn66xx; 681215976Sjmallett}; 682215976Sjmalletttypedef union cvmx_sriox_acc_ctrl cvmx_sriox_acc_ctrl_t; 683215976Sjmallett 684215976Sjmallett/** 685215976Sjmallett * cvmx_srio#_asmbly_id 686215976Sjmallett * 687215976Sjmallett * SRIO_ASMBLY_ID = SRIO Assembly ID 688215976Sjmallett * 689215976Sjmallett * The Assembly ID register controls the Assembly ID and Vendor 690215976Sjmallett * 691215976Sjmallett * Notes: 692232812Sjmallett * This register specifies the Assembly ID and Vendor visible in SRIOMAINT(0,2..3)_ASMBLY_ID register. The 693215976Sjmallett * Assembly Vendor ID is typically supplied by the RapidIO Trade Association. This register is only 694232812Sjmallett * reset during COLD boot and may only be modified while SRIO(0,2..3)_STATUS_REG.ACCESS is zero. 695215976Sjmallett * 696232812Sjmallett * Clk_Rst: SRIO(0,2..3)_ASMBLY_ID sclk srst_cold_n 697215976Sjmallett */ 698232812Sjmallettunion cvmx_sriox_asmbly_id { 699215976Sjmallett uint64_t u64; 700232812Sjmallett struct cvmx_sriox_asmbly_id_s { 701232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 702215976Sjmallett uint64_t reserved_32_63 : 32; 703215976Sjmallett uint64_t assy_id : 16; /**< Assembly Identifer */ 704215976Sjmallett uint64_t assy_ven : 16; /**< Assembly Vendor Identifer */ 705215976Sjmallett#else 706215976Sjmallett uint64_t assy_ven : 16; 707215976Sjmallett uint64_t assy_id : 16; 708215976Sjmallett uint64_t reserved_32_63 : 32; 709215976Sjmallett#endif 710215976Sjmallett } s; 711215976Sjmallett struct cvmx_sriox_asmbly_id_s cn63xx; 712215976Sjmallett struct cvmx_sriox_asmbly_id_s cn63xxp1; 713232812Sjmallett struct cvmx_sriox_asmbly_id_s cn66xx; 714215976Sjmallett}; 715215976Sjmalletttypedef union cvmx_sriox_asmbly_id cvmx_sriox_asmbly_id_t; 716215976Sjmallett 717215976Sjmallett/** 718215976Sjmallett * cvmx_srio#_asmbly_info 719215976Sjmallett * 720215976Sjmallett * SRIO_ASMBLY_INFO = SRIO Assembly Information 721215976Sjmallett * 722215976Sjmallett * The Assembly Info register controls the Assembly Revision 723215976Sjmallett * 724215976Sjmallett * Notes: 725215976Sjmallett * The Assembly Info register controls the Assembly Revision visible in the ASSY_REV field of the 726232812Sjmallett * SRIOMAINT(0,2..3)_ASMBLY_INFO register. This register is only reset during COLD boot and may only be 727232812Sjmallett * modified while SRIO(0,2..3)_STATUS_REG.ACCESS is zero. 728215976Sjmallett * 729232812Sjmallett * Clk_Rst: SRIO(0,2..3)_ASMBLY_INFO sclk srst_cold_n 730215976Sjmallett */ 731232812Sjmallettunion cvmx_sriox_asmbly_info { 732215976Sjmallett uint64_t u64; 733232812Sjmallett struct cvmx_sriox_asmbly_info_s { 734232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 735215976Sjmallett uint64_t reserved_32_63 : 32; 736215976Sjmallett uint64_t assy_rev : 16; /**< Assembly Revision */ 737215976Sjmallett uint64_t reserved_0_15 : 16; 738215976Sjmallett#else 739215976Sjmallett uint64_t reserved_0_15 : 16; 740215976Sjmallett uint64_t assy_rev : 16; 741215976Sjmallett uint64_t reserved_32_63 : 32; 742215976Sjmallett#endif 743215976Sjmallett } s; 744215976Sjmallett struct cvmx_sriox_asmbly_info_s cn63xx; 745215976Sjmallett struct cvmx_sriox_asmbly_info_s cn63xxp1; 746232812Sjmallett struct cvmx_sriox_asmbly_info_s cn66xx; 747215976Sjmallett}; 748215976Sjmalletttypedef union cvmx_sriox_asmbly_info cvmx_sriox_asmbly_info_t; 749215976Sjmallett 750215976Sjmallett/** 751215976Sjmallett * cvmx_srio#_bell_resp_ctrl 752215976Sjmallett * 753215976Sjmallett * SRIO_BELL_RESP_CTRL = SRIO Doorbell Response Control 754215976Sjmallett * 755215976Sjmallett * The SRIO Doorbell Response Control Register 756215976Sjmallett * 757215976Sjmallett * Notes: 758215976Sjmallett * This register is used to override the response priority of the outgoing doorbell responses. 759215976Sjmallett * 760232812Sjmallett * Clk_Rst: SRIO(0,2..3)_BELL_RESP_CTRL hclk hrst_n 761215976Sjmallett */ 762232812Sjmallettunion cvmx_sriox_bell_resp_ctrl { 763215976Sjmallett uint64_t u64; 764232812Sjmallett struct cvmx_sriox_bell_resp_ctrl_s { 765232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 766215976Sjmallett uint64_t reserved_6_63 : 58; 767215976Sjmallett uint64_t rp1_sid : 1; /**< Sets response priority for incomimg doorbells 768215976Sjmallett of priority 1 on the secondary ID (0=2, 1=3) */ 769215976Sjmallett uint64_t rp0_sid : 2; /**< Sets response priority for incomimg doorbells 770215976Sjmallett of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */ 771215976Sjmallett uint64_t rp1_pid : 1; /**< Sets response priority for incomimg doorbells 772215976Sjmallett of priority 1 on the primary ID (0=2, 1=3) */ 773215976Sjmallett uint64_t rp0_pid : 2; /**< Sets response priority for incomimg doorbells 774215976Sjmallett of priority 0 on the primary ID (0,1=1 2=2, 3=3) */ 775215976Sjmallett#else 776215976Sjmallett uint64_t rp0_pid : 2; 777215976Sjmallett uint64_t rp1_pid : 1; 778215976Sjmallett uint64_t rp0_sid : 2; 779215976Sjmallett uint64_t rp1_sid : 1; 780215976Sjmallett uint64_t reserved_6_63 : 58; 781215976Sjmallett#endif 782215976Sjmallett } s; 783215976Sjmallett struct cvmx_sriox_bell_resp_ctrl_s cn63xx; 784215976Sjmallett struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1; 785232812Sjmallett struct cvmx_sriox_bell_resp_ctrl_s cn66xx; 786215976Sjmallett}; 787215976Sjmalletttypedef union cvmx_sriox_bell_resp_ctrl cvmx_sriox_bell_resp_ctrl_t; 788215976Sjmallett 789215976Sjmallett/** 790215976Sjmallett * cvmx_srio#_bist_status 791215976Sjmallett * 792215976Sjmallett * SRIO_BIST_STATUS = SRIO Bist Status 793215976Sjmallett * 794215976Sjmallett * Results from BIST runs of SRIO's memories. 795215976Sjmallett * 796215976Sjmallett * Notes: 797215976Sjmallett * BIST Results. 798215976Sjmallett * 799232812Sjmallett * Clk_Rst: SRIO(0,2..3)_BIST_STATUS hclk hrst_n 800215976Sjmallett */ 801232812Sjmallettunion cvmx_sriox_bist_status { 802215976Sjmallett uint64_t u64; 803232812Sjmallett struct cvmx_sriox_bist_status_s { 804232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 805232812Sjmallett uint64_t reserved_45_63 : 19; 806232812Sjmallett uint64_t lram : 1; /**< Incoming Doorbell Lookup RAM. */ 807232812Sjmallett uint64_t mram : 2; /**< Incoming Message SLI FIFO. */ 808232812Sjmallett uint64_t cram : 2; /**< Incoming Rd/Wr/Response Command FIFO. */ 809232812Sjmallett uint64_t bell : 2; /**< Incoming Doorbell FIFO. */ 810232812Sjmallett uint64_t otag : 2; /**< Outgoing Tag Data. */ 811232812Sjmallett uint64_t itag : 1; /**< Incoming TAG Data. */ 812232812Sjmallett uint64_t ofree : 1; /**< Outgoing Free Pointer RAM (OFIFO) */ 813232812Sjmallett uint64_t rtn : 2; /**< Outgoing Response Return FIFO. */ 814232812Sjmallett uint64_t obulk : 4; /**< Outgoing Bulk Data RAMs (OFIFO) */ 815232812Sjmallett uint64_t optrs : 4; /**< Outgoing Priority Pointer RAMs (OFIFO) */ 816232812Sjmallett uint64_t oarb2 : 2; /**< Additional Outgoing Priority RAMs. */ 817232812Sjmallett uint64_t rxbuf2 : 2; /**< Additional Incoming SRIO MAC Buffers. */ 818232812Sjmallett uint64_t oarb : 2; /**< Outgoing Priority RAMs (OARB) */ 819232812Sjmallett uint64_t ispf : 1; /**< Incoming Soft Packet FIFO */ 820232812Sjmallett uint64_t ospf : 1; /**< Outgoing Soft Packet FIFO */ 821232812Sjmallett uint64_t txbuf : 2; /**< Outgoing SRIO MAC Buffer. */ 822232812Sjmallett uint64_t rxbuf : 2; /**< Incoming SRIO MAC Buffer. */ 823232812Sjmallett uint64_t imsg : 5; /**< Incoming Message RAMs. */ 824232812Sjmallett uint64_t omsg : 7; /**< Outgoing Message RAMs. */ 825232812Sjmallett#else 826232812Sjmallett uint64_t omsg : 7; 827232812Sjmallett uint64_t imsg : 5; 828232812Sjmallett uint64_t rxbuf : 2; 829232812Sjmallett uint64_t txbuf : 2; 830232812Sjmallett uint64_t ospf : 1; 831232812Sjmallett uint64_t ispf : 1; 832232812Sjmallett uint64_t oarb : 2; 833232812Sjmallett uint64_t rxbuf2 : 2; 834232812Sjmallett uint64_t oarb2 : 2; 835232812Sjmallett uint64_t optrs : 4; 836232812Sjmallett uint64_t obulk : 4; 837232812Sjmallett uint64_t rtn : 2; 838232812Sjmallett uint64_t ofree : 1; 839232812Sjmallett uint64_t itag : 1; 840232812Sjmallett uint64_t otag : 2; 841232812Sjmallett uint64_t bell : 2; 842232812Sjmallett uint64_t cram : 2; 843232812Sjmallett uint64_t mram : 2; 844232812Sjmallett uint64_t lram : 1; 845232812Sjmallett uint64_t reserved_45_63 : 19; 846232812Sjmallett#endif 847232812Sjmallett } s; 848232812Sjmallett struct cvmx_sriox_bist_status_cn63xx { 849232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 850215976Sjmallett uint64_t reserved_44_63 : 20; 851215976Sjmallett uint64_t mram : 2; /**< Incoming Message SLI FIFO. */ 852215976Sjmallett uint64_t cram : 2; /**< Incoming Rd/Wr/Response Command FIFO. */ 853215976Sjmallett uint64_t bell : 2; /**< Incoming Doorbell FIFO. */ 854215976Sjmallett uint64_t otag : 2; /**< Outgoing Tag Data. */ 855215976Sjmallett uint64_t itag : 1; /**< Incoming TAG Data. */ 856215976Sjmallett uint64_t ofree : 1; /**< Outgoing Free Pointer RAM (OFIFO) */ 857215976Sjmallett uint64_t rtn : 2; /**< Outgoing Response Return FIFO. */ 858215976Sjmallett uint64_t obulk : 4; /**< Outgoing Bulk Data RAMs (OFIFO) */ 859215976Sjmallett uint64_t optrs : 4; /**< Outgoing Priority Pointer RAMs (OFIFO) */ 860232812Sjmallett uint64_t oarb2 : 2; /**< Additional Outgoing Priority RAMs (Pass 2). */ 861215976Sjmallett uint64_t rxbuf2 : 2; /**< Additional Incoming SRIO MAC Buffers (Pass 2). */ 862215976Sjmallett uint64_t oarb : 2; /**< Outgoing Priority RAMs (OARB) */ 863215976Sjmallett uint64_t ispf : 1; /**< Incoming Soft Packet FIFO */ 864215976Sjmallett uint64_t ospf : 1; /**< Outgoing Soft Packet FIFO */ 865215976Sjmallett uint64_t txbuf : 2; /**< Outgoing SRIO MAC Buffer. */ 866215976Sjmallett uint64_t rxbuf : 2; /**< Incoming SRIO MAC Buffer. */ 867232812Sjmallett uint64_t imsg : 5; /**< Incoming Message RAMs. 868232812Sjmallett IMSG<0> (i.e. <7>) unused in Pass 2 */ 869215976Sjmallett uint64_t omsg : 7; /**< Outgoing Message RAMs. */ 870215976Sjmallett#else 871215976Sjmallett uint64_t omsg : 7; 872215976Sjmallett uint64_t imsg : 5; 873215976Sjmallett uint64_t rxbuf : 2; 874215976Sjmallett uint64_t txbuf : 2; 875215976Sjmallett uint64_t ospf : 1; 876215976Sjmallett uint64_t ispf : 1; 877215976Sjmallett uint64_t oarb : 2; 878215976Sjmallett uint64_t rxbuf2 : 2; 879232812Sjmallett uint64_t oarb2 : 2; 880215976Sjmallett uint64_t optrs : 4; 881215976Sjmallett uint64_t obulk : 4; 882215976Sjmallett uint64_t rtn : 2; 883215976Sjmallett uint64_t ofree : 1; 884215976Sjmallett uint64_t itag : 1; 885215976Sjmallett uint64_t otag : 2; 886215976Sjmallett uint64_t bell : 2; 887215976Sjmallett uint64_t cram : 2; 888215976Sjmallett uint64_t mram : 2; 889215976Sjmallett uint64_t reserved_44_63 : 20; 890215976Sjmallett#endif 891232812Sjmallett } cn63xx; 892232812Sjmallett struct cvmx_sriox_bist_status_cn63xxp1 { 893232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 894215976Sjmallett uint64_t reserved_44_63 : 20; 895215976Sjmallett uint64_t mram : 2; /**< Incoming Message SLI FIFO. */ 896215976Sjmallett uint64_t cram : 2; /**< Incoming Rd/Wr/Response Command FIFO. */ 897215976Sjmallett uint64_t bell : 2; /**< Incoming Doorbell FIFO. */ 898215976Sjmallett uint64_t otag : 2; /**< Outgoing Tag Data. */ 899215976Sjmallett uint64_t itag : 1; /**< Incoming TAG Data. */ 900215976Sjmallett uint64_t ofree : 1; /**< Outgoing Free Pointer RAM (OFIFO) */ 901215976Sjmallett uint64_t rtn : 2; /**< Outgoing Response Return FIFO. */ 902215976Sjmallett uint64_t obulk : 4; /**< Outgoing Bulk Data RAMs (OFIFO) */ 903215976Sjmallett uint64_t optrs : 4; /**< Outgoing Priority Pointer RAMs (OFIFO) */ 904215976Sjmallett uint64_t reserved_20_23 : 4; 905215976Sjmallett uint64_t oarb : 2; /**< Outgoing Priority RAMs (OARB) */ 906215976Sjmallett uint64_t ispf : 1; /**< Incoming Soft Packet FIFO */ 907215976Sjmallett uint64_t ospf : 1; /**< Outgoing Soft Packet FIFO */ 908215976Sjmallett uint64_t txbuf : 2; /**< Outgoing SRIO MAC Buffer. */ 909215976Sjmallett uint64_t rxbuf : 2; /**< Incoming SRIO MAC Buffer. */ 910215976Sjmallett uint64_t imsg : 5; /**< Incoming Message RAMs. */ 911215976Sjmallett uint64_t omsg : 7; /**< Outgoing Message RAMs. */ 912215976Sjmallett#else 913215976Sjmallett uint64_t omsg : 7; 914215976Sjmallett uint64_t imsg : 5; 915215976Sjmallett uint64_t rxbuf : 2; 916215976Sjmallett uint64_t txbuf : 2; 917215976Sjmallett uint64_t ospf : 1; 918215976Sjmallett uint64_t ispf : 1; 919215976Sjmallett uint64_t oarb : 2; 920215976Sjmallett uint64_t reserved_20_23 : 4; 921215976Sjmallett uint64_t optrs : 4; 922215976Sjmallett uint64_t obulk : 4; 923215976Sjmallett uint64_t rtn : 2; 924215976Sjmallett uint64_t ofree : 1; 925215976Sjmallett uint64_t itag : 1; 926215976Sjmallett uint64_t otag : 2; 927215976Sjmallett uint64_t bell : 2; 928215976Sjmallett uint64_t cram : 2; 929215976Sjmallett uint64_t mram : 2; 930215976Sjmallett uint64_t reserved_44_63 : 20; 931215976Sjmallett#endif 932215976Sjmallett } cn63xxp1; 933232812Sjmallett struct cvmx_sriox_bist_status_s cn66xx; 934215976Sjmallett}; 935215976Sjmalletttypedef union cvmx_sriox_bist_status cvmx_sriox_bist_status_t; 936215976Sjmallett 937215976Sjmallett/** 938215976Sjmallett * cvmx_srio#_imsg_ctrl 939215976Sjmallett * 940215976Sjmallett * SRIO_IMSG_CTRL = SRIO Incoming Message Control 941215976Sjmallett * 942215976Sjmallett * The SRIO Incoming Message Control Register 943215976Sjmallett * 944215976Sjmallett * Notes: 945215976Sjmallett * RSP_THR should not typically be modified from reset value. 946215976Sjmallett * 947232812Sjmallett * Clk_Rst: SRIO(0,2..3)_IMSG_CTRL hclk hrst_n 948215976Sjmallett */ 949232812Sjmallettunion cvmx_sriox_imsg_ctrl { 950215976Sjmallett uint64_t u64; 951232812Sjmallett struct cvmx_sriox_imsg_ctrl_s { 952232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 953215976Sjmallett uint64_t reserved_32_63 : 32; 954215976Sjmallett uint64_t to_mode : 1; /**< MP message timeout mode: 955215976Sjmallett - 0: The timeout counter gets reset whenever the 956215976Sjmallett next sequential segment is received, regardless 957215976Sjmallett of whether it is accepted 958215976Sjmallett - 1: The timeout counter gets reset only when the 959215976Sjmallett next sequential segment is received and 960215976Sjmallett accepted */ 961215976Sjmallett uint64_t reserved_30_30 : 1; 962232812Sjmallett uint64_t rsp_thr : 6; /**< Reserved */ 963215976Sjmallett uint64_t reserved_22_23 : 2; 964215976Sjmallett uint64_t rp1_sid : 1; /**< Sets msg response priority for incomimg messages 965215976Sjmallett of priority 1 on the secondary ID (0=2, 1=3) */ 966215976Sjmallett uint64_t rp0_sid : 2; /**< Sets msg response priority for incomimg messages 967215976Sjmallett of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */ 968215976Sjmallett uint64_t rp1_pid : 1; /**< Sets msg response priority for incomimg messages 969215976Sjmallett of priority 1 on the primary ID (0=2, 1=3) */ 970215976Sjmallett uint64_t rp0_pid : 2; /**< Sets msg response priority for incomimg messages 971215976Sjmallett of priority 0 on the primary ID (0,1=1 2=2, 3=3) */ 972215976Sjmallett uint64_t reserved_15_15 : 1; 973215976Sjmallett uint64_t prt_sel : 3; /**< Port/Controller selection method: 974215976Sjmallett - 0: Table lookup based on mailbox 975215976Sjmallett - 1: Table lookup based on priority 976215976Sjmallett - 2: Table lookup based on letter 977215976Sjmallett - 3: Size-based (SP to port 0, MP to port 1) 978215976Sjmallett - 4: ID-based (pri ID to port 0, sec ID to port 1) */ 979215976Sjmallett uint64_t lttr : 4; /**< Port/Controller selection letter table */ 980215976Sjmallett uint64_t prio : 4; /**< Port/Controller selection priority table */ 981215976Sjmallett uint64_t mbox : 4; /**< Port/Controller selection mailbox table */ 982215976Sjmallett#else 983215976Sjmallett uint64_t mbox : 4; 984215976Sjmallett uint64_t prio : 4; 985215976Sjmallett uint64_t lttr : 4; 986215976Sjmallett uint64_t prt_sel : 3; 987215976Sjmallett uint64_t reserved_15_15 : 1; 988215976Sjmallett uint64_t rp0_pid : 2; 989215976Sjmallett uint64_t rp1_pid : 1; 990215976Sjmallett uint64_t rp0_sid : 2; 991215976Sjmallett uint64_t rp1_sid : 1; 992215976Sjmallett uint64_t reserved_22_23 : 2; 993215976Sjmallett uint64_t rsp_thr : 6; 994215976Sjmallett uint64_t reserved_30_30 : 1; 995215976Sjmallett uint64_t to_mode : 1; 996215976Sjmallett uint64_t reserved_32_63 : 32; 997215976Sjmallett#endif 998215976Sjmallett } s; 999215976Sjmallett struct cvmx_sriox_imsg_ctrl_s cn63xx; 1000215976Sjmallett struct cvmx_sriox_imsg_ctrl_s cn63xxp1; 1001232812Sjmallett struct cvmx_sriox_imsg_ctrl_s cn66xx; 1002215976Sjmallett}; 1003215976Sjmalletttypedef union cvmx_sriox_imsg_ctrl cvmx_sriox_imsg_ctrl_t; 1004215976Sjmallett 1005215976Sjmallett/** 1006215976Sjmallett * cvmx_srio#_imsg_inst_hdr# 1007215976Sjmallett * 1008215976Sjmallett * SRIO_IMSG_INST_HDRX = SRIO Incoming Message Packet Instruction Header 1009215976Sjmallett * 1010215976Sjmallett * The SRIO Port/Controller X Incoming Message Packet Instruction Header Register 1011215976Sjmallett * 1012215976Sjmallett * Notes: 1013215976Sjmallett * SRIO HW generates most of the SRIO_WORD1 fields from these values. SRIO_WORD1 is the 2nd of two 1014215976Sjmallett * header words that SRIO inserts in front of all received messages. SRIO_WORD1 may commonly be used 1015215976Sjmallett * as a PIP/IPD PKT_INST_HDR. This CSR matches the PIP/IPD PKT_INST_HDR format except for the QOS 1016215976Sjmallett * and GRP fields. SRIO*_IMSG_QOS_GRP*[QOS*,GRP*] supply the QOS and GRP fields. 1017215976Sjmallett * 1018232812Sjmallett * Clk_Rst: SRIO(0,2..3)_IMSG_INST_HDR[0:1] hclk hrst_n 1019215976Sjmallett */ 1020232812Sjmallettunion cvmx_sriox_imsg_inst_hdrx { 1021215976Sjmallett uint64_t u64; 1022232812Sjmallett struct cvmx_sriox_imsg_inst_hdrx_s { 1023232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1024215976Sjmallett uint64_t r : 1; /**< Port/Controller X R */ 1025215976Sjmallett uint64_t reserved_58_62 : 5; 1026215976Sjmallett uint64_t pm : 2; /**< Port/Controller X PM */ 1027215976Sjmallett uint64_t reserved_55_55 : 1; 1028215976Sjmallett uint64_t sl : 7; /**< Port/Controller X SL */ 1029215976Sjmallett uint64_t reserved_46_47 : 2; 1030215976Sjmallett uint64_t nqos : 1; /**< Port/Controller X NQOS */ 1031215976Sjmallett uint64_t ngrp : 1; /**< Port/Controller X NGRP */ 1032215976Sjmallett uint64_t ntt : 1; /**< Port/Controller X NTT */ 1033215976Sjmallett uint64_t ntag : 1; /**< Port/Controller X NTAG */ 1034215976Sjmallett uint64_t reserved_35_41 : 7; 1035215976Sjmallett uint64_t rs : 1; /**< Port/Controller X RS */ 1036215976Sjmallett uint64_t tt : 2; /**< Port/Controller X TT */ 1037215976Sjmallett uint64_t tag : 32; /**< Port/Controller X TAG */ 1038215976Sjmallett#else 1039215976Sjmallett uint64_t tag : 32; 1040215976Sjmallett uint64_t tt : 2; 1041215976Sjmallett uint64_t rs : 1; 1042215976Sjmallett uint64_t reserved_35_41 : 7; 1043215976Sjmallett uint64_t ntag : 1; 1044215976Sjmallett uint64_t ntt : 1; 1045215976Sjmallett uint64_t ngrp : 1; 1046215976Sjmallett uint64_t nqos : 1; 1047215976Sjmallett uint64_t reserved_46_47 : 2; 1048215976Sjmallett uint64_t sl : 7; 1049215976Sjmallett uint64_t reserved_55_55 : 1; 1050215976Sjmallett uint64_t pm : 2; 1051215976Sjmallett uint64_t reserved_58_62 : 5; 1052215976Sjmallett uint64_t r : 1; 1053215976Sjmallett#endif 1054215976Sjmallett } s; 1055215976Sjmallett struct cvmx_sriox_imsg_inst_hdrx_s cn63xx; 1056215976Sjmallett struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1; 1057232812Sjmallett struct cvmx_sriox_imsg_inst_hdrx_s cn66xx; 1058215976Sjmallett}; 1059215976Sjmalletttypedef union cvmx_sriox_imsg_inst_hdrx cvmx_sriox_imsg_inst_hdrx_t; 1060215976Sjmallett 1061215976Sjmallett/** 1062215976Sjmallett * cvmx_srio#_imsg_qos_grp# 1063215976Sjmallett * 1064215976Sjmallett * SRIO_IMSG_QOS_GRPX = SRIO Incoming Message QOS/GRP Table 1065215976Sjmallett * 1066215976Sjmallett * The SRIO Incoming Message QOS/GRP Table Entry X 1067215976Sjmallett * 1068215976Sjmallett * Notes: 1069232812Sjmallett * The QOS/GRP table contains 32 entries with 8 QOS/GRP pairs per entry - 256 pairs total. HW 1070232812Sjmallett * selects the table entry by the concatenation of SRIO_WORD0[PRIO,DIS,MBOX], thus entry 0 is used 1071232812Sjmallett * for messages with PRIO=0,DIS=0,MBOX=0, entry 1 is for PRIO=0,DIS=0,MBOX=1, etc. HW selects the 1072232812Sjmallett * QOS/GRP pair from the table entry by the concatenation of SRIO_WORD0[ID,LETTER] as shown above. HW 1073232812Sjmallett * then inserts the QOS/GRP pair into SRIO_WORD1[QOS,GRP], which may commonly be used for the PIP/IPD 1074232812Sjmallett * PKT_INST_HDR[QOS,GRP] fields. 1075215976Sjmallett * 1076232812Sjmallett * Clk_Rst: SRIO(0,2..3)_IMSG_QOS_GRP[0:1] hclk hrst_n 1077215976Sjmallett */ 1078232812Sjmallettunion cvmx_sriox_imsg_qos_grpx { 1079215976Sjmallett uint64_t u64; 1080232812Sjmallett struct cvmx_sriox_imsg_qos_grpx_s { 1081232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1082215976Sjmallett uint64_t reserved_63_63 : 1; 1083215976Sjmallett uint64_t qos7 : 3; /**< Entry X:7 QOS (ID=1, LETTER=3) */ 1084215976Sjmallett uint64_t grp7 : 4; /**< Entry X:7 GRP (ID=1, LETTER=3) */ 1085215976Sjmallett uint64_t reserved_55_55 : 1; 1086215976Sjmallett uint64_t qos6 : 3; /**< Entry X:6 QOS (ID=1, LETTER=2) */ 1087215976Sjmallett uint64_t grp6 : 4; /**< Entry X:6 GRP (ID=1, LETTER=2) */ 1088215976Sjmallett uint64_t reserved_47_47 : 1; 1089215976Sjmallett uint64_t qos5 : 3; /**< Entry X:5 QOS (ID=1, LETTER=1) */ 1090215976Sjmallett uint64_t grp5 : 4; /**< Entry X:5 GRP (ID=1, LETTER=1) */ 1091215976Sjmallett uint64_t reserved_39_39 : 1; 1092215976Sjmallett uint64_t qos4 : 3; /**< Entry X:4 QOS (ID=1, LETTER=0) */ 1093215976Sjmallett uint64_t grp4 : 4; /**< Entry X:4 GRP (ID=1, LETTER=0) */ 1094215976Sjmallett uint64_t reserved_31_31 : 1; 1095215976Sjmallett uint64_t qos3 : 3; /**< Entry X:3 QOS (ID=0, LETTER=3) */ 1096215976Sjmallett uint64_t grp3 : 4; /**< Entry X:3 GRP (ID=0, LETTER=3) */ 1097215976Sjmallett uint64_t reserved_23_23 : 1; 1098215976Sjmallett uint64_t qos2 : 3; /**< Entry X:2 QOS (ID=0, LETTER=2) */ 1099215976Sjmallett uint64_t grp2 : 4; /**< Entry X:2 GRP (ID=0, LETTER=2) */ 1100215976Sjmallett uint64_t reserved_15_15 : 1; 1101215976Sjmallett uint64_t qos1 : 3; /**< Entry X:1 QOS (ID=0, LETTER=1) */ 1102215976Sjmallett uint64_t grp1 : 4; /**< Entry X:1 GRP (ID=0, LETTER=1) */ 1103215976Sjmallett uint64_t reserved_7_7 : 1; 1104215976Sjmallett uint64_t qos0 : 3; /**< Entry X:0 QOS (ID=0, LETTER=0) */ 1105215976Sjmallett uint64_t grp0 : 4; /**< Entry X:0 GRP (ID=0, LETTER=0) */ 1106215976Sjmallett#else 1107215976Sjmallett uint64_t grp0 : 4; 1108215976Sjmallett uint64_t qos0 : 3; 1109215976Sjmallett uint64_t reserved_7_7 : 1; 1110215976Sjmallett uint64_t grp1 : 4; 1111215976Sjmallett uint64_t qos1 : 3; 1112215976Sjmallett uint64_t reserved_15_15 : 1; 1113215976Sjmallett uint64_t grp2 : 4; 1114215976Sjmallett uint64_t qos2 : 3; 1115215976Sjmallett uint64_t reserved_23_23 : 1; 1116215976Sjmallett uint64_t grp3 : 4; 1117215976Sjmallett uint64_t qos3 : 3; 1118215976Sjmallett uint64_t reserved_31_31 : 1; 1119215976Sjmallett uint64_t grp4 : 4; 1120215976Sjmallett uint64_t qos4 : 3; 1121215976Sjmallett uint64_t reserved_39_39 : 1; 1122215976Sjmallett uint64_t grp5 : 4; 1123215976Sjmallett uint64_t qos5 : 3; 1124215976Sjmallett uint64_t reserved_47_47 : 1; 1125215976Sjmallett uint64_t grp6 : 4; 1126215976Sjmallett uint64_t qos6 : 3; 1127215976Sjmallett uint64_t reserved_55_55 : 1; 1128215976Sjmallett uint64_t grp7 : 4; 1129215976Sjmallett uint64_t qos7 : 3; 1130215976Sjmallett uint64_t reserved_63_63 : 1; 1131215976Sjmallett#endif 1132215976Sjmallett } s; 1133215976Sjmallett struct cvmx_sriox_imsg_qos_grpx_s cn63xx; 1134215976Sjmallett struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1; 1135232812Sjmallett struct cvmx_sriox_imsg_qos_grpx_s cn66xx; 1136215976Sjmallett}; 1137215976Sjmalletttypedef union cvmx_sriox_imsg_qos_grpx cvmx_sriox_imsg_qos_grpx_t; 1138215976Sjmallett 1139215976Sjmallett/** 1140215976Sjmallett * cvmx_srio#_imsg_status# 1141215976Sjmallett * 1142215976Sjmallett * SRIO_IMSG_STATUSX = SRIO Incoming Message Status Table 1143215976Sjmallett * 1144215976Sjmallett * The SRIO Incoming Message Status Table Entry X 1145215976Sjmallett * 1146215976Sjmallett * Notes: 1147232812Sjmallett * Clk_Rst: SRIO(0,2..3)_IMSG_STATUS[0:1] hclk hrst_n 1148215976Sjmallett * 1149215976Sjmallett */ 1150232812Sjmallettunion cvmx_sriox_imsg_statusx { 1151215976Sjmallett uint64_t u64; 1152232812Sjmallett struct cvmx_sriox_imsg_statusx_s { 1153232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1154215976Sjmallett uint64_t val1 : 1; /**< Entry X:1 Valid */ 1155215976Sjmallett uint64_t err1 : 1; /**< Entry X:1 Error */ 1156215976Sjmallett uint64_t toe1 : 1; /**< Entry X:1 Timeout Error */ 1157215976Sjmallett uint64_t toc1 : 1; /**< Entry X:1 Timeout Count */ 1158215976Sjmallett uint64_t prt1 : 1; /**< Entry X:1 Port */ 1159215976Sjmallett uint64_t reserved_58_58 : 1; 1160215976Sjmallett uint64_t tt1 : 1; /**< Entry X:1 TT ID */ 1161215976Sjmallett uint64_t dis1 : 1; /**< Entry X:1 Dest ID */ 1162215976Sjmallett uint64_t seg1 : 4; /**< Entry X:1 Next Segment */ 1163215976Sjmallett uint64_t mbox1 : 2; /**< Entry X:1 Mailbox */ 1164215976Sjmallett uint64_t lttr1 : 2; /**< Entry X:1 Letter */ 1165215976Sjmallett uint64_t sid1 : 16; /**< Entry X:1 Source ID */ 1166215976Sjmallett uint64_t val0 : 1; /**< Entry X:0 Valid */ 1167215976Sjmallett uint64_t err0 : 1; /**< Entry X:0 Error */ 1168215976Sjmallett uint64_t toe0 : 1; /**< Entry X:0 Timeout Error */ 1169215976Sjmallett uint64_t toc0 : 1; /**< Entry X:0 Timeout Count */ 1170215976Sjmallett uint64_t prt0 : 1; /**< Entry X:0 Port */ 1171215976Sjmallett uint64_t reserved_26_26 : 1; 1172215976Sjmallett uint64_t tt0 : 1; /**< Entry X:0 TT ID */ 1173215976Sjmallett uint64_t dis0 : 1; /**< Entry X:0 Dest ID */ 1174215976Sjmallett uint64_t seg0 : 4; /**< Entry X:0 Next Segment */ 1175215976Sjmallett uint64_t mbox0 : 2; /**< Entry X:0 Mailbox */ 1176215976Sjmallett uint64_t lttr0 : 2; /**< Entry X:0 Letter */ 1177215976Sjmallett uint64_t sid0 : 16; /**< Entry X:0 Source ID */ 1178215976Sjmallett#else 1179215976Sjmallett uint64_t sid0 : 16; 1180215976Sjmallett uint64_t lttr0 : 2; 1181215976Sjmallett uint64_t mbox0 : 2; 1182215976Sjmallett uint64_t seg0 : 4; 1183215976Sjmallett uint64_t dis0 : 1; 1184215976Sjmallett uint64_t tt0 : 1; 1185215976Sjmallett uint64_t reserved_26_26 : 1; 1186215976Sjmallett uint64_t prt0 : 1; 1187215976Sjmallett uint64_t toc0 : 1; 1188215976Sjmallett uint64_t toe0 : 1; 1189215976Sjmallett uint64_t err0 : 1; 1190215976Sjmallett uint64_t val0 : 1; 1191215976Sjmallett uint64_t sid1 : 16; 1192215976Sjmallett uint64_t lttr1 : 2; 1193215976Sjmallett uint64_t mbox1 : 2; 1194215976Sjmallett uint64_t seg1 : 4; 1195215976Sjmallett uint64_t dis1 : 1; 1196215976Sjmallett uint64_t tt1 : 1; 1197215976Sjmallett uint64_t reserved_58_58 : 1; 1198215976Sjmallett uint64_t prt1 : 1; 1199215976Sjmallett uint64_t toc1 : 1; 1200215976Sjmallett uint64_t toe1 : 1; 1201215976Sjmallett uint64_t err1 : 1; 1202215976Sjmallett uint64_t val1 : 1; 1203215976Sjmallett#endif 1204215976Sjmallett } s; 1205215976Sjmallett struct cvmx_sriox_imsg_statusx_s cn63xx; 1206215976Sjmallett struct cvmx_sriox_imsg_statusx_s cn63xxp1; 1207232812Sjmallett struct cvmx_sriox_imsg_statusx_s cn66xx; 1208215976Sjmallett}; 1209215976Sjmalletttypedef union cvmx_sriox_imsg_statusx cvmx_sriox_imsg_statusx_t; 1210215976Sjmallett 1211215976Sjmallett/** 1212215976Sjmallett * cvmx_srio#_imsg_vport_thr 1213215976Sjmallett * 1214215976Sjmallett * SRIO_IMSG_VPORT_THR = SRIO Incoming Message Virtual Port Threshold 1215215976Sjmallett * 1216215976Sjmallett * The SRIO Incoming Message Virtual Port Threshold Register 1217215976Sjmallett * 1218215976Sjmallett * Notes: 1219232812Sjmallett * SRIO0_IMSG_VPORT_THR.MAX_TOT must be >= SRIO0_IMSG_VPORT_THR.BUF_THR 1220232812Sjmallett * + SRIO2_IMSG_VPORT_THR.BUF_THR + SRIO3_IMSG_VPORT_THR.BUF_THR. This register can be accessed 1221232812Sjmallett * regardless of the value in SRIO(0,2..3)_STATUS_REG.ACCESS and is not effected by MAC reset. The maximum 1222232812Sjmallett * number of VPORTs allocated to a MAC is limited to 46 if QLM0 is configured to x2 or x4 mode and 44 1223232812Sjmallett * if configured in x1 mode. 1224215976Sjmallett * 1225232812Sjmallett * Clk_Rst: SRIO(0,2..3)_IMSG_VPORT_THR sclk srst_n 1226215976Sjmallett */ 1227232812Sjmallettunion cvmx_sriox_imsg_vport_thr { 1228215976Sjmallett uint64_t u64; 1229232812Sjmallett struct cvmx_sriox_imsg_vport_thr_s { 1230232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1231215976Sjmallett uint64_t reserved_54_63 : 10; 1232232812Sjmallett uint64_t max_tot : 6; /**< Sets max number of vports available to the chip 1233232812Sjmallett This field is only used in SRIO0. */ 1234215976Sjmallett uint64_t reserved_46_47 : 2; 1235232812Sjmallett uint64_t max_s1 : 6; /**< Reserved 1236232812Sjmallett This field is only used in SRIO0. */ 1237215976Sjmallett uint64_t reserved_38_39 : 2; 1238215976Sjmallett uint64_t max_s0 : 6; /**< Sets max number of vports available to SRIO0 1239232812Sjmallett This field is only used in SRIO0. */ 1240215976Sjmallett uint64_t sp_vport : 1; /**< Single-segment vport pre-allocation. 1241215976Sjmallett When set, single-segment messages use pre-allocated 1242215976Sjmallett vport slots (that do not count toward thresholds). 1243215976Sjmallett When clear, single-segment messages must allocate 1244215976Sjmallett vport slots just like multi-segment messages do. */ 1245215976Sjmallett uint64_t reserved_20_30 : 11; 1246215976Sjmallett uint64_t buf_thr : 4; /**< Sets number of vports to be buffered by this 1247215976Sjmallett interface. BUF_THR must not be zero when receiving 1248215976Sjmallett messages. The max BUF_THR value is 8. 1249215976Sjmallett Recommend BUF_THR values 1-4. If the 46 available 1250215976Sjmallett vports are not statically-allocated across the two 1251215976Sjmallett SRIO's, smaller BUF_THR values may leave more 1252215976Sjmallett vports available for the other SRIO. Lack of a 1253215976Sjmallett buffered vport can force a retry for a received 1254215976Sjmallett first segment, so, particularly if SP_VPORT=0 1255215976Sjmallett (which is not recommended) or the segment size is 1256215976Sjmallett small, larger BUF_THR values may improve 1257215976Sjmallett performance. */ 1258215976Sjmallett uint64_t reserved_14_15 : 2; 1259215976Sjmallett uint64_t max_p1 : 6; /**< Sets max number of open vports in port 1 */ 1260215976Sjmallett uint64_t reserved_6_7 : 2; 1261215976Sjmallett uint64_t max_p0 : 6; /**< Sets max number of open vports in port 0 */ 1262215976Sjmallett#else 1263215976Sjmallett uint64_t max_p0 : 6; 1264215976Sjmallett uint64_t reserved_6_7 : 2; 1265215976Sjmallett uint64_t max_p1 : 6; 1266215976Sjmallett uint64_t reserved_14_15 : 2; 1267215976Sjmallett uint64_t buf_thr : 4; 1268215976Sjmallett uint64_t reserved_20_30 : 11; 1269215976Sjmallett uint64_t sp_vport : 1; 1270215976Sjmallett uint64_t max_s0 : 6; 1271215976Sjmallett uint64_t reserved_38_39 : 2; 1272215976Sjmallett uint64_t max_s1 : 6; 1273215976Sjmallett uint64_t reserved_46_47 : 2; 1274215976Sjmallett uint64_t max_tot : 6; 1275215976Sjmallett uint64_t reserved_54_63 : 10; 1276215976Sjmallett#endif 1277215976Sjmallett } s; 1278215976Sjmallett struct cvmx_sriox_imsg_vport_thr_s cn63xx; 1279215976Sjmallett struct cvmx_sriox_imsg_vport_thr_s cn63xxp1; 1280232812Sjmallett struct cvmx_sriox_imsg_vport_thr_s cn66xx; 1281215976Sjmallett}; 1282215976Sjmalletttypedef union cvmx_sriox_imsg_vport_thr cvmx_sriox_imsg_vport_thr_t; 1283215976Sjmallett 1284215976Sjmallett/** 1285232812Sjmallett * cvmx_srio#_imsg_vport_thr2 1286232812Sjmallett * 1287232812Sjmallett * SRIO_IMSG_VPORT_THR2 = SRIO Incoming Message Virtual Port Additional Threshold 1288232812Sjmallett * 1289232812Sjmallett * The SRIO Incoming Message Virtual Port Additional Threshold Register 1290232812Sjmallett * 1291232812Sjmallett * Notes: 1292232812Sjmallett * Additional vport thresholds for SRIO MACs 2 and 3. This register is only used in SRIO0 and is only 1293232812Sjmallett * used when the QLM0 is configured as x1 lanes or x2 lanes. In the x1 case the maximum number of 1294232812Sjmallett * VPORTs is limited to 44. In the x2 case the maximum number of VPORTs is limited to 46. These 1295232812Sjmallett * values are ignored in the x4 configuration. This register can be accessed regardless of the value 1296232812Sjmallett * in SRIO(0,2..3)_STATUS_REG.ACCESS and is not effected by MAC reset. 1297232812Sjmallett * 1298232812Sjmallett * Clk_Rst: SRIO(0,2..3)_IMSG_VPORT_THR sclk srst_n 1299232812Sjmallett */ 1300232812Sjmallettunion cvmx_sriox_imsg_vport_thr2 { 1301232812Sjmallett uint64_t u64; 1302232812Sjmallett struct cvmx_sriox_imsg_vport_thr2_s { 1303232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1304232812Sjmallett uint64_t reserved_46_63 : 18; 1305232812Sjmallett uint64_t max_s3 : 6; /**< Sets max number of vports available to SRIO3 1306232812Sjmallett This field is only used in SRIO0. */ 1307232812Sjmallett uint64_t reserved_38_39 : 2; 1308232812Sjmallett uint64_t max_s2 : 6; /**< Sets max number of vports available to SRIO2 1309232812Sjmallett This field is only used in SRIO0. */ 1310232812Sjmallett uint64_t reserved_0_31 : 32; 1311232812Sjmallett#else 1312232812Sjmallett uint64_t reserved_0_31 : 32; 1313232812Sjmallett uint64_t max_s2 : 6; 1314232812Sjmallett uint64_t reserved_38_39 : 2; 1315232812Sjmallett uint64_t max_s3 : 6; 1316232812Sjmallett uint64_t reserved_46_63 : 18; 1317232812Sjmallett#endif 1318232812Sjmallett } s; 1319232812Sjmallett struct cvmx_sriox_imsg_vport_thr2_s cn66xx; 1320232812Sjmallett}; 1321232812Sjmalletttypedef union cvmx_sriox_imsg_vport_thr2 cvmx_sriox_imsg_vport_thr2_t; 1322232812Sjmallett 1323232812Sjmallett/** 1324215976Sjmallett * cvmx_srio#_int2_enable 1325215976Sjmallett * 1326232812Sjmallett * SRIO_INT2_ENABLE = SRIO Interrupt 2 Enable 1327215976Sjmallett * 1328215976Sjmallett * Allows SRIO to generate additional interrupts when corresponding enable bit is set. 1329215976Sjmallett * 1330215976Sjmallett * Notes: 1331232812Sjmallett * This register enables interrupts in SRIO(0,2..3)_INT2_REG that can be asserted while the MAC is in reset. 1332232812Sjmallett * The register can be accessed/modified regardless of the value of SRIO(0,2..3)_STATUS_REG.ACCESS. 1333215976Sjmallett * 1334232812Sjmallett * Clk_Rst: SRIO(0,2..3)_INT2_ENABLE sclk srst_n 1335215976Sjmallett */ 1336232812Sjmallettunion cvmx_sriox_int2_enable { 1337215976Sjmallett uint64_t u64; 1338232812Sjmallett struct cvmx_sriox_int2_enable_s { 1339232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1340215976Sjmallett uint64_t reserved_1_63 : 63; 1341215976Sjmallett uint64_t pko_rst : 1; /**< PKO Reset Error Enable */ 1342215976Sjmallett#else 1343215976Sjmallett uint64_t pko_rst : 1; 1344215976Sjmallett uint64_t reserved_1_63 : 63; 1345215976Sjmallett#endif 1346215976Sjmallett } s; 1347215976Sjmallett struct cvmx_sriox_int2_enable_s cn63xx; 1348232812Sjmallett struct cvmx_sriox_int2_enable_s cn66xx; 1349215976Sjmallett}; 1350215976Sjmalletttypedef union cvmx_sriox_int2_enable cvmx_sriox_int2_enable_t; 1351215976Sjmallett 1352215976Sjmallett/** 1353215976Sjmallett * cvmx_srio#_int2_reg 1354215976Sjmallett * 1355232812Sjmallett * SRIO_INT2_REG = SRIO Interrupt 2 Register 1356215976Sjmallett * 1357215976Sjmallett * Displays and clears which enabled interrupts have occured 1358215976Sjmallett * 1359215976Sjmallett * Notes: 1360215976Sjmallett * This register provides interrupt status. Unlike SRIO*_INT_REG, SRIO*_INT2_REG can be accessed 1361215976Sjmallett * whenever the SRIO is present, regardless of whether the corresponding SRIO is in reset or not. 1362232812Sjmallett * INT_SUM shows the status of the interrupts in SRIO(0,2..3)_INT_REG. Any set bits written to this 1363215976Sjmallett * register clear the corresponding interrupt. The register can be accessed/modified regardless of 1364232812Sjmallett * the value of SRIO(0,2..3)_STATUS_REG.ACCESS and probably should be the first register read when an SRIO 1365215976Sjmallett * interrupt occurs. 1366215976Sjmallett * 1367232812Sjmallett * Clk_Rst: SRIO(0,2..3)_INT2_REG sclk srst_n 1368215976Sjmallett */ 1369232812Sjmallettunion cvmx_sriox_int2_reg { 1370215976Sjmallett uint64_t u64; 1371232812Sjmallett struct cvmx_sriox_int2_reg_s { 1372232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1373215976Sjmallett uint64_t reserved_32_63 : 32; 1374232812Sjmallett uint64_t int_sum : 1; /**< Interrupt Set and Enabled in SRIO(0,2..3)_INT_REG */ 1375215976Sjmallett uint64_t reserved_1_30 : 30; 1376215976Sjmallett uint64_t pko_rst : 1; /**< PKO Reset Error - Message Received from PKO while 1377215976Sjmallett MAC in reset. */ 1378215976Sjmallett#else 1379215976Sjmallett uint64_t pko_rst : 1; 1380215976Sjmallett uint64_t reserved_1_30 : 30; 1381215976Sjmallett uint64_t int_sum : 1; 1382215976Sjmallett uint64_t reserved_32_63 : 32; 1383215976Sjmallett#endif 1384215976Sjmallett } s; 1385215976Sjmallett struct cvmx_sriox_int2_reg_s cn63xx; 1386232812Sjmallett struct cvmx_sriox_int2_reg_s cn66xx; 1387215976Sjmallett}; 1388215976Sjmalletttypedef union cvmx_sriox_int2_reg cvmx_sriox_int2_reg_t; 1389215976Sjmallett 1390215976Sjmallett/** 1391215976Sjmallett * cvmx_srio#_int_enable 1392215976Sjmallett * 1393215976Sjmallett * SRIO_INT_ENABLE = SRIO Interrupt Enable 1394215976Sjmallett * 1395215976Sjmallett * Allows SRIO to generate interrupts when corresponding enable bit is set. 1396215976Sjmallett * 1397215976Sjmallett * Notes: 1398215976Sjmallett * This register enables interrupts. 1399215976Sjmallett * 1400232812Sjmallett * Clk_Rst: SRIO(0,2..3)_INT_ENABLE hclk hrst_n 1401215976Sjmallett */ 1402232812Sjmallettunion cvmx_sriox_int_enable { 1403215976Sjmallett uint64_t u64; 1404232812Sjmallett struct cvmx_sriox_int_enable_s { 1405232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1406232812Sjmallett uint64_t reserved_27_63 : 37; 1407232812Sjmallett uint64_t zero_pkt : 1; /**< Received Incoming SRIO Zero byte packet */ 1408232812Sjmallett uint64_t ttl_tout : 1; /**< Outgoing Packet Time to Live Timeout */ 1409232812Sjmallett uint64_t fail : 1; /**< ERB Error Rate reached Fail Count */ 1410232812Sjmallett uint64_t degrade : 1; /**< ERB Error Rate reached Degrade Count */ 1411232812Sjmallett uint64_t mac_buf : 1; /**< SRIO MAC Buffer CRC Error */ 1412215976Sjmallett uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */ 1413215976Sjmallett uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded */ 1414215976Sjmallett uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */ 1415215976Sjmallett uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error */ 1416215976Sjmallett uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */ 1417215976Sjmallett uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */ 1418215976Sjmallett uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */ 1419215976Sjmallett uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */ 1420215976Sjmallett uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB */ 1421215976Sjmallett uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB */ 1422215976Sjmallett uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */ 1423215976Sjmallett uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */ 1424215976Sjmallett uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */ 1425215976Sjmallett uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */ 1426215976Sjmallett uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */ 1427215976Sjmallett uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. */ 1428215976Sjmallett uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */ 1429215976Sjmallett uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */ 1430215976Sjmallett uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. */ 1431215976Sjmallett uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. */ 1432215976Sjmallett uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. */ 1433215976Sjmallett uint64_t txbell : 1; /**< Outgoing Doorbell Complete. */ 1434215976Sjmallett#else 1435215976Sjmallett uint64_t txbell : 1; 1436215976Sjmallett uint64_t bell_err : 1; 1437215976Sjmallett uint64_t rxbell : 1; 1438215976Sjmallett uint64_t maint_op : 1; 1439215976Sjmallett uint64_t bar_err : 1; 1440215976Sjmallett uint64_t deny_wr : 1; 1441215976Sjmallett uint64_t sli_err : 1; 1442215976Sjmallett uint64_t wr_done : 1; 1443215976Sjmallett uint64_t mce_tx : 1; 1444215976Sjmallett uint64_t mce_rx : 1; 1445215976Sjmallett uint64_t soft_tx : 1; 1446215976Sjmallett uint64_t soft_rx : 1; 1447215976Sjmallett uint64_t log_erb : 1; 1448215976Sjmallett uint64_t phy_erb : 1; 1449215976Sjmallett uint64_t link_dwn : 1; 1450215976Sjmallett uint64_t link_up : 1; 1451215976Sjmallett uint64_t omsg0 : 1; 1452215976Sjmallett uint64_t omsg1 : 1; 1453215976Sjmallett uint64_t omsg_err : 1; 1454215976Sjmallett uint64_t pko_err : 1; 1455215976Sjmallett uint64_t rtry_err : 1; 1456215976Sjmallett uint64_t f_error : 1; 1457215976Sjmallett uint64_t mac_buf : 1; 1458215976Sjmallett uint64_t degrade : 1; 1459215976Sjmallett uint64_t fail : 1; 1460215976Sjmallett uint64_t ttl_tout : 1; 1461232812Sjmallett uint64_t zero_pkt : 1; 1462232812Sjmallett uint64_t reserved_27_63 : 37; 1463215976Sjmallett#endif 1464215976Sjmallett } s; 1465215976Sjmallett struct cvmx_sriox_int_enable_s cn63xx; 1466232812Sjmallett struct cvmx_sriox_int_enable_cn63xxp1 { 1467232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1468215976Sjmallett uint64_t reserved_22_63 : 42; 1469215976Sjmallett uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */ 1470215976Sjmallett uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded */ 1471215976Sjmallett uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */ 1472215976Sjmallett uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error */ 1473215976Sjmallett uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */ 1474215976Sjmallett uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */ 1475215976Sjmallett uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */ 1476215976Sjmallett uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */ 1477215976Sjmallett uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB */ 1478215976Sjmallett uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB */ 1479215976Sjmallett uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */ 1480215976Sjmallett uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */ 1481215976Sjmallett uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */ 1482215976Sjmallett uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */ 1483215976Sjmallett uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */ 1484215976Sjmallett uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. */ 1485215976Sjmallett uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */ 1486215976Sjmallett uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */ 1487215976Sjmallett uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. */ 1488215976Sjmallett uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. */ 1489215976Sjmallett uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. */ 1490215976Sjmallett uint64_t txbell : 1; /**< Outgoing Doorbell Complete. */ 1491215976Sjmallett#else 1492215976Sjmallett uint64_t txbell : 1; 1493215976Sjmallett uint64_t bell_err : 1; 1494215976Sjmallett uint64_t rxbell : 1; 1495215976Sjmallett uint64_t maint_op : 1; 1496215976Sjmallett uint64_t bar_err : 1; 1497215976Sjmallett uint64_t deny_wr : 1; 1498215976Sjmallett uint64_t sli_err : 1; 1499215976Sjmallett uint64_t wr_done : 1; 1500215976Sjmallett uint64_t mce_tx : 1; 1501215976Sjmallett uint64_t mce_rx : 1; 1502215976Sjmallett uint64_t soft_tx : 1; 1503215976Sjmallett uint64_t soft_rx : 1; 1504215976Sjmallett uint64_t log_erb : 1; 1505215976Sjmallett uint64_t phy_erb : 1; 1506215976Sjmallett uint64_t link_dwn : 1; 1507215976Sjmallett uint64_t link_up : 1; 1508215976Sjmallett uint64_t omsg0 : 1; 1509215976Sjmallett uint64_t omsg1 : 1; 1510215976Sjmallett uint64_t omsg_err : 1; 1511215976Sjmallett uint64_t pko_err : 1; 1512215976Sjmallett uint64_t rtry_err : 1; 1513215976Sjmallett uint64_t f_error : 1; 1514215976Sjmallett uint64_t reserved_22_63 : 42; 1515215976Sjmallett#endif 1516215976Sjmallett } cn63xxp1; 1517232812Sjmallett struct cvmx_sriox_int_enable_s cn66xx; 1518215976Sjmallett}; 1519215976Sjmalletttypedef union cvmx_sriox_int_enable cvmx_sriox_int_enable_t; 1520215976Sjmallett 1521215976Sjmallett/** 1522215976Sjmallett * cvmx_srio#_int_info0 1523215976Sjmallett * 1524215976Sjmallett * SRIO_INT_INFO0 = SRIO Interrupt Information 1525215976Sjmallett * 1526215976Sjmallett * The SRIO Interrupt Information 1527215976Sjmallett * 1528215976Sjmallett * Notes: 1529215976Sjmallett * This register contains the first header word of the illegal s2m transaction associated with the 1530232812Sjmallett * SLI_ERR interrupt. The remaining information is located in SRIO(0,2..3)_INT_INFO1. This register is 1531215976Sjmallett * only updated when the SLI_ERR is initially detected. Once the interrupt is cleared then 1532215976Sjmallett * additional information can be captured. 1533215976Sjmallett * Common Errors Include: 1534215976Sjmallett * 1. Load/Stores with Length over 32 1535215976Sjmallett * 2. Load/Stores that translate to Maintenance Ops with a length over 8 1536215976Sjmallett * 3. Load Ops that translate to Atomic Ops with other than 1, 2 and 4 byte accesses 1537215976Sjmallett * 4. Load/Store Ops with a Length 0 1538215976Sjmallett * 5. Unexpected Responses 1539215976Sjmallett * 1540232812Sjmallett * Clk_Rst: SRIO(0,2..3)_INT_REG hclk hrst_n 1541215976Sjmallett */ 1542232812Sjmallettunion cvmx_sriox_int_info0 { 1543215976Sjmallett uint64_t u64; 1544232812Sjmallett struct cvmx_sriox_int_info0_s { 1545232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1546215976Sjmallett uint64_t cmd : 4; /**< Command 1547215976Sjmallett 0 = Load, Outgoing Read Request 1548215976Sjmallett 4 = Store, Outgoing Write Request 1549215976Sjmallett 8 = Response, Outgoing Read Response 1550215976Sjmallett All Others are reserved and generate errors */ 1551215976Sjmallett uint64_t type : 4; /**< Command Type 1552215976Sjmallett Load/Store SRIO_S2M_TYPE used 1553215976Sjmallett Response (Reserved) */ 1554215976Sjmallett uint64_t tag : 8; /**< Internal Transaction Number */ 1555215976Sjmallett uint64_t reserved_42_47 : 6; 1556215976Sjmallett uint64_t length : 10; /**< Data Length in 64-bit Words (Load/Store Only) */ 1557215976Sjmallett uint64_t status : 3; /**< Response Status 1558215976Sjmallett 0 = Success 1559215976Sjmallett 1 = Error 1560215976Sjmallett All others reserved */ 1561215976Sjmallett uint64_t reserved_16_28 : 13; 1562215976Sjmallett uint64_t be0 : 8; /**< First 64-bit Word Byte Enables (Load/Store Only) */ 1563215976Sjmallett uint64_t be1 : 8; /**< Last 64-bit Word Byte Enables (Load/Store Only) */ 1564215976Sjmallett#else 1565215976Sjmallett uint64_t be1 : 8; 1566215976Sjmallett uint64_t be0 : 8; 1567215976Sjmallett uint64_t reserved_16_28 : 13; 1568215976Sjmallett uint64_t status : 3; 1569215976Sjmallett uint64_t length : 10; 1570215976Sjmallett uint64_t reserved_42_47 : 6; 1571215976Sjmallett uint64_t tag : 8; 1572215976Sjmallett uint64_t type : 4; 1573215976Sjmallett uint64_t cmd : 4; 1574215976Sjmallett#endif 1575215976Sjmallett } s; 1576215976Sjmallett struct cvmx_sriox_int_info0_s cn63xx; 1577215976Sjmallett struct cvmx_sriox_int_info0_s cn63xxp1; 1578232812Sjmallett struct cvmx_sriox_int_info0_s cn66xx; 1579215976Sjmallett}; 1580215976Sjmalletttypedef union cvmx_sriox_int_info0 cvmx_sriox_int_info0_t; 1581215976Sjmallett 1582215976Sjmallett/** 1583215976Sjmallett * cvmx_srio#_int_info1 1584215976Sjmallett * 1585215976Sjmallett * SRIO_INT_INFO1 = SRIO Interrupt Information 1586215976Sjmallett * 1587215976Sjmallett * The SRIO Interrupt Information 1588215976Sjmallett * 1589215976Sjmallett * Notes: 1590215976Sjmallett * This register contains the second header word of the illegal s2m transaction associated with the 1591232812Sjmallett * SLI_ERR interrupt. The remaining information is located in SRIO(0,2..3)_INT_INFO0. This register is 1592215976Sjmallett * only updated when the SLI_ERR is initially detected. Once the interrupt is cleared then 1593215976Sjmallett * additional information can be captured. 1594215976Sjmallett * 1595232812Sjmallett * Clk_Rst: SRIO(0,2..3)_INT_REG hclk hrst_n 1596215976Sjmallett */ 1597232812Sjmallettunion cvmx_sriox_int_info1 { 1598215976Sjmallett uint64_t u64; 1599232812Sjmallett struct cvmx_sriox_int_info1_s { 1600232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1601215976Sjmallett uint64_t info1 : 64; /**< Address (Load/Store) or First 64-bit Word of 1602215976Sjmallett Response Data Associated with Interrupt */ 1603215976Sjmallett#else 1604215976Sjmallett uint64_t info1 : 64; 1605215976Sjmallett#endif 1606215976Sjmallett } s; 1607215976Sjmallett struct cvmx_sriox_int_info1_s cn63xx; 1608215976Sjmallett struct cvmx_sriox_int_info1_s cn63xxp1; 1609232812Sjmallett struct cvmx_sriox_int_info1_s cn66xx; 1610215976Sjmallett}; 1611215976Sjmalletttypedef union cvmx_sriox_int_info1 cvmx_sriox_int_info1_t; 1612215976Sjmallett 1613215976Sjmallett/** 1614215976Sjmallett * cvmx_srio#_int_info2 1615215976Sjmallett * 1616215976Sjmallett * SRIO_INT_INFO2 = SRIO Interrupt Information 1617215976Sjmallett * 1618215976Sjmallett * The SRIO Interrupt Information 1619215976Sjmallett * 1620215976Sjmallett * Notes: 1621215976Sjmallett * This register contains the invalid outbound message descriptor associated with the OMSG_ERR 1622215976Sjmallett * interrupt. This register is only updated when the OMSG_ERR is initially detected. Once the 1623215976Sjmallett * interrupt is cleared then additional information can be captured. 1624215976Sjmallett * 1625232812Sjmallett * Clk_Rst: SRIO(0,2..3)_INT_REG hclk hrst_n 1626215976Sjmallett */ 1627232812Sjmallettunion cvmx_sriox_int_info2 { 1628215976Sjmallett uint64_t u64; 1629232812Sjmallett struct cvmx_sriox_int_info2_s { 1630232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1631215976Sjmallett uint64_t prio : 2; /**< PRIO field of outbound message descriptor 1632215976Sjmallett associated with the OMSG_ERR interrupt */ 1633215976Sjmallett uint64_t tt : 1; /**< TT field of outbound message descriptor 1634215976Sjmallett associated with the OMSG_ERR interrupt */ 1635215976Sjmallett uint64_t sis : 1; /**< SIS field of outbound message descriptor 1636215976Sjmallett associated with the OMSG_ERR interrupt */ 1637215976Sjmallett uint64_t ssize : 4; /**< SSIZE field of outbound message descriptor 1638215976Sjmallett associated with the OMSG_ERR interrupt */ 1639215976Sjmallett uint64_t did : 16; /**< DID field of outbound message descriptor 1640215976Sjmallett associated with the OMSG_ERR interrupt */ 1641215976Sjmallett uint64_t xmbox : 4; /**< XMBOX field of outbound message descriptor 1642215976Sjmallett associated with the OMSG_ERR interrupt */ 1643215976Sjmallett uint64_t mbox : 2; /**< MBOX field of outbound message descriptor 1644215976Sjmallett associated with the OMSG_ERR interrupt */ 1645215976Sjmallett uint64_t letter : 2; /**< LETTER field of outbound message descriptor 1646215976Sjmallett associated with the OMSG_ERR interrupt */ 1647215976Sjmallett uint64_t rsrvd : 30; /**< RSRVD field of outbound message descriptor 1648215976Sjmallett associated with the OMSG_ERR interrupt */ 1649215976Sjmallett uint64_t lns : 1; /**< LNS field of outbound message descriptor 1650215976Sjmallett associated with the OMSG_ERR interrupt */ 1651215976Sjmallett uint64_t intr : 1; /**< INT field of outbound message descriptor 1652215976Sjmallett associated with the OMSG_ERR interrupt */ 1653215976Sjmallett#else 1654215976Sjmallett uint64_t intr : 1; 1655215976Sjmallett uint64_t lns : 1; 1656215976Sjmallett uint64_t rsrvd : 30; 1657215976Sjmallett uint64_t letter : 2; 1658215976Sjmallett uint64_t mbox : 2; 1659215976Sjmallett uint64_t xmbox : 4; 1660215976Sjmallett uint64_t did : 16; 1661215976Sjmallett uint64_t ssize : 4; 1662215976Sjmallett uint64_t sis : 1; 1663215976Sjmallett uint64_t tt : 1; 1664215976Sjmallett uint64_t prio : 2; 1665215976Sjmallett#endif 1666215976Sjmallett } s; 1667215976Sjmallett struct cvmx_sriox_int_info2_s cn63xx; 1668215976Sjmallett struct cvmx_sriox_int_info2_s cn63xxp1; 1669232812Sjmallett struct cvmx_sriox_int_info2_s cn66xx; 1670215976Sjmallett}; 1671215976Sjmalletttypedef union cvmx_sriox_int_info2 cvmx_sriox_int_info2_t; 1672215976Sjmallett 1673215976Sjmallett/** 1674215976Sjmallett * cvmx_srio#_int_info3 1675215976Sjmallett * 1676215976Sjmallett * SRIO_INT_INFO3 = SRIO Interrupt Information 1677215976Sjmallett * 1678215976Sjmallett * The SRIO Interrupt Information 1679215976Sjmallett * 1680215976Sjmallett * Notes: 1681215976Sjmallett * This register contains the retry response associated with the RTRY_ERR interrupt. This register 1682215976Sjmallett * is only updated when the RTRY_ERR is initially detected. Once the interrupt is cleared then 1683215976Sjmallett * additional information can be captured. 1684215976Sjmallett * 1685232812Sjmallett * Clk_Rst: SRIO(0,2..3)_INT_REG hclk hrst_n 1686215976Sjmallett */ 1687232812Sjmallettunion cvmx_sriox_int_info3 { 1688215976Sjmallett uint64_t u64; 1689232812Sjmallett struct cvmx_sriox_int_info3_s { 1690232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1691215976Sjmallett uint64_t prio : 2; /**< Priority of received retry response message */ 1692215976Sjmallett uint64_t tt : 2; /**< TT of received retry response message */ 1693215976Sjmallett uint64_t type : 4; /**< Type of received retry response message 1694215976Sjmallett (should be 13) */ 1695215976Sjmallett uint64_t other : 48; /**< Other fields of received retry response message 1696215976Sjmallett If TT==0 (8-bit ID's) 1697215976Sjmallett OTHER<47:40> => destination ID 1698215976Sjmallett OTHER<39:32> => source ID 1699215976Sjmallett OTHER<31:28> => transaction (should be 1 - msg) 1700215976Sjmallett OTHER<27:24> => status (should be 3 - retry) 1701215976Sjmallett OTHER<23:22> => letter 1702215976Sjmallett OTHER<21:20> => mbox 1703215976Sjmallett OTHER<19:16> => msgseg 1704215976Sjmallett OTHER<15:0> => unused 1705215976Sjmallett If TT==1 (16-bit ID's) 1706215976Sjmallett OTHER<47:32> => destination ID 1707215976Sjmallett OTHER<31:16> => source ID 1708215976Sjmallett OTHER<15:12> => transaction (should be 1 - msg) 1709215976Sjmallett OTHER<11:8> => status (should be 3 - retry) 1710215976Sjmallett OTHER<7:6> => letter 1711215976Sjmallett OTHER<5:4> => mbox 1712215976Sjmallett OTHER<3:0> => msgseg */ 1713215976Sjmallett uint64_t reserved_0_7 : 8; 1714215976Sjmallett#else 1715215976Sjmallett uint64_t reserved_0_7 : 8; 1716215976Sjmallett uint64_t other : 48; 1717215976Sjmallett uint64_t type : 4; 1718215976Sjmallett uint64_t tt : 2; 1719215976Sjmallett uint64_t prio : 2; 1720215976Sjmallett#endif 1721215976Sjmallett } s; 1722215976Sjmallett struct cvmx_sriox_int_info3_s cn63xx; 1723215976Sjmallett struct cvmx_sriox_int_info3_s cn63xxp1; 1724232812Sjmallett struct cvmx_sriox_int_info3_s cn66xx; 1725215976Sjmallett}; 1726215976Sjmalletttypedef union cvmx_sriox_int_info3 cvmx_sriox_int_info3_t; 1727215976Sjmallett 1728215976Sjmallett/** 1729215976Sjmallett * cvmx_srio#_int_reg 1730215976Sjmallett * 1731215976Sjmallett * SRIO_INT_REG = SRIO Interrupt Register 1732215976Sjmallett * 1733215976Sjmallett * Displays and clears which enabled interrupts have occured 1734215976Sjmallett * 1735215976Sjmallett * Notes: 1736215976Sjmallett * This register provides interrupt status. Like most SRIO CSRs, this register can only 1737215976Sjmallett * be read/written when the corresponding SRIO is both present and not in reset. (SRIO*_INT2_REG 1738215976Sjmallett * can be accessed when SRIO is in reset.) Any set bits written to this register clear the 1739215976Sjmallett * corresponding interrupt. The RXBELL interrupt is cleared by reading all the entries in the 1740215976Sjmallett * incoming Doorbell FIFO. The LOG_ERB interrupt must be cleared before writing zeroes 1741215976Sjmallett * to clear the bits in the SRIOMAINT*_ERB_LT_ERR_DET register. Otherwise a new interrupt may be 1742215976Sjmallett * lost. The PHY_ERB interrupt must be cleared before writing a zero to 1743215976Sjmallett * SRIOMAINT*_ERB_ATTR_CAPT[VALID]. Otherwise, a new interrupt may be lost. OMSG_ERR is set when an 1744215976Sjmallett * invalid outbound message descriptor is received. The descriptor is deemed to be invalid if the 1745215976Sjmallett * SSIZE field is set to a reserved value, the SSIZE field combined with the packet length would 1746215976Sjmallett * result in more than 16 message segments, or the packet only contains a descriptor (no data). 1747215976Sjmallett * 1748232812Sjmallett * Clk_Rst: SRIO(0,2..3)_INT_REG hclk hrst_n 1749215976Sjmallett */ 1750232812Sjmallettunion cvmx_sriox_int_reg { 1751215976Sjmallett uint64_t u64; 1752232812Sjmallett struct cvmx_sriox_int_reg_s { 1753232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1754215976Sjmallett uint64_t reserved_32_63 : 32; 1755232812Sjmallett uint64_t int2_sum : 1; /**< Interrupt Set and Enabled in SRIO(0,2..3)_INT2_REG */ 1756232812Sjmallett uint64_t reserved_27_30 : 4; 1757232812Sjmallett uint64_t zero_pkt : 1; /**< Received Incoming SRIO Zero byte packet */ 1758232812Sjmallett uint64_t ttl_tout : 1; /**< Outgoing Packet Time to Live Timeout 1759232812Sjmallett See SRIOMAINT(0,2..3)_DROP_PACKET */ 1760232812Sjmallett uint64_t fail : 1; /**< ERB Error Rate reached Fail Count 1761232812Sjmallett See SRIOMAINT(0,2..3)_ERB_ERR_RATE */ 1762232812Sjmallett uint64_t degrad : 1; /**< ERB Error Rate reached Degrade Count 1763232812Sjmallett See SRIOMAINT(0,2..3)_ERB_ERR_RATE */ 1764232812Sjmallett uint64_t mac_buf : 1; /**< SRIO MAC Buffer CRC Error 1765232812Sjmallett See SRIO(0,2..3)_MAC_BUFFERS */ 1766215976Sjmallett uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */ 1767215976Sjmallett uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded 1768232812Sjmallett See SRIO(0,2..3)_INT_INFO3 1769215976Sjmallett When one or more of the segments in an outgoing 1770215976Sjmallett message have a RTRY_ERR, SRIO will not set 1771215976Sjmallett OMSG* after the message "transfer". */ 1772215976Sjmallett uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */ 1773215976Sjmallett uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error 1774232812Sjmallett See SRIO(0,2..3)_INT_INFO2 */ 1775232812Sjmallett uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete 1776232812Sjmallett See SRIO(0,2..3)_OMSG_DONE_COUNTS1 */ 1777232812Sjmallett uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete 1778232812Sjmallett See SRIO(0,2..3)_OMSG_DONE_COUNTS0 */ 1779215976Sjmallett uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */ 1780215976Sjmallett uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */ 1781215976Sjmallett uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB 1782215976Sjmallett See SRIOMAINT*_ERB_ATTR_CAPT */ 1783215976Sjmallett uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB 1784232812Sjmallett See SRIOMAINT(0,2..3)_ERB_LT_ERR_DET */ 1785215976Sjmallett uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */ 1786215976Sjmallett uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */ 1787215976Sjmallett uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */ 1788215976Sjmallett uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */ 1789232812Sjmallett uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. 1790232812Sjmallett See SRIO(0,2..3)_WR_DONE_COUNTS */ 1791215976Sjmallett uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. 1792232812Sjmallett See SRIO(0,2..3)_INT_INFO[1:0] */ 1793215976Sjmallett uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */ 1794215976Sjmallett uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */ 1795215976Sjmallett uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. 1796232812Sjmallett See SRIO(0,2..3)_MAINT_OP and SRIO(0,2..3)_MAINT_RD_DATA */ 1797215976Sjmallett uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. 1798232812Sjmallett Read SRIO(0,2..3)_RX_BELL to empty FIFO */ 1799215976Sjmallett uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. 1800232812Sjmallett See SRIO(0,2..3)_TX_BELL_INFO */ 1801215976Sjmallett uint64_t txbell : 1; /**< Outgoing Doorbell Complete. 1802215976Sjmallett TXBELL will not be asserted if a Timeout, Retry or 1803215976Sjmallett Error occurs. */ 1804215976Sjmallett#else 1805215976Sjmallett uint64_t txbell : 1; 1806215976Sjmallett uint64_t bell_err : 1; 1807215976Sjmallett uint64_t rxbell : 1; 1808215976Sjmallett uint64_t maint_op : 1; 1809215976Sjmallett uint64_t bar_err : 1; 1810215976Sjmallett uint64_t deny_wr : 1; 1811215976Sjmallett uint64_t sli_err : 1; 1812215976Sjmallett uint64_t wr_done : 1; 1813215976Sjmallett uint64_t mce_tx : 1; 1814215976Sjmallett uint64_t mce_rx : 1; 1815215976Sjmallett uint64_t soft_tx : 1; 1816215976Sjmallett uint64_t soft_rx : 1; 1817215976Sjmallett uint64_t log_erb : 1; 1818215976Sjmallett uint64_t phy_erb : 1; 1819215976Sjmallett uint64_t link_dwn : 1; 1820215976Sjmallett uint64_t link_up : 1; 1821215976Sjmallett uint64_t omsg0 : 1; 1822215976Sjmallett uint64_t omsg1 : 1; 1823215976Sjmallett uint64_t omsg_err : 1; 1824215976Sjmallett uint64_t pko_err : 1; 1825215976Sjmallett uint64_t rtry_err : 1; 1826215976Sjmallett uint64_t f_error : 1; 1827215976Sjmallett uint64_t mac_buf : 1; 1828215976Sjmallett uint64_t degrad : 1; 1829215976Sjmallett uint64_t fail : 1; 1830215976Sjmallett uint64_t ttl_tout : 1; 1831232812Sjmallett uint64_t zero_pkt : 1; 1832232812Sjmallett uint64_t reserved_27_30 : 4; 1833215976Sjmallett uint64_t int2_sum : 1; 1834215976Sjmallett uint64_t reserved_32_63 : 32; 1835215976Sjmallett#endif 1836215976Sjmallett } s; 1837215976Sjmallett struct cvmx_sriox_int_reg_s cn63xx; 1838232812Sjmallett struct cvmx_sriox_int_reg_cn63xxp1 { 1839232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1840215976Sjmallett uint64_t reserved_22_63 : 42; 1841215976Sjmallett uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */ 1842215976Sjmallett uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded 1843215976Sjmallett See SRIO(0..1)_INT_INFO3 1844215976Sjmallett When one or more of the segments in an outgoing 1845215976Sjmallett message have a RTRY_ERR, SRIO will not set 1846215976Sjmallett OMSG* after the message "transfer". */ 1847215976Sjmallett uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */ 1848215976Sjmallett uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error 1849215976Sjmallett See SRIO(0..1)_INT_INFO2 */ 1850215976Sjmallett uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */ 1851215976Sjmallett uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */ 1852215976Sjmallett uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */ 1853215976Sjmallett uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */ 1854215976Sjmallett uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB 1855215976Sjmallett See SRIOMAINT*_ERB_ATTR_CAPT */ 1856215976Sjmallett uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB 1857215976Sjmallett See SRIOMAINT(0..1)_ERB_LT_ERR_DET */ 1858215976Sjmallett uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */ 1859215976Sjmallett uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */ 1860215976Sjmallett uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */ 1861215976Sjmallett uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */ 1862215976Sjmallett uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */ 1863215976Sjmallett uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. 1864215976Sjmallett See SRIO(0..1)_INT_INFO[1:0] */ 1865215976Sjmallett uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */ 1866215976Sjmallett uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */ 1867215976Sjmallett uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. 1868215976Sjmallett See SRIO(0..1)_MAINT_OP and SRIO(0..1)_MAINT_RD_DATA */ 1869215976Sjmallett uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. 1870215976Sjmallett Read SRIO(0..1)_RX_BELL to empty FIFO */ 1871215976Sjmallett uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. 1872215976Sjmallett See SRIO(0..1)_TX_BELL_INFO */ 1873215976Sjmallett uint64_t txbell : 1; /**< Outgoing Doorbell Complete. 1874215976Sjmallett TXBELL will not be asserted if a Timeout, Retry or 1875215976Sjmallett Error occurs. */ 1876215976Sjmallett#else 1877215976Sjmallett uint64_t txbell : 1; 1878215976Sjmallett uint64_t bell_err : 1; 1879215976Sjmallett uint64_t rxbell : 1; 1880215976Sjmallett uint64_t maint_op : 1; 1881215976Sjmallett uint64_t bar_err : 1; 1882215976Sjmallett uint64_t deny_wr : 1; 1883215976Sjmallett uint64_t sli_err : 1; 1884215976Sjmallett uint64_t wr_done : 1; 1885215976Sjmallett uint64_t mce_tx : 1; 1886215976Sjmallett uint64_t mce_rx : 1; 1887215976Sjmallett uint64_t soft_tx : 1; 1888215976Sjmallett uint64_t soft_rx : 1; 1889215976Sjmallett uint64_t log_erb : 1; 1890215976Sjmallett uint64_t phy_erb : 1; 1891215976Sjmallett uint64_t link_dwn : 1; 1892215976Sjmallett uint64_t link_up : 1; 1893215976Sjmallett uint64_t omsg0 : 1; 1894215976Sjmallett uint64_t omsg1 : 1; 1895215976Sjmallett uint64_t omsg_err : 1; 1896215976Sjmallett uint64_t pko_err : 1; 1897215976Sjmallett uint64_t rtry_err : 1; 1898215976Sjmallett uint64_t f_error : 1; 1899215976Sjmallett uint64_t reserved_22_63 : 42; 1900215976Sjmallett#endif 1901215976Sjmallett } cn63xxp1; 1902232812Sjmallett struct cvmx_sriox_int_reg_s cn66xx; 1903215976Sjmallett}; 1904215976Sjmalletttypedef union cvmx_sriox_int_reg cvmx_sriox_int_reg_t; 1905215976Sjmallett 1906215976Sjmallett/** 1907215976Sjmallett * cvmx_srio#_ip_feature 1908215976Sjmallett * 1909215976Sjmallett * SRIO_IP_FEATURE = SRIO IP Feature Select 1910215976Sjmallett * 1911215976Sjmallett * Debug Register used to enable IP Core Features 1912215976Sjmallett * 1913215976Sjmallett * Notes: 1914215976Sjmallett * This register is used to override powerup values used by the SRIOMAINT Registers and QLM 1915215976Sjmallett * configuration. The register is only reset during COLD boot. It should only be modified only 1916232812Sjmallett * while SRIO(0,2..3)_STATUS_REG.ACCESS is zero. 1917215976Sjmallett * 1918232812Sjmallett * Clk_Rst: SRIO(0,2..3)_IP_FEATURE sclk srst_cold_n 1919215976Sjmallett */ 1920232812Sjmallettunion cvmx_sriox_ip_feature { 1921215976Sjmallett uint64_t u64; 1922232812Sjmallett struct cvmx_sriox_ip_feature_s { 1923232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1924215976Sjmallett uint64_t ops : 32; /**< Reset Value for the OPs fields in both the 1925232812Sjmallett SRIOMAINT(0,2..3)_SRC_OPS and SRIOMAINT(0,2..3)_DST_OPS 1926232812Sjmallett registers. */ 1927232812Sjmallett uint64_t reserved_15_31 : 17; 1928232812Sjmallett uint64_t no_vmin : 1; /**< Lane Sync Valid Minimum Count Disable. (Pass 3) 1929232812Sjmallett 0 = Wait for 2^12 valid codewords and at least 1930232812Sjmallett 127 comma characters before starting 1931232812Sjmallett alignment. 1932232812Sjmallett 1 = Wait only for 127 comma characters before 1933232812Sjmallett starting alignment. (SRIO V1.3 Compatable) */ 1934232812Sjmallett uint64_t a66 : 1; /**< 66-bit Address Support. Value for bit 2 of the 1935232812Sjmallett EX_ADDR field in the SRIOMAINT(0,2..3)_PE_FEAT register. */ 1936232812Sjmallett uint64_t a50 : 1; /**< 50-bit Address Support. Value for bit 1 of the 1937232812Sjmallett EX_ADDR field in the SRIOMAINT(0,2..3)_PE_FEAT register. */ 1938232812Sjmallett uint64_t reserved_11_11 : 1; 1939232812Sjmallett uint64_t tx_flow : 1; /**< Reset Value for the TX_FLOW field in the 1940232812Sjmallett SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG register. */ 1941232812Sjmallett uint64_t pt_width : 2; /**< Value for the PT_WIDTH field in the 1942232812Sjmallett SRIOMAINT(0,2..3)_PORT_0_CTL register. */ 1943232812Sjmallett uint64_t tx_pol : 4; /**< TX Serdes Polarity Lanes 3-0 1944232812Sjmallett 0 = Normal Operation 1945232812Sjmallett 1 = Invert, Swap +/- Tx SERDES Pins */ 1946232812Sjmallett uint64_t rx_pol : 4; /**< RX Serdes Polarity Lanes 3-0 1947232812Sjmallett 0 = Normal Operation 1948232812Sjmallett 1 = Invert, Swap +/- Rx SERDES Pins */ 1949232812Sjmallett#else 1950232812Sjmallett uint64_t rx_pol : 4; 1951232812Sjmallett uint64_t tx_pol : 4; 1952232812Sjmallett uint64_t pt_width : 2; 1953232812Sjmallett uint64_t tx_flow : 1; 1954232812Sjmallett uint64_t reserved_11_11 : 1; 1955232812Sjmallett uint64_t a50 : 1; 1956232812Sjmallett uint64_t a66 : 1; 1957232812Sjmallett uint64_t no_vmin : 1; 1958232812Sjmallett uint64_t reserved_15_31 : 17; 1959232812Sjmallett uint64_t ops : 32; 1960232812Sjmallett#endif 1961232812Sjmallett } s; 1962232812Sjmallett struct cvmx_sriox_ip_feature_cn63xx { 1963232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1964232812Sjmallett uint64_t ops : 32; /**< Reset Value for the OPs fields in both the 1965215976Sjmallett SRIOMAINT(0..1)_SRC_OPS and SRIOMAINT(0..1)_DST_OPS 1966215976Sjmallett registers. */ 1967215976Sjmallett uint64_t reserved_14_31 : 18; 1968215976Sjmallett uint64_t a66 : 1; /**< 66-bit Address Support. Value for bit 2 of the 1969215976Sjmallett EX_ADDR field in the SRIOMAINT(0..1)_PE_FEAT register. */ 1970215976Sjmallett uint64_t a50 : 1; /**< 50-bit Address Support. Value for bit 1 of the 1971215976Sjmallett EX_ADDR field in the SRIOMAINT(0..1)_PE_FEAT register. */ 1972215976Sjmallett uint64_t reserved_11_11 : 1; 1973215976Sjmallett uint64_t tx_flow : 1; /**< Reset Value for the TX_FLOW field in the 1974232812Sjmallett SRIOMAINT(0..1)_IR_BUFFER_CONFIG register. 1975232812Sjmallett Pass 2 will Reset to 1 when RTL ready. 1976232812Sjmallett (TX flow control not supported in pass 1) */ 1977215976Sjmallett uint64_t pt_width : 2; /**< Value for the PT_WIDTH field in the 1978232812Sjmallett SRIOMAINT(0..1)_PORT_0_CTL register. 1979232812Sjmallett Reset to 0x2 rather than 0x3 in pass 1 (2 lane 1980232812Sjmallett interface supported in pass 1). */ 1981215976Sjmallett uint64_t tx_pol : 4; /**< TX Serdes Polarity Lanes 3-0 1982215976Sjmallett 0 = Normal Operation 1983215976Sjmallett 1 = Invert, Swap +/- Tx SERDES Pins */ 1984215976Sjmallett uint64_t rx_pol : 4; /**< RX Serdes Polarity Lanes 3-0 1985215976Sjmallett 0 = Normal Operation 1986215976Sjmallett 1 = Invert, Swap +/- Rx SERDES Pins */ 1987215976Sjmallett#else 1988215976Sjmallett uint64_t rx_pol : 4; 1989215976Sjmallett uint64_t tx_pol : 4; 1990215976Sjmallett uint64_t pt_width : 2; 1991215976Sjmallett uint64_t tx_flow : 1; 1992215976Sjmallett uint64_t reserved_11_11 : 1; 1993215976Sjmallett uint64_t a50 : 1; 1994215976Sjmallett uint64_t a66 : 1; 1995215976Sjmallett uint64_t reserved_14_31 : 18; 1996215976Sjmallett uint64_t ops : 32; 1997215976Sjmallett#endif 1998232812Sjmallett } cn63xx; 1999232812Sjmallett struct cvmx_sriox_ip_feature_cn63xx cn63xxp1; 2000232812Sjmallett struct cvmx_sriox_ip_feature_s cn66xx; 2001215976Sjmallett}; 2002215976Sjmalletttypedef union cvmx_sriox_ip_feature cvmx_sriox_ip_feature_t; 2003215976Sjmallett 2004215976Sjmallett/** 2005215976Sjmallett * cvmx_srio#_mac_buffers 2006215976Sjmallett * 2007232812Sjmallett * SRIO_MAC_BUFFERS = SRIO MAC Buffer Control 2008215976Sjmallett * 2009215976Sjmallett * Reports errors and controls buffer usage on the main MAC buffers 2010215976Sjmallett * 2011215976Sjmallett * Notes: 2012215976Sjmallett * Register displays errors status for each of the eight RX and TX buffers and controls use of the 2013215976Sjmallett * buffer in future operations. It also displays the number of RX and TX buffers currently used by 2014215976Sjmallett * the MAC. 2015215976Sjmallett * 2016232812Sjmallett * Clk_Rst: SRIO(0,2..3)_MAC_BUFFERS hclk hrst_n 2017215976Sjmallett */ 2018232812Sjmallettunion cvmx_sriox_mac_buffers { 2019215976Sjmallett uint64_t u64; 2020232812Sjmallett struct cvmx_sriox_mac_buffers_s { 2021232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2022215976Sjmallett uint64_t reserved_56_63 : 8; 2023215976Sjmallett uint64_t tx_enb : 8; /**< TX Buffer Enable. Each bit enables a specific TX 2024215976Sjmallett Buffer. At least 2 of these bits must be set for 2025215976Sjmallett proper operation. These bits must be cleared to 2026215976Sjmallett and then set again to reuese the buffer after an 2027215976Sjmallett error occurs. */ 2028215976Sjmallett uint64_t reserved_44_47 : 4; 2029215976Sjmallett uint64_t tx_inuse : 4; /**< Number of TX buffers containing packets waiting 2030215976Sjmallett to be transmitted or to be acknowledged. */ 2031215976Sjmallett uint64_t tx_stat : 8; /**< Errors detected in main SRIO Transmit Buffers. 2032215976Sjmallett CRC error detected in buffer sets bit of buffer \# 2033215976Sjmallett until the corresponding TX_ENB is disabled. Each 2034232812Sjmallett bit set causes the SRIO(0,2..3)_INT_REG.MAC_BUF 2035215976Sjmallett interrupt. */ 2036215976Sjmallett uint64_t reserved_24_31 : 8; 2037215976Sjmallett uint64_t rx_enb : 8; /**< RX Buffer Enable. Each bit enables a specific RX 2038215976Sjmallett Buffer. At least 2 of these bits must be set for 2039215976Sjmallett proper operation. These bits must be cleared to 2040215976Sjmallett and then set again to reuese the buffer after an 2041215976Sjmallett error occurs. */ 2042215976Sjmallett uint64_t reserved_12_15 : 4; 2043215976Sjmallett uint64_t rx_inuse : 4; /**< Number of RX buffers containing valid packets 2044215976Sjmallett waiting to be processed by the logical layer. */ 2045215976Sjmallett uint64_t rx_stat : 8; /**< Errors detected in main SRIO Receive Buffers. CRC 2046215976Sjmallett error detected in buffer sets bit of buffer \# 2047215976Sjmallett until the corresponding RX_ENB is disabled. Each 2048232812Sjmallett bit set causes the SRIO(0,2..3)_INT_REG.MAC_BUF 2049215976Sjmallett interrupt. */ 2050215976Sjmallett#else 2051215976Sjmallett uint64_t rx_stat : 8; 2052215976Sjmallett uint64_t rx_inuse : 4; 2053215976Sjmallett uint64_t reserved_12_15 : 4; 2054215976Sjmallett uint64_t rx_enb : 8; 2055215976Sjmallett uint64_t reserved_24_31 : 8; 2056215976Sjmallett uint64_t tx_stat : 8; 2057215976Sjmallett uint64_t tx_inuse : 4; 2058215976Sjmallett uint64_t reserved_44_47 : 4; 2059215976Sjmallett uint64_t tx_enb : 8; 2060215976Sjmallett uint64_t reserved_56_63 : 8; 2061215976Sjmallett#endif 2062215976Sjmallett } s; 2063215976Sjmallett struct cvmx_sriox_mac_buffers_s cn63xx; 2064232812Sjmallett struct cvmx_sriox_mac_buffers_s cn66xx; 2065215976Sjmallett}; 2066215976Sjmalletttypedef union cvmx_sriox_mac_buffers cvmx_sriox_mac_buffers_t; 2067215976Sjmallett 2068215976Sjmallett/** 2069215976Sjmallett * cvmx_srio#_maint_op 2070215976Sjmallett * 2071215976Sjmallett * SRIO_MAINT_OP = SRIO Maintenance Operation 2072215976Sjmallett * 2073215976Sjmallett * Allows access to maintenance registers. 2074215976Sjmallett * 2075215976Sjmallett * Notes: 2076215976Sjmallett * This register allows write access to the local SRIOMAINT registers. A write to this register 2077215976Sjmallett * posts a read or write operation selected by the OP bit to the local SRIOMAINT register selected by 2078215976Sjmallett * ADDR. This write also sets the PENDING bit. The PENDING bit is cleared by hardware when the 2079215976Sjmallett * operation is complete. The MAINT_OP Interrupt is also set as the PENDING bit is cleared. While 2080215976Sjmallett * this bit is set, additional writes to this register stall the RSL. The FAIL bit is set with the 2081215976Sjmallett * clearing of the PENDING bit when an illegal address is selected. WR_DATA is used only during write 2082215976Sjmallett * operations. Only 32-bit Maintenance Operations are supported. 2083215976Sjmallett * 2084232812Sjmallett * Clk_Rst: SRIO(0,2..3)_MAINT_OP hclk hrst_n 2085215976Sjmallett */ 2086232812Sjmallettunion cvmx_sriox_maint_op { 2087215976Sjmallett uint64_t u64; 2088232812Sjmallett struct cvmx_sriox_maint_op_s { 2089232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2090215976Sjmallett uint64_t wr_data : 32; /**< Write Data[31:0]. */ 2091215976Sjmallett uint64_t reserved_27_31 : 5; 2092215976Sjmallett uint64_t fail : 1; /**< Maintenance Operation Address Error */ 2093215976Sjmallett uint64_t pending : 1; /**< Maintenance Operation Pending */ 2094215976Sjmallett uint64_t op : 1; /**< Operation. 0=Read, 1=Write */ 2095215976Sjmallett uint64_t addr : 24; /**< Address. Addr[1:0] are ignored. */ 2096215976Sjmallett#else 2097215976Sjmallett uint64_t addr : 24; 2098215976Sjmallett uint64_t op : 1; 2099215976Sjmallett uint64_t pending : 1; 2100215976Sjmallett uint64_t fail : 1; 2101215976Sjmallett uint64_t reserved_27_31 : 5; 2102215976Sjmallett uint64_t wr_data : 32; 2103215976Sjmallett#endif 2104215976Sjmallett } s; 2105215976Sjmallett struct cvmx_sriox_maint_op_s cn63xx; 2106215976Sjmallett struct cvmx_sriox_maint_op_s cn63xxp1; 2107232812Sjmallett struct cvmx_sriox_maint_op_s cn66xx; 2108215976Sjmallett}; 2109215976Sjmalletttypedef union cvmx_sriox_maint_op cvmx_sriox_maint_op_t; 2110215976Sjmallett 2111215976Sjmallett/** 2112215976Sjmallett * cvmx_srio#_maint_rd_data 2113215976Sjmallett * 2114215976Sjmallett * SRIO_MAINT_RD_DATA = SRIO Maintenance Read Data 2115215976Sjmallett * 2116215976Sjmallett * Allows read access of maintenance registers. 2117215976Sjmallett * 2118215976Sjmallett * Notes: 2119232812Sjmallett * This register allows read access of the local SRIOMAINT registers. A write to the SRIO(0,2..3)_MAINT_OP 2120215976Sjmallett * register with the OP bit set to zero initiates a read request and clears the VALID bit. The 2121215976Sjmallett * resulting read is returned here and the VALID bit is set. Access to the register will not stall 2122215976Sjmallett * the RSL but the VALID bit should be read. 2123215976Sjmallett * 2124232812Sjmallett * Clk_Rst: SRIO(0,2..3)_MAINT_RD_DATA hclk hrst_n 2125215976Sjmallett */ 2126232812Sjmallettunion cvmx_sriox_maint_rd_data { 2127215976Sjmallett uint64_t u64; 2128232812Sjmallett struct cvmx_sriox_maint_rd_data_s { 2129232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2130215976Sjmallett uint64_t reserved_33_63 : 31; 2131215976Sjmallett uint64_t valid : 1; /**< Read Data Valid. */ 2132215976Sjmallett uint64_t rd_data : 32; /**< Read Data[31:0]. */ 2133215976Sjmallett#else 2134215976Sjmallett uint64_t rd_data : 32; 2135215976Sjmallett uint64_t valid : 1; 2136215976Sjmallett uint64_t reserved_33_63 : 31; 2137215976Sjmallett#endif 2138215976Sjmallett } s; 2139215976Sjmallett struct cvmx_sriox_maint_rd_data_s cn63xx; 2140215976Sjmallett struct cvmx_sriox_maint_rd_data_s cn63xxp1; 2141232812Sjmallett struct cvmx_sriox_maint_rd_data_s cn66xx; 2142215976Sjmallett}; 2143215976Sjmalletttypedef union cvmx_sriox_maint_rd_data cvmx_sriox_maint_rd_data_t; 2144215976Sjmallett 2145215976Sjmallett/** 2146215976Sjmallett * cvmx_srio#_mce_tx_ctl 2147215976Sjmallett * 2148215976Sjmallett * SRIO_MCE_TX_CTL = SRIO Multicast Event Transmit Control 2149215976Sjmallett * 2150215976Sjmallett * Multicast Event TX Control 2151215976Sjmallett * 2152215976Sjmallett * Notes: 2153215976Sjmallett * Writes to this register cause the SRIO device to generate a Multicast Event. Setting the MCE bit 2154215976Sjmallett * requests the logic to generate the Multicast Event Symbol. Reading the MCS bit shows the status 2155215976Sjmallett * of the transmit event. The hardware will clear the bit when the event has been transmitted and 2156215976Sjmallett * set the MCS_TX Interrupt. 2157215976Sjmallett * 2158232812Sjmallett * Clk_Rst: SRIO(0,2..3)_MCE_TX_CTL hclk hrst_n 2159215976Sjmallett */ 2160232812Sjmallettunion cvmx_sriox_mce_tx_ctl { 2161215976Sjmallett uint64_t u64; 2162232812Sjmallett struct cvmx_sriox_mce_tx_ctl_s { 2163232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2164215976Sjmallett uint64_t reserved_1_63 : 63; 2165215976Sjmallett uint64_t mce : 1; /**< Multicast Event Transmit. */ 2166215976Sjmallett#else 2167215976Sjmallett uint64_t mce : 1; 2168215976Sjmallett uint64_t reserved_1_63 : 63; 2169215976Sjmallett#endif 2170215976Sjmallett } s; 2171215976Sjmallett struct cvmx_sriox_mce_tx_ctl_s cn63xx; 2172215976Sjmallett struct cvmx_sriox_mce_tx_ctl_s cn63xxp1; 2173232812Sjmallett struct cvmx_sriox_mce_tx_ctl_s cn66xx; 2174215976Sjmallett}; 2175215976Sjmalletttypedef union cvmx_sriox_mce_tx_ctl cvmx_sriox_mce_tx_ctl_t; 2176215976Sjmallett 2177215976Sjmallett/** 2178215976Sjmallett * cvmx_srio#_mem_op_ctrl 2179215976Sjmallett * 2180215976Sjmallett * SRIO_MEM_OP_CTRL = SRIO Memory Operation Control 2181215976Sjmallett * 2182215976Sjmallett * The SRIO Memory Operation Control 2183215976Sjmallett * 2184215976Sjmallett * Notes: 2185215976Sjmallett * This register is used to control memory operations. Bits are provided to override the priority of 2186215976Sjmallett * the outgoing responses to memory operations. The memory operations with responses include NREAD, 2187215976Sjmallett * NWRITE_R, ATOMIC_INC, ATOMIC_DEC, ATOMIC_SET and ATOMIC_CLR. 2188215976Sjmallett * 2189232812Sjmallett * Clk_Rst: SRIO(0,2..3)_MEM_OP_CTRL hclk hrst_n 2190215976Sjmallett */ 2191232812Sjmallettunion cvmx_sriox_mem_op_ctrl { 2192215976Sjmallett uint64_t u64; 2193232812Sjmallett struct cvmx_sriox_mem_op_ctrl_s { 2194232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2195215976Sjmallett uint64_t reserved_10_63 : 54; 2196215976Sjmallett uint64_t rr_ro : 1; /**< Read Response Relaxed Ordering. Controls ordering 2197215976Sjmallett rules for incoming memory operations 2198215976Sjmallett 0 = Normal Ordering 2199215976Sjmallett 1 = Relaxed Ordering */ 2200215976Sjmallett uint64_t w_ro : 1; /**< Write Relaxed Ordering. Controls ordering rules 2201215976Sjmallett for incoming memory operations 2202215976Sjmallett 0 = Normal Ordering 2203215976Sjmallett 1 = Relaxed Ordering */ 2204215976Sjmallett uint64_t reserved_6_7 : 2; 2205215976Sjmallett uint64_t rp1_sid : 1; /**< Sets response priority for incomimg memory ops 2206215976Sjmallett of priority 1 on the secondary ID (0=2, 1=3) */ 2207215976Sjmallett uint64_t rp0_sid : 2; /**< Sets response priority for incomimg memory ops 2208215976Sjmallett of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */ 2209215976Sjmallett uint64_t rp1_pid : 1; /**< Sets response priority for incomimg memory ops 2210215976Sjmallett of priority 1 on the primary ID (0=2, 1=3) */ 2211215976Sjmallett uint64_t rp0_pid : 2; /**< Sets response priority for incomimg memory ops 2212215976Sjmallett of priority 0 on the primary ID (0,1=1 2=2, 3=3) */ 2213215976Sjmallett#else 2214215976Sjmallett uint64_t rp0_pid : 2; 2215215976Sjmallett uint64_t rp1_pid : 1; 2216215976Sjmallett uint64_t rp0_sid : 2; 2217215976Sjmallett uint64_t rp1_sid : 1; 2218215976Sjmallett uint64_t reserved_6_7 : 2; 2219215976Sjmallett uint64_t w_ro : 1; 2220215976Sjmallett uint64_t rr_ro : 1; 2221215976Sjmallett uint64_t reserved_10_63 : 54; 2222215976Sjmallett#endif 2223215976Sjmallett } s; 2224215976Sjmallett struct cvmx_sriox_mem_op_ctrl_s cn63xx; 2225215976Sjmallett struct cvmx_sriox_mem_op_ctrl_s cn63xxp1; 2226232812Sjmallett struct cvmx_sriox_mem_op_ctrl_s cn66xx; 2227215976Sjmallett}; 2228215976Sjmalletttypedef union cvmx_sriox_mem_op_ctrl cvmx_sriox_mem_op_ctrl_t; 2229215976Sjmallett 2230215976Sjmallett/** 2231215976Sjmallett * cvmx_srio#_omsg_ctrl# 2232215976Sjmallett * 2233215976Sjmallett * SRIO_OMSG_CTRLX = SRIO Outbound Message Control 2234215976Sjmallett * 2235215976Sjmallett * The SRIO Controller X Outbound Message Control Register 2236215976Sjmallett * 2237215976Sjmallett * Notes: 2238215976Sjmallett * 1) If IDM_TT, IDM_SIS, and IDM_DID are all clear, then the "ID match" will always be false. 2239215976Sjmallett * 2) LTTR_SP and LTTR_MP must be non-zero at all times, otherwise the message output queue can 2240215976Sjmallett * get blocked 2241215976Sjmallett * 3) TESTMODE has no function on controller 1 2242215976Sjmallett * 4) When IDM_TT=0, it is possible for an ID match to match an 8-bit DID with a 16-bit DID - SRIO 2243215976Sjmallett * zero-extends all 8-bit DID's, and the DID comparisons are always 16-bits. 2244215976Sjmallett * 2245232812Sjmallett * Clk_Rst: SRIO(0,2..3)_OMSG_CTRL[0:1] hclk hrst_n 2246215976Sjmallett */ 2247232812Sjmallettunion cvmx_sriox_omsg_ctrlx { 2248215976Sjmallett uint64_t u64; 2249232812Sjmallett struct cvmx_sriox_omsg_ctrlx_s { 2250232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2251215976Sjmallett uint64_t testmode : 1; /**< Controller X test mode (keep as RSVD in HRM) */ 2252215976Sjmallett uint64_t reserved_37_62 : 26; 2253215976Sjmallett uint64_t silo_max : 5; /**< Sets max number outgoing segments for controller X 2254232812Sjmallett Valid range is 0x01 .. 0x10 Note that lower 2255232812Sjmallett values will reduce bandwidth. */ 2256215976Sjmallett uint64_t rtry_thr : 16; /**< Controller X Retry threshold */ 2257215976Sjmallett uint64_t rtry_en : 1; /**< Controller X Retry threshold enable */ 2258215976Sjmallett uint64_t reserved_11_14 : 4; 2259215976Sjmallett uint64_t idm_tt : 1; /**< Controller X ID match includes TT ID */ 2260215976Sjmallett uint64_t idm_sis : 1; /**< Controller X ID match includes SIS */ 2261215976Sjmallett uint64_t idm_did : 1; /**< Controller X ID match includes DID */ 2262215976Sjmallett uint64_t lttr_sp : 4; /**< Controller X SP allowable letters in dynamic 2263215976Sjmallett letter select mode (LNS) */ 2264215976Sjmallett uint64_t lttr_mp : 4; /**< Controller X MP allowable letters in dynamic 2265215976Sjmallett letter select mode (LNS) */ 2266215976Sjmallett#else 2267215976Sjmallett uint64_t lttr_mp : 4; 2268215976Sjmallett uint64_t lttr_sp : 4; 2269215976Sjmallett uint64_t idm_did : 1; 2270215976Sjmallett uint64_t idm_sis : 1; 2271215976Sjmallett uint64_t idm_tt : 1; 2272215976Sjmallett uint64_t reserved_11_14 : 4; 2273215976Sjmallett uint64_t rtry_en : 1; 2274215976Sjmallett uint64_t rtry_thr : 16; 2275215976Sjmallett uint64_t silo_max : 5; 2276215976Sjmallett uint64_t reserved_37_62 : 26; 2277215976Sjmallett uint64_t testmode : 1; 2278215976Sjmallett#endif 2279215976Sjmallett } s; 2280215976Sjmallett struct cvmx_sriox_omsg_ctrlx_s cn63xx; 2281232812Sjmallett struct cvmx_sriox_omsg_ctrlx_cn63xxp1 { 2282232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2283215976Sjmallett uint64_t testmode : 1; /**< Controller X test mode (keep as RSVD in HRM) */ 2284215976Sjmallett uint64_t reserved_32_62 : 31; 2285215976Sjmallett uint64_t rtry_thr : 16; /**< Controller X Retry threshold */ 2286215976Sjmallett uint64_t rtry_en : 1; /**< Controller X Retry threshold enable */ 2287215976Sjmallett uint64_t reserved_11_14 : 4; 2288215976Sjmallett uint64_t idm_tt : 1; /**< Controller X ID match includes TT ID */ 2289215976Sjmallett uint64_t idm_sis : 1; /**< Controller X ID match includes SIS */ 2290215976Sjmallett uint64_t idm_did : 1; /**< Controller X ID match includes DID */ 2291215976Sjmallett uint64_t lttr_sp : 4; /**< Controller X SP allowable letters in dynamic 2292215976Sjmallett letter select mode (LNS) */ 2293215976Sjmallett uint64_t lttr_mp : 4; /**< Controller X MP allowable letters in dynamic 2294215976Sjmallett letter select mode (LNS) */ 2295215976Sjmallett#else 2296215976Sjmallett uint64_t lttr_mp : 4; 2297215976Sjmallett uint64_t lttr_sp : 4; 2298215976Sjmallett uint64_t idm_did : 1; 2299215976Sjmallett uint64_t idm_sis : 1; 2300215976Sjmallett uint64_t idm_tt : 1; 2301215976Sjmallett uint64_t reserved_11_14 : 4; 2302215976Sjmallett uint64_t rtry_en : 1; 2303215976Sjmallett uint64_t rtry_thr : 16; 2304215976Sjmallett uint64_t reserved_32_62 : 31; 2305215976Sjmallett uint64_t testmode : 1; 2306215976Sjmallett#endif 2307215976Sjmallett } cn63xxp1; 2308232812Sjmallett struct cvmx_sriox_omsg_ctrlx_s cn66xx; 2309215976Sjmallett}; 2310215976Sjmalletttypedef union cvmx_sriox_omsg_ctrlx cvmx_sriox_omsg_ctrlx_t; 2311215976Sjmallett 2312215976Sjmallett/** 2313215976Sjmallett * cvmx_srio#_omsg_done_counts# 2314215976Sjmallett * 2315232812Sjmallett * SRIO_OMSG_DONE_COUNTSX = SRIO Outbound Message Complete Counts 2316215976Sjmallett * 2317215976Sjmallett * The SRIO Controller X Outbound Message Complete Counts Register 2318215976Sjmallett * 2319215976Sjmallett * Notes: 2320215976Sjmallett * This register shows the number of successful and unsuccessful Outgoing Messages issued through 2321215976Sjmallett * this controller. The only messages considered are the ones with the INT field set in the PKO 2322215976Sjmallett * message header. This register is typically not written while Outbound SRIO Memory traffic is 2323215976Sjmallett * enabled. The sum of the GOOD and BAD counts should equal the number of messages sent unless 2324215976Sjmallett * the MAC has been reset. 2325215976Sjmallett * 2326232812Sjmallett * Clk_Rst: SRIO(0,2..3)_OMSG_DONE_COUNTS[0:1] hclk hrst_n 2327215976Sjmallett */ 2328232812Sjmallettunion cvmx_sriox_omsg_done_countsx { 2329215976Sjmallett uint64_t u64; 2330232812Sjmallett struct cvmx_sriox_omsg_done_countsx_s { 2331232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2332215976Sjmallett uint64_t reserved_32_63 : 32; 2333215976Sjmallett uint64_t bad : 16; /**< Number of Outbound Messages requesting an INT that 2334215976Sjmallett did not increment GOOD. (One or more segment of the 2335215976Sjmallett message either timed out, reached the retry limit, 2336215976Sjmallett or received an ERROR response.) */ 2337215976Sjmallett uint64_t good : 16; /**< Number of Outbound Messages requesting an INT that 2338215976Sjmallett received a DONE response for every segment. */ 2339215976Sjmallett#else 2340215976Sjmallett uint64_t good : 16; 2341215976Sjmallett uint64_t bad : 16; 2342215976Sjmallett uint64_t reserved_32_63 : 32; 2343215976Sjmallett#endif 2344215976Sjmallett } s; 2345215976Sjmallett struct cvmx_sriox_omsg_done_countsx_s cn63xx; 2346232812Sjmallett struct cvmx_sriox_omsg_done_countsx_s cn66xx; 2347215976Sjmallett}; 2348215976Sjmalletttypedef union cvmx_sriox_omsg_done_countsx cvmx_sriox_omsg_done_countsx_t; 2349215976Sjmallett 2350215976Sjmallett/** 2351215976Sjmallett * cvmx_srio#_omsg_fmp_mr# 2352215976Sjmallett * 2353215976Sjmallett * SRIO_OMSG_FMP_MRX = SRIO Outbound Message FIRSTMP Message Restriction 2354215976Sjmallett * 2355215976Sjmallett * The SRIO Controller X Outbound Message FIRSTMP Message Restriction Register 2356215976Sjmallett * 2357215976Sjmallett * Notes: 2358215976Sjmallett * This CSR controls when FMP candidate message segments (from the two different controllers) can enter 2359215976Sjmallett * the message segment silo to be sent out. A segment remains in the silo until after is has 2360215976Sjmallett * been transmitted and either acknowledged or errored out. 2361215976Sjmallett * 2362215976Sjmallett * Candidates and silo entries are one of 4 types: 2363215976Sjmallett * SP - a single-segment message 2364215976Sjmallett * FMP - the first segment of a multi-segment message 2365215976Sjmallett * NMP - the other segments in a multi-segment message 2366215976Sjmallett * PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing 2367215976Sjmallett * a multi-segment message into the silo and can match against segments generated by 2368215976Sjmallett * the other controller 2369215976Sjmallett * 2370215976Sjmallett * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo. 2371215976Sjmallett * By default (i.e. zeroes in this CSR), the FMP candidate matches against all entries in the 2372215976Sjmallett * silo. When fields in this CSR are set, FMP candidate segments will match fewer silo entries and 2373215976Sjmallett * can enter the silo more freely, probably providing better performance. 2374215976Sjmallett * 2375232812Sjmallett * Clk_Rst: SRIO(0,2..3)_OMSG_FMP_MR[0:1] hclk hrst_n 2376215976Sjmallett */ 2377232812Sjmallettunion cvmx_sriox_omsg_fmp_mrx { 2378215976Sjmallett uint64_t u64; 2379232812Sjmallett struct cvmx_sriox_omsg_fmp_mrx_s { 2380232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2381215976Sjmallett uint64_t reserved_15_63 : 49; 2382215976Sjmallett uint64_t ctlr_sp : 1; /**< Controller X FIRSTMP enable controller SP 2383215976Sjmallett When set, the FMP candidate message segment can 2384215976Sjmallett only match siloed SP segments that were created 2385215976Sjmallett by the same controller. When clear, this FMP-SP 2386215976Sjmallett match can also occur when the segments were 2387215976Sjmallett created by the other controller. 2388215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2389215976Sjmallett uint64_t ctlr_fmp : 1; /**< Controller X FIRSTMP enable controller FIRSTMP 2390215976Sjmallett When set, the FMP candidate message segment can 2391215976Sjmallett only match siloed FMP segments that were created 2392215976Sjmallett by the same controller. When clear, this FMP-FMP 2393215976Sjmallett match can also occur when the segments were 2394215976Sjmallett created by the other controller. 2395215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2396215976Sjmallett uint64_t ctlr_nmp : 1; /**< Controller X FIRSTMP enable controller NFIRSTMP 2397215976Sjmallett When set, the FMP candidate message segment can 2398215976Sjmallett only match siloed NMP segments that were created 2399215976Sjmallett by the same controller. When clear, this FMP-NMP 2400215976Sjmallett match can also occur when the segments were 2401215976Sjmallett created by the other controller. 2402215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2403215976Sjmallett uint64_t id_sp : 1; /**< Controller X FIRSTMP enable ID SP 2404215976Sjmallett When set, the FMP candidate message segment can 2405215976Sjmallett only match siloed SP segments that "ID match" the 2406215976Sjmallett candidate. When clear, this FMP-SP match can occur 2407215976Sjmallett with any ID values. 2408215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2409215976Sjmallett uint64_t id_fmp : 1; /**< Controller X FIRSTMP enable ID FIRSTMP 2410215976Sjmallett When set, the FMP candidate message segment can 2411215976Sjmallett only match siloed FMP segments that "ID match" the 2412215976Sjmallett candidate. When clear, this FMP-FMP match can occur 2413215976Sjmallett with any ID values. 2414215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2415215976Sjmallett uint64_t id_nmp : 1; /**< Controller X FIRSTMP enable ID NFIRSTMP 2416215976Sjmallett When set, the FMP candidate message segment can 2417215976Sjmallett only match siloed NMP segments that "ID match" the 2418215976Sjmallett candidate. When clear, this FMP-NMP match can occur 2419215976Sjmallett with any ID values. 2420215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2421215976Sjmallett uint64_t id_psd : 1; /**< Controller X FIRSTMP enable ID PSEUDO 2422215976Sjmallett When set, the FMP candidate message segment can 2423215976Sjmallett only match the silo pseudo (for the other 2424215976Sjmallett controller) when it is an "ID match". When clear, 2425215976Sjmallett this FMP-PSD match can occur with any ID values. 2426215976Sjmallett Not used by the hardware when ALL_PSD is set. */ 2427215976Sjmallett uint64_t mbox_sp : 1; /**< Controller X FIRSTMP enable MBOX SP 2428215976Sjmallett When set, the FMP candidate message segment can 2429215976Sjmallett only match siloed SP segments with the same 2-bit 2430215976Sjmallett mbox value as the candidate. When clear, this 2431215976Sjmallett FMP-SP match can occur with any mbox values. 2432215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2433215976Sjmallett uint64_t mbox_fmp : 1; /**< Controller X FIRSTMP enable MBOX FIRSTMP 2434215976Sjmallett When set, the FMP candidate message segment can 2435215976Sjmallett only match siloed FMP segments with the same 2-bit 2436215976Sjmallett mbox value as the candidate. When clear, this 2437215976Sjmallett FMP-FMP match can occur with any mbox values. 2438215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2439215976Sjmallett uint64_t mbox_nmp : 1; /**< Controller X FIRSTMP enable MBOX NFIRSTMP 2440215976Sjmallett When set, the FMP candidate message segment can 2441215976Sjmallett only match siloed NMP segments with the same 2-bit 2442215976Sjmallett mbox value as the candidate. When clear, this 2443215976Sjmallett FMP-NMP match can occur with any mbox values. 2444215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2445215976Sjmallett uint64_t mbox_psd : 1; /**< Controller X FIRSTMP enable MBOX PSEUDO 2446215976Sjmallett When set, the FMP candidate message segment can 2447215976Sjmallett only match the silo pseudo (for the other 2448215976Sjmallett controller) if the pseudo has the same 2-bit mbox 2449215976Sjmallett value as the candidate. When clear, this FMP-PSD 2450215976Sjmallett match can occur with any mbox values. 2451215976Sjmallett Not used by the hardware when ALL_PSD is set. */ 2452215976Sjmallett uint64_t all_sp : 1; /**< Controller X FIRSTMP enable all SP 2453215976Sjmallett When set, no FMP candidate message segments ever 2454215976Sjmallett match siloed SP segments and ID_SP 2455215976Sjmallett and MBOX_SP are not used. When clear, FMP-SP 2456215976Sjmallett matches can occur. */ 2457215976Sjmallett uint64_t all_fmp : 1; /**< Controller X FIRSTMP enable all FIRSTMP 2458215976Sjmallett When set, no FMP candidate message segments ever 2459215976Sjmallett match siloed FMP segments and ID_FMP and MBOX_FMP 2460215976Sjmallett are not used. When clear, FMP-FMP matches can 2461215976Sjmallett occur. */ 2462215976Sjmallett uint64_t all_nmp : 1; /**< Controller X FIRSTMP enable all NFIRSTMP 2463215976Sjmallett When set, no FMP candidate message segments ever 2464215976Sjmallett match siloed NMP segments and ID_NMP and MBOX_NMP 2465215976Sjmallett are not used. When clear, FMP-NMP matches can 2466215976Sjmallett occur. */ 2467215976Sjmallett uint64_t all_psd : 1; /**< Controller X FIRSTMP enable all PSEUDO 2468215976Sjmallett When set, no FMP candidate message segments ever 2469215976Sjmallett match the silo pseudo (for the other controller) 2470215976Sjmallett and ID_PSD and MBOX_PSD are not used. When clear, 2471215976Sjmallett FMP-PSD matches can occur. */ 2472215976Sjmallett#else 2473215976Sjmallett uint64_t all_psd : 1; 2474215976Sjmallett uint64_t all_nmp : 1; 2475215976Sjmallett uint64_t all_fmp : 1; 2476215976Sjmallett uint64_t all_sp : 1; 2477215976Sjmallett uint64_t mbox_psd : 1; 2478215976Sjmallett uint64_t mbox_nmp : 1; 2479215976Sjmallett uint64_t mbox_fmp : 1; 2480215976Sjmallett uint64_t mbox_sp : 1; 2481215976Sjmallett uint64_t id_psd : 1; 2482215976Sjmallett uint64_t id_nmp : 1; 2483215976Sjmallett uint64_t id_fmp : 1; 2484215976Sjmallett uint64_t id_sp : 1; 2485215976Sjmallett uint64_t ctlr_nmp : 1; 2486215976Sjmallett uint64_t ctlr_fmp : 1; 2487215976Sjmallett uint64_t ctlr_sp : 1; 2488215976Sjmallett uint64_t reserved_15_63 : 49; 2489215976Sjmallett#endif 2490215976Sjmallett } s; 2491215976Sjmallett struct cvmx_sriox_omsg_fmp_mrx_s cn63xx; 2492215976Sjmallett struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1; 2493232812Sjmallett struct cvmx_sriox_omsg_fmp_mrx_s cn66xx; 2494215976Sjmallett}; 2495215976Sjmalletttypedef union cvmx_sriox_omsg_fmp_mrx cvmx_sriox_omsg_fmp_mrx_t; 2496215976Sjmallett 2497215976Sjmallett/** 2498215976Sjmallett * cvmx_srio#_omsg_nmp_mr# 2499215976Sjmallett * 2500215976Sjmallett * SRIO_OMSG_NMP_MRX = SRIO Outbound Message NFIRSTMP Message Restriction 2501215976Sjmallett * 2502215976Sjmallett * The SRIO Controller X Outbound Message NFIRSTMP Message Restriction Register 2503215976Sjmallett * 2504215976Sjmallett * Notes: 2505215976Sjmallett * This CSR controls when NMP candidate message segments (from the two different controllers) can enter 2506215976Sjmallett * the message segment silo to be sent out. A segment remains in the silo until after is has 2507215976Sjmallett * been transmitted and either acknowledged or errored out. 2508215976Sjmallett * 2509215976Sjmallett * Candidates and silo entries are one of 4 types: 2510215976Sjmallett * SP - a single-segment message 2511215976Sjmallett * FMP - the first segment of a multi-segment message 2512215976Sjmallett * NMP - the other segments in a multi-segment message 2513215976Sjmallett * PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing 2514215976Sjmallett * a multi-segment message into the silo and can match against segments generated by 2515215976Sjmallett * the other controller 2516215976Sjmallett * 2517215976Sjmallett * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo. 2518215976Sjmallett * By default (i.e. zeroes in this CSR), the NMP candidate matches against all entries in the 2519215976Sjmallett * silo. When fields in this CSR are set, NMP candidate segments will match fewer silo entries and 2520215976Sjmallett * can enter the silo more freely, probably providing better performance. 2521215976Sjmallett * 2522232812Sjmallett * Clk_Rst: SRIO(0,2..3)_OMSG_NMP_MR[0:1] hclk hrst_n 2523215976Sjmallett */ 2524232812Sjmallettunion cvmx_sriox_omsg_nmp_mrx { 2525215976Sjmallett uint64_t u64; 2526232812Sjmallett struct cvmx_sriox_omsg_nmp_mrx_s { 2527232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2528215976Sjmallett uint64_t reserved_15_63 : 49; 2529215976Sjmallett uint64_t ctlr_sp : 1; /**< Controller X NFIRSTMP enable controller SP 2530215976Sjmallett When set, the NMP candidate message segment can 2531215976Sjmallett only match siloed SP segments that were created 2532215976Sjmallett by the same controller. When clear, this NMP-SP 2533215976Sjmallett match can also occur when the segments were 2534215976Sjmallett created by the other controller. 2535215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2536215976Sjmallett uint64_t ctlr_fmp : 1; /**< Controller X NFIRSTMP enable controller FIRSTMP 2537215976Sjmallett When set, the NMP candidate message segment can 2538215976Sjmallett only match siloed FMP segments that were created 2539215976Sjmallett by the same controller. When clear, this NMP-FMP 2540215976Sjmallett match can also occur when the segments were 2541215976Sjmallett created by the other controller. 2542215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2543215976Sjmallett uint64_t ctlr_nmp : 1; /**< Controller X NFIRSTMP enable controller NFIRSTMP 2544215976Sjmallett When set, the NMP candidate message segment can 2545215976Sjmallett only match siloed NMP segments that were created 2546215976Sjmallett by the same controller. When clear, this NMP-NMP 2547215976Sjmallett match can also occur when the segments were 2548215976Sjmallett created by the other controller. 2549215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2550215976Sjmallett uint64_t id_sp : 1; /**< Controller X NFIRSTMP enable ID SP 2551215976Sjmallett When set, the NMP candidate message segment can 2552215976Sjmallett only match siloed SP segments that "ID match" the 2553215976Sjmallett candidate. When clear, this NMP-SP match can occur 2554215976Sjmallett with any ID values. 2555215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2556215976Sjmallett uint64_t id_fmp : 1; /**< Controller X NFIRSTMP enable ID FIRSTMP 2557215976Sjmallett When set, the NMP candidate message segment can 2558215976Sjmallett only match siloed FMP segments that "ID match" the 2559215976Sjmallett candidate. When clear, this NMP-FMP match can occur 2560215976Sjmallett with any ID values. 2561215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2562215976Sjmallett uint64_t id_nmp : 1; /**< Controller X NFIRSTMP enable ID NFIRSTMP 2563215976Sjmallett When set, the NMP candidate message segment can 2564215976Sjmallett only match siloed NMP segments that "ID match" the 2565215976Sjmallett candidate. When clear, this NMP-NMP match can occur 2566215976Sjmallett with any ID values. 2567215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2568215976Sjmallett uint64_t reserved_8_8 : 1; 2569215976Sjmallett uint64_t mbox_sp : 1; /**< Controller X NFIRSTMP enable MBOX SP 2570215976Sjmallett When set, the NMP candidate message segment can 2571215976Sjmallett only match siloed SP segments with the same 2-bit 2572215976Sjmallett mbox value as the candidate. When clear, this 2573215976Sjmallett NMP-SP match can occur with any mbox values. 2574215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2575215976Sjmallett uint64_t mbox_fmp : 1; /**< Controller X NFIRSTMP enable MBOX FIRSTMP 2576215976Sjmallett When set, the NMP candidate message segment can 2577215976Sjmallett only match siloed FMP segments with the same 2-bit 2578215976Sjmallett mbox value as the candidate. When clear, this 2579215976Sjmallett NMP-FMP match can occur with any mbox values. 2580215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2581215976Sjmallett uint64_t mbox_nmp : 1; /**< Controller X NFIRSTMP enable MBOX NFIRSTMP 2582215976Sjmallett When set, the NMP candidate message segment can 2583215976Sjmallett only match siloed NMP segments with the same 2-bit 2584215976Sjmallett mbox value as the candidate. When clear, this 2585215976Sjmallett NMP-NMP match can occur with any mbox values. 2586215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2587215976Sjmallett uint64_t reserved_4_4 : 1; 2588215976Sjmallett uint64_t all_sp : 1; /**< Controller X NFIRSTMP enable all SP 2589215976Sjmallett When set, no NMP candidate message segments ever 2590215976Sjmallett match siloed SP segments and ID_SP 2591215976Sjmallett and MBOX_SP are not used. When clear, NMP-SP 2592215976Sjmallett matches can occur. */ 2593215976Sjmallett uint64_t all_fmp : 1; /**< Controller X NFIRSTMP enable all FIRSTMP 2594215976Sjmallett When set, no NMP candidate message segments ever 2595215976Sjmallett match siloed FMP segments and ID_FMP and MBOX_FMP 2596215976Sjmallett are not used. When clear, NMP-FMP matches can 2597215976Sjmallett occur. */ 2598215976Sjmallett uint64_t all_nmp : 1; /**< Controller X NFIRSTMP enable all NFIRSTMP 2599215976Sjmallett When set, no NMP candidate message segments ever 2600215976Sjmallett match siloed NMP segments and ID_NMP and MBOX_NMP 2601215976Sjmallett are not used. When clear, NMP-NMP matches can 2602215976Sjmallett occur. */ 2603215976Sjmallett uint64_t reserved_0_0 : 1; 2604215976Sjmallett#else 2605215976Sjmallett uint64_t reserved_0_0 : 1; 2606215976Sjmallett uint64_t all_nmp : 1; 2607215976Sjmallett uint64_t all_fmp : 1; 2608215976Sjmallett uint64_t all_sp : 1; 2609215976Sjmallett uint64_t reserved_4_4 : 1; 2610215976Sjmallett uint64_t mbox_nmp : 1; 2611215976Sjmallett uint64_t mbox_fmp : 1; 2612215976Sjmallett uint64_t mbox_sp : 1; 2613215976Sjmallett uint64_t reserved_8_8 : 1; 2614215976Sjmallett uint64_t id_nmp : 1; 2615215976Sjmallett uint64_t id_fmp : 1; 2616215976Sjmallett uint64_t id_sp : 1; 2617215976Sjmallett uint64_t ctlr_nmp : 1; 2618215976Sjmallett uint64_t ctlr_fmp : 1; 2619215976Sjmallett uint64_t ctlr_sp : 1; 2620215976Sjmallett uint64_t reserved_15_63 : 49; 2621215976Sjmallett#endif 2622215976Sjmallett } s; 2623215976Sjmallett struct cvmx_sriox_omsg_nmp_mrx_s cn63xx; 2624215976Sjmallett struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1; 2625232812Sjmallett struct cvmx_sriox_omsg_nmp_mrx_s cn66xx; 2626215976Sjmallett}; 2627215976Sjmalletttypedef union cvmx_sriox_omsg_nmp_mrx cvmx_sriox_omsg_nmp_mrx_t; 2628215976Sjmallett 2629215976Sjmallett/** 2630215976Sjmallett * cvmx_srio#_omsg_port# 2631215976Sjmallett * 2632215976Sjmallett * SRIO_OMSG_PORTX = SRIO Outbound Message Port 2633215976Sjmallett * 2634215976Sjmallett * The SRIO Controller X Outbound Message Port Register 2635215976Sjmallett * 2636215976Sjmallett * Notes: 2637215976Sjmallett * PORT maps the PKO port to SRIO interface \# / controller X as follows: 2638215976Sjmallett * 2639232812Sjmallett * 000 == PKO port 40 2640232812Sjmallett * 001 == PKO port 41 2641232812Sjmallett * 010 == PKO port 42 2642232812Sjmallett * 011 == PKO port 43 2643232812Sjmallett * 100 == PKO port 44 2644232812Sjmallett * 101 == PKO port 45 2645232812Sjmallett * 110 == PKO port 46 2646232812Sjmallett * 111 == PKO port 47 2647215976Sjmallett * 2648215976Sjmallett * No two PORT fields among the enabled controllers (ENABLE == 1) may be set to the same value. 2649215976Sjmallett * The register is only reset during COLD boot. The register can be accessed/modified regardless of 2650232812Sjmallett * the value in SRIO(0,2..3)_STATUS_REG.ACCESS. 2651215976Sjmallett * 2652232812Sjmallett * Clk_Rst: SRIO(0,2..3)_OMSG_PORT[0:1] sclk srst_n 2653215976Sjmallett */ 2654232812Sjmallettunion cvmx_sriox_omsg_portx { 2655215976Sjmallett uint64_t u64; 2656232812Sjmallett struct cvmx_sriox_omsg_portx_s { 2657232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2658215976Sjmallett uint64_t reserved_32_63 : 32; 2659215976Sjmallett uint64_t enable : 1; /**< Controller X enable */ 2660232812Sjmallett uint64_t reserved_3_30 : 28; 2661232812Sjmallett uint64_t port : 3; /**< Controller X PKO port */ 2662232812Sjmallett#else 2663232812Sjmallett uint64_t port : 3; 2664232812Sjmallett uint64_t reserved_3_30 : 28; 2665232812Sjmallett uint64_t enable : 1; 2666232812Sjmallett uint64_t reserved_32_63 : 32; 2667232812Sjmallett#endif 2668232812Sjmallett } s; 2669232812Sjmallett struct cvmx_sriox_omsg_portx_cn63xx { 2670232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2671232812Sjmallett uint64_t reserved_32_63 : 32; 2672232812Sjmallett uint64_t enable : 1; /**< Controller X enable */ 2673215976Sjmallett uint64_t reserved_2_30 : 29; 2674215976Sjmallett uint64_t port : 2; /**< Controller X PKO port */ 2675215976Sjmallett#else 2676215976Sjmallett uint64_t port : 2; 2677215976Sjmallett uint64_t reserved_2_30 : 29; 2678215976Sjmallett uint64_t enable : 1; 2679215976Sjmallett uint64_t reserved_32_63 : 32; 2680215976Sjmallett#endif 2681232812Sjmallett } cn63xx; 2682232812Sjmallett struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1; 2683232812Sjmallett struct cvmx_sriox_omsg_portx_s cn66xx; 2684215976Sjmallett}; 2685215976Sjmalletttypedef union cvmx_sriox_omsg_portx cvmx_sriox_omsg_portx_t; 2686215976Sjmallett 2687215976Sjmallett/** 2688215976Sjmallett * cvmx_srio#_omsg_silo_thr 2689215976Sjmallett * 2690232812Sjmallett * SRIO_OMSG_SILO_THR = SRIO Outgoing Message SILO Thresholds 2691215976Sjmallett * 2692215976Sjmallett * The SRIO Outgoing Message SILO Thresholds 2693215976Sjmallett * 2694215976Sjmallett * Notes: 2695232812Sjmallett * Limits the number of Outgoing Message Segments in flight at a time. 2696215976Sjmallett * 2697232812Sjmallett * Clk_Rst: SRIO(0,2..3)_OMSG_SILO_THR hclk hrst_n 2698215976Sjmallett */ 2699232812Sjmallettunion cvmx_sriox_omsg_silo_thr { 2700215976Sjmallett uint64_t u64; 2701232812Sjmallett struct cvmx_sriox_omsg_silo_thr_s { 2702232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2703215976Sjmallett uint64_t reserved_5_63 : 59; 2704215976Sjmallett uint64_t tot_silo : 5; /**< Sets max number segments in flight for all 2705232812Sjmallett controllers. Valid range is 0x01 .. 0x10 but 2706232812Sjmallett lower values reduce bandwidth. */ 2707215976Sjmallett#else 2708215976Sjmallett uint64_t tot_silo : 5; 2709215976Sjmallett uint64_t reserved_5_63 : 59; 2710215976Sjmallett#endif 2711215976Sjmallett } s; 2712215976Sjmallett struct cvmx_sriox_omsg_silo_thr_s cn63xx; 2713232812Sjmallett struct cvmx_sriox_omsg_silo_thr_s cn66xx; 2714215976Sjmallett}; 2715215976Sjmalletttypedef union cvmx_sriox_omsg_silo_thr cvmx_sriox_omsg_silo_thr_t; 2716215976Sjmallett 2717215976Sjmallett/** 2718215976Sjmallett * cvmx_srio#_omsg_sp_mr# 2719215976Sjmallett * 2720215976Sjmallett * SRIO_OMSG_SP_MRX = SRIO Outbound Message SP Message Restriction 2721215976Sjmallett * 2722215976Sjmallett * The SRIO Controller X Outbound Message SP Message Restriction Register 2723215976Sjmallett * 2724215976Sjmallett * Notes: 2725215976Sjmallett * This CSR controls when SP candidate message segments (from the two different controllers) can enter 2726215976Sjmallett * the message segment silo to be sent out. A segment remains in the silo until after is has 2727215976Sjmallett * been transmitted and either acknowledged or errored out. 2728215976Sjmallett * 2729215976Sjmallett * Candidates and silo entries are one of 4 types: 2730215976Sjmallett * SP - a single-segment message 2731215976Sjmallett * FMP - the first segment of a multi-segment message 2732215976Sjmallett * NMP - the other segments in a multi-segment message 2733215976Sjmallett * PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing 2734215976Sjmallett * a multi-segment message into the silo and can match against segments generated by 2735215976Sjmallett * the other controller 2736215976Sjmallett * 2737215976Sjmallett * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo. 2738215976Sjmallett * By default (i.e. zeroes in this CSR), the SP candidate matches against all entries in the 2739215976Sjmallett * silo. When fields in this CSR are set, SP candidate segments will match fewer silo entries and 2740215976Sjmallett * can enter the silo more freely, probably providing better performance. 2741215976Sjmallett * 2742232812Sjmallett * Clk_Rst: SRIO(0,2..3)_OMSG_SP_MR[0:1] hclk hrst_n 2743215976Sjmallett */ 2744232812Sjmallettunion cvmx_sriox_omsg_sp_mrx { 2745215976Sjmallett uint64_t u64; 2746232812Sjmallett struct cvmx_sriox_omsg_sp_mrx_s { 2747232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2748215976Sjmallett uint64_t reserved_16_63 : 48; 2749215976Sjmallett uint64_t xmbox_sp : 1; /**< Controller X SP enable XMBOX SP 2750215976Sjmallett When set, the SP candidate message can only 2751215976Sjmallett match siloed SP segments with the same 4-bit xmbox 2752215976Sjmallett value as the candidate. When clear, this SP-SP 2753215976Sjmallett match can occur with any xmbox values. 2754215976Sjmallett When XMBOX_SP is set, MBOX_SP will commonly be set. 2755215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2756215976Sjmallett uint64_t ctlr_sp : 1; /**< Controller X SP enable controller SP 2757215976Sjmallett When set, the SP candidate message can 2758215976Sjmallett only match siloed SP segments that were created 2759215976Sjmallett by the same controller. When clear, this SP-SP 2760215976Sjmallett match can also occur when the segments were 2761215976Sjmallett created by the other controller. 2762215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2763215976Sjmallett uint64_t ctlr_fmp : 1; /**< Controller X SP enable controller FIRSTMP 2764215976Sjmallett When set, the SP candidate message can 2765215976Sjmallett only match siloed FMP segments that were created 2766215976Sjmallett by the same controller. When clear, this SP-FMP 2767215976Sjmallett match can also occur when the segments were 2768215976Sjmallett created by the other controller. 2769215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2770215976Sjmallett uint64_t ctlr_nmp : 1; /**< Controller X SP enable controller NFIRSTMP 2771215976Sjmallett When set, the SP candidate message can 2772215976Sjmallett only match siloed NMP segments that were created 2773215976Sjmallett by the same controller. When clear, this SP-NMP 2774215976Sjmallett match can also occur when the segments were 2775215976Sjmallett created by the other controller. 2776215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2777215976Sjmallett uint64_t id_sp : 1; /**< Controller X SP enable ID SP 2778215976Sjmallett When set, the SP candidate message can 2779215976Sjmallett only match siloed SP segments that "ID match" the 2780215976Sjmallett candidate. When clear, this SP-SP match can occur 2781215976Sjmallett with any ID values. 2782215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2783215976Sjmallett uint64_t id_fmp : 1; /**< Controller X SP enable ID FIRSTMP 2784215976Sjmallett When set, the SP candidate message can 2785215976Sjmallett only match siloed FMP segments that "ID match" the 2786215976Sjmallett candidate. When clear, this SP-FMP match can occur 2787215976Sjmallett with any ID values. 2788215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2789215976Sjmallett uint64_t id_nmp : 1; /**< Controller X SP enable ID NFIRSTMP 2790215976Sjmallett When set, the SP candidate message can 2791215976Sjmallett only match siloed NMP segments that "ID match" the 2792215976Sjmallett candidate. When clear, this SP-NMP match can occur 2793215976Sjmallett with any ID values. 2794215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2795215976Sjmallett uint64_t id_psd : 1; /**< Controller X SP enable ID PSEUDO 2796215976Sjmallett When set, the SP candidate message can 2797215976Sjmallett only match the silo pseudo (for the other 2798215976Sjmallett controller) when it is an "ID match". When clear, 2799215976Sjmallett this SP-PSD match can occur with any ID values. 2800215976Sjmallett Not used by the hardware when ALL_PSD is set. */ 2801215976Sjmallett uint64_t mbox_sp : 1; /**< Controller X SP enable MBOX SP 2802215976Sjmallett When set, the SP candidate message can only 2803215976Sjmallett match siloed SP segments with the same 2-bit mbox 2804215976Sjmallett value as the candidate. When clear, this SP-SP 2805215976Sjmallett match can occur with any mbox values. 2806215976Sjmallett Not used by the hardware when ALL_SP is set. */ 2807215976Sjmallett uint64_t mbox_fmp : 1; /**< Controller X SP enable MBOX FIRSTMP 2808215976Sjmallett When set, the SP candidate message can only 2809215976Sjmallett match siloed FMP segments with the same 2-bit mbox 2810215976Sjmallett value as the candidate. When clear, this SP-FMP 2811215976Sjmallett match can occur with any mbox values. 2812215976Sjmallett Not used by the hardware when ALL_FMP is set. */ 2813215976Sjmallett uint64_t mbox_nmp : 1; /**< Controller X SP enable MBOX NFIRSTMP 2814215976Sjmallett When set, the SP candidate message can only 2815215976Sjmallett match siloed NMP segments with the same 2-bit mbox 2816215976Sjmallett value as the candidate. When clear, this SP-NMP 2817215976Sjmallett match can occur with any mbox values. 2818215976Sjmallett Not used by the hardware when ALL_NMP is set. */ 2819215976Sjmallett uint64_t mbox_psd : 1; /**< Controller X SP enable MBOX PSEUDO 2820215976Sjmallett When set, the SP candidate message can only 2821215976Sjmallett match the silo pseudo (for the other controller) 2822215976Sjmallett if the pseudo has the same 2-bit mbox value as the 2823215976Sjmallett candidate. When clear, this SP-PSD match can occur 2824215976Sjmallett with any mbox values. 2825215976Sjmallett Not used by the hardware when ALL_PSD is set. */ 2826215976Sjmallett uint64_t all_sp : 1; /**< Controller X SP enable all SP 2827215976Sjmallett When set, no SP candidate messages ever 2828215976Sjmallett match siloed SP segments, and XMBOX_SP, ID_SP, 2829215976Sjmallett and MBOX_SP are not used. When clear, SP-SP 2830215976Sjmallett matches can occur. */ 2831215976Sjmallett uint64_t all_fmp : 1; /**< Controller X SP enable all FIRSTMP 2832215976Sjmallett When set, no SP candidate messages ever 2833215976Sjmallett match siloed FMP segments and ID_FMP and MBOX_FMP 2834215976Sjmallett are not used. When clear, SP-FMP matches can 2835215976Sjmallett occur. */ 2836215976Sjmallett uint64_t all_nmp : 1; /**< Controller X SP enable all NFIRSTMP 2837215976Sjmallett When set, no SP candidate messages ever 2838215976Sjmallett match siloed NMP segments and ID_NMP and MBOX_NMP 2839215976Sjmallett are not used. When clear, SP-NMP matches can 2840215976Sjmallett occur. */ 2841215976Sjmallett uint64_t all_psd : 1; /**< Controller X SP enable all PSEUDO 2842215976Sjmallett When set, no SP candidate messages ever 2843215976Sjmallett match the silo pseudo (for the other controller) 2844215976Sjmallett and ID_PSD and MBOX_PSD are not used. When clear, 2845215976Sjmallett SP-PSD matches can occur. */ 2846215976Sjmallett#else 2847215976Sjmallett uint64_t all_psd : 1; 2848215976Sjmallett uint64_t all_nmp : 1; 2849215976Sjmallett uint64_t all_fmp : 1; 2850215976Sjmallett uint64_t all_sp : 1; 2851215976Sjmallett uint64_t mbox_psd : 1; 2852215976Sjmallett uint64_t mbox_nmp : 1; 2853215976Sjmallett uint64_t mbox_fmp : 1; 2854215976Sjmallett uint64_t mbox_sp : 1; 2855215976Sjmallett uint64_t id_psd : 1; 2856215976Sjmallett uint64_t id_nmp : 1; 2857215976Sjmallett uint64_t id_fmp : 1; 2858215976Sjmallett uint64_t id_sp : 1; 2859215976Sjmallett uint64_t ctlr_nmp : 1; 2860215976Sjmallett uint64_t ctlr_fmp : 1; 2861215976Sjmallett uint64_t ctlr_sp : 1; 2862215976Sjmallett uint64_t xmbox_sp : 1; 2863215976Sjmallett uint64_t reserved_16_63 : 48; 2864215976Sjmallett#endif 2865215976Sjmallett } s; 2866215976Sjmallett struct cvmx_sriox_omsg_sp_mrx_s cn63xx; 2867215976Sjmallett struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1; 2868232812Sjmallett struct cvmx_sriox_omsg_sp_mrx_s cn66xx; 2869215976Sjmallett}; 2870215976Sjmalletttypedef union cvmx_sriox_omsg_sp_mrx cvmx_sriox_omsg_sp_mrx_t; 2871215976Sjmallett 2872215976Sjmallett/** 2873215976Sjmallett * cvmx_srio#_prio#_in_use 2874215976Sjmallett * 2875232812Sjmallett * SRIO_PRIO[0:3]_IN_USE = S2M PRIORITY FIFO IN USE COUNTS 2876215976Sjmallett * 2877215976Sjmallett * SRIO S2M Priority X FIFO Inuse counts 2878215976Sjmallett * 2879215976Sjmallett * Notes: 2880215976Sjmallett * These registers provide status information on the number of read/write requests pending in the S2M 2881215976Sjmallett * Priority FIFOs. The information can be used to help determine when an S2M_TYPE register can be 2882215976Sjmallett * reallocated. For example, if an S2M_TYPE is used N times in a DMA write operation and the DMA has 2883215976Sjmallett * completed. The register corresponding to the RD/WR_PRIOR of the S2M_TYPE can be read to determine 2884215976Sjmallett * the START_CNT and then can be polled to see if the END_CNT equals the START_CNT or at least 2885232812Sjmallett * START_CNT+N. These registers can be accessed regardless of the value of SRIO(0,2..3)_STATUS_REG.ACCESS 2886215976Sjmallett * but are reset by either the MAC or Core being reset. 2887215976Sjmallett * 2888232812Sjmallett * Clk_Rst: SRIO(0,2..3)_PRIO[0:3]_IN_USE sclk srst_n, hrst_n 2889215976Sjmallett */ 2890232812Sjmallettunion cvmx_sriox_priox_in_use { 2891215976Sjmallett uint64_t u64; 2892232812Sjmallett struct cvmx_sriox_priox_in_use_s { 2893232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2894215976Sjmallett uint64_t reserved_32_63 : 32; 2895215976Sjmallett uint64_t end_cnt : 16; /**< Count of Packets with S2M_TYPES completed for this 2896215976Sjmallett Priority X FIFO */ 2897215976Sjmallett uint64_t start_cnt : 16; /**< Count of Packets with S2M_TYPES started for this 2898215976Sjmallett Priority X FIFO */ 2899215976Sjmallett#else 2900215976Sjmallett uint64_t start_cnt : 16; 2901215976Sjmallett uint64_t end_cnt : 16; 2902215976Sjmallett uint64_t reserved_32_63 : 32; 2903215976Sjmallett#endif 2904215976Sjmallett } s; 2905215976Sjmallett struct cvmx_sriox_priox_in_use_s cn63xx; 2906232812Sjmallett struct cvmx_sriox_priox_in_use_s cn66xx; 2907215976Sjmallett}; 2908215976Sjmalletttypedef union cvmx_sriox_priox_in_use cvmx_sriox_priox_in_use_t; 2909215976Sjmallett 2910215976Sjmallett/** 2911215976Sjmallett * cvmx_srio#_rx_bell 2912215976Sjmallett * 2913215976Sjmallett * SRIO_RX_BELL = SRIO Receive Doorbell 2914215976Sjmallett * 2915215976Sjmallett * The SRIO Incoming (RX) Doorbell 2916215976Sjmallett * 2917215976Sjmallett * Notes: 2918215976Sjmallett * This register contains the SRIO Information, Device ID, Transaction Type and Priority of the 2919215976Sjmallett * incoming Doorbell Transaction as well as the number of transactions waiting to be read. Reading 2920215976Sjmallett * this register causes a Doorbell to be removed from the RX Bell FIFO and the COUNT to be 2921215976Sjmallett * decremented. If the COUNT is zero then the FIFO is empty and the other fields should be 2922215976Sjmallett * considered invalid. When the FIFO is full an ERROR is automatically issued. The RXBELL Interrupt 2923215976Sjmallett * can be used to detect posts to this FIFO. 2924215976Sjmallett * 2925232812Sjmallett * Clk_Rst: SRIO(0,2..3)_RX_BELL hclk hrst_n 2926215976Sjmallett */ 2927232812Sjmallettunion cvmx_sriox_rx_bell { 2928215976Sjmallett uint64_t u64; 2929232812Sjmallett struct cvmx_sriox_rx_bell_s { 2930232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2931215976Sjmallett uint64_t reserved_48_63 : 16; 2932215976Sjmallett uint64_t data : 16; /**< Information field from received doorbell */ 2933215976Sjmallett uint64_t src_id : 16; /**< Doorbell Source Device ID[15:0] */ 2934215976Sjmallett uint64_t count : 8; /**< RX Bell FIFO Count 2935215976Sjmallett Note: Count must be > 0 for entry to be valid. */ 2936215976Sjmallett uint64_t reserved_5_7 : 3; 2937215976Sjmallett uint64_t dest_id : 1; /**< Destination Device ID 0=Primary, 1=Secondary */ 2938215976Sjmallett uint64_t id16 : 1; /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */ 2939215976Sjmallett uint64_t reserved_2_2 : 1; 2940215976Sjmallett uint64_t priority : 2; /**< Doorbell Priority */ 2941215976Sjmallett#else 2942215976Sjmallett uint64_t priority : 2; 2943215976Sjmallett uint64_t reserved_2_2 : 1; 2944215976Sjmallett uint64_t id16 : 1; 2945215976Sjmallett uint64_t dest_id : 1; 2946215976Sjmallett uint64_t reserved_5_7 : 3; 2947215976Sjmallett uint64_t count : 8; 2948215976Sjmallett uint64_t src_id : 16; 2949215976Sjmallett uint64_t data : 16; 2950215976Sjmallett uint64_t reserved_48_63 : 16; 2951215976Sjmallett#endif 2952215976Sjmallett } s; 2953215976Sjmallett struct cvmx_sriox_rx_bell_s cn63xx; 2954215976Sjmallett struct cvmx_sriox_rx_bell_s cn63xxp1; 2955232812Sjmallett struct cvmx_sriox_rx_bell_s cn66xx; 2956215976Sjmallett}; 2957215976Sjmalletttypedef union cvmx_sriox_rx_bell cvmx_sriox_rx_bell_t; 2958215976Sjmallett 2959215976Sjmallett/** 2960215976Sjmallett * cvmx_srio#_rx_bell_seq 2961215976Sjmallett * 2962215976Sjmallett * SRIO_RX_BELL_SEQ = SRIO Receive Doorbell Sequence Count 2963215976Sjmallett * 2964215976Sjmallett * The SRIO Incoming (RX) Doorbell Sequence Count 2965215976Sjmallett * 2966215976Sjmallett * Notes: 2967215976Sjmallett * This register contains the value of the sequence counter when the doorbell was received and a 2968215976Sjmallett * shadow copy of the Bell FIFO Count that can be read without emptying the FIFO. This register must 2969232812Sjmallett * be read prior to SRIO(0,2..3)_RX_BELL to guarantee that the information corresponds to the correct 2970215976Sjmallett * doorbell. 2971215976Sjmallett * 2972232812Sjmallett * Clk_Rst: SRIO(0,2..3)_RX_BELL_SEQ hclk hrst_n 2973215976Sjmallett */ 2974232812Sjmallettunion cvmx_sriox_rx_bell_seq { 2975215976Sjmallett uint64_t u64; 2976232812Sjmallett struct cvmx_sriox_rx_bell_seq_s { 2977232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2978215976Sjmallett uint64_t reserved_40_63 : 24; 2979215976Sjmallett uint64_t count : 8; /**< RX Bell FIFO Count 2980215976Sjmallett Note: Count must be > 0 for entry to be valid. */ 2981215976Sjmallett uint64_t seq : 32; /**< 32-bit Sequence \# associated with Doorbell Message */ 2982215976Sjmallett#else 2983215976Sjmallett uint64_t seq : 32; 2984215976Sjmallett uint64_t count : 8; 2985215976Sjmallett uint64_t reserved_40_63 : 24; 2986215976Sjmallett#endif 2987215976Sjmallett } s; 2988215976Sjmallett struct cvmx_sriox_rx_bell_seq_s cn63xx; 2989215976Sjmallett struct cvmx_sriox_rx_bell_seq_s cn63xxp1; 2990232812Sjmallett struct cvmx_sriox_rx_bell_seq_s cn66xx; 2991215976Sjmallett}; 2992215976Sjmalletttypedef union cvmx_sriox_rx_bell_seq cvmx_sriox_rx_bell_seq_t; 2993215976Sjmallett 2994215976Sjmallett/** 2995215976Sjmallett * cvmx_srio#_rx_status 2996215976Sjmallett * 2997215976Sjmallett * SRIO_RX_STATUS = SRIO Inbound Credits/Response Status 2998215976Sjmallett * 2999215976Sjmallett * Specifies the current number of credits/responses by SRIO for Inbound Traffic 3000215976Sjmallett * 3001215976Sjmallett * Notes: 3002215976Sjmallett * Debug Register specifying the number of credits/responses currently in use for Inbound Traffic. 3003232812Sjmallett * The maximum value for COMP, N_POST and POST is set in SRIO(0,2..3)_TLP_CREDITS. When all inbound traffic 3004215976Sjmallett * has stopped the values should eventually return to the maximum values. The RTN_PR[3:1] entry 3005215976Sjmallett * counts should eventually return to the reset values. 3006215976Sjmallett * 3007232812Sjmallett * Clk_Rst: SRIO(0,2..3)_RX_STATUS hclk hrst_n 3008215976Sjmallett */ 3009232812Sjmallettunion cvmx_sriox_rx_status { 3010215976Sjmallett uint64_t u64; 3011232812Sjmallett struct cvmx_sriox_rx_status_s { 3012232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3013215976Sjmallett uint64_t rtn_pr3 : 8; /**< Number of pending Priority 3 Response Entries. */ 3014215976Sjmallett uint64_t rtn_pr2 : 8; /**< Number of pending Priority 2 Response Entries. */ 3015215976Sjmallett uint64_t rtn_pr1 : 8; /**< Number of pending Priority 1 Response Entries. */ 3016215976Sjmallett uint64_t reserved_28_39 : 12; 3017215976Sjmallett uint64_t mbox : 4; /**< Credits for Mailbox Data used in M2S. */ 3018215976Sjmallett uint64_t comp : 8; /**< Credits for Read Completions used in M2S. */ 3019215976Sjmallett uint64_t reserved_13_15 : 3; 3020215976Sjmallett uint64_t n_post : 5; /**< Credits for Read Requests used in M2S. */ 3021215976Sjmallett uint64_t post : 8; /**< Credits for Write Request Postings used in M2S. */ 3022215976Sjmallett#else 3023215976Sjmallett uint64_t post : 8; 3024215976Sjmallett uint64_t n_post : 5; 3025215976Sjmallett uint64_t reserved_13_15 : 3; 3026215976Sjmallett uint64_t comp : 8; 3027215976Sjmallett uint64_t mbox : 4; 3028215976Sjmallett uint64_t reserved_28_39 : 12; 3029215976Sjmallett uint64_t rtn_pr1 : 8; 3030215976Sjmallett uint64_t rtn_pr2 : 8; 3031215976Sjmallett uint64_t rtn_pr3 : 8; 3032215976Sjmallett#endif 3033215976Sjmallett } s; 3034215976Sjmallett struct cvmx_sriox_rx_status_s cn63xx; 3035215976Sjmallett struct cvmx_sriox_rx_status_s cn63xxp1; 3036232812Sjmallett struct cvmx_sriox_rx_status_s cn66xx; 3037215976Sjmallett}; 3038215976Sjmalletttypedef union cvmx_sriox_rx_status cvmx_sriox_rx_status_t; 3039215976Sjmallett 3040215976Sjmallett/** 3041215976Sjmallett * cvmx_srio#_s2m_type# 3042215976Sjmallett * 3043215976Sjmallett * SRIO_S2M_TYPE[0:15] = SLI to SRIO MAC Operation Type 3044215976Sjmallett * 3045215976Sjmallett * SRIO Operation Type selected by PP or DMA Accesses 3046215976Sjmallett * 3047215976Sjmallett * Notes: 3048215976Sjmallett * This CSR table specifies how to convert a SLI/DPI MAC read or write into sRIO operations. 3049215976Sjmallett * Each SLI/DPI read or write access supplies a 64-bit address (MACADD[63:0]), 2-bit ADDRTYPE, and 3050215976Sjmallett * 2-bit endian-swap. This SRIO*_S2M_TYPE* CSR description specifies a table with 16 CSRs. SRIO 3051215976Sjmallett * selects one of the table entries with TYPEIDX[3:0], which it creates from the SLI/DPI MAC memory 3052215976Sjmallett * space read or write as follows: 3053215976Sjmallett * TYPEIDX[1:0] = ADDRTYPE[1:0] (ADDRTYPE[1] is no-snoop to the PCIe MAC, 3054215976Sjmallett * ADDRTYPE[0] is relaxed-ordering to the PCIe MAC) 3055215976Sjmallett * TYPEIDX[2] = MACADD[50] 3056215976Sjmallett * TYPEIDX[3] = MACADD[59] 3057215976Sjmallett * 3058232812Sjmallett * Clk_Rst: SRIO(0,2..3)_S2M_TYPE[0:15] hclk hrst_n 3059215976Sjmallett */ 3060232812Sjmallettunion cvmx_sriox_s2m_typex { 3061215976Sjmallett uint64_t u64; 3062232812Sjmallett struct cvmx_sriox_s2m_typex_s { 3063232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3064215976Sjmallett uint64_t reserved_19_63 : 45; 3065215976Sjmallett uint64_t wr_op : 3; /**< sRIO operation for SLI/DPI writes 3066215976Sjmallett 3067215976Sjmallett SLI/DPI hardware break MAC memory space writes 3068215976Sjmallett that they generate into pieces of maximum size 3069215976Sjmallett 256B. For NWRITE/NWRITE_R/SWRITE WR_OP variants 3070215976Sjmallett below, SRIO will, if necessary to obey sRIO 3071215976Sjmallett requirements, automatically break the write into 3072215976Sjmallett even smaller writes. The same is not true for 3073215976Sjmallett MAINTENANCE writes and port-writes. Additional 3074215976Sjmallett SW/usage restrictions are required for these 3075215976Sjmallett MAINTENANCE WR_OP's to work correctly. SW must 3076215976Sjmallett restrict the alignment and length of DPI pointers, 3077215976Sjmallett limit the store sizes that the cores issue, and 3078215976Sjmallett possibly also set SLI_MEM_ACCESS_SUBID*[NMERGE] 3079215976Sjmallett so that all MAC memory space writes with 3080215976Sjmallett MAINTENANCE write and port-write WR_OP's can be 3081215976Sjmallett serviced in a single sRIO operation. 3082215976Sjmallett 3083215976Sjmallett SRIO always sends the write data (64-bit) words 3084215976Sjmallett out in order. 3085215976Sjmallett 3086215976Sjmallett WR_OP = 0 = Normal Write (NWRITE) 3087215976Sjmallett SRIO breaks a MAC memory space write into 3088215976Sjmallett the minimum number of required sRIO NWRITE 3089215976Sjmallett operations. This will be 1-5 total NWRITEs, 3090215976Sjmallett depending on endian-swap, alignment, and 3091215976Sjmallett length. 3092215976Sjmallett 3093215976Sjmallett WR_OP = 1 = Normal Write w/Response (NWRITE_R) 3094215976Sjmallett SRIO breaks a MAC memory space write into 3095215976Sjmallett the minimum number of required sRIO 3096215976Sjmallett NWRITE_R operations. This will be 1-5 total 3097215976Sjmallett NWRITE_R's, depending on endian-swap, 3098215976Sjmallett alignment, and length. 3099215976Sjmallett 3100215976Sjmallett SRIO sets SRIO*_INT_REG[WR_DONE] after it 3101215976Sjmallett receives the DONE response for the last 3102215976Sjmallett NWRITE_R sent. 3103215976Sjmallett 3104215976Sjmallett WR_OP = 2 = NWRITE, Streaming write (SWRITE), 3105215976Sjmallett NWRITE 3106215976Sjmallett SRIO attempts to turn the MAC memory space 3107215976Sjmallett write into an SWRITE operation. There will 3108215976Sjmallett be 1-5 total sRIO operations (0-2 NWRITE's 3109215976Sjmallett followed by 0-1 SWRITE's followed by 0-2 3110215976Sjmallett NWRITE's) generated to complete the MAC 3111215976Sjmallett memory space write, depending on 3112215976Sjmallett endian-swap, alignment, and length. 3113215976Sjmallett 3114215976Sjmallett If the starting address is not 64-bit 3115215976Sjmallett aligned, SRIO first creates 1-4 NWRITE's to 3116215976Sjmallett either align it or complete the write. Then 3117215976Sjmallett SRIO creates a SWRITE including all aligned 3118215976Sjmallett 64-bit words. (SRIO won't create an SWRITE 3119215976Sjmallett when there are none.) If store data 3120215976Sjmallett remains, SRIO finally creates another 1 or 3121215976Sjmallett 2 NWRITE's. 3122215976Sjmallett 3123215976Sjmallett WR_OP = 3 = NWRITE, SWRITE, NWRITE_R 3124215976Sjmallett SRIO attempts to turn the MAC memory space 3125215976Sjmallett write into an SWRITE operation followed by 3126215976Sjmallett a NWRITE_R operation. The last operation 3127215976Sjmallett is always NWRITE_R. There will be 1-5 3128215976Sjmallett total sRIO operations (0-2 NWRITE's, 3129215976Sjmallett followed by 0-1 SWRITE, followed by 1-4 3130215976Sjmallett NWRITE_R's) generated to service the MAC 3131215976Sjmallett memory space write, depending on 3132215976Sjmallett endian-swap, alignment, and length. 3133215976Sjmallett 3134215976Sjmallett If the write is contained in one aligned 3135215976Sjmallett 64-bit word, SRIO will completely service 3136215976Sjmallett the MAC memory space write with 1-4 3137215976Sjmallett NWRITE_R's. 3138215976Sjmallett 3139215976Sjmallett Otherwise, if the write spans multiple 3140215976Sjmallett words, SRIO services the write as follows. 3141215976Sjmallett First, if the start of the write is not 3142215976Sjmallett word-aligned, SRIO creates 1 or 2 NWRITE's 3143215976Sjmallett to align it. Then SRIO creates an SWRITE 3144215976Sjmallett that includes all aligned 64-bit words, 3145215976Sjmallett leaving data for the final NWRITE_R(s). 3146215976Sjmallett (SRIO won't create the SWRITE when there is 3147215976Sjmallett no data for it.) Then SRIO finally creates 3148215976Sjmallett 1 or 2 NWRITE_R's. 3149215976Sjmallett 3150215976Sjmallett In any case, SRIO sets 3151215976Sjmallett SRIO*_INT_REG[WR_DONE] after it receives 3152215976Sjmallett the DONE response for the last NWRITE_R 3153215976Sjmallett sent. 3154215976Sjmallett 3155215976Sjmallett WR_OP = 4 = NWRITE, NWRITE_R 3156215976Sjmallett SRIO attempts to turn the MAC memory space 3157215976Sjmallett write into an NWRITE operation followed by 3158215976Sjmallett a NWRITE_R operation. The last operation 3159215976Sjmallett is always NWRITE_R. There will be 1-5 3160215976Sjmallett total sRIO operations (0-3 NWRITE's 3161215976Sjmallett followed by 1-4 NWRITE_R's) generated to 3162215976Sjmallett service the MAC memory space write, 3163215976Sjmallett depending on endian-swap, alignment, and 3164215976Sjmallett length. 3165215976Sjmallett 3166215976Sjmallett If the write is contained in one aligned 3167215976Sjmallett 64-bit word, SRIO will completely service 3168215976Sjmallett the MAC memory space write with 1-4 3169215976Sjmallett NWRITE_R's. 3170215976Sjmallett 3171215976Sjmallett Otherwise, if the write spans multiple 3172215976Sjmallett words, SRIO services the write as follows. 3173215976Sjmallett First, if the start of the write is not 3174215976Sjmallett word-aligned, SRIO creates 1 or 2 NWRITE's 3175215976Sjmallett to align it. Then SRIO creates an NWRITE 3176215976Sjmallett that includes all aligned 64-bit words, 3177215976Sjmallett leaving data for the final NWRITE_R(s). 3178215976Sjmallett (SRIO won't create this NWRITE when there 3179215976Sjmallett is no data for it.) Then SRIO finally 3180215976Sjmallett creates 1 or 2 NWRITE_R's. 3181215976Sjmallett 3182215976Sjmallett In any case, SRIO sets 3183215976Sjmallett SRIO*_INT_REG[WR_DONE] after it receives 3184215976Sjmallett the DONE response for the last NWRITE_R 3185215976Sjmallett sent. 3186215976Sjmallett 3187215976Sjmallett WR_OP = 5 = Reserved 3188215976Sjmallett 3189215976Sjmallett WR_OP = 6 = Maintenance Write 3190215976Sjmallett - SRIO will create one sRIO MAINTENANCE write 3191215976Sjmallett operation to service the MAC memory space 3192215976Sjmallett write 3193215976Sjmallett - IAOW_SEL must be zero. (see description 3194215976Sjmallett below.) 3195215976Sjmallett - MDS must be zero. (MDS is MACADD[63:62] - 3196215976Sjmallett see IAOW_SEL description below.) 3197215976Sjmallett - Hop Cnt is MACADD[31:24]/SRIOAddress[31:24] 3198215976Sjmallett - MACADD[23:0]/SRIOAddress[23:0] selects 3199215976Sjmallett maintenance register (i.e. config_offset) 3200215976Sjmallett - sRIODestID[15:0] is MACADD[49:34]. 3201215976Sjmallett (MACADD[49:42] unused when ID16=0) 3202215976Sjmallett - Write size/alignment must obey sRIO rules 3203215976Sjmallett (4, 8, 16, 24, 32, 40, 48, 56 and 64 byte 3204215976Sjmallett lengths allowed) 3205215976Sjmallett 3206215976Sjmallett WR_OP = 7 = Maintenance Port Write 3207215976Sjmallett - SRIO will create one sRIO MAINTENANCE port 3208215976Sjmallett write operation to service the MAC memory 3209215976Sjmallett space write 3210215976Sjmallett - IAOW_SEL must be zero. (see description 3211215976Sjmallett below.) 3212215976Sjmallett - MDS must be zero. (MDS is MACADD[63:62] - 3213215976Sjmallett see IAOW_SEL description below.) 3214215976Sjmallett - Hop Cnt is MACADD[31:24]/sRIOAddress[31:24] 3215215976Sjmallett - MACADD[23:0]/sRIOAddress[23:0] MBZ 3216215976Sjmallett (config_offset field reserved by sRIO) 3217215976Sjmallett - sRIODestID[15:0] is MACADD[49:34]. 3218215976Sjmallett (MACADD[49:42] unused when ID16=0) 3219215976Sjmallett - Write size/alignment must obey sRIO rules 3220215976Sjmallett (4, 8, 16, 24, 32, 40, 48, 56 and 64 byte 3221215976Sjmallett lengths allowed) */ 3222215976Sjmallett uint64_t reserved_15_15 : 1; 3223215976Sjmallett uint64_t rd_op : 3; /**< sRIO operation for SLI/DPI reads 3224215976Sjmallett 3225215976Sjmallett SLI/DPI hardware and sRIO configuration 3226215976Sjmallett restrictions guarantee that SRIO can service any 3227215976Sjmallett MAC memory space read that it receives from SLI/DPI 3228215976Sjmallett with a single NREAD, assuming that RD_OP selects 3229215976Sjmallett NREAD. DPI will break a read into multiple MAC 3230215976Sjmallett memory space reads to ensure this holds. The same 3231215976Sjmallett is not true for the ATOMIC and MAINTENANCE RD_OP 3232215976Sjmallett values. Additional SW/usage restrictions are 3233215976Sjmallett required for ATOMIC and MAINTENANCE RD_OP to work 3234215976Sjmallett correctly. SW must restrict the alignment and 3235215976Sjmallett length of DPI pointers and limit the load sizes 3236215976Sjmallett that the cores issue such that all MAC memory space 3237215976Sjmallett reads with ATOMIC and MAINTENANCE RD_OP's can be 3238215976Sjmallett serviced in a single sRIO operation. 3239215976Sjmallett 3240215976Sjmallett RD_OP = 0 = Normal Read (NREAD) 3241215976Sjmallett - SRIO will create one sRIO NREAD 3242215976Sjmallett operation to service the MAC memory 3243215976Sjmallett space read 3244215976Sjmallett - Read size/alignment must obey sRIO rules 3245215976Sjmallett (up to 256 byte lengths). (This requirement 3246215976Sjmallett is guaranteed by SLI/DPI usage restrictions 3247215976Sjmallett and configuration.) 3248215976Sjmallett 3249215976Sjmallett RD_OP = 1 = Reserved 3250215976Sjmallett 3251215976Sjmallett RD_OP = 2 = Atomic Set 3252215976Sjmallett - SRIO will create one sRIO ATOMIC set 3253215976Sjmallett operation to service the MAC memory 3254215976Sjmallett space read 3255215976Sjmallett - Read size/alignment must obey sRIO rules 3256215976Sjmallett (1, 2, and 4 byte lengths allowed) 3257215976Sjmallett 3258215976Sjmallett RD_OP = 3 = Atomic Clear 3259215976Sjmallett - SRIO will create one sRIO ATOMIC clr 3260215976Sjmallett operation to service the MAC memory 3261215976Sjmallett space read 3262215976Sjmallett - Read size/alignment must obey sRIO rules 3263215976Sjmallett (1, 2, and 4 byte lengths allowed) 3264215976Sjmallett 3265215976Sjmallett RD_OP = 4 = Atomic Increment 3266215976Sjmallett - SRIO will create one sRIO ATOMIC inc 3267215976Sjmallett operation to service the MAC memory 3268215976Sjmallett space read 3269215976Sjmallett - Read size/alignment must obey sRIO rules 3270215976Sjmallett (1, 2, and 4 byte lengths allowed) 3271215976Sjmallett 3272215976Sjmallett RD_OP = 5 = Atomic Decrement 3273215976Sjmallett - SRIO will create one sRIO ATOMIC dec 3274215976Sjmallett operation to service the MAC memory 3275215976Sjmallett space read 3276215976Sjmallett - Read size/alignment must obey sRIO rules 3277215976Sjmallett (1, 2, and 4 byte lengths allowed) 3278215976Sjmallett 3279215976Sjmallett RD_OP = 6 = Maintenance Read 3280215976Sjmallett - SRIO will create one sRIO MAINTENANCE read 3281215976Sjmallett operation to service the MAC memory 3282215976Sjmallett space read 3283215976Sjmallett - IAOW_SEL must be zero. (see description 3284215976Sjmallett below.) 3285215976Sjmallett - MDS must be zero. (MDS is MACADD[63:62] - 3286215976Sjmallett see IAOW_SEL description below.) 3287215976Sjmallett - Hop Cnt is MACADD[31:24]/sRIOAddress[31:24] 3288215976Sjmallett - MACADD[23:0]/sRIOAddress[23:0] selects 3289215976Sjmallett maintenance register (i.e. config_offset) 3290215976Sjmallett - sRIODestID[15:0] is MACADD[49:34]. 3291215976Sjmallett (MACADD[49:42] unused when ID16=0) 3292215976Sjmallett - Read size/alignment must obey sRIO rules 3293215976Sjmallett (4, 8, 16, 32 and 64 byte lengths allowed) 3294215976Sjmallett 3295215976Sjmallett RD_OP = 7 = Reserved */ 3296215976Sjmallett uint64_t wr_prior : 2; /**< Transaction Priority 0-3 used for writes */ 3297215976Sjmallett uint64_t rd_prior : 2; /**< Transaction Priority 0-3 used for reads/ATOMICs */ 3298215976Sjmallett uint64_t reserved_6_7 : 2; 3299215976Sjmallett uint64_t src_id : 1; /**< Source ID 3300215976Sjmallett 3301215976Sjmallett 0 = Use Primary ID as Source ID 3302215976Sjmallett (SRIOMAINT*_PRI_DEV_ID[ID16 or ID8], depending 3303215976Sjmallett on SRIO TT ID (i.e. ID16 below)) 3304215976Sjmallett 3305215976Sjmallett 1 = Use Secondary ID as Source ID 3306215976Sjmallett (SRIOMAINT*_SEC_DEV_ID[ID16 or ID8], depending 3307215976Sjmallett on SRIO TT ID (i.e. ID16 below)) */ 3308215976Sjmallett uint64_t id16 : 1; /**< SRIO TT ID 0=8bit, 1=16-bit 3309215976Sjmallett IAOW_SEL must not be 2 when ID16=1. */ 3310215976Sjmallett uint64_t reserved_2_3 : 2; 3311215976Sjmallett uint64_t iaow_sel : 2; /**< Internal Address Offset Width Select 3312215976Sjmallett 3313215976Sjmallett IAOW_SEL determines how to convert the 3314215976Sjmallett MACADD[63:62,58:51,49:0] recieved from SLI/DPI with 3315215976Sjmallett read/write into an sRIO address (sRIOAddress[...]) 3316215976Sjmallett and sRIO destination ID (sRIODestID[...]). The sRIO 3317215976Sjmallett address width mode (SRIOMAINT_PE_LLC[EX_ADDR]) and 3318215976Sjmallett ID16, determine the width of the sRIO address and 3319215976Sjmallett ID in the outgoing request(s), respectively. 3320215976Sjmallett 3321215976Sjmallett MACADD[61:60] is always unused. 3322215976Sjmallett 3323215976Sjmallett MACADD[59] is always TYPEIDX[3] 3324215976Sjmallett MACADD[50] is always TYPEIDX[2] 3325215976Sjmallett (TYPEIDX[3:0] selects one of these 3326215976Sjmallett SRIO*_S2M_TYPE* table entries.) 3327215976Sjmallett 3328215976Sjmallett MACADD[17:0] always becomes sRIOAddress[17:0]. 3329215976Sjmallett 3330215976Sjmallett IAOW_SEL = 0 = 34-bit Address Offset 3331215976Sjmallett 3332215976Sjmallett Must be used when sRIO link is in 34-bit 3333215976Sjmallett address width mode. 3334215976Sjmallett When sRIO is in 50-bit address width mode, 3335215976Sjmallett sRIOAddress[49:34]=0 in the outgoing request. 3336215976Sjmallett When sRIO is in 66-bit address width mode, 3337215976Sjmallett sRIOAddress[65:34]=0 in the outgoing request. 3338215976Sjmallett 3339215976Sjmallett Usage of the SLI/DPI MAC address when 3340215976Sjmallett IAOW_SEL = 0: 3341215976Sjmallett MACADD[63:62] = Multi-Device Swap (MDS) 3342215976Sjmallett MDS value affects MACADD[49:18] usage 3343215976Sjmallett MACADD[58:51] => unused 3344215976Sjmallett MACADD[49:18] usage depends on MDS value 3345215976Sjmallett MDS = 0 3346215976Sjmallett MACADD[49:34] => sRIODestID[15:0] 3347215976Sjmallett (MACADD[49:42] unused when ID16=0) 3348215976Sjmallett MACADD[33:18] => sRIOAddress[33:18] 3349215976Sjmallett MDS = 1 3350215976Sjmallett MACADD[49:42] => sRIODestID[15:8] 3351215976Sjmallett (MACADD[49:42] unused when ID16 = 0) 3352215976Sjmallett MACADD[41:34] => sRIOAddress[33:26] 3353215976Sjmallett MACADD[33:26] => sRIODestID[7:0] 3354215976Sjmallett MACADD[25:18] => sRIOAddress[25:18] 3355215976Sjmallett MDS = 2 3356215976Sjmallett ID16 must be one. 3357215976Sjmallett MACADD[49:34] => sRIOAddress[33:18] 3358215976Sjmallett MACADD[33:18] => sRIODestID[15:0] 3359215976Sjmallett MDS = 3 = Reserved 3360215976Sjmallett 3361215976Sjmallett IAOW_SEL = 1 = 42-bit Address Offset 3362215976Sjmallett 3363215976Sjmallett Must not be used when sRIO link is in 34-bit 3364215976Sjmallett address width mode. 3365215976Sjmallett When sRIO is in 50-bit address width mode, 3366215976Sjmallett sRIOAddress[49:42]=0 in the outgoing request. 3367215976Sjmallett When sRIO is in 66-bit address width mode, 3368215976Sjmallett sRIOAddress[65:42]=0 in the outgoing request. 3369215976Sjmallett 3370215976Sjmallett Usage of the SLI/DPI MAC address when 3371215976Sjmallett IAOW_SEL = 1: 3372215976Sjmallett MACADD[63:62] => Multi-Device Swap (MDS) 3373215976Sjmallett MDS value affects MACADD[58:51,49:42,33:18] 3374215976Sjmallett use 3375215976Sjmallett MACADD[41:34] => sRIOAddress[41:34] 3376215976Sjmallett MACADD[58:51,49:42,33:18] usage depends on 3377215976Sjmallett MDS value: 3378215976Sjmallett MDS = 0 3379215976Sjmallett MACADD[58:51] => sRIODestID[15:8] 3380215976Sjmallett MACADD[49:42] => sRIODestID[7:0] 3381215976Sjmallett (MACADD[58:51] unused when ID16=0) 3382215976Sjmallett MACADD[33:18] => sRIOAddress[33:18] 3383215976Sjmallett MDS = 1 3384215976Sjmallett MACADD[58:51] => sRIODestID[15:8] 3385215976Sjmallett (MACADD[58:51] unused when ID16 = 0) 3386215976Sjmallett MACADD[49:42] => sRIOAddress[33:26] 3387215976Sjmallett MACADD[33:26] => sRIODestID[7:0] 3388215976Sjmallett MACADD[25:18] => sRIOAddress[25:18] 3389215976Sjmallett MDS = 2 3390215976Sjmallett ID16 must be one. 3391215976Sjmallett MACADD[58:51] => sRIOAddress[33:26] 3392215976Sjmallett MACADD[49:42] => sRIOAddress[25:18] 3393215976Sjmallett MACADD[33:18] => sRIODestID[15:0] 3394215976Sjmallett MDS = 3 = Reserved 3395215976Sjmallett 3396215976Sjmallett IAOW_SEL = 2 = 50-bit Address Offset 3397215976Sjmallett 3398215976Sjmallett Must not be used when sRIO link is in 34-bit 3399215976Sjmallett address width mode. 3400215976Sjmallett Must not be used when ID16=1. 3401215976Sjmallett When sRIO is in 66-bit address width mode, 3402215976Sjmallett sRIOAddress[65:50]=0 in the outgoing request. 3403215976Sjmallett 3404215976Sjmallett Usage of the SLI/DPI MAC address when 3405215976Sjmallett IAOW_SEL = 2: 3406215976Sjmallett MACADD[63:62] => Multi-Device Swap (MDS) 3407215976Sjmallett MDS value affects MACADD[58:51,33:26] use 3408215976Sjmallett MDS value 3 is reserved 3409215976Sjmallett MACADD[49:34] => sRIOAddress[49:34] 3410215976Sjmallett MACADD[25:18] => sRIOAddress[25:18] 3411215976Sjmallett MACADD[58:51,33:26] usage depends on 3412215976Sjmallett MDS value: 3413215976Sjmallett MDS = 0 3414215976Sjmallett MACADD[58:51] => sRIODestID[7:0] 3415215976Sjmallett MACADD[33:26] => sRIOAddress[33:26] 3416215976Sjmallett MDS = 1 3417215976Sjmallett MACADD[58:51] => sRIOAddress[33:26] 3418215976Sjmallett MACADD[33:26] => sRIODestID[7:0] 3419215976Sjmallett MDS = 2 = Reserved 3420215976Sjmallett MDS = 3 = Reserved 3421215976Sjmallett 3422215976Sjmallett IAOW_SEL = 3 = Reserved */ 3423215976Sjmallett#else 3424215976Sjmallett uint64_t iaow_sel : 2; 3425215976Sjmallett uint64_t reserved_2_3 : 2; 3426215976Sjmallett uint64_t id16 : 1; 3427215976Sjmallett uint64_t src_id : 1; 3428215976Sjmallett uint64_t reserved_6_7 : 2; 3429215976Sjmallett uint64_t rd_prior : 2; 3430215976Sjmallett uint64_t wr_prior : 2; 3431215976Sjmallett uint64_t rd_op : 3; 3432215976Sjmallett uint64_t reserved_15_15 : 1; 3433215976Sjmallett uint64_t wr_op : 3; 3434215976Sjmallett uint64_t reserved_19_63 : 45; 3435215976Sjmallett#endif 3436215976Sjmallett } s; 3437215976Sjmallett struct cvmx_sriox_s2m_typex_s cn63xx; 3438215976Sjmallett struct cvmx_sriox_s2m_typex_s cn63xxp1; 3439232812Sjmallett struct cvmx_sriox_s2m_typex_s cn66xx; 3440215976Sjmallett}; 3441215976Sjmalletttypedef union cvmx_sriox_s2m_typex cvmx_sriox_s2m_typex_t; 3442215976Sjmallett 3443215976Sjmallett/** 3444215976Sjmallett * cvmx_srio#_seq 3445215976Sjmallett * 3446215976Sjmallett * SRIO_SEQ = SRIO Sequence Count 3447215976Sjmallett * 3448215976Sjmallett * The SRIO Sequence Count 3449215976Sjmallett * 3450215976Sjmallett * Notes: 3451215976Sjmallett * This register contains the current value of the sequence counter. This counter increments every 3452215976Sjmallett * time a doorbell or the first segment of a message is accepted. 3453215976Sjmallett * 3454232812Sjmallett * Clk_Rst: SRIO(0,2..3)_SEQ hclk hrst_n 3455215976Sjmallett */ 3456232812Sjmallettunion cvmx_sriox_seq { 3457215976Sjmallett uint64_t u64; 3458232812Sjmallett struct cvmx_sriox_seq_s { 3459232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3460215976Sjmallett uint64_t reserved_32_63 : 32; 3461215976Sjmallett uint64_t seq : 32; /**< 32-bit Sequence \# */ 3462215976Sjmallett#else 3463215976Sjmallett uint64_t seq : 32; 3464215976Sjmallett uint64_t reserved_32_63 : 32; 3465215976Sjmallett#endif 3466215976Sjmallett } s; 3467215976Sjmallett struct cvmx_sriox_seq_s cn63xx; 3468215976Sjmallett struct cvmx_sriox_seq_s cn63xxp1; 3469232812Sjmallett struct cvmx_sriox_seq_s cn66xx; 3470215976Sjmallett}; 3471215976Sjmalletttypedef union cvmx_sriox_seq cvmx_sriox_seq_t; 3472215976Sjmallett 3473215976Sjmallett/** 3474215976Sjmallett * cvmx_srio#_status_reg 3475215976Sjmallett * 3476232812Sjmallett * 13e20 reserved 3477215976Sjmallett * 3478232812Sjmallett * 3479232812Sjmallett * SRIO_STATUS_REG = SRIO Status Register 3480232812Sjmallett * 3481215976Sjmallett * General status of the SRIO. 3482215976Sjmallett * 3483215976Sjmallett * Notes: 3484215976Sjmallett * The SRIO field displays if the port has been configured for SRIO operation. This register can be 3485215976Sjmallett * read regardless of whether the SRIO is selected or being reset. Although some other registers can 3486215976Sjmallett * be accessed while the ACCESS bit is zero (see individual registers for details), the majority of 3487215976Sjmallett * SRIO registers and all the SRIOMAINT registers can be used only when the ACCESS bit is asserted. 3488215976Sjmallett * 3489232812Sjmallett * Clk_Rst: SRIO(0,2..3)_STATUS_REG sclk srst_n 3490215976Sjmallett */ 3491232812Sjmallettunion cvmx_sriox_status_reg { 3492215976Sjmallett uint64_t u64; 3493232812Sjmallett struct cvmx_sriox_status_reg_s { 3494232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3495215976Sjmallett uint64_t reserved_2_63 : 62; 3496215976Sjmallett uint64_t access : 1; /**< SRIO and SRIOMAINT Register Access. 3497215976Sjmallett 0 - Register Access Disabled. 3498215976Sjmallett 1 - Register Access Enabled. */ 3499215976Sjmallett uint64_t srio : 1; /**< SRIO Port Enabled. 3500215976Sjmallett 0 - All SRIO functions disabled. 3501215976Sjmallett 1 - All SRIO Operations permitted. */ 3502215976Sjmallett#else 3503215976Sjmallett uint64_t srio : 1; 3504215976Sjmallett uint64_t access : 1; 3505215976Sjmallett uint64_t reserved_2_63 : 62; 3506215976Sjmallett#endif 3507215976Sjmallett } s; 3508215976Sjmallett struct cvmx_sriox_status_reg_s cn63xx; 3509215976Sjmallett struct cvmx_sriox_status_reg_s cn63xxp1; 3510232812Sjmallett struct cvmx_sriox_status_reg_s cn66xx; 3511215976Sjmallett}; 3512215976Sjmalletttypedef union cvmx_sriox_status_reg cvmx_sriox_status_reg_t; 3513215976Sjmallett 3514215976Sjmallett/** 3515215976Sjmallett * cvmx_srio#_tag_ctrl 3516215976Sjmallett * 3517215976Sjmallett * SRIO_TAG_CTRL = SRIO TAG Control 3518215976Sjmallett * 3519215976Sjmallett * The SRIO TAG Control 3520215976Sjmallett * 3521215976Sjmallett * Notes: 3522215976Sjmallett * This register is used to show the state of the internal transaction tags and provides a manual 3523215976Sjmallett * reset of the outgoing tags. 3524215976Sjmallett * 3525232812Sjmallett * Clk_Rst: SRIO(0,2..3)_TAG_CTRL hclk hrst_n 3526215976Sjmallett */ 3527232812Sjmallettunion cvmx_sriox_tag_ctrl { 3528215976Sjmallett uint64_t u64; 3529232812Sjmallett struct cvmx_sriox_tag_ctrl_s { 3530232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3531215976Sjmallett uint64_t reserved_17_63 : 47; 3532215976Sjmallett uint64_t o_clr : 1; /**< Manual OTAG Clear. This bit manually resets the 3533215976Sjmallett number of OTAGs back to 16 and loses track of any 3534215976Sjmallett outgoing packets. This function is automatically 3535215976Sjmallett performed when the SRIO MAC is reset but it may be 3536215976Sjmallett necessary after a chip reset while the MAC is in 3537215976Sjmallett operation. This bit must be set then cleared to 3538215976Sjmallett return to normal operation. Typically, Outgoing 3539215976Sjmallett SRIO packets must be halted 6 seconds prior to 3540215976Sjmallett this bit is set to avoid generating duplicate tags 3541215976Sjmallett and unexpected response errors. */ 3542215976Sjmallett uint64_t reserved_13_15 : 3; 3543215976Sjmallett uint64_t otag : 5; /**< Number of Available Outbound Tags. Tags are 3544215976Sjmallett required for all outgoing memory and maintenance 3545215976Sjmallett operations that require a response. (Max 16) */ 3546215976Sjmallett uint64_t reserved_5_7 : 3; 3547215976Sjmallett uint64_t itag : 5; /**< Number of Available Inbound Tags. Tags are 3548215976Sjmallett required for all incoming memory operations that 3549215976Sjmallett require a response. (Max 16) */ 3550215976Sjmallett#else 3551215976Sjmallett uint64_t itag : 5; 3552215976Sjmallett uint64_t reserved_5_7 : 3; 3553215976Sjmallett uint64_t otag : 5; 3554215976Sjmallett uint64_t reserved_13_15 : 3; 3555215976Sjmallett uint64_t o_clr : 1; 3556215976Sjmallett uint64_t reserved_17_63 : 47; 3557215976Sjmallett#endif 3558215976Sjmallett } s; 3559215976Sjmallett struct cvmx_sriox_tag_ctrl_s cn63xx; 3560215976Sjmallett struct cvmx_sriox_tag_ctrl_s cn63xxp1; 3561232812Sjmallett struct cvmx_sriox_tag_ctrl_s cn66xx; 3562215976Sjmallett}; 3563215976Sjmalletttypedef union cvmx_sriox_tag_ctrl cvmx_sriox_tag_ctrl_t; 3564215976Sjmallett 3565215976Sjmallett/** 3566215976Sjmallett * cvmx_srio#_tlp_credits 3567215976Sjmallett * 3568215976Sjmallett * SRIO_TLP_CREDITS = SRIO TLP Credits 3569215976Sjmallett * 3570215976Sjmallett * Specifies the number of credits the SRIO can use for incoming Commands and Messages. 3571215976Sjmallett * 3572215976Sjmallett * Notes: 3573215976Sjmallett * Specifies the number of maximum credits the SRIO can use for incoming Commands and Messages. 3574232812Sjmallett * Reset values for COMP, N_POST and POST credits are based on the number of lanes allocated by the 3575232812Sjmallett * QLM Configuration to the SRIO MAC and whether QLM1 is used by PCIe. If SRIO MACs are unused then 3576232812Sjmallett * credits may be allocated to other MACs under some circumstances. The following table shows the 3577232812Sjmallett * reset values for COMP/N_POST/POST: 3578232812Sjmallett * QLM0_CFG QLM1_CFG SRIO0 SRIO2 SRIO3 3579232812Sjmallett * ====================================================== 3580232812Sjmallett * PEM Any 0/0/0 0/0/0 0/0/0 3581232812Sjmallett * SRIO x4 Any 128/16/128 0/0/0 0/0/0 3582232812Sjmallett * SRIO x2 PEM 64/8/64 64/8/64 0/0/0 3583232812Sjmallett * SRIO x2 non-PEM 128/16/128 128/16/128 0/0/0 3584232812Sjmallett * SRIO x1 PEM 42/5/42 42/5/42 42/5/42 3585232812Sjmallett * SRIO x1 non-PEM 64/8/64 64/8/64 64/8/64 3586215976Sjmallett * 3587232812Sjmallett * Clk_Rst: SRIO(0,2..3)_TLP_CREDITS hclk hrst_n 3588215976Sjmallett */ 3589232812Sjmallettunion cvmx_sriox_tlp_credits { 3590215976Sjmallett uint64_t u64; 3591232812Sjmallett struct cvmx_sriox_tlp_credits_s { 3592232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3593215976Sjmallett uint64_t reserved_28_63 : 36; 3594215976Sjmallett uint64_t mbox : 4; /**< Credits for Mailbox Data used in M2S. 3595215976Sjmallett Legal values are 0x2 to 0x8. */ 3596215976Sjmallett uint64_t comp : 8; /**< Credits for Read Completions used in M2S. 3597215976Sjmallett Legal values are 0x22 to 0x80. */ 3598215976Sjmallett uint64_t reserved_13_15 : 3; 3599215976Sjmallett uint64_t n_post : 5; /**< Credits for Read Requests used in M2S. 3600215976Sjmallett Legal values are 0x4 to 0x10. */ 3601215976Sjmallett uint64_t post : 8; /**< Credits for Write Request Postings used in M2S. 3602215976Sjmallett Legal values are 0x22 to 0x80. */ 3603215976Sjmallett#else 3604215976Sjmallett uint64_t post : 8; 3605215976Sjmallett uint64_t n_post : 5; 3606215976Sjmallett uint64_t reserved_13_15 : 3; 3607215976Sjmallett uint64_t comp : 8; 3608215976Sjmallett uint64_t mbox : 4; 3609215976Sjmallett uint64_t reserved_28_63 : 36; 3610215976Sjmallett#endif 3611215976Sjmallett } s; 3612215976Sjmallett struct cvmx_sriox_tlp_credits_s cn63xx; 3613215976Sjmallett struct cvmx_sriox_tlp_credits_s cn63xxp1; 3614232812Sjmallett struct cvmx_sriox_tlp_credits_s cn66xx; 3615215976Sjmallett}; 3616215976Sjmalletttypedef union cvmx_sriox_tlp_credits cvmx_sriox_tlp_credits_t; 3617215976Sjmallett 3618215976Sjmallett/** 3619215976Sjmallett * cvmx_srio#_tx_bell 3620215976Sjmallett * 3621215976Sjmallett * SRIO_TX_BELL = SRIO Transmit Doorbell 3622215976Sjmallett * 3623215976Sjmallett * The SRIO Outgoing (TX) Doorbell 3624215976Sjmallett * 3625215976Sjmallett * Notes: 3626215976Sjmallett * This register specifies SRIO Information, Device ID, Transaction Type and Priority of the outgoing 3627215976Sjmallett * Doorbell Transaction. Writes to this register causes the Doorbell to be issued using these bits. 3628215976Sjmallett * The write also causes the PENDING bit to be set. The hardware automatically clears bit when the 3629215976Sjmallett * Doorbell operation has been acknowledged. A write to this register while the PENDING bit is set 3630215976Sjmallett * should be avoided as it will stall the RSL until the first Doorbell has completed. 3631215976Sjmallett * 3632232812Sjmallett * Clk_Rst: SRIO(0,2..3)_TX_BELL hclk hrst_n 3633215976Sjmallett */ 3634232812Sjmallettunion cvmx_sriox_tx_bell { 3635215976Sjmallett uint64_t u64; 3636232812Sjmallett struct cvmx_sriox_tx_bell_s { 3637232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3638215976Sjmallett uint64_t reserved_48_63 : 16; 3639215976Sjmallett uint64_t data : 16; /**< Information field for next doorbell operation */ 3640215976Sjmallett uint64_t dest_id : 16; /**< Doorbell Destination Device ID[15:0] */ 3641215976Sjmallett uint64_t reserved_9_15 : 7; 3642215976Sjmallett uint64_t pending : 1; /**< Doorbell Transmit in Progress */ 3643215976Sjmallett uint64_t reserved_5_7 : 3; 3644215976Sjmallett uint64_t src_id : 1; /**< Source Device ID 0=Primary, 1=Secondary */ 3645215976Sjmallett uint64_t id16 : 1; /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */ 3646215976Sjmallett uint64_t reserved_2_2 : 1; 3647215976Sjmallett uint64_t priority : 2; /**< Doorbell Priority */ 3648215976Sjmallett#else 3649215976Sjmallett uint64_t priority : 2; 3650215976Sjmallett uint64_t reserved_2_2 : 1; 3651215976Sjmallett uint64_t id16 : 1; 3652215976Sjmallett uint64_t src_id : 1; 3653215976Sjmallett uint64_t reserved_5_7 : 3; 3654215976Sjmallett uint64_t pending : 1; 3655215976Sjmallett uint64_t reserved_9_15 : 7; 3656215976Sjmallett uint64_t dest_id : 16; 3657215976Sjmallett uint64_t data : 16; 3658215976Sjmallett uint64_t reserved_48_63 : 16; 3659215976Sjmallett#endif 3660215976Sjmallett } s; 3661215976Sjmallett struct cvmx_sriox_tx_bell_s cn63xx; 3662215976Sjmallett struct cvmx_sriox_tx_bell_s cn63xxp1; 3663232812Sjmallett struct cvmx_sriox_tx_bell_s cn66xx; 3664215976Sjmallett}; 3665215976Sjmalletttypedef union cvmx_sriox_tx_bell cvmx_sriox_tx_bell_t; 3666215976Sjmallett 3667215976Sjmallett/** 3668215976Sjmallett * cvmx_srio#_tx_bell_info 3669215976Sjmallett * 3670215976Sjmallett * SRIO_TX_BELL_INFO = SRIO Transmit Doorbell Interrupt Information 3671215976Sjmallett * 3672215976Sjmallett * The SRIO Outgoing (TX) Doorbell Interrupt Information 3673215976Sjmallett * 3674215976Sjmallett * Notes: 3675232812Sjmallett * This register is only updated if the BELL_ERR bit is clear in SRIO(0,2..3)_INT_REG. This register 3676215976Sjmallett * displays SRIO Information, Device ID, Transaction Type and Priority of the Doorbell Transaction 3677215976Sjmallett * that generated the BELL_ERR Interrupt. The register includes either a RETRY, ERROR or TIMEOUT 3678215976Sjmallett * Status. 3679215976Sjmallett * 3680232812Sjmallett * Clk_Rst: SRIO(0,2..3)_TX_BELL_INFO hclk hrst_n 3681215976Sjmallett */ 3682232812Sjmallettunion cvmx_sriox_tx_bell_info { 3683215976Sjmallett uint64_t u64; 3684232812Sjmallett struct cvmx_sriox_tx_bell_info_s { 3685232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3686215976Sjmallett uint64_t reserved_48_63 : 16; 3687215976Sjmallett uint64_t data : 16; /**< Information field from last doorbell operation */ 3688215976Sjmallett uint64_t dest_id : 16; /**< Doorbell Destination Device ID[15:0] */ 3689215976Sjmallett uint64_t reserved_8_15 : 8; 3690215976Sjmallett uint64_t timeout : 1; /**< Transmit Doorbell Failed with Timeout. */ 3691215976Sjmallett uint64_t error : 1; /**< Transmit Doorbell Destination returned Error. */ 3692215976Sjmallett uint64_t retry : 1; /**< Transmit Doorbell Requests a retransmission. */ 3693215976Sjmallett uint64_t src_id : 1; /**< Source Device ID 0=Primary, 1=Secondary */ 3694215976Sjmallett uint64_t id16 : 1; /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */ 3695215976Sjmallett uint64_t reserved_2_2 : 1; 3696215976Sjmallett uint64_t priority : 2; /**< Doorbell Priority */ 3697215976Sjmallett#else 3698215976Sjmallett uint64_t priority : 2; 3699215976Sjmallett uint64_t reserved_2_2 : 1; 3700215976Sjmallett uint64_t id16 : 1; 3701215976Sjmallett uint64_t src_id : 1; 3702215976Sjmallett uint64_t retry : 1; 3703215976Sjmallett uint64_t error : 1; 3704215976Sjmallett uint64_t timeout : 1; 3705215976Sjmallett uint64_t reserved_8_15 : 8; 3706215976Sjmallett uint64_t dest_id : 16; 3707215976Sjmallett uint64_t data : 16; 3708215976Sjmallett uint64_t reserved_48_63 : 16; 3709215976Sjmallett#endif 3710215976Sjmallett } s; 3711215976Sjmallett struct cvmx_sriox_tx_bell_info_s cn63xx; 3712215976Sjmallett struct cvmx_sriox_tx_bell_info_s cn63xxp1; 3713232812Sjmallett struct cvmx_sriox_tx_bell_info_s cn66xx; 3714215976Sjmallett}; 3715215976Sjmalletttypedef union cvmx_sriox_tx_bell_info cvmx_sriox_tx_bell_info_t; 3716215976Sjmallett 3717215976Sjmallett/** 3718215976Sjmallett * cvmx_srio#_tx_ctrl 3719215976Sjmallett * 3720215976Sjmallett * SRIO_TX_CTRL = SRIO Transmit Control 3721215976Sjmallett * 3722215976Sjmallett * The SRIO Transmit Control 3723215976Sjmallett * 3724215976Sjmallett * Notes: 3725232812Sjmallett * This register is used to control SRIO Outgoing Packet Allocation. TAG_TH[2:0] set the thresholds 3726232812Sjmallett * to allow priority traffic requiring responses to be queued based on the number of outgoing tags 3727232812Sjmallett * (TIDs) available. 16 Tags are available. If a priority is blocked for lack of tags then all 3728232812Sjmallett * lower priority packets are also blocked irregardless of whether they require tags. 3729215976Sjmallett * 3730232812Sjmallett * Clk_Rst: SRIO(0,2..3)_TX_CTRL hclk hrst_n 3731215976Sjmallett */ 3732232812Sjmallettunion cvmx_sriox_tx_ctrl { 3733215976Sjmallett uint64_t u64; 3734232812Sjmallett struct cvmx_sriox_tx_ctrl_s { 3735232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3736215976Sjmallett uint64_t reserved_53_63 : 11; 3737215976Sjmallett uint64_t tag_th2 : 5; /**< Sets threshold for minimum number of OTAGs 3738215976Sjmallett required before a packet of priority 2 requiring a 3739215976Sjmallett response will be queued for transmission. (Max 16) 3740215976Sjmallett There generally should be no priority 3 request 3741215976Sjmallett packets which require a response/tag, so a TAG_THR 3742215976Sjmallett value as low as 0 is allowed. */ 3743215976Sjmallett uint64_t reserved_45_47 : 3; 3744215976Sjmallett uint64_t tag_th1 : 5; /**< Sets threshold for minimum number of OTAGs 3745215976Sjmallett required before a packet of priority 1 requiring a 3746215976Sjmallett response will be queued for transmission. (Max 16) 3747215976Sjmallett Generally, TAG_TH1 must be > TAG_TH2 to leave OTAGs 3748215976Sjmallett for outgoing priority 2 (or 3) requests. */ 3749215976Sjmallett uint64_t reserved_37_39 : 3; 3750215976Sjmallett uint64_t tag_th0 : 5; /**< Sets threshold for minimum number of OTAGs 3751215976Sjmallett required before a packet of priority 0 requiring a 3752215976Sjmallett response will be queued for transmission. (Max 16) 3753215976Sjmallett Generally, TAG_TH0 must be > TAG_TH1 to leave OTAGs 3754215976Sjmallett for outgoing priority 1 or 2 (or 3) requests. */ 3755215976Sjmallett uint64_t reserved_20_31 : 12; 3756232812Sjmallett uint64_t tx_th2 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */ 3757215976Sjmallett uint64_t reserved_12_15 : 4; 3758232812Sjmallett uint64_t tx_th1 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */ 3759215976Sjmallett uint64_t reserved_4_7 : 4; 3760232812Sjmallett uint64_t tx_th0 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */ 3761215976Sjmallett#else 3762215976Sjmallett uint64_t tx_th0 : 4; 3763215976Sjmallett uint64_t reserved_4_7 : 4; 3764215976Sjmallett uint64_t tx_th1 : 4; 3765215976Sjmallett uint64_t reserved_12_15 : 4; 3766215976Sjmallett uint64_t tx_th2 : 4; 3767215976Sjmallett uint64_t reserved_20_31 : 12; 3768215976Sjmallett uint64_t tag_th0 : 5; 3769215976Sjmallett uint64_t reserved_37_39 : 3; 3770215976Sjmallett uint64_t tag_th1 : 5; 3771215976Sjmallett uint64_t reserved_45_47 : 3; 3772215976Sjmallett uint64_t tag_th2 : 5; 3773215976Sjmallett uint64_t reserved_53_63 : 11; 3774215976Sjmallett#endif 3775215976Sjmallett } s; 3776215976Sjmallett struct cvmx_sriox_tx_ctrl_s cn63xx; 3777215976Sjmallett struct cvmx_sriox_tx_ctrl_s cn63xxp1; 3778232812Sjmallett struct cvmx_sriox_tx_ctrl_s cn66xx; 3779215976Sjmallett}; 3780215976Sjmalletttypedef union cvmx_sriox_tx_ctrl cvmx_sriox_tx_ctrl_t; 3781215976Sjmallett 3782215976Sjmallett/** 3783215976Sjmallett * cvmx_srio#_tx_emphasis 3784215976Sjmallett * 3785232812Sjmallett * SRIO_TX_EMPHASIS = SRIO TX Lane Emphasis 3786215976Sjmallett * 3787215976Sjmallett * Controls TX Emphasis used by the SRIO SERDES 3788215976Sjmallett * 3789215976Sjmallett * Notes: 3790215976Sjmallett * This controls the emphasis value used by the SRIO SERDES. This register is only reset during COLD 3791232812Sjmallett * boot and may be modified regardless of the value in SRIO(0,2..3)_STATUS_REG.ACCESS. This register is not 3792232812Sjmallett * connected to the QLM and thus has no effect. It should not be included in the documentation. 3793215976Sjmallett * 3794232812Sjmallett * Clk_Rst: SRIO(0,2..3)_TX_EMPHASIS sclk srst_cold_n 3795215976Sjmallett */ 3796232812Sjmallettunion cvmx_sriox_tx_emphasis { 3797215976Sjmallett uint64_t u64; 3798232812Sjmallett struct cvmx_sriox_tx_emphasis_s { 3799232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3800215976Sjmallett uint64_t reserved_4_63 : 60; 3801215976Sjmallett uint64_t emph : 4; /**< Emphasis Value used for all lanes. Default value 3802215976Sjmallett is 0x0 for 1.25G b/s and 0xA for all other rates. */ 3803215976Sjmallett#else 3804215976Sjmallett uint64_t emph : 4; 3805215976Sjmallett uint64_t reserved_4_63 : 60; 3806215976Sjmallett#endif 3807215976Sjmallett } s; 3808215976Sjmallett struct cvmx_sriox_tx_emphasis_s cn63xx; 3809232812Sjmallett struct cvmx_sriox_tx_emphasis_s cn66xx; 3810215976Sjmallett}; 3811215976Sjmalletttypedef union cvmx_sriox_tx_emphasis cvmx_sriox_tx_emphasis_t; 3812215976Sjmallett 3813215976Sjmallett/** 3814215976Sjmallett * cvmx_srio#_tx_status 3815215976Sjmallett * 3816215976Sjmallett * SRIO_TX_STATUS = SRIO Outbound Credits/Ops Status 3817215976Sjmallett * 3818215976Sjmallett * Specifies the current number of credits/ops by SRIO for Outbound Traffic 3819215976Sjmallett * 3820215976Sjmallett * Notes: 3821215976Sjmallett * Debug Register specifying the number of credits/ops currently in use for Outbound Traffic. 3822215976Sjmallett * When all outbound traffic has stopped the values should eventually return to the reset values. 3823215976Sjmallett * 3824232812Sjmallett * Clk_Rst: SRIO(0,2..3)_TX_STATUS hclk hrst_n 3825215976Sjmallett */ 3826232812Sjmallettunion cvmx_sriox_tx_status { 3827215976Sjmallett uint64_t u64; 3828232812Sjmallett struct cvmx_sriox_tx_status_s { 3829232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3830215976Sjmallett uint64_t reserved_32_63 : 32; 3831215976Sjmallett uint64_t s2m_pr3 : 8; /**< Number of pending S2M Priority 3 Entries. */ 3832215976Sjmallett uint64_t s2m_pr2 : 8; /**< Number of pending S2M Priority 2 Entries. */ 3833215976Sjmallett uint64_t s2m_pr1 : 8; /**< Number of pending S2M Priority 1 Entries. */ 3834215976Sjmallett uint64_t s2m_pr0 : 8; /**< Number of pending S2M Priority 0 Entries. */ 3835215976Sjmallett#else 3836215976Sjmallett uint64_t s2m_pr0 : 8; 3837215976Sjmallett uint64_t s2m_pr1 : 8; 3838215976Sjmallett uint64_t s2m_pr2 : 8; 3839215976Sjmallett uint64_t s2m_pr3 : 8; 3840215976Sjmallett uint64_t reserved_32_63 : 32; 3841215976Sjmallett#endif 3842215976Sjmallett } s; 3843215976Sjmallett struct cvmx_sriox_tx_status_s cn63xx; 3844215976Sjmallett struct cvmx_sriox_tx_status_s cn63xxp1; 3845232812Sjmallett struct cvmx_sriox_tx_status_s cn66xx; 3846215976Sjmallett}; 3847215976Sjmalletttypedef union cvmx_sriox_tx_status cvmx_sriox_tx_status_t; 3848215976Sjmallett 3849215976Sjmallett/** 3850215976Sjmallett * cvmx_srio#_wr_done_counts 3851215976Sjmallett * 3852232812Sjmallett * SRIO_WR_DONE_COUNTS = SRIO Outgoing Write Done Counts 3853215976Sjmallett * 3854215976Sjmallett * The SRIO Outbound Write Done Counts 3855215976Sjmallett * 3856215976Sjmallett * Notes: 3857215976Sjmallett * This register shows the number of successful and unsuccessful NwriteRs issued through this MAC. 3858215976Sjmallett * These count only considers the last NwriteR generated by each Store Instruction. If any NwriteR 3859232812Sjmallett * in the series receives an ERROR Status then it is reported in SRIOMAINT(0,2..3)_ERB_LT_ERR_DET.IO_ERR. 3860215976Sjmallett * If any NwriteR does not receive a response within the timeout period then it is reported in 3861232812Sjmallett * SRIOMAINT(0,2..3)_ERB_LT_ERR_DET.PKT_TOUT. Only errors on the last NwriteR's are counted as BAD. This 3862215976Sjmallett * register is typically not written while Outbound SRIO Memory traffic is enabled. 3863215976Sjmallett * 3864232812Sjmallett * Clk_Rst: SRIO(0,2..3)_WR_DONE_COUNTS hclk hrst_n 3865215976Sjmallett */ 3866232812Sjmallettunion cvmx_sriox_wr_done_counts { 3867215976Sjmallett uint64_t u64; 3868232812Sjmallett struct cvmx_sriox_wr_done_counts_s { 3869232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3870215976Sjmallett uint64_t reserved_32_63 : 32; 3871215976Sjmallett uint64_t bad : 16; /**< Count of the final outbound NwriteR in the series 3872215976Sjmallett associated with a Store Operation that have timed 3873215976Sjmallett out or received a response with an ERROR status. */ 3874215976Sjmallett uint64_t good : 16; /**< Count of the final outbound NwriteR in the series 3875215976Sjmallett associated with a Store operation that has 3876215976Sjmallett received a response with a DONE status. */ 3877215976Sjmallett#else 3878215976Sjmallett uint64_t good : 16; 3879215976Sjmallett uint64_t bad : 16; 3880215976Sjmallett uint64_t reserved_32_63 : 32; 3881215976Sjmallett#endif 3882215976Sjmallett } s; 3883215976Sjmallett struct cvmx_sriox_wr_done_counts_s cn63xx; 3884232812Sjmallett struct cvmx_sriox_wr_done_counts_s cn66xx; 3885215976Sjmallett}; 3886215976Sjmalletttypedef union cvmx_sriox_wr_done_counts cvmx_sriox_wr_done_counts_t; 3887215976Sjmallett 3888215976Sjmallett#endif 3889