cvmx-pci-defs.h revision 215976
1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pci-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pci. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_PCI_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_PCI_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_PCI_BAR1_INDEXX(unsigned long offset) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) || 61215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) || 62215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) || 63215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31))))) 64215976Sjmallett cvmx_warn("CVMX_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset); 65215976Sjmallett return 0x0000000000000100ull + ((offset) & 31) * 4; 66215976Sjmallett} 67215976Sjmallett#else 68215976Sjmallett#define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4) 69215976Sjmallett#endif 70215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71215976Sjmallett#define CVMX_PCI_BIST_REG CVMX_PCI_BIST_REG_FUNC() 72215976Sjmallettstatic inline uint64_t CVMX_PCI_BIST_REG_FUNC(void) 73215976Sjmallett{ 74215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN50XX))) 75215976Sjmallett cvmx_warn("CVMX_PCI_BIST_REG not supported on this chip\n"); 76215976Sjmallett return 0x00000000000001C0ull; 77215976Sjmallett} 78215976Sjmallett#else 79215976Sjmallett#define CVMX_PCI_BIST_REG (0x00000000000001C0ull) 80215976Sjmallett#endif 81215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82215976Sjmallett#define CVMX_PCI_CFG00 CVMX_PCI_CFG00_FUNC() 83215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG00_FUNC(void) 84215976Sjmallett{ 85215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 86215976Sjmallett cvmx_warn("CVMX_PCI_CFG00 not supported on this chip\n"); 87215976Sjmallett return 0x0000000000000000ull; 88215976Sjmallett} 89215976Sjmallett#else 90215976Sjmallett#define CVMX_PCI_CFG00 (0x0000000000000000ull) 91215976Sjmallett#endif 92215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 93215976Sjmallett#define CVMX_PCI_CFG01 CVMX_PCI_CFG01_FUNC() 94215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG01_FUNC(void) 95215976Sjmallett{ 96215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 97215976Sjmallett cvmx_warn("CVMX_PCI_CFG01 not supported on this chip\n"); 98215976Sjmallett return 0x0000000000000004ull; 99215976Sjmallett} 100215976Sjmallett#else 101215976Sjmallett#define CVMX_PCI_CFG01 (0x0000000000000004ull) 102215976Sjmallett#endif 103215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104215976Sjmallett#define CVMX_PCI_CFG02 CVMX_PCI_CFG02_FUNC() 105215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG02_FUNC(void) 106215976Sjmallett{ 107215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 108215976Sjmallett cvmx_warn("CVMX_PCI_CFG02 not supported on this chip\n"); 109215976Sjmallett return 0x0000000000000008ull; 110215976Sjmallett} 111215976Sjmallett#else 112215976Sjmallett#define CVMX_PCI_CFG02 (0x0000000000000008ull) 113215976Sjmallett#endif 114215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 115215976Sjmallett#define CVMX_PCI_CFG03 CVMX_PCI_CFG03_FUNC() 116215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG03_FUNC(void) 117215976Sjmallett{ 118215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 119215976Sjmallett cvmx_warn("CVMX_PCI_CFG03 not supported on this chip\n"); 120215976Sjmallett return 0x000000000000000Cull; 121215976Sjmallett} 122215976Sjmallett#else 123215976Sjmallett#define CVMX_PCI_CFG03 (0x000000000000000Cull) 124215976Sjmallett#endif 125215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 126215976Sjmallett#define CVMX_PCI_CFG04 CVMX_PCI_CFG04_FUNC() 127215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG04_FUNC(void) 128215976Sjmallett{ 129215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 130215976Sjmallett cvmx_warn("CVMX_PCI_CFG04 not supported on this chip\n"); 131215976Sjmallett return 0x0000000000000010ull; 132215976Sjmallett} 133215976Sjmallett#else 134215976Sjmallett#define CVMX_PCI_CFG04 (0x0000000000000010ull) 135215976Sjmallett#endif 136215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 137215976Sjmallett#define CVMX_PCI_CFG05 CVMX_PCI_CFG05_FUNC() 138215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG05_FUNC(void) 139215976Sjmallett{ 140215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 141215976Sjmallett cvmx_warn("CVMX_PCI_CFG05 not supported on this chip\n"); 142215976Sjmallett return 0x0000000000000014ull; 143215976Sjmallett} 144215976Sjmallett#else 145215976Sjmallett#define CVMX_PCI_CFG05 (0x0000000000000014ull) 146215976Sjmallett#endif 147215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 148215976Sjmallett#define CVMX_PCI_CFG06 CVMX_PCI_CFG06_FUNC() 149215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG06_FUNC(void) 150215976Sjmallett{ 151215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 152215976Sjmallett cvmx_warn("CVMX_PCI_CFG06 not supported on this chip\n"); 153215976Sjmallett return 0x0000000000000018ull; 154215976Sjmallett} 155215976Sjmallett#else 156215976Sjmallett#define CVMX_PCI_CFG06 (0x0000000000000018ull) 157215976Sjmallett#endif 158215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 159215976Sjmallett#define CVMX_PCI_CFG07 CVMX_PCI_CFG07_FUNC() 160215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG07_FUNC(void) 161215976Sjmallett{ 162215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 163215976Sjmallett cvmx_warn("CVMX_PCI_CFG07 not supported on this chip\n"); 164215976Sjmallett return 0x000000000000001Cull; 165215976Sjmallett} 166215976Sjmallett#else 167215976Sjmallett#define CVMX_PCI_CFG07 (0x000000000000001Cull) 168215976Sjmallett#endif 169215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 170215976Sjmallett#define CVMX_PCI_CFG08 CVMX_PCI_CFG08_FUNC() 171215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG08_FUNC(void) 172215976Sjmallett{ 173215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 174215976Sjmallett cvmx_warn("CVMX_PCI_CFG08 not supported on this chip\n"); 175215976Sjmallett return 0x0000000000000020ull; 176215976Sjmallett} 177215976Sjmallett#else 178215976Sjmallett#define CVMX_PCI_CFG08 (0x0000000000000020ull) 179215976Sjmallett#endif 180215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 181215976Sjmallett#define CVMX_PCI_CFG09 CVMX_PCI_CFG09_FUNC() 182215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG09_FUNC(void) 183215976Sjmallett{ 184215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 185215976Sjmallett cvmx_warn("CVMX_PCI_CFG09 not supported on this chip\n"); 186215976Sjmallett return 0x0000000000000024ull; 187215976Sjmallett} 188215976Sjmallett#else 189215976Sjmallett#define CVMX_PCI_CFG09 (0x0000000000000024ull) 190215976Sjmallett#endif 191215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 192215976Sjmallett#define CVMX_PCI_CFG10 CVMX_PCI_CFG10_FUNC() 193215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG10_FUNC(void) 194215976Sjmallett{ 195215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 196215976Sjmallett cvmx_warn("CVMX_PCI_CFG10 not supported on this chip\n"); 197215976Sjmallett return 0x0000000000000028ull; 198215976Sjmallett} 199215976Sjmallett#else 200215976Sjmallett#define CVMX_PCI_CFG10 (0x0000000000000028ull) 201215976Sjmallett#endif 202215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 203215976Sjmallett#define CVMX_PCI_CFG11 CVMX_PCI_CFG11_FUNC() 204215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG11_FUNC(void) 205215976Sjmallett{ 206215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 207215976Sjmallett cvmx_warn("CVMX_PCI_CFG11 not supported on this chip\n"); 208215976Sjmallett return 0x000000000000002Cull; 209215976Sjmallett} 210215976Sjmallett#else 211215976Sjmallett#define CVMX_PCI_CFG11 (0x000000000000002Cull) 212215976Sjmallett#endif 213215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 214215976Sjmallett#define CVMX_PCI_CFG12 CVMX_PCI_CFG12_FUNC() 215215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG12_FUNC(void) 216215976Sjmallett{ 217215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 218215976Sjmallett cvmx_warn("CVMX_PCI_CFG12 not supported on this chip\n"); 219215976Sjmallett return 0x0000000000000030ull; 220215976Sjmallett} 221215976Sjmallett#else 222215976Sjmallett#define CVMX_PCI_CFG12 (0x0000000000000030ull) 223215976Sjmallett#endif 224215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225215976Sjmallett#define CVMX_PCI_CFG13 CVMX_PCI_CFG13_FUNC() 226215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG13_FUNC(void) 227215976Sjmallett{ 228215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 229215976Sjmallett cvmx_warn("CVMX_PCI_CFG13 not supported on this chip\n"); 230215976Sjmallett return 0x0000000000000034ull; 231215976Sjmallett} 232215976Sjmallett#else 233215976Sjmallett#define CVMX_PCI_CFG13 (0x0000000000000034ull) 234215976Sjmallett#endif 235215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236215976Sjmallett#define CVMX_PCI_CFG15 CVMX_PCI_CFG15_FUNC() 237215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG15_FUNC(void) 238215976Sjmallett{ 239215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 240215976Sjmallett cvmx_warn("CVMX_PCI_CFG15 not supported on this chip\n"); 241215976Sjmallett return 0x000000000000003Cull; 242215976Sjmallett} 243215976Sjmallett#else 244215976Sjmallett#define CVMX_PCI_CFG15 (0x000000000000003Cull) 245215976Sjmallett#endif 246215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 247215976Sjmallett#define CVMX_PCI_CFG16 CVMX_PCI_CFG16_FUNC() 248215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG16_FUNC(void) 249215976Sjmallett{ 250215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 251215976Sjmallett cvmx_warn("CVMX_PCI_CFG16 not supported on this chip\n"); 252215976Sjmallett return 0x0000000000000040ull; 253215976Sjmallett} 254215976Sjmallett#else 255215976Sjmallett#define CVMX_PCI_CFG16 (0x0000000000000040ull) 256215976Sjmallett#endif 257215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 258215976Sjmallett#define CVMX_PCI_CFG17 CVMX_PCI_CFG17_FUNC() 259215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG17_FUNC(void) 260215976Sjmallett{ 261215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 262215976Sjmallett cvmx_warn("CVMX_PCI_CFG17 not supported on this chip\n"); 263215976Sjmallett return 0x0000000000000044ull; 264215976Sjmallett} 265215976Sjmallett#else 266215976Sjmallett#define CVMX_PCI_CFG17 (0x0000000000000044ull) 267215976Sjmallett#endif 268215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 269215976Sjmallett#define CVMX_PCI_CFG18 CVMX_PCI_CFG18_FUNC() 270215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG18_FUNC(void) 271215976Sjmallett{ 272215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 273215976Sjmallett cvmx_warn("CVMX_PCI_CFG18 not supported on this chip\n"); 274215976Sjmallett return 0x0000000000000048ull; 275215976Sjmallett} 276215976Sjmallett#else 277215976Sjmallett#define CVMX_PCI_CFG18 (0x0000000000000048ull) 278215976Sjmallett#endif 279215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 280215976Sjmallett#define CVMX_PCI_CFG19 CVMX_PCI_CFG19_FUNC() 281215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG19_FUNC(void) 282215976Sjmallett{ 283215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 284215976Sjmallett cvmx_warn("CVMX_PCI_CFG19 not supported on this chip\n"); 285215976Sjmallett return 0x000000000000004Cull; 286215976Sjmallett} 287215976Sjmallett#else 288215976Sjmallett#define CVMX_PCI_CFG19 (0x000000000000004Cull) 289215976Sjmallett#endif 290215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 291215976Sjmallett#define CVMX_PCI_CFG20 CVMX_PCI_CFG20_FUNC() 292215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG20_FUNC(void) 293215976Sjmallett{ 294215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 295215976Sjmallett cvmx_warn("CVMX_PCI_CFG20 not supported on this chip\n"); 296215976Sjmallett return 0x0000000000000050ull; 297215976Sjmallett} 298215976Sjmallett#else 299215976Sjmallett#define CVMX_PCI_CFG20 (0x0000000000000050ull) 300215976Sjmallett#endif 301215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 302215976Sjmallett#define CVMX_PCI_CFG21 CVMX_PCI_CFG21_FUNC() 303215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG21_FUNC(void) 304215976Sjmallett{ 305215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 306215976Sjmallett cvmx_warn("CVMX_PCI_CFG21 not supported on this chip\n"); 307215976Sjmallett return 0x0000000000000054ull; 308215976Sjmallett} 309215976Sjmallett#else 310215976Sjmallett#define CVMX_PCI_CFG21 (0x0000000000000054ull) 311215976Sjmallett#endif 312215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 313215976Sjmallett#define CVMX_PCI_CFG22 CVMX_PCI_CFG22_FUNC() 314215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG22_FUNC(void) 315215976Sjmallett{ 316215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 317215976Sjmallett cvmx_warn("CVMX_PCI_CFG22 not supported on this chip\n"); 318215976Sjmallett return 0x0000000000000058ull; 319215976Sjmallett} 320215976Sjmallett#else 321215976Sjmallett#define CVMX_PCI_CFG22 (0x0000000000000058ull) 322215976Sjmallett#endif 323215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 324215976Sjmallett#define CVMX_PCI_CFG56 CVMX_PCI_CFG56_FUNC() 325215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG56_FUNC(void) 326215976Sjmallett{ 327215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 328215976Sjmallett cvmx_warn("CVMX_PCI_CFG56 not supported on this chip\n"); 329215976Sjmallett return 0x00000000000000E0ull; 330215976Sjmallett} 331215976Sjmallett#else 332215976Sjmallett#define CVMX_PCI_CFG56 (0x00000000000000E0ull) 333215976Sjmallett#endif 334215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 335215976Sjmallett#define CVMX_PCI_CFG57 CVMX_PCI_CFG57_FUNC() 336215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG57_FUNC(void) 337215976Sjmallett{ 338215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 339215976Sjmallett cvmx_warn("CVMX_PCI_CFG57 not supported on this chip\n"); 340215976Sjmallett return 0x00000000000000E4ull; 341215976Sjmallett} 342215976Sjmallett#else 343215976Sjmallett#define CVMX_PCI_CFG57 (0x00000000000000E4ull) 344215976Sjmallett#endif 345215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 346215976Sjmallett#define CVMX_PCI_CFG58 CVMX_PCI_CFG58_FUNC() 347215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG58_FUNC(void) 348215976Sjmallett{ 349215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 350215976Sjmallett cvmx_warn("CVMX_PCI_CFG58 not supported on this chip\n"); 351215976Sjmallett return 0x00000000000000E8ull; 352215976Sjmallett} 353215976Sjmallett#else 354215976Sjmallett#define CVMX_PCI_CFG58 (0x00000000000000E8ull) 355215976Sjmallett#endif 356215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 357215976Sjmallett#define CVMX_PCI_CFG59 CVMX_PCI_CFG59_FUNC() 358215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG59_FUNC(void) 359215976Sjmallett{ 360215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 361215976Sjmallett cvmx_warn("CVMX_PCI_CFG59 not supported on this chip\n"); 362215976Sjmallett return 0x00000000000000ECull; 363215976Sjmallett} 364215976Sjmallett#else 365215976Sjmallett#define CVMX_PCI_CFG59 (0x00000000000000ECull) 366215976Sjmallett#endif 367215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 368215976Sjmallett#define CVMX_PCI_CFG60 CVMX_PCI_CFG60_FUNC() 369215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG60_FUNC(void) 370215976Sjmallett{ 371215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 372215976Sjmallett cvmx_warn("CVMX_PCI_CFG60 not supported on this chip\n"); 373215976Sjmallett return 0x00000000000000F0ull; 374215976Sjmallett} 375215976Sjmallett#else 376215976Sjmallett#define CVMX_PCI_CFG60 (0x00000000000000F0ull) 377215976Sjmallett#endif 378215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 379215976Sjmallett#define CVMX_PCI_CFG61 CVMX_PCI_CFG61_FUNC() 380215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG61_FUNC(void) 381215976Sjmallett{ 382215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 383215976Sjmallett cvmx_warn("CVMX_PCI_CFG61 not supported on this chip\n"); 384215976Sjmallett return 0x00000000000000F4ull; 385215976Sjmallett} 386215976Sjmallett#else 387215976Sjmallett#define CVMX_PCI_CFG61 (0x00000000000000F4ull) 388215976Sjmallett#endif 389215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 390215976Sjmallett#define CVMX_PCI_CFG62 CVMX_PCI_CFG62_FUNC() 391215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG62_FUNC(void) 392215976Sjmallett{ 393215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 394215976Sjmallett cvmx_warn("CVMX_PCI_CFG62 not supported on this chip\n"); 395215976Sjmallett return 0x00000000000000F8ull; 396215976Sjmallett} 397215976Sjmallett#else 398215976Sjmallett#define CVMX_PCI_CFG62 (0x00000000000000F8ull) 399215976Sjmallett#endif 400215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 401215976Sjmallett#define CVMX_PCI_CFG63 CVMX_PCI_CFG63_FUNC() 402215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG63_FUNC(void) 403215976Sjmallett{ 404215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 405215976Sjmallett cvmx_warn("CVMX_PCI_CFG63 not supported on this chip\n"); 406215976Sjmallett return 0x00000000000000FCull; 407215976Sjmallett} 408215976Sjmallett#else 409215976Sjmallett#define CVMX_PCI_CFG63 (0x00000000000000FCull) 410215976Sjmallett#endif 411215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 412215976Sjmallett#define CVMX_PCI_CNT_REG CVMX_PCI_CNT_REG_FUNC() 413215976Sjmallettstatic inline uint64_t CVMX_PCI_CNT_REG_FUNC(void) 414215976Sjmallett{ 415215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 416215976Sjmallett cvmx_warn("CVMX_PCI_CNT_REG not supported on this chip\n"); 417215976Sjmallett return 0x00000000000001B8ull; 418215976Sjmallett} 419215976Sjmallett#else 420215976Sjmallett#define CVMX_PCI_CNT_REG (0x00000000000001B8ull) 421215976Sjmallett#endif 422215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 423215976Sjmallett#define CVMX_PCI_CTL_STATUS_2 CVMX_PCI_CTL_STATUS_2_FUNC() 424215976Sjmallettstatic inline uint64_t CVMX_PCI_CTL_STATUS_2_FUNC(void) 425215976Sjmallett{ 426215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 427215976Sjmallett cvmx_warn("CVMX_PCI_CTL_STATUS_2 not supported on this chip\n"); 428215976Sjmallett return 0x000000000000018Cull; 429215976Sjmallett} 430215976Sjmallett#else 431215976Sjmallett#define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull) 432215976Sjmallett#endif 433215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 434215976Sjmallettstatic inline uint64_t CVMX_PCI_DBELL_X(unsigned long offset) 435215976Sjmallett{ 436215976Sjmallett if (!( 437215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 438215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 439215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 440215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 441215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 442215976Sjmallett cvmx_warn("CVMX_PCI_DBELL_X(%lu) is invalid on this chip\n", offset); 443215976Sjmallett return 0x0000000000000080ull + ((offset) & 3) * 8; 444215976Sjmallett} 445215976Sjmallett#else 446215976Sjmallett#define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8) 447215976Sjmallett#endif 448215976Sjmallett#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0) 449215976Sjmallett#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1) 450215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 451215976Sjmallettstatic inline uint64_t CVMX_PCI_DMA_CNTX(unsigned long offset) 452215976Sjmallett{ 453215976Sjmallett if (!( 454215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 455215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 456215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 457215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 458215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 459215976Sjmallett cvmx_warn("CVMX_PCI_DMA_CNTX(%lu) is invalid on this chip\n", offset); 460215976Sjmallett return 0x00000000000000A0ull + ((offset) & 1) * 8; 461215976Sjmallett} 462215976Sjmallett#else 463215976Sjmallett#define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8) 464215976Sjmallett#endif 465215976Sjmallett#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0) 466215976Sjmallett#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1) 467215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 468215976Sjmallettstatic inline uint64_t CVMX_PCI_DMA_INT_LEVX(unsigned long offset) 469215976Sjmallett{ 470215976Sjmallett if (!( 471215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 472215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 473215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 474215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 475215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 476215976Sjmallett cvmx_warn("CVMX_PCI_DMA_INT_LEVX(%lu) is invalid on this chip\n", offset); 477215976Sjmallett return 0x00000000000000A4ull + ((offset) & 1) * 8; 478215976Sjmallett} 479215976Sjmallett#else 480215976Sjmallett#define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8) 481215976Sjmallett#endif 482215976Sjmallett#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0) 483215976Sjmallett#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1) 484215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485215976Sjmallettstatic inline uint64_t CVMX_PCI_DMA_TIMEX(unsigned long offset) 486215976Sjmallett{ 487215976Sjmallett if (!( 488215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 489215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 490215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 491215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 492215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 493215976Sjmallett cvmx_warn("CVMX_PCI_DMA_TIMEX(%lu) is invalid on this chip\n", offset); 494215976Sjmallett return 0x00000000000000B0ull + ((offset) & 1) * 4; 495215976Sjmallett} 496215976Sjmallett#else 497215976Sjmallett#define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4) 498215976Sjmallett#endif 499215976Sjmallett#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0) 500215976Sjmallett#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1) 501215976Sjmallett#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2) 502215976Sjmallett#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3) 503215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 504215976Sjmallettstatic inline uint64_t CVMX_PCI_INSTR_COUNTX(unsigned long offset) 505215976Sjmallett{ 506215976Sjmallett if (!( 507215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 508215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 509215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 510215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 511215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 512215976Sjmallett cvmx_warn("CVMX_PCI_INSTR_COUNTX(%lu) is invalid on this chip\n", offset); 513215976Sjmallett return 0x0000000000000084ull + ((offset) & 3) * 8; 514215976Sjmallett} 515215976Sjmallett#else 516215976Sjmallett#define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8) 517215976Sjmallett#endif 518215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 519215976Sjmallett#define CVMX_PCI_INT_ENB CVMX_PCI_INT_ENB_FUNC() 520215976Sjmallettstatic inline uint64_t CVMX_PCI_INT_ENB_FUNC(void) 521215976Sjmallett{ 522215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 523215976Sjmallett cvmx_warn("CVMX_PCI_INT_ENB not supported on this chip\n"); 524215976Sjmallett return 0x0000000000000038ull; 525215976Sjmallett} 526215976Sjmallett#else 527215976Sjmallett#define CVMX_PCI_INT_ENB (0x0000000000000038ull) 528215976Sjmallett#endif 529215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 530215976Sjmallett#define CVMX_PCI_INT_ENB2 CVMX_PCI_INT_ENB2_FUNC() 531215976Sjmallettstatic inline uint64_t CVMX_PCI_INT_ENB2_FUNC(void) 532215976Sjmallett{ 533215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 534215976Sjmallett cvmx_warn("CVMX_PCI_INT_ENB2 not supported on this chip\n"); 535215976Sjmallett return 0x00000000000001A0ull; 536215976Sjmallett} 537215976Sjmallett#else 538215976Sjmallett#define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull) 539215976Sjmallett#endif 540215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 541215976Sjmallett#define CVMX_PCI_INT_SUM CVMX_PCI_INT_SUM_FUNC() 542215976Sjmallettstatic inline uint64_t CVMX_PCI_INT_SUM_FUNC(void) 543215976Sjmallett{ 544215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 545215976Sjmallett cvmx_warn("CVMX_PCI_INT_SUM not supported on this chip\n"); 546215976Sjmallett return 0x0000000000000030ull; 547215976Sjmallett} 548215976Sjmallett#else 549215976Sjmallett#define CVMX_PCI_INT_SUM (0x0000000000000030ull) 550215976Sjmallett#endif 551215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 552215976Sjmallett#define CVMX_PCI_INT_SUM2 CVMX_PCI_INT_SUM2_FUNC() 553215976Sjmallettstatic inline uint64_t CVMX_PCI_INT_SUM2_FUNC(void) 554215976Sjmallett{ 555215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 556215976Sjmallett cvmx_warn("CVMX_PCI_INT_SUM2 not supported on this chip\n"); 557215976Sjmallett return 0x0000000000000198ull; 558215976Sjmallett} 559215976Sjmallett#else 560215976Sjmallett#define CVMX_PCI_INT_SUM2 (0x0000000000000198ull) 561215976Sjmallett#endif 562215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 563215976Sjmallett#define CVMX_PCI_MSI_RCV CVMX_PCI_MSI_RCV_FUNC() 564215976Sjmallettstatic inline uint64_t CVMX_PCI_MSI_RCV_FUNC(void) 565215976Sjmallett{ 566215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 567215976Sjmallett cvmx_warn("CVMX_PCI_MSI_RCV not supported on this chip\n"); 568215976Sjmallett return 0x00000000000000F0ull; 569215976Sjmallett} 570215976Sjmallett#else 571215976Sjmallett#define CVMX_PCI_MSI_RCV (0x00000000000000F0ull) 572215976Sjmallett#endif 573215976Sjmallett#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0) 574215976Sjmallett#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1) 575215976Sjmallett#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2) 576215976Sjmallett#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3) 577215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 578215976Sjmallettstatic inline uint64_t CVMX_PCI_PKTS_SENTX(unsigned long offset) 579215976Sjmallett{ 580215976Sjmallett if (!( 581215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 582215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 583215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 584215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 585215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 586215976Sjmallett cvmx_warn("CVMX_PCI_PKTS_SENTX(%lu) is invalid on this chip\n", offset); 587215976Sjmallett return 0x0000000000000040ull + ((offset) & 3) * 16; 588215976Sjmallett} 589215976Sjmallett#else 590215976Sjmallett#define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16) 591215976Sjmallett#endif 592215976Sjmallett#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0) 593215976Sjmallett#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1) 594215976Sjmallett#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2) 595215976Sjmallett#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3) 596215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 597215976Sjmallettstatic inline uint64_t CVMX_PCI_PKTS_SENT_INT_LEVX(unsigned long offset) 598215976Sjmallett{ 599215976Sjmallett if (!( 600215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 601215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 602215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 603215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 604215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 605215976Sjmallett cvmx_warn("CVMX_PCI_PKTS_SENT_INT_LEVX(%lu) is invalid on this chip\n", offset); 606215976Sjmallett return 0x0000000000000048ull + ((offset) & 3) * 16; 607215976Sjmallett} 608215976Sjmallett#else 609215976Sjmallett#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16) 610215976Sjmallett#endif 611215976Sjmallett#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0) 612215976Sjmallett#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1) 613215976Sjmallett#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2) 614215976Sjmallett#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3) 615215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 616215976Sjmallettstatic inline uint64_t CVMX_PCI_PKTS_SENT_TIMEX(unsigned long offset) 617215976Sjmallett{ 618215976Sjmallett if (!( 619215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 620215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 621215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 622215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 623215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 624215976Sjmallett cvmx_warn("CVMX_PCI_PKTS_SENT_TIMEX(%lu) is invalid on this chip\n", offset); 625215976Sjmallett return 0x000000000000004Cull + ((offset) & 3) * 16; 626215976Sjmallett} 627215976Sjmallett#else 628215976Sjmallett#define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16) 629215976Sjmallett#endif 630215976Sjmallett#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0) 631215976Sjmallett#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1) 632215976Sjmallett#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2) 633215976Sjmallett#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3) 634215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 635215976Sjmallettstatic inline uint64_t CVMX_PCI_PKT_CREDITSX(unsigned long offset) 636215976Sjmallett{ 637215976Sjmallett if (!( 638215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 639215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 640215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 641215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 642215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 643215976Sjmallett cvmx_warn("CVMX_PCI_PKT_CREDITSX(%lu) is invalid on this chip\n", offset); 644215976Sjmallett return 0x0000000000000044ull + ((offset) & 3) * 16; 645215976Sjmallett} 646215976Sjmallett#else 647215976Sjmallett#define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16) 648215976Sjmallett#endif 649215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650215976Sjmallett#define CVMX_PCI_READ_CMD_6 CVMX_PCI_READ_CMD_6_FUNC() 651215976Sjmallettstatic inline uint64_t CVMX_PCI_READ_CMD_6_FUNC(void) 652215976Sjmallett{ 653215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 654215976Sjmallett cvmx_warn("CVMX_PCI_READ_CMD_6 not supported on this chip\n"); 655215976Sjmallett return 0x0000000000000180ull; 656215976Sjmallett} 657215976Sjmallett#else 658215976Sjmallett#define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull) 659215976Sjmallett#endif 660215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661215976Sjmallett#define CVMX_PCI_READ_CMD_C CVMX_PCI_READ_CMD_C_FUNC() 662215976Sjmallettstatic inline uint64_t CVMX_PCI_READ_CMD_C_FUNC(void) 663215976Sjmallett{ 664215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 665215976Sjmallett cvmx_warn("CVMX_PCI_READ_CMD_C not supported on this chip\n"); 666215976Sjmallett return 0x0000000000000184ull; 667215976Sjmallett} 668215976Sjmallett#else 669215976Sjmallett#define CVMX_PCI_READ_CMD_C (0x0000000000000184ull) 670215976Sjmallett#endif 671215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672215976Sjmallett#define CVMX_PCI_READ_CMD_E CVMX_PCI_READ_CMD_E_FUNC() 673215976Sjmallettstatic inline uint64_t CVMX_PCI_READ_CMD_E_FUNC(void) 674215976Sjmallett{ 675215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 676215976Sjmallett cvmx_warn("CVMX_PCI_READ_CMD_E not supported on this chip\n"); 677215976Sjmallett return 0x0000000000000188ull; 678215976Sjmallett} 679215976Sjmallett#else 680215976Sjmallett#define CVMX_PCI_READ_CMD_E (0x0000000000000188ull) 681215976Sjmallett#endif 682215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 683215976Sjmallett#define CVMX_PCI_READ_TIMEOUT CVMX_PCI_READ_TIMEOUT_FUNC() 684215976Sjmallettstatic inline uint64_t CVMX_PCI_READ_TIMEOUT_FUNC(void) 685215976Sjmallett{ 686215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 687215976Sjmallett cvmx_warn("CVMX_PCI_READ_TIMEOUT not supported on this chip\n"); 688215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000000B0ull); 689215976Sjmallett} 690215976Sjmallett#else 691215976Sjmallett#define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull)) 692215976Sjmallett#endif 693215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 694215976Sjmallett#define CVMX_PCI_SCM_REG CVMX_PCI_SCM_REG_FUNC() 695215976Sjmallettstatic inline uint64_t CVMX_PCI_SCM_REG_FUNC(void) 696215976Sjmallett{ 697215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 698215976Sjmallett cvmx_warn("CVMX_PCI_SCM_REG not supported on this chip\n"); 699215976Sjmallett return 0x00000000000001A8ull; 700215976Sjmallett} 701215976Sjmallett#else 702215976Sjmallett#define CVMX_PCI_SCM_REG (0x00000000000001A8ull) 703215976Sjmallett#endif 704215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 705215976Sjmallett#define CVMX_PCI_TSR_REG CVMX_PCI_TSR_REG_FUNC() 706215976Sjmallettstatic inline uint64_t CVMX_PCI_TSR_REG_FUNC(void) 707215976Sjmallett{ 708215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 709215976Sjmallett cvmx_warn("CVMX_PCI_TSR_REG not supported on this chip\n"); 710215976Sjmallett return 0x00000000000001B0ull; 711215976Sjmallett} 712215976Sjmallett#else 713215976Sjmallett#define CVMX_PCI_TSR_REG (0x00000000000001B0ull) 714215976Sjmallett#endif 715215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716215976Sjmallett#define CVMX_PCI_WIN_RD_ADDR CVMX_PCI_WIN_RD_ADDR_FUNC() 717215976Sjmallettstatic inline uint64_t CVMX_PCI_WIN_RD_ADDR_FUNC(void) 718215976Sjmallett{ 719215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 720215976Sjmallett cvmx_warn("CVMX_PCI_WIN_RD_ADDR not supported on this chip\n"); 721215976Sjmallett return 0x0000000000000008ull; 722215976Sjmallett} 723215976Sjmallett#else 724215976Sjmallett#define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull) 725215976Sjmallett#endif 726215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 727215976Sjmallett#define CVMX_PCI_WIN_RD_DATA CVMX_PCI_WIN_RD_DATA_FUNC() 728215976Sjmallettstatic inline uint64_t CVMX_PCI_WIN_RD_DATA_FUNC(void) 729215976Sjmallett{ 730215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 731215976Sjmallett cvmx_warn("CVMX_PCI_WIN_RD_DATA not supported on this chip\n"); 732215976Sjmallett return 0x0000000000000020ull; 733215976Sjmallett} 734215976Sjmallett#else 735215976Sjmallett#define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull) 736215976Sjmallett#endif 737215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 738215976Sjmallett#define CVMX_PCI_WIN_WR_ADDR CVMX_PCI_WIN_WR_ADDR_FUNC() 739215976Sjmallettstatic inline uint64_t CVMX_PCI_WIN_WR_ADDR_FUNC(void) 740215976Sjmallett{ 741215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 742215976Sjmallett cvmx_warn("CVMX_PCI_WIN_WR_ADDR not supported on this chip\n"); 743215976Sjmallett return 0x0000000000000000ull; 744215976Sjmallett} 745215976Sjmallett#else 746215976Sjmallett#define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull) 747215976Sjmallett#endif 748215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 749215976Sjmallett#define CVMX_PCI_WIN_WR_DATA CVMX_PCI_WIN_WR_DATA_FUNC() 750215976Sjmallettstatic inline uint64_t CVMX_PCI_WIN_WR_DATA_FUNC(void) 751215976Sjmallett{ 752215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 753215976Sjmallett cvmx_warn("CVMX_PCI_WIN_WR_DATA not supported on this chip\n"); 754215976Sjmallett return 0x0000000000000010ull; 755215976Sjmallett} 756215976Sjmallett#else 757215976Sjmallett#define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull) 758215976Sjmallett#endif 759215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 760215976Sjmallett#define CVMX_PCI_WIN_WR_MASK CVMX_PCI_WIN_WR_MASK_FUNC() 761215976Sjmallettstatic inline uint64_t CVMX_PCI_WIN_WR_MASK_FUNC(void) 762215976Sjmallett{ 763215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 764215976Sjmallett cvmx_warn("CVMX_PCI_WIN_WR_MASK not supported on this chip\n"); 765215976Sjmallett return 0x0000000000000018ull; 766215976Sjmallett} 767215976Sjmallett#else 768215976Sjmallett#define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull) 769215976Sjmallett#endif 770215976Sjmallett 771215976Sjmallett/** 772215976Sjmallett * cvmx_pci_bar1_index# 773215976Sjmallett * 774215976Sjmallett * PCI_BAR1_INDEXX = PCI IndexX Register 775215976Sjmallett * 776215976Sjmallett * Contains address index and control bits for access to memory ranges of Bar-1, 777215976Sjmallett * when PCI supplied address-bits [26:22] == X. 778215976Sjmallett */ 779215976Sjmallettunion cvmx_pci_bar1_indexx 780215976Sjmallett{ 781215976Sjmallett uint32_t u32; 782215976Sjmallett struct cvmx_pci_bar1_indexx_s 783215976Sjmallett { 784215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 785215976Sjmallett uint32_t reserved_18_31 : 14; 786215976Sjmallett uint32_t addr_idx : 14; /**< Address bits [35:22] sent to L2C */ 787215976Sjmallett uint32_t ca : 1; /**< Set '1' when access is not to be cached in L2. */ 788215976Sjmallett uint32_t end_swp : 2; /**< Endian Swap Mode */ 789215976Sjmallett uint32_t addr_v : 1; /**< Set '1' when the selected address range is valid. */ 790215976Sjmallett#else 791215976Sjmallett uint32_t addr_v : 1; 792215976Sjmallett uint32_t end_swp : 2; 793215976Sjmallett uint32_t ca : 1; 794215976Sjmallett uint32_t addr_idx : 14; 795215976Sjmallett uint32_t reserved_18_31 : 14; 796215976Sjmallett#endif 797215976Sjmallett } s; 798215976Sjmallett struct cvmx_pci_bar1_indexx_s cn30xx; 799215976Sjmallett struct cvmx_pci_bar1_indexx_s cn31xx; 800215976Sjmallett struct cvmx_pci_bar1_indexx_s cn38xx; 801215976Sjmallett struct cvmx_pci_bar1_indexx_s cn38xxp2; 802215976Sjmallett struct cvmx_pci_bar1_indexx_s cn50xx; 803215976Sjmallett struct cvmx_pci_bar1_indexx_s cn58xx; 804215976Sjmallett struct cvmx_pci_bar1_indexx_s cn58xxp1; 805215976Sjmallett}; 806215976Sjmalletttypedef union cvmx_pci_bar1_indexx cvmx_pci_bar1_indexx_t; 807215976Sjmallett 808215976Sjmallett/** 809215976Sjmallett * cvmx_pci_bist_reg 810215976Sjmallett * 811215976Sjmallett * PCI_BIST_REG = PCI PNI BIST Status Register 812215976Sjmallett * 813215976Sjmallett * Contains the bist results for the PNI memories. 814215976Sjmallett */ 815215976Sjmallettunion cvmx_pci_bist_reg 816215976Sjmallett{ 817215976Sjmallett uint64_t u64; 818215976Sjmallett struct cvmx_pci_bist_reg_s 819215976Sjmallett { 820215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 821215976Sjmallett uint64_t reserved_10_63 : 54; 822215976Sjmallett uint64_t rsp_bs : 1; /**< Bist Status For b12_rsp_fifo_bist 823215976Sjmallett The value of this register is available 100,000 824215976Sjmallett core clocks + 21,000 pclks after: 825215976Sjmallett Host Mode - deassertion of pci_rst_n 826215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 827215976Sjmallett uint64_t dma0_bs : 1; /**< Bist Status For dmao_count 828215976Sjmallett The value of this register is available 100,000 829215976Sjmallett core clocks + 21,000 pclks after: 830215976Sjmallett Host Mode - deassertion of pci_rst_n 831215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 832215976Sjmallett uint64_t cmd0_bs : 1; /**< Bist Status For npi_cmd0_pni_am0 833215976Sjmallett The value of this register is available 100,000 834215976Sjmallett core clocks + 21,000 pclks after: 835215976Sjmallett Host Mode - deassertion of pci_rst_n 836215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 837215976Sjmallett uint64_t cmd_bs : 1; /**< Bist Status For npi_cmd_pni_am1 838215976Sjmallett The value of this register is available 100,000 839215976Sjmallett core clocks + 21,000 pclks after: 840215976Sjmallett Host Mode - deassertion of pci_rst_n 841215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 842215976Sjmallett uint64_t csr2p_bs : 1; /**< Bist Status For npi_csr_2_pni_am 843215976Sjmallett The value of this register is available 100,000 844215976Sjmallett core clocks + 21,000 pclks after: 845215976Sjmallett Host Mode - deassertion of pci_rst_n 846215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 847215976Sjmallett uint64_t csrr_bs : 1; /**< Bist Status For npi_csr_rsp_2_pni_am 848215976Sjmallett The value of this register is available 100,000 849215976Sjmallett core clocks + 21,000 pclks after: 850215976Sjmallett Host Mode - deassertion of pci_rst_n 851215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 852215976Sjmallett uint64_t rsp2p_bs : 1; /**< Bist Status For npi_rsp_2_pni_am 853215976Sjmallett The value of this register is available 100,000 854215976Sjmallett core clocks + 21,000 pclks after: 855215976Sjmallett Host Mode - deassertion of pci_rst_n 856215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 857215976Sjmallett uint64_t csr2n_bs : 1; /**< Bist Status For pni_csr_2_npi_am 858215976Sjmallett The value of this register is available 100,000 859215976Sjmallett core clocks + 21,000 pclks after: 860215976Sjmallett Host Mode - deassertion of pci_rst_n 861215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 862215976Sjmallett uint64_t dat2n_bs : 1; /**< Bist Status For pni_data_2_npi_am 863215976Sjmallett The value of this register is available 100,000 864215976Sjmallett core clocks + 21,000 pclks after: 865215976Sjmallett Host Mode - deassertion of pci_rst_n 866215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 867215976Sjmallett uint64_t dbg2n_bs : 1; /**< Bist Status For pni_dbg_data_2_npi_am 868215976Sjmallett The value of this register is available 100,000 869215976Sjmallett core clocks + 21,000 pclks after: 870215976Sjmallett Host Mode - deassertion of pci_rst_n 871215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 872215976Sjmallett#else 873215976Sjmallett uint64_t dbg2n_bs : 1; 874215976Sjmallett uint64_t dat2n_bs : 1; 875215976Sjmallett uint64_t csr2n_bs : 1; 876215976Sjmallett uint64_t rsp2p_bs : 1; 877215976Sjmallett uint64_t csrr_bs : 1; 878215976Sjmallett uint64_t csr2p_bs : 1; 879215976Sjmallett uint64_t cmd_bs : 1; 880215976Sjmallett uint64_t cmd0_bs : 1; 881215976Sjmallett uint64_t dma0_bs : 1; 882215976Sjmallett uint64_t rsp_bs : 1; 883215976Sjmallett uint64_t reserved_10_63 : 54; 884215976Sjmallett#endif 885215976Sjmallett } s; 886215976Sjmallett struct cvmx_pci_bist_reg_s cn50xx; 887215976Sjmallett}; 888215976Sjmalletttypedef union cvmx_pci_bist_reg cvmx_pci_bist_reg_t; 889215976Sjmallett 890215976Sjmallett/** 891215976Sjmallett * cvmx_pci_cfg00 892215976Sjmallett * 893215976Sjmallett * Registers at address 0x1000 -> 0x17FF are PNI 894215976Sjmallett * Start at 0x100 into range 895215976Sjmallett * these are shifted by 2 to the left to make address 896215976Sjmallett * Registers at address 0x1800 -> 0x18FF are CFG 897215976Sjmallett * these are shifted by 2 to the left to make address 898215976Sjmallett * 899215976Sjmallett * PCI_CFG00 = First 32-bits of PCI config space (PCI Vendor + Device) 900215976Sjmallett * 901215976Sjmallett * This register contains the first 32-bits of the PCI config space registers 902215976Sjmallett */ 903215976Sjmallettunion cvmx_pci_cfg00 904215976Sjmallett{ 905215976Sjmallett uint32_t u32; 906215976Sjmallett struct cvmx_pci_cfg00_s 907215976Sjmallett { 908215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 909215976Sjmallett uint32_t devid : 16; /**< This is the device ID for OCTEON (90nm shhrink) */ 910215976Sjmallett uint32_t vendid : 16; /**< This is the Cavium's vendor ID */ 911215976Sjmallett#else 912215976Sjmallett uint32_t vendid : 16; 913215976Sjmallett uint32_t devid : 16; 914215976Sjmallett#endif 915215976Sjmallett } s; 916215976Sjmallett struct cvmx_pci_cfg00_s cn30xx; 917215976Sjmallett struct cvmx_pci_cfg00_s cn31xx; 918215976Sjmallett struct cvmx_pci_cfg00_s cn38xx; 919215976Sjmallett struct cvmx_pci_cfg00_s cn38xxp2; 920215976Sjmallett struct cvmx_pci_cfg00_s cn50xx; 921215976Sjmallett struct cvmx_pci_cfg00_s cn58xx; 922215976Sjmallett struct cvmx_pci_cfg00_s cn58xxp1; 923215976Sjmallett}; 924215976Sjmalletttypedef union cvmx_pci_cfg00 cvmx_pci_cfg00_t; 925215976Sjmallett 926215976Sjmallett/** 927215976Sjmallett * cvmx_pci_cfg01 928215976Sjmallett * 929215976Sjmallett * PCI_CFG01 = Second 32-bits of PCI config space (Command/Status Register) 930215976Sjmallett * 931215976Sjmallett */ 932215976Sjmallettunion cvmx_pci_cfg01 933215976Sjmallett{ 934215976Sjmallett uint32_t u32; 935215976Sjmallett struct cvmx_pci_cfg01_s 936215976Sjmallett { 937215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 938215976Sjmallett uint32_t dpe : 1; /**< Detected Parity Error */ 939215976Sjmallett uint32_t sse : 1; /**< Signaled System Error */ 940215976Sjmallett uint32_t rma : 1; /**< Received Master Abort */ 941215976Sjmallett uint32_t rta : 1; /**< Received Target Abort */ 942215976Sjmallett uint32_t sta : 1; /**< Signaled Target Abort */ 943215976Sjmallett uint32_t devt : 2; /**< DEVSEL# timing (for PCI only/for PCIX = don't care) */ 944215976Sjmallett uint32_t mdpe : 1; /**< Master Data Parity Error */ 945215976Sjmallett uint32_t fbb : 1; /**< Fast Back-to-Back Transactions Capable 946215976Sjmallett Mode Dependent (1 = PCI Mode / 0 = PCIX Mode) */ 947215976Sjmallett uint32_t reserved_22_22 : 1; 948215976Sjmallett uint32_t m66 : 1; /**< 66MHz Capable */ 949215976Sjmallett uint32_t cle : 1; /**< Capabilities List Enable */ 950215976Sjmallett uint32_t i_stat : 1; /**< When INTx# is asserted by OCTEON this bit will be set. 951215976Sjmallett When deasserted by OCTEON this bit will be cleared. */ 952215976Sjmallett uint32_t reserved_11_18 : 8; 953215976Sjmallett uint32_t i_dis : 1; /**< When asserted '1' disables the generation of INTx# 954215976Sjmallett by OCTEON. When disabled '0' allows assertion of INTx# 955215976Sjmallett by OCTEON. */ 956215976Sjmallett uint32_t fbbe : 1; /**< Fast Back to Back Transaction Enable */ 957215976Sjmallett uint32_t see : 1; /**< System Error Enable */ 958215976Sjmallett uint32_t ads : 1; /**< Address/Data Stepping 959215976Sjmallett NOTE: Octeon does NOT support address/data stepping. */ 960215976Sjmallett uint32_t pee : 1; /**< PERR# Enable */ 961215976Sjmallett uint32_t vps : 1; /**< VGA Palette Snooping */ 962215976Sjmallett uint32_t mwice : 1; /**< Memory Write & Invalidate Command Enable */ 963215976Sjmallett uint32_t scse : 1; /**< Special Cycle Snooping Enable */ 964215976Sjmallett uint32_t me : 1; /**< Master Enable 965215976Sjmallett Must be set for OCTEON to master a PCI/PCI-X 966215976Sjmallett transaction. This should always be set any time 967215976Sjmallett that OCTEON is connected to a PCI/PCI-X bus. */ 968215976Sjmallett uint32_t msae : 1; /**< Memory Space Access Enable 969215976Sjmallett Must be set to recieve a PCI/PCI-X memory space 970215976Sjmallett transaction. This must always be set any time that 971215976Sjmallett OCTEON is connected to a PCI/PCI-X bus. */ 972215976Sjmallett uint32_t isae : 1; /**< I/O Space Access Enable 973215976Sjmallett NOTE: For OCTEON, this bit MUST NEVER be set 974215976Sjmallett (it is read-only and OCTEON does not respond to I/O 975215976Sjmallett Space accesses). */ 976215976Sjmallett#else 977215976Sjmallett uint32_t isae : 1; 978215976Sjmallett uint32_t msae : 1; 979215976Sjmallett uint32_t me : 1; 980215976Sjmallett uint32_t scse : 1; 981215976Sjmallett uint32_t mwice : 1; 982215976Sjmallett uint32_t vps : 1; 983215976Sjmallett uint32_t pee : 1; 984215976Sjmallett uint32_t ads : 1; 985215976Sjmallett uint32_t see : 1; 986215976Sjmallett uint32_t fbbe : 1; 987215976Sjmallett uint32_t i_dis : 1; 988215976Sjmallett uint32_t reserved_11_18 : 8; 989215976Sjmallett uint32_t i_stat : 1; 990215976Sjmallett uint32_t cle : 1; 991215976Sjmallett uint32_t m66 : 1; 992215976Sjmallett uint32_t reserved_22_22 : 1; 993215976Sjmallett uint32_t fbb : 1; 994215976Sjmallett uint32_t mdpe : 1; 995215976Sjmallett uint32_t devt : 2; 996215976Sjmallett uint32_t sta : 1; 997215976Sjmallett uint32_t rta : 1; 998215976Sjmallett uint32_t rma : 1; 999215976Sjmallett uint32_t sse : 1; 1000215976Sjmallett uint32_t dpe : 1; 1001215976Sjmallett#endif 1002215976Sjmallett } s; 1003215976Sjmallett struct cvmx_pci_cfg01_s cn30xx; 1004215976Sjmallett struct cvmx_pci_cfg01_s cn31xx; 1005215976Sjmallett struct cvmx_pci_cfg01_s cn38xx; 1006215976Sjmallett struct cvmx_pci_cfg01_s cn38xxp2; 1007215976Sjmallett struct cvmx_pci_cfg01_s cn50xx; 1008215976Sjmallett struct cvmx_pci_cfg01_s cn58xx; 1009215976Sjmallett struct cvmx_pci_cfg01_s cn58xxp1; 1010215976Sjmallett}; 1011215976Sjmalletttypedef union cvmx_pci_cfg01 cvmx_pci_cfg01_t; 1012215976Sjmallett 1013215976Sjmallett/** 1014215976Sjmallett * cvmx_pci_cfg02 1015215976Sjmallett * 1016215976Sjmallett * PCI_CFG02 = Third 32-bits of PCI config space (Class Code / Revision ID) 1017215976Sjmallett * 1018215976Sjmallett */ 1019215976Sjmallettunion cvmx_pci_cfg02 1020215976Sjmallett{ 1021215976Sjmallett uint32_t u32; 1022215976Sjmallett struct cvmx_pci_cfg02_s 1023215976Sjmallett { 1024215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1025215976Sjmallett uint32_t cc : 24; /**< Class Code (Processor/MIPS) 1026215976Sjmallett (was 0x100000 in pass 1 and pass 2) */ 1027215976Sjmallett uint32_t rid : 8; /**< Revision ID 1028215976Sjmallett (0 in pass 1, 1 in pass 1.1, 8 in pass 2.0) */ 1029215976Sjmallett#else 1030215976Sjmallett uint32_t rid : 8; 1031215976Sjmallett uint32_t cc : 24; 1032215976Sjmallett#endif 1033215976Sjmallett } s; 1034215976Sjmallett struct cvmx_pci_cfg02_s cn30xx; 1035215976Sjmallett struct cvmx_pci_cfg02_s cn31xx; 1036215976Sjmallett struct cvmx_pci_cfg02_s cn38xx; 1037215976Sjmallett struct cvmx_pci_cfg02_s cn38xxp2; 1038215976Sjmallett struct cvmx_pci_cfg02_s cn50xx; 1039215976Sjmallett struct cvmx_pci_cfg02_s cn58xx; 1040215976Sjmallett struct cvmx_pci_cfg02_s cn58xxp1; 1041215976Sjmallett}; 1042215976Sjmalletttypedef union cvmx_pci_cfg02 cvmx_pci_cfg02_t; 1043215976Sjmallett 1044215976Sjmallett/** 1045215976Sjmallett * cvmx_pci_cfg03 1046215976Sjmallett * 1047215976Sjmallett * PCI_CFG03 = Fourth 32-bits of PCI config space (BIST, HEADER Type, Latency timer, line size) 1048215976Sjmallett * 1049215976Sjmallett */ 1050215976Sjmallettunion cvmx_pci_cfg03 1051215976Sjmallett{ 1052215976Sjmallett uint32_t u32; 1053215976Sjmallett struct cvmx_pci_cfg03_s 1054215976Sjmallett { 1055215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1056215976Sjmallett uint32_t bcap : 1; /**< BIST Capable */ 1057215976Sjmallett uint32_t brb : 1; /**< BIST Request/busy bit 1058215976Sjmallett Note: OCTEON does not support PCI BIST, therefore 1059215976Sjmallett this bit should remain zero. */ 1060215976Sjmallett uint32_t reserved_28_29 : 2; 1061215976Sjmallett uint32_t bcod : 4; /**< BIST Code */ 1062215976Sjmallett uint32_t ht : 8; /**< Header Type (Type 0) */ 1063215976Sjmallett uint32_t lt : 8; /**< Latency Timer 1064215976Sjmallett (0=PCI) (0=PCI) 1065215976Sjmallett (0x40=PCIX) (0x40=PCIX) */ 1066215976Sjmallett uint32_t cls : 8; /**< Cache Line Size */ 1067215976Sjmallett#else 1068215976Sjmallett uint32_t cls : 8; 1069215976Sjmallett uint32_t lt : 8; 1070215976Sjmallett uint32_t ht : 8; 1071215976Sjmallett uint32_t bcod : 4; 1072215976Sjmallett uint32_t reserved_28_29 : 2; 1073215976Sjmallett uint32_t brb : 1; 1074215976Sjmallett uint32_t bcap : 1; 1075215976Sjmallett#endif 1076215976Sjmallett } s; 1077215976Sjmallett struct cvmx_pci_cfg03_s cn30xx; 1078215976Sjmallett struct cvmx_pci_cfg03_s cn31xx; 1079215976Sjmallett struct cvmx_pci_cfg03_s cn38xx; 1080215976Sjmallett struct cvmx_pci_cfg03_s cn38xxp2; 1081215976Sjmallett struct cvmx_pci_cfg03_s cn50xx; 1082215976Sjmallett struct cvmx_pci_cfg03_s cn58xx; 1083215976Sjmallett struct cvmx_pci_cfg03_s cn58xxp1; 1084215976Sjmallett}; 1085215976Sjmalletttypedef union cvmx_pci_cfg03 cvmx_pci_cfg03_t; 1086215976Sjmallett 1087215976Sjmallett/** 1088215976Sjmallett * cvmx_pci_cfg04 1089215976Sjmallett * 1090215976Sjmallett * PCI_CFG04 = Fifth 32-bits of PCI config space (Base Address Register 0 - Low) 1091215976Sjmallett * 1092215976Sjmallett * Description: BAR0: 4KB 64-bit Prefetchable Memory Space 1093215976Sjmallett * [0]: 0 (Memory Space) 1094215976Sjmallett * [2:1]: 2 (64bit memory decoder) 1095215976Sjmallett * [3]: 1 (Prefetchable) 1096215976Sjmallett * [11:4]: RAZ (to imply 4KB space) 1097215976Sjmallett * [31:12]: RW (User may define base address) 1098215976Sjmallett */ 1099215976Sjmallettunion cvmx_pci_cfg04 1100215976Sjmallett{ 1101215976Sjmallett uint32_t u32; 1102215976Sjmallett struct cvmx_pci_cfg04_s 1103215976Sjmallett { 1104215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1105215976Sjmallett uint32_t lbase : 20; /**< Base Address[31:12] 1106215976Sjmallett Base Address[30:12] read as zero if 1107215976Sjmallett PCI_CTL_STATUS_2[BB0] is set (in pass 3+) */ 1108215976Sjmallett uint32_t lbasez : 8; /**< Base Address[11:4] (Read as Zero) */ 1109215976Sjmallett uint32_t pf : 1; /**< Prefetchable Space */ 1110215976Sjmallett uint32_t typ : 2; /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */ 1111215976Sjmallett uint32_t mspc : 1; /**< Memory Space Indicator */ 1112215976Sjmallett#else 1113215976Sjmallett uint32_t mspc : 1; 1114215976Sjmallett uint32_t typ : 2; 1115215976Sjmallett uint32_t pf : 1; 1116215976Sjmallett uint32_t lbasez : 8; 1117215976Sjmallett uint32_t lbase : 20; 1118215976Sjmallett#endif 1119215976Sjmallett } s; 1120215976Sjmallett struct cvmx_pci_cfg04_s cn30xx; 1121215976Sjmallett struct cvmx_pci_cfg04_s cn31xx; 1122215976Sjmallett struct cvmx_pci_cfg04_s cn38xx; 1123215976Sjmallett struct cvmx_pci_cfg04_s cn38xxp2; 1124215976Sjmallett struct cvmx_pci_cfg04_s cn50xx; 1125215976Sjmallett struct cvmx_pci_cfg04_s cn58xx; 1126215976Sjmallett struct cvmx_pci_cfg04_s cn58xxp1; 1127215976Sjmallett}; 1128215976Sjmalletttypedef union cvmx_pci_cfg04 cvmx_pci_cfg04_t; 1129215976Sjmallett 1130215976Sjmallett/** 1131215976Sjmallett * cvmx_pci_cfg05 1132215976Sjmallett * 1133215976Sjmallett * PCI_CFG05 = Sixth 32-bits of PCI config space (Base Address Register 0 - High) 1134215976Sjmallett * 1135215976Sjmallett */ 1136215976Sjmallettunion cvmx_pci_cfg05 1137215976Sjmallett{ 1138215976Sjmallett uint32_t u32; 1139215976Sjmallett struct cvmx_pci_cfg05_s 1140215976Sjmallett { 1141215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1142215976Sjmallett uint32_t hbase : 32; /**< Base Address[63:32] */ 1143215976Sjmallett#else 1144215976Sjmallett uint32_t hbase : 32; 1145215976Sjmallett#endif 1146215976Sjmallett } s; 1147215976Sjmallett struct cvmx_pci_cfg05_s cn30xx; 1148215976Sjmallett struct cvmx_pci_cfg05_s cn31xx; 1149215976Sjmallett struct cvmx_pci_cfg05_s cn38xx; 1150215976Sjmallett struct cvmx_pci_cfg05_s cn38xxp2; 1151215976Sjmallett struct cvmx_pci_cfg05_s cn50xx; 1152215976Sjmallett struct cvmx_pci_cfg05_s cn58xx; 1153215976Sjmallett struct cvmx_pci_cfg05_s cn58xxp1; 1154215976Sjmallett}; 1155215976Sjmalletttypedef union cvmx_pci_cfg05 cvmx_pci_cfg05_t; 1156215976Sjmallett 1157215976Sjmallett/** 1158215976Sjmallett * cvmx_pci_cfg06 1159215976Sjmallett * 1160215976Sjmallett * PCI_CFG06 = Seventh 32-bits of PCI config space (Base Address Register 1 - Low) 1161215976Sjmallett * 1162215976Sjmallett * Description: BAR1: 128MB 64-bit Prefetchable Memory Space 1163215976Sjmallett * [0]: 0 (Memory Space) 1164215976Sjmallett * [2:1]: 2 (64bit memory decoder) 1165215976Sjmallett * [3]: 1 (Prefetchable) 1166215976Sjmallett * [26:4]: RAZ (to imply 128MB space) 1167215976Sjmallett * [31:27]: RW (User may define base address) 1168215976Sjmallett */ 1169215976Sjmallettunion cvmx_pci_cfg06 1170215976Sjmallett{ 1171215976Sjmallett uint32_t u32; 1172215976Sjmallett struct cvmx_pci_cfg06_s 1173215976Sjmallett { 1174215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1175215976Sjmallett uint32_t lbase : 5; /**< Base Address[31:27] 1176215976Sjmallett In pass 3+: 1177215976Sjmallett Base Address[29:27] read as zero if 1178215976Sjmallett PCI_CTL_STATUS_2[BB1] is set 1179215976Sjmallett Base Address[30] reads as zero if 1180215976Sjmallett PCI_CTL_STATUS_2[BB1] is set and 1181215976Sjmallett PCI_CTL_STATUS_2[BB1_SIZE] is set */ 1182215976Sjmallett uint32_t lbasez : 23; /**< Base Address[26:4] (Read as Zero) */ 1183215976Sjmallett uint32_t pf : 1; /**< Prefetchable Space */ 1184215976Sjmallett uint32_t typ : 2; /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */ 1185215976Sjmallett uint32_t mspc : 1; /**< Memory Space Indicator */ 1186215976Sjmallett#else 1187215976Sjmallett uint32_t mspc : 1; 1188215976Sjmallett uint32_t typ : 2; 1189215976Sjmallett uint32_t pf : 1; 1190215976Sjmallett uint32_t lbasez : 23; 1191215976Sjmallett uint32_t lbase : 5; 1192215976Sjmallett#endif 1193215976Sjmallett } s; 1194215976Sjmallett struct cvmx_pci_cfg06_s cn30xx; 1195215976Sjmallett struct cvmx_pci_cfg06_s cn31xx; 1196215976Sjmallett struct cvmx_pci_cfg06_s cn38xx; 1197215976Sjmallett struct cvmx_pci_cfg06_s cn38xxp2; 1198215976Sjmallett struct cvmx_pci_cfg06_s cn50xx; 1199215976Sjmallett struct cvmx_pci_cfg06_s cn58xx; 1200215976Sjmallett struct cvmx_pci_cfg06_s cn58xxp1; 1201215976Sjmallett}; 1202215976Sjmalletttypedef union cvmx_pci_cfg06 cvmx_pci_cfg06_t; 1203215976Sjmallett 1204215976Sjmallett/** 1205215976Sjmallett * cvmx_pci_cfg07 1206215976Sjmallett * 1207215976Sjmallett * PCI_CFG07 = Eighth 32-bits of PCI config space (Base Address Register 1 - High) 1208215976Sjmallett * 1209215976Sjmallett */ 1210215976Sjmallettunion cvmx_pci_cfg07 1211215976Sjmallett{ 1212215976Sjmallett uint32_t u32; 1213215976Sjmallett struct cvmx_pci_cfg07_s 1214215976Sjmallett { 1215215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1216215976Sjmallett uint32_t hbase : 32; /**< Base Address[63:32] */ 1217215976Sjmallett#else 1218215976Sjmallett uint32_t hbase : 32; 1219215976Sjmallett#endif 1220215976Sjmallett } s; 1221215976Sjmallett struct cvmx_pci_cfg07_s cn30xx; 1222215976Sjmallett struct cvmx_pci_cfg07_s cn31xx; 1223215976Sjmallett struct cvmx_pci_cfg07_s cn38xx; 1224215976Sjmallett struct cvmx_pci_cfg07_s cn38xxp2; 1225215976Sjmallett struct cvmx_pci_cfg07_s cn50xx; 1226215976Sjmallett struct cvmx_pci_cfg07_s cn58xx; 1227215976Sjmallett struct cvmx_pci_cfg07_s cn58xxp1; 1228215976Sjmallett}; 1229215976Sjmalletttypedef union cvmx_pci_cfg07 cvmx_pci_cfg07_t; 1230215976Sjmallett 1231215976Sjmallett/** 1232215976Sjmallett * cvmx_pci_cfg08 1233215976Sjmallett * 1234215976Sjmallett * PCI_CFG08 = Ninth 32-bits of PCI config space (Base Address Register 2 - Low) 1235215976Sjmallett * 1236215976Sjmallett * Description: BAR1: 2^39 (512GB) 64-bit Prefetchable Memory Space 1237215976Sjmallett * [0]: 0 (Memory Space) 1238215976Sjmallett * [2:1]: 2 (64bit memory decoder) 1239215976Sjmallett * [3]: 1 (Prefetchable) 1240215976Sjmallett * [31:4]: RAZ 1241215976Sjmallett */ 1242215976Sjmallettunion cvmx_pci_cfg08 1243215976Sjmallett{ 1244215976Sjmallett uint32_t u32; 1245215976Sjmallett struct cvmx_pci_cfg08_s 1246215976Sjmallett { 1247215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1248215976Sjmallett uint32_t lbasez : 28; /**< Base Address[31:4] (Read as Zero) */ 1249215976Sjmallett uint32_t pf : 1; /**< Prefetchable Space */ 1250215976Sjmallett uint32_t typ : 2; /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */ 1251215976Sjmallett uint32_t mspc : 1; /**< Memory Space Indicator */ 1252215976Sjmallett#else 1253215976Sjmallett uint32_t mspc : 1; 1254215976Sjmallett uint32_t typ : 2; 1255215976Sjmallett uint32_t pf : 1; 1256215976Sjmallett uint32_t lbasez : 28; 1257215976Sjmallett#endif 1258215976Sjmallett } s; 1259215976Sjmallett struct cvmx_pci_cfg08_s cn30xx; 1260215976Sjmallett struct cvmx_pci_cfg08_s cn31xx; 1261215976Sjmallett struct cvmx_pci_cfg08_s cn38xx; 1262215976Sjmallett struct cvmx_pci_cfg08_s cn38xxp2; 1263215976Sjmallett struct cvmx_pci_cfg08_s cn50xx; 1264215976Sjmallett struct cvmx_pci_cfg08_s cn58xx; 1265215976Sjmallett struct cvmx_pci_cfg08_s cn58xxp1; 1266215976Sjmallett}; 1267215976Sjmalletttypedef union cvmx_pci_cfg08 cvmx_pci_cfg08_t; 1268215976Sjmallett 1269215976Sjmallett/** 1270215976Sjmallett * cvmx_pci_cfg09 1271215976Sjmallett * 1272215976Sjmallett * PCI_CFG09 = Tenth 32-bits of PCI config space (Base Address Register 2 - High) 1273215976Sjmallett * 1274215976Sjmallett */ 1275215976Sjmallettunion cvmx_pci_cfg09 1276215976Sjmallett{ 1277215976Sjmallett uint32_t u32; 1278215976Sjmallett struct cvmx_pci_cfg09_s 1279215976Sjmallett { 1280215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1281215976Sjmallett uint32_t hbase : 25; /**< Base Address[63:39] */ 1282215976Sjmallett uint32_t hbasez : 7; /**< Base Address[38:31] (Read as Zero) */ 1283215976Sjmallett#else 1284215976Sjmallett uint32_t hbasez : 7; 1285215976Sjmallett uint32_t hbase : 25; 1286215976Sjmallett#endif 1287215976Sjmallett } s; 1288215976Sjmallett struct cvmx_pci_cfg09_s cn30xx; 1289215976Sjmallett struct cvmx_pci_cfg09_s cn31xx; 1290215976Sjmallett struct cvmx_pci_cfg09_s cn38xx; 1291215976Sjmallett struct cvmx_pci_cfg09_s cn38xxp2; 1292215976Sjmallett struct cvmx_pci_cfg09_s cn50xx; 1293215976Sjmallett struct cvmx_pci_cfg09_s cn58xx; 1294215976Sjmallett struct cvmx_pci_cfg09_s cn58xxp1; 1295215976Sjmallett}; 1296215976Sjmalletttypedef union cvmx_pci_cfg09 cvmx_pci_cfg09_t; 1297215976Sjmallett 1298215976Sjmallett/** 1299215976Sjmallett * cvmx_pci_cfg10 1300215976Sjmallett * 1301215976Sjmallett * PCI_CFG10 = Eleventh 32-bits of PCI config space (Card Bus CIS Pointer) 1302215976Sjmallett * 1303215976Sjmallett */ 1304215976Sjmallettunion cvmx_pci_cfg10 1305215976Sjmallett{ 1306215976Sjmallett uint32_t u32; 1307215976Sjmallett struct cvmx_pci_cfg10_s 1308215976Sjmallett { 1309215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1310215976Sjmallett uint32_t cisp : 32; /**< CardBus CIS Pointer (UNUSED) */ 1311215976Sjmallett#else 1312215976Sjmallett uint32_t cisp : 32; 1313215976Sjmallett#endif 1314215976Sjmallett } s; 1315215976Sjmallett struct cvmx_pci_cfg10_s cn30xx; 1316215976Sjmallett struct cvmx_pci_cfg10_s cn31xx; 1317215976Sjmallett struct cvmx_pci_cfg10_s cn38xx; 1318215976Sjmallett struct cvmx_pci_cfg10_s cn38xxp2; 1319215976Sjmallett struct cvmx_pci_cfg10_s cn50xx; 1320215976Sjmallett struct cvmx_pci_cfg10_s cn58xx; 1321215976Sjmallett struct cvmx_pci_cfg10_s cn58xxp1; 1322215976Sjmallett}; 1323215976Sjmalletttypedef union cvmx_pci_cfg10 cvmx_pci_cfg10_t; 1324215976Sjmallett 1325215976Sjmallett/** 1326215976Sjmallett * cvmx_pci_cfg11 1327215976Sjmallett * 1328215976Sjmallett * PCI_CFG11 = Twelfth 32-bits of PCI config space (SubSystem ID/Subsystem Vendor ID Register) 1329215976Sjmallett * 1330215976Sjmallett */ 1331215976Sjmallettunion cvmx_pci_cfg11 1332215976Sjmallett{ 1333215976Sjmallett uint32_t u32; 1334215976Sjmallett struct cvmx_pci_cfg11_s 1335215976Sjmallett { 1336215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1337215976Sjmallett uint32_t ssid : 16; /**< SubSystem ID */ 1338215976Sjmallett uint32_t ssvid : 16; /**< Subsystem Vendor ID */ 1339215976Sjmallett#else 1340215976Sjmallett uint32_t ssvid : 16; 1341215976Sjmallett uint32_t ssid : 16; 1342215976Sjmallett#endif 1343215976Sjmallett } s; 1344215976Sjmallett struct cvmx_pci_cfg11_s cn30xx; 1345215976Sjmallett struct cvmx_pci_cfg11_s cn31xx; 1346215976Sjmallett struct cvmx_pci_cfg11_s cn38xx; 1347215976Sjmallett struct cvmx_pci_cfg11_s cn38xxp2; 1348215976Sjmallett struct cvmx_pci_cfg11_s cn50xx; 1349215976Sjmallett struct cvmx_pci_cfg11_s cn58xx; 1350215976Sjmallett struct cvmx_pci_cfg11_s cn58xxp1; 1351215976Sjmallett}; 1352215976Sjmalletttypedef union cvmx_pci_cfg11 cvmx_pci_cfg11_t; 1353215976Sjmallett 1354215976Sjmallett/** 1355215976Sjmallett * cvmx_pci_cfg12 1356215976Sjmallett * 1357215976Sjmallett * PCI_CFG12 = Thirteenth 32-bits of PCI config space (Expansion ROM Base Address Register) 1358215976Sjmallett * 1359215976Sjmallett */ 1360215976Sjmallettunion cvmx_pci_cfg12 1361215976Sjmallett{ 1362215976Sjmallett uint32_t u32; 1363215976Sjmallett struct cvmx_pci_cfg12_s 1364215976Sjmallett { 1365215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1366215976Sjmallett uint32_t erbar : 16; /**< Expansion ROM Base Address[31:16] 64KB in size */ 1367215976Sjmallett uint32_t erbarz : 5; /**< Expansion ROM Base Base Address (Read as Zero) */ 1368215976Sjmallett uint32_t reserved_1_10 : 10; 1369215976Sjmallett uint32_t erbar_en : 1; /**< Expansion ROM Address Decode Enable */ 1370215976Sjmallett#else 1371215976Sjmallett uint32_t erbar_en : 1; 1372215976Sjmallett uint32_t reserved_1_10 : 10; 1373215976Sjmallett uint32_t erbarz : 5; 1374215976Sjmallett uint32_t erbar : 16; 1375215976Sjmallett#endif 1376215976Sjmallett } s; 1377215976Sjmallett struct cvmx_pci_cfg12_s cn30xx; 1378215976Sjmallett struct cvmx_pci_cfg12_s cn31xx; 1379215976Sjmallett struct cvmx_pci_cfg12_s cn38xx; 1380215976Sjmallett struct cvmx_pci_cfg12_s cn38xxp2; 1381215976Sjmallett struct cvmx_pci_cfg12_s cn50xx; 1382215976Sjmallett struct cvmx_pci_cfg12_s cn58xx; 1383215976Sjmallett struct cvmx_pci_cfg12_s cn58xxp1; 1384215976Sjmallett}; 1385215976Sjmalletttypedef union cvmx_pci_cfg12 cvmx_pci_cfg12_t; 1386215976Sjmallett 1387215976Sjmallett/** 1388215976Sjmallett * cvmx_pci_cfg13 1389215976Sjmallett * 1390215976Sjmallett * PCI_CFG13 = Fourteenth 32-bits of PCI config space (Capabilities Pointer Register) 1391215976Sjmallett * 1392215976Sjmallett */ 1393215976Sjmallettunion cvmx_pci_cfg13 1394215976Sjmallett{ 1395215976Sjmallett uint32_t u32; 1396215976Sjmallett struct cvmx_pci_cfg13_s 1397215976Sjmallett { 1398215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1399215976Sjmallett uint32_t reserved_8_31 : 24; 1400215976Sjmallett uint32_t cp : 8; /**< Capabilities Pointer */ 1401215976Sjmallett#else 1402215976Sjmallett uint32_t cp : 8; 1403215976Sjmallett uint32_t reserved_8_31 : 24; 1404215976Sjmallett#endif 1405215976Sjmallett } s; 1406215976Sjmallett struct cvmx_pci_cfg13_s cn30xx; 1407215976Sjmallett struct cvmx_pci_cfg13_s cn31xx; 1408215976Sjmallett struct cvmx_pci_cfg13_s cn38xx; 1409215976Sjmallett struct cvmx_pci_cfg13_s cn38xxp2; 1410215976Sjmallett struct cvmx_pci_cfg13_s cn50xx; 1411215976Sjmallett struct cvmx_pci_cfg13_s cn58xx; 1412215976Sjmallett struct cvmx_pci_cfg13_s cn58xxp1; 1413215976Sjmallett}; 1414215976Sjmalletttypedef union cvmx_pci_cfg13 cvmx_pci_cfg13_t; 1415215976Sjmallett 1416215976Sjmallett/** 1417215976Sjmallett * cvmx_pci_cfg15 1418215976Sjmallett * 1419215976Sjmallett * PCI_CFG15 = Sixteenth 32-bits of PCI config space (INT/ARB/LATENCY Register) 1420215976Sjmallett * 1421215976Sjmallett */ 1422215976Sjmallettunion cvmx_pci_cfg15 1423215976Sjmallett{ 1424215976Sjmallett uint32_t u32; 1425215976Sjmallett struct cvmx_pci_cfg15_s 1426215976Sjmallett { 1427215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1428215976Sjmallett uint32_t ml : 8; /**< Maximum Latency */ 1429215976Sjmallett uint32_t mg : 8; /**< Minimum Grant */ 1430215976Sjmallett uint32_t inta : 8; /**< Interrupt Pin (INTA#) */ 1431215976Sjmallett uint32_t il : 8; /**< Interrupt Line */ 1432215976Sjmallett#else 1433215976Sjmallett uint32_t il : 8; 1434215976Sjmallett uint32_t inta : 8; 1435215976Sjmallett uint32_t mg : 8; 1436215976Sjmallett uint32_t ml : 8; 1437215976Sjmallett#endif 1438215976Sjmallett } s; 1439215976Sjmallett struct cvmx_pci_cfg15_s cn30xx; 1440215976Sjmallett struct cvmx_pci_cfg15_s cn31xx; 1441215976Sjmallett struct cvmx_pci_cfg15_s cn38xx; 1442215976Sjmallett struct cvmx_pci_cfg15_s cn38xxp2; 1443215976Sjmallett struct cvmx_pci_cfg15_s cn50xx; 1444215976Sjmallett struct cvmx_pci_cfg15_s cn58xx; 1445215976Sjmallett struct cvmx_pci_cfg15_s cn58xxp1; 1446215976Sjmallett}; 1447215976Sjmalletttypedef union cvmx_pci_cfg15 cvmx_pci_cfg15_t; 1448215976Sjmallett 1449215976Sjmallett/** 1450215976Sjmallett * cvmx_pci_cfg16 1451215976Sjmallett * 1452215976Sjmallett * PCI_CFG16 = Seventeenth 32-bits of PCI config space (Target Implementation Register) 1453215976Sjmallett * 1454215976Sjmallett */ 1455215976Sjmallettunion cvmx_pci_cfg16 1456215976Sjmallett{ 1457215976Sjmallett uint32_t u32; 1458215976Sjmallett struct cvmx_pci_cfg16_s 1459215976Sjmallett { 1460215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1461215976Sjmallett uint32_t trdnpr : 1; /**< Target Read Delayed Transaction for I/O and 1462215976Sjmallett non-prefetchable regions discarded. */ 1463215976Sjmallett uint32_t trdard : 1; /**< Target Read Delayed Transaction for all regions 1464215976Sjmallett discarded. */ 1465215976Sjmallett uint32_t rdsati : 1; /**< Target(I/O and Memory) Read Delayed/Split at 1466215976Sjmallett timeout/immediately (default timeout). 1467215976Sjmallett Note: OCTEON requires that this bit MBZ(must be zero). */ 1468215976Sjmallett uint32_t trdrs : 1; /**< Target(I/O and Memory) Read Delayed/Split or Retry 1469215976Sjmallett select (of the application interface is not ready) 1470215976Sjmallett 0 = Delayed Split Transaction 1471215976Sjmallett 1 = Retry Transaction (always Immediate Retry, no 1472215976Sjmallett AT_REQ to application). */ 1473215976Sjmallett uint32_t trtae : 1; /**< Target(I/O and Memory) Read Target Abort Enable 1474215976Sjmallett (if application interface is not ready at the 1475215976Sjmallett latency timeout). 1476215976Sjmallett Note: OCTEON as target will never target-abort, 1477215976Sjmallett therefore this bit should never be set. */ 1478215976Sjmallett uint32_t twsei : 1; /**< Target(I/O) Write Split Enable (at timeout / 1479215976Sjmallett immediately; default timeout) */ 1480215976Sjmallett uint32_t twsen : 1; /**< T(I/O) write split Enable (if the application 1481215976Sjmallett interface is not ready) */ 1482215976Sjmallett uint32_t twtae : 1; /**< Target(I/O and Memory) Write Target Abort Enable 1483215976Sjmallett (if the application interface is not ready at the 1484215976Sjmallett start of the cycle). 1485215976Sjmallett Note: OCTEON as target will never target-abort, 1486215976Sjmallett therefore this bit should never be set. */ 1487215976Sjmallett uint32_t tmae : 1; /**< Target(Read/Write) Master Abort Enable; check 1488215976Sjmallett at the start of each transaction. 1489215976Sjmallett Note: This bit can be used to force a Master 1490215976Sjmallett Abort when OCTEON is acting as the intended target 1491215976Sjmallett device. */ 1492215976Sjmallett uint32_t tslte : 3; /**< Target Subsequent(2nd-last) Latency Timeout Enable 1493215976Sjmallett Valid range: [1..7] and 0=8. */ 1494215976Sjmallett uint32_t tilt : 4; /**< Target Initial(1st data) Latency Timeout in PCI 1495215976Sjmallett ModeValid range: [8..15] and 0=16. */ 1496215976Sjmallett uint32_t pbe : 12; /**< Programmable Boundary Enable to disconnect/prefetch 1497215976Sjmallett for target burst read cycles to prefetchable 1498215976Sjmallett region in PCI. A value of 1 indicates end of 1499215976Sjmallett boundary (64 KB down to 16 Bytes). */ 1500215976Sjmallett uint32_t dppmr : 1; /**< Disconnect/Prefetch to prefetchable memory 1501215976Sjmallett regions Enable. Prefetchable memory regions 1502215976Sjmallett are always disconnected on a region boundary. 1503215976Sjmallett Non-prefetchable regions for PCI are always 1504215976Sjmallett disconnected on the first transfer. 1505215976Sjmallett Note: OCTEON as target will never target-disconnect, 1506215976Sjmallett therefore this bit should never be set. */ 1507215976Sjmallett uint32_t reserved_2_2 : 1; 1508215976Sjmallett uint32_t tswc : 1; /**< Target Split Write Control 1509215976Sjmallett 0 = Blocks all requests except PMW 1510215976Sjmallett 1 = Blocks all requests including PMW until 1511215976Sjmallett split completion occurs. */ 1512215976Sjmallett uint32_t mltd : 1; /**< Master Latency Timer Disable 1513215976Sjmallett Note: For OCTEON, it is recommended that this bit 1514215976Sjmallett be set(to disable the Master Latency timer). */ 1515215976Sjmallett#else 1516215976Sjmallett uint32_t mltd : 1; 1517215976Sjmallett uint32_t tswc : 1; 1518215976Sjmallett uint32_t reserved_2_2 : 1; 1519215976Sjmallett uint32_t dppmr : 1; 1520215976Sjmallett uint32_t pbe : 12; 1521215976Sjmallett uint32_t tilt : 4; 1522215976Sjmallett uint32_t tslte : 3; 1523215976Sjmallett uint32_t tmae : 1; 1524215976Sjmallett uint32_t twtae : 1; 1525215976Sjmallett uint32_t twsen : 1; 1526215976Sjmallett uint32_t twsei : 1; 1527215976Sjmallett uint32_t trtae : 1; 1528215976Sjmallett uint32_t trdrs : 1; 1529215976Sjmallett uint32_t rdsati : 1; 1530215976Sjmallett uint32_t trdard : 1; 1531215976Sjmallett uint32_t trdnpr : 1; 1532215976Sjmallett#endif 1533215976Sjmallett } s; 1534215976Sjmallett struct cvmx_pci_cfg16_s cn30xx; 1535215976Sjmallett struct cvmx_pci_cfg16_s cn31xx; 1536215976Sjmallett struct cvmx_pci_cfg16_s cn38xx; 1537215976Sjmallett struct cvmx_pci_cfg16_s cn38xxp2; 1538215976Sjmallett struct cvmx_pci_cfg16_s cn50xx; 1539215976Sjmallett struct cvmx_pci_cfg16_s cn58xx; 1540215976Sjmallett struct cvmx_pci_cfg16_s cn58xxp1; 1541215976Sjmallett}; 1542215976Sjmalletttypedef union cvmx_pci_cfg16 cvmx_pci_cfg16_t; 1543215976Sjmallett 1544215976Sjmallett/** 1545215976Sjmallett * cvmx_pci_cfg17 1546215976Sjmallett * 1547215976Sjmallett * PCI_CFG17 = Eighteenth 32-bits of PCI config space (Target Split Completion Message 1548215976Sjmallett * Enable Register) 1549215976Sjmallett */ 1550215976Sjmallettunion cvmx_pci_cfg17 1551215976Sjmallett{ 1552215976Sjmallett uint32_t u32; 1553215976Sjmallett struct cvmx_pci_cfg17_s 1554215976Sjmallett { 1555215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1556215976Sjmallett uint32_t tscme : 32; /**< Target Split Completion Message Enable 1557215976Sjmallett [31:30]: 00 1558215976Sjmallett [29]: Split Completion Error Indication 1559215976Sjmallett [28]: 0 1560215976Sjmallett [27:20]: Split Completion Message Index 1561215976Sjmallett [19:0]: 0x00000 1562215976Sjmallett For OCTEON, this register is intended for debug use 1563215976Sjmallett only. (as such, it is recommended NOT to be written 1564215976Sjmallett with anything other than ZEROES). */ 1565215976Sjmallett#else 1566215976Sjmallett uint32_t tscme : 32; 1567215976Sjmallett#endif 1568215976Sjmallett } s; 1569215976Sjmallett struct cvmx_pci_cfg17_s cn30xx; 1570215976Sjmallett struct cvmx_pci_cfg17_s cn31xx; 1571215976Sjmallett struct cvmx_pci_cfg17_s cn38xx; 1572215976Sjmallett struct cvmx_pci_cfg17_s cn38xxp2; 1573215976Sjmallett struct cvmx_pci_cfg17_s cn50xx; 1574215976Sjmallett struct cvmx_pci_cfg17_s cn58xx; 1575215976Sjmallett struct cvmx_pci_cfg17_s cn58xxp1; 1576215976Sjmallett}; 1577215976Sjmalletttypedef union cvmx_pci_cfg17 cvmx_pci_cfg17_t; 1578215976Sjmallett 1579215976Sjmallett/** 1580215976Sjmallett * cvmx_pci_cfg18 1581215976Sjmallett * 1582215976Sjmallett * PCI_CFG18 = Nineteenth 32-bits of PCI config space (Target Delayed/Split Request 1583215976Sjmallett * Pending Sequences) 1584215976Sjmallett */ 1585215976Sjmallettunion cvmx_pci_cfg18 1586215976Sjmallett{ 1587215976Sjmallett uint32_t u32; 1588215976Sjmallett struct cvmx_pci_cfg18_s 1589215976Sjmallett { 1590215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1591215976Sjmallett uint32_t tdsrps : 32; /**< Target Delayed/Split Request Pending Sequences 1592215976Sjmallett The application uses this address to remove a 1593215976Sjmallett pending split sequence from the target queue by 1594215976Sjmallett clearing the appropriate bit. Example: Clearing [14] 1595215976Sjmallett clears the pending sequence \#14. An application 1596215976Sjmallett or configuration write to this address can clear this 1597215976Sjmallett register. 1598215976Sjmallett For OCTEON, this register is intended for debug use 1599215976Sjmallett only and MUST NEVER be written with anything other 1600215976Sjmallett than ZEROES. */ 1601215976Sjmallett#else 1602215976Sjmallett uint32_t tdsrps : 32; 1603215976Sjmallett#endif 1604215976Sjmallett } s; 1605215976Sjmallett struct cvmx_pci_cfg18_s cn30xx; 1606215976Sjmallett struct cvmx_pci_cfg18_s cn31xx; 1607215976Sjmallett struct cvmx_pci_cfg18_s cn38xx; 1608215976Sjmallett struct cvmx_pci_cfg18_s cn38xxp2; 1609215976Sjmallett struct cvmx_pci_cfg18_s cn50xx; 1610215976Sjmallett struct cvmx_pci_cfg18_s cn58xx; 1611215976Sjmallett struct cvmx_pci_cfg18_s cn58xxp1; 1612215976Sjmallett}; 1613215976Sjmalletttypedef union cvmx_pci_cfg18 cvmx_pci_cfg18_t; 1614215976Sjmallett 1615215976Sjmallett/** 1616215976Sjmallett * cvmx_pci_cfg19 1617215976Sjmallett * 1618215976Sjmallett * PCI_CFG19 = Twentieth 32-bits of PCI config space (Master/Target Implementation Register) 1619215976Sjmallett * 1620215976Sjmallett */ 1621215976Sjmallettunion cvmx_pci_cfg19 1622215976Sjmallett{ 1623215976Sjmallett uint32_t u32; 1624215976Sjmallett struct cvmx_pci_cfg19_s 1625215976Sjmallett { 1626215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1627215976Sjmallett uint32_t mrbcm : 1; /**< Master Request (Memory Read) Byte Count/Byte 1628215976Sjmallett Enable select. 1629215976Sjmallett 0 = Byte Enables valid. In PCI mode, a burst 1630215976Sjmallett transaction cannot be performed using 1631215976Sjmallett Memory Read command=4'h6. 1632215976Sjmallett 1 = DWORD Byte Count valid (default). In PCI 1633215976Sjmallett Mode, the memory read byte enables are 1634215976Sjmallett automatically generated by the core. 1635215976Sjmallett NOTE: For OCTEON, this bit must always be one 1636215976Sjmallett for proper operation. */ 1637215976Sjmallett uint32_t mrbci : 1; /**< Master Request (I/O and CR cycles) byte count/byte 1638215976Sjmallett enable select. 1639215976Sjmallett 0 = Byte Enables valid (default) 1640215976Sjmallett 1 = DWORD byte count valid 1641215976Sjmallett NOTE: For OCTEON, this bit must always be zero 1642215976Sjmallett for proper operation (in support of 1643215976Sjmallett Type0/1 Cfg Space accesses which require byte 1644215976Sjmallett enable generation directly from a read mask). */ 1645215976Sjmallett uint32_t mdwe : 1; /**< Master (Retry) Deferred Write Enable (allow 1646215976Sjmallett read requests to pass). 1647215976Sjmallett NOTE: Applicable to PCI Mode I/O and memory 1648215976Sjmallett transactions only. 1649215976Sjmallett 0 = New read requests are NOT accepted until 1650215976Sjmallett the current write cycle completes. [Reads 1651215976Sjmallett cannot pass writes] 1652215976Sjmallett 1 = New read requests are accepted, even when 1653215976Sjmallett there is a write cycle pending [Reads can 1654215976Sjmallett pass writes]. 1655215976Sjmallett NOTE: For OCTEON, this bit must always be zero 1656215976Sjmallett for proper operation. */ 1657215976Sjmallett uint32_t mdre : 1; /**< Master (Retry) Deferred Read Enable (Allows 1658215976Sjmallett read/write requests to pass). 1659215976Sjmallett NOTE: Applicable to PCI mode I/O and memory 1660215976Sjmallett transactions only. 1661215976Sjmallett 0 = New read/write requests are NOT accepted 1662215976Sjmallett until the current read cycle completes. 1663215976Sjmallett [Read/write requests CANNOT pass reads] 1664215976Sjmallett 1 = New read/write requests are accepted, even 1665215976Sjmallett when there is a read cycle pending. 1666215976Sjmallett [Read/write requests CAN pass reads] 1667215976Sjmallett NOTE: For OCTEON, this bit must always be zero 1668215976Sjmallett for proper operation. */ 1669215976Sjmallett uint32_t mdrimc : 1; /**< Master I/O Deferred/Split Request Outstanding 1670215976Sjmallett Maximum Count 1671215976Sjmallett 0 = MDRRMC[26:24] 1672215976Sjmallett 1 = 1 */ 1673215976Sjmallett uint32_t mdrrmc : 3; /**< Master Deferred Read Request Outstanding Max 1674215976Sjmallett Count (PCI only). 1675215976Sjmallett CR4C[26:24] Max SAC cycles MAX DAC cycles 1676215976Sjmallett 000 8 4 1677215976Sjmallett 001 1 0 1678215976Sjmallett 010 2 1 1679215976Sjmallett 011 3 1 1680215976Sjmallett 100 4 2 1681215976Sjmallett 101 5 2 1682215976Sjmallett 110 6 3 1683215976Sjmallett 111 7 3 1684215976Sjmallett For example, if these bits are programmed to 1685215976Sjmallett 100, the core can support 2 DAC cycles, 4 SAC 1686215976Sjmallett cycles or a combination of 1 DAC and 2 SAC cycles. 1687215976Sjmallett NOTE: For the PCI-X maximum outstanding split 1688215976Sjmallett transactions, refer to CRE0[22:20] */ 1689215976Sjmallett uint32_t tmes : 8; /**< Target/Master Error Sequence \# */ 1690215976Sjmallett uint32_t teci : 1; /**< Target Error Command Indication 1691215976Sjmallett 0 = Delayed/Split 1692215976Sjmallett 1 = Others */ 1693215976Sjmallett uint32_t tmei : 1; /**< Target/Master Error Indication 1694215976Sjmallett 0 = Target 1695215976Sjmallett 1 = Master */ 1696215976Sjmallett uint32_t tmse : 1; /**< Target/Master System Error. This bit is set 1697215976Sjmallett whenever ATM_SERR_O is active. */ 1698215976Sjmallett uint32_t tmdpes : 1; /**< Target/Master Data PERR# error status. This 1699215976Sjmallett bit is set whenever ATM_DATA_PERR_O is active. */ 1700215976Sjmallett uint32_t tmapes : 1; /**< Target/Master Address PERR# error status. This 1701215976Sjmallett bit is set whenever ATM_ADDR_PERR_O is active. */ 1702215976Sjmallett uint32_t reserved_9_10 : 2; 1703215976Sjmallett uint32_t tibcd : 1; /**< Target Illegal I/O DWORD byte combinations detected. */ 1704215976Sjmallett uint32_t tibde : 1; /**< Target Illegal I/O DWORD byte detection enable */ 1705215976Sjmallett uint32_t reserved_6_6 : 1; 1706215976Sjmallett uint32_t tidomc : 1; /**< Target I/O Delayed/Split request outstanding 1707215976Sjmallett maximum count. 1708215976Sjmallett 0 = TDOMC[4:0] 1709215976Sjmallett 1 = 1 */ 1710215976Sjmallett uint32_t tdomc : 5; /**< Target Delayed/Split request outstanding maximum 1711215976Sjmallett count. [1..31] and 0=32. 1712215976Sjmallett NOTE: If the user programs these bits beyond the 1713215976Sjmallett Designed Maximum outstanding count, then the 1714215976Sjmallett designed maximum table depth will be used instead. 1715215976Sjmallett No additional Deferred/Split transactions will be 1716215976Sjmallett accepted if this outstanding maximum count 1717215976Sjmallett is reached. Furthermore, no additional 1718215976Sjmallett deferred/split transactions will be accepted if 1719215976Sjmallett the I/O delay/ I/O Split Request outstanding 1720215976Sjmallett maximum is reached. 1721215976Sjmallett NOTE: For OCTEON in PCI Mode, this field MUST BE 1722215976Sjmallett programmed to 1. (OCTEON can only handle 1 delayed 1723215976Sjmallett read at a time). 1724215976Sjmallett For OCTEON in PCIX Mode, this field can range from 1725215976Sjmallett 1-4. (The designed maximum table depth is 4 1726215976Sjmallett for PCIX mode splits). */ 1727215976Sjmallett#else 1728215976Sjmallett uint32_t tdomc : 5; 1729215976Sjmallett uint32_t tidomc : 1; 1730215976Sjmallett uint32_t reserved_6_6 : 1; 1731215976Sjmallett uint32_t tibde : 1; 1732215976Sjmallett uint32_t tibcd : 1; 1733215976Sjmallett uint32_t reserved_9_10 : 2; 1734215976Sjmallett uint32_t tmapes : 1; 1735215976Sjmallett uint32_t tmdpes : 1; 1736215976Sjmallett uint32_t tmse : 1; 1737215976Sjmallett uint32_t tmei : 1; 1738215976Sjmallett uint32_t teci : 1; 1739215976Sjmallett uint32_t tmes : 8; 1740215976Sjmallett uint32_t mdrrmc : 3; 1741215976Sjmallett uint32_t mdrimc : 1; 1742215976Sjmallett uint32_t mdre : 1; 1743215976Sjmallett uint32_t mdwe : 1; 1744215976Sjmallett uint32_t mrbci : 1; 1745215976Sjmallett uint32_t mrbcm : 1; 1746215976Sjmallett#endif 1747215976Sjmallett } s; 1748215976Sjmallett struct cvmx_pci_cfg19_s cn30xx; 1749215976Sjmallett struct cvmx_pci_cfg19_s cn31xx; 1750215976Sjmallett struct cvmx_pci_cfg19_s cn38xx; 1751215976Sjmallett struct cvmx_pci_cfg19_s cn38xxp2; 1752215976Sjmallett struct cvmx_pci_cfg19_s cn50xx; 1753215976Sjmallett struct cvmx_pci_cfg19_s cn58xx; 1754215976Sjmallett struct cvmx_pci_cfg19_s cn58xxp1; 1755215976Sjmallett}; 1756215976Sjmalletttypedef union cvmx_pci_cfg19 cvmx_pci_cfg19_t; 1757215976Sjmallett 1758215976Sjmallett/** 1759215976Sjmallett * cvmx_pci_cfg20 1760215976Sjmallett * 1761215976Sjmallett * PCI_CFG20 = Twenty-first 32-bits of PCI config space (Master Deferred/Split Sequence Pending) 1762215976Sjmallett * 1763215976Sjmallett */ 1764215976Sjmallettunion cvmx_pci_cfg20 1765215976Sjmallett{ 1766215976Sjmallett uint32_t u32; 1767215976Sjmallett struct cvmx_pci_cfg20_s 1768215976Sjmallett { 1769215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1770215976Sjmallett uint32_t mdsp : 32; /**< Master Deferred/Split sequence Pending 1771215976Sjmallett For OCTEON, this register is intended for debug use 1772215976Sjmallett only and MUST NEVER be written with anything other 1773215976Sjmallett than ZEROES. */ 1774215976Sjmallett#else 1775215976Sjmallett uint32_t mdsp : 32; 1776215976Sjmallett#endif 1777215976Sjmallett } s; 1778215976Sjmallett struct cvmx_pci_cfg20_s cn30xx; 1779215976Sjmallett struct cvmx_pci_cfg20_s cn31xx; 1780215976Sjmallett struct cvmx_pci_cfg20_s cn38xx; 1781215976Sjmallett struct cvmx_pci_cfg20_s cn38xxp2; 1782215976Sjmallett struct cvmx_pci_cfg20_s cn50xx; 1783215976Sjmallett struct cvmx_pci_cfg20_s cn58xx; 1784215976Sjmallett struct cvmx_pci_cfg20_s cn58xxp1; 1785215976Sjmallett}; 1786215976Sjmalletttypedef union cvmx_pci_cfg20 cvmx_pci_cfg20_t; 1787215976Sjmallett 1788215976Sjmallett/** 1789215976Sjmallett * cvmx_pci_cfg21 1790215976Sjmallett * 1791215976Sjmallett * PCI_CFG21 = Twenty-second 32-bits of PCI config space (Master Split Completion Message Register) 1792215976Sjmallett * 1793215976Sjmallett */ 1794215976Sjmallettunion cvmx_pci_cfg21 1795215976Sjmallett{ 1796215976Sjmallett uint32_t u32; 1797215976Sjmallett struct cvmx_pci_cfg21_s 1798215976Sjmallett { 1799215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1800215976Sjmallett uint32_t scmre : 32; /**< Master Split Completion message received with 1801215976Sjmallett error message. 1802215976Sjmallett For OCTEON, this register is intended for debug use 1803215976Sjmallett only and MUST NEVER be written with anything other 1804215976Sjmallett than ZEROES. */ 1805215976Sjmallett#else 1806215976Sjmallett uint32_t scmre : 32; 1807215976Sjmallett#endif 1808215976Sjmallett } s; 1809215976Sjmallett struct cvmx_pci_cfg21_s cn30xx; 1810215976Sjmallett struct cvmx_pci_cfg21_s cn31xx; 1811215976Sjmallett struct cvmx_pci_cfg21_s cn38xx; 1812215976Sjmallett struct cvmx_pci_cfg21_s cn38xxp2; 1813215976Sjmallett struct cvmx_pci_cfg21_s cn50xx; 1814215976Sjmallett struct cvmx_pci_cfg21_s cn58xx; 1815215976Sjmallett struct cvmx_pci_cfg21_s cn58xxp1; 1816215976Sjmallett}; 1817215976Sjmalletttypedef union cvmx_pci_cfg21 cvmx_pci_cfg21_t; 1818215976Sjmallett 1819215976Sjmallett/** 1820215976Sjmallett * cvmx_pci_cfg22 1821215976Sjmallett * 1822215976Sjmallett * PCI_CFG22 = Twenty-third 32-bits of PCI config space (Master Arbiter Control Register) 1823215976Sjmallett * 1824215976Sjmallett */ 1825215976Sjmallettunion cvmx_pci_cfg22 1826215976Sjmallett{ 1827215976Sjmallett uint32_t u32; 1828215976Sjmallett struct cvmx_pci_cfg22_s 1829215976Sjmallett { 1830215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1831215976Sjmallett uint32_t mac : 7; /**< Master Arbiter Control 1832215976Sjmallett [31:26]: Used only in Fixed Priority mode 1833215976Sjmallett (when [25]=1) 1834215976Sjmallett [31:30]: MSI Request 1835215976Sjmallett 00 = Highest Priority 1836215976Sjmallett 01 = Medium Priority 1837215976Sjmallett 10 = Lowest Priority 1838215976Sjmallett 11 = RESERVED 1839215976Sjmallett [29:28]: Target Split Completion 1840215976Sjmallett 00 = Highest Priority 1841215976Sjmallett 01 = Medium Priority 1842215976Sjmallett 10 = Lowest Priority 1843215976Sjmallett 11 = RESERVED 1844215976Sjmallett [27:26]: New Request; Deferred Read,Deferred Write 1845215976Sjmallett 00 = Highest Priority 1846215976Sjmallett 01 = Medium Priority 1847215976Sjmallett 10 = Lowest Priority 1848215976Sjmallett 11 = RESERVED 1849215976Sjmallett [25]: Fixed/Round Robin Priority Selector 1850215976Sjmallett 0 = Round Robin 1851215976Sjmallett 1 = Fixed 1852215976Sjmallett NOTE: When [25]=1(fixed priority), the three levels 1853215976Sjmallett [31:26] MUST BE programmed to have mutually exclusive 1854215976Sjmallett priority levels for proper operation. (Failure to do 1855215976Sjmallett so may result in PCI hangs). */ 1856215976Sjmallett uint32_t reserved_19_24 : 6; 1857215976Sjmallett uint32_t flush : 1; /**< AM_DO_FLUSH_I control 1858215976Sjmallett NOTE: This bit MUST BE ONE for proper OCTEON operation */ 1859215976Sjmallett uint32_t mra : 1; /**< Master Retry Aborted */ 1860215976Sjmallett uint32_t mtta : 1; /**< Master TRDY timeout aborted */ 1861215976Sjmallett uint32_t mrv : 8; /**< Master Retry Value [1..255] and 0=infinite */ 1862215976Sjmallett uint32_t mttv : 8; /**< Master TRDY timeout value [1..255] and 0=disabled 1863215976Sjmallett NOTE: For OCTEON, this bit must always be zero 1864215976Sjmallett for proper operation. (OCTEON does not support 1865215976Sjmallett master TRDY timeout - target is expected to be 1866215976Sjmallett well behaved). */ 1867215976Sjmallett#else 1868215976Sjmallett uint32_t mttv : 8; 1869215976Sjmallett uint32_t mrv : 8; 1870215976Sjmallett uint32_t mtta : 1; 1871215976Sjmallett uint32_t mra : 1; 1872215976Sjmallett uint32_t flush : 1; 1873215976Sjmallett uint32_t reserved_19_24 : 6; 1874215976Sjmallett uint32_t mac : 7; 1875215976Sjmallett#endif 1876215976Sjmallett } s; 1877215976Sjmallett struct cvmx_pci_cfg22_s cn30xx; 1878215976Sjmallett struct cvmx_pci_cfg22_s cn31xx; 1879215976Sjmallett struct cvmx_pci_cfg22_s cn38xx; 1880215976Sjmallett struct cvmx_pci_cfg22_s cn38xxp2; 1881215976Sjmallett struct cvmx_pci_cfg22_s cn50xx; 1882215976Sjmallett struct cvmx_pci_cfg22_s cn58xx; 1883215976Sjmallett struct cvmx_pci_cfg22_s cn58xxp1; 1884215976Sjmallett}; 1885215976Sjmalletttypedef union cvmx_pci_cfg22 cvmx_pci_cfg22_t; 1886215976Sjmallett 1887215976Sjmallett/** 1888215976Sjmallett * cvmx_pci_cfg56 1889215976Sjmallett * 1890215976Sjmallett * PCI_CFG56 = Fifty-seventh 32-bits of PCI config space (PCIX Capabilities Register) 1891215976Sjmallett * 1892215976Sjmallett */ 1893215976Sjmallettunion cvmx_pci_cfg56 1894215976Sjmallett{ 1895215976Sjmallett uint32_t u32; 1896215976Sjmallett struct cvmx_pci_cfg56_s 1897215976Sjmallett { 1898215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1899215976Sjmallett uint32_t reserved_23_31 : 9; 1900215976Sjmallett uint32_t most : 3; /**< Maximum outstanding Split transactions 1901215976Sjmallett Encoded Value \#Max outstanding splits 1902215976Sjmallett 000 1 1903215976Sjmallett 001 2 1904215976Sjmallett 010 3 1905215976Sjmallett 011 4 1906215976Sjmallett 100 8 1907215976Sjmallett 101 8(clamped) 1908215976Sjmallett 110 8(clamped) 1909215976Sjmallett 111 8(clamped) 1910215976Sjmallett NOTE: OCTEON only supports upto a MAXIMUM of 8 1911215976Sjmallett outstanding master split transactions. */ 1912215976Sjmallett uint32_t mmbc : 2; /**< Maximum Memory Byte Count 1913215976Sjmallett [0=512B,1=1024B,2=2048B,3=4096B] 1914215976Sjmallett NOTE: OCTEON does not support this field and has 1915215976Sjmallett no effect on limiting the maximum memory byte count. */ 1916215976Sjmallett uint32_t roe : 1; /**< Relaxed Ordering Enable */ 1917215976Sjmallett uint32_t dpere : 1; /**< Data Parity Error Recovery Enable */ 1918215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer */ 1919215976Sjmallett uint32_t pxcid : 8; /**< PCI-X Capability ID */ 1920215976Sjmallett#else 1921215976Sjmallett uint32_t pxcid : 8; 1922215976Sjmallett uint32_t ncp : 8; 1923215976Sjmallett uint32_t dpere : 1; 1924215976Sjmallett uint32_t roe : 1; 1925215976Sjmallett uint32_t mmbc : 2; 1926215976Sjmallett uint32_t most : 3; 1927215976Sjmallett uint32_t reserved_23_31 : 9; 1928215976Sjmallett#endif 1929215976Sjmallett } s; 1930215976Sjmallett struct cvmx_pci_cfg56_s cn30xx; 1931215976Sjmallett struct cvmx_pci_cfg56_s cn31xx; 1932215976Sjmallett struct cvmx_pci_cfg56_s cn38xx; 1933215976Sjmallett struct cvmx_pci_cfg56_s cn38xxp2; 1934215976Sjmallett struct cvmx_pci_cfg56_s cn50xx; 1935215976Sjmallett struct cvmx_pci_cfg56_s cn58xx; 1936215976Sjmallett struct cvmx_pci_cfg56_s cn58xxp1; 1937215976Sjmallett}; 1938215976Sjmalletttypedef union cvmx_pci_cfg56 cvmx_pci_cfg56_t; 1939215976Sjmallett 1940215976Sjmallett/** 1941215976Sjmallett * cvmx_pci_cfg57 1942215976Sjmallett * 1943215976Sjmallett * PCI_CFG57 = Fifty-eigth 32-bits of PCI config space (PCIX Status Register) 1944215976Sjmallett * 1945215976Sjmallett */ 1946215976Sjmallettunion cvmx_pci_cfg57 1947215976Sjmallett{ 1948215976Sjmallett uint32_t u32; 1949215976Sjmallett struct cvmx_pci_cfg57_s 1950215976Sjmallett { 1951215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1952215976Sjmallett uint32_t reserved_30_31 : 2; 1953215976Sjmallett uint32_t scemr : 1; /**< Split Completion Error Message Received */ 1954215976Sjmallett uint32_t mcrsd : 3; /**< Maximum Cumulative Read Size designed */ 1955215976Sjmallett uint32_t mostd : 3; /**< Maximum Outstanding Split transaction designed */ 1956215976Sjmallett uint32_t mmrbcd : 2; /**< Maximum Memory Read byte count designed */ 1957215976Sjmallett uint32_t dc : 1; /**< Device Complexity 1958215976Sjmallett 0 = Simple Device 1959215976Sjmallett 1 = Bridge Device */ 1960215976Sjmallett uint32_t usc : 1; /**< Unexpected Split Completion */ 1961215976Sjmallett uint32_t scd : 1; /**< Split Completion Discarded */ 1962215976Sjmallett uint32_t m133 : 1; /**< 133MHz Capable */ 1963215976Sjmallett uint32_t w64 : 1; /**< Indicates a 32b(=0) or 64b(=1) device */ 1964215976Sjmallett uint32_t bn : 8; /**< Bus Number. Updated on all configuration write 1965215976Sjmallett (0x11=PCI) cycles. Its value is dependent upon the PCI/X 1966215976Sjmallett (0xFF=PCIX) mode. */ 1967215976Sjmallett uint32_t dn : 5; /**< Device Number. Updated on all configuration 1968215976Sjmallett write cycles. */ 1969215976Sjmallett uint32_t fn : 3; /**< Function Number */ 1970215976Sjmallett#else 1971215976Sjmallett uint32_t fn : 3; 1972215976Sjmallett uint32_t dn : 5; 1973215976Sjmallett uint32_t bn : 8; 1974215976Sjmallett uint32_t w64 : 1; 1975215976Sjmallett uint32_t m133 : 1; 1976215976Sjmallett uint32_t scd : 1; 1977215976Sjmallett uint32_t usc : 1; 1978215976Sjmallett uint32_t dc : 1; 1979215976Sjmallett uint32_t mmrbcd : 2; 1980215976Sjmallett uint32_t mostd : 3; 1981215976Sjmallett uint32_t mcrsd : 3; 1982215976Sjmallett uint32_t scemr : 1; 1983215976Sjmallett uint32_t reserved_30_31 : 2; 1984215976Sjmallett#endif 1985215976Sjmallett } s; 1986215976Sjmallett struct cvmx_pci_cfg57_s cn30xx; 1987215976Sjmallett struct cvmx_pci_cfg57_s cn31xx; 1988215976Sjmallett struct cvmx_pci_cfg57_s cn38xx; 1989215976Sjmallett struct cvmx_pci_cfg57_s cn38xxp2; 1990215976Sjmallett struct cvmx_pci_cfg57_s cn50xx; 1991215976Sjmallett struct cvmx_pci_cfg57_s cn58xx; 1992215976Sjmallett struct cvmx_pci_cfg57_s cn58xxp1; 1993215976Sjmallett}; 1994215976Sjmalletttypedef union cvmx_pci_cfg57 cvmx_pci_cfg57_t; 1995215976Sjmallett 1996215976Sjmallett/** 1997215976Sjmallett * cvmx_pci_cfg58 1998215976Sjmallett * 1999215976Sjmallett * PCI_CFG58 = Fifty-ninth 32-bits of PCI config space (Power Management Capabilities Register) 2000215976Sjmallett * 2001215976Sjmallett */ 2002215976Sjmallettunion cvmx_pci_cfg58 2003215976Sjmallett{ 2004215976Sjmallett uint32_t u32; 2005215976Sjmallett struct cvmx_pci_cfg58_s 2006215976Sjmallett { 2007215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2008215976Sjmallett uint32_t pmes : 5; /**< PME Support (D0 to D3cold) */ 2009215976Sjmallett uint32_t d2s : 1; /**< D2_Support */ 2010215976Sjmallett uint32_t d1s : 1; /**< D1_Support */ 2011215976Sjmallett uint32_t auxc : 3; /**< AUX_Current (0..375mA) */ 2012215976Sjmallett uint32_t dsi : 1; /**< Device Specific Initialization */ 2013215976Sjmallett uint32_t reserved_20_20 : 1; 2014215976Sjmallett uint32_t pmec : 1; /**< PME Clock */ 2015215976Sjmallett uint32_t pcimiv : 3; /**< Indicates the version of the PCI 2016215976Sjmallett Management 2017215976Sjmallett Interface Specification with which the core 2018215976Sjmallett complies. 2019215976Sjmallett 010b = Complies with PCI Management Interface 2020215976Sjmallett Specification Revision 1.1 */ 2021215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer */ 2022215976Sjmallett uint32_t pmcid : 8; /**< Power Management Capability ID */ 2023215976Sjmallett#else 2024215976Sjmallett uint32_t pmcid : 8; 2025215976Sjmallett uint32_t ncp : 8; 2026215976Sjmallett uint32_t pcimiv : 3; 2027215976Sjmallett uint32_t pmec : 1; 2028215976Sjmallett uint32_t reserved_20_20 : 1; 2029215976Sjmallett uint32_t dsi : 1; 2030215976Sjmallett uint32_t auxc : 3; 2031215976Sjmallett uint32_t d1s : 1; 2032215976Sjmallett uint32_t d2s : 1; 2033215976Sjmallett uint32_t pmes : 5; 2034215976Sjmallett#endif 2035215976Sjmallett } s; 2036215976Sjmallett struct cvmx_pci_cfg58_s cn30xx; 2037215976Sjmallett struct cvmx_pci_cfg58_s cn31xx; 2038215976Sjmallett struct cvmx_pci_cfg58_s cn38xx; 2039215976Sjmallett struct cvmx_pci_cfg58_s cn38xxp2; 2040215976Sjmallett struct cvmx_pci_cfg58_s cn50xx; 2041215976Sjmallett struct cvmx_pci_cfg58_s cn58xx; 2042215976Sjmallett struct cvmx_pci_cfg58_s cn58xxp1; 2043215976Sjmallett}; 2044215976Sjmalletttypedef union cvmx_pci_cfg58 cvmx_pci_cfg58_t; 2045215976Sjmallett 2046215976Sjmallett/** 2047215976Sjmallett * cvmx_pci_cfg59 2048215976Sjmallett * 2049215976Sjmallett * PCI_CFG59 = Sixtieth 32-bits of PCI config space (Power Management Data/PMCSR Register(s)) 2050215976Sjmallett * 2051215976Sjmallett */ 2052215976Sjmallettunion cvmx_pci_cfg59 2053215976Sjmallett{ 2054215976Sjmallett uint32_t u32; 2055215976Sjmallett struct cvmx_pci_cfg59_s 2056215976Sjmallett { 2057215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2058215976Sjmallett uint32_t pmdia : 8; /**< Power Management data input from application 2059215976Sjmallett (PME_DATA) */ 2060215976Sjmallett uint32_t bpccen : 1; /**< BPCC_En (bus power/clock control) enable */ 2061215976Sjmallett uint32_t bd3h : 1; /**< B2_B3\#, B2/B3 Support for D3hot */ 2062215976Sjmallett uint32_t reserved_16_21 : 6; 2063215976Sjmallett uint32_t pmess : 1; /**< PME_Status sticky bit */ 2064215976Sjmallett uint32_t pmedsia : 2; /**< PME_Data_Scale input from application 2065215976Sjmallett Device (PME_DATA_SCALE[1:0]) 2066215976Sjmallett Specific */ 2067215976Sjmallett uint32_t pmds : 4; /**< Power Management Data_select */ 2068215976Sjmallett uint32_t pmeens : 1; /**< PME_En sticky bit */ 2069215976Sjmallett uint32_t reserved_2_7 : 6; 2070215976Sjmallett uint32_t ps : 2; /**< Power State (D0 to D3) 2071215976Sjmallett The N2 DOES NOT support D1/D2 Power Management 2072215976Sjmallett states, therefore writing to this register has 2073215976Sjmallett no effect (please refer to the PCI Power 2074215976Sjmallett Management 2075215976Sjmallett Specification v1.1 for further details about 2076215976Sjmallett it?s R/W nature. This is not a conventional 2077215976Sjmallett R/W style register. */ 2078215976Sjmallett#else 2079215976Sjmallett uint32_t ps : 2; 2080215976Sjmallett uint32_t reserved_2_7 : 6; 2081215976Sjmallett uint32_t pmeens : 1; 2082215976Sjmallett uint32_t pmds : 4; 2083215976Sjmallett uint32_t pmedsia : 2; 2084215976Sjmallett uint32_t pmess : 1; 2085215976Sjmallett uint32_t reserved_16_21 : 6; 2086215976Sjmallett uint32_t bd3h : 1; 2087215976Sjmallett uint32_t bpccen : 1; 2088215976Sjmallett uint32_t pmdia : 8; 2089215976Sjmallett#endif 2090215976Sjmallett } s; 2091215976Sjmallett struct cvmx_pci_cfg59_s cn30xx; 2092215976Sjmallett struct cvmx_pci_cfg59_s cn31xx; 2093215976Sjmallett struct cvmx_pci_cfg59_s cn38xx; 2094215976Sjmallett struct cvmx_pci_cfg59_s cn38xxp2; 2095215976Sjmallett struct cvmx_pci_cfg59_s cn50xx; 2096215976Sjmallett struct cvmx_pci_cfg59_s cn58xx; 2097215976Sjmallett struct cvmx_pci_cfg59_s cn58xxp1; 2098215976Sjmallett}; 2099215976Sjmalletttypedef union cvmx_pci_cfg59 cvmx_pci_cfg59_t; 2100215976Sjmallett 2101215976Sjmallett/** 2102215976Sjmallett * cvmx_pci_cfg60 2103215976Sjmallett * 2104215976Sjmallett * PCI_CFG60 = Sixty-first 32-bits of PCI config space (MSI Capabilities Register) 2105215976Sjmallett * 2106215976Sjmallett */ 2107215976Sjmallettunion cvmx_pci_cfg60 2108215976Sjmallett{ 2109215976Sjmallett uint32_t u32; 2110215976Sjmallett struct cvmx_pci_cfg60_s 2111215976Sjmallett { 2112215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2113215976Sjmallett uint32_t reserved_24_31 : 8; 2114215976Sjmallett uint32_t m64 : 1; /**< 32/64 b message */ 2115215976Sjmallett uint32_t mme : 3; /**< Multiple Message Enable(1,2,4,8,16,32) */ 2116215976Sjmallett uint32_t mmc : 3; /**< Multiple Message Capable(0=1,1=2,2=4,3=8,4=16,5=32) */ 2117215976Sjmallett uint32_t msien : 1; /**< MSI Enable */ 2118215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer */ 2119215976Sjmallett uint32_t msicid : 8; /**< MSI Capability ID */ 2120215976Sjmallett#else 2121215976Sjmallett uint32_t msicid : 8; 2122215976Sjmallett uint32_t ncp : 8; 2123215976Sjmallett uint32_t msien : 1; 2124215976Sjmallett uint32_t mmc : 3; 2125215976Sjmallett uint32_t mme : 3; 2126215976Sjmallett uint32_t m64 : 1; 2127215976Sjmallett uint32_t reserved_24_31 : 8; 2128215976Sjmallett#endif 2129215976Sjmallett } s; 2130215976Sjmallett struct cvmx_pci_cfg60_s cn30xx; 2131215976Sjmallett struct cvmx_pci_cfg60_s cn31xx; 2132215976Sjmallett struct cvmx_pci_cfg60_s cn38xx; 2133215976Sjmallett struct cvmx_pci_cfg60_s cn38xxp2; 2134215976Sjmallett struct cvmx_pci_cfg60_s cn50xx; 2135215976Sjmallett struct cvmx_pci_cfg60_s cn58xx; 2136215976Sjmallett struct cvmx_pci_cfg60_s cn58xxp1; 2137215976Sjmallett}; 2138215976Sjmalletttypedef union cvmx_pci_cfg60 cvmx_pci_cfg60_t; 2139215976Sjmallett 2140215976Sjmallett/** 2141215976Sjmallett * cvmx_pci_cfg61 2142215976Sjmallett * 2143215976Sjmallett * PCI_CFG61 = Sixty-second 32-bits of PCI config space (MSI Lower Address Register) 2144215976Sjmallett * 2145215976Sjmallett */ 2146215976Sjmallettunion cvmx_pci_cfg61 2147215976Sjmallett{ 2148215976Sjmallett uint32_t u32; 2149215976Sjmallett struct cvmx_pci_cfg61_s 2150215976Sjmallett { 2151215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2152215976Sjmallett uint32_t msi31t2 : 30; /**< App Specific MSI Address [31:2] */ 2153215976Sjmallett uint32_t reserved_0_1 : 2; 2154215976Sjmallett#else 2155215976Sjmallett uint32_t reserved_0_1 : 2; 2156215976Sjmallett uint32_t msi31t2 : 30; 2157215976Sjmallett#endif 2158215976Sjmallett } s; 2159215976Sjmallett struct cvmx_pci_cfg61_s cn30xx; 2160215976Sjmallett struct cvmx_pci_cfg61_s cn31xx; 2161215976Sjmallett struct cvmx_pci_cfg61_s cn38xx; 2162215976Sjmallett struct cvmx_pci_cfg61_s cn38xxp2; 2163215976Sjmallett struct cvmx_pci_cfg61_s cn50xx; 2164215976Sjmallett struct cvmx_pci_cfg61_s cn58xx; 2165215976Sjmallett struct cvmx_pci_cfg61_s cn58xxp1; 2166215976Sjmallett}; 2167215976Sjmalletttypedef union cvmx_pci_cfg61 cvmx_pci_cfg61_t; 2168215976Sjmallett 2169215976Sjmallett/** 2170215976Sjmallett * cvmx_pci_cfg62 2171215976Sjmallett * 2172215976Sjmallett * PCI_CFG62 = Sixty-third 32-bits of PCI config space (MSI Upper Address Register) 2173215976Sjmallett * 2174215976Sjmallett */ 2175215976Sjmallettunion cvmx_pci_cfg62 2176215976Sjmallett{ 2177215976Sjmallett uint32_t u32; 2178215976Sjmallett struct cvmx_pci_cfg62_s 2179215976Sjmallett { 2180215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2181215976Sjmallett uint32_t msi : 32; /**< MSI Address [63:32] */ 2182215976Sjmallett#else 2183215976Sjmallett uint32_t msi : 32; 2184215976Sjmallett#endif 2185215976Sjmallett } s; 2186215976Sjmallett struct cvmx_pci_cfg62_s cn30xx; 2187215976Sjmallett struct cvmx_pci_cfg62_s cn31xx; 2188215976Sjmallett struct cvmx_pci_cfg62_s cn38xx; 2189215976Sjmallett struct cvmx_pci_cfg62_s cn38xxp2; 2190215976Sjmallett struct cvmx_pci_cfg62_s cn50xx; 2191215976Sjmallett struct cvmx_pci_cfg62_s cn58xx; 2192215976Sjmallett struct cvmx_pci_cfg62_s cn58xxp1; 2193215976Sjmallett}; 2194215976Sjmalletttypedef union cvmx_pci_cfg62 cvmx_pci_cfg62_t; 2195215976Sjmallett 2196215976Sjmallett/** 2197215976Sjmallett * cvmx_pci_cfg63 2198215976Sjmallett * 2199215976Sjmallett * PCI_CFG63 = Sixty-fourth 32-bits of PCI config space (MSI Message Data Register) 2200215976Sjmallett * 2201215976Sjmallett */ 2202215976Sjmallettunion cvmx_pci_cfg63 2203215976Sjmallett{ 2204215976Sjmallett uint32_t u32; 2205215976Sjmallett struct cvmx_pci_cfg63_s 2206215976Sjmallett { 2207215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2208215976Sjmallett uint32_t reserved_16_31 : 16; 2209215976Sjmallett uint32_t msimd : 16; /**< MSI Message Data */ 2210215976Sjmallett#else 2211215976Sjmallett uint32_t msimd : 16; 2212215976Sjmallett uint32_t reserved_16_31 : 16; 2213215976Sjmallett#endif 2214215976Sjmallett } s; 2215215976Sjmallett struct cvmx_pci_cfg63_s cn30xx; 2216215976Sjmallett struct cvmx_pci_cfg63_s cn31xx; 2217215976Sjmallett struct cvmx_pci_cfg63_s cn38xx; 2218215976Sjmallett struct cvmx_pci_cfg63_s cn38xxp2; 2219215976Sjmallett struct cvmx_pci_cfg63_s cn50xx; 2220215976Sjmallett struct cvmx_pci_cfg63_s cn58xx; 2221215976Sjmallett struct cvmx_pci_cfg63_s cn58xxp1; 2222215976Sjmallett}; 2223215976Sjmalletttypedef union cvmx_pci_cfg63 cvmx_pci_cfg63_t; 2224215976Sjmallett 2225215976Sjmallett/** 2226215976Sjmallett * cvmx_pci_cnt_reg 2227215976Sjmallett * 2228215976Sjmallett * PCI_CNT_REG = PCI Clock Count Register 2229215976Sjmallett * 2230215976Sjmallett * This register is provided to software as a means to determine PCI Bus Type/Speed. 2231215976Sjmallett */ 2232215976Sjmallettunion cvmx_pci_cnt_reg 2233215976Sjmallett{ 2234215976Sjmallett uint64_t u64; 2235215976Sjmallett struct cvmx_pci_cnt_reg_s 2236215976Sjmallett { 2237215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2238215976Sjmallett uint64_t reserved_38_63 : 26; 2239215976Sjmallett uint64_t hm_pcix : 1; /**< PCI Host Mode Sampled Bus Type (0:PCI/1:PCIX) 2240215976Sjmallett This field represents what OCTEON(in Host mode) 2241215976Sjmallett sampled as the 'intended' PCI Bus Type based on 2242215976Sjmallett the PCI_PCIXCAP pin. (see HM_SPEED Bus Type/Speed 2243215976Sjmallett encoding table). */ 2244215976Sjmallett uint64_t hm_speed : 2; /**< PCI Host Mode Sampled Bus Speed 2245215976Sjmallett This field represents what OCTEON(in Host mode) 2246215976Sjmallett sampled as the 'intended' PCI Bus Speed based on 2247215976Sjmallett the PCI100, PCI_M66EN and PCI_PCIXCAP pins. 2248215976Sjmallett NOTE: This DOES NOT reflect what the actual PCI 2249215976Sjmallett Bus Type/Speed values are. They only indicate what 2250215976Sjmallett OCTEON sampled as the 'intended' values. 2251215976Sjmallett PCI Host Mode Sampled Bus Type/Speed Table: 2252215976Sjmallett M66EN | PCIXCAP | PCI100 | HM_PCIX | HM_SPEED[1:0] 2253215976Sjmallett ---------+---------+---------+----------+------------- 2254215976Sjmallett 0 | 0 | 0 | 0=PCI | 00=33 MHz 2255215976Sjmallett 0 | 0 | 1 | 0=PCI | 00=33 MHz 2256215976Sjmallett 0 | Z | 0 | 0=PCI | 01=66 MHz 2257215976Sjmallett 0 | Z | 1 | 0=PCI | 01=66 MHz 2258215976Sjmallett 1 | 0 | 0 | 0=PCI | 01=66 MHz 2259215976Sjmallett 1 | 0 | 1 | 0=PCI | 01=66 MHz 2260215976Sjmallett 1 | Z | 0 | 0=PCI | 01=66 MHz 2261215976Sjmallett 1 | Z | 1 | 0=PCI | 01=66 MHz 2262215976Sjmallett 0 | 1 | 1 | 1=PCIX | 10=100 MHz 2263215976Sjmallett 1 | 1 | 1 | 1=PCIX | 10=100 MHz 2264215976Sjmallett 0 | 1 | 0 | 1=PCIX | 11=133 MHz 2265215976Sjmallett 1 | 1 | 0 | 1=PCIX | 11=133 MHz 2266215976Sjmallett NOTE: PCIXCAP has tri-level value (0,1,Z). See PCI specification 2267215976Sjmallett for more details on board level hookup to achieve these 2268215976Sjmallett values. 2269215976Sjmallett NOTE: Software can use the NPI_PCI_INT_ARB_CFG[PCI_OVR] 2270215976Sjmallett to override the 'sampled' PCI Bus Type/Speed. 2271215976Sjmallett NOTE: Software can also use the PCI_CNT_REG[PCICNT] to determine 2272215976Sjmallett the exact PCI(X) Bus speed. 2273215976Sjmallett Example: PCI_REF_CLKIN=133MHz 2274215976Sjmallett PCI_HOST_MODE=1 2275215976Sjmallett PCI_M66EN=0 2276215976Sjmallett PCI_PCIXCAP=1 2277215976Sjmallett PCI_PCI100=1 2278215976Sjmallett For this example, OCTEON will generate 2279215976Sjmallett PCI_CLK_OUT=100MHz and drive the proper PCI 2280215976Sjmallett Initialization sequence (DEVSEL#=Deasserted, 2281215976Sjmallett STOP#=Asserted, TRDY#=Asserted) during PCI_RST_N 2282215976Sjmallett deassertion. 2283215976Sjmallett NOTE: The HM_SPEED field is only valid after 2284215976Sjmallett PLL_REF_CLK is active and PLL_DCOK is asserted. 2285215976Sjmallett (see HRM description for power-on/reset sequence). 2286215976Sjmallett NOTE: PCI_REF_CLKIN input must be 133MHz (and is used 2287215976Sjmallett to generate the PCI_CLK_OUT pin in Host Mode). */ 2288215976Sjmallett uint64_t ap_pcix : 1; /**< PCI(X) Bus Type (0:PCI/1:PCIX) 2289215976Sjmallett At PCI_RST_N de-assertion, the PCI Initialization 2290215976Sjmallett pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is 2291215976Sjmallett captured to provide information to software regarding 2292215976Sjmallett the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range. */ 2293215976Sjmallett uint64_t ap_speed : 2; /**< PCI(X) Bus Speed (0:33/1:66/2:100/3:133) 2294215976Sjmallett At PCI_RST_N de-assertion, the PCI Initialization 2295215976Sjmallett pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is 2296215976Sjmallett captured to provide information to software regarding 2297215976Sjmallett the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range. 2298215976Sjmallett PCI-X Initialization Pattern(see PCIX Spec): 2299215976Sjmallett PCI_DEVSEL_N PCI_STOP_N PCI_TRDY_N Mode MaxClk(ns) MinClk(ns) MinClk(MHz) MaxClk(MHz) 2300215976Sjmallett -------------+----------+----------+-------+---------+----------+----------+------------------ 2301215976Sjmallett Deasserted Deasserted Deasserted PCI 33 -- 30 0 33 2302215976Sjmallett PCI 66 30 15 33 66 2303215976Sjmallett Deasserted Deasserted Asserted PCI-X 20 15 50 66 2304215976Sjmallett Deasserted Asserted Deasserted PCI-X 15 10 66 100 2305215976Sjmallett Deasserted Asserted Asserted PCI-X 10 7.5 100 133 2306215976Sjmallett Asserted Deasserted Deasserted PCI-X Reserved Reserved Reserved Reserved 2307215976Sjmallett Asserted Deasserted Asserted PCI-X Reserved Reserved Reserved Reserved 2308215976Sjmallett Asserted Asserted Deasserted PCI-X Reserved Reserved Reserved Reserved 2309215976Sjmallett Asserted Asserted Asserted PCI-X Reserved Reserved Reserved Reserved 2310215976Sjmallett NOTE: The PCI Bus speed 'assumed' from the initialization 2311215976Sjmallett pattern is really intended for an operational range. 2312215976Sjmallett For example: If PINIT=100, this indicates PCI-X in the 2313215976Sjmallett 100-133MHz range. The PCI_CNT field can be used to further 2314215976Sjmallett determine a more exacting PCI Bus frequency value if 2315215976Sjmallett required. */ 2316215976Sjmallett uint64_t pcicnt : 32; /**< Free Running PCI Clock counter. 2317215976Sjmallett At PCI Reset, the PCICNT=0, and is auto-incremented 2318215976Sjmallett on every PCI clock and will auto-wrap back to zero 2319215976Sjmallett when saturated. 2320215976Sjmallett NOTE: Writes override the auto-increment to allow 2321215976Sjmallett software to preload any initial value. 2322215976Sjmallett The PCICNT field is provided to software as a means 2323215976Sjmallett to determine the PCI Bus Speed. 2324215976Sjmallett Assuming software has knowledge of the core frequency 2325215976Sjmallett (eclk), this register can be written with a value X, 2326215976Sjmallett wait 'n' core clocks(eclk) and then read later(Y) to 2327215976Sjmallett determine \#PCI clocks(Y-X) have elapsed within 'n' core 2328215976Sjmallett clocks to determine the PCI input Clock frequency. */ 2329215976Sjmallett#else 2330215976Sjmallett uint64_t pcicnt : 32; 2331215976Sjmallett uint64_t ap_speed : 2; 2332215976Sjmallett uint64_t ap_pcix : 1; 2333215976Sjmallett uint64_t hm_speed : 2; 2334215976Sjmallett uint64_t hm_pcix : 1; 2335215976Sjmallett uint64_t reserved_38_63 : 26; 2336215976Sjmallett#endif 2337215976Sjmallett } s; 2338215976Sjmallett struct cvmx_pci_cnt_reg_s cn50xx; 2339215976Sjmallett struct cvmx_pci_cnt_reg_s cn58xx; 2340215976Sjmallett struct cvmx_pci_cnt_reg_s cn58xxp1; 2341215976Sjmallett}; 2342215976Sjmalletttypedef union cvmx_pci_cnt_reg cvmx_pci_cnt_reg_t; 2343215976Sjmallett 2344215976Sjmallett/** 2345215976Sjmallett * cvmx_pci_ctl_status_2 2346215976Sjmallett * 2347215976Sjmallett * PCI_CTL_STATUS_2 = PCI Control Status 2 Register 2348215976Sjmallett * 2349215976Sjmallett * Control status register accessable from both PCI and NCB. 2350215976Sjmallett */ 2351215976Sjmallettunion cvmx_pci_ctl_status_2 2352215976Sjmallett{ 2353215976Sjmallett uint32_t u32; 2354215976Sjmallett struct cvmx_pci_ctl_status_2_s 2355215976Sjmallett { 2356215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2357215976Sjmallett uint32_t reserved_29_31 : 3; 2358215976Sjmallett uint32_t bb1_hole : 3; /**< Big BAR 1 Hole 2359215976Sjmallett NOT IN PASS 1 NOR PASS 2 2360215976Sjmallett When PCI_CTL_STATUS_2[BB1]=1, this field defines 2361215976Sjmallett an encoded size of the upper BAR1 region which 2362215976Sjmallett OCTEON will mask out (ie: not respond to). 2363215976Sjmallett (see definition of BB1_HOLE and BB1_SIZ encodings 2364215976Sjmallett in the PCI_CTL_STATUS_2[BB1] definition below). */ 2365215976Sjmallett uint32_t bb1_siz : 1; /**< Big BAR 1 Size 2366215976Sjmallett NOT IN PASS 1 NOR PASS 2 2367215976Sjmallett When PCI_CTL_STATUS_2[BB1]=1, this field defines 2368215976Sjmallett the programmable SIZE of BAR 1. 2369215976Sjmallett - 0: 1GB / 1: 2GB */ 2370215976Sjmallett uint32_t bb_ca : 1; /**< Set to '1' for Big Bar Mode to do STT/LDT L2C 2371215976Sjmallett operations. 2372215976Sjmallett NOT IN PASS 1 NOR PASS 2 */ 2373215976Sjmallett uint32_t bb_es : 2; /**< Big Bar Node Endian Swap Mode 2374215976Sjmallett - 0: No Swizzle 2375215976Sjmallett - 1: Byte Swizzle (per-QW) 2376215976Sjmallett - 2: Byte Swizzle (per-LW) 2377215976Sjmallett - 3: LongWord Swizzle 2378215976Sjmallett NOT IN PASS 1 NOR PASS 2 */ 2379215976Sjmallett uint32_t bb1 : 1; /**< Big Bar 1 Enable 2380215976Sjmallett NOT IN PASS 1 NOR PASS 2 2381215976Sjmallett When PCI_CTL_STATUS_2[BB1] is set, the following differences 2382215976Sjmallett occur: 2383215976Sjmallett - OCTEON's BAR1 becomes somewhere in the range 512-2048 MB rather 2384215976Sjmallett than the default 128MB. 2385215976Sjmallett - The following table indicates the effective size of 2386215976Sjmallett BAR1 when BB1 is set: 2387215976Sjmallett BB1_SIZ BB1_HOLE Effective size Comment 2388215976Sjmallett +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2389215976Sjmallett 0 0 1024 MB Normal 1GB BAR 2390215976Sjmallett 0 1 1008 MB 1 GB, 16 MB hole 2391215976Sjmallett 0 2 992 MB 1 GB, 32 MB hole 2392215976Sjmallett 0 3 960 MB 1 GB, 64 MB hole 2393215976Sjmallett 0 4 896 MB 1 GB,128 MB hole 2394215976Sjmallett 0 5 768 MB 1 GB,256 MB hole 2395215976Sjmallett 0 6 512 MB 1 GB,512 MB hole 2396215976Sjmallett 0 7 Illegal 2397215976Sjmallett 1 0 2048 MB Normal 2GB BAR 2398215976Sjmallett 1 1 2032 MB 2 GB, 16 MB hole 2399215976Sjmallett 1 2 2016 MB 2 GB, 32 MB hole 2400215976Sjmallett 1 3 1984 MB 2 GB, 64 MB hole 2401215976Sjmallett 1 4 1920 MB 2 GB,128 MB hole 2402215976Sjmallett 1 5 1792 MB 2 GB,256 MB hole 2403215976Sjmallett 1 6 1536 MB 2 GB,512 MB hole 2404215976Sjmallett 1 7 Illegal 2405215976Sjmallett - When BB1_SIZ is 0: PCI_CFG06[LBASE<2:0>] reads as zero 2406215976Sjmallett and are ignored on write. BAR1 is an entirely ordinary 2407215976Sjmallett 1 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0. 2408215976Sjmallett When BB1_HOLE is not zero, BAR1 addresses are programmed 2409215976Sjmallett as if the BAR were 1GB, but, OCTEON does not respond 2410215976Sjmallett to addresses in the programmed holes. 2411215976Sjmallett - When BB1_SIZ is 1: PCI_CFG06[LBASE<3:0>] reads as zero 2412215976Sjmallett and are ignored on write. BAR1 is an entirely ordinary 2413215976Sjmallett 2 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0. 2414215976Sjmallett When BB1_HOLE is not zero, BAR1 addresses are programmed 2415215976Sjmallett as if the BAR were 2GB, but, OCTEON does not respond 2416215976Sjmallett to addresses in the programmed holes. 2417215976Sjmallett - Note that the BB1_HOLE value has no effect on the 2418215976Sjmallett PCI_CFG06[LBASE] behavior. BB1_HOLE only affects whether 2419215976Sjmallett OCTEON accepts an address. BB1_SIZ does affect PCI_CFG06[LBASE] 2420215976Sjmallett behavior, however. 2421215976Sjmallett - The first 128MB, i.e. addresses on the PCI bus in the range 2422215976Sjmallett BAR1+0 .. BAR1+0x07FFFFFF 2423215976Sjmallett access OCTEON's DRAM addresses with PCI_BAR1_INDEX CSR's 2424215976Sjmallett as before 2425215976Sjmallett - The remaining address space, i.e. addresses 2426215976Sjmallett on the PCI bus in the range 2427215976Sjmallett BAR1+0x08000000 .. BAR1+size-1, 2428215976Sjmallett where size is the size of BAR1 as selected by the above 2429215976Sjmallett table (based on the BB1_SIZ and BB1_HOLE values), are mapped to 2430215976Sjmallett OCTEON physical DRAM addresses as follows: 2431215976Sjmallett PCI Address Range OCTEON Physical Address Range 2432215976Sjmallett ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2433215976Sjmallett BAR1+0x08000000 .. BAR1+size-1 | 0x88000000 .. 0x7FFFFFFF+size 2434215976Sjmallett and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and 2435215976Sjmallett PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit 2436215976Sjmallett for these references. 2437215976Sjmallett The consequences of any burst that crosses the end of the PCI 2438215976Sjmallett Address Range for BAR1 are unpredicable. 2439215976Sjmallett - The consequences of any burst access that crosses the boundary 2440215976Sjmallett between BAR1+0x07FFFFFF and BAR1+0x08000000 are unpredictable in PCI-X 2441215976Sjmallett mode. OCTEON may disconnect PCI references at this boundary. */ 2442215976Sjmallett uint32_t bb0 : 1; /**< Big Bar 0 Enable 2443215976Sjmallett NOT IN PASS 1 NOR PASS 2 2444215976Sjmallett When PCI_CTL_STATUS_2[BB0] is set, the following 2445215976Sjmallett differences occur: 2446215976Sjmallett - OCTEON's BAR0 becomes 2GB rather than the default 4KB. 2447215976Sjmallett PCI_CFG04[LBASE<18:0>] reads as zero and is ignored on write. 2448215976Sjmallett - OCTEON's BAR0 becomes burstable. (When BB0 is clear, OCTEON 2449215976Sjmallett single-phase disconnects PCI BAR0 reads and PCI/PCI-X BAR0 2450215976Sjmallett writes, and splits (burstably) PCI-X BAR0 reads.) 2451215976Sjmallett - The first 4KB, i.e. addresses on the PCI bus in the range 2452215976Sjmallett BAR0+0 .. BAR0+0xFFF 2453215976Sjmallett access OCTEON's PCI-type CSR's as when BB0 is clear. 2454215976Sjmallett - The remaining address space, i.e. addresses on the PCI bus 2455215976Sjmallett in the range 2456215976Sjmallett BAR0+0x1000 .. BAR0+0x7FFFFFFF 2457215976Sjmallett are mapped to OCTEON physical DRAM addresses as follows: 2458215976Sjmallett PCI Address Range OCTEON Physical Address Range 2459215976Sjmallett ------------------------------------+------------------------------ 2460215976Sjmallett BAR0+0x00001000 .. BAR0+0x0FFFFFFF | 0x000001000 .. 0x00FFFFFFF 2461215976Sjmallett BAR0+0x10000000 .. BAR0+0x1FFFFFFF | 0x410000000 .. 0x41FFFFFFF 2462215976Sjmallett BAR0+0x20000000 .. BAR0+0x7FFFFFFF | 0x020000000 .. 0x07FFFFFFF 2463215976Sjmallett and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and 2464215976Sjmallett PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit 2465215976Sjmallett for these references. 2466215976Sjmallett The consequences of any burst that crosses the end of the PCI 2467215976Sjmallett Address Range for BAR0 are unpredicable. 2468215976Sjmallett - The consequences of any burst access that crosses the boundary 2469215976Sjmallett between BAR0+0xFFF and BAR0+0x1000 are unpredictable in PCI-X 2470215976Sjmallett mode. OCTEON may disconnect PCI references at this boundary. 2471215976Sjmallett - The results of any burst read that crosses the boundary 2472215976Sjmallett between BAR0+0x0FFFFFFF and BAR0+0x10000000 are unpredictable. 2473215976Sjmallett The consequences of any burst write that crosses this same 2474215976Sjmallett boundary are unpredictable. 2475215976Sjmallett - The results of any burst read that crosses the boundary 2476215976Sjmallett between BAR0+0x1FFFFFFF and BAR0+0x20000000 are unpredictable. 2477215976Sjmallett The consequences of any burst write that crosses this same 2478215976Sjmallett boundary are unpredictable. */ 2479215976Sjmallett uint32_t erst_n : 1; /**< Reset active Low. PASS-2 */ 2480215976Sjmallett uint32_t bar2pres : 1; /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN]) 2481215976Sjmallett is NOT blown the value of this field is '0' after 2482215976Sjmallett reset and BAR2 is NOT present. When the fuse IS 2483215976Sjmallett blown the value of this field is '1' after reset 2484215976Sjmallett and BAR2 is present. Note that SW can change this 2485215976Sjmallett field after reset. This is a PASS-2 field. */ 2486215976Sjmallett uint32_t scmtyp : 1; /**< Split Completion Message CMD Type (0=RD/1=WR) 2487215976Sjmallett When SCM=1, SCMTYP specifies the CMD intent (R/W) */ 2488215976Sjmallett uint32_t scm : 1; /**< Split Completion Message Detected (Read or Write) */ 2489215976Sjmallett uint32_t en_wfilt : 1; /**< When '1' the window-access filter is enabled. 2490215976Sjmallett Unfilter writes are: 2491215976Sjmallett MIO, SubId0 2492215976Sjmallett MIO, SubId7 2493215976Sjmallett NPI, SubId0 2494215976Sjmallett NPI, SubId7 2495215976Sjmallett POW, SubId7 2496215976Sjmallett DFA, SubId7 2497215976Sjmallett IPD, SubId7 2498215976Sjmallett Unfiltered Reads are: 2499215976Sjmallett MIO, SubId0 2500215976Sjmallett MIO, SubId7 2501215976Sjmallett NPI, SubId0 2502215976Sjmallett NPI, SubId7 2503215976Sjmallett POW, SubId1 2504215976Sjmallett POW, SubId2 2505215976Sjmallett POW, SubId3 2506215976Sjmallett POW, SubId7 2507215976Sjmallett DFA, SubId7 2508215976Sjmallett IPD, SubId7 */ 2509215976Sjmallett uint32_t reserved_14_14 : 1; 2510215976Sjmallett uint32_t ap_pcix : 1; /**< PCX Core Mode status (0=PCI Bus/1=PCIX) 2511215976Sjmallett If one or more of PCI_DEVSEL_N, PCI_STOP_N, and 2512215976Sjmallett PCI_TRDY_N are asserted at the rising edge of 2513215976Sjmallett PCI_RST_N, the device enters PCI-X mode. 2514215976Sjmallett Otherwise, the device enters conventional PCI 2515215976Sjmallett mode at the rising edge of RST#. */ 2516215976Sjmallett uint32_t ap_64ad : 1; /**< PCX Core Bus status (0=32b Bus/1=64b Bus) 2517215976Sjmallett When PCI_RST_N pin is de-asserted, the state 2518215976Sjmallett of PCI_REQ64_N(driven by central agent) determines 2519215976Sjmallett the width of the PCI/X bus. */ 2520215976Sjmallett uint32_t b12_bist : 1; /**< Bist Status For Memeory In B12 */ 2521215976Sjmallett uint32_t pmo_amod : 1; /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */ 2522215976Sjmallett uint32_t pmo_fpc : 3; /**< PMO-ARB Fixed Priority Counter 2523215976Sjmallett When PMO_AMOD=0 (FP mode), this field represents 2524215976Sjmallett the \# of CMD1 requests that are issued (at higher 2525215976Sjmallett priority) before a single lower priority CMD0 2526215976Sjmallett is allowed to issue (to ensure foward progress). 2527215976Sjmallett - 0: 1 CMD1 Request issued before CMD0 allowed 2528215976Sjmallett - ... 2529215976Sjmallett - 7: 8 CMD1 Requests issued before CMD0 allowed */ 2530215976Sjmallett uint32_t tsr_hwm : 3; /**< Target Split-Read ADB(allowable disconnect boundary) 2531215976Sjmallett High Water Mark. 2532215976Sjmallett Specifies the number of ADBs(128 Byte aligned chunks) 2533215976Sjmallett that are accumulated(pending) BEFORE the Target Split 2534215976Sjmallett completion is attempted on the PCI bus. 2535215976Sjmallett - 0: RESERVED/ILLEGAL 2536215976Sjmallett - 1: 2 Pending ADBs (129B-256B) 2537215976Sjmallett - 2: 3 Pending ADBs (257B-384B) 2538215976Sjmallett - 3: 4 Pending ADBs (385B-512B) 2539215976Sjmallett - 4: 5 Pending ADBs (513B-640B) 2540215976Sjmallett - 5: 6 Pending ADBs (641B-768B) 2541215976Sjmallett - 6: 7 Pending ADBs (769B-896B) 2542215976Sjmallett - 7: 8 Pending ADBs (897B-1024B) 2543215976Sjmallett Example: Suppose a 1KB target memory request with 2544215976Sjmallett starting byte offset address[6:0]=0x7F is split by 2545215976Sjmallett the OCTEON and the TSR_HWM=1(2 ADBs). 2546215976Sjmallett The OCTEON will start the target split completion 2547215976Sjmallett on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B 2548215976Sjmallett of data have been received from memory (even though 2549215976Sjmallett the remaining 895B has not yet been received). The 2550215976Sjmallett OCTEON will continue the split completion until it 2551215976Sjmallett has consumed all of the pended split data. If the 2552215976Sjmallett full transaction length(1KB) of data was NOT entirely 2553215976Sjmallett transferred, then OCTEON will terminate the split 2554215976Sjmallett completion and again wait for another 2 ADB-aligned data 2555215976Sjmallett chunks(256B) of pended split data to be received from 2556215976Sjmallett memory before starting another split completion request. 2557215976Sjmallett This allows Octeon (as split completer), to send back 2558215976Sjmallett multiple split completions for a given large split 2559215976Sjmallett transaction without having to wait for the entire 2560215976Sjmallett transaction length to be received from memory. 2561215976Sjmallett NOTE: For split transaction sizes 'smaller' than the 2562215976Sjmallett specified TSR_HWM value, the split completion 2563215976Sjmallett is started when the last datum has been received from 2564215976Sjmallett memory. 2565215976Sjmallett NOTE: It is IMPERATIVE that this field NEVER BE 2566215976Sjmallett written to a ZERO value. A value of zero is 2567215976Sjmallett reserved/illegal and can result in PCIX bus hangs). */ 2568215976Sjmallett uint32_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 2569215976Sjmallett clear '0' BAR2 access will be target-aborted. */ 2570215976Sjmallett uint32_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to 2571215976Sjmallett determine the endian swap mode. */ 2572215976Sjmallett uint32_t bar2_cax : 1; /**< Value will be XORed with pci-address[38] to 2573215976Sjmallett determine the L2 cache attribute. 2574215976Sjmallett When XOR result is 1, not cached in L2 */ 2575215976Sjmallett#else 2576215976Sjmallett uint32_t bar2_cax : 1; 2577215976Sjmallett uint32_t bar2_esx : 2; 2578215976Sjmallett uint32_t bar2_enb : 1; 2579215976Sjmallett uint32_t tsr_hwm : 3; 2580215976Sjmallett uint32_t pmo_fpc : 3; 2581215976Sjmallett uint32_t pmo_amod : 1; 2582215976Sjmallett uint32_t b12_bist : 1; 2583215976Sjmallett uint32_t ap_64ad : 1; 2584215976Sjmallett uint32_t ap_pcix : 1; 2585215976Sjmallett uint32_t reserved_14_14 : 1; 2586215976Sjmallett uint32_t en_wfilt : 1; 2587215976Sjmallett uint32_t scm : 1; 2588215976Sjmallett uint32_t scmtyp : 1; 2589215976Sjmallett uint32_t bar2pres : 1; 2590215976Sjmallett uint32_t erst_n : 1; 2591215976Sjmallett uint32_t bb0 : 1; 2592215976Sjmallett uint32_t bb1 : 1; 2593215976Sjmallett uint32_t bb_es : 2; 2594215976Sjmallett uint32_t bb_ca : 1; 2595215976Sjmallett uint32_t bb1_siz : 1; 2596215976Sjmallett uint32_t bb1_hole : 3; 2597215976Sjmallett uint32_t reserved_29_31 : 3; 2598215976Sjmallett#endif 2599215976Sjmallett } s; 2600215976Sjmallett struct cvmx_pci_ctl_status_2_s cn30xx; 2601215976Sjmallett struct cvmx_pci_ctl_status_2_cn31xx 2602215976Sjmallett { 2603215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2604215976Sjmallett uint32_t reserved_20_31 : 12; 2605215976Sjmallett uint32_t erst_n : 1; /**< Reset active Low. */ 2606215976Sjmallett uint32_t bar2pres : 1; /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN]) 2607215976Sjmallett is NOT blown the value of this field is '0' after 2608215976Sjmallett reset and BAR2 is NOT present. When the fuse IS 2609215976Sjmallett blown the value of this field is '1' after reset 2610215976Sjmallett and BAR2 is present. Note that SW can change this 2611215976Sjmallett field after reset. */ 2612215976Sjmallett uint32_t scmtyp : 1; /**< Split Completion Message CMD Type (0=RD/1=WR) 2613215976Sjmallett When SCM=1, SCMTYP specifies the CMD intent (R/W) */ 2614215976Sjmallett uint32_t scm : 1; /**< Split Completion Message Detected (Read or Write) */ 2615215976Sjmallett uint32_t en_wfilt : 1; /**< When '1' the window-access filter is enabled. 2616215976Sjmallett Unfilter writes are: 2617215976Sjmallett MIO, SubId0 2618215976Sjmallett MIO, SubId7 2619215976Sjmallett NPI, SubId0 2620215976Sjmallett NPI, SubId7 2621215976Sjmallett POW, SubId7 2622215976Sjmallett DFA, SubId7 2623215976Sjmallett IPD, SubId7 2624215976Sjmallett USBN, SubId7 2625215976Sjmallett Unfiltered Reads are: 2626215976Sjmallett MIO, SubId0 2627215976Sjmallett MIO, SubId7 2628215976Sjmallett NPI, SubId0 2629215976Sjmallett NPI, SubId7 2630215976Sjmallett POW, SubId1 2631215976Sjmallett POW, SubId2 2632215976Sjmallett POW, SubId3 2633215976Sjmallett POW, SubId7 2634215976Sjmallett DFA, SubId7 2635215976Sjmallett IPD, SubId7 2636215976Sjmallett USBN, SubId7 */ 2637215976Sjmallett uint32_t reserved_14_14 : 1; 2638215976Sjmallett uint32_t ap_pcix : 1; /**< PCX Core Mode status (0=PCI Bus/1=PCIX) */ 2639215976Sjmallett uint32_t ap_64ad : 1; /**< PCX Core Bus status (0=32b Bus/1=64b Bus) */ 2640215976Sjmallett uint32_t b12_bist : 1; /**< Bist Status For Memeory In B12 */ 2641215976Sjmallett uint32_t pmo_amod : 1; /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */ 2642215976Sjmallett uint32_t pmo_fpc : 3; /**< PMO-ARB Fixed Priority Counter 2643215976Sjmallett When PMO_AMOD=0 (FP mode), this field represents 2644215976Sjmallett the \# of CMD1 requests that are issued (at higher 2645215976Sjmallett priority) before a single lower priority CMD0 2646215976Sjmallett is allowed to issue (to ensure foward progress). 2647215976Sjmallett - 0: 1 CMD1 Request issued before CMD0 allowed 2648215976Sjmallett - ... 2649215976Sjmallett - 7: 8 CMD1 Requests issued before CMD0 allowed */ 2650215976Sjmallett uint32_t tsr_hwm : 3; /**< Target Split-Read ADB(allowable disconnect boundary) 2651215976Sjmallett High Water Mark. 2652215976Sjmallett Specifies the number of ADBs(128 Byte aligned chunks) 2653215976Sjmallett that are accumulated(pending) BEFORE the Target Split 2654215976Sjmallett completion is attempted on the PCI bus. 2655215976Sjmallett - 0: RESERVED/ILLEGAL 2656215976Sjmallett - 1: 2 Pending ADBs (129B-256B) 2657215976Sjmallett - 2: 3 Pending ADBs (257B-384B) 2658215976Sjmallett - 3: 4 Pending ADBs (385B-512B) 2659215976Sjmallett - 4: 5 Pending ADBs (513B-640B) 2660215976Sjmallett - 5: 6 Pending ADBs (641B-768B) 2661215976Sjmallett - 6: 7 Pending ADBs (769B-896B) 2662215976Sjmallett - 7: 8 Pending ADBs (897B-1024B) 2663215976Sjmallett Example: Suppose a 1KB target memory request with 2664215976Sjmallett starting byte offset address[6:0]=0x7F is split by 2665215976Sjmallett the OCTEON and the TSR_HWM=1(2 ADBs). 2666215976Sjmallett The OCTEON will start the target split completion 2667215976Sjmallett on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B 2668215976Sjmallett of data have been received from memory (even though 2669215976Sjmallett the remaining 895B has not yet been received). The 2670215976Sjmallett OCTEON will continue the split completion until it 2671215976Sjmallett has consumed all of the pended split data. If the 2672215976Sjmallett full transaction length(1KB) of data was NOT entirely 2673215976Sjmallett transferred, then OCTEON will terminate the split 2674215976Sjmallett completion and again wait for another 2 ADB-aligned data 2675215976Sjmallett chunks(256B) of pended split data to be received from 2676215976Sjmallett memory before starting another split completion request. 2677215976Sjmallett This allows Octeon (as split completer), to send back 2678215976Sjmallett multiple split completions for a given large split 2679215976Sjmallett transaction without having to wait for the entire 2680215976Sjmallett transaction length to be received from memory. 2681215976Sjmallett NOTE: For split transaction sizes 'smaller' than the 2682215976Sjmallett specified TSR_HWM value, the split completion 2683215976Sjmallett is started when the last datum has been received from 2684215976Sjmallett memory. 2685215976Sjmallett NOTE: It is IMPERATIVE that this field NEVER BE 2686215976Sjmallett written to a ZERO value. A value of zero is 2687215976Sjmallett reserved/illegal and can result in PCIX bus hangs). */ 2688215976Sjmallett uint32_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 2689215976Sjmallett clear '0' BAR2 access will be target-aborted. */ 2690215976Sjmallett uint32_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to 2691215976Sjmallett determine the endian swap mode. */ 2692215976Sjmallett uint32_t bar2_cax : 1; /**< Value will be XORed with pci-address[38] to 2693215976Sjmallett determine the L2 cache attribute. 2694215976Sjmallett When XOR result is 1, not allocated in L2 cache */ 2695215976Sjmallett#else 2696215976Sjmallett uint32_t bar2_cax : 1; 2697215976Sjmallett uint32_t bar2_esx : 2; 2698215976Sjmallett uint32_t bar2_enb : 1; 2699215976Sjmallett uint32_t tsr_hwm : 3; 2700215976Sjmallett uint32_t pmo_fpc : 3; 2701215976Sjmallett uint32_t pmo_amod : 1; 2702215976Sjmallett uint32_t b12_bist : 1; 2703215976Sjmallett uint32_t ap_64ad : 1; 2704215976Sjmallett uint32_t ap_pcix : 1; 2705215976Sjmallett uint32_t reserved_14_14 : 1; 2706215976Sjmallett uint32_t en_wfilt : 1; 2707215976Sjmallett uint32_t scm : 1; 2708215976Sjmallett uint32_t scmtyp : 1; 2709215976Sjmallett uint32_t bar2pres : 1; 2710215976Sjmallett uint32_t erst_n : 1; 2711215976Sjmallett uint32_t reserved_20_31 : 12; 2712215976Sjmallett#endif 2713215976Sjmallett } cn31xx; 2714215976Sjmallett struct cvmx_pci_ctl_status_2_s cn38xx; 2715215976Sjmallett struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2; 2716215976Sjmallett struct cvmx_pci_ctl_status_2_s cn50xx; 2717215976Sjmallett struct cvmx_pci_ctl_status_2_s cn58xx; 2718215976Sjmallett struct cvmx_pci_ctl_status_2_s cn58xxp1; 2719215976Sjmallett}; 2720215976Sjmalletttypedef union cvmx_pci_ctl_status_2 cvmx_pci_ctl_status_2_t; 2721215976Sjmallett 2722215976Sjmallett/** 2723215976Sjmallett * cvmx_pci_dbell# 2724215976Sjmallett * 2725215976Sjmallett * PCI_DBELL0 = PCI Doorbell-0 2726215976Sjmallett * 2727215976Sjmallett * The value to write to the doorbell 0 register. The value in this register is acted upon when the 2728215976Sjmallett * least-significant-byte of this register is written. 2729215976Sjmallett */ 2730215976Sjmallettunion cvmx_pci_dbellx 2731215976Sjmallett{ 2732215976Sjmallett uint32_t u32; 2733215976Sjmallett struct cvmx_pci_dbellx_s 2734215976Sjmallett { 2735215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2736215976Sjmallett uint32_t reserved_16_31 : 16; 2737215976Sjmallett uint32_t inc_val : 16; /**< Software writes this register with the 2738215976Sjmallett number of new Instructions to be processed 2739215976Sjmallett on the Instruction Queue. When read this 2740215976Sjmallett register contains the last write value. */ 2741215976Sjmallett#else 2742215976Sjmallett uint32_t inc_val : 16; 2743215976Sjmallett uint32_t reserved_16_31 : 16; 2744215976Sjmallett#endif 2745215976Sjmallett } s; 2746215976Sjmallett struct cvmx_pci_dbellx_s cn30xx; 2747215976Sjmallett struct cvmx_pci_dbellx_s cn31xx; 2748215976Sjmallett struct cvmx_pci_dbellx_s cn38xx; 2749215976Sjmallett struct cvmx_pci_dbellx_s cn38xxp2; 2750215976Sjmallett struct cvmx_pci_dbellx_s cn50xx; 2751215976Sjmallett struct cvmx_pci_dbellx_s cn58xx; 2752215976Sjmallett struct cvmx_pci_dbellx_s cn58xxp1; 2753215976Sjmallett}; 2754215976Sjmalletttypedef union cvmx_pci_dbellx cvmx_pci_dbellx_t; 2755215976Sjmallett 2756215976Sjmallett/** 2757215976Sjmallett * cvmx_pci_dma_cnt# 2758215976Sjmallett * 2759215976Sjmallett * PCI_DMA_CNT0 = PCI DMA Count0 2760215976Sjmallett * 2761215976Sjmallett * Keeps track of the number of DMAs or bytes sent by DMAs. The value in this register is acted upon when the 2762215976Sjmallett * least-significant-byte of this register is written. 2763215976Sjmallett */ 2764215976Sjmallettunion cvmx_pci_dma_cntx 2765215976Sjmallett{ 2766215976Sjmallett uint32_t u32; 2767215976Sjmallett struct cvmx_pci_dma_cntx_s 2768215976Sjmallett { 2769215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2770215976Sjmallett uint32_t dma_cnt : 32; /**< Update with the number of DMAs completed or the 2771215976Sjmallett number of bytes sent for DMA's associated with 2772215976Sjmallett this counter. When this register is written the 2773215976Sjmallett value written to [15:0] will be subtracted from 2774215976Sjmallett the value in this register. */ 2775215976Sjmallett#else 2776215976Sjmallett uint32_t dma_cnt : 32; 2777215976Sjmallett#endif 2778215976Sjmallett } s; 2779215976Sjmallett struct cvmx_pci_dma_cntx_s cn30xx; 2780215976Sjmallett struct cvmx_pci_dma_cntx_s cn31xx; 2781215976Sjmallett struct cvmx_pci_dma_cntx_s cn38xx; 2782215976Sjmallett struct cvmx_pci_dma_cntx_s cn38xxp2; 2783215976Sjmallett struct cvmx_pci_dma_cntx_s cn50xx; 2784215976Sjmallett struct cvmx_pci_dma_cntx_s cn58xx; 2785215976Sjmallett struct cvmx_pci_dma_cntx_s cn58xxp1; 2786215976Sjmallett}; 2787215976Sjmalletttypedef union cvmx_pci_dma_cntx cvmx_pci_dma_cntx_t; 2788215976Sjmallett 2789215976Sjmallett/** 2790215976Sjmallett * cvmx_pci_dma_int_lev# 2791215976Sjmallett * 2792215976Sjmallett * PCI_DMA_INT_LEV0 = PCI DMA Sent Interrupt Level For DMA 0 2793215976Sjmallett * 2794215976Sjmallett * Interrupt when the value in PCI_DMA_CNT0 is equal to or greater than the register value. 2795215976Sjmallett */ 2796215976Sjmallettunion cvmx_pci_dma_int_levx 2797215976Sjmallett{ 2798215976Sjmallett uint32_t u32; 2799215976Sjmallett struct cvmx_pci_dma_int_levx_s 2800215976Sjmallett { 2801215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2802215976Sjmallett uint32_t pkt_cnt : 32; /**< When PCI_DMA_CNT0 exceeds the value in this 2803215976Sjmallett DCNT0 will be set in PCI_INT_SUM and PCI_INT_SUM2. */ 2804215976Sjmallett#else 2805215976Sjmallett uint32_t pkt_cnt : 32; 2806215976Sjmallett#endif 2807215976Sjmallett } s; 2808215976Sjmallett struct cvmx_pci_dma_int_levx_s cn30xx; 2809215976Sjmallett struct cvmx_pci_dma_int_levx_s cn31xx; 2810215976Sjmallett struct cvmx_pci_dma_int_levx_s cn38xx; 2811215976Sjmallett struct cvmx_pci_dma_int_levx_s cn38xxp2; 2812215976Sjmallett struct cvmx_pci_dma_int_levx_s cn50xx; 2813215976Sjmallett struct cvmx_pci_dma_int_levx_s cn58xx; 2814215976Sjmallett struct cvmx_pci_dma_int_levx_s cn58xxp1; 2815215976Sjmallett}; 2816215976Sjmalletttypedef union cvmx_pci_dma_int_levx cvmx_pci_dma_int_levx_t; 2817215976Sjmallett 2818215976Sjmallett/** 2819215976Sjmallett * cvmx_pci_dma_time# 2820215976Sjmallett * 2821215976Sjmallett * PCI_DMA_TIME0 = PCI DMA Sent Timer For DMA0 2822215976Sjmallett * 2823215976Sjmallett * Time to wait from DMA being sent before issuing an interrupt. 2824215976Sjmallett */ 2825215976Sjmallettunion cvmx_pci_dma_timex 2826215976Sjmallett{ 2827215976Sjmallett uint32_t u32; 2828215976Sjmallett struct cvmx_pci_dma_timex_s 2829215976Sjmallett { 2830215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2831215976Sjmallett uint32_t dma_time : 32; /**< Number of PCI clock cycle to wait before 2832215976Sjmallett setting DTIME0 in PCI_INT_SUM and PCI_INT_SUM2. 2833215976Sjmallett After PCI_DMA_CNT0 becomes non-zero. 2834215976Sjmallett The timer is reset when the 2835215976Sjmallett PCI_INT_SUM[27] register is cleared. */ 2836215976Sjmallett#else 2837215976Sjmallett uint32_t dma_time : 32; 2838215976Sjmallett#endif 2839215976Sjmallett } s; 2840215976Sjmallett struct cvmx_pci_dma_timex_s cn30xx; 2841215976Sjmallett struct cvmx_pci_dma_timex_s cn31xx; 2842215976Sjmallett struct cvmx_pci_dma_timex_s cn38xx; 2843215976Sjmallett struct cvmx_pci_dma_timex_s cn38xxp2; 2844215976Sjmallett struct cvmx_pci_dma_timex_s cn50xx; 2845215976Sjmallett struct cvmx_pci_dma_timex_s cn58xx; 2846215976Sjmallett struct cvmx_pci_dma_timex_s cn58xxp1; 2847215976Sjmallett}; 2848215976Sjmalletttypedef union cvmx_pci_dma_timex cvmx_pci_dma_timex_t; 2849215976Sjmallett 2850215976Sjmallett/** 2851215976Sjmallett * cvmx_pci_instr_count# 2852215976Sjmallett * 2853215976Sjmallett * PCI_INSTR_COUNT0 = PCI Instructions Outstanding Request Count 2854215976Sjmallett * 2855215976Sjmallett * The number of instructions to be fetched by the Instruction-0 Engine. 2856215976Sjmallett */ 2857215976Sjmallettunion cvmx_pci_instr_countx 2858215976Sjmallett{ 2859215976Sjmallett uint32_t u32; 2860215976Sjmallett struct cvmx_pci_instr_countx_s 2861215976Sjmallett { 2862215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2863215976Sjmallett uint32_t icnt : 32; /**< Number of Instructions to be fetched by the 2864215976Sjmallett Instruction Engine. 2865215976Sjmallett A write of any non zero value to this register 2866215976Sjmallett will clear the value of this register. */ 2867215976Sjmallett#else 2868215976Sjmallett uint32_t icnt : 32; 2869215976Sjmallett#endif 2870215976Sjmallett } s; 2871215976Sjmallett struct cvmx_pci_instr_countx_s cn30xx; 2872215976Sjmallett struct cvmx_pci_instr_countx_s cn31xx; 2873215976Sjmallett struct cvmx_pci_instr_countx_s cn38xx; 2874215976Sjmallett struct cvmx_pci_instr_countx_s cn38xxp2; 2875215976Sjmallett struct cvmx_pci_instr_countx_s cn50xx; 2876215976Sjmallett struct cvmx_pci_instr_countx_s cn58xx; 2877215976Sjmallett struct cvmx_pci_instr_countx_s cn58xxp1; 2878215976Sjmallett}; 2879215976Sjmalletttypedef union cvmx_pci_instr_countx cvmx_pci_instr_countx_t; 2880215976Sjmallett 2881215976Sjmallett/** 2882215976Sjmallett * cvmx_pci_int_enb 2883215976Sjmallett * 2884215976Sjmallett * PCI_INT_ENB = PCI Interrupt Enable 2885215976Sjmallett * 2886215976Sjmallett * Enables interrupt bits in the PCI_INT_SUM register. 2887215976Sjmallett */ 2888215976Sjmallettunion cvmx_pci_int_enb 2889215976Sjmallett{ 2890215976Sjmallett uint64_t u64; 2891215976Sjmallett struct cvmx_pci_int_enb_s 2892215976Sjmallett { 2893215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2894215976Sjmallett uint64_t reserved_34_63 : 30; 2895215976Sjmallett uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */ 2896215976Sjmallett uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */ 2897215976Sjmallett uint64_t win_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */ 2898215976Sjmallett uint64_t dma1_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */ 2899215976Sjmallett uint64_t dma0_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */ 2900215976Sjmallett uint64_t idtime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */ 2901215976Sjmallett uint64_t idtime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */ 2902215976Sjmallett uint64_t idcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */ 2903215976Sjmallett uint64_t idcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */ 2904215976Sjmallett uint64_t iptime3 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[24] */ 2905215976Sjmallett uint64_t iptime2 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[23] */ 2906215976Sjmallett uint64_t iptime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */ 2907215976Sjmallett uint64_t iptime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */ 2908215976Sjmallett uint64_t ipcnt3 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[20] */ 2909215976Sjmallett uint64_t ipcnt2 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[19] */ 2910215976Sjmallett uint64_t ipcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */ 2911215976Sjmallett uint64_t ipcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */ 2912215976Sjmallett uint64_t irsl_int : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */ 2913215976Sjmallett uint64_t ill_rrd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */ 2914215976Sjmallett uint64_t ill_rwr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */ 2915215976Sjmallett uint64_t idperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */ 2916215976Sjmallett uint64_t iaperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */ 2917215976Sjmallett uint64_t iserr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */ 2918215976Sjmallett uint64_t itsr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */ 2919215976Sjmallett uint64_t imsc_msg : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */ 2920215976Sjmallett uint64_t imsi_mabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */ 2921215976Sjmallett uint64_t imsi_tabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */ 2922215976Sjmallett uint64_t imsi_per : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */ 2923215976Sjmallett uint64_t imr_tto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */ 2924215976Sjmallett uint64_t imr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */ 2925215976Sjmallett uint64_t itr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */ 2926215976Sjmallett uint64_t imr_wtto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */ 2927215976Sjmallett uint64_t imr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */ 2928215976Sjmallett uint64_t itr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */ 2929215976Sjmallett#else 2930215976Sjmallett uint64_t itr_wabt : 1; 2931215976Sjmallett uint64_t imr_wabt : 1; 2932215976Sjmallett uint64_t imr_wtto : 1; 2933215976Sjmallett uint64_t itr_abt : 1; 2934215976Sjmallett uint64_t imr_abt : 1; 2935215976Sjmallett uint64_t imr_tto : 1; 2936215976Sjmallett uint64_t imsi_per : 1; 2937215976Sjmallett uint64_t imsi_tabt : 1; 2938215976Sjmallett uint64_t imsi_mabt : 1; 2939215976Sjmallett uint64_t imsc_msg : 1; 2940215976Sjmallett uint64_t itsr_abt : 1; 2941215976Sjmallett uint64_t iserr : 1; 2942215976Sjmallett uint64_t iaperr : 1; 2943215976Sjmallett uint64_t idperr : 1; 2944215976Sjmallett uint64_t ill_rwr : 1; 2945215976Sjmallett uint64_t ill_rrd : 1; 2946215976Sjmallett uint64_t irsl_int : 1; 2947215976Sjmallett uint64_t ipcnt0 : 1; 2948215976Sjmallett uint64_t ipcnt1 : 1; 2949215976Sjmallett uint64_t ipcnt2 : 1; 2950215976Sjmallett uint64_t ipcnt3 : 1; 2951215976Sjmallett uint64_t iptime0 : 1; 2952215976Sjmallett uint64_t iptime1 : 1; 2953215976Sjmallett uint64_t iptime2 : 1; 2954215976Sjmallett uint64_t iptime3 : 1; 2955215976Sjmallett uint64_t idcnt0 : 1; 2956215976Sjmallett uint64_t idcnt1 : 1; 2957215976Sjmallett uint64_t idtime0 : 1; 2958215976Sjmallett uint64_t idtime1 : 1; 2959215976Sjmallett uint64_t dma0_fi : 1; 2960215976Sjmallett uint64_t dma1_fi : 1; 2961215976Sjmallett uint64_t win_wr : 1; 2962215976Sjmallett uint64_t ill_wr : 1; 2963215976Sjmallett uint64_t ill_rd : 1; 2964215976Sjmallett uint64_t reserved_34_63 : 30; 2965215976Sjmallett#endif 2966215976Sjmallett } s; 2967215976Sjmallett struct cvmx_pci_int_enb_cn30xx 2968215976Sjmallett { 2969215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2970215976Sjmallett uint64_t reserved_34_63 : 30; 2971215976Sjmallett uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */ 2972215976Sjmallett uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */ 2973215976Sjmallett uint64_t win_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */ 2974215976Sjmallett uint64_t dma1_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */ 2975215976Sjmallett uint64_t dma0_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */ 2976215976Sjmallett uint64_t idtime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */ 2977215976Sjmallett uint64_t idtime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */ 2978215976Sjmallett uint64_t idcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */ 2979215976Sjmallett uint64_t idcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */ 2980215976Sjmallett uint64_t reserved_22_24 : 3; 2981215976Sjmallett uint64_t iptime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */ 2982215976Sjmallett uint64_t reserved_18_20 : 3; 2983215976Sjmallett uint64_t ipcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */ 2984215976Sjmallett uint64_t irsl_int : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */ 2985215976Sjmallett uint64_t ill_rrd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */ 2986215976Sjmallett uint64_t ill_rwr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */ 2987215976Sjmallett uint64_t idperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */ 2988215976Sjmallett uint64_t iaperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */ 2989215976Sjmallett uint64_t iserr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */ 2990215976Sjmallett uint64_t itsr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */ 2991215976Sjmallett uint64_t imsc_msg : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */ 2992215976Sjmallett uint64_t imsi_mabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */ 2993215976Sjmallett uint64_t imsi_tabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */ 2994215976Sjmallett uint64_t imsi_per : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */ 2995215976Sjmallett uint64_t imr_tto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */ 2996215976Sjmallett uint64_t imr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */ 2997215976Sjmallett uint64_t itr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */ 2998215976Sjmallett uint64_t imr_wtto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */ 2999215976Sjmallett uint64_t imr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */ 3000215976Sjmallett uint64_t itr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */ 3001215976Sjmallett#else 3002215976Sjmallett uint64_t itr_wabt : 1; 3003215976Sjmallett uint64_t imr_wabt : 1; 3004215976Sjmallett uint64_t imr_wtto : 1; 3005215976Sjmallett uint64_t itr_abt : 1; 3006215976Sjmallett uint64_t imr_abt : 1; 3007215976Sjmallett uint64_t imr_tto : 1; 3008215976Sjmallett uint64_t imsi_per : 1; 3009215976Sjmallett uint64_t imsi_tabt : 1; 3010215976Sjmallett uint64_t imsi_mabt : 1; 3011215976Sjmallett uint64_t imsc_msg : 1; 3012215976Sjmallett uint64_t itsr_abt : 1; 3013215976Sjmallett uint64_t iserr : 1; 3014215976Sjmallett uint64_t iaperr : 1; 3015215976Sjmallett uint64_t idperr : 1; 3016215976Sjmallett uint64_t ill_rwr : 1; 3017215976Sjmallett uint64_t ill_rrd : 1; 3018215976Sjmallett uint64_t irsl_int : 1; 3019215976Sjmallett uint64_t ipcnt0 : 1; 3020215976Sjmallett uint64_t reserved_18_20 : 3; 3021215976Sjmallett uint64_t iptime0 : 1; 3022215976Sjmallett uint64_t reserved_22_24 : 3; 3023215976Sjmallett uint64_t idcnt0 : 1; 3024215976Sjmallett uint64_t idcnt1 : 1; 3025215976Sjmallett uint64_t idtime0 : 1; 3026215976Sjmallett uint64_t idtime1 : 1; 3027215976Sjmallett uint64_t dma0_fi : 1; 3028215976Sjmallett uint64_t dma1_fi : 1; 3029215976Sjmallett uint64_t win_wr : 1; 3030215976Sjmallett uint64_t ill_wr : 1; 3031215976Sjmallett uint64_t ill_rd : 1; 3032215976Sjmallett uint64_t reserved_34_63 : 30; 3033215976Sjmallett#endif 3034215976Sjmallett } cn30xx; 3035215976Sjmallett struct cvmx_pci_int_enb_cn31xx 3036215976Sjmallett { 3037215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3038215976Sjmallett uint64_t reserved_34_63 : 30; 3039215976Sjmallett uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */ 3040215976Sjmallett uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */ 3041215976Sjmallett uint64_t win_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */ 3042215976Sjmallett uint64_t dma1_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */ 3043215976Sjmallett uint64_t dma0_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */ 3044215976Sjmallett uint64_t idtime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */ 3045215976Sjmallett uint64_t idtime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */ 3046215976Sjmallett uint64_t idcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */ 3047215976Sjmallett uint64_t idcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */ 3048215976Sjmallett uint64_t reserved_23_24 : 2; 3049215976Sjmallett uint64_t iptime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */ 3050215976Sjmallett uint64_t iptime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */ 3051215976Sjmallett uint64_t reserved_19_20 : 2; 3052215976Sjmallett uint64_t ipcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */ 3053215976Sjmallett uint64_t ipcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */ 3054215976Sjmallett uint64_t irsl_int : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */ 3055215976Sjmallett uint64_t ill_rrd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */ 3056215976Sjmallett uint64_t ill_rwr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */ 3057215976Sjmallett uint64_t idperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */ 3058215976Sjmallett uint64_t iaperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */ 3059215976Sjmallett uint64_t iserr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */ 3060215976Sjmallett uint64_t itsr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */ 3061215976Sjmallett uint64_t imsc_msg : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */ 3062215976Sjmallett uint64_t imsi_mabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */ 3063215976Sjmallett uint64_t imsi_tabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */ 3064215976Sjmallett uint64_t imsi_per : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */ 3065215976Sjmallett uint64_t imr_tto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */ 3066215976Sjmallett uint64_t imr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */ 3067215976Sjmallett uint64_t itr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */ 3068215976Sjmallett uint64_t imr_wtto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */ 3069215976Sjmallett uint64_t imr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */ 3070215976Sjmallett uint64_t itr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */ 3071215976Sjmallett#else 3072215976Sjmallett uint64_t itr_wabt : 1; 3073215976Sjmallett uint64_t imr_wabt : 1; 3074215976Sjmallett uint64_t imr_wtto : 1; 3075215976Sjmallett uint64_t itr_abt : 1; 3076215976Sjmallett uint64_t imr_abt : 1; 3077215976Sjmallett uint64_t imr_tto : 1; 3078215976Sjmallett uint64_t imsi_per : 1; 3079215976Sjmallett uint64_t imsi_tabt : 1; 3080215976Sjmallett uint64_t imsi_mabt : 1; 3081215976Sjmallett uint64_t imsc_msg : 1; 3082215976Sjmallett uint64_t itsr_abt : 1; 3083215976Sjmallett uint64_t iserr : 1; 3084215976Sjmallett uint64_t iaperr : 1; 3085215976Sjmallett uint64_t idperr : 1; 3086215976Sjmallett uint64_t ill_rwr : 1; 3087215976Sjmallett uint64_t ill_rrd : 1; 3088215976Sjmallett uint64_t irsl_int : 1; 3089215976Sjmallett uint64_t ipcnt0 : 1; 3090215976Sjmallett uint64_t ipcnt1 : 1; 3091215976Sjmallett uint64_t reserved_19_20 : 2; 3092215976Sjmallett uint64_t iptime0 : 1; 3093215976Sjmallett uint64_t iptime1 : 1; 3094215976Sjmallett uint64_t reserved_23_24 : 2; 3095215976Sjmallett uint64_t idcnt0 : 1; 3096215976Sjmallett uint64_t idcnt1 : 1; 3097215976Sjmallett uint64_t idtime0 : 1; 3098215976Sjmallett uint64_t idtime1 : 1; 3099215976Sjmallett uint64_t dma0_fi : 1; 3100215976Sjmallett uint64_t dma1_fi : 1; 3101215976Sjmallett uint64_t win_wr : 1; 3102215976Sjmallett uint64_t ill_wr : 1; 3103215976Sjmallett uint64_t ill_rd : 1; 3104215976Sjmallett uint64_t reserved_34_63 : 30; 3105215976Sjmallett#endif 3106215976Sjmallett } cn31xx; 3107215976Sjmallett struct cvmx_pci_int_enb_s cn38xx; 3108215976Sjmallett struct cvmx_pci_int_enb_s cn38xxp2; 3109215976Sjmallett struct cvmx_pci_int_enb_cn31xx cn50xx; 3110215976Sjmallett struct cvmx_pci_int_enb_s cn58xx; 3111215976Sjmallett struct cvmx_pci_int_enb_s cn58xxp1; 3112215976Sjmallett}; 3113215976Sjmalletttypedef union cvmx_pci_int_enb cvmx_pci_int_enb_t; 3114215976Sjmallett 3115215976Sjmallett/** 3116215976Sjmallett * cvmx_pci_int_enb2 3117215976Sjmallett * 3118215976Sjmallett * PCI_INT_ENB2 = PCI Interrupt Enable2 Register 3119215976Sjmallett * 3120215976Sjmallett * Enables interrupt bits in the PCI_INT_SUM2 register. 3121215976Sjmallett */ 3122215976Sjmallettunion cvmx_pci_int_enb2 3123215976Sjmallett{ 3124215976Sjmallett uint64_t u64; 3125215976Sjmallett struct cvmx_pci_int_enb2_s 3126215976Sjmallett { 3127215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3128215976Sjmallett uint64_t reserved_34_63 : 30; 3129215976Sjmallett uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */ 3130215976Sjmallett uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */ 3131215976Sjmallett uint64_t win_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */ 3132215976Sjmallett uint64_t dma1_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */ 3133215976Sjmallett uint64_t dma0_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */ 3134215976Sjmallett uint64_t rdtime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */ 3135215976Sjmallett uint64_t rdtime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */ 3136215976Sjmallett uint64_t rdcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */ 3137215976Sjmallett uint64_t rdcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */ 3138215976Sjmallett uint64_t rptime3 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[24] */ 3139215976Sjmallett uint64_t rptime2 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[23] */ 3140215976Sjmallett uint64_t rptime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */ 3141215976Sjmallett uint64_t rptime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */ 3142215976Sjmallett uint64_t rpcnt3 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[20] */ 3143215976Sjmallett uint64_t rpcnt2 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[19] */ 3144215976Sjmallett uint64_t rpcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */ 3145215976Sjmallett uint64_t rpcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */ 3146215976Sjmallett uint64_t rrsl_int : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */ 3147215976Sjmallett uint64_t ill_rrd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */ 3148215976Sjmallett uint64_t ill_rwr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */ 3149215976Sjmallett uint64_t rdperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */ 3150215976Sjmallett uint64_t raperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */ 3151215976Sjmallett uint64_t rserr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */ 3152215976Sjmallett uint64_t rtsr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */ 3153215976Sjmallett uint64_t rmsc_msg : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */ 3154215976Sjmallett uint64_t rmsi_mabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */ 3155215976Sjmallett uint64_t rmsi_tabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */ 3156215976Sjmallett uint64_t rmsi_per : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */ 3157215976Sjmallett uint64_t rmr_tto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */ 3158215976Sjmallett uint64_t rmr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */ 3159215976Sjmallett uint64_t rtr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */ 3160215976Sjmallett uint64_t rmr_wtto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */ 3161215976Sjmallett uint64_t rmr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */ 3162215976Sjmallett uint64_t rtr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */ 3163215976Sjmallett#else 3164215976Sjmallett uint64_t rtr_wabt : 1; 3165215976Sjmallett uint64_t rmr_wabt : 1; 3166215976Sjmallett uint64_t rmr_wtto : 1; 3167215976Sjmallett uint64_t rtr_abt : 1; 3168215976Sjmallett uint64_t rmr_abt : 1; 3169215976Sjmallett uint64_t rmr_tto : 1; 3170215976Sjmallett uint64_t rmsi_per : 1; 3171215976Sjmallett uint64_t rmsi_tabt : 1; 3172215976Sjmallett uint64_t rmsi_mabt : 1; 3173215976Sjmallett uint64_t rmsc_msg : 1; 3174215976Sjmallett uint64_t rtsr_abt : 1; 3175215976Sjmallett uint64_t rserr : 1; 3176215976Sjmallett uint64_t raperr : 1; 3177215976Sjmallett uint64_t rdperr : 1; 3178215976Sjmallett uint64_t ill_rwr : 1; 3179215976Sjmallett uint64_t ill_rrd : 1; 3180215976Sjmallett uint64_t rrsl_int : 1; 3181215976Sjmallett uint64_t rpcnt0 : 1; 3182215976Sjmallett uint64_t rpcnt1 : 1; 3183215976Sjmallett uint64_t rpcnt2 : 1; 3184215976Sjmallett uint64_t rpcnt3 : 1; 3185215976Sjmallett uint64_t rptime0 : 1; 3186215976Sjmallett uint64_t rptime1 : 1; 3187215976Sjmallett uint64_t rptime2 : 1; 3188215976Sjmallett uint64_t rptime3 : 1; 3189215976Sjmallett uint64_t rdcnt0 : 1; 3190215976Sjmallett uint64_t rdcnt1 : 1; 3191215976Sjmallett uint64_t rdtime0 : 1; 3192215976Sjmallett uint64_t rdtime1 : 1; 3193215976Sjmallett uint64_t dma0_fi : 1; 3194215976Sjmallett uint64_t dma1_fi : 1; 3195215976Sjmallett uint64_t win_wr : 1; 3196215976Sjmallett uint64_t ill_wr : 1; 3197215976Sjmallett uint64_t ill_rd : 1; 3198215976Sjmallett uint64_t reserved_34_63 : 30; 3199215976Sjmallett#endif 3200215976Sjmallett } s; 3201215976Sjmallett struct cvmx_pci_int_enb2_cn30xx 3202215976Sjmallett { 3203215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3204215976Sjmallett uint64_t reserved_34_63 : 30; 3205215976Sjmallett uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */ 3206215976Sjmallett uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */ 3207215976Sjmallett uint64_t win_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */ 3208215976Sjmallett uint64_t dma1_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */ 3209215976Sjmallett uint64_t dma0_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */ 3210215976Sjmallett uint64_t rdtime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */ 3211215976Sjmallett uint64_t rdtime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */ 3212215976Sjmallett uint64_t rdcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */ 3213215976Sjmallett uint64_t rdcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */ 3214215976Sjmallett uint64_t reserved_22_24 : 3; 3215215976Sjmallett uint64_t rptime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */ 3216215976Sjmallett uint64_t reserved_18_20 : 3; 3217215976Sjmallett uint64_t rpcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */ 3218215976Sjmallett uint64_t rrsl_int : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */ 3219215976Sjmallett uint64_t ill_rrd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */ 3220215976Sjmallett uint64_t ill_rwr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */ 3221215976Sjmallett uint64_t rdperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */ 3222215976Sjmallett uint64_t raperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */ 3223215976Sjmallett uint64_t rserr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */ 3224215976Sjmallett uint64_t rtsr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */ 3225215976Sjmallett uint64_t rmsc_msg : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */ 3226215976Sjmallett uint64_t rmsi_mabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */ 3227215976Sjmallett uint64_t rmsi_tabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */ 3228215976Sjmallett uint64_t rmsi_per : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */ 3229215976Sjmallett uint64_t rmr_tto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */ 3230215976Sjmallett uint64_t rmr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */ 3231215976Sjmallett uint64_t rtr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */ 3232215976Sjmallett uint64_t rmr_wtto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */ 3233215976Sjmallett uint64_t rmr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */ 3234215976Sjmallett uint64_t rtr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */ 3235215976Sjmallett#else 3236215976Sjmallett uint64_t rtr_wabt : 1; 3237215976Sjmallett uint64_t rmr_wabt : 1; 3238215976Sjmallett uint64_t rmr_wtto : 1; 3239215976Sjmallett uint64_t rtr_abt : 1; 3240215976Sjmallett uint64_t rmr_abt : 1; 3241215976Sjmallett uint64_t rmr_tto : 1; 3242215976Sjmallett uint64_t rmsi_per : 1; 3243215976Sjmallett uint64_t rmsi_tabt : 1; 3244215976Sjmallett uint64_t rmsi_mabt : 1; 3245215976Sjmallett uint64_t rmsc_msg : 1; 3246215976Sjmallett uint64_t rtsr_abt : 1; 3247215976Sjmallett uint64_t rserr : 1; 3248215976Sjmallett uint64_t raperr : 1; 3249215976Sjmallett uint64_t rdperr : 1; 3250215976Sjmallett uint64_t ill_rwr : 1; 3251215976Sjmallett uint64_t ill_rrd : 1; 3252215976Sjmallett uint64_t rrsl_int : 1; 3253215976Sjmallett uint64_t rpcnt0 : 1; 3254215976Sjmallett uint64_t reserved_18_20 : 3; 3255215976Sjmallett uint64_t rptime0 : 1; 3256215976Sjmallett uint64_t reserved_22_24 : 3; 3257215976Sjmallett uint64_t rdcnt0 : 1; 3258215976Sjmallett uint64_t rdcnt1 : 1; 3259215976Sjmallett uint64_t rdtime0 : 1; 3260215976Sjmallett uint64_t rdtime1 : 1; 3261215976Sjmallett uint64_t dma0_fi : 1; 3262215976Sjmallett uint64_t dma1_fi : 1; 3263215976Sjmallett uint64_t win_wr : 1; 3264215976Sjmallett uint64_t ill_wr : 1; 3265215976Sjmallett uint64_t ill_rd : 1; 3266215976Sjmallett uint64_t reserved_34_63 : 30; 3267215976Sjmallett#endif 3268215976Sjmallett } cn30xx; 3269215976Sjmallett struct cvmx_pci_int_enb2_cn31xx 3270215976Sjmallett { 3271215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3272215976Sjmallett uint64_t reserved_34_63 : 30; 3273215976Sjmallett uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */ 3274215976Sjmallett uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */ 3275215976Sjmallett uint64_t win_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */ 3276215976Sjmallett uint64_t dma1_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */ 3277215976Sjmallett uint64_t dma0_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */ 3278215976Sjmallett uint64_t rdtime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */ 3279215976Sjmallett uint64_t rdtime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */ 3280215976Sjmallett uint64_t rdcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */ 3281215976Sjmallett uint64_t rdcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */ 3282215976Sjmallett uint64_t reserved_23_24 : 2; 3283215976Sjmallett uint64_t rptime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */ 3284215976Sjmallett uint64_t rptime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */ 3285215976Sjmallett uint64_t reserved_19_20 : 2; 3286215976Sjmallett uint64_t rpcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */ 3287215976Sjmallett uint64_t rpcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */ 3288215976Sjmallett uint64_t rrsl_int : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */ 3289215976Sjmallett uint64_t ill_rrd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */ 3290215976Sjmallett uint64_t ill_rwr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */ 3291215976Sjmallett uint64_t rdperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */ 3292215976Sjmallett uint64_t raperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */ 3293215976Sjmallett uint64_t rserr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */ 3294215976Sjmallett uint64_t rtsr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */ 3295215976Sjmallett uint64_t rmsc_msg : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */ 3296215976Sjmallett uint64_t rmsi_mabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */ 3297215976Sjmallett uint64_t rmsi_tabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */ 3298215976Sjmallett uint64_t rmsi_per : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */ 3299215976Sjmallett uint64_t rmr_tto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */ 3300215976Sjmallett uint64_t rmr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */ 3301215976Sjmallett uint64_t rtr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */ 3302215976Sjmallett uint64_t rmr_wtto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */ 3303215976Sjmallett uint64_t rmr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */ 3304215976Sjmallett uint64_t rtr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */ 3305215976Sjmallett#else 3306215976Sjmallett uint64_t rtr_wabt : 1; 3307215976Sjmallett uint64_t rmr_wabt : 1; 3308215976Sjmallett uint64_t rmr_wtto : 1; 3309215976Sjmallett uint64_t rtr_abt : 1; 3310215976Sjmallett uint64_t rmr_abt : 1; 3311215976Sjmallett uint64_t rmr_tto : 1; 3312215976Sjmallett uint64_t rmsi_per : 1; 3313215976Sjmallett uint64_t rmsi_tabt : 1; 3314215976Sjmallett uint64_t rmsi_mabt : 1; 3315215976Sjmallett uint64_t rmsc_msg : 1; 3316215976Sjmallett uint64_t rtsr_abt : 1; 3317215976Sjmallett uint64_t rserr : 1; 3318215976Sjmallett uint64_t raperr : 1; 3319215976Sjmallett uint64_t rdperr : 1; 3320215976Sjmallett uint64_t ill_rwr : 1; 3321215976Sjmallett uint64_t ill_rrd : 1; 3322215976Sjmallett uint64_t rrsl_int : 1; 3323215976Sjmallett uint64_t rpcnt0 : 1; 3324215976Sjmallett uint64_t rpcnt1 : 1; 3325215976Sjmallett uint64_t reserved_19_20 : 2; 3326215976Sjmallett uint64_t rptime0 : 1; 3327215976Sjmallett uint64_t rptime1 : 1; 3328215976Sjmallett uint64_t reserved_23_24 : 2; 3329215976Sjmallett uint64_t rdcnt0 : 1; 3330215976Sjmallett uint64_t rdcnt1 : 1; 3331215976Sjmallett uint64_t rdtime0 : 1; 3332215976Sjmallett uint64_t rdtime1 : 1; 3333215976Sjmallett uint64_t dma0_fi : 1; 3334215976Sjmallett uint64_t dma1_fi : 1; 3335215976Sjmallett uint64_t win_wr : 1; 3336215976Sjmallett uint64_t ill_wr : 1; 3337215976Sjmallett uint64_t ill_rd : 1; 3338215976Sjmallett uint64_t reserved_34_63 : 30; 3339215976Sjmallett#endif 3340215976Sjmallett } cn31xx; 3341215976Sjmallett struct cvmx_pci_int_enb2_s cn38xx; 3342215976Sjmallett struct cvmx_pci_int_enb2_s cn38xxp2; 3343215976Sjmallett struct cvmx_pci_int_enb2_cn31xx cn50xx; 3344215976Sjmallett struct cvmx_pci_int_enb2_s cn58xx; 3345215976Sjmallett struct cvmx_pci_int_enb2_s cn58xxp1; 3346215976Sjmallett}; 3347215976Sjmalletttypedef union cvmx_pci_int_enb2 cvmx_pci_int_enb2_t; 3348215976Sjmallett 3349215976Sjmallett/** 3350215976Sjmallett * cvmx_pci_int_sum 3351215976Sjmallett * 3352215976Sjmallett * PCI_INT_SUM = PCI Interrupt Summary 3353215976Sjmallett * 3354215976Sjmallett * The PCI Interrupt Summary Register. 3355215976Sjmallett */ 3356215976Sjmallettunion cvmx_pci_int_sum 3357215976Sjmallett{ 3358215976Sjmallett uint64_t u64; 3359215976Sjmallett struct cvmx_pci_int_sum_s 3360215976Sjmallett { 3361215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3362215976Sjmallett uint64_t reserved_34_63 : 30; 3363215976Sjmallett uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3364215976Sjmallett when the mem area is disabled. */ 3365215976Sjmallett uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3366215976Sjmallett when the mem area is disabled. */ 3367215976Sjmallett uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3368215976Sjmallett Read-Address Register took place. */ 3369215976Sjmallett uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3370215976Sjmallett required to set the FORCE-INT bit for counter 1. */ 3371215976Sjmallett uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3372215976Sjmallett required to set the FORCE-INT bit for counter 0. */ 3373215976Sjmallett uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3374215976Sjmallett register is not 0 the DMA_CNT1 timer counts. 3375215976Sjmallett When the DMA1_CNT timer has a value greater 3376215976Sjmallett than the PCI_DMA_TIME1 register this 3377215976Sjmallett bit is set. The timer is reset when bit is 3378215976Sjmallett written with a one. */ 3379215976Sjmallett uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3380215976Sjmallett register is not 0 the DMA_CNT0 timer counts. 3381215976Sjmallett When the DMA0_CNT timer has a value greater 3382215976Sjmallett than the PCI_DMA_TIME0 register this 3383215976Sjmallett bit is set. The timer is reset when bit is 3384215976Sjmallett written with a one. */ 3385215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3386215976Sjmallett value is greater than the value 3387215976Sjmallett in the PCI_DMA_INT_LEV1 register. */ 3388215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3389215976Sjmallett value is greater than the value 3390215976Sjmallett in the PCI_DMA_INT_LEV0 register. */ 3391215976Sjmallett uint64_t ptime3 : 1; /**< When the value in the PCI_PKTS_SENT3 3392215976Sjmallett register is not 0 the Sent-3 timer counts. 3393215976Sjmallett When the Sent-3 timer has a value greater 3394215976Sjmallett than the PCI_PKTS_SENT_TIME3 register this 3395215976Sjmallett bit is set. The timer is reset when bit is 3396215976Sjmallett written with a one. */ 3397215976Sjmallett uint64_t ptime2 : 1; /**< When the value in the PCI_PKTS_SENT2 3398215976Sjmallett register is not 0 the Sent-2 timer counts. 3399215976Sjmallett When the Sent-2 timer has a value greater 3400215976Sjmallett than the PCI_PKTS_SENT_TIME2 register this 3401215976Sjmallett bit is set. The timer is reset when bit is 3402215976Sjmallett written with a one. */ 3403215976Sjmallett uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3404215976Sjmallett register is not 0 the Sent-1 timer counts. 3405215976Sjmallett When the Sent-1 timer has a value greater 3406215976Sjmallett than the PCI_PKTS_SENT_TIME1 register this 3407215976Sjmallett bit is set. The timer is reset when bit is 3408215976Sjmallett written with a one. */ 3409215976Sjmallett uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3410215976Sjmallett register is not 0 the Sent-0 timer counts. 3411215976Sjmallett When the Sent-0 timer has a value greater 3412215976Sjmallett than the PCI_PKTS_SENT_TIME0 register this 3413215976Sjmallett bit is set. The timer is reset when bit is 3414215976Sjmallett written with a one. */ 3415215976Sjmallett uint64_t pcnt3 : 1; /**< This bit indicates that PCI_PKTS_SENT3 3416215976Sjmallett value is greater than the value 3417215976Sjmallett in the PCI_PKTS_SENT_INT_LEV3 register. */ 3418215976Sjmallett uint64_t pcnt2 : 1; /**< This bit indicates that PCI_PKTS_SENT2 3419215976Sjmallett value is greater than the value 3420215976Sjmallett in the PCI_PKTS_SENT_INT_LEV2 register. */ 3421215976Sjmallett uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3422215976Sjmallett value is greater than the value 3423215976Sjmallett in the PCI_PKTS_SENT_INT_LEV1 register. */ 3424215976Sjmallett uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3425215976Sjmallett value is greater than the value 3426215976Sjmallett in the PCI_PKTS_SENT_INT_LEV0 register. */ 3427215976Sjmallett uint64_t rsl_int : 1; /**< This bit is set when the mio_pci_inta_dr wire 3428215976Sjmallett is asserted by the MIO. */ 3429215976Sjmallett uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3430215976Sjmallett uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3431215976Sjmallett uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3432215976Sjmallett uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3433215976Sjmallett uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3434215976Sjmallett uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected 3435215976Sjmallett CN58XX (as completer), has encountered an error 3436215976Sjmallett which prevents the split transaction from 3437215976Sjmallett completing. In this event, the CN58XX (as completer), 3438215976Sjmallett sends a SCM (Split Completion Message) to the 3439215976Sjmallett initiator. See: PCIX Spec v1.0a Fig 2-40. 3440215976Sjmallett [31:28]: Message Class = 2(completer error) 3441215976Sjmallett [27:20]: Message Index = 0x80 3442215976Sjmallett [18:12]: Remaining Lower Address 3443215976Sjmallett [11:0]: Remaining Byte Count */ 3444215976Sjmallett uint64_t msc_msg : 1; /**< Master Split Completion Message (SCM) Detected 3445215976Sjmallett for either a Split-Read/Write error case. 3446215976Sjmallett Set if: 3447215976Sjmallett a) A Split-Write SCM is detected with SCE=1. 3448215976Sjmallett b) A Split-Read SCM is detected (regardless 3449215976Sjmallett of SCE status). 3450215976Sjmallett The Split completion message(SCM) 3451215976Sjmallett is also latched into the PCI_SCM_REG[SCM] to 3452215976Sjmallett assist SW with error recovery. */ 3453215976Sjmallett uint64_t msi_mabt : 1; /**< PCI Master Abort on Master MSI */ 3454215976Sjmallett uint64_t msi_tabt : 1; /**< PCI Target-Abort on Master MSI */ 3455215976Sjmallett uint64_t msi_per : 1; /**< PCI Parity Error on Master MSI */ 3456215976Sjmallett uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Master-Read */ 3457215976Sjmallett uint64_t mr_abt : 1; /**< PCI Master Abort On Master-Read */ 3458215976Sjmallett uint64_t tr_abt : 1; /**< PCI Target Abort On Master-Read */ 3459215976Sjmallett uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on Master-write */ 3460215976Sjmallett uint64_t mr_wabt : 1; /**< PCI Master Abort detected on Master-write */ 3461215976Sjmallett uint64_t tr_wabt : 1; /**< PCI Target Abort detected on Master-write */ 3462215976Sjmallett#else 3463215976Sjmallett uint64_t tr_wabt : 1; 3464215976Sjmallett uint64_t mr_wabt : 1; 3465215976Sjmallett uint64_t mr_wtto : 1; 3466215976Sjmallett uint64_t tr_abt : 1; 3467215976Sjmallett uint64_t mr_abt : 1; 3468215976Sjmallett uint64_t mr_tto : 1; 3469215976Sjmallett uint64_t msi_per : 1; 3470215976Sjmallett uint64_t msi_tabt : 1; 3471215976Sjmallett uint64_t msi_mabt : 1; 3472215976Sjmallett uint64_t msc_msg : 1; 3473215976Sjmallett uint64_t tsr_abt : 1; 3474215976Sjmallett uint64_t serr : 1; 3475215976Sjmallett uint64_t aperr : 1; 3476215976Sjmallett uint64_t dperr : 1; 3477215976Sjmallett uint64_t ill_rwr : 1; 3478215976Sjmallett uint64_t ill_rrd : 1; 3479215976Sjmallett uint64_t rsl_int : 1; 3480215976Sjmallett uint64_t pcnt0 : 1; 3481215976Sjmallett uint64_t pcnt1 : 1; 3482215976Sjmallett uint64_t pcnt2 : 1; 3483215976Sjmallett uint64_t pcnt3 : 1; 3484215976Sjmallett uint64_t ptime0 : 1; 3485215976Sjmallett uint64_t ptime1 : 1; 3486215976Sjmallett uint64_t ptime2 : 1; 3487215976Sjmallett uint64_t ptime3 : 1; 3488215976Sjmallett uint64_t dcnt0 : 1; 3489215976Sjmallett uint64_t dcnt1 : 1; 3490215976Sjmallett uint64_t dtime0 : 1; 3491215976Sjmallett uint64_t dtime1 : 1; 3492215976Sjmallett uint64_t dma0_fi : 1; 3493215976Sjmallett uint64_t dma1_fi : 1; 3494215976Sjmallett uint64_t win_wr : 1; 3495215976Sjmallett uint64_t ill_wr : 1; 3496215976Sjmallett uint64_t ill_rd : 1; 3497215976Sjmallett uint64_t reserved_34_63 : 30; 3498215976Sjmallett#endif 3499215976Sjmallett } s; 3500215976Sjmallett struct cvmx_pci_int_sum_cn30xx 3501215976Sjmallett { 3502215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3503215976Sjmallett uint64_t reserved_34_63 : 30; 3504215976Sjmallett uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3505215976Sjmallett when the mem area is disabled. */ 3506215976Sjmallett uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3507215976Sjmallett when the mem area is disabled. */ 3508215976Sjmallett uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3509215976Sjmallett Read-Address Register took place. */ 3510215976Sjmallett uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3511215976Sjmallett required to set the FORCE-INT bit for counter 1. */ 3512215976Sjmallett uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3513215976Sjmallett required to set the FORCE-INT bit for counter 0. */ 3514215976Sjmallett uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3515215976Sjmallett register is not 0 the DMA_CNT1 timer counts. 3516215976Sjmallett When the DMA1_CNT timer has a value greater 3517215976Sjmallett than the PCI_DMA_TIME1 register this 3518215976Sjmallett bit is set. The timer is reset when bit is 3519215976Sjmallett written with a one. */ 3520215976Sjmallett uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3521215976Sjmallett register is not 0 the DMA_CNT0 timer counts. 3522215976Sjmallett When the DMA0_CNT timer has a value greater 3523215976Sjmallett than the PCI_DMA_TIME0 register this 3524215976Sjmallett bit is set. The timer is reset when bit is 3525215976Sjmallett written with a one. */ 3526215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3527215976Sjmallett value is greater than the value 3528215976Sjmallett in the PCI_DMA_INT_LEV1 register. */ 3529215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3530215976Sjmallett value is greater than the value 3531215976Sjmallett in the PCI_DMA_INT_LEV0 register. */ 3532215976Sjmallett uint64_t reserved_22_24 : 3; 3533215976Sjmallett uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3534215976Sjmallett register is not 0 the Sent-0 timer counts. 3535215976Sjmallett When the Sent-0 timer has a value greater 3536215976Sjmallett than the PCI_PKTS_SENT_TIME0 register this 3537215976Sjmallett bit is set. The timer is reset when bit is 3538215976Sjmallett written with a one. */ 3539215976Sjmallett uint64_t reserved_18_20 : 3; 3540215976Sjmallett uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3541215976Sjmallett value is greater than the value 3542215976Sjmallett in the PCI_PKTS_SENT_INT_LEV0 register. */ 3543215976Sjmallett uint64_t rsl_int : 1; /**< This bit is set when the mio_pci_inta_dr wire 3544215976Sjmallett is asserted by the MIO */ 3545215976Sjmallett uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3546215976Sjmallett uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3547215976Sjmallett uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3548215976Sjmallett uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3549215976Sjmallett uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3550215976Sjmallett uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected 3551215976Sjmallett N3K (as completer), has encountered an error 3552215976Sjmallett which prevents the split transaction from 3553215976Sjmallett completing. In this event, the N3K (as completer), 3554215976Sjmallett sends a SCM (Split Completion Message) to the 3555215976Sjmallett initiator. See: PCIX Spec v1.0a Fig 2-40. 3556215976Sjmallett [31:28]: Message Class = 2(completer error) 3557215976Sjmallett [27:20]: Message Index = 0x80 3558215976Sjmallett [18:12]: Remaining Lower Address 3559215976Sjmallett [11:0]: Remaining Byte Count */ 3560215976Sjmallett uint64_t msc_msg : 1; /**< Master Split Completion Message (SCM) Detected 3561215976Sjmallett for either a Split-Read/Write error case. 3562215976Sjmallett Set if: 3563215976Sjmallett a) A Split-Write SCM is detected with SCE=1. 3564215976Sjmallett b) A Split-Read SCM is detected (regardless 3565215976Sjmallett of SCE status). 3566215976Sjmallett The Split completion message(SCM) 3567215976Sjmallett is also latched into the PCI_SCM_REG[SCM] to 3568215976Sjmallett assist SW with error recovery. */ 3569215976Sjmallett uint64_t msi_mabt : 1; /**< PCI Master Abort on Master MSI */ 3570215976Sjmallett uint64_t msi_tabt : 1; /**< PCI Target-Abort on Master MSI */ 3571215976Sjmallett uint64_t msi_per : 1; /**< PCI Parity Error on Master MSI */ 3572215976Sjmallett uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Master-Read */ 3573215976Sjmallett uint64_t mr_abt : 1; /**< PCI Master Abort On Master-Read */ 3574215976Sjmallett uint64_t tr_abt : 1; /**< PCI Target Abort On Master-Read */ 3575215976Sjmallett uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on Master-write */ 3576215976Sjmallett uint64_t mr_wabt : 1; /**< PCI Master Abort detected on Master-write */ 3577215976Sjmallett uint64_t tr_wabt : 1; /**< PCI Target Abort detected on Master-write */ 3578215976Sjmallett#else 3579215976Sjmallett uint64_t tr_wabt : 1; 3580215976Sjmallett uint64_t mr_wabt : 1; 3581215976Sjmallett uint64_t mr_wtto : 1; 3582215976Sjmallett uint64_t tr_abt : 1; 3583215976Sjmallett uint64_t mr_abt : 1; 3584215976Sjmallett uint64_t mr_tto : 1; 3585215976Sjmallett uint64_t msi_per : 1; 3586215976Sjmallett uint64_t msi_tabt : 1; 3587215976Sjmallett uint64_t msi_mabt : 1; 3588215976Sjmallett uint64_t msc_msg : 1; 3589215976Sjmallett uint64_t tsr_abt : 1; 3590215976Sjmallett uint64_t serr : 1; 3591215976Sjmallett uint64_t aperr : 1; 3592215976Sjmallett uint64_t dperr : 1; 3593215976Sjmallett uint64_t ill_rwr : 1; 3594215976Sjmallett uint64_t ill_rrd : 1; 3595215976Sjmallett uint64_t rsl_int : 1; 3596215976Sjmallett uint64_t pcnt0 : 1; 3597215976Sjmallett uint64_t reserved_18_20 : 3; 3598215976Sjmallett uint64_t ptime0 : 1; 3599215976Sjmallett uint64_t reserved_22_24 : 3; 3600215976Sjmallett uint64_t dcnt0 : 1; 3601215976Sjmallett uint64_t dcnt1 : 1; 3602215976Sjmallett uint64_t dtime0 : 1; 3603215976Sjmallett uint64_t dtime1 : 1; 3604215976Sjmallett uint64_t dma0_fi : 1; 3605215976Sjmallett uint64_t dma1_fi : 1; 3606215976Sjmallett uint64_t win_wr : 1; 3607215976Sjmallett uint64_t ill_wr : 1; 3608215976Sjmallett uint64_t ill_rd : 1; 3609215976Sjmallett uint64_t reserved_34_63 : 30; 3610215976Sjmallett#endif 3611215976Sjmallett } cn30xx; 3612215976Sjmallett struct cvmx_pci_int_sum_cn31xx 3613215976Sjmallett { 3614215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3615215976Sjmallett uint64_t reserved_34_63 : 30; 3616215976Sjmallett uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3617215976Sjmallett when the mem area is disabled. */ 3618215976Sjmallett uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3619215976Sjmallett when the mem area is disabled. */ 3620215976Sjmallett uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3621215976Sjmallett Read-Address Register took place. */ 3622215976Sjmallett uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3623215976Sjmallett required to set the FORCE-INT bit for counter 1. */ 3624215976Sjmallett uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3625215976Sjmallett required to set the FORCE-INT bit for counter 0. */ 3626215976Sjmallett uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3627215976Sjmallett register is not 0 the DMA_CNT1 timer counts. 3628215976Sjmallett When the DMA1_CNT timer has a value greater 3629215976Sjmallett than the PCI_DMA_TIME1 register this 3630215976Sjmallett bit is set. The timer is reset when bit is 3631215976Sjmallett written with a one. */ 3632215976Sjmallett uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3633215976Sjmallett register is not 0 the DMA_CNT0 timer counts. 3634215976Sjmallett When the DMA0_CNT timer has a value greater 3635215976Sjmallett than the PCI_DMA_TIME0 register this 3636215976Sjmallett bit is set. The timer is reset when bit is 3637215976Sjmallett written with a one. */ 3638215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3639215976Sjmallett value is greater than the value 3640215976Sjmallett in the PCI_DMA_INT_LEV1 register. */ 3641215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3642215976Sjmallett value is greater than the value 3643215976Sjmallett in the PCI_DMA_INT_LEV0 register. */ 3644215976Sjmallett uint64_t reserved_23_24 : 2; 3645215976Sjmallett uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3646215976Sjmallett register is not 0 the Sent-1 timer counts. 3647215976Sjmallett When the Sent-1 timer has a value greater 3648215976Sjmallett than the PCI_PKTS_SENT_TIME1 register this 3649215976Sjmallett bit is set. The timer is reset when bit is 3650215976Sjmallett written with a one. */ 3651215976Sjmallett uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3652215976Sjmallett register is not 0 the Sent-0 timer counts. 3653215976Sjmallett When the Sent-0 timer has a value greater 3654215976Sjmallett than the PCI_PKTS_SENT_TIME0 register this 3655215976Sjmallett bit is set. The timer is reset when bit is 3656215976Sjmallett written with a one. */ 3657215976Sjmallett uint64_t reserved_19_20 : 2; 3658215976Sjmallett uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3659215976Sjmallett value is greater than the value 3660215976Sjmallett in the PCI_PKTS_SENT_INT_LEV1 register. */ 3661215976Sjmallett uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3662215976Sjmallett value is greater than the value 3663215976Sjmallett in the PCI_PKTS_SENT_INT_LEV0 register. */ 3664215976Sjmallett uint64_t rsl_int : 1; /**< This bit is set when the mio_pci_inta_dr wire 3665215976Sjmallett is asserted by the MIO */ 3666215976Sjmallett uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3667215976Sjmallett uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3668215976Sjmallett uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3669215976Sjmallett uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3670215976Sjmallett uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3671215976Sjmallett uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected 3672215976Sjmallett N3K (as completer), has encountered an error 3673215976Sjmallett which prevents the split transaction from 3674215976Sjmallett completing. In this event, the N3K (as completer), 3675215976Sjmallett sends a SCM (Split Completion Message) to the 3676215976Sjmallett initiator. See: PCIX Spec v1.0a Fig 2-40. 3677215976Sjmallett [31:28]: Message Class = 2(completer error) 3678215976Sjmallett [27:20]: Message Index = 0x80 3679215976Sjmallett [18:12]: Remaining Lower Address 3680215976Sjmallett [11:0]: Remaining Byte Count */ 3681215976Sjmallett uint64_t msc_msg : 1; /**< Master Split Completion Message (SCM) Detected 3682215976Sjmallett for either a Split-Read/Write error case. 3683215976Sjmallett Set if: 3684215976Sjmallett a) A Split-Write SCM is detected with SCE=1. 3685215976Sjmallett b) A Split-Read SCM is detected (regardless 3686215976Sjmallett of SCE status). 3687215976Sjmallett The Split completion message(SCM) 3688215976Sjmallett is also latched into the PCI_SCM_REG[SCM] to 3689215976Sjmallett assist SW with error recovery. */ 3690215976Sjmallett uint64_t msi_mabt : 1; /**< PCI Master Abort on Master MSI */ 3691215976Sjmallett uint64_t msi_tabt : 1; /**< PCI Target-Abort on Master MSI */ 3692215976Sjmallett uint64_t msi_per : 1; /**< PCI Parity Error on Master MSI */ 3693215976Sjmallett uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Master-Read */ 3694215976Sjmallett uint64_t mr_abt : 1; /**< PCI Master Abort On Master-Read */ 3695215976Sjmallett uint64_t tr_abt : 1; /**< PCI Target Abort On Master-Read */ 3696215976Sjmallett uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on Master-write */ 3697215976Sjmallett uint64_t mr_wabt : 1; /**< PCI Master Abort detected on Master-write */ 3698215976Sjmallett uint64_t tr_wabt : 1; /**< PCI Target Abort detected on Master-write */ 3699215976Sjmallett#else 3700215976Sjmallett uint64_t tr_wabt : 1; 3701215976Sjmallett uint64_t mr_wabt : 1; 3702215976Sjmallett uint64_t mr_wtto : 1; 3703215976Sjmallett uint64_t tr_abt : 1; 3704215976Sjmallett uint64_t mr_abt : 1; 3705215976Sjmallett uint64_t mr_tto : 1; 3706215976Sjmallett uint64_t msi_per : 1; 3707215976Sjmallett uint64_t msi_tabt : 1; 3708215976Sjmallett uint64_t msi_mabt : 1; 3709215976Sjmallett uint64_t msc_msg : 1; 3710215976Sjmallett uint64_t tsr_abt : 1; 3711215976Sjmallett uint64_t serr : 1; 3712215976Sjmallett uint64_t aperr : 1; 3713215976Sjmallett uint64_t dperr : 1; 3714215976Sjmallett uint64_t ill_rwr : 1; 3715215976Sjmallett uint64_t ill_rrd : 1; 3716215976Sjmallett uint64_t rsl_int : 1; 3717215976Sjmallett uint64_t pcnt0 : 1; 3718215976Sjmallett uint64_t pcnt1 : 1; 3719215976Sjmallett uint64_t reserved_19_20 : 2; 3720215976Sjmallett uint64_t ptime0 : 1; 3721215976Sjmallett uint64_t ptime1 : 1; 3722215976Sjmallett uint64_t reserved_23_24 : 2; 3723215976Sjmallett uint64_t dcnt0 : 1; 3724215976Sjmallett uint64_t dcnt1 : 1; 3725215976Sjmallett uint64_t dtime0 : 1; 3726215976Sjmallett uint64_t dtime1 : 1; 3727215976Sjmallett uint64_t dma0_fi : 1; 3728215976Sjmallett uint64_t dma1_fi : 1; 3729215976Sjmallett uint64_t win_wr : 1; 3730215976Sjmallett uint64_t ill_wr : 1; 3731215976Sjmallett uint64_t ill_rd : 1; 3732215976Sjmallett uint64_t reserved_34_63 : 30; 3733215976Sjmallett#endif 3734215976Sjmallett } cn31xx; 3735215976Sjmallett struct cvmx_pci_int_sum_s cn38xx; 3736215976Sjmallett struct cvmx_pci_int_sum_s cn38xxp2; 3737215976Sjmallett struct cvmx_pci_int_sum_cn31xx cn50xx; 3738215976Sjmallett struct cvmx_pci_int_sum_s cn58xx; 3739215976Sjmallett struct cvmx_pci_int_sum_s cn58xxp1; 3740215976Sjmallett}; 3741215976Sjmalletttypedef union cvmx_pci_int_sum cvmx_pci_int_sum_t; 3742215976Sjmallett 3743215976Sjmallett/** 3744215976Sjmallett * cvmx_pci_int_sum2 3745215976Sjmallett * 3746215976Sjmallett * PCI_INT_SUM2 = PCI Interrupt Summary2 Register 3747215976Sjmallett * 3748215976Sjmallett * The PCI Interrupt Summary2 Register copy used for RSL interrupts. 3749215976Sjmallett */ 3750215976Sjmallettunion cvmx_pci_int_sum2 3751215976Sjmallett{ 3752215976Sjmallett uint64_t u64; 3753215976Sjmallett struct cvmx_pci_int_sum2_s 3754215976Sjmallett { 3755215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3756215976Sjmallett uint64_t reserved_34_63 : 30; 3757215976Sjmallett uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3758215976Sjmallett when the mem area is disabled. */ 3759215976Sjmallett uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3760215976Sjmallett when the mem area is disabled. */ 3761215976Sjmallett uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3762215976Sjmallett Read-Address Register took place. */ 3763215976Sjmallett uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3764215976Sjmallett required to set the FORCE-INT bit for counter 1. */ 3765215976Sjmallett uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3766215976Sjmallett required to set the FORCE-INT bit for counter 0. */ 3767215976Sjmallett uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3768215976Sjmallett register is not 0 the DMA_CNT1 timer counts. 3769215976Sjmallett When the DMA1_CNT timer has a value greater 3770215976Sjmallett than the PCI_DMA_TIME1 register this 3771215976Sjmallett bit is set. The timer is reset when bit is 3772215976Sjmallett written with a one. */ 3773215976Sjmallett uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3774215976Sjmallett register is not 0 the DMA_CNT0 timer counts. 3775215976Sjmallett When the DMA0_CNT timer has a value greater 3776215976Sjmallett than the PCI_DMA_TIME0 register this 3777215976Sjmallett bit is set. The timer is reset when bit is 3778215976Sjmallett written with a one. */ 3779215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3780215976Sjmallett value is greater than the value 3781215976Sjmallett in the PCI_DMA_INT_LEV1 register. */ 3782215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3783215976Sjmallett value is greater than the value 3784215976Sjmallett in the PCI_DMA_INT_LEV0 register. */ 3785215976Sjmallett uint64_t ptime3 : 1; /**< When the value in the PCI_PKTS_SENT3 3786215976Sjmallett register is not 0 the Sent-3 timer counts. 3787215976Sjmallett When the Sent-3 timer has a value greater 3788215976Sjmallett than the PCI_PKTS_SENT_TIME3 register this 3789215976Sjmallett bit is set. The timer is reset when bit is 3790215976Sjmallett written with a one. */ 3791215976Sjmallett uint64_t ptime2 : 1; /**< When the value in the PCI_PKTS_SENT2 3792215976Sjmallett register is not 0 the Sent-2 timer counts. 3793215976Sjmallett When the Sent-2 timer has a value greater 3794215976Sjmallett than the PCI_PKTS_SENT_TIME2 register this 3795215976Sjmallett bit is set. The timer is reset when bit is 3796215976Sjmallett written with a one. */ 3797215976Sjmallett uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3798215976Sjmallett register is not 0 the Sent-1 timer counts. 3799215976Sjmallett When the Sent-1 timer has a value greater 3800215976Sjmallett than the PCI_PKTS_SENT_TIME1 register this 3801215976Sjmallett bit is set. The timer is reset when bit is 3802215976Sjmallett written with a one. */ 3803215976Sjmallett uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3804215976Sjmallett register is not 0 the Sent-0 timer counts. 3805215976Sjmallett When the Sent-0 timer has a value greater 3806215976Sjmallett than the PCI_PKTS_SENT_TIME0 register this 3807215976Sjmallett bit is set. The timer is reset when bit is 3808215976Sjmallett written with a one. */ 3809215976Sjmallett uint64_t pcnt3 : 1; /**< This bit indicates that PCI_PKTS_SENT3 3810215976Sjmallett value is greater than the value 3811215976Sjmallett in the PCI_PKTS_SENT_INT_LEV3 register. */ 3812215976Sjmallett uint64_t pcnt2 : 1; /**< This bit indicates that PCI_PKTS_SENT2 3813215976Sjmallett value is greater than the value 3814215976Sjmallett in the PCI_PKTS_SENT_INT_LEV2 register. */ 3815215976Sjmallett uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3816215976Sjmallett value is greater than the value 3817215976Sjmallett in the PCI_PKTS_SENT_INT_LEV1 register. */ 3818215976Sjmallett uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3819215976Sjmallett value is greater than the value 3820215976Sjmallett in the PCI_PKTS_SENT_INT_LEV0 register. */ 3821215976Sjmallett uint64_t rsl_int : 1; /**< This bit is set when the RSL Chain has 3822215976Sjmallett generated an interrupt. */ 3823215976Sjmallett uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3824215976Sjmallett uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3825215976Sjmallett uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3826215976Sjmallett uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3827215976Sjmallett uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3828215976Sjmallett uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected */ 3829215976Sjmallett uint64_t msc_msg : 1; /**< Master Split Completion Message Detected */ 3830215976Sjmallett uint64_t msi_mabt : 1; /**< PCI MSI Master Abort. */ 3831215976Sjmallett uint64_t msi_tabt : 1; /**< PCI MSI Target Abort. */ 3832215976Sjmallett uint64_t msi_per : 1; /**< PCI MSI Parity Error. */ 3833215976Sjmallett uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Read. */ 3834215976Sjmallett uint64_t mr_abt : 1; /**< PCI Master Abort On Read. */ 3835215976Sjmallett uint64_t tr_abt : 1; /**< PCI Target Abort On Read. */ 3836215976Sjmallett uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on write. */ 3837215976Sjmallett uint64_t mr_wabt : 1; /**< PCI Master Abort detected on write. */ 3838215976Sjmallett uint64_t tr_wabt : 1; /**< PCI Target Abort detected on write. */ 3839215976Sjmallett#else 3840215976Sjmallett uint64_t tr_wabt : 1; 3841215976Sjmallett uint64_t mr_wabt : 1; 3842215976Sjmallett uint64_t mr_wtto : 1; 3843215976Sjmallett uint64_t tr_abt : 1; 3844215976Sjmallett uint64_t mr_abt : 1; 3845215976Sjmallett uint64_t mr_tto : 1; 3846215976Sjmallett uint64_t msi_per : 1; 3847215976Sjmallett uint64_t msi_tabt : 1; 3848215976Sjmallett uint64_t msi_mabt : 1; 3849215976Sjmallett uint64_t msc_msg : 1; 3850215976Sjmallett uint64_t tsr_abt : 1; 3851215976Sjmallett uint64_t serr : 1; 3852215976Sjmallett uint64_t aperr : 1; 3853215976Sjmallett uint64_t dperr : 1; 3854215976Sjmallett uint64_t ill_rwr : 1; 3855215976Sjmallett uint64_t ill_rrd : 1; 3856215976Sjmallett uint64_t rsl_int : 1; 3857215976Sjmallett uint64_t pcnt0 : 1; 3858215976Sjmallett uint64_t pcnt1 : 1; 3859215976Sjmallett uint64_t pcnt2 : 1; 3860215976Sjmallett uint64_t pcnt3 : 1; 3861215976Sjmallett uint64_t ptime0 : 1; 3862215976Sjmallett uint64_t ptime1 : 1; 3863215976Sjmallett uint64_t ptime2 : 1; 3864215976Sjmallett uint64_t ptime3 : 1; 3865215976Sjmallett uint64_t dcnt0 : 1; 3866215976Sjmallett uint64_t dcnt1 : 1; 3867215976Sjmallett uint64_t dtime0 : 1; 3868215976Sjmallett uint64_t dtime1 : 1; 3869215976Sjmallett uint64_t dma0_fi : 1; 3870215976Sjmallett uint64_t dma1_fi : 1; 3871215976Sjmallett uint64_t win_wr : 1; 3872215976Sjmallett uint64_t ill_wr : 1; 3873215976Sjmallett uint64_t ill_rd : 1; 3874215976Sjmallett uint64_t reserved_34_63 : 30; 3875215976Sjmallett#endif 3876215976Sjmallett } s; 3877215976Sjmallett struct cvmx_pci_int_sum2_cn30xx 3878215976Sjmallett { 3879215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3880215976Sjmallett uint64_t reserved_34_63 : 30; 3881215976Sjmallett uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3882215976Sjmallett when the mem area is disabled. */ 3883215976Sjmallett uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3884215976Sjmallett when the mem area is disabled. */ 3885215976Sjmallett uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3886215976Sjmallett Read-Address Register took place. */ 3887215976Sjmallett uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3888215976Sjmallett required to set the FORCE-INT bit for counter 1. */ 3889215976Sjmallett uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3890215976Sjmallett required to set the FORCE-INT bit for counter 0. */ 3891215976Sjmallett uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3892215976Sjmallett register is not 0 the DMA_CNT1 timer counts. 3893215976Sjmallett When the DMA1_CNT timer has a value greater 3894215976Sjmallett than the PCI_DMA_TIME1 register this 3895215976Sjmallett bit is set. The timer is reset when bit is 3896215976Sjmallett written with a one. */ 3897215976Sjmallett uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3898215976Sjmallett register is not 0 the DMA_CNT0 timer counts. 3899215976Sjmallett When the DMA0_CNT timer has a value greater 3900215976Sjmallett than the PCI_DMA_TIME0 register this 3901215976Sjmallett bit is set. The timer is reset when bit is 3902215976Sjmallett written with a one. */ 3903215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3904215976Sjmallett value is greater than the value 3905215976Sjmallett in the PCI_DMA_INT_LEV1 register. */ 3906215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3907215976Sjmallett value is greater than the value 3908215976Sjmallett in the PCI_DMA_INT_LEV0 register. */ 3909215976Sjmallett uint64_t reserved_22_24 : 3; 3910215976Sjmallett uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3911215976Sjmallett register is not 0 the Sent-0 timer counts. 3912215976Sjmallett When the Sent-0 timer has a value greater 3913215976Sjmallett than the PCI_PKTS_SENT_TIME0 register this 3914215976Sjmallett bit is set. The timer is reset when bit is 3915215976Sjmallett written with a one. */ 3916215976Sjmallett uint64_t reserved_18_20 : 3; 3917215976Sjmallett uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3918215976Sjmallett value is greater than the value 3919215976Sjmallett in the PCI_PKTS_SENT_INT_LEV0 register. */ 3920215976Sjmallett uint64_t rsl_int : 1; /**< This bit is set when the RSL Chain has 3921215976Sjmallett generated an interrupt. */ 3922215976Sjmallett uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3923215976Sjmallett uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3924215976Sjmallett uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3925215976Sjmallett uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3926215976Sjmallett uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3927215976Sjmallett uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected */ 3928215976Sjmallett uint64_t msc_msg : 1; /**< Master Split Completion Message Detected */ 3929215976Sjmallett uint64_t msi_mabt : 1; /**< PCI MSI Master Abort. */ 3930215976Sjmallett uint64_t msi_tabt : 1; /**< PCI MSI Target Abort. */ 3931215976Sjmallett uint64_t msi_per : 1; /**< PCI MSI Parity Error. */ 3932215976Sjmallett uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Read. */ 3933215976Sjmallett uint64_t mr_abt : 1; /**< PCI Master Abort On Read. */ 3934215976Sjmallett uint64_t tr_abt : 1; /**< PCI Target Abort On Read. */ 3935215976Sjmallett uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on write. */ 3936215976Sjmallett uint64_t mr_wabt : 1; /**< PCI Master Abort detected on write. */ 3937215976Sjmallett uint64_t tr_wabt : 1; /**< PCI Target Abort detected on write. */ 3938215976Sjmallett#else 3939215976Sjmallett uint64_t tr_wabt : 1; 3940215976Sjmallett uint64_t mr_wabt : 1; 3941215976Sjmallett uint64_t mr_wtto : 1; 3942215976Sjmallett uint64_t tr_abt : 1; 3943215976Sjmallett uint64_t mr_abt : 1; 3944215976Sjmallett uint64_t mr_tto : 1; 3945215976Sjmallett uint64_t msi_per : 1; 3946215976Sjmallett uint64_t msi_tabt : 1; 3947215976Sjmallett uint64_t msi_mabt : 1; 3948215976Sjmallett uint64_t msc_msg : 1; 3949215976Sjmallett uint64_t tsr_abt : 1; 3950215976Sjmallett uint64_t serr : 1; 3951215976Sjmallett uint64_t aperr : 1; 3952215976Sjmallett uint64_t dperr : 1; 3953215976Sjmallett uint64_t ill_rwr : 1; 3954215976Sjmallett uint64_t ill_rrd : 1; 3955215976Sjmallett uint64_t rsl_int : 1; 3956215976Sjmallett uint64_t pcnt0 : 1; 3957215976Sjmallett uint64_t reserved_18_20 : 3; 3958215976Sjmallett uint64_t ptime0 : 1; 3959215976Sjmallett uint64_t reserved_22_24 : 3; 3960215976Sjmallett uint64_t dcnt0 : 1; 3961215976Sjmallett uint64_t dcnt1 : 1; 3962215976Sjmallett uint64_t dtime0 : 1; 3963215976Sjmallett uint64_t dtime1 : 1; 3964215976Sjmallett uint64_t dma0_fi : 1; 3965215976Sjmallett uint64_t dma1_fi : 1; 3966215976Sjmallett uint64_t win_wr : 1; 3967215976Sjmallett uint64_t ill_wr : 1; 3968215976Sjmallett uint64_t ill_rd : 1; 3969215976Sjmallett uint64_t reserved_34_63 : 30; 3970215976Sjmallett#endif 3971215976Sjmallett } cn30xx; 3972215976Sjmallett struct cvmx_pci_int_sum2_cn31xx 3973215976Sjmallett { 3974215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3975215976Sjmallett uint64_t reserved_34_63 : 30; 3976215976Sjmallett uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3977215976Sjmallett when the mem area is disabled. */ 3978215976Sjmallett uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3979215976Sjmallett when the mem area is disabled. */ 3980215976Sjmallett uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3981215976Sjmallett Read-Address Register took place. */ 3982215976Sjmallett uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3983215976Sjmallett required to set the FORCE-INT bit for counter 1. */ 3984215976Sjmallett uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3985215976Sjmallett required to set the FORCE-INT bit for counter 0. */ 3986215976Sjmallett uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3987215976Sjmallett register is not 0 the DMA_CNT1 timer counts. 3988215976Sjmallett When the DMA1_CNT timer has a value greater 3989215976Sjmallett than the PCI_DMA_TIME1 register this 3990215976Sjmallett bit is set. The timer is reset when bit is 3991215976Sjmallett written with a one. */ 3992215976Sjmallett uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3993215976Sjmallett register is not 0 the DMA_CNT0 timer counts. 3994215976Sjmallett When the DMA0_CNT timer has a value greater 3995215976Sjmallett than the PCI_DMA_TIME0 register this 3996215976Sjmallett bit is set. The timer is reset when bit is 3997215976Sjmallett written with a one. */ 3998215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3999215976Sjmallett value is greater than the value 4000215976Sjmallett in the PCI_DMA_INT_LEV1 register. */ 4001215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 4002215976Sjmallett value is greater than the value 4003215976Sjmallett in the PCI_DMA_INT_LEV0 register. */ 4004215976Sjmallett uint64_t reserved_23_24 : 2; 4005215976Sjmallett uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 4006215976Sjmallett register is not 0 the Sent-1 timer counts. 4007215976Sjmallett When the Sent-1 timer has a value greater 4008215976Sjmallett than the PCI_PKTS_SENT_TIME1 register this 4009215976Sjmallett bit is set. The timer is reset when bit is 4010215976Sjmallett written with a one. */ 4011215976Sjmallett uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 4012215976Sjmallett register is not 0 the Sent-0 timer counts. 4013215976Sjmallett When the Sent-0 timer has a value greater 4014215976Sjmallett than the PCI_PKTS_SENT_TIME0 register this 4015215976Sjmallett bit is set. The timer is reset when bit is 4016215976Sjmallett written with a one. */ 4017215976Sjmallett uint64_t reserved_19_20 : 2; 4018215976Sjmallett uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 4019215976Sjmallett value is greater than the value 4020215976Sjmallett in the PCI_PKTS_SENT_INT_LEV1 register. */ 4021215976Sjmallett uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 4022215976Sjmallett value is greater than the value 4023215976Sjmallett in the PCI_PKTS_SENT_INT_LEV0 register. */ 4024215976Sjmallett uint64_t rsl_int : 1; /**< This bit is set when the RSL Chain has 4025215976Sjmallett generated an interrupt. */ 4026215976Sjmallett uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 4027215976Sjmallett uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 4028215976Sjmallett uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 4029215976Sjmallett uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 4030215976Sjmallett uint64_t serr : 1; /**< SERR# detected by PCX Core */ 4031215976Sjmallett uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected */ 4032215976Sjmallett uint64_t msc_msg : 1; /**< Master Split Completion Message Detected */ 4033215976Sjmallett uint64_t msi_mabt : 1; /**< PCI MSI Master Abort. */ 4034215976Sjmallett uint64_t msi_tabt : 1; /**< PCI MSI Target Abort. */ 4035215976Sjmallett uint64_t msi_per : 1; /**< PCI MSI Parity Error. */ 4036215976Sjmallett uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Read. */ 4037215976Sjmallett uint64_t mr_abt : 1; /**< PCI Master Abort On Read. */ 4038215976Sjmallett uint64_t tr_abt : 1; /**< PCI Target Abort On Read. */ 4039215976Sjmallett uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on write. */ 4040215976Sjmallett uint64_t mr_wabt : 1; /**< PCI Master Abort detected on write. */ 4041215976Sjmallett uint64_t tr_wabt : 1; /**< PCI Target Abort detected on write. */ 4042215976Sjmallett#else 4043215976Sjmallett uint64_t tr_wabt : 1; 4044215976Sjmallett uint64_t mr_wabt : 1; 4045215976Sjmallett uint64_t mr_wtto : 1; 4046215976Sjmallett uint64_t tr_abt : 1; 4047215976Sjmallett uint64_t mr_abt : 1; 4048215976Sjmallett uint64_t mr_tto : 1; 4049215976Sjmallett uint64_t msi_per : 1; 4050215976Sjmallett uint64_t msi_tabt : 1; 4051215976Sjmallett uint64_t msi_mabt : 1; 4052215976Sjmallett uint64_t msc_msg : 1; 4053215976Sjmallett uint64_t tsr_abt : 1; 4054215976Sjmallett uint64_t serr : 1; 4055215976Sjmallett uint64_t aperr : 1; 4056215976Sjmallett uint64_t dperr : 1; 4057215976Sjmallett uint64_t ill_rwr : 1; 4058215976Sjmallett uint64_t ill_rrd : 1; 4059215976Sjmallett uint64_t rsl_int : 1; 4060215976Sjmallett uint64_t pcnt0 : 1; 4061215976Sjmallett uint64_t pcnt1 : 1; 4062215976Sjmallett uint64_t reserved_19_20 : 2; 4063215976Sjmallett uint64_t ptime0 : 1; 4064215976Sjmallett uint64_t ptime1 : 1; 4065215976Sjmallett uint64_t reserved_23_24 : 2; 4066215976Sjmallett uint64_t dcnt0 : 1; 4067215976Sjmallett uint64_t dcnt1 : 1; 4068215976Sjmallett uint64_t dtime0 : 1; 4069215976Sjmallett uint64_t dtime1 : 1; 4070215976Sjmallett uint64_t dma0_fi : 1; 4071215976Sjmallett uint64_t dma1_fi : 1; 4072215976Sjmallett uint64_t win_wr : 1; 4073215976Sjmallett uint64_t ill_wr : 1; 4074215976Sjmallett uint64_t ill_rd : 1; 4075215976Sjmallett uint64_t reserved_34_63 : 30; 4076215976Sjmallett#endif 4077215976Sjmallett } cn31xx; 4078215976Sjmallett struct cvmx_pci_int_sum2_s cn38xx; 4079215976Sjmallett struct cvmx_pci_int_sum2_s cn38xxp2; 4080215976Sjmallett struct cvmx_pci_int_sum2_cn31xx cn50xx; 4081215976Sjmallett struct cvmx_pci_int_sum2_s cn58xx; 4082215976Sjmallett struct cvmx_pci_int_sum2_s cn58xxp1; 4083215976Sjmallett}; 4084215976Sjmalletttypedef union cvmx_pci_int_sum2 cvmx_pci_int_sum2_t; 4085215976Sjmallett 4086215976Sjmallett/** 4087215976Sjmallett * cvmx_pci_msi_rcv 4088215976Sjmallett * 4089215976Sjmallett * PCI_MSI_RCV = PCI's MSI Received Vector Register 4090215976Sjmallett * 4091215976Sjmallett * A bit is set in this register relative to the vector received during a MSI. The value in this 4092215976Sjmallett * register is acted upon when the least-significant-byte of this register is written. 4093215976Sjmallett */ 4094215976Sjmallettunion cvmx_pci_msi_rcv 4095215976Sjmallett{ 4096215976Sjmallett uint32_t u32; 4097215976Sjmallett struct cvmx_pci_msi_rcv_s 4098215976Sjmallett { 4099215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4100215976Sjmallett uint32_t reserved_6_31 : 26; 4101215976Sjmallett uint32_t intr : 6; /**< When an MSI is received on the PCI the bit selected 4102215976Sjmallett by data [5:0] will be set in this register. To 4103215976Sjmallett clear this bit a write must take place to the 4104215976Sjmallett NPI_MSI_RCV register where any bit set to 1 is 4105215976Sjmallett cleared. Reading this address will return an 4106215976Sjmallett unpredicatable value. */ 4107215976Sjmallett#else 4108215976Sjmallett uint32_t intr : 6; 4109215976Sjmallett uint32_t reserved_6_31 : 26; 4110215976Sjmallett#endif 4111215976Sjmallett } s; 4112215976Sjmallett struct cvmx_pci_msi_rcv_s cn30xx; 4113215976Sjmallett struct cvmx_pci_msi_rcv_s cn31xx; 4114215976Sjmallett struct cvmx_pci_msi_rcv_s cn38xx; 4115215976Sjmallett struct cvmx_pci_msi_rcv_s cn38xxp2; 4116215976Sjmallett struct cvmx_pci_msi_rcv_s cn50xx; 4117215976Sjmallett struct cvmx_pci_msi_rcv_s cn58xx; 4118215976Sjmallett struct cvmx_pci_msi_rcv_s cn58xxp1; 4119215976Sjmallett}; 4120215976Sjmalletttypedef union cvmx_pci_msi_rcv cvmx_pci_msi_rcv_t; 4121215976Sjmallett 4122215976Sjmallett/** 4123215976Sjmallett * cvmx_pci_pkt_credits# 4124215976Sjmallett * 4125215976Sjmallett * PCI_PKT_CREDITS0 = PCI Packet Credits For Output 0 4126215976Sjmallett * 4127215976Sjmallett * Used to decrease the number of packets to be processed by the host from Output-0 and return 4128215976Sjmallett * buffer/info pointer pairs to OCTEON Output-0. The value in this register is acted upon when the 4129215976Sjmallett * least-significant-byte of this register is written. 4130215976Sjmallett */ 4131215976Sjmallettunion cvmx_pci_pkt_creditsx 4132215976Sjmallett{ 4133215976Sjmallett uint32_t u32; 4134215976Sjmallett struct cvmx_pci_pkt_creditsx_s 4135215976Sjmallett { 4136215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4137215976Sjmallett uint32_t pkt_cnt : 16; /**< The value written to this field will be 4138215976Sjmallett subtracted from PCI_PKTS_SENT0[PKT_CNT]. */ 4139215976Sjmallett uint32_t ptr_cnt : 16; /**< This field value is added to the 4140215976Sjmallett NPI's internal Buffer/Info Pointer Pair count. */ 4141215976Sjmallett#else 4142215976Sjmallett uint32_t ptr_cnt : 16; 4143215976Sjmallett uint32_t pkt_cnt : 16; 4144215976Sjmallett#endif 4145215976Sjmallett } s; 4146215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn30xx; 4147215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn31xx; 4148215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn38xx; 4149215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn38xxp2; 4150215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn50xx; 4151215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn58xx; 4152215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn58xxp1; 4153215976Sjmallett}; 4154215976Sjmalletttypedef union cvmx_pci_pkt_creditsx cvmx_pci_pkt_creditsx_t; 4155215976Sjmallett 4156215976Sjmallett/** 4157215976Sjmallett * cvmx_pci_pkts_sent# 4158215976Sjmallett * 4159215976Sjmallett * PCI_PKTS_SENT0 = PCI Packets Sent 0 4160215976Sjmallett * 4161215976Sjmallett * Number of packets sent to the host memory from PCI Output 0 4162215976Sjmallett */ 4163215976Sjmallettunion cvmx_pci_pkts_sentx 4164215976Sjmallett{ 4165215976Sjmallett uint32_t u32; 4166215976Sjmallett struct cvmx_pci_pkts_sentx_s 4167215976Sjmallett { 4168215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4169215976Sjmallett uint32_t pkt_cnt : 32; /**< Each time a packet is written to the memory via 4170215976Sjmallett PCI from PCI Output 0, this counter is 4171215976Sjmallett incremented by 1 or the byte count of the packet 4172215976Sjmallett as set in NPI_OUTPUT_CONTROL[P0_BMODE]. */ 4173215976Sjmallett#else 4174215976Sjmallett uint32_t pkt_cnt : 32; 4175215976Sjmallett#endif 4176215976Sjmallett } s; 4177215976Sjmallett struct cvmx_pci_pkts_sentx_s cn30xx; 4178215976Sjmallett struct cvmx_pci_pkts_sentx_s cn31xx; 4179215976Sjmallett struct cvmx_pci_pkts_sentx_s cn38xx; 4180215976Sjmallett struct cvmx_pci_pkts_sentx_s cn38xxp2; 4181215976Sjmallett struct cvmx_pci_pkts_sentx_s cn50xx; 4182215976Sjmallett struct cvmx_pci_pkts_sentx_s cn58xx; 4183215976Sjmallett struct cvmx_pci_pkts_sentx_s cn58xxp1; 4184215976Sjmallett}; 4185215976Sjmalletttypedef union cvmx_pci_pkts_sentx cvmx_pci_pkts_sentx_t; 4186215976Sjmallett 4187215976Sjmallett/** 4188215976Sjmallett * cvmx_pci_pkts_sent_int_lev# 4189215976Sjmallett * 4190215976Sjmallett * PCI_PKTS_SENT_INT_LEV0 = PCI Packets Sent Interrupt Level For Output 0 4191215976Sjmallett * 4192215976Sjmallett * Interrupt when number of packets sent is equal to or greater than the register value. 4193215976Sjmallett */ 4194215976Sjmallettunion cvmx_pci_pkts_sent_int_levx 4195215976Sjmallett{ 4196215976Sjmallett uint32_t u32; 4197215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s 4198215976Sjmallett { 4199215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4200215976Sjmallett uint32_t pkt_cnt : 32; /**< When corresponding port's PCI_PKTS_SENT0 value 4201215976Sjmallett exceeds the value in this register, PCNT0 of the 4202215976Sjmallett PCI_INT_SUM and PCI_INT_SUM2 will be set. */ 4203215976Sjmallett#else 4204215976Sjmallett uint32_t pkt_cnt : 32; 4205215976Sjmallett#endif 4206215976Sjmallett } s; 4207215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn30xx; 4208215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn31xx; 4209215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn38xx; 4210215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2; 4211215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn50xx; 4212215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn58xx; 4213215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1; 4214215976Sjmallett}; 4215215976Sjmalletttypedef union cvmx_pci_pkts_sent_int_levx cvmx_pci_pkts_sent_int_levx_t; 4216215976Sjmallett 4217215976Sjmallett/** 4218215976Sjmallett * cvmx_pci_pkts_sent_time# 4219215976Sjmallett * 4220215976Sjmallett * PCI_PKTS_SENT_TIME0 = PCI Packets Sent Timer For Output-0 4221215976Sjmallett * 4222215976Sjmallett * Time to wait from packet being sent to host from Output-0 before issuing an interrupt. 4223215976Sjmallett */ 4224215976Sjmallettunion cvmx_pci_pkts_sent_timex 4225215976Sjmallett{ 4226215976Sjmallett uint32_t u32; 4227215976Sjmallett struct cvmx_pci_pkts_sent_timex_s 4228215976Sjmallett { 4229215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4230215976Sjmallett uint32_t pkt_time : 32; /**< Number of PCI clock cycle to wait before 4231215976Sjmallett issuing an interrupt to the host when a 4232215976Sjmallett packet from this port has been sent to the 4233215976Sjmallett host. The timer is reset when the 4234215976Sjmallett PCI_INT_SUM[21] register is cleared. */ 4235215976Sjmallett#else 4236215976Sjmallett uint32_t pkt_time : 32; 4237215976Sjmallett#endif 4238215976Sjmallett } s; 4239215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn30xx; 4240215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn31xx; 4241215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn38xx; 4242215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn38xxp2; 4243215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn50xx; 4244215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn58xx; 4245215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn58xxp1; 4246215976Sjmallett}; 4247215976Sjmalletttypedef union cvmx_pci_pkts_sent_timex cvmx_pci_pkts_sent_timex_t; 4248215976Sjmallett 4249215976Sjmallett/** 4250215976Sjmallett * cvmx_pci_read_cmd_6 4251215976Sjmallett * 4252215976Sjmallett * PCI_READ_CMD_6 = PCI Read Command 6 Register 4253215976Sjmallett * 4254215976Sjmallett * Contains control inforamtion related to a received PCI Command 6. 4255215976Sjmallett */ 4256215976Sjmallettunion cvmx_pci_read_cmd_6 4257215976Sjmallett{ 4258215976Sjmallett uint32_t u32; 4259215976Sjmallett struct cvmx_pci_read_cmd_6_s 4260215976Sjmallett { 4261215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4262215976Sjmallett uint32_t reserved_9_31 : 23; 4263215976Sjmallett uint32_t min_data : 6; /**< The number of words to have buffered in the PNI 4264215976Sjmallett before informing the PCIX-Core that we have 4265215976Sjmallett read data available for the outstanding Delayed 4266215976Sjmallett read. 0 is treated as a 64. 4267215976Sjmallett For reads to the expansion this value is not used. */ 4268215976Sjmallett uint32_t prefetch : 3; /**< Control the amount of data to be preteched when 4269215976Sjmallett this type of bhmstREAD command is received. 4270215976Sjmallett 0 = 1 32/64 bit word. 4271215976Sjmallett 1 = From address to end of 128B block. 4272215976Sjmallett 2 = From address to end of 128B block plus 128B. 4273215976Sjmallett 3 = From address to end of 128B block plus 256B. 4274215976Sjmallett 4 = From address to end of 128B block plus 384B. 4275215976Sjmallett For reads to the expansion this value is not used. */ 4276215976Sjmallett#else 4277215976Sjmallett uint32_t prefetch : 3; 4278215976Sjmallett uint32_t min_data : 6; 4279215976Sjmallett uint32_t reserved_9_31 : 23; 4280215976Sjmallett#endif 4281215976Sjmallett } s; 4282215976Sjmallett struct cvmx_pci_read_cmd_6_s cn30xx; 4283215976Sjmallett struct cvmx_pci_read_cmd_6_s cn31xx; 4284215976Sjmallett struct cvmx_pci_read_cmd_6_s cn38xx; 4285215976Sjmallett struct cvmx_pci_read_cmd_6_s cn38xxp2; 4286215976Sjmallett struct cvmx_pci_read_cmd_6_s cn50xx; 4287215976Sjmallett struct cvmx_pci_read_cmd_6_s cn58xx; 4288215976Sjmallett struct cvmx_pci_read_cmd_6_s cn58xxp1; 4289215976Sjmallett}; 4290215976Sjmalletttypedef union cvmx_pci_read_cmd_6 cvmx_pci_read_cmd_6_t; 4291215976Sjmallett 4292215976Sjmallett/** 4293215976Sjmallett * cvmx_pci_read_cmd_c 4294215976Sjmallett * 4295215976Sjmallett * PCI_READ_CMD_C = PCI Read Command C Register 4296215976Sjmallett * 4297215976Sjmallett * Contains control inforamtion related to a received PCI Command C. 4298215976Sjmallett */ 4299215976Sjmallettunion cvmx_pci_read_cmd_c 4300215976Sjmallett{ 4301215976Sjmallett uint32_t u32; 4302215976Sjmallett struct cvmx_pci_read_cmd_c_s 4303215976Sjmallett { 4304215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4305215976Sjmallett uint32_t reserved_9_31 : 23; 4306215976Sjmallett uint32_t min_data : 6; /**< The number of words to have buffered in the PNI 4307215976Sjmallett before informing the PCIX-Core that we have 4308215976Sjmallett read data available for the outstanding Delayed 4309215976Sjmallett read. 0 is treated as a 64. 4310215976Sjmallett For reads to the expansion this value is not used. */ 4311215976Sjmallett uint32_t prefetch : 3; /**< Control the amount of data to be preteched when 4312215976Sjmallett this type of READ command is received. 4313215976Sjmallett 0 = 1 32/64 bit word. 4314215976Sjmallett 1 = From address to end of 128B block. 4315215976Sjmallett 2 = From address to end of 128B block plus 128B. 4316215976Sjmallett 3 = From address to end of 128B block plus 256B. 4317215976Sjmallett 4 = From address to end of 128B block plus 384B. 4318215976Sjmallett For reads to the expansion this value is not used. */ 4319215976Sjmallett#else 4320215976Sjmallett uint32_t prefetch : 3; 4321215976Sjmallett uint32_t min_data : 6; 4322215976Sjmallett uint32_t reserved_9_31 : 23; 4323215976Sjmallett#endif 4324215976Sjmallett } s; 4325215976Sjmallett struct cvmx_pci_read_cmd_c_s cn30xx; 4326215976Sjmallett struct cvmx_pci_read_cmd_c_s cn31xx; 4327215976Sjmallett struct cvmx_pci_read_cmd_c_s cn38xx; 4328215976Sjmallett struct cvmx_pci_read_cmd_c_s cn38xxp2; 4329215976Sjmallett struct cvmx_pci_read_cmd_c_s cn50xx; 4330215976Sjmallett struct cvmx_pci_read_cmd_c_s cn58xx; 4331215976Sjmallett struct cvmx_pci_read_cmd_c_s cn58xxp1; 4332215976Sjmallett}; 4333215976Sjmalletttypedef union cvmx_pci_read_cmd_c cvmx_pci_read_cmd_c_t; 4334215976Sjmallett 4335215976Sjmallett/** 4336215976Sjmallett * cvmx_pci_read_cmd_e 4337215976Sjmallett * 4338215976Sjmallett * PCI_READ_CMD_E = PCI Read Command E Register 4339215976Sjmallett * 4340215976Sjmallett * Contains control inforamtion related to a received PCI Command 6. 4341215976Sjmallett */ 4342215976Sjmallettunion cvmx_pci_read_cmd_e 4343215976Sjmallett{ 4344215976Sjmallett uint32_t u32; 4345215976Sjmallett struct cvmx_pci_read_cmd_e_s 4346215976Sjmallett { 4347215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4348215976Sjmallett uint32_t reserved_9_31 : 23; 4349215976Sjmallett uint32_t min_data : 6; /**< The number of words to have buffered in the PNI 4350215976Sjmallett before informaing the PCIX-Core that we have 4351215976Sjmallett read data available for the outstanding Delayed 4352215976Sjmallett read. 0 is treated as a 64. 4353215976Sjmallett For reads to the expansion this value is not used. */ 4354215976Sjmallett uint32_t prefetch : 3; /**< Control the amount of data to be preteched when 4355215976Sjmallett this type of READ command is received. 4356215976Sjmallett 0 = 1 32/64 bit word. 4357215976Sjmallett 1 = From address to end of 128B block. 4358215976Sjmallett 2 = From address to end of 128B block plus 128B. 4359215976Sjmallett 3 = From address to end of 128B block plus 256B. 4360215976Sjmallett 4 = From address to end of 128B block plus 384B. 4361215976Sjmallett For reads to the expansion this value is not used. */ 4362215976Sjmallett#else 4363215976Sjmallett uint32_t prefetch : 3; 4364215976Sjmallett uint32_t min_data : 6; 4365215976Sjmallett uint32_t reserved_9_31 : 23; 4366215976Sjmallett#endif 4367215976Sjmallett } s; 4368215976Sjmallett struct cvmx_pci_read_cmd_e_s cn30xx; 4369215976Sjmallett struct cvmx_pci_read_cmd_e_s cn31xx; 4370215976Sjmallett struct cvmx_pci_read_cmd_e_s cn38xx; 4371215976Sjmallett struct cvmx_pci_read_cmd_e_s cn38xxp2; 4372215976Sjmallett struct cvmx_pci_read_cmd_e_s cn50xx; 4373215976Sjmallett struct cvmx_pci_read_cmd_e_s cn58xx; 4374215976Sjmallett struct cvmx_pci_read_cmd_e_s cn58xxp1; 4375215976Sjmallett}; 4376215976Sjmalletttypedef union cvmx_pci_read_cmd_e cvmx_pci_read_cmd_e_t; 4377215976Sjmallett 4378215976Sjmallett/** 4379215976Sjmallett * cvmx_pci_read_timeout 4380215976Sjmallett * 4381215976Sjmallett * PCI_READ_TIMEOUT = PCI Read Timeour Register 4382215976Sjmallett * 4383215976Sjmallett * The address to start reading Instructions from for Input-3. 4384215976Sjmallett */ 4385215976Sjmallettunion cvmx_pci_read_timeout 4386215976Sjmallett{ 4387215976Sjmallett uint64_t u64; 4388215976Sjmallett struct cvmx_pci_read_timeout_s 4389215976Sjmallett { 4390215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4391215976Sjmallett uint64_t reserved_32_63 : 32; 4392215976Sjmallett uint64_t enb : 1; /**< Enable the use of the Timeout function. */ 4393215976Sjmallett uint64_t cnt : 31; /**< The number of eclk cycles to wait after issuing 4394215976Sjmallett a read request to the PNI before setting a 4395215976Sjmallett timeout and not expecting the data to return. 4396215976Sjmallett This is considered a fatal condition by the NPI. */ 4397215976Sjmallett#else 4398215976Sjmallett uint64_t cnt : 31; 4399215976Sjmallett uint64_t enb : 1; 4400215976Sjmallett uint64_t reserved_32_63 : 32; 4401215976Sjmallett#endif 4402215976Sjmallett } s; 4403215976Sjmallett struct cvmx_pci_read_timeout_s cn30xx; 4404215976Sjmallett struct cvmx_pci_read_timeout_s cn31xx; 4405215976Sjmallett struct cvmx_pci_read_timeout_s cn38xx; 4406215976Sjmallett struct cvmx_pci_read_timeout_s cn38xxp2; 4407215976Sjmallett struct cvmx_pci_read_timeout_s cn50xx; 4408215976Sjmallett struct cvmx_pci_read_timeout_s cn58xx; 4409215976Sjmallett struct cvmx_pci_read_timeout_s cn58xxp1; 4410215976Sjmallett}; 4411215976Sjmalletttypedef union cvmx_pci_read_timeout cvmx_pci_read_timeout_t; 4412215976Sjmallett 4413215976Sjmallett/** 4414215976Sjmallett * cvmx_pci_scm_reg 4415215976Sjmallett * 4416215976Sjmallett * PCI_SCM_REG = PCI Master Split Completion Message Register 4417215976Sjmallett * 4418215976Sjmallett * This register contains the Master Split Completion Message(SCM) generated when a master split 4419215976Sjmallett * transaction is aborted. 4420215976Sjmallett */ 4421215976Sjmallettunion cvmx_pci_scm_reg 4422215976Sjmallett{ 4423215976Sjmallett uint64_t u64; 4424215976Sjmallett struct cvmx_pci_scm_reg_s 4425215976Sjmallett { 4426215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4427215976Sjmallett uint64_t reserved_32_63 : 32; 4428215976Sjmallett uint64_t scm : 32; /**< Contains the Split Completion Message (SCM) 4429215976Sjmallett driven when a master-split transaction is aborted. 4430215976Sjmallett [31:28]: Message Class 4431215976Sjmallett [27:20]: Message Index 4432215976Sjmallett [19]: Reserved 4433215976Sjmallett [18:12]: Remaining Lower Address 4434215976Sjmallett [11:8]: Upper Remaining Byte Count 4435215976Sjmallett [7:0]: Lower Remaining Byte Count 4436215976Sjmallett Refer to the PCIX1.0a specification, Fig 2-40 4437215976Sjmallett for additional details for the split completion 4438215976Sjmallett message format. */ 4439215976Sjmallett#else 4440215976Sjmallett uint64_t scm : 32; 4441215976Sjmallett uint64_t reserved_32_63 : 32; 4442215976Sjmallett#endif 4443215976Sjmallett } s; 4444215976Sjmallett struct cvmx_pci_scm_reg_s cn30xx; 4445215976Sjmallett struct cvmx_pci_scm_reg_s cn31xx; 4446215976Sjmallett struct cvmx_pci_scm_reg_s cn38xx; 4447215976Sjmallett struct cvmx_pci_scm_reg_s cn38xxp2; 4448215976Sjmallett struct cvmx_pci_scm_reg_s cn50xx; 4449215976Sjmallett struct cvmx_pci_scm_reg_s cn58xx; 4450215976Sjmallett struct cvmx_pci_scm_reg_s cn58xxp1; 4451215976Sjmallett}; 4452215976Sjmalletttypedef union cvmx_pci_scm_reg cvmx_pci_scm_reg_t; 4453215976Sjmallett 4454215976Sjmallett/** 4455215976Sjmallett * cvmx_pci_tsr_reg 4456215976Sjmallett * 4457215976Sjmallett * PCI_TSR_REG = PCI Target Split Attribute Register 4458215976Sjmallett * 4459215976Sjmallett * This register contains the Attribute field Master Split Completion Message(SCM) generated when a master split 4460215976Sjmallett * transaction is aborted. 4461215976Sjmallett */ 4462215976Sjmallettunion cvmx_pci_tsr_reg 4463215976Sjmallett{ 4464215976Sjmallett uint64_t u64; 4465215976Sjmallett struct cvmx_pci_tsr_reg_s 4466215976Sjmallett { 4467215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4468215976Sjmallett uint64_t reserved_36_63 : 28; 4469215976Sjmallett uint64_t tsr : 36; /**< Contains the Target Split Attribute field when a 4470215976Sjmallett target-split transaction is aborted. 4471215976Sjmallett [35:32]: Upper Byte Count 4472215976Sjmallett [31]: BCM=Byte Count Modified 4473215976Sjmallett [30]: SCE=Split Completion Error 4474215976Sjmallett [29]: SCM=Split Completion Message 4475215976Sjmallett [28:24]: RESERVED 4476215976Sjmallett [23:16]: Completer Bus Number 4477215976Sjmallett [15:11]: Completer Device Number 4478215976Sjmallett [10:8]: Completer Function Number 4479215976Sjmallett [7:0]: Lower Byte Count 4480215976Sjmallett Refer to the PCIX1.0a specification, Fig 2-39 4481215976Sjmallett for additional details on the completer attribute 4482215976Sjmallett bit assignments. */ 4483215976Sjmallett#else 4484215976Sjmallett uint64_t tsr : 36; 4485215976Sjmallett uint64_t reserved_36_63 : 28; 4486215976Sjmallett#endif 4487215976Sjmallett } s; 4488215976Sjmallett struct cvmx_pci_tsr_reg_s cn30xx; 4489215976Sjmallett struct cvmx_pci_tsr_reg_s cn31xx; 4490215976Sjmallett struct cvmx_pci_tsr_reg_s cn38xx; 4491215976Sjmallett struct cvmx_pci_tsr_reg_s cn38xxp2; 4492215976Sjmallett struct cvmx_pci_tsr_reg_s cn50xx; 4493215976Sjmallett struct cvmx_pci_tsr_reg_s cn58xx; 4494215976Sjmallett struct cvmx_pci_tsr_reg_s cn58xxp1; 4495215976Sjmallett}; 4496215976Sjmalletttypedef union cvmx_pci_tsr_reg cvmx_pci_tsr_reg_t; 4497215976Sjmallett 4498215976Sjmallett/** 4499215976Sjmallett * cvmx_pci_win_rd_addr 4500215976Sjmallett * 4501215976Sjmallett * PCI_WIN_RD_ADDR = PCI Window Read Address Register 4502215976Sjmallett * 4503215976Sjmallett * Writing the least-significant-byte of this register will cause a read operation to take place, 4504215976Sjmallett * UNLESS, a read operation is already taking place. A read is consider to end when the PCI_WIN_RD_DATA 4505215976Sjmallett * register is read. 4506215976Sjmallett */ 4507215976Sjmallettunion cvmx_pci_win_rd_addr 4508215976Sjmallett{ 4509215976Sjmallett uint64_t u64; 4510215976Sjmallett struct cvmx_pci_win_rd_addr_s 4511215976Sjmallett { 4512215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4513215976Sjmallett uint64_t reserved_49_63 : 15; 4514215976Sjmallett uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4515215976Sjmallett read as '0'. */ 4516215976Sjmallett uint64_t reserved_0_47 : 48; 4517215976Sjmallett#else 4518215976Sjmallett uint64_t reserved_0_47 : 48; 4519215976Sjmallett uint64_t iobit : 1; 4520215976Sjmallett uint64_t reserved_49_63 : 15; 4521215976Sjmallett#endif 4522215976Sjmallett } s; 4523215976Sjmallett struct cvmx_pci_win_rd_addr_cn30xx 4524215976Sjmallett { 4525215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4526215976Sjmallett uint64_t reserved_49_63 : 15; 4527215976Sjmallett uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4528215976Sjmallett read as '0'. */ 4529215976Sjmallett uint64_t rd_addr : 46; /**< The address to be read from. Whenever the LSB of 4530215976Sjmallett this register is written, the Read Operation will 4531215976Sjmallett take place. 4532215976Sjmallett [47:40] = NCB_ID 4533215976Sjmallett [39:3] = Address 4534215976Sjmallett When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 4535215976Sjmallett [39:32] == x, Not Used 4536215976Sjmallett [31:27] == RSL_ID 4537215976Sjmallett [12:2] == RSL Register Offset 4538215976Sjmallett [1:0] == x, Not Used */ 4539215976Sjmallett uint64_t reserved_0_1 : 2; 4540215976Sjmallett#else 4541215976Sjmallett uint64_t reserved_0_1 : 2; 4542215976Sjmallett uint64_t rd_addr : 46; 4543215976Sjmallett uint64_t iobit : 1; 4544215976Sjmallett uint64_t reserved_49_63 : 15; 4545215976Sjmallett#endif 4546215976Sjmallett } cn30xx; 4547215976Sjmallett struct cvmx_pci_win_rd_addr_cn30xx cn31xx; 4548215976Sjmallett struct cvmx_pci_win_rd_addr_cn38xx 4549215976Sjmallett { 4550215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4551215976Sjmallett uint64_t reserved_49_63 : 15; 4552215976Sjmallett uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4553215976Sjmallett read as '0'. */ 4554215976Sjmallett uint64_t rd_addr : 45; /**< The address to be read from. Whenever the LSB of 4555215976Sjmallett this register is written, the Read Operation will 4556215976Sjmallett take place. 4557215976Sjmallett [47:40] = NCB_ID 4558215976Sjmallett [39:3] = Address 4559215976Sjmallett When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 4560215976Sjmallett [39:32] == x, Not Used 4561215976Sjmallett [31:27] == RSL_ID 4562215976Sjmallett [12:3] == RSL Register Offset 4563215976Sjmallett [2:0] == x, Not Used */ 4564215976Sjmallett uint64_t reserved_0_2 : 3; 4565215976Sjmallett#else 4566215976Sjmallett uint64_t reserved_0_2 : 3; 4567215976Sjmallett uint64_t rd_addr : 45; 4568215976Sjmallett uint64_t iobit : 1; 4569215976Sjmallett uint64_t reserved_49_63 : 15; 4570215976Sjmallett#endif 4571215976Sjmallett } cn38xx; 4572215976Sjmallett struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2; 4573215976Sjmallett struct cvmx_pci_win_rd_addr_cn30xx cn50xx; 4574215976Sjmallett struct cvmx_pci_win_rd_addr_cn38xx cn58xx; 4575215976Sjmallett struct cvmx_pci_win_rd_addr_cn38xx cn58xxp1; 4576215976Sjmallett}; 4577215976Sjmalletttypedef union cvmx_pci_win_rd_addr cvmx_pci_win_rd_addr_t; 4578215976Sjmallett 4579215976Sjmallett/** 4580215976Sjmallett * cvmx_pci_win_rd_data 4581215976Sjmallett * 4582215976Sjmallett * PCI_WIN_RD_DATA = PCI Window Read Data Register 4583215976Sjmallett * 4584215976Sjmallett * Contains the result from the read operation that took place when the LSB of the PCI_WIN_RD_ADDR 4585215976Sjmallett * register was written. 4586215976Sjmallett */ 4587215976Sjmallettunion cvmx_pci_win_rd_data 4588215976Sjmallett{ 4589215976Sjmallett uint64_t u64; 4590215976Sjmallett struct cvmx_pci_win_rd_data_s 4591215976Sjmallett { 4592215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4593215976Sjmallett uint64_t rd_data : 64; /**< The read data. */ 4594215976Sjmallett#else 4595215976Sjmallett uint64_t rd_data : 64; 4596215976Sjmallett#endif 4597215976Sjmallett } s; 4598215976Sjmallett struct cvmx_pci_win_rd_data_s cn30xx; 4599215976Sjmallett struct cvmx_pci_win_rd_data_s cn31xx; 4600215976Sjmallett struct cvmx_pci_win_rd_data_s cn38xx; 4601215976Sjmallett struct cvmx_pci_win_rd_data_s cn38xxp2; 4602215976Sjmallett struct cvmx_pci_win_rd_data_s cn50xx; 4603215976Sjmallett struct cvmx_pci_win_rd_data_s cn58xx; 4604215976Sjmallett struct cvmx_pci_win_rd_data_s cn58xxp1; 4605215976Sjmallett}; 4606215976Sjmalletttypedef union cvmx_pci_win_rd_data cvmx_pci_win_rd_data_t; 4607215976Sjmallett 4608215976Sjmallett/** 4609215976Sjmallett * cvmx_pci_win_wr_addr 4610215976Sjmallett * 4611215976Sjmallett * PCI_WIN_WR_ADDR = PCI Window Write Address Register 4612215976Sjmallett * 4613215976Sjmallett * Contains the address to be writen to when a write operation is started by writing the 4614215976Sjmallett * PCI_WIN_WR_DATA register (see below). 4615215976Sjmallett */ 4616215976Sjmallettunion cvmx_pci_win_wr_addr 4617215976Sjmallett{ 4618215976Sjmallett uint64_t u64; 4619215976Sjmallett struct cvmx_pci_win_wr_addr_s 4620215976Sjmallett { 4621215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4622215976Sjmallett uint64_t reserved_49_63 : 15; 4623215976Sjmallett uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4624215976Sjmallett read as '0'. */ 4625215976Sjmallett uint64_t wr_addr : 45; /**< The address that will be written to when the 4626215976Sjmallett PCI_WIN_WR_DATA register is written. 4627215976Sjmallett [47:40] = NCB_ID 4628215976Sjmallett [39:3] = Address 4629215976Sjmallett When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 4630215976Sjmallett [39:32] == x, Not Used 4631215976Sjmallett [31:27] == RSL_ID 4632215976Sjmallett [12:3] == RSL Register Offset 4633215976Sjmallett [2:0] == x, Not Used */ 4634215976Sjmallett uint64_t reserved_0_2 : 3; 4635215976Sjmallett#else 4636215976Sjmallett uint64_t reserved_0_2 : 3; 4637215976Sjmallett uint64_t wr_addr : 45; 4638215976Sjmallett uint64_t iobit : 1; 4639215976Sjmallett uint64_t reserved_49_63 : 15; 4640215976Sjmallett#endif 4641215976Sjmallett } s; 4642215976Sjmallett struct cvmx_pci_win_wr_addr_s cn30xx; 4643215976Sjmallett struct cvmx_pci_win_wr_addr_s cn31xx; 4644215976Sjmallett struct cvmx_pci_win_wr_addr_s cn38xx; 4645215976Sjmallett struct cvmx_pci_win_wr_addr_s cn38xxp2; 4646215976Sjmallett struct cvmx_pci_win_wr_addr_s cn50xx; 4647215976Sjmallett struct cvmx_pci_win_wr_addr_s cn58xx; 4648215976Sjmallett struct cvmx_pci_win_wr_addr_s cn58xxp1; 4649215976Sjmallett}; 4650215976Sjmalletttypedef union cvmx_pci_win_wr_addr cvmx_pci_win_wr_addr_t; 4651215976Sjmallett 4652215976Sjmallett/** 4653215976Sjmallett * cvmx_pci_win_wr_data 4654215976Sjmallett * 4655215976Sjmallett * PCI_WIN_WR_DATA = PCI Window Write Data Register 4656215976Sjmallett * 4657215976Sjmallett * Contains the data to write to the address located in the PCI_WIN_WR_ADDR Register. 4658215976Sjmallett * Writing the least-significant-byte of this register will cause a write operation to take place. 4659215976Sjmallett */ 4660215976Sjmallettunion cvmx_pci_win_wr_data 4661215976Sjmallett{ 4662215976Sjmallett uint64_t u64; 4663215976Sjmallett struct cvmx_pci_win_wr_data_s 4664215976Sjmallett { 4665215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4666215976Sjmallett uint64_t wr_data : 64; /**< The data to be written. Whenever the LSB of this 4667215976Sjmallett register is written, the Window Write will take 4668215976Sjmallett place. */ 4669215976Sjmallett#else 4670215976Sjmallett uint64_t wr_data : 64; 4671215976Sjmallett#endif 4672215976Sjmallett } s; 4673215976Sjmallett struct cvmx_pci_win_wr_data_s cn30xx; 4674215976Sjmallett struct cvmx_pci_win_wr_data_s cn31xx; 4675215976Sjmallett struct cvmx_pci_win_wr_data_s cn38xx; 4676215976Sjmallett struct cvmx_pci_win_wr_data_s cn38xxp2; 4677215976Sjmallett struct cvmx_pci_win_wr_data_s cn50xx; 4678215976Sjmallett struct cvmx_pci_win_wr_data_s cn58xx; 4679215976Sjmallett struct cvmx_pci_win_wr_data_s cn58xxp1; 4680215976Sjmallett}; 4681215976Sjmalletttypedef union cvmx_pci_win_wr_data cvmx_pci_win_wr_data_t; 4682215976Sjmallett 4683215976Sjmallett/** 4684215976Sjmallett * cvmx_pci_win_wr_mask 4685215976Sjmallett * 4686215976Sjmallett * PCI_WIN_WR_MASK = PCI Window Write Mask Register 4687215976Sjmallett * 4688215976Sjmallett * Contains the mask for the data in the PCI_WIN_WR_DATA Register. 4689215976Sjmallett */ 4690215976Sjmallettunion cvmx_pci_win_wr_mask 4691215976Sjmallett{ 4692215976Sjmallett uint64_t u64; 4693215976Sjmallett struct cvmx_pci_win_wr_mask_s 4694215976Sjmallett { 4695215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4696215976Sjmallett uint64_t reserved_8_63 : 56; 4697215976Sjmallett uint64_t wr_mask : 8; /**< The data to be written. When a bit is set '1' 4698215976Sjmallett the corresponding byte will not be written. */ 4699215976Sjmallett#else 4700215976Sjmallett uint64_t wr_mask : 8; 4701215976Sjmallett uint64_t reserved_8_63 : 56; 4702215976Sjmallett#endif 4703215976Sjmallett } s; 4704215976Sjmallett struct cvmx_pci_win_wr_mask_s cn30xx; 4705215976Sjmallett struct cvmx_pci_win_wr_mask_s cn31xx; 4706215976Sjmallett struct cvmx_pci_win_wr_mask_s cn38xx; 4707215976Sjmallett struct cvmx_pci_win_wr_mask_s cn38xxp2; 4708215976Sjmallett struct cvmx_pci_win_wr_mask_s cn50xx; 4709215976Sjmallett struct cvmx_pci_win_wr_mask_s cn58xx; 4710215976Sjmallett struct cvmx_pci_win_wr_mask_s cn58xxp1; 4711215976Sjmallett}; 4712215976Sjmalletttypedef union cvmx_pci_win_wr_mask cvmx_pci_win_wr_mask_t; 4713215976Sjmallett 4714215976Sjmallett#endif 4715