1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett 45215990Sjmallett 46210284Sjmallett/** 47210284Sjmallett * @file 48210284Sjmallett * 49210284Sjmallett * PCI / PCIe packet engine related structures. 50210284Sjmallett * 51232812Sjmallett * <hr>$Revision: 70030 $<hr> 52210284Sjmallett */ 53210284Sjmallett 54210284Sjmallett#ifndef __CVMX_NPI_H__ 55210284Sjmallett#define __CVMX_NPI_H__ 56210284Sjmallett 57210284Sjmallett#ifdef __cplusplus 58210284Sjmallettextern "C" { 59210284Sjmallett#endif 60210284Sjmallett 61210284Sjmallett/** 62210284Sjmallett * PCI / PCIe packet instruction header format 63210284Sjmallett */ 64210284Sjmalletttypedef union 65210284Sjmallett{ 66210284Sjmallett uint64_t u64; 67210284Sjmallett struct 68210284Sjmallett { 69232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 70210284Sjmallett uint64_t r : 1; /**< Packet is RAW */ 71210284Sjmallett uint64_t g : 1; /**< Gather list is used */ 72210284Sjmallett uint64_t dlengsz : 14; /**< Data length / Gather list size */ 73210284Sjmallett uint64_t fsz : 6; /**< Front data size */ 74210284Sjmallett uint64_t qos : 3; /**< POW QoS queue */ 75210284Sjmallett uint64_t grp : 4; /**< POW Group */ 76210284Sjmallett uint64_t rs : 1; /**< Real short */ 77210284Sjmallett cvmx_pow_tag_type_t tt : 2; /**< POW Tag type */ 78210284Sjmallett uint64_t tag : 32; /**< POW 32 bit tag */ 79210284Sjmallett#else 80210284Sjmallett uint64_t tag : 32; 81210284Sjmallett cvmx_pow_tag_type_t tt : 2; 82210284Sjmallett uint64_t rs : 1; 83210284Sjmallett uint64_t grp : 4; 84210284Sjmallett uint64_t qos : 3; 85210284Sjmallett uint64_t fsz : 6; 86210284Sjmallett uint64_t dlengsz : 14; 87210284Sjmallett uint64_t g : 1; 88210284Sjmallett uint64_t r : 1; 89210284Sjmallett#endif 90210284Sjmallett } s; 91210284Sjmallett} cvmx_npi_inst_hdr_t; 92210284Sjmallett 93210284Sjmallett/** 94210284Sjmallett * PCI / PCIe packet data pointer formats 0-3 95210284Sjmallett */ 96210284Sjmalletttypedef union 97210284Sjmallett{ 98210284Sjmallett uint64_t dptr0; 99210284Sjmallett struct 100210284Sjmallett { 101232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 102210284Sjmallett uint64_t es : 2; /**< Endian swap mode */ 103210284Sjmallett uint64_t ns : 1; /**< No snoop */ 104210284Sjmallett uint64_t ro : 1; /**< Relaxed ordering */ 105210284Sjmallett uint64_t addr : 60; /**< PCI/PCIe address */ 106210284Sjmallett#else 107210284Sjmallett uint64_t addr : 60; 108210284Sjmallett uint64_t ro : 1; 109210284Sjmallett uint64_t ns : 1; 110210284Sjmallett uint64_t es : 2; 111210284Sjmallett#endif 112210284Sjmallett } dptr1; 113210284Sjmallett struct 114210284Sjmallett { 115232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 116210284Sjmallett uint64_t pm : 2; /**< Parse mode */ 117210284Sjmallett uint64_t sl : 7; /**< Skip length */ 118210284Sjmallett uint64_t addr : 55; /**< PCI/PCIe address */ 119210284Sjmallett#else 120210284Sjmallett uint64_t addr : 55; 121210284Sjmallett uint64_t sl : 7; 122210284Sjmallett uint64_t pm : 2; 123210284Sjmallett#endif 124210284Sjmallett } dptr2; 125210284Sjmallett struct 126210284Sjmallett { 127232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 128210284Sjmallett uint64_t es : 2; /**< Endian swap mode */ 129210284Sjmallett uint64_t ns : 1; /**< No snoop */ 130210284Sjmallett uint64_t ro : 1; /**< Relaxed ordering */ 131210284Sjmallett uint64_t pm : 2; /**< Parse mode */ 132210284Sjmallett uint64_t sl : 7; /**< Skip length */ 133210284Sjmallett uint64_t addr : 51; /**< PCI/PCIe address */ 134210284Sjmallett#else 135210284Sjmallett uint64_t addr : 51; 136210284Sjmallett uint64_t sl : 7; 137210284Sjmallett uint64_t pm : 2; 138210284Sjmallett uint64_t ro : 1; 139210284Sjmallett uint64_t ns : 1; 140210284Sjmallett uint64_t es : 2; 141210284Sjmallett#endif 142210284Sjmallett } dptr3; 143210284Sjmallett} cvmx_npi_dptr_t; 144210284Sjmallett 145210284Sjmallett#ifdef __cplusplus 146210284Sjmallett} 147210284Sjmallett#endif 148210284Sjmallett 149210284Sjmallett#endif /* __CVMX_NPI_H__ */ 150