cvmx-l2c.h revision 210284
1/***********************license start*************** 2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 * 23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31 * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33 * 34 * 35 * For any questions regarding licensing please contact marketing@caviumnetworks.com 36 * 37 ***********************license end**************************************/ 38 39 40 41 42 43 44/** 45 * @file 46 * 47 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging 48 * facilities. 49 * 50 * <hr>$Revision: 41586 $<hr> 51 * 52 */ 53 54#ifndef __CVMX_L2C_H__ 55#define __CVMX_L2C_H__ 56 57#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */ 58#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */ 59#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */ 60 61 62#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */ 63#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) 64 65/* Defines for index aliasing computations */ 66#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits()) 67#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) 68 69 70 /*------------*/ 71 /* TYPEDEFS */ 72 /*------------*/ 73typedef union { // L2C Tag/Data Store Debug Register 74 uint64_t u64; 75 struct { 76 uint64_t reserved: 32, 77 lfb_enum: 4, 78 lfb_dmp: 1, 79 ppnum: 4, 80 set: 3, 81 finv: 1, 82 l2d: 1, 83 l2t: 1; 84 }; 85} cvmx_l2c_dbg; 86 87typedef union 88{ 89 uint64_t u64; 90#if __BYTE_ORDER == __BIG_ENDIAN 91 struct 92 { 93 uint64_t reserved : 28; 94 uint64_t V : 1; // Line valid 95 uint64_t D : 1; // Line dirty 96 uint64_t L : 1; // Line locked 97 uint64_t U : 1; // Use, LRU eviction 98 uint64_t addr : 32; // Phys mem (not all bits valid) 99 } s; 100#endif 101} cvmx_l2c_tag_t; 102 103 104 /* L2C Performance Counter events. */ 105typedef enum 106{ 107 CVMX_L2C_EVENT_CYCLES = 0, 108 CVMX_L2C_EVENT_INSTRUCTION_MISS = 1, 109 CVMX_L2C_EVENT_INSTRUCTION_HIT = 2, 110 CVMX_L2C_EVENT_DATA_MISS = 3, 111 CVMX_L2C_EVENT_DATA_HIT = 4, 112 CVMX_L2C_EVENT_MISS = 5, 113 CVMX_L2C_EVENT_HIT = 6, 114 CVMX_L2C_EVENT_VICTIM_HIT = 7, 115 CVMX_L2C_EVENT_INDEX_CONFLICT = 8, 116 CVMX_L2C_EVENT_TAG_PROBE = 9, 117 CVMX_L2C_EVENT_TAG_UPDATE = 10, 118 CVMX_L2C_EVENT_TAG_COMPLETE = 11, 119 CVMX_L2C_EVENT_TAG_DIRTY = 12, 120 CVMX_L2C_EVENT_DATA_STORE_NOP = 13, 121 CVMX_L2C_EVENT_DATA_STORE_READ = 14, 122 CVMX_L2C_EVENT_DATA_STORE_WRITE = 15, 123 CVMX_L2C_EVENT_FILL_DATA_VALID = 16, 124 CVMX_L2C_EVENT_WRITE_REQUEST = 17, 125 CVMX_L2C_EVENT_READ_REQUEST = 18, 126 CVMX_L2C_EVENT_WRITE_DATA_VALID = 19, 127 CVMX_L2C_EVENT_XMC_NOP = 20, 128 CVMX_L2C_EVENT_XMC_LDT = 21, 129 CVMX_L2C_EVENT_XMC_LDI = 22, 130 CVMX_L2C_EVENT_XMC_LDD = 23, 131 CVMX_L2C_EVENT_XMC_STF = 24, 132 CVMX_L2C_EVENT_XMC_STT = 25, 133 CVMX_L2C_EVENT_XMC_STP = 26, 134 CVMX_L2C_EVENT_XMC_STC = 27, 135 CVMX_L2C_EVENT_XMC_DWB = 28, 136 CVMX_L2C_EVENT_XMC_PL2 = 29, 137 CVMX_L2C_EVENT_XMC_PSL1 = 30, 138 CVMX_L2C_EVENT_XMC_IOBLD = 31, 139 CVMX_L2C_EVENT_XMC_IOBST = 32, 140 CVMX_L2C_EVENT_XMC_IOBDMA = 33, 141 CVMX_L2C_EVENT_XMC_IOBRSP = 34, 142 CVMX_L2C_EVENT_XMC_BUS_VALID = 35, 143 CVMX_L2C_EVENT_XMC_MEM_DATA = 36, 144 CVMX_L2C_EVENT_XMC_REFL_DATA = 37, 145 CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38, 146 CVMX_L2C_EVENT_RSC_NOP = 39, 147 CVMX_L2C_EVENT_RSC_STDN = 40, 148 CVMX_L2C_EVENT_RSC_FILL = 41, 149 CVMX_L2C_EVENT_RSC_REFL = 42, 150 CVMX_L2C_EVENT_RSC_STIN = 43, 151 CVMX_L2C_EVENT_RSC_SCIN = 44, 152 CVMX_L2C_EVENT_RSC_SCFL = 45, 153 CVMX_L2C_EVENT_RSC_SCDN = 46, 154 CVMX_L2C_EVENT_RSC_DATA_VALID = 47, 155 CVMX_L2C_EVENT_RSC_VALID_FILL = 48, 156 CVMX_L2C_EVENT_RSC_VALID_STRSP = 49, 157 CVMX_L2C_EVENT_RSC_VALID_REFL = 50, 158 CVMX_L2C_EVENT_LRF_REQ = 51, 159 CVMX_L2C_EVENT_DT_RD_ALLOC = 52, 160 CVMX_L2C_EVENT_DT_WR_INVAL = 53 161} cvmx_l2c_event_t; 162 163/** 164 * Configure one of the four L2 Cache performance counters to capture event 165 * occurences. 166 * 167 * @param counter The counter to configure. Range 0..3. 168 * @param event The type of L2 Cache event occurrence to count. 169 * @param clear_on_read When asserted, any read of the performance counter 170 * clears the counter. 171 * 172 * @note The routine does not clear the counter. 173 */ 174void cvmx_l2c_config_perf(uint32_t counter, 175 cvmx_l2c_event_t event, 176 uint32_t clear_on_read); 177/** 178 * Read the given L2 Cache performance counter. The counter must be configured 179 * before reading, but this routine does not enforce this requirement. 180 * 181 * @param counter The counter to configure. Range 0..3. 182 * 183 * @return The current counter value. 184 */ 185uint64_t cvmx_l2c_read_perf(uint32_t counter); 186 187/** 188 * Return the L2 Cache way partitioning for a given core. 189 * 190 * @param core The core processor of interest. 191 * 192 * @return The mask specifying the partitioning. 0 bits in mask indicates 193 * the cache 'ways' that a core can evict from. 194 * -1 on error 195 */ 196int cvmx_l2c_get_core_way_partition(uint32_t core); 197 198/** 199 * Partitions the L2 cache for a core 200 * 201 * @param core The core that the partitioning applies to. 202 * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core 203 * to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines 204 * from that way. There must be at least one allowed way (0 bit) in the mask. 205 * 206 * @note If any ways are blocked for all cores and the HW blocks, then those ways will never have 207 * any cache lines evicted from them. All cores and the hardware blocks are free to read from 208 * all ways regardless of the partitioning. 209 */ 210int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); 211 212/** 213 * Return the L2 Cache way partitioning for the hw blocks. 214 * 215 * @return The mask specifying the reserved way. 0 bits in mask indicates 216 * the cache 'ways' that a core can evict from. 217 * -1 on error 218 */ 219int cvmx_l2c_get_hw_way_partition(void); 220 221/** 222 * Partitions the L2 cache for the hardware blocks. 223 * 224 * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core 225 * to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines 226 * from that way. There must be at least one allowed way (0 bit) in the mask. 227 * 228 * @note If any ways are blocked for all cores and the HW blocks, then those ways will never have 229 * any cache lines evicted from them. All cores and the hardware blocks are free to read from 230 * all ways regardless of the partitioning. 231 */ 232int cvmx_l2c_set_hw_way_partition(uint32_t mask); 233 234 235/** 236 * Locks a line in the L2 cache at the specified physical address 237 * 238 * @param addr physical address of line to lock 239 * 240 * @return 0 on success, 241 * 1 if line not locked. 242 */ 243int cvmx_l2c_lock_line(uint64_t addr); 244 245/** 246 * Locks a specified memory region in the L2 cache. 247 * 248 * Note that if not all lines can be locked, that means that all 249 * but one of the ways (associations) available to the locking 250 * core are locked. Having only 1 association available for 251 * normal caching may have a significant adverse affect on performance. 252 * Care should be taken to ensure that enough of the L2 cache is left 253 * unlocked to allow for normal caching of DRAM. 254 * 255 * @param start Physical address of the start of the region to lock 256 * @param len Length (in bytes) of region to lock 257 * 258 * @return Number of requested lines that where not locked. 259 * 0 on success (all locked) 260 */ 261int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len); 262 263 264/** 265 * Unlock and flush a cache line from the L2 cache. 266 * IMPORTANT: Must only be run by one core at a time due to use 267 * of L2C debug features. 268 * Note that this function will flush a matching but unlocked cache line. 269 * (If address is not in L2, no lines are flushed.) 270 * 271 * @param address Physical address to unlock 272 * 273 * @return 0: line not unlocked 274 * 1: line unlocked 275 */ 276int cvmx_l2c_unlock_line(uint64_t address); 277 278/** 279 * Unlocks a region of memory that is locked in the L2 cache 280 * 281 * @param start start physical address 282 * @param len length (in bytes) to unlock 283 * 284 * @return Number of locked lines that the call unlocked 285 */ 286int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len); 287 288 289 290 291/** 292 * Read the L2 controller tag for a given location in L2 293 * 294 * @param association 295 * Which association to read line from 296 * @param index Which way to read from. 297 * 298 * @return l2c tag structure for line requested. 299 */ 300cvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index); 301 302/* Wrapper around deprecated old function name */ 303static inline cvmx_l2c_tag_t cvmx_get_l2c_tag(uint32_t association, uint32_t index) 304{ 305 return cvmx_l2c_get_tag(association, index); 306} 307 308 309/** 310 * Returns the cache index for a given physical address 311 * 312 * @param addr physical address 313 * 314 * @return L2 cache index 315 */ 316uint32_t cvmx_l2c_address_to_index (uint64_t addr); 317 318 319/** 320 * Flushes (and unlocks) the entire L2 cache. 321 * IMPORTANT: Must only be run by one core at a time due to use 322 * of L2C debug features. 323 */ 324void cvmx_l2c_flush(void); 325 326 327 328/** 329 * 330 * @return Returns the size of the L2 cache in bytes, 331 * -1 on error (unrecognized model) 332 */ 333int cvmx_l2c_get_cache_size_bytes(void); 334 335/** 336 * Return the number of sets in the L2 Cache 337 * 338 * @return 339 */ 340int cvmx_l2c_get_num_sets(void); 341 342/** 343 * Return log base 2 of the number of sets in the L2 cache 344 * @return 345 */ 346int cvmx_l2c_get_set_bits(void); 347/** 348 * Return the number of associations in the L2 Cache 349 * 350 * @return 351 */ 352int cvmx_l2c_get_num_assoc(void); 353 354/** 355 * Flush a line from the L2 cache 356 * This should only be called from one core at a time, as this routine 357 * sets the core to the 'debug' core in order to flush the line. 358 * 359 * @param assoc Association (or way) to flush 360 * @param index Index to flush 361 */ 362void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index); 363 364#endif /* __CVMX_L2C_H__ */ 365