1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-l2c-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon l2c. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_L2C_DEFS_H__ 53232812Sjmallett#define __CVMX_L2C_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_L2C_BIG_CTL CVMX_L2C_BIG_CTL_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_L2C_BIG_CTL_FUNC(void) 58215976Sjmallett{ 59232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60215976Sjmallett cvmx_warn("CVMX_L2C_BIG_CTL not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080800030ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_L2C_BIG_CTL (CVMX_ADD_IO_SEG(0x0001180080800030ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_L2C_BST CVMX_L2C_BST_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_L2C_BST_FUNC(void) 69215976Sjmallett{ 70232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 71215976Sjmallett cvmx_warn("CVMX_L2C_BST not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800808007F8ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_L2C_BST (CVMX_ADD_IO_SEG(0x00011800808007F8ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_L2C_BST0 CVMX_L2C_BST0_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_L2C_BST0_FUNC(void) 80215976Sjmallett{ 81215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 82215976Sjmallett cvmx_warn("CVMX_L2C_BST0 not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800007F8ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallett#define CVMX_L2C_BST1 CVMX_L2C_BST1_FUNC() 90215976Sjmallettstatic inline uint64_t CVMX_L2C_BST1_FUNC(void) 91215976Sjmallett{ 92215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 93215976Sjmallett cvmx_warn("CVMX_L2C_BST1 not supported on this chip\n"); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800007F0ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallett#define CVMX_L2C_BST2 CVMX_L2C_BST2_FUNC() 101215976Sjmallettstatic inline uint64_t CVMX_L2C_BST2_FUNC(void) 102215976Sjmallett{ 103215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 104215976Sjmallett cvmx_warn("CVMX_L2C_BST2 not supported on this chip\n"); 105215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800007E8ull); 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull)) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallettstatic inline uint64_t CVMX_L2C_BST_MEMX(unsigned long block_id) 112215976Sjmallett{ 113215976Sjmallett if (!( 114232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 115232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 116232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 117232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 118232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 119215976Sjmallett cvmx_warn("CVMX_L2C_BST_MEMX(%lu) is invalid on this chip\n", block_id); 120232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080C007F8ull) + ((block_id) & 3) * 0x40000ull; 121215976Sjmallett} 122215976Sjmallett#else 123232812Sjmallett#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull) + ((block_id) & 3) * 0x40000ull) 124215976Sjmallett#endif 125215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 126215976Sjmallettstatic inline uint64_t CVMX_L2C_BST_TDTX(unsigned long block_id) 127215976Sjmallett{ 128215976Sjmallett if (!( 129232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 130232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 131232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 132232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 133232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 134215976Sjmallett cvmx_warn("CVMX_L2C_BST_TDTX(%lu) is invalid on this chip\n", block_id); 135232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A007F0ull) + ((block_id) & 3) * 0x40000ull; 136215976Sjmallett} 137215976Sjmallett#else 138232812Sjmallett#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull) + ((block_id) & 3) * 0x40000ull) 139215976Sjmallett#endif 140215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 141215976Sjmallettstatic inline uint64_t CVMX_L2C_BST_TTGX(unsigned long block_id) 142215976Sjmallett{ 143215976Sjmallett if (!( 144232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 145232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 146232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 147232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 148232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 149215976Sjmallett cvmx_warn("CVMX_L2C_BST_TTGX(%lu) is invalid on this chip\n", block_id); 150232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A007F8ull) + ((block_id) & 3) * 0x40000ull; 151215976Sjmallett} 152215976Sjmallett#else 153232812Sjmallett#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull) + ((block_id) & 3) * 0x40000ull) 154215976Sjmallett#endif 155215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 156215976Sjmallett#define CVMX_L2C_CFG CVMX_L2C_CFG_FUNC() 157215976Sjmallettstatic inline uint64_t CVMX_L2C_CFG_FUNC(void) 158215976Sjmallett{ 159215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 160215976Sjmallett cvmx_warn("CVMX_L2C_CFG not supported on this chip\n"); 161215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000000ull); 162215976Sjmallett} 163215976Sjmallett#else 164215976Sjmallett#define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull)) 165215976Sjmallett#endif 166215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 167215976Sjmallettstatic inline uint64_t CVMX_L2C_COP0_MAPX(unsigned long offset) 168215976Sjmallett{ 169215976Sjmallett if (!( 170232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1023) || ((offset >= 16128) && (offset <= 16383)))) || 171232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1535) || ((offset >= 16128) && (offset <= 16383)))) || 172232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 2559) || ((offset >= 16128) && (offset <= 16383)))) || 173232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8191) || ((offset >= 16128) && (offset <= 16383)))) || 174232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1023) || ((offset >= 16128) && (offset <= 16383)))))) 175215976Sjmallett cvmx_warn("CVMX_L2C_COP0_MAPX(%lu) is invalid on this chip\n", offset); 176215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8; 177215976Sjmallett} 178215976Sjmallett#else 179215976Sjmallett#define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8) 180215976Sjmallett#endif 181215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 182215976Sjmallett#define CVMX_L2C_CTL CVMX_L2C_CTL_FUNC() 183215976Sjmallettstatic inline uint64_t CVMX_L2C_CTL_FUNC(void) 184215976Sjmallett{ 185232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 186215976Sjmallett cvmx_warn("CVMX_L2C_CTL not supported on this chip\n"); 187215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080800000ull); 188215976Sjmallett} 189215976Sjmallett#else 190215976Sjmallett#define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull)) 191215976Sjmallett#endif 192215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 193215976Sjmallett#define CVMX_L2C_DBG CVMX_L2C_DBG_FUNC() 194215976Sjmallettstatic inline uint64_t CVMX_L2C_DBG_FUNC(void) 195215976Sjmallett{ 196215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 197215976Sjmallett cvmx_warn("CVMX_L2C_DBG not supported on this chip\n"); 198215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000030ull); 199215976Sjmallett} 200215976Sjmallett#else 201215976Sjmallett#define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull)) 202215976Sjmallett#endif 203215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 204215976Sjmallett#define CVMX_L2C_DUT CVMX_L2C_DUT_FUNC() 205215976Sjmallettstatic inline uint64_t CVMX_L2C_DUT_FUNC(void) 206215976Sjmallett{ 207215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 208215976Sjmallett cvmx_warn("CVMX_L2C_DUT not supported on this chip\n"); 209215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000050ull); 210215976Sjmallett} 211215976Sjmallett#else 212215976Sjmallett#define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull)) 213215976Sjmallett#endif 214215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 215215976Sjmallettstatic inline uint64_t CVMX_L2C_DUT_MAPX(unsigned long offset) 216215976Sjmallett{ 217215976Sjmallett if (!( 218232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1023))) || 219232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1535))) || 220232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 2559))) || 221232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8191))) || 222232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1023))))) 223215976Sjmallett cvmx_warn("CVMX_L2C_DUT_MAPX(%lu) is invalid on this chip\n", offset); 224232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 8191) * 8; 225215976Sjmallett} 226215976Sjmallett#else 227232812Sjmallett#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 8191) * 8) 228215976Sjmallett#endif 229215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 230215976Sjmallettstatic inline uint64_t CVMX_L2C_ERR_TDTX(unsigned long block_id) 231215976Sjmallett{ 232215976Sjmallett if (!( 233232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 234232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 235232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 236232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 237232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 238215976Sjmallett cvmx_warn("CVMX_L2C_ERR_TDTX(%lu) is invalid on this chip\n", block_id); 239232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull; 240215976Sjmallett} 241215976Sjmallett#else 242232812Sjmallett#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull) 243215976Sjmallett#endif 244215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 245215976Sjmallettstatic inline uint64_t CVMX_L2C_ERR_TTGX(unsigned long block_id) 246215976Sjmallett{ 247215976Sjmallett if (!( 248232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 249232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 250232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 251232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 252232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 253215976Sjmallett cvmx_warn("CVMX_L2C_ERR_TTGX(%lu) is invalid on this chip\n", block_id); 254232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull; 255215976Sjmallett} 256215976Sjmallett#else 257232812Sjmallett#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull) 258215976Sjmallett#endif 259215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 260215976Sjmallettstatic inline uint64_t CVMX_L2C_ERR_VBFX(unsigned long block_id) 261215976Sjmallett{ 262215976Sjmallett if (!( 263232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 264232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 265232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 266232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 267232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 268215976Sjmallett cvmx_warn("CVMX_L2C_ERR_VBFX(%lu) is invalid on this chip\n", block_id); 269232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080C007F0ull) + ((block_id) & 3) * 0x40000ull; 270215976Sjmallett} 271215976Sjmallett#else 272232812Sjmallett#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull) + ((block_id) & 3) * 0x40000ull) 273215976Sjmallett#endif 274215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 275215976Sjmallett#define CVMX_L2C_ERR_XMC CVMX_L2C_ERR_XMC_FUNC() 276215976Sjmallettstatic inline uint64_t CVMX_L2C_ERR_XMC_FUNC(void) 277215976Sjmallett{ 278232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 279215976Sjmallett cvmx_warn("CVMX_L2C_ERR_XMC not supported on this chip\n"); 280215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800808007D8ull); 281215976Sjmallett} 282215976Sjmallett#else 283215976Sjmallett#define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull)) 284215976Sjmallett#endif 285215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 286215976Sjmallett#define CVMX_L2C_GRPWRR0 CVMX_L2C_GRPWRR0_FUNC() 287215976Sjmallettstatic inline uint64_t CVMX_L2C_GRPWRR0_FUNC(void) 288215976Sjmallett{ 289215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 290215976Sjmallett cvmx_warn("CVMX_L2C_GRPWRR0 not supported on this chip\n"); 291215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800000C8ull); 292215976Sjmallett} 293215976Sjmallett#else 294215976Sjmallett#define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull)) 295215976Sjmallett#endif 296215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 297215976Sjmallett#define CVMX_L2C_GRPWRR1 CVMX_L2C_GRPWRR1_FUNC() 298215976Sjmallettstatic inline uint64_t CVMX_L2C_GRPWRR1_FUNC(void) 299215976Sjmallett{ 300215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 301215976Sjmallett cvmx_warn("CVMX_L2C_GRPWRR1 not supported on this chip\n"); 302215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800000D0ull); 303215976Sjmallett} 304215976Sjmallett#else 305215976Sjmallett#define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull)) 306215976Sjmallett#endif 307215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 308215976Sjmallett#define CVMX_L2C_INT_EN CVMX_L2C_INT_EN_FUNC() 309215976Sjmallettstatic inline uint64_t CVMX_L2C_INT_EN_FUNC(void) 310215976Sjmallett{ 311215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 312215976Sjmallett cvmx_warn("CVMX_L2C_INT_EN not supported on this chip\n"); 313215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000100ull); 314215976Sjmallett} 315215976Sjmallett#else 316215976Sjmallett#define CVMX_L2C_INT_EN (CVMX_ADD_IO_SEG(0x0001180080000100ull)) 317215976Sjmallett#endif 318215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 319215976Sjmallett#define CVMX_L2C_INT_ENA CVMX_L2C_INT_ENA_FUNC() 320215976Sjmallettstatic inline uint64_t CVMX_L2C_INT_ENA_FUNC(void) 321215976Sjmallett{ 322232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 323215976Sjmallett cvmx_warn("CVMX_L2C_INT_ENA not supported on this chip\n"); 324215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080800020ull); 325215976Sjmallett} 326215976Sjmallett#else 327215976Sjmallett#define CVMX_L2C_INT_ENA (CVMX_ADD_IO_SEG(0x0001180080800020ull)) 328215976Sjmallett#endif 329215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 330215976Sjmallett#define CVMX_L2C_INT_REG CVMX_L2C_INT_REG_FUNC() 331215976Sjmallettstatic inline uint64_t CVMX_L2C_INT_REG_FUNC(void) 332215976Sjmallett{ 333232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 334215976Sjmallett cvmx_warn("CVMX_L2C_INT_REG not supported on this chip\n"); 335215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080800018ull); 336215976Sjmallett} 337215976Sjmallett#else 338215976Sjmallett#define CVMX_L2C_INT_REG (CVMX_ADD_IO_SEG(0x0001180080800018ull)) 339215976Sjmallett#endif 340215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341215976Sjmallett#define CVMX_L2C_INT_STAT CVMX_L2C_INT_STAT_FUNC() 342215976Sjmallettstatic inline uint64_t CVMX_L2C_INT_STAT_FUNC(void) 343215976Sjmallett{ 344215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 345215976Sjmallett cvmx_warn("CVMX_L2C_INT_STAT not supported on this chip\n"); 346215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800000F8ull); 347215976Sjmallett} 348215976Sjmallett#else 349215976Sjmallett#define CVMX_L2C_INT_STAT (CVMX_ADD_IO_SEG(0x00011800800000F8ull)) 350215976Sjmallett#endif 351215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 352215976Sjmallettstatic inline uint64_t CVMX_L2C_IOCX_PFC(unsigned long block_id) 353215976Sjmallett{ 354215976Sjmallett if (!( 355232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 356232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 357232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 358232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 359232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 360215976Sjmallett cvmx_warn("CVMX_L2C_IOCX_PFC(%lu) is invalid on this chip\n", block_id); 361215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080800420ull); 362215976Sjmallett} 363215976Sjmallett#else 364215976Sjmallett#define CVMX_L2C_IOCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800420ull)) 365215976Sjmallett#endif 366215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 367215976Sjmallettstatic inline uint64_t CVMX_L2C_IORX_PFC(unsigned long block_id) 368215976Sjmallett{ 369215976Sjmallett if (!( 370232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 371232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 372232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 373232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 374232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 375215976Sjmallett cvmx_warn("CVMX_L2C_IORX_PFC(%lu) is invalid on this chip\n", block_id); 376215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080800428ull); 377215976Sjmallett} 378215976Sjmallett#else 379215976Sjmallett#define CVMX_L2C_IORX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800428ull)) 380215976Sjmallett#endif 381215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 382215976Sjmallett#define CVMX_L2C_LCKBASE CVMX_L2C_LCKBASE_FUNC() 383215976Sjmallettstatic inline uint64_t CVMX_L2C_LCKBASE_FUNC(void) 384215976Sjmallett{ 385215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 386215976Sjmallett cvmx_warn("CVMX_L2C_LCKBASE not supported on this chip\n"); 387215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000058ull); 388215976Sjmallett} 389215976Sjmallett#else 390215976Sjmallett#define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull)) 391215976Sjmallett#endif 392215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 393215976Sjmallett#define CVMX_L2C_LCKOFF CVMX_L2C_LCKOFF_FUNC() 394215976Sjmallettstatic inline uint64_t CVMX_L2C_LCKOFF_FUNC(void) 395215976Sjmallett{ 396215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 397215976Sjmallett cvmx_warn("CVMX_L2C_LCKOFF not supported on this chip\n"); 398215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000060ull); 399215976Sjmallett} 400215976Sjmallett#else 401215976Sjmallett#define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull)) 402215976Sjmallett#endif 403215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 404215976Sjmallett#define CVMX_L2C_LFB0 CVMX_L2C_LFB0_FUNC() 405215976Sjmallettstatic inline uint64_t CVMX_L2C_LFB0_FUNC(void) 406215976Sjmallett{ 407215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 408215976Sjmallett cvmx_warn("CVMX_L2C_LFB0 not supported on this chip\n"); 409215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000038ull); 410215976Sjmallett} 411215976Sjmallett#else 412215976Sjmallett#define CVMX_L2C_LFB0 (CVMX_ADD_IO_SEG(0x0001180080000038ull)) 413215976Sjmallett#endif 414215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 415215976Sjmallett#define CVMX_L2C_LFB1 CVMX_L2C_LFB1_FUNC() 416215976Sjmallettstatic inline uint64_t CVMX_L2C_LFB1_FUNC(void) 417215976Sjmallett{ 418215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 419215976Sjmallett cvmx_warn("CVMX_L2C_LFB1 not supported on this chip\n"); 420215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000040ull); 421215976Sjmallett} 422215976Sjmallett#else 423215976Sjmallett#define CVMX_L2C_LFB1 (CVMX_ADD_IO_SEG(0x0001180080000040ull)) 424215976Sjmallett#endif 425215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 426215976Sjmallett#define CVMX_L2C_LFB2 CVMX_L2C_LFB2_FUNC() 427215976Sjmallettstatic inline uint64_t CVMX_L2C_LFB2_FUNC(void) 428215976Sjmallett{ 429215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 430215976Sjmallett cvmx_warn("CVMX_L2C_LFB2 not supported on this chip\n"); 431215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000048ull); 432215976Sjmallett} 433215976Sjmallett#else 434215976Sjmallett#define CVMX_L2C_LFB2 (CVMX_ADD_IO_SEG(0x0001180080000048ull)) 435215976Sjmallett#endif 436215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 437215976Sjmallett#define CVMX_L2C_LFB3 CVMX_L2C_LFB3_FUNC() 438215976Sjmallettstatic inline uint64_t CVMX_L2C_LFB3_FUNC(void) 439215976Sjmallett{ 440215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 441215976Sjmallett cvmx_warn("CVMX_L2C_LFB3 not supported on this chip\n"); 442215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800000B8ull); 443215976Sjmallett} 444215976Sjmallett#else 445215976Sjmallett#define CVMX_L2C_LFB3 (CVMX_ADD_IO_SEG(0x00011800800000B8ull)) 446215976Sjmallett#endif 447215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 448215976Sjmallett#define CVMX_L2C_OOB CVMX_L2C_OOB_FUNC() 449215976Sjmallettstatic inline uint64_t CVMX_L2C_OOB_FUNC(void) 450215976Sjmallett{ 451215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 452215976Sjmallett cvmx_warn("CVMX_L2C_OOB not supported on this chip\n"); 453215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800000D8ull); 454215976Sjmallett} 455215976Sjmallett#else 456215976Sjmallett#define CVMX_L2C_OOB (CVMX_ADD_IO_SEG(0x00011800800000D8ull)) 457215976Sjmallett#endif 458215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 459215976Sjmallett#define CVMX_L2C_OOB1 CVMX_L2C_OOB1_FUNC() 460215976Sjmallettstatic inline uint64_t CVMX_L2C_OOB1_FUNC(void) 461215976Sjmallett{ 462215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 463215976Sjmallett cvmx_warn("CVMX_L2C_OOB1 not supported on this chip\n"); 464215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800000E0ull); 465215976Sjmallett} 466215976Sjmallett#else 467215976Sjmallett#define CVMX_L2C_OOB1 (CVMX_ADD_IO_SEG(0x00011800800000E0ull)) 468215976Sjmallett#endif 469215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 470215976Sjmallett#define CVMX_L2C_OOB2 CVMX_L2C_OOB2_FUNC() 471215976Sjmallettstatic inline uint64_t CVMX_L2C_OOB2_FUNC(void) 472215976Sjmallett{ 473215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 474215976Sjmallett cvmx_warn("CVMX_L2C_OOB2 not supported on this chip\n"); 475215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800000E8ull); 476215976Sjmallett} 477215976Sjmallett#else 478215976Sjmallett#define CVMX_L2C_OOB2 (CVMX_ADD_IO_SEG(0x00011800800000E8ull)) 479215976Sjmallett#endif 480215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 481215976Sjmallett#define CVMX_L2C_OOB3 CVMX_L2C_OOB3_FUNC() 482215976Sjmallettstatic inline uint64_t CVMX_L2C_OOB3_FUNC(void) 483215976Sjmallett{ 484215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 485215976Sjmallett cvmx_warn("CVMX_L2C_OOB3 not supported on this chip\n"); 486215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800000F0ull); 487215976Sjmallett} 488215976Sjmallett#else 489215976Sjmallett#define CVMX_L2C_OOB3 (CVMX_ADD_IO_SEG(0x00011800800000F0ull)) 490215976Sjmallett#endif 491215976Sjmallett#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0) 492215976Sjmallett#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1) 493215976Sjmallett#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2) 494215976Sjmallett#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3) 495215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496215976Sjmallett#define CVMX_L2C_PFCTL CVMX_L2C_PFCTL_FUNC() 497215976Sjmallettstatic inline uint64_t CVMX_L2C_PFCTL_FUNC(void) 498215976Sjmallett{ 499215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 500215976Sjmallett cvmx_warn("CVMX_L2C_PFCTL not supported on this chip\n"); 501215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000090ull); 502215976Sjmallett} 503215976Sjmallett#else 504215976Sjmallett#define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull)) 505215976Sjmallett#endif 506215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507215976Sjmallettstatic inline uint64_t CVMX_L2C_PFCX(unsigned long offset) 508215976Sjmallett{ 509215976Sjmallett if (!( 510215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 511215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 512215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 513215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 514215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 515215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) || 516215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 517215976Sjmallett cvmx_warn("CVMX_L2C_PFCX(%lu) is invalid on this chip\n", offset); 518215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8; 519215976Sjmallett} 520215976Sjmallett#else 521215976Sjmallett#define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8) 522215976Sjmallett#endif 523215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 524215976Sjmallett#define CVMX_L2C_PPGRP CVMX_L2C_PPGRP_FUNC() 525215976Sjmallettstatic inline uint64_t CVMX_L2C_PPGRP_FUNC(void) 526215976Sjmallett{ 527215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 528215976Sjmallett cvmx_warn("CVMX_L2C_PPGRP not supported on this chip\n"); 529215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800800000C0ull); 530215976Sjmallett} 531215976Sjmallett#else 532215976Sjmallett#define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull)) 533215976Sjmallett#endif 534215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 535232812Sjmallettstatic inline uint64_t CVMX_L2C_QOS_IOBX(unsigned long offset) 536215976Sjmallett{ 537215976Sjmallett if (!( 538232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) || 539232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) || 540232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) || 541232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 542232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0))))) 543232812Sjmallett cvmx_warn("CVMX_L2C_QOS_IOBX(%lu) is invalid on this chip\n", offset); 544232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080880200ull) + ((offset) & 1) * 8; 545215976Sjmallett} 546215976Sjmallett#else 547232812Sjmallett#define CVMX_L2C_QOS_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080880200ull) + ((offset) & 1) * 8) 548215976Sjmallett#endif 549215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 550215976Sjmallettstatic inline uint64_t CVMX_L2C_QOS_PPX(unsigned long offset) 551215976Sjmallett{ 552215976Sjmallett if (!( 553232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 554232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 555232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 556232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 557232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 558215976Sjmallett cvmx_warn("CVMX_L2C_QOS_PPX(%lu) is invalid on this chip\n", offset); 559232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 31) * 8; 560215976Sjmallett} 561215976Sjmallett#else 562232812Sjmallett#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 31) * 8) 563215976Sjmallett#endif 564215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 565215976Sjmallett#define CVMX_L2C_QOS_WGT CVMX_L2C_QOS_WGT_FUNC() 566215976Sjmallettstatic inline uint64_t CVMX_L2C_QOS_WGT_FUNC(void) 567215976Sjmallett{ 568232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 569215976Sjmallett cvmx_warn("CVMX_L2C_QOS_WGT not supported on this chip\n"); 570215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080800008ull); 571215976Sjmallett} 572215976Sjmallett#else 573215976Sjmallett#define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull)) 574215976Sjmallett#endif 575215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 576232812Sjmallettstatic inline uint64_t CVMX_L2C_RSCX_PFC(unsigned long offset) 577215976Sjmallett{ 578215976Sjmallett if (!( 579232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) || 580232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) || 581232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) || 582232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) || 583232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0))))) 584232812Sjmallett cvmx_warn("CVMX_L2C_RSCX_PFC(%lu) is invalid on this chip\n", offset); 585232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080800410ull) + ((offset) & 3) * 64; 586215976Sjmallett} 587215976Sjmallett#else 588232812Sjmallett#define CVMX_L2C_RSCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800410ull) + ((offset) & 3) * 64) 589215976Sjmallett#endif 590215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 591232812Sjmallettstatic inline uint64_t CVMX_L2C_RSDX_PFC(unsigned long offset) 592215976Sjmallett{ 593215976Sjmallett if (!( 594232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) || 595232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) || 596232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) || 597232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) || 598232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0))))) 599232812Sjmallett cvmx_warn("CVMX_L2C_RSDX_PFC(%lu) is invalid on this chip\n", offset); 600232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080800418ull) + ((offset) & 3) * 64; 601215976Sjmallett} 602215976Sjmallett#else 603232812Sjmallett#define CVMX_L2C_RSDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800418ull) + ((offset) & 3) * 64) 604215976Sjmallett#endif 605215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 606215976Sjmallett#define CVMX_L2C_SPAR0 CVMX_L2C_SPAR0_FUNC() 607215976Sjmallettstatic inline uint64_t CVMX_L2C_SPAR0_FUNC(void) 608215976Sjmallett{ 609215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 610215976Sjmallett cvmx_warn("CVMX_L2C_SPAR0 not supported on this chip\n"); 611215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000068ull); 612215976Sjmallett} 613215976Sjmallett#else 614215976Sjmallett#define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull)) 615215976Sjmallett#endif 616215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617215976Sjmallett#define CVMX_L2C_SPAR1 CVMX_L2C_SPAR1_FUNC() 618215976Sjmallettstatic inline uint64_t CVMX_L2C_SPAR1_FUNC(void) 619215976Sjmallett{ 620215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 621215976Sjmallett cvmx_warn("CVMX_L2C_SPAR1 not supported on this chip\n"); 622215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000070ull); 623215976Sjmallett} 624215976Sjmallett#else 625215976Sjmallett#define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull)) 626215976Sjmallett#endif 627215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628215976Sjmallett#define CVMX_L2C_SPAR2 CVMX_L2C_SPAR2_FUNC() 629215976Sjmallettstatic inline uint64_t CVMX_L2C_SPAR2_FUNC(void) 630215976Sjmallett{ 631215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 632215976Sjmallett cvmx_warn("CVMX_L2C_SPAR2 not supported on this chip\n"); 633215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000078ull); 634215976Sjmallett} 635215976Sjmallett#else 636215976Sjmallett#define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull)) 637215976Sjmallett#endif 638215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 639215976Sjmallett#define CVMX_L2C_SPAR3 CVMX_L2C_SPAR3_FUNC() 640215976Sjmallettstatic inline uint64_t CVMX_L2C_SPAR3_FUNC(void) 641215976Sjmallett{ 642215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 643215976Sjmallett cvmx_warn("CVMX_L2C_SPAR3 not supported on this chip\n"); 644215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000080ull); 645215976Sjmallett} 646215976Sjmallett#else 647215976Sjmallett#define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull)) 648215976Sjmallett#endif 649215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650215976Sjmallett#define CVMX_L2C_SPAR4 CVMX_L2C_SPAR4_FUNC() 651215976Sjmallettstatic inline uint64_t CVMX_L2C_SPAR4_FUNC(void) 652215976Sjmallett{ 653215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 654215976Sjmallett cvmx_warn("CVMX_L2C_SPAR4 not supported on this chip\n"); 655215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000088ull); 656215976Sjmallett} 657215976Sjmallett#else 658215976Sjmallett#define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull)) 659215976Sjmallett#endif 660215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661215976Sjmallettstatic inline uint64_t CVMX_L2C_TADX_ECC0(unsigned long block_id) 662215976Sjmallett{ 663215976Sjmallett if (!( 664232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 665232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 666232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 667232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 668232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 669215976Sjmallett cvmx_warn("CVMX_L2C_TADX_ECC0(%lu) is invalid on this chip\n", block_id); 670232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A00018ull) + ((block_id) & 3) * 0x40000ull; 671215976Sjmallett} 672215976Sjmallett#else 673232812Sjmallett#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull) + ((block_id) & 3) * 0x40000ull) 674215976Sjmallett#endif 675215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 676215976Sjmallettstatic inline uint64_t CVMX_L2C_TADX_ECC1(unsigned long block_id) 677215976Sjmallett{ 678215976Sjmallett if (!( 679232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 680232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 681232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 682232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 683232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 684215976Sjmallett cvmx_warn("CVMX_L2C_TADX_ECC1(%lu) is invalid on this chip\n", block_id); 685232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A00020ull) + ((block_id) & 3) * 0x40000ull; 686215976Sjmallett} 687215976Sjmallett#else 688232812Sjmallett#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull) + ((block_id) & 3) * 0x40000ull) 689215976Sjmallett#endif 690215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 691215976Sjmallettstatic inline uint64_t CVMX_L2C_TADX_IEN(unsigned long block_id) 692215976Sjmallett{ 693215976Sjmallett if (!( 694232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 695232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 696232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 697232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 698232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 699215976Sjmallett cvmx_warn("CVMX_L2C_TADX_IEN(%lu) is invalid on this chip\n", block_id); 700232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A00000ull) + ((block_id) & 3) * 0x40000ull; 701215976Sjmallett} 702215976Sjmallett#else 703232812Sjmallett#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull) + ((block_id) & 3) * 0x40000ull) 704215976Sjmallett#endif 705215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 706215976Sjmallettstatic inline uint64_t CVMX_L2C_TADX_INT(unsigned long block_id) 707215976Sjmallett{ 708215976Sjmallett if (!( 709232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 710232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 711232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 712232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 713232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 714215976Sjmallett cvmx_warn("CVMX_L2C_TADX_INT(%lu) is invalid on this chip\n", block_id); 715232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A00028ull) + ((block_id) & 3) * 0x40000ull; 716215976Sjmallett} 717215976Sjmallett#else 718232812Sjmallett#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull) + ((block_id) & 3) * 0x40000ull) 719215976Sjmallett#endif 720215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 721215976Sjmallettstatic inline uint64_t CVMX_L2C_TADX_PFC0(unsigned long block_id) 722215976Sjmallett{ 723215976Sjmallett if (!( 724232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 725232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 726232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 727232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 728232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 729215976Sjmallett cvmx_warn("CVMX_L2C_TADX_PFC0(%lu) is invalid on this chip\n", block_id); 730232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A00400ull) + ((block_id) & 3) * 0x40000ull; 731215976Sjmallett} 732215976Sjmallett#else 733232812Sjmallett#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + ((block_id) & 3) * 0x40000ull) 734215976Sjmallett#endif 735215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 736215976Sjmallettstatic inline uint64_t CVMX_L2C_TADX_PFC1(unsigned long block_id) 737215976Sjmallett{ 738215976Sjmallett if (!( 739232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 740232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 741232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 742232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 743232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 744215976Sjmallett cvmx_warn("CVMX_L2C_TADX_PFC1(%lu) is invalid on this chip\n", block_id); 745232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A00408ull) + ((block_id) & 3) * 0x40000ull; 746215976Sjmallett} 747215976Sjmallett#else 748232812Sjmallett#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + ((block_id) & 3) * 0x40000ull) 749215976Sjmallett#endif 750215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 751215976Sjmallettstatic inline uint64_t CVMX_L2C_TADX_PFC2(unsigned long block_id) 752215976Sjmallett{ 753215976Sjmallett if (!( 754232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 755232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 756232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 757232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 758232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 759215976Sjmallett cvmx_warn("CVMX_L2C_TADX_PFC2(%lu) is invalid on this chip\n", block_id); 760232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A00410ull) + ((block_id) & 3) * 0x40000ull; 761215976Sjmallett} 762215976Sjmallett#else 763232812Sjmallett#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + ((block_id) & 3) * 0x40000ull) 764215976Sjmallett#endif 765215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 766215976Sjmallettstatic inline uint64_t CVMX_L2C_TADX_PFC3(unsigned long block_id) 767215976Sjmallett{ 768215976Sjmallett if (!( 769232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 770232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 771232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 772232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 773232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 774215976Sjmallett cvmx_warn("CVMX_L2C_TADX_PFC3(%lu) is invalid on this chip\n", block_id); 775232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A00418ull) + ((block_id) & 3) * 0x40000ull; 776215976Sjmallett} 777215976Sjmallett#else 778232812Sjmallett#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + ((block_id) & 3) * 0x40000ull) 779215976Sjmallett#endif 780215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 781215976Sjmallettstatic inline uint64_t CVMX_L2C_TADX_PRF(unsigned long block_id) 782215976Sjmallett{ 783215976Sjmallett if (!( 784232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 785232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 786232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 787232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 788232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 789215976Sjmallett cvmx_warn("CVMX_L2C_TADX_PRF(%lu) is invalid on this chip\n", block_id); 790232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A00008ull) + ((block_id) & 3) * 0x40000ull; 791215976Sjmallett} 792215976Sjmallett#else 793232812Sjmallett#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull) + ((block_id) & 3) * 0x40000ull) 794215976Sjmallett#endif 795215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 796215976Sjmallettstatic inline uint64_t CVMX_L2C_TADX_TAG(unsigned long block_id) 797215976Sjmallett{ 798215976Sjmallett if (!( 799232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 800232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 801232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 802232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 803232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 804215976Sjmallett cvmx_warn("CVMX_L2C_TADX_TAG(%lu) is invalid on this chip\n", block_id); 805232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080A00010ull) + ((block_id) & 3) * 0x40000ull; 806215976Sjmallett} 807215976Sjmallett#else 808232812Sjmallett#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull) + ((block_id) & 3) * 0x40000ull) 809215976Sjmallett#endif 810215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 811215976Sjmallett#define CVMX_L2C_VER_ID CVMX_L2C_VER_ID_FUNC() 812215976Sjmallettstatic inline uint64_t CVMX_L2C_VER_ID_FUNC(void) 813215976Sjmallett{ 814232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 815215976Sjmallett cvmx_warn("CVMX_L2C_VER_ID not supported on this chip\n"); 816215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800808007E0ull); 817215976Sjmallett} 818215976Sjmallett#else 819215976Sjmallett#define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull)) 820215976Sjmallett#endif 821215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 822215976Sjmallett#define CVMX_L2C_VER_IOB CVMX_L2C_VER_IOB_FUNC() 823215976Sjmallettstatic inline uint64_t CVMX_L2C_VER_IOB_FUNC(void) 824215976Sjmallett{ 825232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 826215976Sjmallett cvmx_warn("CVMX_L2C_VER_IOB not supported on this chip\n"); 827215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800808007F0ull); 828215976Sjmallett} 829215976Sjmallett#else 830215976Sjmallett#define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull)) 831215976Sjmallett#endif 832215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 833215976Sjmallett#define CVMX_L2C_VER_MSC CVMX_L2C_VER_MSC_FUNC() 834215976Sjmallettstatic inline uint64_t CVMX_L2C_VER_MSC_FUNC(void) 835215976Sjmallett{ 836232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 837215976Sjmallett cvmx_warn("CVMX_L2C_VER_MSC not supported on this chip\n"); 838215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800808007D0ull); 839215976Sjmallett} 840215976Sjmallett#else 841215976Sjmallett#define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull)) 842215976Sjmallett#endif 843215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 844215976Sjmallett#define CVMX_L2C_VER_PP CVMX_L2C_VER_PP_FUNC() 845215976Sjmallettstatic inline uint64_t CVMX_L2C_VER_PP_FUNC(void) 846215976Sjmallett{ 847232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 848215976Sjmallett cvmx_warn("CVMX_L2C_VER_PP not supported on this chip\n"); 849215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800808007E8ull); 850215976Sjmallett} 851215976Sjmallett#else 852215976Sjmallett#define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull)) 853215976Sjmallett#endif 854215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 855232812Sjmallettstatic inline uint64_t CVMX_L2C_VIRTID_IOBX(unsigned long offset) 856215976Sjmallett{ 857215976Sjmallett if (!( 858232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) || 859232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) || 860232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) || 861232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 862232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0))))) 863232812Sjmallett cvmx_warn("CVMX_L2C_VIRTID_IOBX(%lu) is invalid on this chip\n", offset); 864232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800808C0200ull) + ((offset) & 1) * 8; 865215976Sjmallett} 866215976Sjmallett#else 867232812Sjmallett#define CVMX_L2C_VIRTID_IOBX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0200ull) + ((offset) & 1) * 8) 868215976Sjmallett#endif 869215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 870215976Sjmallettstatic inline uint64_t CVMX_L2C_VIRTID_PPX(unsigned long offset) 871215976Sjmallett{ 872215976Sjmallett if (!( 873232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 874232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 875232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 876232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 877232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 878215976Sjmallett cvmx_warn("CVMX_L2C_VIRTID_PPX(%lu) is invalid on this chip\n", offset); 879232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 31) * 8; 880215976Sjmallett} 881215976Sjmallett#else 882232812Sjmallett#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 31) * 8) 883215976Sjmallett#endif 884215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 885215976Sjmallett#define CVMX_L2C_VRT_CTL CVMX_L2C_VRT_CTL_FUNC() 886215976Sjmallettstatic inline uint64_t CVMX_L2C_VRT_CTL_FUNC(void) 887215976Sjmallett{ 888232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 889215976Sjmallett cvmx_warn("CVMX_L2C_VRT_CTL not supported on this chip\n"); 890215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080800010ull); 891215976Sjmallett} 892215976Sjmallett#else 893215976Sjmallett#define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull)) 894215976Sjmallett#endif 895215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 896215976Sjmallettstatic inline uint64_t CVMX_L2C_VRT_MEMX(unsigned long offset) 897215976Sjmallett{ 898215976Sjmallett if (!( 899232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1023))) || 900232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1023))) || 901232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1023))) || 902232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1023))) || 903232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1023))))) 904215976Sjmallett cvmx_warn("CVMX_L2C_VRT_MEMX(%lu) is invalid on this chip\n", offset); 905215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8; 906215976Sjmallett} 907215976Sjmallett#else 908215976Sjmallett#define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8) 909215976Sjmallett#endif 910215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 911232812Sjmallettstatic inline uint64_t CVMX_L2C_WPAR_IOBX(unsigned long offset) 912215976Sjmallett{ 913215976Sjmallett if (!( 914232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) || 915232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) || 916232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) || 917232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 918232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0))))) 919232812Sjmallett cvmx_warn("CVMX_L2C_WPAR_IOBX(%lu) is invalid on this chip\n", offset); 920232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080840200ull) + ((offset) & 1) * 8; 921215976Sjmallett} 922215976Sjmallett#else 923232812Sjmallett#define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull) + ((offset) & 1) * 8) 924215976Sjmallett#endif 925215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 926215976Sjmallettstatic inline uint64_t CVMX_L2C_WPAR_PPX(unsigned long offset) 927215976Sjmallett{ 928215976Sjmallett if (!( 929232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 930232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 931232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 932232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 933232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 934215976Sjmallett cvmx_warn("CVMX_L2C_WPAR_PPX(%lu) is invalid on this chip\n", offset); 935232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 31) * 8; 936215976Sjmallett} 937215976Sjmallett#else 938232812Sjmallett#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 31) * 8) 939215976Sjmallett#endif 940215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 941232812Sjmallettstatic inline uint64_t CVMX_L2C_XMCX_PFC(unsigned long offset) 942215976Sjmallett{ 943215976Sjmallett if (!( 944232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) || 945232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) || 946232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) || 947232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) || 948232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0))))) 949232812Sjmallett cvmx_warn("CVMX_L2C_XMCX_PFC(%lu) is invalid on this chip\n", offset); 950232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080800400ull) + ((offset) & 3) * 64; 951215976Sjmallett} 952215976Sjmallett#else 953232812Sjmallett#define CVMX_L2C_XMCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800400ull) + ((offset) & 3) * 64) 954215976Sjmallett#endif 955215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 956215976Sjmallett#define CVMX_L2C_XMC_CMD CVMX_L2C_XMC_CMD_FUNC() 957215976Sjmallettstatic inline uint64_t CVMX_L2C_XMC_CMD_FUNC(void) 958215976Sjmallett{ 959232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 960215976Sjmallett cvmx_warn("CVMX_L2C_XMC_CMD not supported on this chip\n"); 961215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080800028ull); 962215976Sjmallett} 963215976Sjmallett#else 964215976Sjmallett#define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull)) 965215976Sjmallett#endif 966215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 967232812Sjmallettstatic inline uint64_t CVMX_L2C_XMDX_PFC(unsigned long offset) 968215976Sjmallett{ 969215976Sjmallett if (!( 970232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) || 971232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) || 972232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) || 973232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) || 974232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0))))) 975232812Sjmallett cvmx_warn("CVMX_L2C_XMDX_PFC(%lu) is invalid on this chip\n", offset); 976232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180080800408ull) + ((offset) & 3) * 64; 977215976Sjmallett} 978215976Sjmallett#else 979232812Sjmallett#define CVMX_L2C_XMDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800408ull) + ((offset) & 3) * 64) 980215976Sjmallett#endif 981215976Sjmallett 982215976Sjmallett/** 983215976Sjmallett * cvmx_l2c_big_ctl 984215976Sjmallett * 985215976Sjmallett * L2C_BIG_CTL = L2C Big memory control register 986215976Sjmallett * 987215976Sjmallett * 988215976Sjmallett * Notes: 989215976Sjmallett * (1) BIGRD interrupts can occur during normal operation as the PP's are allowed to prefetch to 990215976Sjmallett * non-existent memory locations. Therefore, BIGRD is for informational purposes only. 991215976Sjmallett * 992215976Sjmallett * (2) When HOLEWR/BIGWR blocks a store L2C_VER_ID, L2C_VER_PP, L2C_VER_IOB, and L2C_VER_MSC will be 993215976Sjmallett * loaded just like a store which is blocked by VRTWR. Additionally, L2C_ERR_XMC will be loaded. 994215976Sjmallett */ 995232812Sjmallettunion cvmx_l2c_big_ctl { 996215976Sjmallett uint64_t u64; 997232812Sjmallett struct cvmx_l2c_big_ctl_s { 998232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 999215976Sjmallett uint64_t reserved_8_63 : 56; 1000215976Sjmallett uint64_t maxdram : 4; /**< Amount of configured DRAM 1001215976Sjmallett 0 = reserved 1002215976Sjmallett 1 = 512MB 1003215976Sjmallett 2 = 1GB 1004215976Sjmallett 3 = 2GB 1005215976Sjmallett 4 = 4GB 1006215976Sjmallett 5 = 8GB 1007215976Sjmallett 6 = 16GB 1008215976Sjmallett 7 = 32GB 1009215976Sjmallett 8 = 64GB (**reserved in 63xx**) 1010215976Sjmallett 9 = 128GB (**reserved in 63xx**) 1011215976Sjmallett 10-15 reserved 1012215976Sjmallett Violations of this limit causes 1013215976Sjmallett L2C to set L2C_INT_REG[BIGRD/BIGWR]. */ 1014215976Sjmallett uint64_t reserved_1_3 : 3; 1015215976Sjmallett uint64_t disable : 1; /**< When set, disables the BIGWR/BIGRD logic completely 1016215976Sjmallett and reverts HOLEWR to 63xx pass 1.x behavior. 1017215976Sjmallett When clear, BIGWR and HOLEWR block stores in the same 1018215976Sjmallett same manner as the VRT logic, and BIGRD is reported. */ 1019215976Sjmallett#else 1020215976Sjmallett uint64_t disable : 1; 1021215976Sjmallett uint64_t reserved_1_3 : 3; 1022215976Sjmallett uint64_t maxdram : 4; 1023215976Sjmallett uint64_t reserved_8_63 : 56; 1024215976Sjmallett#endif 1025215976Sjmallett } s; 1026232812Sjmallett struct cvmx_l2c_big_ctl_s cn61xx; 1027215976Sjmallett struct cvmx_l2c_big_ctl_s cn63xx; 1028232812Sjmallett struct cvmx_l2c_big_ctl_s cn66xx; 1029232812Sjmallett struct cvmx_l2c_big_ctl_s cn68xx; 1030232812Sjmallett struct cvmx_l2c_big_ctl_s cn68xxp1; 1031232812Sjmallett struct cvmx_l2c_big_ctl_s cnf71xx; 1032215976Sjmallett}; 1033215976Sjmalletttypedef union cvmx_l2c_big_ctl cvmx_l2c_big_ctl_t; 1034215976Sjmallett 1035215976Sjmallett/** 1036215976Sjmallett * cvmx_l2c_bst 1037215976Sjmallett * 1038215976Sjmallett * L2C_BST = L2C BIST Status 1039215976Sjmallett * 1040215976Sjmallett */ 1041232812Sjmallettunion cvmx_l2c_bst { 1042215976Sjmallett uint64_t u64; 1043232812Sjmallett struct cvmx_l2c_bst_s { 1044232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1045232812Sjmallett uint64_t dutfl : 32; /**< BIST failure status for PP0-3 DUT */ 1046232812Sjmallett uint64_t rbffl : 4; /**< BIST failure status for RBF0-3 */ 1047232812Sjmallett uint64_t xbffl : 4; /**< BIST failure status for XBF0-3 */ 1048232812Sjmallett uint64_t tdpfl : 4; /**< BIST failure status for TDP0-3 */ 1049232812Sjmallett uint64_t ioccmdfl : 4; /**< BIST failure status for IOCCMD */ 1050232812Sjmallett uint64_t iocdatfl : 4; /**< BIST failure status for IOCDAT */ 1051232812Sjmallett uint64_t dutresfl : 4; /**< BIST failure status for DUTRES */ 1052232812Sjmallett uint64_t vrtfl : 4; /**< BIST failure status for VRT0 */ 1053232812Sjmallett uint64_t tdffl : 4; /**< BIST failure status for TDF0 */ 1054232812Sjmallett#else 1055232812Sjmallett uint64_t tdffl : 4; 1056232812Sjmallett uint64_t vrtfl : 4; 1057232812Sjmallett uint64_t dutresfl : 4; 1058232812Sjmallett uint64_t iocdatfl : 4; 1059232812Sjmallett uint64_t ioccmdfl : 4; 1060232812Sjmallett uint64_t tdpfl : 4; 1061232812Sjmallett uint64_t xbffl : 4; 1062232812Sjmallett uint64_t rbffl : 4; 1063232812Sjmallett uint64_t dutfl : 32; 1064232812Sjmallett#endif 1065232812Sjmallett } s; 1066232812Sjmallett struct cvmx_l2c_bst_cn61xx { 1067232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1068232812Sjmallett uint64_t reserved_36_63 : 28; 1069232812Sjmallett uint64_t dutfl : 4; /**< BIST failure status for PP0-3 DUT */ 1070232812Sjmallett uint64_t reserved_17_31 : 15; 1071232812Sjmallett uint64_t ioccmdfl : 1; /**< BIST failure status for IOCCMD */ 1072232812Sjmallett uint64_t reserved_13_15 : 3; 1073232812Sjmallett uint64_t iocdatfl : 1; /**< BIST failure status for IOCDAT */ 1074232812Sjmallett uint64_t reserved_9_11 : 3; 1075232812Sjmallett uint64_t dutresfl : 1; /**< BIST failure status for DUTRES */ 1076232812Sjmallett uint64_t reserved_5_7 : 3; 1077232812Sjmallett uint64_t vrtfl : 1; /**< BIST failure status for VRT0 */ 1078232812Sjmallett uint64_t reserved_1_3 : 3; 1079232812Sjmallett uint64_t tdffl : 1; /**< BIST failure status for TDF0 */ 1080232812Sjmallett#else 1081232812Sjmallett uint64_t tdffl : 1; 1082232812Sjmallett uint64_t reserved_1_3 : 3; 1083232812Sjmallett uint64_t vrtfl : 1; 1084232812Sjmallett uint64_t reserved_5_7 : 3; 1085232812Sjmallett uint64_t dutresfl : 1; 1086232812Sjmallett uint64_t reserved_9_11 : 3; 1087232812Sjmallett uint64_t iocdatfl : 1; 1088232812Sjmallett uint64_t reserved_13_15 : 3; 1089232812Sjmallett uint64_t ioccmdfl : 1; 1090232812Sjmallett uint64_t reserved_17_31 : 15; 1091232812Sjmallett uint64_t dutfl : 4; 1092232812Sjmallett uint64_t reserved_36_63 : 28; 1093232812Sjmallett#endif 1094232812Sjmallett } cn61xx; 1095232812Sjmallett struct cvmx_l2c_bst_cn63xx { 1096232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1097215976Sjmallett uint64_t reserved_38_63 : 26; 1098215976Sjmallett uint64_t dutfl : 6; /**< BIST failure status for PP0-5 DUT */ 1099215976Sjmallett uint64_t reserved_17_31 : 15; 1100215976Sjmallett uint64_t ioccmdfl : 1; /**< BIST failure status for IOCCMD */ 1101215976Sjmallett uint64_t reserved_13_15 : 3; 1102215976Sjmallett uint64_t iocdatfl : 1; /**< BIST failure status for IOCDAT */ 1103215976Sjmallett uint64_t reserved_9_11 : 3; 1104215976Sjmallett uint64_t dutresfl : 1; /**< BIST failure status for DUTRES */ 1105215976Sjmallett uint64_t reserved_5_7 : 3; 1106215976Sjmallett uint64_t vrtfl : 1; /**< BIST failure status for VRT0 */ 1107215976Sjmallett uint64_t reserved_1_3 : 3; 1108215976Sjmallett uint64_t tdffl : 1; /**< BIST failure status for TDF0 */ 1109215976Sjmallett#else 1110215976Sjmallett uint64_t tdffl : 1; 1111215976Sjmallett uint64_t reserved_1_3 : 3; 1112215976Sjmallett uint64_t vrtfl : 1; 1113215976Sjmallett uint64_t reserved_5_7 : 3; 1114215976Sjmallett uint64_t dutresfl : 1; 1115215976Sjmallett uint64_t reserved_9_11 : 3; 1116215976Sjmallett uint64_t iocdatfl : 1; 1117215976Sjmallett uint64_t reserved_13_15 : 3; 1118215976Sjmallett uint64_t ioccmdfl : 1; 1119215976Sjmallett uint64_t reserved_17_31 : 15; 1120215976Sjmallett uint64_t dutfl : 6; 1121215976Sjmallett uint64_t reserved_38_63 : 26; 1122215976Sjmallett#endif 1123232812Sjmallett } cn63xx; 1124232812Sjmallett struct cvmx_l2c_bst_cn63xx cn63xxp1; 1125232812Sjmallett struct cvmx_l2c_bst_cn66xx { 1126232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1127232812Sjmallett uint64_t reserved_42_63 : 22; 1128232812Sjmallett uint64_t dutfl : 10; /**< BIST failure status for PP0-9 DUT */ 1129232812Sjmallett uint64_t reserved_17_31 : 15; 1130232812Sjmallett uint64_t ioccmdfl : 1; /**< BIST failure status for IOCCMD */ 1131232812Sjmallett uint64_t reserved_13_15 : 3; 1132232812Sjmallett uint64_t iocdatfl : 1; /**< BIST failure status for IOCDAT */ 1133232812Sjmallett uint64_t reserved_9_11 : 3; 1134232812Sjmallett uint64_t dutresfl : 1; /**< BIST failure status for DUTRES */ 1135232812Sjmallett uint64_t reserved_5_7 : 3; 1136232812Sjmallett uint64_t vrtfl : 1; /**< BIST failure status for VRT0 */ 1137232812Sjmallett uint64_t reserved_1_3 : 3; 1138232812Sjmallett uint64_t tdffl : 1; /**< BIST failure status for TDF0 */ 1139232812Sjmallett#else 1140232812Sjmallett uint64_t tdffl : 1; 1141232812Sjmallett uint64_t reserved_1_3 : 3; 1142232812Sjmallett uint64_t vrtfl : 1; 1143232812Sjmallett uint64_t reserved_5_7 : 3; 1144232812Sjmallett uint64_t dutresfl : 1; 1145232812Sjmallett uint64_t reserved_9_11 : 3; 1146232812Sjmallett uint64_t iocdatfl : 1; 1147232812Sjmallett uint64_t reserved_13_15 : 3; 1148232812Sjmallett uint64_t ioccmdfl : 1; 1149232812Sjmallett uint64_t reserved_17_31 : 15; 1150232812Sjmallett uint64_t dutfl : 10; 1151232812Sjmallett uint64_t reserved_42_63 : 22; 1152232812Sjmallett#endif 1153232812Sjmallett } cn66xx; 1154232812Sjmallett struct cvmx_l2c_bst_s cn68xx; 1155232812Sjmallett struct cvmx_l2c_bst_s cn68xxp1; 1156232812Sjmallett struct cvmx_l2c_bst_cn61xx cnf71xx; 1157215976Sjmallett}; 1158215976Sjmalletttypedef union cvmx_l2c_bst cvmx_l2c_bst_t; 1159215976Sjmallett 1160215976Sjmallett/** 1161215976Sjmallett * cvmx_l2c_bst0 1162215976Sjmallett * 1163215976Sjmallett * L2C_BST0 = L2C BIST 0 CTL/STAT 1164215976Sjmallett * 1165215976Sjmallett */ 1166232812Sjmallettunion cvmx_l2c_bst0 { 1167215976Sjmallett uint64_t u64; 1168232812Sjmallett struct cvmx_l2c_bst0_s { 1169232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1170215976Sjmallett uint64_t reserved_24_63 : 40; 1171215976Sjmallett uint64_t dtbnk : 1; /**< DuTag Bank# 1172215976Sjmallett When DT=1(BAD), this field provides additional information 1173215976Sjmallett about which DuTag Bank (0/1) failed. */ 1174215976Sjmallett uint64_t wlb_msk : 4; /**< Bist Results for WLB-MSK RAM [DP0-3] 1175215976Sjmallett - 0: GOOD (or bist in progress/never run) 1176215976Sjmallett - 1: BAD */ 1177215976Sjmallett uint64_t dtcnt : 13; /**< DuTag BiST Counter (used to help isolate the failure) 1178215976Sjmallett [12]: i (0=FORWARD/1=REVERSE pass) 1179215976Sjmallett [11:10]: j (Pattern# 1 of 4) 1180215976Sjmallett [9:4]: k (DT Index 1 of 64) 1181215976Sjmallett [3:0]: l (DT# 1 of 16 DTs) */ 1182215976Sjmallett uint64_t dt : 1; /**< Bist Results for DuTAG RAM(s) 1183215976Sjmallett - 0: GOOD (or bist in progress/never run) 1184215976Sjmallett - 1: BAD */ 1185215976Sjmallett uint64_t stin_msk : 1; /**< Bist Results for STIN-MSK RAM 1186215976Sjmallett - 0: GOOD (or bist in progress/never run) 1187215976Sjmallett - 1: BAD */ 1188215976Sjmallett uint64_t wlb_dat : 4; /**< Bist Results for WLB-DAT RAM [DP0-3] 1189215976Sjmallett - 0: GOOD (or bist in progress/never run) 1190215976Sjmallett - 1: BAD */ 1191215976Sjmallett#else 1192215976Sjmallett uint64_t wlb_dat : 4; 1193215976Sjmallett uint64_t stin_msk : 1; 1194215976Sjmallett uint64_t dt : 1; 1195215976Sjmallett uint64_t dtcnt : 13; 1196215976Sjmallett uint64_t wlb_msk : 4; 1197215976Sjmallett uint64_t dtbnk : 1; 1198215976Sjmallett uint64_t reserved_24_63 : 40; 1199215976Sjmallett#endif 1200215976Sjmallett } s; 1201232812Sjmallett struct cvmx_l2c_bst0_cn30xx { 1202232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1203215976Sjmallett uint64_t reserved_23_63 : 41; 1204215976Sjmallett uint64_t wlb_msk : 4; /**< Bist Results for WLB-MSK RAM [DP0-3] 1205215976Sjmallett - 0: GOOD (or bist in progress/never run) 1206215976Sjmallett - 1: BAD */ 1207215976Sjmallett uint64_t reserved_15_18 : 4; 1208215976Sjmallett uint64_t dtcnt : 9; /**< DuTag BiST Counter (used to help isolate the failure) 1209215976Sjmallett [8]: i (0=FORWARD/1=REVERSE pass) 1210215976Sjmallett [7:6]: j (Pattern# 1 of 4) 1211215976Sjmallett [5:0]: k (DT Index 1 of 64) */ 1212215976Sjmallett uint64_t dt : 1; /**< Bist Results for DuTAG RAM(s) 1213215976Sjmallett - 0: GOOD (or bist in progress/never run) 1214215976Sjmallett - 1: BAD */ 1215215976Sjmallett uint64_t reserved_4_4 : 1; 1216215976Sjmallett uint64_t wlb_dat : 4; /**< Bist Results for WLB-DAT RAM [DP0-3] 1217215976Sjmallett - 0: GOOD (or bist in progress/never run) 1218215976Sjmallett - 1: BAD */ 1219215976Sjmallett#else 1220215976Sjmallett uint64_t wlb_dat : 4; 1221215976Sjmallett uint64_t reserved_4_4 : 1; 1222215976Sjmallett uint64_t dt : 1; 1223215976Sjmallett uint64_t dtcnt : 9; 1224215976Sjmallett uint64_t reserved_15_18 : 4; 1225215976Sjmallett uint64_t wlb_msk : 4; 1226215976Sjmallett uint64_t reserved_23_63 : 41; 1227215976Sjmallett#endif 1228215976Sjmallett } cn30xx; 1229232812Sjmallett struct cvmx_l2c_bst0_cn31xx { 1230232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1231215976Sjmallett uint64_t reserved_23_63 : 41; 1232215976Sjmallett uint64_t wlb_msk : 4; /**< Bist Results for WLB-MSK RAM [DP0-3] 1233215976Sjmallett - 0: GOOD (or bist in progress/never run) 1234215976Sjmallett - 1: BAD */ 1235215976Sjmallett uint64_t reserved_16_18 : 3; 1236215976Sjmallett uint64_t dtcnt : 10; /**< DuTag BiST Counter (used to help isolate the failure) 1237215976Sjmallett [9]: i (0=FORWARD/1=REVERSE pass) 1238215976Sjmallett [8:7]: j (Pattern# 1 of 4) 1239215976Sjmallett [6:1]: k (DT Index 1 of 64) 1240215976Sjmallett [0]: l (DT# 1 of 2 DTs) */ 1241215976Sjmallett uint64_t dt : 1; /**< Bist Results for DuTAG RAM(s) 1242215976Sjmallett - 0: GOOD (or bist in progress/never run) 1243215976Sjmallett - 1: BAD */ 1244215976Sjmallett uint64_t stin_msk : 1; /**< Bist Results for STIN-MSK RAM 1245215976Sjmallett - 0: GOOD (or bist in progress/never run) 1246215976Sjmallett - 1: BAD */ 1247215976Sjmallett uint64_t wlb_dat : 4; /**< Bist Results for WLB-DAT RAM [DP0-3] 1248215976Sjmallett - 0: GOOD (or bist in progress/never run) 1249215976Sjmallett - 1: BAD */ 1250215976Sjmallett#else 1251215976Sjmallett uint64_t wlb_dat : 4; 1252215976Sjmallett uint64_t stin_msk : 1; 1253215976Sjmallett uint64_t dt : 1; 1254215976Sjmallett uint64_t dtcnt : 10; 1255215976Sjmallett uint64_t reserved_16_18 : 3; 1256215976Sjmallett uint64_t wlb_msk : 4; 1257215976Sjmallett uint64_t reserved_23_63 : 41; 1258215976Sjmallett#endif 1259215976Sjmallett } cn31xx; 1260232812Sjmallett struct cvmx_l2c_bst0_cn38xx { 1261232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1262215976Sjmallett uint64_t reserved_19_63 : 45; 1263215976Sjmallett uint64_t dtcnt : 13; /**< DuTag BiST Counter (used to help isolate the failure) 1264215976Sjmallett [12]: i (0=FORWARD/1=REVERSE pass) 1265215976Sjmallett [11:10]: j (Pattern# 1 of 4) 1266215976Sjmallett [9:4]: k (DT Index 1 of 64) 1267215976Sjmallett [3:0]: l (DT# 1 of 16 DTs) */ 1268215976Sjmallett uint64_t dt : 1; /**< Bist Results for DuTAG RAM(s) 1269215976Sjmallett - 0: GOOD (or bist in progress/never run) 1270215976Sjmallett - 1: BAD */ 1271215976Sjmallett uint64_t stin_msk : 1; /**< Bist Results for STIN-MSK RAM 1272215976Sjmallett - 0: GOOD (or bist in progress/never run) 1273215976Sjmallett - 1: BAD */ 1274215976Sjmallett uint64_t wlb_dat : 4; /**< Bist Results for WLB-DAT RAM [DP0-3] 1275215976Sjmallett - 0: GOOD (or bist in progress/never run) 1276215976Sjmallett - 1: BAD */ 1277215976Sjmallett#else 1278215976Sjmallett uint64_t wlb_dat : 4; 1279215976Sjmallett uint64_t stin_msk : 1; 1280215976Sjmallett uint64_t dt : 1; 1281215976Sjmallett uint64_t dtcnt : 13; 1282215976Sjmallett uint64_t reserved_19_63 : 45; 1283215976Sjmallett#endif 1284215976Sjmallett } cn38xx; 1285215976Sjmallett struct cvmx_l2c_bst0_cn38xx cn38xxp2; 1286232812Sjmallett struct cvmx_l2c_bst0_cn50xx { 1287232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1288215976Sjmallett uint64_t reserved_24_63 : 40; 1289215976Sjmallett uint64_t dtbnk : 1; /**< DuTag Bank# 1290215976Sjmallett When DT=1(BAD), this field provides additional information 1291215976Sjmallett about which DuTag Bank (0/1) failed. */ 1292215976Sjmallett uint64_t wlb_msk : 4; /**< Bist Results for WLB-MSK RAM [DP0-3] 1293215976Sjmallett - 0: GOOD (or bist in progress/never run) 1294215976Sjmallett - 1: BAD */ 1295215976Sjmallett uint64_t reserved_16_18 : 3; 1296215976Sjmallett uint64_t dtcnt : 10; /**< DuTag BiST Counter (used to help isolate the failure) 1297215976Sjmallett [9]: i (0=FORWARD/1=REVERSE pass) 1298215976Sjmallett [8:7]: j (Pattern# 1 of 4) 1299215976Sjmallett [6:1]: k (DT Index 1 of 64) 1300215976Sjmallett [0]: l (DT# 1 of 2 DTs) */ 1301215976Sjmallett uint64_t dt : 1; /**< Bist Results for DuTAG RAM(s) 1302215976Sjmallett - 0: GOOD (or bist in progress/never run) 1303215976Sjmallett - 1: BAD */ 1304215976Sjmallett uint64_t stin_msk : 1; /**< Bist Results for STIN-MSK RAM 1305215976Sjmallett - 0: GOOD (or bist in progress/never run) 1306215976Sjmallett - 1: BAD */ 1307215976Sjmallett uint64_t wlb_dat : 4; /**< Bist Results for WLB-DAT RAM [DP0-3] 1308215976Sjmallett - 0: GOOD (or bist in progress/never run) 1309215976Sjmallett - 1: BAD */ 1310215976Sjmallett#else 1311215976Sjmallett uint64_t wlb_dat : 4; 1312215976Sjmallett uint64_t stin_msk : 1; 1313215976Sjmallett uint64_t dt : 1; 1314215976Sjmallett uint64_t dtcnt : 10; 1315215976Sjmallett uint64_t reserved_16_18 : 3; 1316215976Sjmallett uint64_t wlb_msk : 4; 1317215976Sjmallett uint64_t dtbnk : 1; 1318215976Sjmallett uint64_t reserved_24_63 : 40; 1319215976Sjmallett#endif 1320215976Sjmallett } cn50xx; 1321215976Sjmallett struct cvmx_l2c_bst0_cn50xx cn52xx; 1322215976Sjmallett struct cvmx_l2c_bst0_cn50xx cn52xxp1; 1323215976Sjmallett struct cvmx_l2c_bst0_s cn56xx; 1324215976Sjmallett struct cvmx_l2c_bst0_s cn56xxp1; 1325215976Sjmallett struct cvmx_l2c_bst0_s cn58xx; 1326215976Sjmallett struct cvmx_l2c_bst0_s cn58xxp1; 1327215976Sjmallett}; 1328215976Sjmalletttypedef union cvmx_l2c_bst0 cvmx_l2c_bst0_t; 1329215976Sjmallett 1330215976Sjmallett/** 1331215976Sjmallett * cvmx_l2c_bst1 1332215976Sjmallett * 1333215976Sjmallett * L2C_BST1 = L2C BIST 1 CTL/STAT 1334215976Sjmallett * 1335215976Sjmallett */ 1336232812Sjmallettunion cvmx_l2c_bst1 { 1337215976Sjmallett uint64_t u64; 1338232812Sjmallett struct cvmx_l2c_bst1_s { 1339232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1340215976Sjmallett uint64_t reserved_9_63 : 55; 1341215976Sjmallett uint64_t l2t : 9; /**< Bist Results for L2T (USE+8SET RAMs) 1342215976Sjmallett - 0: GOOD (or bist in progress/never run) 1343215976Sjmallett - 1: BAD */ 1344215976Sjmallett#else 1345215976Sjmallett uint64_t l2t : 9; 1346215976Sjmallett uint64_t reserved_9_63 : 55; 1347215976Sjmallett#endif 1348215976Sjmallett } s; 1349232812Sjmallett struct cvmx_l2c_bst1_cn30xx { 1350232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1351215976Sjmallett uint64_t reserved_16_63 : 48; 1352215976Sjmallett uint64_t vwdf : 4; /**< Bist Results for VWDF RAMs 1353215976Sjmallett - 0: GOOD (or bist in progress/never run) 1354215976Sjmallett - 1: BAD */ 1355215976Sjmallett uint64_t lrf : 2; /**< Bist Results for LRF RAMs (PLC+ILC) 1356215976Sjmallett - 0: GOOD (or bist in progress/never run) 1357215976Sjmallett - 1: BAD */ 1358215976Sjmallett uint64_t vab_vwcf : 1; /**< Bist Results for VAB VWCF_MEM 1359215976Sjmallett - 0: GOOD (or bist in progress/never run) 1360215976Sjmallett - 1: BAD */ 1361215976Sjmallett uint64_t reserved_5_8 : 4; 1362215976Sjmallett uint64_t l2t : 5; /**< Bist Results for L2T (USE+4SET RAMs) 1363215976Sjmallett - 0: GOOD (or bist in progress/never run) 1364215976Sjmallett - 1: BAD */ 1365215976Sjmallett#else 1366215976Sjmallett uint64_t l2t : 5; 1367215976Sjmallett uint64_t reserved_5_8 : 4; 1368215976Sjmallett uint64_t vab_vwcf : 1; 1369215976Sjmallett uint64_t lrf : 2; 1370215976Sjmallett uint64_t vwdf : 4; 1371215976Sjmallett uint64_t reserved_16_63 : 48; 1372215976Sjmallett#endif 1373215976Sjmallett } cn30xx; 1374215976Sjmallett struct cvmx_l2c_bst1_cn30xx cn31xx; 1375232812Sjmallett struct cvmx_l2c_bst1_cn38xx { 1376232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1377215976Sjmallett uint64_t reserved_16_63 : 48; 1378215976Sjmallett uint64_t vwdf : 4; /**< Bist Results for VWDF RAMs 1379215976Sjmallett - 0: GOOD (or bist in progress/never run) 1380215976Sjmallett - 1: BAD */ 1381215976Sjmallett uint64_t lrf : 2; /**< Bist Results for LRF RAMs (PLC+ILC) 1382215976Sjmallett - 0: GOOD (or bist in progress/never run) 1383215976Sjmallett - 1: BAD */ 1384215976Sjmallett uint64_t vab_vwcf : 1; /**< Bist Results for VAB VWCF_MEM 1385215976Sjmallett - 0: GOOD (or bist in progress/never run) 1386215976Sjmallett - 1: BAD */ 1387215976Sjmallett uint64_t l2t : 9; /**< Bist Results for L2T (USE+8SET RAMs) 1388215976Sjmallett - 0: GOOD (or bist in progress/never run) 1389215976Sjmallett - 1: BAD */ 1390215976Sjmallett#else 1391215976Sjmallett uint64_t l2t : 9; 1392215976Sjmallett uint64_t vab_vwcf : 1; 1393215976Sjmallett uint64_t lrf : 2; 1394215976Sjmallett uint64_t vwdf : 4; 1395215976Sjmallett uint64_t reserved_16_63 : 48; 1396215976Sjmallett#endif 1397215976Sjmallett } cn38xx; 1398215976Sjmallett struct cvmx_l2c_bst1_cn38xx cn38xxp2; 1399215976Sjmallett struct cvmx_l2c_bst1_cn38xx cn50xx; 1400232812Sjmallett struct cvmx_l2c_bst1_cn52xx { 1401232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1402215976Sjmallett uint64_t reserved_19_63 : 45; 1403215976Sjmallett uint64_t plc2 : 1; /**< Bist Results for PLC2 RAM 1404215976Sjmallett - 0: GOOD (or bist in progress/never run) 1405215976Sjmallett - 1: BAD */ 1406215976Sjmallett uint64_t plc1 : 1; /**< Bist Results for PLC1 RAM 1407215976Sjmallett - 0: GOOD (or bist in progress/never run) 1408215976Sjmallett - 1: BAD */ 1409215976Sjmallett uint64_t plc0 : 1; /**< Bist Results for PLC0 RAM 1410215976Sjmallett - 0: GOOD (or bist in progress/never run) 1411215976Sjmallett - 1: BAD */ 1412215976Sjmallett uint64_t vwdf : 4; /**< Bist Results for VWDF RAMs 1413215976Sjmallett - 0: GOOD (or bist in progress/never run) 1414215976Sjmallett - 1: BAD */ 1415215976Sjmallett uint64_t reserved_11_11 : 1; 1416215976Sjmallett uint64_t ilc : 1; /**< Bist Results for ILC RAM 1417215976Sjmallett - 0: GOOD (or bist in progress/never run) 1418215976Sjmallett - 1: BAD */ 1419215976Sjmallett uint64_t vab_vwcf : 1; /**< Bist Results for VAB VWCF_MEM 1420215976Sjmallett - 0: GOOD (or bist in progress/never run) 1421215976Sjmallett - 1: BAD */ 1422215976Sjmallett uint64_t l2t : 9; /**< Bist Results for L2T (USE+8SET RAMs) 1423215976Sjmallett - 0: GOOD (or bist in progress/never run) 1424215976Sjmallett - 1: BAD */ 1425215976Sjmallett#else 1426215976Sjmallett uint64_t l2t : 9; 1427215976Sjmallett uint64_t vab_vwcf : 1; 1428215976Sjmallett uint64_t ilc : 1; 1429215976Sjmallett uint64_t reserved_11_11 : 1; 1430215976Sjmallett uint64_t vwdf : 4; 1431215976Sjmallett uint64_t plc0 : 1; 1432215976Sjmallett uint64_t plc1 : 1; 1433215976Sjmallett uint64_t plc2 : 1; 1434215976Sjmallett uint64_t reserved_19_63 : 45; 1435215976Sjmallett#endif 1436215976Sjmallett } cn52xx; 1437215976Sjmallett struct cvmx_l2c_bst1_cn52xx cn52xxp1; 1438232812Sjmallett struct cvmx_l2c_bst1_cn56xx { 1439232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1440215976Sjmallett uint64_t reserved_24_63 : 40; 1441215976Sjmallett uint64_t plc2 : 1; /**< Bist Results for LRF RAMs (ILC) 1442215976Sjmallett - 0: GOOD (or bist in progress/never run) 1443215976Sjmallett - 1: BAD */ 1444215976Sjmallett uint64_t plc1 : 1; /**< Bist Results for LRF RAMs (ILC) 1445215976Sjmallett - 0: GOOD (or bist in progress/never run) 1446215976Sjmallett - 1: BAD */ 1447215976Sjmallett uint64_t plc0 : 1; /**< Bist Results for LRF RAMs (ILC) 1448215976Sjmallett - 0: GOOD (or bist in progress/never run) 1449215976Sjmallett - 1: BAD */ 1450215976Sjmallett uint64_t ilc : 1; /**< Bist Results for LRF RAMs (ILC) 1451215976Sjmallett - 0: GOOD (or bist in progress/never run) 1452215976Sjmallett - 1: BAD */ 1453215976Sjmallett uint64_t vwdf1 : 4; /**< Bist Results for VWDF1 RAMs 1454215976Sjmallett - 0: GOOD (or bist in progress/never run) 1455215976Sjmallett - 1: BAD */ 1456215976Sjmallett uint64_t vwdf0 : 4; /**< Bist Results for VWDF0 RAMs 1457215976Sjmallett - 0: GOOD (or bist in progress/never run) 1458215976Sjmallett - 1: BAD */ 1459215976Sjmallett uint64_t vab_vwcf1 : 1; /**< Bist Results for VAB VWCF1_MEM */ 1460215976Sjmallett uint64_t reserved_10_10 : 1; 1461215976Sjmallett uint64_t vab_vwcf0 : 1; /**< Bist Results for VAB VWCF0_MEM 1462215976Sjmallett - 0: GOOD (or bist in progress/never run) 1463215976Sjmallett - 1: BAD */ 1464215976Sjmallett uint64_t l2t : 9; /**< Bist Results for L2T (USE+8SET RAMs) 1465215976Sjmallett - 0: GOOD (or bist in progress/never run) 1466215976Sjmallett - 1: BAD */ 1467215976Sjmallett#else 1468215976Sjmallett uint64_t l2t : 9; 1469215976Sjmallett uint64_t vab_vwcf0 : 1; 1470215976Sjmallett uint64_t reserved_10_10 : 1; 1471215976Sjmallett uint64_t vab_vwcf1 : 1; 1472215976Sjmallett uint64_t vwdf0 : 4; 1473215976Sjmallett uint64_t vwdf1 : 4; 1474215976Sjmallett uint64_t ilc : 1; 1475215976Sjmallett uint64_t plc0 : 1; 1476215976Sjmallett uint64_t plc1 : 1; 1477215976Sjmallett uint64_t plc2 : 1; 1478215976Sjmallett uint64_t reserved_24_63 : 40; 1479215976Sjmallett#endif 1480215976Sjmallett } cn56xx; 1481215976Sjmallett struct cvmx_l2c_bst1_cn56xx cn56xxp1; 1482215976Sjmallett struct cvmx_l2c_bst1_cn38xx cn58xx; 1483215976Sjmallett struct cvmx_l2c_bst1_cn38xx cn58xxp1; 1484215976Sjmallett}; 1485215976Sjmalletttypedef union cvmx_l2c_bst1 cvmx_l2c_bst1_t; 1486215976Sjmallett 1487215976Sjmallett/** 1488215976Sjmallett * cvmx_l2c_bst2 1489215976Sjmallett * 1490215976Sjmallett * L2C_BST2 = L2C BIST 2 CTL/STAT 1491215976Sjmallett * 1492215976Sjmallett */ 1493232812Sjmallettunion cvmx_l2c_bst2 { 1494215976Sjmallett uint64_t u64; 1495232812Sjmallett struct cvmx_l2c_bst2_s { 1496232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1497215976Sjmallett uint64_t reserved_16_63 : 48; 1498215976Sjmallett uint64_t mrb : 4; /**< Bist Results for MRB RAMs 1499215976Sjmallett - 0: GOOD (or bist in progress/never run) 1500215976Sjmallett - 1: BAD */ 1501215976Sjmallett uint64_t reserved_4_11 : 8; 1502215976Sjmallett uint64_t ipcbst : 1; /**< Bist Results for RFB IPC RAM 1503215976Sjmallett - 1: BAD */ 1504215976Sjmallett uint64_t picbst : 1; /**< Bist Results for RFB PIC RAM 1505215976Sjmallett - 1: BAD */ 1506215976Sjmallett uint64_t xrdmsk : 1; /**< Bist Results for RFB XRD-MSK RAM 1507215976Sjmallett - 0: GOOD (or bist in progress/never run) 1508215976Sjmallett - 1: BAD */ 1509215976Sjmallett uint64_t xrddat : 1; /**< Bist Results for RFB XRD-DAT RAM 1510215976Sjmallett - 0: GOOD (or bist in progress/never run) 1511215976Sjmallett - 1: BAD */ 1512215976Sjmallett#else 1513215976Sjmallett uint64_t xrddat : 1; 1514215976Sjmallett uint64_t xrdmsk : 1; 1515215976Sjmallett uint64_t picbst : 1; 1516215976Sjmallett uint64_t ipcbst : 1; 1517215976Sjmallett uint64_t reserved_4_11 : 8; 1518215976Sjmallett uint64_t mrb : 4; 1519215976Sjmallett uint64_t reserved_16_63 : 48; 1520215976Sjmallett#endif 1521215976Sjmallett } s; 1522232812Sjmallett struct cvmx_l2c_bst2_cn30xx { 1523232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1524215976Sjmallett uint64_t reserved_16_63 : 48; 1525215976Sjmallett uint64_t mrb : 4; /**< Bist Results for MRB RAMs 1526215976Sjmallett - 0: GOOD (or bist in progress/never run) 1527215976Sjmallett - 1: BAD */ 1528215976Sjmallett uint64_t rmdf : 4; /**< Bist Results for RMDF RAMs 1529215976Sjmallett - 0: GOOD (or bist in progress/never run) 1530215976Sjmallett - 1: BAD */ 1531215976Sjmallett uint64_t reserved_4_7 : 4; 1532215976Sjmallett uint64_t ipcbst : 1; /**< Bist Results for RFB IPC RAM 1533215976Sjmallett - 0: GOOD (or bist in progress/never run) 1534215976Sjmallett - 1: BAD */ 1535215976Sjmallett uint64_t reserved_2_2 : 1; 1536215976Sjmallett uint64_t xrdmsk : 1; /**< Bist Results for RFB XRD-MSK RAM 1537215976Sjmallett - 0: GOOD (or bist in progress/never run) 1538215976Sjmallett - 1: BAD */ 1539215976Sjmallett uint64_t xrddat : 1; /**< Bist Results for RFB XRD-DAT RAM 1540215976Sjmallett - 0: GOOD (or bist in progress/never run) 1541215976Sjmallett - 1: BAD */ 1542215976Sjmallett#else 1543215976Sjmallett uint64_t xrddat : 1; 1544215976Sjmallett uint64_t xrdmsk : 1; 1545215976Sjmallett uint64_t reserved_2_2 : 1; 1546215976Sjmallett uint64_t ipcbst : 1; 1547215976Sjmallett uint64_t reserved_4_7 : 4; 1548215976Sjmallett uint64_t rmdf : 4; 1549215976Sjmallett uint64_t mrb : 4; 1550215976Sjmallett uint64_t reserved_16_63 : 48; 1551215976Sjmallett#endif 1552215976Sjmallett } cn30xx; 1553215976Sjmallett struct cvmx_l2c_bst2_cn30xx cn31xx; 1554232812Sjmallett struct cvmx_l2c_bst2_cn38xx { 1555232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1556215976Sjmallett uint64_t reserved_16_63 : 48; 1557215976Sjmallett uint64_t mrb : 4; /**< Bist Results for MRB RAMs 1558215976Sjmallett - 0: GOOD (or bist in progress/never run) 1559215976Sjmallett - 1: BAD */ 1560215976Sjmallett uint64_t rmdf : 4; /**< Bist Results for RMDF RAMs 1561215976Sjmallett - 0: GOOD (or bist in progress/never run) 1562215976Sjmallett - 1: BAD */ 1563215976Sjmallett uint64_t rhdf : 4; /**< Bist Results for RHDF RAMs 1564215976Sjmallett - 0: GOOD (or bist in progress/never run) 1565215976Sjmallett - 1: BAD */ 1566215976Sjmallett uint64_t ipcbst : 1; /**< Bist Results for RFB IPC RAM 1567215976Sjmallett - 1: BAD */ 1568215976Sjmallett uint64_t picbst : 1; /**< Bist Results for RFB PIC RAM 1569215976Sjmallett - 1: BAD */ 1570215976Sjmallett uint64_t xrdmsk : 1; /**< Bist Results for RFB XRD-MSK RAM 1571215976Sjmallett - 0: GOOD (or bist in progress/never run) 1572215976Sjmallett - 1: BAD */ 1573215976Sjmallett uint64_t xrddat : 1; /**< Bist Results for RFB XRD-DAT RAM 1574215976Sjmallett - 0: GOOD (or bist in progress/never run) 1575215976Sjmallett - 1: BAD */ 1576215976Sjmallett#else 1577215976Sjmallett uint64_t xrddat : 1; 1578215976Sjmallett uint64_t xrdmsk : 1; 1579215976Sjmallett uint64_t picbst : 1; 1580215976Sjmallett uint64_t ipcbst : 1; 1581215976Sjmallett uint64_t rhdf : 4; 1582215976Sjmallett uint64_t rmdf : 4; 1583215976Sjmallett uint64_t mrb : 4; 1584215976Sjmallett uint64_t reserved_16_63 : 48; 1585215976Sjmallett#endif 1586215976Sjmallett } cn38xx; 1587215976Sjmallett struct cvmx_l2c_bst2_cn38xx cn38xxp2; 1588215976Sjmallett struct cvmx_l2c_bst2_cn30xx cn50xx; 1589215976Sjmallett struct cvmx_l2c_bst2_cn30xx cn52xx; 1590215976Sjmallett struct cvmx_l2c_bst2_cn30xx cn52xxp1; 1591232812Sjmallett struct cvmx_l2c_bst2_cn56xx { 1592232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1593215976Sjmallett uint64_t reserved_16_63 : 48; 1594215976Sjmallett uint64_t mrb : 4; /**< Bist Results for MRB RAMs 1595215976Sjmallett - 0: GOOD (or bist in progress/never run) 1596215976Sjmallett - 1: BAD */ 1597215976Sjmallett uint64_t rmdb : 4; /**< Bist Results for RMDB RAMs 1598215976Sjmallett - 0: GOOD (or bist in progress/never run) 1599215976Sjmallett - 1: BAD */ 1600215976Sjmallett uint64_t rhdb : 4; /**< Bist Results for RHDB RAMs 1601215976Sjmallett - 0: GOOD (or bist in progress/never run) 1602215976Sjmallett - 1: BAD */ 1603215976Sjmallett uint64_t ipcbst : 1; /**< Bist Results for RFB IPC RAM 1604215976Sjmallett - 1: BAD */ 1605215976Sjmallett uint64_t picbst : 1; /**< Bist Results for RFB PIC RAM 1606215976Sjmallett - 1: BAD */ 1607215976Sjmallett uint64_t xrdmsk : 1; /**< Bist Results for RFB XRD-MSK RAM 1608215976Sjmallett - 0: GOOD (or bist in progress/never run) 1609215976Sjmallett - 1: BAD */ 1610215976Sjmallett uint64_t xrddat : 1; /**< Bist Results for RFB XRD-DAT RAM 1611215976Sjmallett - 0: GOOD (or bist in progress/never run) 1612215976Sjmallett - 1: BAD */ 1613215976Sjmallett#else 1614215976Sjmallett uint64_t xrddat : 1; 1615215976Sjmallett uint64_t xrdmsk : 1; 1616215976Sjmallett uint64_t picbst : 1; 1617215976Sjmallett uint64_t ipcbst : 1; 1618215976Sjmallett uint64_t rhdb : 4; 1619215976Sjmallett uint64_t rmdb : 4; 1620215976Sjmallett uint64_t mrb : 4; 1621215976Sjmallett uint64_t reserved_16_63 : 48; 1622215976Sjmallett#endif 1623215976Sjmallett } cn56xx; 1624215976Sjmallett struct cvmx_l2c_bst2_cn56xx cn56xxp1; 1625215976Sjmallett struct cvmx_l2c_bst2_cn56xx cn58xx; 1626215976Sjmallett struct cvmx_l2c_bst2_cn56xx cn58xxp1; 1627215976Sjmallett}; 1628215976Sjmalletttypedef union cvmx_l2c_bst2 cvmx_l2c_bst2_t; 1629215976Sjmallett 1630215976Sjmallett/** 1631215976Sjmallett * cvmx_l2c_bst_mem# 1632215976Sjmallett * 1633215976Sjmallett * L2C_BST_MEM = L2C MEM BIST Status 1634215976Sjmallett * 1635215976Sjmallett * 1636215976Sjmallett * Notes: 1637215976Sjmallett * (1) CLEAR_BIST must be written to 1 before START_BIST is written to 1 using a separate CSR write. 1638215976Sjmallett * 1639215976Sjmallett * (2) CLEAR_BIST must not be changed after writing START_BIST to 1 until the BIST operation completes 1640215976Sjmallett * (indicated by START_BIST returning to 0) or operation is undefined. 1641215976Sjmallett */ 1642232812Sjmallettunion cvmx_l2c_bst_memx { 1643215976Sjmallett uint64_t u64; 1644232812Sjmallett struct cvmx_l2c_bst_memx_s { 1645232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1646215976Sjmallett uint64_t start_bist : 1; /**< When written to 1, starts BIST. Will read 1 until 1647215976Sjmallett BIST is complete (see Note). */ 1648215976Sjmallett uint64_t clear_bist : 1; /**< When BIST is triggered, run clear BIST (see Note) */ 1649215976Sjmallett uint64_t reserved_5_61 : 57; 1650215976Sjmallett uint64_t rdffl : 1; /**< BIST failure status for RDF */ 1651215976Sjmallett uint64_t vbffl : 4; /**< BIST failure status for VBF0-3 */ 1652215976Sjmallett#else 1653215976Sjmallett uint64_t vbffl : 4; 1654215976Sjmallett uint64_t rdffl : 1; 1655215976Sjmallett uint64_t reserved_5_61 : 57; 1656215976Sjmallett uint64_t clear_bist : 1; 1657215976Sjmallett uint64_t start_bist : 1; 1658215976Sjmallett#endif 1659215976Sjmallett } s; 1660232812Sjmallett struct cvmx_l2c_bst_memx_s cn61xx; 1661215976Sjmallett struct cvmx_l2c_bst_memx_s cn63xx; 1662215976Sjmallett struct cvmx_l2c_bst_memx_s cn63xxp1; 1663232812Sjmallett struct cvmx_l2c_bst_memx_s cn66xx; 1664232812Sjmallett struct cvmx_l2c_bst_memx_s cn68xx; 1665232812Sjmallett struct cvmx_l2c_bst_memx_s cn68xxp1; 1666232812Sjmallett struct cvmx_l2c_bst_memx_s cnf71xx; 1667215976Sjmallett}; 1668215976Sjmalletttypedef union cvmx_l2c_bst_memx cvmx_l2c_bst_memx_t; 1669215976Sjmallett 1670215976Sjmallett/** 1671215976Sjmallett * cvmx_l2c_bst_tdt# 1672215976Sjmallett * 1673215976Sjmallett * L2C_BST_TDT = L2C TAD DaTa BIST Status 1674215976Sjmallett * 1675215976Sjmallett */ 1676232812Sjmallettunion cvmx_l2c_bst_tdtx { 1677215976Sjmallett uint64_t u64; 1678232812Sjmallett struct cvmx_l2c_bst_tdtx_s { 1679232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1680215976Sjmallett uint64_t reserved_32_63 : 32; 1681215976Sjmallett uint64_t fbfrspfl : 8; /**< BIST failure status for quad 0-7 FBF RSP read port */ 1682215976Sjmallett uint64_t sbffl : 8; /**< BIST failure status for quad 0-7 SBF */ 1683232812Sjmallett uint64_t fbffl : 8; /**< BIST failure status for quad 0-7 FBF WRP read port */ 1684215976Sjmallett uint64_t l2dfl : 8; /**< BIST failure status for quad 0-7 L2D */ 1685215976Sjmallett#else 1686215976Sjmallett uint64_t l2dfl : 8; 1687215976Sjmallett uint64_t fbffl : 8; 1688215976Sjmallett uint64_t sbffl : 8; 1689215976Sjmallett uint64_t fbfrspfl : 8; 1690215976Sjmallett uint64_t reserved_32_63 : 32; 1691215976Sjmallett#endif 1692215976Sjmallett } s; 1693232812Sjmallett struct cvmx_l2c_bst_tdtx_s cn61xx; 1694215976Sjmallett struct cvmx_l2c_bst_tdtx_s cn63xx; 1695232812Sjmallett struct cvmx_l2c_bst_tdtx_cn63xxp1 { 1696232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1697215976Sjmallett uint64_t reserved_24_63 : 40; 1698215976Sjmallett uint64_t sbffl : 8; /**< BIST failure status for quad 0-7 SBF */ 1699215976Sjmallett uint64_t fbffl : 8; /**< BIST failure status for quad 0-7 FBF */ 1700215976Sjmallett uint64_t l2dfl : 8; /**< BIST failure status for quad 0-7 L2D */ 1701215976Sjmallett#else 1702215976Sjmallett uint64_t l2dfl : 8; 1703215976Sjmallett uint64_t fbffl : 8; 1704215976Sjmallett uint64_t sbffl : 8; 1705215976Sjmallett uint64_t reserved_24_63 : 40; 1706215976Sjmallett#endif 1707215976Sjmallett } cn63xxp1; 1708232812Sjmallett struct cvmx_l2c_bst_tdtx_s cn66xx; 1709232812Sjmallett struct cvmx_l2c_bst_tdtx_s cn68xx; 1710232812Sjmallett struct cvmx_l2c_bst_tdtx_s cn68xxp1; 1711232812Sjmallett struct cvmx_l2c_bst_tdtx_s cnf71xx; 1712215976Sjmallett}; 1713215976Sjmalletttypedef union cvmx_l2c_bst_tdtx cvmx_l2c_bst_tdtx_t; 1714215976Sjmallett 1715215976Sjmallett/** 1716215976Sjmallett * cvmx_l2c_bst_ttg# 1717215976Sjmallett * 1718215976Sjmallett * L2C_BST_TTG = L2C TAD TaG BIST Status 1719215976Sjmallett * 1720215976Sjmallett */ 1721232812Sjmallettunion cvmx_l2c_bst_ttgx { 1722215976Sjmallett uint64_t u64; 1723232812Sjmallett struct cvmx_l2c_bst_ttgx_s { 1724232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1725215976Sjmallett uint64_t reserved_17_63 : 47; 1726215976Sjmallett uint64_t lrufl : 1; /**< BIST failure status for tag LRU */ 1727215976Sjmallett uint64_t tagfl : 16; /**< BIST failure status for tag ways 0-15 */ 1728215976Sjmallett#else 1729215976Sjmallett uint64_t tagfl : 16; 1730215976Sjmallett uint64_t lrufl : 1; 1731215976Sjmallett uint64_t reserved_17_63 : 47; 1732215976Sjmallett#endif 1733215976Sjmallett } s; 1734232812Sjmallett struct cvmx_l2c_bst_ttgx_s cn61xx; 1735215976Sjmallett struct cvmx_l2c_bst_ttgx_s cn63xx; 1736215976Sjmallett struct cvmx_l2c_bst_ttgx_s cn63xxp1; 1737232812Sjmallett struct cvmx_l2c_bst_ttgx_s cn66xx; 1738232812Sjmallett struct cvmx_l2c_bst_ttgx_s cn68xx; 1739232812Sjmallett struct cvmx_l2c_bst_ttgx_s cn68xxp1; 1740232812Sjmallett struct cvmx_l2c_bst_ttgx_s cnf71xx; 1741215976Sjmallett}; 1742215976Sjmalletttypedef union cvmx_l2c_bst_ttgx cvmx_l2c_bst_ttgx_t; 1743215976Sjmallett 1744215976Sjmallett/** 1745215976Sjmallett * cvmx_l2c_cfg 1746215976Sjmallett * 1747215976Sjmallett * Specify the RSL base addresses for the block 1748215976Sjmallett * 1749215976Sjmallett * L2C_CFG = L2C Configuration 1750215976Sjmallett * 1751215976Sjmallett * Description: 1752215976Sjmallett */ 1753232812Sjmallettunion cvmx_l2c_cfg { 1754215976Sjmallett uint64_t u64; 1755232812Sjmallett struct cvmx_l2c_cfg_s { 1756232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1757215976Sjmallett uint64_t reserved_20_63 : 44; 1758215976Sjmallett uint64_t bstrun : 1; /**< L2 Data Store Bist Running 1759215976Sjmallett Indicates when the L2C HW Bist sequence(short or long) is 1760215976Sjmallett running. [L2C ECC Bist FSM is not in the RESET/DONE state] */ 1761215976Sjmallett uint64_t lbist : 1; /**< L2C Data Store Long Bist Sequence 1762215976Sjmallett When the previous state was '0' and SW writes a '1', 1763215976Sjmallett the long bist sequence (enhanced 13N March) is performed. 1764215976Sjmallett SW can then read the L2C_CFG[BSTRUN] which will indicate 1765215976Sjmallett that the long bist sequence is running. When BSTRUN-=0, 1766215976Sjmallett the state of the L2D_BST[0-3] registers contain information 1767215976Sjmallett which reflects the status of the recent long bist sequence. 1768215976Sjmallett NOTE: SW must never write LBIST=0 while Long Bist is running 1769215976Sjmallett (ie: when BSTRUN=1 never write LBIST=0). 1770215976Sjmallett NOTE: LBIST is disabled if the MIO_FUS_DAT2.BIST_DIS 1771215976Sjmallett Fuse is blown. */ 1772215976Sjmallett uint64_t xor_bank : 1; /**< L2C XOR Bank Bit 1773215976Sjmallett When both LMC's are enabled(DPRES1=1/DPRES0=1), this 1774215976Sjmallett bit determines how addresses are assigned to 1775215976Sjmallett LMC port(s). 1776215976Sjmallett XOR_BANK| LMC# 1777215976Sjmallett ----------+--------------------------------- 1778215976Sjmallett 0 | byte address[7] 1779215976Sjmallett 1 | byte address[7] XOR byte address[12] 1780215976Sjmallett Example: If both LMC ports are enabled (DPRES1=1/DPRES0=1) 1781215976Sjmallett and XOR_BANK=1, then addr[7] XOR addr[12] is used to determine 1782215976Sjmallett which LMC Port# a reference is directed to. */ 1783215976Sjmallett uint64_t dpres1 : 1; /**< DDR1 Present/LMC1 Enable 1784215976Sjmallett When DPRES1 is set, LMC#1 is enabled(DDR1 pins at 1785215976Sjmallett the BOTTOM of the chip are active). 1786215976Sjmallett NOTE: When both LMC ports are enabled(DPRES1=1/DPRES0=1), 1787215976Sjmallett see XOR_BANK bit to determine how a reference is 1788215976Sjmallett assigned to a DDR/LMC port. (Also, in dual-LMC configuration, 1789215976Sjmallett the address sent to the targeted LMC port is the 1790215976Sjmallett address shifted right by one). 1791215976Sjmallett NOTE: For power-savings, the DPRES1 is also used to 1792215976Sjmallett disable DDR1/LMC1 clocks. */ 1793215976Sjmallett uint64_t dpres0 : 1; /**< DDR0 Present/LMC0 Enable 1794215976Sjmallett When DPRES0 is set, LMC#0 is enabled(DDR0 pins at 1795215976Sjmallett the BOTTOM of the chip are active). 1796215976Sjmallett NOTE: When both LMC ports are enabled(DPRES1=1/DPRES0=1), 1797215976Sjmallett see XOR_BANK bit to determine how a reference is 1798215976Sjmallett assigned to a DDR/LMC port. (Also, in dual-LMC configuration, 1799215976Sjmallett the address sent to the targeted LMC port is the 1800215976Sjmallett address shifted right by one). 1801215976Sjmallett NOTE: For power-savings, the DPRES0 is also used to 1802215976Sjmallett disable DDR0/LMC0 clocks. */ 1803215976Sjmallett uint64_t dfill_dis : 1; /**< L2C Dual Fill Disable 1804215976Sjmallett When set, the L2C dual-fill performance feature is 1805215976Sjmallett disabled. 1806215976Sjmallett NOTE: This bit is only intended to evaluate the 1807215976Sjmallett effectiveness of the dual-fill feature. For OPTIMAL 1808215976Sjmallett performance, this bit should ALWAYS be zero. */ 1809215976Sjmallett uint64_t fpexp : 4; /**< [CYA] Forward Progress Counter Exponent 1810215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 1811215976Sjmallett When FPEN is enabled and the LFB is empty, the 1812215976Sjmallett forward progress counter (FPCNT) is initialized to: 1813215976Sjmallett FPCNT[24:0] = 2^(9+FPEXP) 1814215976Sjmallett When the LFB is non-empty the FPCNT is decremented 1815215976Sjmallett (every eclk interval). If the FPCNT reaches zero, 1816215976Sjmallett the LFB no longer accepts new requests until either 1817215976Sjmallett a) all of the current LFB entries have completed 1818215976Sjmallett (to ensure forward progress). 1819215976Sjmallett b) FPEMPTY=0 and another forward progress count 1820215976Sjmallett interval timeout expires. 1821215976Sjmallett EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks. 1822215976Sjmallett (For eclk=500MHz(2ns), this would be ~4us). */ 1823215976Sjmallett uint64_t fpempty : 1; /**< [CYA] Forward Progress Counter Empty 1824215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 1825215976Sjmallett When set, if the forward progress counter expires, 1826215976Sjmallett all new LFB-NQs are stopped UNTIL all current LFB 1827215976Sjmallett entries have completed. 1828215976Sjmallett When clear, if the forward progress counter expires, 1829215976Sjmallett all new LFB-NQs are stopped UNTIL either 1830215976Sjmallett a) all current LFB entries have completed. 1831215976Sjmallett b) another forward progress interval expires 1832215976Sjmallett NOTE: We may want to FREEZE/HANG the system when 1833215976Sjmallett we encounter an LFB entry cannot complete, and there 1834215976Sjmallett may be times when we want to allow further LFB-NQs 1835215976Sjmallett to be permitted to help in further analyzing the 1836215976Sjmallett source */ 1837215976Sjmallett uint64_t fpen : 1; /**< [CYA] Forward Progress Counter Enable 1838215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 1839215976Sjmallett When set, enables the Forward Progress Counter to 1840215976Sjmallett prevent new LFB entries from enqueueing until ALL 1841215976Sjmallett current LFB entries have completed. */ 1842215976Sjmallett uint64_t idxalias : 1; /**< L2C Index Alias Enable 1843215976Sjmallett When set, the L2 Tag/Data Store will alias the 11-bit 1844215976Sjmallett index with the low order 11-bits of the tag. 1845215976Sjmallett index[17:7] = (tag[28:18] ^ index[17:7]) 1846215976Sjmallett NOTE: This bit must only be modified at boot time, 1847215976Sjmallett when it can be guaranteed that no blocks have been 1848215976Sjmallett loaded into the L2 Cache. 1849215976Sjmallett The index aliasing is a performance enhancement feature 1850215976Sjmallett which reduces the L2 cache thrashing experienced for 1851215976Sjmallett regular stride references. 1852215976Sjmallett NOTE: The index alias is stored in the LFB and VAB, and 1853215976Sjmallett its effects are reversed for memory references (Victims, 1854215976Sjmallett STT-Misses and Read-Misses) */ 1855215976Sjmallett uint64_t mwf_crd : 4; /**< MWF Credit Threshold: When the remaining MWF credits 1856215976Sjmallett become less than or equal to the MWF_CRD, the L2C will 1857215976Sjmallett assert l2c__lmi_mwd_hiwater_a to signal the LMC to give 1858215976Sjmallett writes (victims) higher priority. */ 1859215976Sjmallett uint64_t rsp_arb_mode : 1; /**< RSP Arbitration Mode: 1860215976Sjmallett - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC] 1861215976Sjmallett - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss), 1862215976Sjmallett RHCF(RdHit), STRSP(ST RSP w/ invalidate), 1863215976Sjmallett STRSC(ST RSP no invalidate)] */ 1864215976Sjmallett uint64_t rfb_arb_mode : 1; /**< RFB Arbitration Mode: 1865215976Sjmallett - 0: Fixed Priority - 1866215976Sjmallett IOB->PP requests are higher priority than 1867215976Sjmallett PP->IOB requests 1868215976Sjmallett - 1: Round Robin - 1869215976Sjmallett I/O requests from PP and IOB are serviced in 1870215976Sjmallett round robin */ 1871215976Sjmallett uint64_t lrf_arb_mode : 1; /**< RF Arbitration Mode: 1872215976Sjmallett - 0: Fixed Priority - 1873215976Sjmallett IOB memory requests are higher priority than PP 1874215976Sjmallett memory requests. 1875215976Sjmallett - 1: Round Robin - 1876215976Sjmallett Memory requests from PP and IOB are serviced in 1877215976Sjmallett round robin. */ 1878215976Sjmallett#else 1879215976Sjmallett uint64_t lrf_arb_mode : 1; 1880215976Sjmallett uint64_t rfb_arb_mode : 1; 1881215976Sjmallett uint64_t rsp_arb_mode : 1; 1882215976Sjmallett uint64_t mwf_crd : 4; 1883215976Sjmallett uint64_t idxalias : 1; 1884215976Sjmallett uint64_t fpen : 1; 1885215976Sjmallett uint64_t fpempty : 1; 1886215976Sjmallett uint64_t fpexp : 4; 1887215976Sjmallett uint64_t dfill_dis : 1; 1888215976Sjmallett uint64_t dpres0 : 1; 1889215976Sjmallett uint64_t dpres1 : 1; 1890215976Sjmallett uint64_t xor_bank : 1; 1891215976Sjmallett uint64_t lbist : 1; 1892215976Sjmallett uint64_t bstrun : 1; 1893215976Sjmallett uint64_t reserved_20_63 : 44; 1894215976Sjmallett#endif 1895215976Sjmallett } s; 1896232812Sjmallett struct cvmx_l2c_cfg_cn30xx { 1897232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1898215976Sjmallett uint64_t reserved_14_63 : 50; 1899215976Sjmallett uint64_t fpexp : 4; /**< [CYA] Forward Progress Counter Exponent 1900215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 1901215976Sjmallett When FPEN is enabled and the LFB is empty, the 1902215976Sjmallett forward progress counter (FPCNT) is initialized to: 1903215976Sjmallett FPCNT[24:0] = 2^(9+FPEXP) 1904215976Sjmallett When the LFB is non-empty the FPCNT is decremented 1905215976Sjmallett (every eclk interval). If the FPCNT reaches zero, 1906215976Sjmallett the LFB no longer accepts new requests until either 1907215976Sjmallett a) all of the current LFB entries have completed 1908215976Sjmallett (to ensure forward progress). 1909215976Sjmallett b) FPEMPTY=0 and another forward progress count 1910215976Sjmallett interval timeout expires. 1911215976Sjmallett EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks. 1912215976Sjmallett (For eclk=500MHz(2ns), this would be ~4us). */ 1913215976Sjmallett uint64_t fpempty : 1; /**< [CYA] Forward Progress Counter Empty 1914215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 1915215976Sjmallett When set, if the forward progress counter expires, 1916215976Sjmallett all new LFB-NQs are stopped UNTIL all current LFB 1917215976Sjmallett entries have completed. 1918215976Sjmallett When clear, if the forward progress counter expires, 1919215976Sjmallett all new LFB-NQs are stopped UNTIL either 1920215976Sjmallett a) all current LFB entries have completed. 1921215976Sjmallett b) another forward progress interval expires 1922215976Sjmallett NOTE: We may want to FREEZE/HANG the system when 1923215976Sjmallett we encounter an LFB entry cannot complete, and there 1924215976Sjmallett may be times when we want to allow further LFB-NQs 1925215976Sjmallett to be permitted to help in further analyzing the 1926215976Sjmallett source */ 1927215976Sjmallett uint64_t fpen : 1; /**< [CYA] Forward Progress Counter Enable 1928215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 1929215976Sjmallett When set, enables the Forward Progress Counter to 1930215976Sjmallett prevent new LFB entries from enqueueing until ALL 1931215976Sjmallett current LFB entries have completed. */ 1932215976Sjmallett uint64_t idxalias : 1; /**< L2C Index Alias Enable 1933215976Sjmallett When set, the L2 Tag/Data Store will alias the 8-bit 1934215976Sjmallett index with the low order 8-bits of the tag. 1935215976Sjmallett index[14:7] = (tag[22:15] ^ index[14:7]) 1936215976Sjmallett NOTE: This bit must only be modified at boot time, 1937215976Sjmallett when it can be guaranteed that no blocks have been 1938215976Sjmallett loaded into the L2 Cache. 1939215976Sjmallett The index aliasing is a performance enhancement feature 1940215976Sjmallett which reduces the L2 cache thrashing experienced for 1941215976Sjmallett regular stride references. 1942215976Sjmallett NOTE: The index alias is stored in the LFB and VAB, and 1943215976Sjmallett its effects are reversed for memory references (Victims, 1944215976Sjmallett STT-Misses and Read-Misses) */ 1945215976Sjmallett uint64_t mwf_crd : 4; /**< MWF Credit Threshold: When the remaining MWF credits 1946215976Sjmallett become less than or equal to the MWF_CRD, the L2C will 1947215976Sjmallett assert l2c__lmi_mwd_hiwater_a to signal the LMC to give 1948215976Sjmallett writes (victims) higher priority. */ 1949215976Sjmallett uint64_t rsp_arb_mode : 1; /**< RSP Arbitration Mode: 1950215976Sjmallett - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC] 1951215976Sjmallett - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss), 1952215976Sjmallett RHCF(RdHit), STRSP(ST RSP w/ invalidate), 1953215976Sjmallett STRSC(ST RSP no invalidate)] */ 1954215976Sjmallett uint64_t rfb_arb_mode : 1; /**< RFB Arbitration Mode: 1955215976Sjmallett - 0: Fixed Priority - 1956215976Sjmallett IOB->PP requests are higher priority than 1957215976Sjmallett PP->IOB requests 1958215976Sjmallett - 1: Round Robin - 1959215976Sjmallett I/O requests from PP and IOB are serviced in 1960215976Sjmallett round robin */ 1961215976Sjmallett uint64_t lrf_arb_mode : 1; /**< RF Arbitration Mode: 1962215976Sjmallett - 0: Fixed Priority - 1963215976Sjmallett IOB memory requests are higher priority than PP 1964215976Sjmallett memory requests. 1965215976Sjmallett - 1: Round Robin - 1966215976Sjmallett Memory requests from PP and IOB are serviced in 1967215976Sjmallett round robin. */ 1968215976Sjmallett#else 1969215976Sjmallett uint64_t lrf_arb_mode : 1; 1970215976Sjmallett uint64_t rfb_arb_mode : 1; 1971215976Sjmallett uint64_t rsp_arb_mode : 1; 1972215976Sjmallett uint64_t mwf_crd : 4; 1973215976Sjmallett uint64_t idxalias : 1; 1974215976Sjmallett uint64_t fpen : 1; 1975215976Sjmallett uint64_t fpempty : 1; 1976215976Sjmallett uint64_t fpexp : 4; 1977215976Sjmallett uint64_t reserved_14_63 : 50; 1978215976Sjmallett#endif 1979215976Sjmallett } cn30xx; 1980215976Sjmallett struct cvmx_l2c_cfg_cn30xx cn31xx; 1981215976Sjmallett struct cvmx_l2c_cfg_cn30xx cn38xx; 1982215976Sjmallett struct cvmx_l2c_cfg_cn30xx cn38xxp2; 1983232812Sjmallett struct cvmx_l2c_cfg_cn50xx { 1984232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1985215976Sjmallett uint64_t reserved_20_63 : 44; 1986215976Sjmallett uint64_t bstrun : 1; /**< L2 Data Store Bist Running 1987215976Sjmallett Indicates when the L2C HW Bist sequence(short or long) is 1988215976Sjmallett running. [L2C ECC Bist FSM is not in the RESET/DONE state] */ 1989215976Sjmallett uint64_t lbist : 1; /**< L2C Data Store Long Bist Sequence 1990215976Sjmallett When the previous state was '0' and SW writes a '1', 1991215976Sjmallett the long bist sequence (enhanced 13N March) is performed. 1992215976Sjmallett SW can then read the L2C_CFG[BSTRUN] which will indicate 1993215976Sjmallett that the long bist sequence is running. When BSTRUN-=0, 1994215976Sjmallett the state of the L2D_BST[0-3] registers contain information 1995215976Sjmallett which reflects the status of the recent long bist sequence. 1996215976Sjmallett NOTE: SW must never write LBIST=0 while Long Bist is running 1997215976Sjmallett (ie: when BSTRUN=1 never write LBIST=0). */ 1998215976Sjmallett uint64_t reserved_14_17 : 4; 1999215976Sjmallett uint64_t fpexp : 4; /**< [CYA] Forward Progress Counter Exponent 2000215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 2001215976Sjmallett When FPEN is enabled and the LFB is empty, the 2002215976Sjmallett forward progress counter (FPCNT) is initialized to: 2003215976Sjmallett FPCNT[24:0] = 2^(9+FPEXP) 2004215976Sjmallett When the LFB is non-empty the FPCNT is decremented 2005215976Sjmallett (every eclk interval). If the FPCNT reaches zero, 2006215976Sjmallett the LFB no longer accepts new requests until either 2007215976Sjmallett a) all of the current LFB entries have completed 2008215976Sjmallett (to ensure forward progress). 2009215976Sjmallett b) FPEMPTY=0 and another forward progress count 2010215976Sjmallett interval timeout expires. 2011215976Sjmallett EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks. 2012215976Sjmallett (For eclk=500MHz(2ns), this would be ~4us). */ 2013215976Sjmallett uint64_t fpempty : 1; /**< [CYA] Forward Progress Counter Empty 2014215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 2015215976Sjmallett When set, if the forward progress counter expires, 2016215976Sjmallett all new LFB-NQs are stopped UNTIL all current LFB 2017215976Sjmallett entries have completed. 2018215976Sjmallett When clear, if the forward progress counter expires, 2019215976Sjmallett all new LFB-NQs are stopped UNTIL either 2020215976Sjmallett a) all current LFB entries have completed. 2021215976Sjmallett b) another forward progress interval expires 2022215976Sjmallett NOTE: We may want to FREEZE/HANG the system when 2023215976Sjmallett we encounter an LFB entry cannot complete, and there 2024215976Sjmallett may be times when we want to allow further LFB-NQs 2025215976Sjmallett to be permitted to help in further analyzing the 2026215976Sjmallett source */ 2027215976Sjmallett uint64_t fpen : 1; /**< [CYA] Forward Progress Counter Enable 2028215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 2029215976Sjmallett When set, enables the Forward Progress Counter to 2030215976Sjmallett prevent new LFB entries from enqueueing until ALL 2031215976Sjmallett current LFB entries have completed. */ 2032215976Sjmallett uint64_t idxalias : 1; /**< L2C Index Alias Enable 2033215976Sjmallett When set, the L2 Tag/Data Store will alias the 7-bit 2034215976Sjmallett index with the low order 7-bits of the tag. 2035215976Sjmallett index[13:7] = (tag[20:14] ^ index[13:7]) 2036215976Sjmallett NOTE: This bit must only be modified at boot time, 2037215976Sjmallett when it can be guaranteed that no blocks have been 2038215976Sjmallett loaded into the L2 Cache. 2039215976Sjmallett The index aliasing is a performance enhancement feature 2040215976Sjmallett which reduces the L2 cache thrashing experienced for 2041215976Sjmallett regular stride references. 2042215976Sjmallett NOTE: The index alias is stored in the LFB and VAB, and 2043215976Sjmallett its effects are reversed for memory references (Victims, 2044215976Sjmallett STT-Misses and Read-Misses) */ 2045215976Sjmallett uint64_t mwf_crd : 4; /**< MWF Credit Threshold: When the remaining MWF credits 2046215976Sjmallett become less than or equal to the MWF_CRD, the L2C will 2047215976Sjmallett assert l2c__lmi_mwd_hiwater_a to signal the LMC to give 2048215976Sjmallett writes (victims) higher priority. */ 2049215976Sjmallett uint64_t rsp_arb_mode : 1; /**< RSP Arbitration Mode: 2050215976Sjmallett - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC] 2051215976Sjmallett - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss), 2052215976Sjmallett RHCF(RdHit), STRSP(ST RSP w/ invalidate), 2053215976Sjmallett STRSC(ST RSP no invalidate)] */ 2054215976Sjmallett uint64_t rfb_arb_mode : 1; /**< RFB Arbitration Mode: 2055215976Sjmallett - 0: Fixed Priority - 2056215976Sjmallett IOB->PP requests are higher priority than 2057215976Sjmallett PP->IOB requests 2058215976Sjmallett - 1: Round Robin - 2059215976Sjmallett I/O requests from PP and IOB are serviced in 2060215976Sjmallett round robin */ 2061215976Sjmallett uint64_t lrf_arb_mode : 1; /**< RF Arbitration Mode: 2062215976Sjmallett - 0: Fixed Priority - 2063215976Sjmallett IOB memory requests are higher priority than PP 2064215976Sjmallett memory requests. 2065215976Sjmallett - 1: Round Robin - 2066215976Sjmallett Memory requests from PP and IOB are serviced in 2067215976Sjmallett round robin. */ 2068215976Sjmallett#else 2069215976Sjmallett uint64_t lrf_arb_mode : 1; 2070215976Sjmallett uint64_t rfb_arb_mode : 1; 2071215976Sjmallett uint64_t rsp_arb_mode : 1; 2072215976Sjmallett uint64_t mwf_crd : 4; 2073215976Sjmallett uint64_t idxalias : 1; 2074215976Sjmallett uint64_t fpen : 1; 2075215976Sjmallett uint64_t fpempty : 1; 2076215976Sjmallett uint64_t fpexp : 4; 2077215976Sjmallett uint64_t reserved_14_17 : 4; 2078215976Sjmallett uint64_t lbist : 1; 2079215976Sjmallett uint64_t bstrun : 1; 2080215976Sjmallett uint64_t reserved_20_63 : 44; 2081215976Sjmallett#endif 2082215976Sjmallett } cn50xx; 2083215976Sjmallett struct cvmx_l2c_cfg_cn50xx cn52xx; 2084215976Sjmallett struct cvmx_l2c_cfg_cn50xx cn52xxp1; 2085215976Sjmallett struct cvmx_l2c_cfg_s cn56xx; 2086215976Sjmallett struct cvmx_l2c_cfg_s cn56xxp1; 2087232812Sjmallett struct cvmx_l2c_cfg_cn58xx { 2088232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2089215976Sjmallett uint64_t reserved_20_63 : 44; 2090215976Sjmallett uint64_t bstrun : 1; /**< L2 Data Store Bist Running 2091215976Sjmallett Indicates when the L2C HW Bist sequence(short or long) is 2092215976Sjmallett running. [L2C ECC Bist FSM is not in the RESET/DONE state] */ 2093215976Sjmallett uint64_t lbist : 1; /**< L2C Data Store Long Bist Sequence 2094215976Sjmallett When the previous state was '0' and SW writes a '1', 2095215976Sjmallett the long bist sequence (enhanced 13N March) is performed. 2096215976Sjmallett SW can then read the L2C_CFG[BSTRUN] which will indicate 2097215976Sjmallett that the long bist sequence is running. When BSTRUN-=0, 2098215976Sjmallett the state of the L2D_BST[0-3] registers contain information 2099215976Sjmallett which reflects the status of the recent long bist sequence. 2100215976Sjmallett NOTE: SW must never write LBIST=0 while Long Bist is running 2101215976Sjmallett (ie: when BSTRUN=1 never write LBIST=0). 2102215976Sjmallett NOTE: LBIST is disabled if the MIO_FUS_DAT2.BIST_DIS 2103215976Sjmallett Fuse is blown. */ 2104215976Sjmallett uint64_t reserved_15_17 : 3; 2105215976Sjmallett uint64_t dfill_dis : 1; /**< L2C Dual Fill Disable 2106215976Sjmallett When set, the L2C dual-fill performance feature is 2107215976Sjmallett disabled. 2108215976Sjmallett NOTE: This bit is only intended to evaluate the 2109215976Sjmallett effectiveness of the dual-fill feature. For OPTIMAL 2110215976Sjmallett performance, this bit should ALWAYS be zero. */ 2111215976Sjmallett uint64_t fpexp : 4; /**< [CYA] Forward Progress Counter Exponent 2112215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 2113215976Sjmallett When FPEN is enabled and the LFB is empty, the 2114215976Sjmallett forward progress counter (FPCNT) is initialized to: 2115215976Sjmallett FPCNT[24:0] = 2^(9+FPEXP) 2116215976Sjmallett When the LFB is non-empty the FPCNT is decremented 2117215976Sjmallett (every eclk interval). If the FPCNT reaches zero, 2118215976Sjmallett the LFB no longer accepts new requests until either 2119215976Sjmallett a) all of the current LFB entries have completed 2120215976Sjmallett (to ensure forward progress). 2121215976Sjmallett b) FPEMPTY=0 and another forward progress count 2122215976Sjmallett interval timeout expires. 2123215976Sjmallett EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks. 2124215976Sjmallett (For eclk=500MHz(2ns), this would be ~4us). */ 2125215976Sjmallett uint64_t fpempty : 1; /**< [CYA] Forward Progress Counter Empty 2126215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 2127215976Sjmallett When set, if the forward progress counter expires, 2128215976Sjmallett all new LFB-NQs are stopped UNTIL all current LFB 2129215976Sjmallett entries have completed. 2130215976Sjmallett When clear, if the forward progress counter expires, 2131215976Sjmallett all new LFB-NQs are stopped UNTIL either 2132215976Sjmallett a) all current LFB entries have completed. 2133215976Sjmallett b) another forward progress interval expires 2134215976Sjmallett NOTE: We may want to FREEZE/HANG the system when 2135215976Sjmallett we encounter an LFB entry cannot complete, and there 2136215976Sjmallett may be times when we want to allow further LFB-NQs 2137215976Sjmallett to be permitted to help in further analyzing the 2138215976Sjmallett source */ 2139215976Sjmallett uint64_t fpen : 1; /**< [CYA] Forward Progress Counter Enable 2140215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 2141215976Sjmallett When set, enables the Forward Progress Counter to 2142215976Sjmallett prevent new LFB entries from enqueueing until ALL 2143215976Sjmallett current LFB entries have completed. */ 2144215976Sjmallett uint64_t idxalias : 1; /**< L2C Index Alias Enable 2145215976Sjmallett When set, the L2 Tag/Data Store will alias the 11-bit 2146215976Sjmallett index with the low order 11-bits of the tag. 2147215976Sjmallett index[17:7] = (tag[28:18] ^ index[17:7]) 2148215976Sjmallett NOTE: This bit must only be modified at boot time, 2149215976Sjmallett when it can be guaranteed that no blocks have been 2150215976Sjmallett loaded into the L2 Cache. 2151215976Sjmallett The index aliasing is a performance enhancement feature 2152215976Sjmallett which reduces the L2 cache thrashing experienced for 2153215976Sjmallett regular stride references. 2154215976Sjmallett NOTE: The index alias is stored in the LFB and VAB, and 2155215976Sjmallett its effects are reversed for memory references (Victims, 2156215976Sjmallett STT-Misses and Read-Misses) */ 2157215976Sjmallett uint64_t mwf_crd : 4; /**< MWF Credit Threshold: When the remaining MWF credits 2158215976Sjmallett become less than or equal to the MWF_CRD, the L2C will 2159215976Sjmallett assert l2c__lmi_mwd_hiwater_a to signal the LMC to give 2160215976Sjmallett writes (victims) higher priority. */ 2161215976Sjmallett uint64_t rsp_arb_mode : 1; /**< RSP Arbitration Mode: 2162215976Sjmallett - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC] 2163215976Sjmallett - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss), 2164215976Sjmallett RHCF(RdHit), STRSP(ST RSP w/ invalidate), 2165215976Sjmallett STRSC(ST RSP no invalidate)] */ 2166215976Sjmallett uint64_t rfb_arb_mode : 1; /**< RFB Arbitration Mode: 2167215976Sjmallett - 0: Fixed Priority - 2168215976Sjmallett IOB->PP requests are higher priority than 2169215976Sjmallett PP->IOB requests 2170215976Sjmallett - 1: Round Robin - 2171215976Sjmallett I/O requests from PP and IOB are serviced in 2172215976Sjmallett round robin */ 2173215976Sjmallett uint64_t lrf_arb_mode : 1; /**< RF Arbitration Mode: 2174215976Sjmallett - 0: Fixed Priority - 2175215976Sjmallett IOB memory requests are higher priority than PP 2176215976Sjmallett memory requests. 2177215976Sjmallett - 1: Round Robin - 2178215976Sjmallett Memory requests from PP and IOB are serviced in 2179215976Sjmallett round robin. */ 2180215976Sjmallett#else 2181215976Sjmallett uint64_t lrf_arb_mode : 1; 2182215976Sjmallett uint64_t rfb_arb_mode : 1; 2183215976Sjmallett uint64_t rsp_arb_mode : 1; 2184215976Sjmallett uint64_t mwf_crd : 4; 2185215976Sjmallett uint64_t idxalias : 1; 2186215976Sjmallett uint64_t fpen : 1; 2187215976Sjmallett uint64_t fpempty : 1; 2188215976Sjmallett uint64_t fpexp : 4; 2189215976Sjmallett uint64_t dfill_dis : 1; 2190215976Sjmallett uint64_t reserved_15_17 : 3; 2191215976Sjmallett uint64_t lbist : 1; 2192215976Sjmallett uint64_t bstrun : 1; 2193215976Sjmallett uint64_t reserved_20_63 : 44; 2194215976Sjmallett#endif 2195215976Sjmallett } cn58xx; 2196232812Sjmallett struct cvmx_l2c_cfg_cn58xxp1 { 2197232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2198215976Sjmallett uint64_t reserved_15_63 : 49; 2199215976Sjmallett uint64_t dfill_dis : 1; /**< L2C Dual Fill Disable 2200215976Sjmallett When set, the L2C dual-fill performance feature is 2201215976Sjmallett disabled. 2202215976Sjmallett NOTE: This bit is only intended to evaluate the 2203215976Sjmallett effectiveness of the dual-fill feature. For OPTIMAL 2204215976Sjmallett performance, this bit should ALWAYS be zero. */ 2205215976Sjmallett uint64_t fpexp : 4; /**< [CYA] Forward Progress Counter Exponent 2206215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 2207215976Sjmallett When FPEN is enabled and the LFB is empty, the 2208215976Sjmallett forward progress counter (FPCNT) is initialized to: 2209215976Sjmallett FPCNT[24:0] = 2^(9+FPEXP) 2210215976Sjmallett When the LFB is non-empty the FPCNT is decremented 2211215976Sjmallett (every eclk interval). If the FPCNT reaches zero, 2212215976Sjmallett the LFB no longer accepts new requests until either 2213215976Sjmallett a) all of the current LFB entries have completed 2214215976Sjmallett (to ensure forward progress). 2215215976Sjmallett b) FPEMPTY=0 and another forward progress count 2216215976Sjmallett interval timeout expires. 2217215976Sjmallett EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks. 2218215976Sjmallett (For eclk=500MHz(2ns), this would be ~4us). */ 2219215976Sjmallett uint64_t fpempty : 1; /**< [CYA] Forward Progress Counter Empty 2220215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 2221215976Sjmallett When set, if the forward progress counter expires, 2222215976Sjmallett all new LFB-NQs are stopped UNTIL all current LFB 2223215976Sjmallett entries have completed. 2224215976Sjmallett When clear, if the forward progress counter expires, 2225215976Sjmallett all new LFB-NQs are stopped UNTIL either 2226215976Sjmallett a) all current LFB entries have completed. 2227215976Sjmallett b) another forward progress interval expires 2228215976Sjmallett NOTE: We may want to FREEZE/HANG the system when 2229215976Sjmallett we encounter an LFB entry cannot complete, and there 2230215976Sjmallett may be times when we want to allow further LFB-NQs 2231215976Sjmallett to be permitted to help in further analyzing the 2232215976Sjmallett source */ 2233215976Sjmallett uint64_t fpen : 1; /**< [CYA] Forward Progress Counter Enable 2234215976Sjmallett NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY] 2235215976Sjmallett When set, enables the Forward Progress Counter to 2236215976Sjmallett prevent new LFB entries from enqueueing until ALL 2237215976Sjmallett current LFB entries have completed. */ 2238215976Sjmallett uint64_t idxalias : 1; /**< L2C Index Alias Enable 2239215976Sjmallett When set, the L2 Tag/Data Store will alias the 11-bit 2240215976Sjmallett index with the low order 11-bits of the tag. 2241215976Sjmallett index[17:7] = (tag[28:18] ^ index[17:7]) 2242215976Sjmallett NOTE: This bit must only be modified at boot time, 2243215976Sjmallett when it can be guaranteed that no blocks have been 2244215976Sjmallett loaded into the L2 Cache. 2245215976Sjmallett The index aliasing is a performance enhancement feature 2246215976Sjmallett which reduces the L2 cache thrashing experienced for 2247215976Sjmallett regular stride references. 2248215976Sjmallett NOTE: The index alias is stored in the LFB and VAB, and 2249215976Sjmallett its effects are reversed for memory references (Victims, 2250215976Sjmallett STT-Misses and Read-Misses) */ 2251215976Sjmallett uint64_t mwf_crd : 4; /**< MWF Credit Threshold: When the remaining MWF credits 2252215976Sjmallett become less than or equal to the MWF_CRD, the L2C will 2253215976Sjmallett assert l2c__lmi_mwd_hiwater_a to signal the LMC to give 2254215976Sjmallett writes (victims) higher priority. */ 2255215976Sjmallett uint64_t rsp_arb_mode : 1; /**< RSP Arbitration Mode: 2256215976Sjmallett - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC] 2257215976Sjmallett - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss), 2258215976Sjmallett RHCF(RdHit), STRSP(ST RSP w/ invalidate), 2259215976Sjmallett STRSC(ST RSP no invalidate)] */ 2260215976Sjmallett uint64_t rfb_arb_mode : 1; /**< RFB Arbitration Mode: 2261215976Sjmallett - 0: Fixed Priority - 2262215976Sjmallett IOB->PP requests are higher priority than 2263215976Sjmallett PP->IOB requests 2264215976Sjmallett - 1: Round Robin - 2265215976Sjmallett I/O requests from PP and IOB are serviced in 2266215976Sjmallett round robin */ 2267215976Sjmallett uint64_t lrf_arb_mode : 1; /**< RF Arbitration Mode: 2268215976Sjmallett - 0: Fixed Priority - 2269215976Sjmallett IOB memory requests are higher priority than PP 2270215976Sjmallett memory requests. 2271215976Sjmallett - 1: Round Robin - 2272215976Sjmallett Memory requests from PP and IOB are serviced in 2273215976Sjmallett round robin. */ 2274215976Sjmallett#else 2275215976Sjmallett uint64_t lrf_arb_mode : 1; 2276215976Sjmallett uint64_t rfb_arb_mode : 1; 2277215976Sjmallett uint64_t rsp_arb_mode : 1; 2278215976Sjmallett uint64_t mwf_crd : 4; 2279215976Sjmallett uint64_t idxalias : 1; 2280215976Sjmallett uint64_t fpen : 1; 2281215976Sjmallett uint64_t fpempty : 1; 2282215976Sjmallett uint64_t fpexp : 4; 2283215976Sjmallett uint64_t dfill_dis : 1; 2284215976Sjmallett uint64_t reserved_15_63 : 49; 2285215976Sjmallett#endif 2286215976Sjmallett } cn58xxp1; 2287215976Sjmallett}; 2288215976Sjmalletttypedef union cvmx_l2c_cfg cvmx_l2c_cfg_t; 2289215976Sjmallett 2290215976Sjmallett/** 2291215976Sjmallett * cvmx_l2c_cop0_map# 2292215976Sjmallett * 2293215976Sjmallett * L2C_COP0_MAP = PP COP0 register memory mapped region 2294215976Sjmallett * 2295215976Sjmallett * Description: PP COP0 register mapped region. 2296215976Sjmallett * 2297232812Sjmallett * NOTE: for 63xx, if the PPID is outside the range of 0-3,63 the write will be ignored and reads 2298215976Sjmallett * will return 0x2bad2bad2bad2bad 2299215976Sjmallett * 2300215976Sjmallett * Notes: 2301215976Sjmallett * (1) There are 256 COP0 registers per PP. Registers 0-255 map to PP0's COP0 registers, 256-511 are 2302215976Sjmallett * mapped to PP1's, etc. A special set X PP63 (registers 16128-16383) are for broadcast writes. 2303215976Sjmallett * Any write done to these registers will take effect in ALL PPs. Note the means the L2C_COP0_MAP 2304215976Sjmallett * register to access can be gotten by: 2305215976Sjmallett * 2306215976Sjmallett * REGNUM = [ PPID[5:0], rd[4:0], sel[2:0] ] 2307215976Sjmallett * 2308215976Sjmallett * where rd and sel are as defined in the HRM description of Core Coprocessor 0 registers 2309215976Sjmallett * and note 4 below. 2310215976Sjmallett * 2311215976Sjmallett * (2) if a COP0 register cannot be accessed by this mechanism the write be silently ignored and the 2312215976Sjmallett * read data will be 0xBADDEED. 2313215976Sjmallett * 2314232812Sjmallett * (3) for 61xx, if the PPID is outside the range of 0-3,63 or if the PP in question is in reset a 2315215976Sjmallett * write will be ignored and reads will timeout the RSL bus. 2316215976Sjmallett * 2317215976Sjmallett * (4) Referring to note (1) above, the following rd/sel values are supported: 2318215976Sjmallett * 2319215976Sjmallett * NOTE: Put only the "Customer type" in HRM. do not put the "Real type" in HRM. 2320215976Sjmallett * 2321215976Sjmallett * Customer Real 2322215976Sjmallett * rd sel type Description type 2323215976Sjmallett * ======+=======+==========+==============================================+========= 2324215976Sjmallett * 4 2 RO COP0 UserLocal RW 2325215976Sjmallett * 7 0 RO COP0 HWREna RW 2326215976Sjmallett * 9 0 RO COP0 Count RW 2327215976Sjmallett * 9 6 RO COP0 CvmCount RW 2328215976Sjmallett * 9 7 RO COP0 CvmCtl RW 2329215976Sjmallett * 11 0 RO COP0 Compare RW 2330215976Sjmallett * 11 6 RW COP0 PowThrottle RW 2331215976Sjmallett * 12 0 RO COP0 Status RW 2332215976Sjmallett * 12 1 RO COP0 IntCtl RO 2333215976Sjmallett * 12 2 RO COP0 SRSCtl RO 2334215976Sjmallett * 13 0 RO COP0 Cause RW 2335215976Sjmallett * 14 0 RO COP0 EPC RW 2336215976Sjmallett * 15 0 RO COP0 PrID RO 2337215976Sjmallett * 15 1 RO COP0 EBase RW 2338215976Sjmallett * 16 0 RO PC Issue Debug Info (see details below) RO 2339215976Sjmallett * 16 1 RO PC Fetch Debug Info (see details below) RO 2340215976Sjmallett * 16 2 RO PC Fill Debug Info (see details below) RO 2341215976Sjmallett * 16 3 RO PC Misc Debug Info (see details below) RO 2342215976Sjmallett * 18 0 RO COP0 WatchLo0 RW 2343215976Sjmallett * 19 0 RO COP0 WatchHi0 RW 2344215976Sjmallett * 22 0 RO COP0 MultiCoreDebug RW 2345232812Sjmallett * 22 1 COP0 VoltageMonitor RW 2346215976Sjmallett * 23 0 RO COP0 Debug RW 2347215976Sjmallett * 23 6 RO COP0 Debug2 RO 2348215976Sjmallett * 24 0 RO COP0 DEPC RW 2349215976Sjmallett * 25 0 RO COP0 PerfCnt Control0 RW 2350215976Sjmallett * 25 1 RO COP0 PerfCnt Counter0 RW 2351215976Sjmallett * 25 2 RO COP0 PerfCnt Control1 RW 2352215976Sjmallett * 25 3 RO COP0 PerfCnt Counter1 RW 2353215976Sjmallett * 27 0 RO COP0 CacheErr (icache) RW 2354215976Sjmallett * 28 0 RO COP0 TagLo (icache) RW 2355215976Sjmallett * 28 1 RO COP0 DataLo (icache) RW 2356215976Sjmallett * 29 1 RO COP0 DataHi (icache) RW 2357215976Sjmallett * 30 0 RO COP0 ErrorEPC RW 2358215976Sjmallett * 31 0 RO COP0 DESAVE RW 2359215976Sjmallett * 31 2 RO COP0 Scratch RW 2360215976Sjmallett * 31 3 RO COP0 Scratch1 RW 2361215976Sjmallett * 31 4 RO COP0 Scratch2 RW 2362215976Sjmallett * 2363215976Sjmallett * - PC Issue Debug Info 2364215976Sjmallett * 2365215976Sjmallett * - 63:2 pc0_5a<63:2> // often VA<63:2> of the next instruction to issue 2366215976Sjmallett * // but can also be the VA of an instruction executing/replaying on pipe 0 2367215976Sjmallett * // or can also be a VA being filled into the instruction cache 2368215976Sjmallett * // or can also be unpredictable 2369215976Sjmallett * // <61:49> RAZ 2370215976Sjmallett * 1 illegal // set when illegal VA 2371215976Sjmallett * 0 delayslot // set when VA is delayslot (prior branch may be either taken or not taken) 2372215976Sjmallett * 2373215976Sjmallett * - PC Fetch Debug Info 2374215976Sjmallett * 2375215976Sjmallett * - 63:0 fetch_address_3a // VA being fetched from the instruction cache 2376215976Sjmallett * // <61:49>, <1:0> RAZ 2377215976Sjmallett * 2378215976Sjmallett * - PC Fill Debug Info 2379215976Sjmallett * 2380215976Sjmallett * - 63:0 fill_address_4a<63:2> // VA<63:2> being filled into instruction cache 2381215976Sjmallett * // valid when waiting_for_ifill_4a is set (see PC Misc Debug Info below) 2382215976Sjmallett * // <61:49> RAZ 2383215976Sjmallett * 1 illegal // set when illegal VA 2384215976Sjmallett * 0 RAZ 2385215976Sjmallett * 2386215976Sjmallett * - PC Misc Debug Info 2387215976Sjmallett * 2388215976Sjmallett * - 63:3 RAZ 2389215976Sjmallett * 2 mem_stall_3a // stall term from L1 memory system 2390215976Sjmallett * 1 waiting_for_pfill_4a // when waiting_for_ifill_4a is set, indicates whether instruction cache fill is due to a prefetch 2391215976Sjmallett * 0 waiting_for_ifill_4a // set when there is an outstanding instruction cache fill 2392215976Sjmallett */ 2393232812Sjmallettunion cvmx_l2c_cop0_mapx { 2394215976Sjmallett uint64_t u64; 2395232812Sjmallett struct cvmx_l2c_cop0_mapx_s { 2396232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2397215976Sjmallett uint64_t data : 64; /**< Data to write to/read from designated PP's COP0 2398215976Sjmallett register. */ 2399215976Sjmallett#else 2400215976Sjmallett uint64_t data : 64; 2401215976Sjmallett#endif 2402215976Sjmallett } s; 2403232812Sjmallett struct cvmx_l2c_cop0_mapx_s cn61xx; 2404215976Sjmallett struct cvmx_l2c_cop0_mapx_s cn63xx; 2405215976Sjmallett struct cvmx_l2c_cop0_mapx_s cn63xxp1; 2406232812Sjmallett struct cvmx_l2c_cop0_mapx_s cn66xx; 2407232812Sjmallett struct cvmx_l2c_cop0_mapx_s cn68xx; 2408232812Sjmallett struct cvmx_l2c_cop0_mapx_s cn68xxp1; 2409232812Sjmallett struct cvmx_l2c_cop0_mapx_s cnf71xx; 2410215976Sjmallett}; 2411215976Sjmalletttypedef union cvmx_l2c_cop0_mapx cvmx_l2c_cop0_mapx_t; 2412215976Sjmallett 2413215976Sjmallett/** 2414215976Sjmallett * cvmx_l2c_ctl 2415215976Sjmallett * 2416215976Sjmallett * L2C_CTL = L2C Control 2417215976Sjmallett * 2418215976Sjmallett * 2419215976Sjmallett * Notes: 2420215976Sjmallett * (1) If MAXVAB is != 0, VAB_THRESH should be less than MAXVAB. 2421215976Sjmallett * 2422215976Sjmallett * (2) L2DFDBE and L2DFSBE allows software to generate L2DSBE, L2DDBE, VBFSBE, and VBFDBE errors for 2423215976Sjmallett * the purposes of testing error handling code. When one (or both) of these bits are set a PL2 2424215976Sjmallett * which misses in the L2 will fill with the appropriate error in the first 2 OWs of the fill. 2425215976Sjmallett * Software can determine which OW pair gets the error by choosing the desired fill order 2426215976Sjmallett * (address<6:5>). A PL2 which hits in the L2 will not inject any errors. Therefore sending a 2427215976Sjmallett * WBIL2 prior to the PL2 is recommended to make a miss likely (if multiple processors are involved 2428215976Sjmallett * software must be careful to be sure no other processor or IO device can bring the block into the 2429215976Sjmallett * L2). 2430215976Sjmallett * 2431215976Sjmallett * To generate a VBFSBE or VBFDBE, software must first get the cache block into the cache with an 2432215976Sjmallett * error using a PL2 which misses the L2. Then a store partial to a portion of the cache block 2433215976Sjmallett * without the error must change the block to dirty. Then, a subsequent WBL2/WBIL2/victim will 2434215976Sjmallett * trigger the VBFSBE/VBFDBE error. 2435215976Sjmallett */ 2436232812Sjmallettunion cvmx_l2c_ctl { 2437215976Sjmallett uint64_t u64; 2438232812Sjmallett struct cvmx_l2c_ctl_s { 2439232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2440232812Sjmallett uint64_t reserved_30_63 : 34; 2441232812Sjmallett uint64_t sepcmt : 1; /**< Sends all invals before the corresponding commit. */ 2442232812Sjmallett uint64_t rdf_fast : 1; /**< When 0, delay read data fifo from DCLK to RCLK by one 2443232812Sjmallett cycle. Needed when DCLK:RCLK ratio > 3:1. Should be 2444232812Sjmallett set before DDR traffic begins and only changed when 2445232812Sjmallett memory traffic is idle. */ 2446232812Sjmallett uint64_t disstgl2i : 1; /**< Disable STGL2I's from changing the tags */ 2447232812Sjmallett uint64_t l2dfsbe : 1; /**< Force single bit ECC error on PL2 allocates (2) */ 2448232812Sjmallett uint64_t l2dfdbe : 1; /**< Force double bit ECC error on PL2 allocates (2) */ 2449232812Sjmallett uint64_t discclk : 1; /**< Disable conditional clocking in L2C PNR blocks */ 2450232812Sjmallett uint64_t maxvab : 4; /**< Maximum VABs in use at once 2451232812Sjmallett (0 means 16, 1-15 as expected) */ 2452232812Sjmallett uint64_t maxlfb : 4; /**< Maximum LFBs in use at once 2453232812Sjmallett (0 means 16, 1-15 as expected) */ 2454232812Sjmallett uint64_t rsp_arb_mode : 1; /**< Arbitration mode for RSC/RSD bus 2455232812Sjmallett == 0, round-robin 2456232812Sjmallett == 1, static priority 2457232812Sjmallett 1. IOR data 2458232812Sjmallett 2. STIN/FILLs 2459232812Sjmallett 3. STDN/SCDN/SCFL */ 2460232812Sjmallett uint64_t xmc_arb_mode : 1; /**< Arbitration mode for XMC QOS queues 2461232812Sjmallett == 0, fully determined through QOS 2462232812Sjmallett == 1, QOS0 highest priority, QOS1-3 use normal mode */ 2463232812Sjmallett uint64_t ef_ena : 1; /**< LMC early fill enable */ 2464232812Sjmallett uint64_t ef_cnt : 7; /**< LMC early fill count 2465232812Sjmallett Specifies the number of cycles after the first LMC 2466232812Sjmallett fill cycle to wait before requesting a fill on the 2467232812Sjmallett RSC/RSD bus. 2468232812Sjmallett // 7 dclks (we've received 1st out of 8 2469232812Sjmallett // by the time we start counting) 2470232812Sjmallett ef_cnt = ((LMCn_CONFIG[MODE32b] ? 14 : 7) * 2471232812Sjmallett dclk0_period) / rclk_period; 2472232812Sjmallett // + 1 rclk if the dclk and rclk edges don't 2473232812Sjmallett // stay in the same position 2474232812Sjmallett if ((dclk0_gen.period % rclk_gen.period) != 0) 2475232812Sjmallett ef_cnt = ef_cnt + 1; 2476232812Sjmallett // + 2 rclk synchronization uncertainty 2477232812Sjmallett ef_cnt = ef_cnt + 2; 2478232812Sjmallett // - 3 rclks to recognize first write 2479232812Sjmallett ef_cnt = ef_cnt - 3; 2480232812Sjmallett // + 3 rclks to perform first write 2481232812Sjmallett ef_cnt = ef_cnt + 3; 2482232812Sjmallett // - 9 rclks minimum latency from counter expire 2483232812Sjmallett // to final fbf read 2484232812Sjmallett ef_cnt = ef_cnt - 9; */ 2485232812Sjmallett uint64_t vab_thresh : 4; /**< VAB Threshold 2486232812Sjmallett When the number of valid VABs exceeds this number the 2487232812Sjmallett L2C increases the priority of all writes in the LMC. */ 2488232812Sjmallett uint64_t disecc : 1; /**< Tag and Data ECC Disable */ 2489232812Sjmallett uint64_t disidxalias : 1; /**< Index Alias Disable */ 2490232812Sjmallett#else 2491232812Sjmallett uint64_t disidxalias : 1; 2492232812Sjmallett uint64_t disecc : 1; 2493232812Sjmallett uint64_t vab_thresh : 4; 2494232812Sjmallett uint64_t ef_cnt : 7; 2495232812Sjmallett uint64_t ef_ena : 1; 2496232812Sjmallett uint64_t xmc_arb_mode : 1; 2497232812Sjmallett uint64_t rsp_arb_mode : 1; 2498232812Sjmallett uint64_t maxlfb : 4; 2499232812Sjmallett uint64_t maxvab : 4; 2500232812Sjmallett uint64_t discclk : 1; 2501232812Sjmallett uint64_t l2dfdbe : 1; 2502232812Sjmallett uint64_t l2dfsbe : 1; 2503232812Sjmallett uint64_t disstgl2i : 1; 2504232812Sjmallett uint64_t rdf_fast : 1; 2505232812Sjmallett uint64_t sepcmt : 1; 2506232812Sjmallett uint64_t reserved_30_63 : 34; 2507232812Sjmallett#endif 2508232812Sjmallett } s; 2509232812Sjmallett struct cvmx_l2c_ctl_cn61xx { 2510232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2511232812Sjmallett uint64_t reserved_29_63 : 35; 2512232812Sjmallett uint64_t rdf_fast : 1; /**< When 0, delay read data fifo from DCLK to RCLK by one 2513232812Sjmallett cycle. Needed when DCLK:RCLK ratio > 3:1. Should be 2514232812Sjmallett set before DDR traffic begins and only changed when 2515232812Sjmallett memory traffic is idle. */ 2516232812Sjmallett uint64_t disstgl2i : 1; /**< Disable STGL2I's from changing the tags */ 2517232812Sjmallett uint64_t l2dfsbe : 1; /**< Force single bit ECC error on PL2 allocates (2) */ 2518232812Sjmallett uint64_t l2dfdbe : 1; /**< Force double bit ECC error on PL2 allocates (2) */ 2519232812Sjmallett uint64_t discclk : 1; /**< Disable conditional clocking in L2C PNR blocks */ 2520232812Sjmallett uint64_t maxvab : 4; /**< Maximum VABs in use at once 2521232812Sjmallett (0 means 16, 1-15 as expected) */ 2522232812Sjmallett uint64_t maxlfb : 4; /**< Maximum LFBs in use at once 2523232812Sjmallett (0 means 16, 1-15 as expected) */ 2524232812Sjmallett uint64_t rsp_arb_mode : 1; /**< Arbitration mode for RSC/RSD bus 2525232812Sjmallett == 0, round-robin 2526232812Sjmallett == 1, static priority 2527232812Sjmallett 1. IOR data 2528232812Sjmallett 2. STIN/FILLs 2529232812Sjmallett 3. STDN/SCDN/SCFL */ 2530232812Sjmallett uint64_t xmc_arb_mode : 1; /**< Arbitration mode for XMC QOS queues 2531232812Sjmallett == 0, fully determined through QOS 2532232812Sjmallett == 1, QOS0 highest priority, QOS1-3 use normal mode */ 2533232812Sjmallett uint64_t ef_ena : 1; /**< LMC early fill enable */ 2534232812Sjmallett uint64_t ef_cnt : 7; /**< LMC early fill count 2535232812Sjmallett Specifies the number of cycles after the first LMC 2536232812Sjmallett fill cycle to wait before requesting a fill on the 2537232812Sjmallett RSC/RSD bus. 2538232812Sjmallett // 7 dclks (we've received 1st out of 8 2539232812Sjmallett // by the time we start counting) 2540232812Sjmallett ef_cnt = ((LMCn_CONFIG[MODE32b] ? 14 : 7) * 2541232812Sjmallett dclk0_period) / rclk_period; 2542232812Sjmallett // + 1 rclk if the dclk and rclk edges don't 2543232812Sjmallett // stay in the same position 2544232812Sjmallett if ((dclk0_gen.period % rclk_gen.period) != 0) 2545232812Sjmallett ef_cnt = ef_cnt + 1; 2546232812Sjmallett // + 2 rclk synchronization uncertainty 2547232812Sjmallett ef_cnt = ef_cnt + 2; 2548232812Sjmallett // - 3 rclks to recognize first write 2549232812Sjmallett ef_cnt = ef_cnt - 3; 2550232812Sjmallett // + 3 rclks to perform first write 2551232812Sjmallett ef_cnt = ef_cnt + 3; 2552232812Sjmallett // - 9 rclks minimum latency from counter expire 2553232812Sjmallett // to final fbf read 2554232812Sjmallett ef_cnt = ef_cnt - 9; */ 2555232812Sjmallett uint64_t vab_thresh : 4; /**< VAB Threshold 2556232812Sjmallett When the number of valid VABs exceeds this number the 2557232812Sjmallett L2C increases the priority of all writes in the LMC. */ 2558232812Sjmallett uint64_t disecc : 1; /**< Tag and Data ECC Disable */ 2559232812Sjmallett uint64_t disidxalias : 1; /**< Index Alias Disable */ 2560232812Sjmallett#else 2561232812Sjmallett uint64_t disidxalias : 1; 2562232812Sjmallett uint64_t disecc : 1; 2563232812Sjmallett uint64_t vab_thresh : 4; 2564232812Sjmallett uint64_t ef_cnt : 7; 2565232812Sjmallett uint64_t ef_ena : 1; 2566232812Sjmallett uint64_t xmc_arb_mode : 1; 2567232812Sjmallett uint64_t rsp_arb_mode : 1; 2568232812Sjmallett uint64_t maxlfb : 4; 2569232812Sjmallett uint64_t maxvab : 4; 2570232812Sjmallett uint64_t discclk : 1; 2571232812Sjmallett uint64_t l2dfdbe : 1; 2572232812Sjmallett uint64_t l2dfsbe : 1; 2573232812Sjmallett uint64_t disstgl2i : 1; 2574232812Sjmallett uint64_t rdf_fast : 1; 2575232812Sjmallett uint64_t reserved_29_63 : 35; 2576232812Sjmallett#endif 2577232812Sjmallett } cn61xx; 2578232812Sjmallett struct cvmx_l2c_ctl_cn63xx { 2579232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2580215976Sjmallett uint64_t reserved_28_63 : 36; 2581215976Sjmallett uint64_t disstgl2i : 1; /**< Disable STGL2I's from changing the tags */ 2582215976Sjmallett uint64_t l2dfsbe : 1; /**< Force single bit ECC error on PL2 allocates (2) */ 2583215976Sjmallett uint64_t l2dfdbe : 1; /**< Force double bit ECC error on PL2 allocates (2) */ 2584215976Sjmallett uint64_t discclk : 1; /**< Disable conditional clocking in L2C PNR blocks */ 2585215976Sjmallett uint64_t maxvab : 4; /**< Maximum VABs in use at once 2586215976Sjmallett (0 means 16, 1-15 as expected) */ 2587215976Sjmallett uint64_t maxlfb : 4; /**< Maximum LFBs in use at once 2588215976Sjmallett (0 means 16, 1-15 as expected) */ 2589215976Sjmallett uint64_t rsp_arb_mode : 1; /**< Arbitration mode for RSC/RSD bus 2590215976Sjmallett == 0, round-robin 2591215976Sjmallett == 1, static priority 2592215976Sjmallett 1. IOR data 2593215976Sjmallett 2. STIN/FILLs 2594215976Sjmallett 3. STDN/SCDN/SCFL */ 2595215976Sjmallett uint64_t xmc_arb_mode : 1; /**< Arbitration mode for XMC QOS queues 2596215976Sjmallett == 0, fully determined through QOS 2597215976Sjmallett == 1, QOS0 highest priority, QOS1-3 use normal mode */ 2598215976Sjmallett uint64_t ef_ena : 1; /**< LMC early fill enable */ 2599215976Sjmallett uint64_t ef_cnt : 7; /**< LMC early fill count 2600215976Sjmallett Specifies the number of cycles after the first LMC 2601215976Sjmallett fill cycle to wait before requesting a fill on the 2602215976Sjmallett RSC/RSD bus. 2603215976Sjmallett // 7 dclks (we've received 1st out of 8 2604215976Sjmallett // by the time we start counting) 2605215976Sjmallett ef_cnt = (7 * dclk0_period) / rclk_period; 2606215976Sjmallett // + 1 rclk if the dclk and rclk edges don't 2607215976Sjmallett // stay in the same position 2608215976Sjmallett if ((dclk0_gen.period % rclk_gen.period) != 0) 2609215976Sjmallett ef_cnt = ef_cnt + 1; 2610215976Sjmallett // + 2 rclk synchronization uncertainty 2611215976Sjmallett ef_cnt = ef_cnt + 2; 2612215976Sjmallett // - 3 rclks to recognize first write 2613215976Sjmallett ef_cnt = ef_cnt - 3; 2614215976Sjmallett // + 3 rclks to perform first write 2615215976Sjmallett ef_cnt = ef_cnt + 3; 2616215976Sjmallett // - 9 rclks minimum latency from counter expire 2617215976Sjmallett // to final fbf read 2618215976Sjmallett ef_cnt = ef_cnt - 9; */ 2619215976Sjmallett uint64_t vab_thresh : 4; /**< VAB Threshold 2620215976Sjmallett When the number of valid VABs exceeds this number the 2621215976Sjmallett L2C increases the priority of all writes in the LMC. */ 2622215976Sjmallett uint64_t disecc : 1; /**< Tag and Data ECC Disable */ 2623215976Sjmallett uint64_t disidxalias : 1; /**< Index Alias Disable */ 2624215976Sjmallett#else 2625215976Sjmallett uint64_t disidxalias : 1; 2626215976Sjmallett uint64_t disecc : 1; 2627215976Sjmallett uint64_t vab_thresh : 4; 2628215976Sjmallett uint64_t ef_cnt : 7; 2629215976Sjmallett uint64_t ef_ena : 1; 2630215976Sjmallett uint64_t xmc_arb_mode : 1; 2631215976Sjmallett uint64_t rsp_arb_mode : 1; 2632215976Sjmallett uint64_t maxlfb : 4; 2633215976Sjmallett uint64_t maxvab : 4; 2634215976Sjmallett uint64_t discclk : 1; 2635215976Sjmallett uint64_t l2dfdbe : 1; 2636215976Sjmallett uint64_t l2dfsbe : 1; 2637215976Sjmallett uint64_t disstgl2i : 1; 2638215976Sjmallett uint64_t reserved_28_63 : 36; 2639215976Sjmallett#endif 2640232812Sjmallett } cn63xx; 2641232812Sjmallett struct cvmx_l2c_ctl_cn63xxp1 { 2642232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2643215976Sjmallett uint64_t reserved_25_63 : 39; 2644215976Sjmallett uint64_t discclk : 1; /**< Disable conditional clocking in L2C PNR blocks */ 2645215976Sjmallett uint64_t maxvab : 4; /**< Maximum VABs in use at once 2646215976Sjmallett (0 means 16, 1-15 as expected) */ 2647215976Sjmallett uint64_t maxlfb : 4; /**< Maximum LFBs in use at once 2648215976Sjmallett (0 means 16, 1-15 as expected) */ 2649215976Sjmallett uint64_t rsp_arb_mode : 1; /**< Arbitration mode for RSC/RSD bus 2650215976Sjmallett == 0, round-robin 2651215976Sjmallett == 1, static priority 2652215976Sjmallett 1. IOR data 2653215976Sjmallett 2. STIN/FILLs 2654215976Sjmallett 3. STDN/SCDN/SCFL */ 2655215976Sjmallett uint64_t xmc_arb_mode : 1; /**< Arbitration mode for XMC QOS queues 2656215976Sjmallett == 0, fully determined through QOS 2657215976Sjmallett == 1, QOS0 highest priority, QOS1-3 use normal mode */ 2658215976Sjmallett uint64_t ef_ena : 1; /**< LMC early fill enable */ 2659215976Sjmallett uint64_t ef_cnt : 7; /**< LMC early fill count 2660215976Sjmallett Specifies the number of cycles after the first LMC 2661215976Sjmallett fill cycle to wait before requesting a fill on the 2662215976Sjmallett RSC/RSD bus. 2663215976Sjmallett // 7 dclks (we've received 1st out of 8 2664215976Sjmallett // by the time we start counting) 2665215976Sjmallett ef_cnt = (7 * dclk0_period) / rclk_period; 2666215976Sjmallett // + 1 rclk if the dclk and rclk edges don't 2667215976Sjmallett // stay in the same position 2668215976Sjmallett if ((dclk0_gen.period % rclk_gen.period) != 0) 2669215976Sjmallett ef_cnt = ef_cnt + 1; 2670215976Sjmallett // + 2 rclk synchronization uncertainty 2671215976Sjmallett ef_cnt = ef_cnt + 2; 2672215976Sjmallett // - 3 rclks to recognize first write 2673215976Sjmallett ef_cnt = ef_cnt - 3; 2674215976Sjmallett // + 3 rclks to perform first write 2675215976Sjmallett ef_cnt = ef_cnt + 3; 2676215976Sjmallett // - 9 rclks minimum latency from counter expire 2677215976Sjmallett // to final fbf read 2678215976Sjmallett ef_cnt = ef_cnt - 9; */ 2679215976Sjmallett uint64_t vab_thresh : 4; /**< VAB Threshold 2680215976Sjmallett When the number of valid VABs exceeds this number the 2681215976Sjmallett L2C increases the priority of all writes in the LMC. */ 2682215976Sjmallett uint64_t disecc : 1; /**< Tag and Data ECC Disable */ 2683215976Sjmallett uint64_t disidxalias : 1; /**< Index Alias Disable */ 2684215976Sjmallett#else 2685215976Sjmallett uint64_t disidxalias : 1; 2686215976Sjmallett uint64_t disecc : 1; 2687215976Sjmallett uint64_t vab_thresh : 4; 2688215976Sjmallett uint64_t ef_cnt : 7; 2689215976Sjmallett uint64_t ef_ena : 1; 2690215976Sjmallett uint64_t xmc_arb_mode : 1; 2691215976Sjmallett uint64_t rsp_arb_mode : 1; 2692215976Sjmallett uint64_t maxlfb : 4; 2693215976Sjmallett uint64_t maxvab : 4; 2694215976Sjmallett uint64_t discclk : 1; 2695215976Sjmallett uint64_t reserved_25_63 : 39; 2696215976Sjmallett#endif 2697215976Sjmallett } cn63xxp1; 2698232812Sjmallett struct cvmx_l2c_ctl_cn61xx cn66xx; 2699232812Sjmallett struct cvmx_l2c_ctl_s cn68xx; 2700232812Sjmallett struct cvmx_l2c_ctl_cn63xx cn68xxp1; 2701232812Sjmallett struct cvmx_l2c_ctl_cn61xx cnf71xx; 2702215976Sjmallett}; 2703215976Sjmalletttypedef union cvmx_l2c_ctl cvmx_l2c_ctl_t; 2704215976Sjmallett 2705215976Sjmallett/** 2706215976Sjmallett * cvmx_l2c_dbg 2707215976Sjmallett * 2708215976Sjmallett * L2C_DBG = L2C DEBUG Register 2709215976Sjmallett * 2710215976Sjmallett * Description: L2C Tag/Data Store Debug Register 2711215976Sjmallett * 2712215976Sjmallett * Notes: 2713215976Sjmallett * (1) When using the L2T, L2D or FINV Debug probe feature, the LDD command WILL NOT update the DuTags. 2714215976Sjmallett * (2) L2T, L2D, FINV MUST BE mutually exclusive (only one set) 2715215976Sjmallett * (3) Force Invalidate is intended as a means for SW to invalidate the L2 Cache while also writing back 2716215976Sjmallett * dirty data to memory to maintain coherency. 2717215976Sjmallett * (4) L2 Cache Lock Down feature MUST BE disabled (L2C_LCKBASE[LCK_ENA]=0) if ANY of the L2C debug 2718215976Sjmallett * features (L2T, L2D, FINV) are enabled. 2719215976Sjmallett */ 2720232812Sjmallettunion cvmx_l2c_dbg { 2721215976Sjmallett uint64_t u64; 2722232812Sjmallett struct cvmx_l2c_dbg_s { 2723232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2724215976Sjmallett uint64_t reserved_15_63 : 49; 2725215976Sjmallett uint64_t lfb_enum : 4; /**< Specifies the LFB Entry# which is to be captured. */ 2726215976Sjmallett uint64_t lfb_dmp : 1; /**< LFB Dump Enable: When written(=1), the contents of 2727215976Sjmallett the LFB specified by LFB_ENUM[3:0] are captured 2728215976Sjmallett into the L2C_LFB(0/1/2) registers. 2729215976Sjmallett NOTE: Some fields of the LFB entry are unpredictable 2730215976Sjmallett and dependent on usage. This is only intended to be 2731215976Sjmallett used for HW debug. */ 2732215976Sjmallett uint64_t ppnum : 4; /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV] 2733215976Sjmallett is enabled, this field determines which one-of-16 2734215976Sjmallett PPs is selected as the diagnostic PP. */ 2735215976Sjmallett uint64_t set : 3; /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV] 2736215976Sjmallett is enabled, this field determines 1-of-n targeted 2737215976Sjmallett sets to act upon. 2738215976Sjmallett NOTE: L2C_DBG[SET] must never equal a crippled or 2739215976Sjmallett unusable set (see UMSK* registers and Cripple mode 2740215976Sjmallett fuses). */ 2741215976Sjmallett uint64_t finv : 1; /**< Flush-Invalidate. 2742215976Sjmallett When flush-invalidate is enable (FINV=1), all STF 2743215976Sjmallett (L1 store-miss) commands generated from the diagnostic PP 2744215976Sjmallett (L2C_DBG[PPNUM]) will invalidate the specified set 2745215976Sjmallett (L2C_DBG[SET]) at the index specified in the STF 2746215976Sjmallett address[17:7]. If a dirty block is detected (D=1), it is 2747215976Sjmallett written back to memory. The contents of the invalid 2748215976Sjmallett L2 Cache line is also 'scrubbed' with the STF write data. 2749215976Sjmallett NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in 2750215976Sjmallett STF address[17:7] refers to the 'aliased' address. 2751215976Sjmallett NOTE: An STF command with write data=ZEROES can be 2752215976Sjmallett generated by SW using the Prefetch instruction with 2753215976Sjmallett Hint=30d "prepare for Store", followed by a SYNCW. 2754215976Sjmallett What is seen at the L2C as an STF w/wrdcnt=0 with all 2755215976Sjmallett of its mask bits clear (indicates zero-fill data). 2756215976Sjmallett A flush-invalidate will 'force-hit' the L2 cache at 2757215976Sjmallett [index,set] and invalidate the entry (V=0/D=0/L=0/U=0). 2758215976Sjmallett If the cache block is dirty, it is also written back 2759215976Sjmallett to memory. The DuTag state is probed/updated as normal 2760215976Sjmallett for an STF request. 2761215976Sjmallett TYPICAL APPLICATIONS: 2762215976Sjmallett 1) L2 Tag/Data ECC SW Recovery 2763215976Sjmallett 2) Cache Unlocking 2764215976Sjmallett NOTE: If the cacheline had been previously LOCKED(L=1), 2765215976Sjmallett a flush-invalidate operation will explicitly UNLOCK 2766215976Sjmallett (L=0) the set/index specified. 2767215976Sjmallett NOTE: The diagnostic PP cores can generate STF 2768215976Sjmallett commands to the L2 Cache whenever all 128 bytes in a 2769215976Sjmallett block are written. SW must take this into consideration 2770215976Sjmallett to avoid 'errant' Flush-Invalidates. */ 2771215976Sjmallett uint64_t l2d : 1; /**< When enabled (and L2C_DBG[L2T]=0), fill data is 2772215976Sjmallett returned directly from the L2 Data Store 2773215976Sjmallett (regardless of hit/miss) when an LDD(L1 load-miss) command 2774215976Sjmallett is issued from a PP determined by the L2C_DBG[PPNUM] 2775215976Sjmallett field. The selected set# is determined by the 2776215976Sjmallett L2C_DBG[SET] field, and the index is determined 2777215976Sjmallett from the address[17:7] associated with the LDD 2778215976Sjmallett command. 2779215976Sjmallett This 'force-hit' will NOT alter the current L2 Tag 2780215976Sjmallett state OR the DuTag state. */ 2781215976Sjmallett uint64_t l2t : 1; /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:18]] 2782215976Sjmallett is returned on the data bus starting at +32(and +96) bytes 2783215976Sjmallett offset from the beginning of cacheline when an LDD 2784215976Sjmallett (L1 load-miss) command is issued from a PP determined by 2785215976Sjmallett the L2C_DBG[PPNUM] field. 2786215976Sjmallett The selected L2 set# is determined by the L2C_DBG[SET] 2787215976Sjmallett field, and the L2 index is determined from the 2788215976Sjmallett phys_addr[17:7] associated with the LDD command. 2789215976Sjmallett This 'L2 force-hit' will NOT alter the current L2 Tag 2790215976Sjmallett state OR the DuTag state. 2791215976Sjmallett NOTE: The diagnostic PP should issue a d-stream load 2792215976Sjmallett to an aligned cacheline+0x20(+0x60) in order to have the 2793215976Sjmallett return VDLUTAG information (in OW2/OW6) written directly 2794215976Sjmallett into the proper PP register. The diagnostic PP should also 2795215976Sjmallett flush it's local L1 cache after use(to ensure data 2796215976Sjmallett coherency). 2797215976Sjmallett NOTE: The position of the VDLUTAG data in the destination 2798215976Sjmallett register is dependent on the endian mode(big/little). 2799215976Sjmallett NOTE: N3K-Pass2 modification. (This bit's functionality 2800215976Sjmallett has changed since Pass1-in the following way). 2801215976Sjmallett NOTE: (For L2C BitMap testing of L2 Data Store OW ECC): 2802215976Sjmallett If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected 2803215976Sjmallett half cacheline (see: L2D_ERR[BMHCLSEL] is also 2804215976Sjmallett conditionally latched into the L2D_FSYN0/1 CSRs if an 2805215976Sjmallett LDD command is detected from the diagnostic PP(L2C_DBG[PPNUM]). */ 2806215976Sjmallett#else 2807215976Sjmallett uint64_t l2t : 1; 2808215976Sjmallett uint64_t l2d : 1; 2809215976Sjmallett uint64_t finv : 1; 2810215976Sjmallett uint64_t set : 3; 2811215976Sjmallett uint64_t ppnum : 4; 2812215976Sjmallett uint64_t lfb_dmp : 1; 2813215976Sjmallett uint64_t lfb_enum : 4; 2814215976Sjmallett uint64_t reserved_15_63 : 49; 2815215976Sjmallett#endif 2816215976Sjmallett } s; 2817232812Sjmallett struct cvmx_l2c_dbg_cn30xx { 2818232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2819215976Sjmallett uint64_t reserved_13_63 : 51; 2820215976Sjmallett uint64_t lfb_enum : 2; /**< Specifies the LFB Entry# which is to be captured. */ 2821215976Sjmallett uint64_t lfb_dmp : 1; /**< LFB Dump Enable: When written(=1), the contents of 2822215976Sjmallett the LFB specified by LFB_ENUM are captured 2823215976Sjmallett into the L2C_LFB(0/1/2) registers. 2824215976Sjmallett NOTE: Some fields of the LFB entry are unpredictable 2825215976Sjmallett and dependent on usage. This is only intended to be 2826215976Sjmallett used for HW debug. */ 2827215976Sjmallett uint64_t reserved_7_9 : 3; 2828215976Sjmallett uint64_t ppnum : 1; /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV] 2829215976Sjmallett is enabled, this field determines which 2830215976Sjmallett PP is selected as the diagnostic PP. 2831215976Sjmallett NOTE: For CN30XX single core PPNUM=0 (MBZ) */ 2832215976Sjmallett uint64_t reserved_5_5 : 1; 2833215976Sjmallett uint64_t set : 2; /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV] 2834215976Sjmallett is enabled, this field determines 1-of-n targeted 2835215976Sjmallett sets to act upon. 2836215976Sjmallett NOTE: L2C_DBG[SET] must never equal a crippled or 2837215976Sjmallett unusable set (see UMSK* registers and Cripple mode 2838215976Sjmallett fuses). */ 2839215976Sjmallett uint64_t finv : 1; /**< Flush-Invalidate. 2840215976Sjmallett When flush-invalidate is enable (FINV=1), all STF 2841215976Sjmallett (L1 store-miss) commands generated from the PP will invalidate 2842215976Sjmallett the specified set(L2C_DBG[SET]) at the index specified 2843215976Sjmallett in the STF address[14:7]. If a dirty block is detected(D=1), 2844215976Sjmallett it is written back to memory. The contents of the invalid 2845215976Sjmallett L2 Cache line is also 'scrubbed' with the STF write data. 2846215976Sjmallett NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in 2847215976Sjmallett STF address[14:7] refers to the 'aliased' address. 2848215976Sjmallett NOTE: An STF command with write data=ZEROES can be 2849215976Sjmallett generated by SW using the Prefetch instruction with 2850215976Sjmallett Hint=30d "prepare for Store", followed by a SYNCW. 2851215976Sjmallett What is seen at the L2C as an STF w/wrdcnt=0 with all 2852215976Sjmallett of its mask bits clear (indicates zero-fill data). 2853215976Sjmallett A flush-invalidate will 'force-hit' the L2 cache at 2854215976Sjmallett [index,set] and invalidate the entry (V=0/D=0/L=0/U=0). 2855215976Sjmallett If the cache block is dirty, it is also written back 2856215976Sjmallett to memory. The DuTag state is probed/updated as normal 2857215976Sjmallett for an STF request. 2858215976Sjmallett TYPICAL APPLICATIONS: 2859215976Sjmallett 1) L2 Tag/Data ECC SW Recovery 2860215976Sjmallett 2) Cache Unlocking 2861215976Sjmallett NOTE: If the cacheline had been previously LOCKED(L=1), 2862215976Sjmallett a flush-invalidate operation will explicitly UNLOCK 2863215976Sjmallett (L=0) the set/index specified. 2864215976Sjmallett NOTE: The PP can generate STF(L1 store-miss) 2865215976Sjmallett commands to the L2 Cache whenever all 128 bytes in a 2866215976Sjmallett block are written. SW must take this into consideration 2867215976Sjmallett to avoid 'errant' Flush-Invalidates. */ 2868215976Sjmallett uint64_t l2d : 1; /**< When enabled (and L2C_DBG[L2T]=0), fill data is 2869215976Sjmallett returned directly from the L2 Data Store 2870215976Sjmallett (regardless of hit/miss) when an LDD(L1 load-miss) 2871215976Sjmallett command is issued from the PP. 2872215976Sjmallett The selected set# is determined by the 2873215976Sjmallett L2C_DBG[SET] field, and the index is determined 2874215976Sjmallett from the address[14:7] associated with the LDD 2875215976Sjmallett command. 2876215976Sjmallett This 'force-hit' will NOT alter the current L2 Tag 2877215976Sjmallett state OR the DuTag state. */ 2878215976Sjmallett uint64_t l2t : 1; /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:15]] 2879215976Sjmallett is returned on the data bus starting at +32(and +96) bytes 2880215976Sjmallett offset from the beginning of cacheline when an LDD 2881215976Sjmallett (L1 load-miss) command is issued from the PP. 2882215976Sjmallett The selected L2 set# is determined by the L2C_DBG[SET] 2883215976Sjmallett field, and the L2 index is determined from the 2884215976Sjmallett phys_addr[14:7] associated with the LDD command. 2885215976Sjmallett This 'L2 force-hit' will NOT alter the current L2 Tag 2886215976Sjmallett state OR the DuTag state. 2887215976Sjmallett NOTE: The diagnostic PP should issue a d-stream load 2888215976Sjmallett to an aligned cacheline+0x20(+0x60) in order to have the 2889215976Sjmallett return VDLUTAG information (in OW2/OW6) written directly 2890215976Sjmallett into the proper PP register. The diagnostic PP should also 2891215976Sjmallett flush it's local L1 cache after use(to ensure data 2892215976Sjmallett coherency). 2893215976Sjmallett NOTE: The position of the VDLUTAG data in the destination 2894215976Sjmallett register is dependent on the endian mode(big/little). 2895215976Sjmallett NOTE: (For L2C BitMap testing of L2 Data Store OW ECC): 2896215976Sjmallett If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected 2897215976Sjmallett half cacheline (see: L2D_ERR[BMHCLSEL] is also 2898215976Sjmallett conditionally latched into the L2D_FSYN0/1 CSRs if an 2899215976Sjmallett LDD(L1 load-miss) is detected. */ 2900215976Sjmallett#else 2901215976Sjmallett uint64_t l2t : 1; 2902215976Sjmallett uint64_t l2d : 1; 2903215976Sjmallett uint64_t finv : 1; 2904215976Sjmallett uint64_t set : 2; 2905215976Sjmallett uint64_t reserved_5_5 : 1; 2906215976Sjmallett uint64_t ppnum : 1; 2907215976Sjmallett uint64_t reserved_7_9 : 3; 2908215976Sjmallett uint64_t lfb_dmp : 1; 2909215976Sjmallett uint64_t lfb_enum : 2; 2910215976Sjmallett uint64_t reserved_13_63 : 51; 2911215976Sjmallett#endif 2912215976Sjmallett } cn30xx; 2913232812Sjmallett struct cvmx_l2c_dbg_cn31xx { 2914232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2915215976Sjmallett uint64_t reserved_14_63 : 50; 2916215976Sjmallett uint64_t lfb_enum : 3; /**< Specifies the LFB Entry# which is to be captured. */ 2917215976Sjmallett uint64_t lfb_dmp : 1; /**< LFB Dump Enable: When written(=1), the contents of 2918215976Sjmallett the LFB specified by LFB_ENUM are captured 2919215976Sjmallett into the L2C_LFB(0/1/2) registers. 2920215976Sjmallett NOTE: Some fields of the LFB entry are unpredictable 2921215976Sjmallett and dependent on usage. This is only intended to be 2922215976Sjmallett used for HW debug. */ 2923215976Sjmallett uint64_t reserved_7_9 : 3; 2924215976Sjmallett uint64_t ppnum : 1; /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV] 2925215976Sjmallett is enabled, this field determines which 2926215976Sjmallett PP is selected as the diagnostic PP. */ 2927215976Sjmallett uint64_t reserved_5_5 : 1; 2928215976Sjmallett uint64_t set : 2; /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV] 2929215976Sjmallett is enabled, this field determines 1-of-n targeted 2930215976Sjmallett sets to act upon. 2931215976Sjmallett NOTE: L2C_DBG[SET] must never equal a crippled or 2932215976Sjmallett unusable set (see UMSK* registers and Cripple mode 2933215976Sjmallett fuses). */ 2934215976Sjmallett uint64_t finv : 1; /**< Flush-Invalidate. 2935215976Sjmallett When flush-invalidate is enable (FINV=1), all STF 2936215976Sjmallett (L1 store-miss) commands generated from the diagnostic PP 2937215976Sjmallett (L2C_DBG[PPNUM]) will invalidate the specified set 2938215976Sjmallett (L2C_DBG[SET]) at the index specified in the STF 2939215976Sjmallett address[15:7]. If a dirty block is detected (D=1), it is 2940215976Sjmallett written back to memory. The contents of the invalid 2941215976Sjmallett L2 Cache line is also 'scrubbed' with the STF write data. 2942215976Sjmallett NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in 2943215976Sjmallett STF address[15:7] refers to the 'aliased' address. 2944215976Sjmallett NOTE: An STF command with write data=ZEROES can be 2945215976Sjmallett generated by SW using the Prefetch instruction with 2946215976Sjmallett Hint=30d "prepare for Store", followed by a SYNCW. 2947215976Sjmallett What is seen at the L2C as an STF w/wrdcnt=0 with all 2948215976Sjmallett of its mask bits clear (indicates zero-fill data). 2949215976Sjmallett A flush-invalidate will 'force-hit' the L2 cache at 2950215976Sjmallett [index,set] and invalidate the entry (V=0/D=0/L=0/U=0). 2951215976Sjmallett If the cache block is dirty, it is also written back 2952215976Sjmallett to memory. The DuTag state is probed/updated as normal 2953215976Sjmallett for an STF request. 2954215976Sjmallett TYPICAL APPLICATIONS: 2955215976Sjmallett 1) L2 Tag/Data ECC SW Recovery 2956215976Sjmallett 2) Cache Unlocking 2957215976Sjmallett NOTE: If the cacheline had been previously LOCKED(L=1), 2958215976Sjmallett a flush-invalidate operation will explicitly UNLOCK 2959215976Sjmallett (L=0) the set/index specified. 2960215976Sjmallett NOTE: The diagnostic PP cores can generate STF(L1 store-miss) 2961215976Sjmallett commands to the L2 Cache whenever all 128 bytes in a 2962215976Sjmallett block are written. SW must take this into consideration 2963215976Sjmallett to avoid 'errant' Flush-Invalidates. */ 2964215976Sjmallett uint64_t l2d : 1; /**< When enabled (and L2C_DBG[L2T]=0), fill data is 2965215976Sjmallett returned directly from the L2 Data Store 2966215976Sjmallett (regardless of hit/miss) when an LDD(L1 load-miss) 2967215976Sjmallett command is issued from a PP determined by the 2968215976Sjmallett L2C_DBG[PPNUM] field. The selected set# is determined 2969215976Sjmallett by the L2C_DBG[SET] field, and the index is determined 2970215976Sjmallett from the address[15:7] associated with the LDD command. 2971215976Sjmallett This 'L2 force-hit' will NOT alter the current L2 Tag 2972215976Sjmallett state OR the DuTag state. */ 2973215976Sjmallett uint64_t l2t : 1; /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:16]] 2974215976Sjmallett is returned on the data bus starting at +32(and +96) bytes 2975215976Sjmallett offset from the beginning of cacheline when an LDD 2976215976Sjmallett (L1 load-miss) command is issued from a PP determined by 2977215976Sjmallett the L2C_DBG[PPNUM] field. 2978215976Sjmallett The selected L2 set# is determined by the L2C_DBG[SET] 2979215976Sjmallett field, and the L2 index is determined from the 2980215976Sjmallett phys_addr[15:7] associated with the LDD command. 2981215976Sjmallett This 'L2 force-hit' will NOT alter the current L2 Tag 2982215976Sjmallett state OR the DuTag state. 2983215976Sjmallett NOTE: The diagnostic PP should issue a d-stream load 2984215976Sjmallett to an aligned cacheline+0x20(+0x60) in order to have the 2985215976Sjmallett return VDLUTAG information (in OW2/OW6) written directly 2986215976Sjmallett into the proper PP register. The diagnostic PP should also 2987215976Sjmallett flush it's local L1 cache after use(to ensure data 2988215976Sjmallett coherency). 2989215976Sjmallett NOTE: The position of the VDLUTAG data in the destination 2990215976Sjmallett register is dependent on the endian mode(big/little). 2991215976Sjmallett NOTE: (For L2C BitMap testing of L2 Data Store OW ECC): 2992215976Sjmallett If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected 2993215976Sjmallett half cacheline (see: L2D_ERR[BMHCLSEL] is also 2994215976Sjmallett conditionally latched into the L2D_FSYN0/1 CSRs if an 2995215976Sjmallett LDD(L1 load-miss) is detected from the diagnostic PP 2996215976Sjmallett (L2C_DBG[PPNUM]). */ 2997215976Sjmallett#else 2998215976Sjmallett uint64_t l2t : 1; 2999215976Sjmallett uint64_t l2d : 1; 3000215976Sjmallett uint64_t finv : 1; 3001215976Sjmallett uint64_t set : 2; 3002215976Sjmallett uint64_t reserved_5_5 : 1; 3003215976Sjmallett uint64_t ppnum : 1; 3004215976Sjmallett uint64_t reserved_7_9 : 3; 3005215976Sjmallett uint64_t lfb_dmp : 1; 3006215976Sjmallett uint64_t lfb_enum : 3; 3007215976Sjmallett uint64_t reserved_14_63 : 50; 3008215976Sjmallett#endif 3009215976Sjmallett } cn31xx; 3010215976Sjmallett struct cvmx_l2c_dbg_s cn38xx; 3011215976Sjmallett struct cvmx_l2c_dbg_s cn38xxp2; 3012232812Sjmallett struct cvmx_l2c_dbg_cn50xx { 3013232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3014215976Sjmallett uint64_t reserved_14_63 : 50; 3015215976Sjmallett uint64_t lfb_enum : 3; /**< Specifies the LFB Entry# which is to be captured. */ 3016215976Sjmallett uint64_t lfb_dmp : 1; /**< LFB Dump Enable: When written(=1), the contents of 3017215976Sjmallett the LFB specified by LFB_ENUM[2:0] are captured 3018215976Sjmallett into the L2C_LFB(0/1/2) registers. 3019215976Sjmallett NOTE: Some fields of the LFB entry are unpredictable 3020215976Sjmallett and dependent on usage. This is only intended to be 3021215976Sjmallett used for HW debug. */ 3022215976Sjmallett uint64_t reserved_7_9 : 3; 3023215976Sjmallett uint64_t ppnum : 1; /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV] 3024215976Sjmallett is enabled, this field determines which 1-of-2 3025215976Sjmallett PPs is selected as the diagnostic PP. */ 3026215976Sjmallett uint64_t set : 3; /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV] 3027215976Sjmallett is enabled, this field determines 1-of-n targeted 3028215976Sjmallett sets to act upon. 3029215976Sjmallett NOTE: L2C_DBG[SET] must never equal a crippled or 3030215976Sjmallett unusable set (see UMSK* registers and Cripple mode 3031215976Sjmallett fuses). */ 3032215976Sjmallett uint64_t finv : 1; /**< Flush-Invalidate. 3033215976Sjmallett When flush-invalidate is enable (FINV=1), all STF 3034215976Sjmallett (L1 store-miss) commands generated from the diagnostic PP 3035215976Sjmallett (L2C_DBG[PPNUM]) will invalidate the specified set 3036215976Sjmallett (L2C_DBG[SET]) at the index specified in the STF 3037215976Sjmallett address[13:7]. If a dirty block is detected (D=1), it is 3038215976Sjmallett written back to memory. The contents of the invalid 3039215976Sjmallett L2 Cache line is also 'scrubbed' with the STF write data. 3040215976Sjmallett NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in 3041215976Sjmallett STF address[13:7] refers to the 'aliased' address. 3042215976Sjmallett NOTE: An STF command with write data=ZEROES can be 3043215976Sjmallett generated by SW using the Prefetch instruction with 3044215976Sjmallett Hint=30d "prepare for Store", followed by a SYNCW. 3045215976Sjmallett What is seen at the L2C as an STF w/wrdcnt=0 with all 3046215976Sjmallett of its mask bits clear (indicates zero-fill data). 3047215976Sjmallett A flush-invalidate will 'force-hit' the L2 cache at 3048215976Sjmallett [index,set] and invalidate the entry (V=0/D=0/L=0/U=0). 3049215976Sjmallett If the cache block is dirty, it is also written back 3050215976Sjmallett to memory. The DuTag state is probed/updated as normal 3051215976Sjmallett for an STF request. 3052215976Sjmallett TYPICAL APPLICATIONS: 3053215976Sjmallett 1) L2 Tag/Data ECC SW Recovery 3054215976Sjmallett 2) Cache Unlocking 3055215976Sjmallett NOTE: If the cacheline had been previously LOCKED(L=1), 3056215976Sjmallett a flush-invalidate operation will explicitly UNLOCK 3057215976Sjmallett (L=0) the set/index specified. 3058215976Sjmallett NOTE: The diagnostic PP cores can generate STF 3059215976Sjmallett commands to the L2 Cache whenever all 128 bytes in a 3060215976Sjmallett block are written. SW must take this into consideration 3061215976Sjmallett to avoid 'errant' Flush-Invalidates. */ 3062215976Sjmallett uint64_t l2d : 1; /**< When enabled (and L2C_DBG[L2T]=0), fill data is 3063215976Sjmallett returned directly from the L2 Data Store 3064215976Sjmallett (regardless of hit/miss) when an LDD(L1 load-miss) command 3065215976Sjmallett is issued from a PP determined by the L2C_DBG[PPNUM] 3066215976Sjmallett field. The selected set# is determined by the 3067215976Sjmallett L2C_DBG[SET] field, and the index is determined 3068215976Sjmallett from the address[13:7] associated with the LDD 3069215976Sjmallett command. 3070215976Sjmallett This 'force-hit' will NOT alter the current L2 Tag 3071215976Sjmallett state OR the DuTag state. */ 3072215976Sjmallett uint64_t l2t : 1; /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:14]] 3073215976Sjmallett is returned on the data bus starting at +32(and +96) bytes 3074215976Sjmallett offset from the beginning of cacheline when an LDD 3075215976Sjmallett (L1 load-miss) command is issued from a PP determined by 3076215976Sjmallett the L2C_DBG[PPNUM] field. 3077215976Sjmallett The selected L2 set# is determined by the L2C_DBG[SET] 3078215976Sjmallett field, and the L2 index is determined from the 3079215976Sjmallett phys_addr[13:7] associated with the LDD command. 3080215976Sjmallett This 'L2 force-hit' will NOT alter the current L2 Tag 3081215976Sjmallett state OR the DuTag state. 3082215976Sjmallett NOTE: The diagnostic PP should issue a d-stream load 3083215976Sjmallett to an aligned cacheline+0x20(+0x60) in order to have the 3084215976Sjmallett return VDLUTAG information (in OW2/OW6) written directly 3085215976Sjmallett into the proper PP register. The diagnostic PP should also 3086215976Sjmallett flush it's local L1 cache after use(to ensure data 3087215976Sjmallett coherency). 3088215976Sjmallett NOTE: The position of the VDLUTAG data in the destination 3089215976Sjmallett register is dependent on the endian mode(big/little). 3090215976Sjmallett NOTE: (For L2C BitMap testing of L2 Data Store OW ECC): 3091215976Sjmallett If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected 3092215976Sjmallett half cacheline (see: L2D_ERR[BMHCLSEL] is also 3093215976Sjmallett conditionally latched into the L2D_FSYN0/1 CSRs if an 3094215976Sjmallett LDD command is detected from the diagnostic PP(L2C_DBG[PPNUM]). */ 3095215976Sjmallett#else 3096215976Sjmallett uint64_t l2t : 1; 3097215976Sjmallett uint64_t l2d : 1; 3098215976Sjmallett uint64_t finv : 1; 3099215976Sjmallett uint64_t set : 3; 3100215976Sjmallett uint64_t ppnum : 1; 3101215976Sjmallett uint64_t reserved_7_9 : 3; 3102215976Sjmallett uint64_t lfb_dmp : 1; 3103215976Sjmallett uint64_t lfb_enum : 3; 3104215976Sjmallett uint64_t reserved_14_63 : 50; 3105215976Sjmallett#endif 3106215976Sjmallett } cn50xx; 3107232812Sjmallett struct cvmx_l2c_dbg_cn52xx { 3108232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3109215976Sjmallett uint64_t reserved_14_63 : 50; 3110215976Sjmallett uint64_t lfb_enum : 3; /**< Specifies the LFB Entry# which is to be captured. */ 3111215976Sjmallett uint64_t lfb_dmp : 1; /**< LFB Dump Enable: When written(=1), the contents of 3112215976Sjmallett the LFB specified by LFB_ENUM[2:0] are captured 3113215976Sjmallett into the L2C_LFB(0/1/2) registers. 3114215976Sjmallett NOTE: Some fields of the LFB entry are unpredictable 3115215976Sjmallett and dependent on usage. This is only intended to be 3116215976Sjmallett used for HW debug. */ 3117215976Sjmallett uint64_t reserved_8_9 : 2; 3118215976Sjmallett uint64_t ppnum : 2; /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV] 3119215976Sjmallett is enabled, this field determines which 1-of-4 3120215976Sjmallett PPs is selected as the diagnostic PP. */ 3121215976Sjmallett uint64_t set : 3; /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV] 3122215976Sjmallett is enabled, this field determines 1-of-n targeted 3123215976Sjmallett sets to act upon. 3124215976Sjmallett NOTE: L2C_DBG[SET] must never equal a crippled or 3125215976Sjmallett unusable set (see UMSK* registers and Cripple mode 3126215976Sjmallett fuses). */ 3127215976Sjmallett uint64_t finv : 1; /**< Flush-Invalidate. 3128215976Sjmallett When flush-invalidate is enable (FINV=1), all STF 3129215976Sjmallett (L1 store-miss) commands generated from the diagnostic PP 3130215976Sjmallett (L2C_DBG[PPNUM]) will invalidate the specified set 3131215976Sjmallett (L2C_DBG[SET]) at the index specified in the STF 3132215976Sjmallett address[15:7]. If a dirty block is detected (D=1), it is 3133215976Sjmallett written back to memory. The contents of the invalid 3134215976Sjmallett L2 Cache line is also 'scrubbed' with the STF write data. 3135215976Sjmallett NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in 3136215976Sjmallett STF address[15:7] refers to the 'aliased' address. 3137215976Sjmallett NOTE: An STF command with write data=ZEROES can be 3138215976Sjmallett generated by SW using the Prefetch instruction with 3139215976Sjmallett Hint=30d "prepare for Store", followed by a SYNCW. 3140215976Sjmallett What is seen at the L2C as an STF w/wrdcnt=0 with all 3141215976Sjmallett of its mask bits clear (indicates zero-fill data). 3142215976Sjmallett A flush-invalidate will 'force-hit' the L2 cache at 3143215976Sjmallett [index,set] and invalidate the entry (V=0/D=0/L=0/U=0). 3144215976Sjmallett If the cache block is dirty, it is also written back 3145215976Sjmallett to memory. The DuTag state is probed/updated as normal 3146215976Sjmallett for an STF request. 3147215976Sjmallett TYPICAL APPLICATIONS: 3148215976Sjmallett 1) L2 Tag/Data ECC SW Recovery 3149215976Sjmallett 2) Cache Unlocking 3150215976Sjmallett NOTE: If the cacheline had been previously LOCKED(L=1), 3151215976Sjmallett a flush-invalidate operation will explicitly UNLOCK 3152215976Sjmallett (L=0) the set/index specified. 3153215976Sjmallett NOTE: The diagnostic PP cores can generate STF 3154215976Sjmallett commands to the L2 Cache whenever all 128 bytes in a 3155215976Sjmallett block are written. SW must take this into consideration 3156215976Sjmallett to avoid 'errant' Flush-Invalidates. */ 3157215976Sjmallett uint64_t l2d : 1; /**< When enabled (and L2C_DBG[L2T]=0), fill data is 3158215976Sjmallett returned directly from the L2 Data Store 3159215976Sjmallett (regardless of hit/miss) when an LDD(L1 load-miss) command 3160215976Sjmallett is issued from a PP determined by the L2C_DBG[PPNUM] 3161215976Sjmallett field. The selected set# is determined by the 3162215976Sjmallett L2C_DBG[SET] field, and the index is determined 3163215976Sjmallett from the address[15:7] associated with the LDD 3164215976Sjmallett command. 3165215976Sjmallett This 'force-hit' will NOT alter the current L2 Tag 3166215976Sjmallett state OR the DuTag state. */ 3167215976Sjmallett uint64_t l2t : 1; /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:16]] 3168215976Sjmallett is returned on the data bus starting at +32(and +96) bytes 3169215976Sjmallett offset from the beginning of cacheline when an LDD 3170215976Sjmallett (L1 load-miss) command is issued from a PP determined by 3171215976Sjmallett the L2C_DBG[PPNUM] field. 3172215976Sjmallett The selected L2 set# is determined by the L2C_DBG[SET] 3173215976Sjmallett field, and the L2 index is determined from the 3174215976Sjmallett phys_addr[15:7] associated with the LDD command. 3175215976Sjmallett This 'L2 force-hit' will NOT alter the current L2 Tag 3176215976Sjmallett state OR the DuTag state. 3177215976Sjmallett NOTE: The diagnostic PP should issue a d-stream load 3178215976Sjmallett to an aligned cacheline+0x20(+0x60) in order to have the 3179215976Sjmallett return VDLUTAG information (in OW2/OW6) written directly 3180215976Sjmallett into the proper PP register. The diagnostic PP should also 3181215976Sjmallett flush it's local L1 cache after use(to ensure data 3182215976Sjmallett coherency). 3183215976Sjmallett NOTE: The position of the VDLUTAG data in the destination 3184215976Sjmallett register is dependent on the endian mode(big/little). 3185215976Sjmallett NOTE: (For L2C BitMap testing of L2 Data Store OW ECC): 3186215976Sjmallett If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected 3187215976Sjmallett half cacheline (see: L2D_ERR[BMHCLSEL] is also 3188215976Sjmallett conditionally latched into the L2D_FSYN0/1 CSRs if an 3189215976Sjmallett LDD command is detected from the diagnostic PP(L2C_DBG[PPNUM]). */ 3190215976Sjmallett#else 3191215976Sjmallett uint64_t l2t : 1; 3192215976Sjmallett uint64_t l2d : 1; 3193215976Sjmallett uint64_t finv : 1; 3194215976Sjmallett uint64_t set : 3; 3195215976Sjmallett uint64_t ppnum : 2; 3196215976Sjmallett uint64_t reserved_8_9 : 2; 3197215976Sjmallett uint64_t lfb_dmp : 1; 3198215976Sjmallett uint64_t lfb_enum : 3; 3199215976Sjmallett uint64_t reserved_14_63 : 50; 3200215976Sjmallett#endif 3201215976Sjmallett } cn52xx; 3202215976Sjmallett struct cvmx_l2c_dbg_cn52xx cn52xxp1; 3203215976Sjmallett struct cvmx_l2c_dbg_s cn56xx; 3204215976Sjmallett struct cvmx_l2c_dbg_s cn56xxp1; 3205215976Sjmallett struct cvmx_l2c_dbg_s cn58xx; 3206215976Sjmallett struct cvmx_l2c_dbg_s cn58xxp1; 3207215976Sjmallett}; 3208215976Sjmalletttypedef union cvmx_l2c_dbg cvmx_l2c_dbg_t; 3209215976Sjmallett 3210215976Sjmallett/** 3211215976Sjmallett * cvmx_l2c_dut 3212215976Sjmallett * 3213215976Sjmallett * L2C_DUT = L2C DUTAG Register 3214215976Sjmallett * 3215215976Sjmallett * Description: L2C Duplicate Tag State Register 3216215976Sjmallett * 3217215976Sjmallett * Notes: 3218215976Sjmallett * (1) When using the L2T, L2D or FINV Debug probe feature, an LDD command issued by the diagnostic PP 3219215976Sjmallett * WILL NOT update the DuTags. 3220215976Sjmallett * (2) L2T, L2D, FINV MUST BE mutually exclusive (only one enabled at a time). 3221215976Sjmallett * (3) Force Invalidate is intended as a means for SW to invalidate the L2 Cache while also writing back 3222215976Sjmallett * dirty data to memory to maintain coherency. (A side effect of FINV is that an LDD L2 fill is 3223215976Sjmallett * launched which fills data into the L2 DS). 3224215976Sjmallett */ 3225232812Sjmallettunion cvmx_l2c_dut { 3226215976Sjmallett uint64_t u64; 3227232812Sjmallett struct cvmx_l2c_dut_s { 3228232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3229215976Sjmallett uint64_t reserved_32_63 : 32; 3230215976Sjmallett uint64_t dtena : 1; /**< DuTag Diagnostic read enable. 3231215976Sjmallett When L2C_DUT[DTENA]=1, all LDD(L1 load-miss) 3232215976Sjmallett commands issued from the diagnostic PP 3233215976Sjmallett (L2C_DBG[PPNUM]) will capture the DuTag state (V|L1TAG) 3234215976Sjmallett of the PP#(specified in the LDD address[29:26] into 3235215976Sjmallett the L2C_DUT CSR register. This allows the diagPP to 3236215976Sjmallett read ALL DuTags (from any PP). 3237215976Sjmallett The DuTag Set# to capture is extracted from the LDD 3238215976Sjmallett address[25:20]. The diagnostic PP would issue the 3239215976Sjmallett LDD then read the L2C_DUT register (one at a time). 3240215976Sjmallett This LDD 'L2 force-hit' will NOT alter the current L2 3241215976Sjmallett Tag State OR the DuTag state. 3242215976Sjmallett NOTE: For CN58XX the DuTag SIZE has doubled (to 16KB) 3243215976Sjmallett where each DuTag is organized as 2x 64-way entries. 3244215976Sjmallett The LDD address[7] determines which 1(of-2) internal 3245215976Sjmallett 64-ways to select. 3246215976Sjmallett The fill data is returned directly from the L2 Data 3247215976Sjmallett Store(regardless of hit/miss) when an LDD command 3248215976Sjmallett is issued from a PP determined by the L2C_DBG[PPNUM] 3249215976Sjmallett field. The selected L2 Set# is determined by the 3250215976Sjmallett L2C_DBG[SET] field, and the index is determined 3251215976Sjmallett from the address[17:7] associated with the LDD 3252215976Sjmallett command. 3253215976Sjmallett This 'L2 force-hit' will NOT alter the current L2 Tag 3254215976Sjmallett state OR the DuTag state. 3255215976Sjmallett NOTE: In order for the DiagPP to generate an LDD command 3256215976Sjmallett to the L2C, it must first force an L1 Dcache flush. */ 3257215976Sjmallett uint64_t reserved_30_30 : 1; 3258215976Sjmallett uint64_t dt_vld : 1; /**< Duplicate L1 Tag Valid bit latched in for previous 3259215976Sjmallett LDD(L1 load-miss) command sourced by diagnostic PP. */ 3260215976Sjmallett uint64_t dt_tag : 29; /**< Duplicate L1 Tag[35:7] latched in for previous 3261215976Sjmallett LDD(L1 load-miss) command sourced by diagnostic PP. */ 3262215976Sjmallett#else 3263215976Sjmallett uint64_t dt_tag : 29; 3264215976Sjmallett uint64_t dt_vld : 1; 3265215976Sjmallett uint64_t reserved_30_30 : 1; 3266215976Sjmallett uint64_t dtena : 1; 3267215976Sjmallett uint64_t reserved_32_63 : 32; 3268215976Sjmallett#endif 3269215976Sjmallett } s; 3270215976Sjmallett struct cvmx_l2c_dut_s cn30xx; 3271215976Sjmallett struct cvmx_l2c_dut_s cn31xx; 3272215976Sjmallett struct cvmx_l2c_dut_s cn38xx; 3273215976Sjmallett struct cvmx_l2c_dut_s cn38xxp2; 3274215976Sjmallett struct cvmx_l2c_dut_s cn50xx; 3275215976Sjmallett struct cvmx_l2c_dut_s cn52xx; 3276215976Sjmallett struct cvmx_l2c_dut_s cn52xxp1; 3277215976Sjmallett struct cvmx_l2c_dut_s cn56xx; 3278215976Sjmallett struct cvmx_l2c_dut_s cn56xxp1; 3279215976Sjmallett struct cvmx_l2c_dut_s cn58xx; 3280215976Sjmallett struct cvmx_l2c_dut_s cn58xxp1; 3281215976Sjmallett}; 3282215976Sjmalletttypedef union cvmx_l2c_dut cvmx_l2c_dut_t; 3283215976Sjmallett 3284215976Sjmallett/** 3285215976Sjmallett * cvmx_l2c_dut_map# 3286215976Sjmallett * 3287215976Sjmallett * L2C_DUT_MAP = L2C DUT memory map region 3288215976Sjmallett * 3289215976Sjmallett * Description: Address of the start of the region mapped to the duplicate tag. Can be used to read 3290215976Sjmallett * and write the raw duplicate tag CAM. Writes should be used only with great care as they can easily 3291215976Sjmallett * destroy the coherency of the memory system. In any case this region is expected to only be used 3292215976Sjmallett * for debug. 3293215976Sjmallett * 3294215976Sjmallett * This base address should be combined with PP virtual ID, L1 way and L1 set to produce the final 3295215976Sjmallett * address as follows: 3296232812Sjmallett * addr<63:13> L2C_DUT_MAP<63:13> 3297232812Sjmallett * addr<12:11> PP VID 3298215976Sjmallett * addr<10:6> L1 way 3299215976Sjmallett * addr<5:3> L1 set 3300215976Sjmallett * addr<2:0> UNUSED 3301215976Sjmallett * 3302215976Sjmallett * Notes: 3303215976Sjmallett * (1) The tag is 37:10 from the 38-bit OCTEON physical address after hole removal. (The hole is between DR0 3304215976Sjmallett * and DR1. Remove the hole by subtracting 256MB from 38-bit OCTEON L2/DRAM physical addresses >= 512 MB.) 3305215976Sjmallett */ 3306232812Sjmallettunion cvmx_l2c_dut_mapx { 3307215976Sjmallett uint64_t u64; 3308232812Sjmallett struct cvmx_l2c_dut_mapx_s { 3309232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3310215976Sjmallett uint64_t reserved_38_63 : 26; 3311215976Sjmallett uint64_t tag : 28; /**< The tag value (see Note 1) */ 3312215976Sjmallett uint64_t reserved_1_9 : 9; 3313215976Sjmallett uint64_t valid : 1; /**< The valid bit */ 3314215976Sjmallett#else 3315215976Sjmallett uint64_t valid : 1; 3316215976Sjmallett uint64_t reserved_1_9 : 9; 3317215976Sjmallett uint64_t tag : 28; 3318215976Sjmallett uint64_t reserved_38_63 : 26; 3319215976Sjmallett#endif 3320215976Sjmallett } s; 3321232812Sjmallett struct cvmx_l2c_dut_mapx_s cn61xx; 3322215976Sjmallett struct cvmx_l2c_dut_mapx_s cn63xx; 3323215976Sjmallett struct cvmx_l2c_dut_mapx_s cn63xxp1; 3324232812Sjmallett struct cvmx_l2c_dut_mapx_s cn66xx; 3325232812Sjmallett struct cvmx_l2c_dut_mapx_s cn68xx; 3326232812Sjmallett struct cvmx_l2c_dut_mapx_s cn68xxp1; 3327232812Sjmallett struct cvmx_l2c_dut_mapx_s cnf71xx; 3328215976Sjmallett}; 3329215976Sjmalletttypedef union cvmx_l2c_dut_mapx cvmx_l2c_dut_mapx_t; 3330215976Sjmallett 3331215976Sjmallett/** 3332215976Sjmallett * cvmx_l2c_err_tdt# 3333215976Sjmallett * 3334215976Sjmallett * L2C_ERR_TDT = L2C TAD DaTa Error Info 3335215976Sjmallett * 3336215976Sjmallett * 3337215976Sjmallett * Notes: 3338215976Sjmallett * (1) If the status bit corresponding to the value of the TYPE field is not set the WAYIDX/SYN fields 3339215976Sjmallett * are not associated with the errors currently logged by the status bits and should be ignored. 3340215976Sjmallett * This can occur, for example, because of a race between a write to clear a DBE and a new, lower 3341215976Sjmallett * priority, SBE error occuring. If the SBE arrives prior to the DBE clear the WAYIDX/SYN fields 3342215976Sjmallett * will still be locked, but the new SBE error status bit will still be set. 3343215976Sjmallett * 3344215976Sjmallett * (2) The four types of errors have differing priorities. Priority (from lowest to highest) is SBE, 3345215976Sjmallett * VSBE, DBE, VDBE. A error will lock the WAYIDX, and SYN fields for other errors of equal or 3346215976Sjmallett * lower priority until cleared by software. This means that the error information is always 3347215976Sjmallett * (assuming the TYPE field matches) for the highest priority error logged in the status bits. 3348215976Sjmallett * 3349215976Sjmallett * (3) If VSBE or VDBE are set (and the TYPE field matches), the WAYIDX fields are valid and the 3350215976Sjmallett * syndrome can be found in L2C_ERR_VBF. 3351215976Sjmallett * 3352215976Sjmallett * (4) The syndrome is recorded for DBE errors, though the utility of the value is not clear. 3353215976Sjmallett */ 3354232812Sjmallettunion cvmx_l2c_err_tdtx { 3355215976Sjmallett uint64_t u64; 3356232812Sjmallett struct cvmx_l2c_err_tdtx_s { 3357232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3358215976Sjmallett uint64_t dbe : 1; /**< L2D Double-Bit error has occurred */ 3359215976Sjmallett uint64_t sbe : 1; /**< L2D Single-Bit error has occurred */ 3360215976Sjmallett uint64_t vdbe : 1; /**< VBF Double-Bit error has occurred */ 3361215976Sjmallett uint64_t vsbe : 1; /**< VBF Single-Bit error has occurred */ 3362215976Sjmallett uint64_t syn : 10; /**< L2D syndrome (valid only for SBE/DBE, not VSBE/VDBE) */ 3363232812Sjmallett uint64_t reserved_22_49 : 28; 3364232812Sjmallett uint64_t wayidx : 18; /**< Way, index, OW of the L2 block containing the error */ 3365232812Sjmallett uint64_t reserved_2_3 : 2; 3366232812Sjmallett uint64_t type : 2; /**< The type of error the WAYIDX,SYN were latched for. 3367232812Sjmallett 0 - VSBE 3368232812Sjmallett 1 - VDBE 3369232812Sjmallett 2 - SBE 3370232812Sjmallett 3 - DBE */ 3371232812Sjmallett#else 3372232812Sjmallett uint64_t type : 2; 3373232812Sjmallett uint64_t reserved_2_3 : 2; 3374232812Sjmallett uint64_t wayidx : 18; 3375232812Sjmallett uint64_t reserved_22_49 : 28; 3376232812Sjmallett uint64_t syn : 10; 3377232812Sjmallett uint64_t vsbe : 1; 3378232812Sjmallett uint64_t vdbe : 1; 3379232812Sjmallett uint64_t sbe : 1; 3380232812Sjmallett uint64_t dbe : 1; 3381232812Sjmallett#endif 3382232812Sjmallett } s; 3383232812Sjmallett struct cvmx_l2c_err_tdtx_cn61xx { 3384232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3385232812Sjmallett uint64_t dbe : 1; /**< L2D Double-Bit error has occurred */ 3386232812Sjmallett uint64_t sbe : 1; /**< L2D Single-Bit error has occurred */ 3387232812Sjmallett uint64_t vdbe : 1; /**< VBF Double-Bit error has occurred */ 3388232812Sjmallett uint64_t vsbe : 1; /**< VBF Single-Bit error has occurred */ 3389232812Sjmallett uint64_t syn : 10; /**< L2D syndrome (valid only for SBE/DBE, not VSBE/VDBE) */ 3390232812Sjmallett uint64_t reserved_20_49 : 30; 3391232812Sjmallett uint64_t wayidx : 16; /**< Way, index, OW of the L2 block containing the error */ 3392232812Sjmallett uint64_t reserved_2_3 : 2; 3393232812Sjmallett uint64_t type : 2; /**< The type of error the WAYIDX,SYN were latched for. 3394232812Sjmallett 0 - VSBE 3395232812Sjmallett 1 - VDBE 3396232812Sjmallett 2 - SBE 3397232812Sjmallett 3 - DBE */ 3398232812Sjmallett#else 3399232812Sjmallett uint64_t type : 2; 3400232812Sjmallett uint64_t reserved_2_3 : 2; 3401232812Sjmallett uint64_t wayidx : 16; 3402232812Sjmallett uint64_t reserved_20_49 : 30; 3403232812Sjmallett uint64_t syn : 10; 3404232812Sjmallett uint64_t vsbe : 1; 3405232812Sjmallett uint64_t vdbe : 1; 3406232812Sjmallett uint64_t sbe : 1; 3407232812Sjmallett uint64_t dbe : 1; 3408232812Sjmallett#endif 3409232812Sjmallett } cn61xx; 3410232812Sjmallett struct cvmx_l2c_err_tdtx_cn63xx { 3411232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3412232812Sjmallett uint64_t dbe : 1; /**< L2D Double-Bit error has occurred */ 3413232812Sjmallett uint64_t sbe : 1; /**< L2D Single-Bit error has occurred */ 3414232812Sjmallett uint64_t vdbe : 1; /**< VBF Double-Bit error has occurred */ 3415232812Sjmallett uint64_t vsbe : 1; /**< VBF Single-Bit error has occurred */ 3416232812Sjmallett uint64_t syn : 10; /**< L2D syndrome (valid only for SBE/DBE, not VSBE/VDBE) */ 3417215976Sjmallett uint64_t reserved_21_49 : 29; 3418215976Sjmallett uint64_t wayidx : 17; /**< Way, index, OW of the L2 block containing the error */ 3419215976Sjmallett uint64_t reserved_2_3 : 2; 3420215976Sjmallett uint64_t type : 2; /**< The type of error the WAYIDX,SYN were latched for. 3421215976Sjmallett 0 - VSBE 3422215976Sjmallett 1 - VDBE 3423215976Sjmallett 2 - SBE 3424215976Sjmallett 3 - DBE */ 3425215976Sjmallett#else 3426215976Sjmallett uint64_t type : 2; 3427215976Sjmallett uint64_t reserved_2_3 : 2; 3428215976Sjmallett uint64_t wayidx : 17; 3429215976Sjmallett uint64_t reserved_21_49 : 29; 3430215976Sjmallett uint64_t syn : 10; 3431215976Sjmallett uint64_t vsbe : 1; 3432215976Sjmallett uint64_t vdbe : 1; 3433215976Sjmallett uint64_t sbe : 1; 3434215976Sjmallett uint64_t dbe : 1; 3435215976Sjmallett#endif 3436232812Sjmallett } cn63xx; 3437232812Sjmallett struct cvmx_l2c_err_tdtx_cn63xx cn63xxp1; 3438232812Sjmallett struct cvmx_l2c_err_tdtx_cn63xx cn66xx; 3439232812Sjmallett struct cvmx_l2c_err_tdtx_s cn68xx; 3440232812Sjmallett struct cvmx_l2c_err_tdtx_s cn68xxp1; 3441232812Sjmallett struct cvmx_l2c_err_tdtx_cn61xx cnf71xx; 3442215976Sjmallett}; 3443215976Sjmalletttypedef union cvmx_l2c_err_tdtx cvmx_l2c_err_tdtx_t; 3444215976Sjmallett 3445215976Sjmallett/** 3446215976Sjmallett * cvmx_l2c_err_ttg# 3447215976Sjmallett * 3448215976Sjmallett * L2C_ERR_TTG = L2C TAD TaG Error Info 3449215976Sjmallett * 3450215976Sjmallett * 3451215976Sjmallett * Notes: 3452215976Sjmallett * (1) The priority of errors (highest to lowest) is DBE, SBE, NOWAY. An error will lock the SYN, and 3453215976Sjmallett * WAYIDX fields for equal or lower priority errors until cleared by software. 3454215976Sjmallett * 3455215976Sjmallett * (2) The syndrome is recorded for DBE errors, though the utility of the value is not clear. 3456215976Sjmallett * 3457215976Sjmallett * (3) A NOWAY error does not change the value of the SYN field, and leaves WAYIDX[20:17] 3458215976Sjmallett * unpredictable. WAYIDX[16:7] is the L2 block index associated with the command which had no way 3459215976Sjmallett * to allocate. 3460215976Sjmallett * 3461215976Sjmallett * (4) If the status bit corresponding to the value of the TYPE field is not set the WAYIDX/SYN fields 3462215976Sjmallett * are not associated with the errors currently logged by the status bits and should be ignored. 3463215976Sjmallett * This can occur, for example, because of a race between a write to clear a DBE and a new, lower 3464215976Sjmallett * priority, SBE error occuring. If the SBE arrives prior to the DBE clear the WAYIDX/SYN fields 3465215976Sjmallett * will still be locked, but the new SBE error status bit will still be set. 3466215976Sjmallett */ 3467232812Sjmallettunion cvmx_l2c_err_ttgx { 3468215976Sjmallett uint64_t u64; 3469232812Sjmallett struct cvmx_l2c_err_ttgx_s { 3470232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3471215976Sjmallett uint64_t dbe : 1; /**< Double-Bit ECC error */ 3472215976Sjmallett uint64_t sbe : 1; /**< Single-Bit ECC error */ 3473215976Sjmallett uint64_t noway : 1; /**< No way was available for allocation. 3474215976Sjmallett L2C sets NOWAY during its processing of a 3475215976Sjmallett transaction whenever it needed/wanted to allocate 3476215976Sjmallett a WAY in the L2 cache, but was unable to. NOWAY==1 3477215976Sjmallett is (generally) not an indication that L2C failed to 3478215976Sjmallett complete transactions. Rather, it is a hint of 3479215976Sjmallett possible performance degradation. (For example, L2C 3480215976Sjmallett must read-modify-write DRAM for every transaction 3481215976Sjmallett that updates some, but not all, of the bytes in a 3482215976Sjmallett cache block, misses in the L2 cache, and cannot 3483215976Sjmallett allocate a WAY.) There is one "failure" case where 3484215976Sjmallett L2C will set NOWAY: when it cannot leave a block 3485215976Sjmallett locked in the L2 cache as part of a LCKL2 3486215976Sjmallett transaction. */ 3487215976Sjmallett uint64_t reserved_56_60 : 5; 3488215976Sjmallett uint64_t syn : 6; /**< Syndrome for the single-bit error */ 3489232812Sjmallett uint64_t reserved_22_49 : 28; 3490232812Sjmallett uint64_t wayidx : 15; /**< Way and index of the L2 block containing the error */ 3491232812Sjmallett uint64_t reserved_2_6 : 5; 3492232812Sjmallett uint64_t type : 2; /**< The type of error the WAYIDX,SYN were latched for. 3493232812Sjmallett 0 - not valid 3494232812Sjmallett 1 - NOWAY 3495232812Sjmallett 2 - SBE 3496232812Sjmallett 3 - DBE */ 3497232812Sjmallett#else 3498232812Sjmallett uint64_t type : 2; 3499232812Sjmallett uint64_t reserved_2_6 : 5; 3500232812Sjmallett uint64_t wayidx : 15; 3501232812Sjmallett uint64_t reserved_22_49 : 28; 3502232812Sjmallett uint64_t syn : 6; 3503232812Sjmallett uint64_t reserved_56_60 : 5; 3504232812Sjmallett uint64_t noway : 1; 3505232812Sjmallett uint64_t sbe : 1; 3506232812Sjmallett uint64_t dbe : 1; 3507232812Sjmallett#endif 3508232812Sjmallett } s; 3509232812Sjmallett struct cvmx_l2c_err_ttgx_cn61xx { 3510232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3511232812Sjmallett uint64_t dbe : 1; /**< Double-Bit ECC error */ 3512232812Sjmallett uint64_t sbe : 1; /**< Single-Bit ECC error */ 3513232812Sjmallett uint64_t noway : 1; /**< No way was available for allocation. 3514232812Sjmallett L2C sets NOWAY during its processing of a 3515232812Sjmallett transaction whenever it needed/wanted to allocate 3516232812Sjmallett a WAY in the L2 cache, but was unable to. NOWAY==1 3517232812Sjmallett is (generally) not an indication that L2C failed to 3518232812Sjmallett complete transactions. Rather, it is a hint of 3519232812Sjmallett possible performance degradation. (For example, L2C 3520232812Sjmallett must read-modify-write DRAM for every transaction 3521232812Sjmallett that updates some, but not all, of the bytes in a 3522232812Sjmallett cache block, misses in the L2 cache, and cannot 3523232812Sjmallett allocate a WAY.) There is one "failure" case where 3524232812Sjmallett L2C will set NOWAY: when it cannot leave a block 3525232812Sjmallett locked in the L2 cache as part of a LCKL2 3526232812Sjmallett transaction. */ 3527232812Sjmallett uint64_t reserved_56_60 : 5; 3528232812Sjmallett uint64_t syn : 6; /**< Syndrome for the single-bit error */ 3529232812Sjmallett uint64_t reserved_20_49 : 30; 3530232812Sjmallett uint64_t wayidx : 13; /**< Way and index of the L2 block containing the error */ 3531232812Sjmallett uint64_t reserved_2_6 : 5; 3532232812Sjmallett uint64_t type : 2; /**< The type of error the WAYIDX,SYN were latched for. 3533232812Sjmallett 0 - not valid 3534232812Sjmallett 1 - NOWAY 3535232812Sjmallett 2 - SBE 3536232812Sjmallett 3 - DBE */ 3537232812Sjmallett#else 3538232812Sjmallett uint64_t type : 2; 3539232812Sjmallett uint64_t reserved_2_6 : 5; 3540232812Sjmallett uint64_t wayidx : 13; 3541232812Sjmallett uint64_t reserved_20_49 : 30; 3542232812Sjmallett uint64_t syn : 6; 3543232812Sjmallett uint64_t reserved_56_60 : 5; 3544232812Sjmallett uint64_t noway : 1; 3545232812Sjmallett uint64_t sbe : 1; 3546232812Sjmallett uint64_t dbe : 1; 3547232812Sjmallett#endif 3548232812Sjmallett } cn61xx; 3549232812Sjmallett struct cvmx_l2c_err_ttgx_cn63xx { 3550232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3551232812Sjmallett uint64_t dbe : 1; /**< Double-Bit ECC error */ 3552232812Sjmallett uint64_t sbe : 1; /**< Single-Bit ECC error */ 3553232812Sjmallett uint64_t noway : 1; /**< No way was available for allocation. 3554232812Sjmallett L2C sets NOWAY during its processing of a 3555232812Sjmallett transaction whenever it needed/wanted to allocate 3556232812Sjmallett a WAY in the L2 cache, but was unable to. NOWAY==1 3557232812Sjmallett is (generally) not an indication that L2C failed to 3558232812Sjmallett complete transactions. Rather, it is a hint of 3559232812Sjmallett possible performance degradation. (For example, L2C 3560232812Sjmallett must read-modify-write DRAM for every transaction 3561232812Sjmallett that updates some, but not all, of the bytes in a 3562232812Sjmallett cache block, misses in the L2 cache, and cannot 3563232812Sjmallett allocate a WAY.) There is one "failure" case where 3564232812Sjmallett L2C will set NOWAY: when it cannot leave a block 3565232812Sjmallett locked in the L2 cache as part of a LCKL2 3566232812Sjmallett transaction. */ 3567232812Sjmallett uint64_t reserved_56_60 : 5; 3568232812Sjmallett uint64_t syn : 6; /**< Syndrome for the single-bit error */ 3569215976Sjmallett uint64_t reserved_21_49 : 29; 3570215976Sjmallett uint64_t wayidx : 14; /**< Way and index of the L2 block containing the error */ 3571215976Sjmallett uint64_t reserved_2_6 : 5; 3572215976Sjmallett uint64_t type : 2; /**< The type of error the WAYIDX,SYN were latched for. 3573215976Sjmallett 0 - not valid 3574215976Sjmallett 1 - NOWAY 3575215976Sjmallett 2 - SBE 3576215976Sjmallett 3 - DBE */ 3577215976Sjmallett#else 3578215976Sjmallett uint64_t type : 2; 3579215976Sjmallett uint64_t reserved_2_6 : 5; 3580215976Sjmallett uint64_t wayidx : 14; 3581215976Sjmallett uint64_t reserved_21_49 : 29; 3582215976Sjmallett uint64_t syn : 6; 3583215976Sjmallett uint64_t reserved_56_60 : 5; 3584215976Sjmallett uint64_t noway : 1; 3585215976Sjmallett uint64_t sbe : 1; 3586215976Sjmallett uint64_t dbe : 1; 3587215976Sjmallett#endif 3588232812Sjmallett } cn63xx; 3589232812Sjmallett struct cvmx_l2c_err_ttgx_cn63xx cn63xxp1; 3590232812Sjmallett struct cvmx_l2c_err_ttgx_cn63xx cn66xx; 3591232812Sjmallett struct cvmx_l2c_err_ttgx_s cn68xx; 3592232812Sjmallett struct cvmx_l2c_err_ttgx_s cn68xxp1; 3593232812Sjmallett struct cvmx_l2c_err_ttgx_cn61xx cnf71xx; 3594215976Sjmallett}; 3595215976Sjmalletttypedef union cvmx_l2c_err_ttgx cvmx_l2c_err_ttgx_t; 3596215976Sjmallett 3597215976Sjmallett/** 3598215976Sjmallett * cvmx_l2c_err_vbf# 3599215976Sjmallett * 3600215976Sjmallett * L2C_ERR_VBF = L2C VBF Error Info 3601215976Sjmallett * 3602215976Sjmallett * 3603215976Sjmallett * Notes: 3604215976Sjmallett * (1) The way/index information is stored in L2C_ERR_TDT, assuming no later interrupt occurred to 3605215976Sjmallett * overwrite the information. See the notes associated with L2C_ERR_TDT for full details. 3606215976Sjmallett * 3607215976Sjmallett * (2) The first VSBE will lock the register for other VSBE's. A VDBE, however, will overwrite a 3608215976Sjmallett * previously logged VSBE. Once a VDBE has been logged all later errors will not be logged. This 3609215976Sjmallett * means that if VDBE is set the information in the register is for the VDBE, if VDBE is clear and 3610215976Sjmallett * VSBE is set the register contains information about the VSBE. 3611215976Sjmallett * 3612215976Sjmallett * (3) The syndrome is recorded for VDBE errors, though the utility of the value is not clear. 3613215976Sjmallett * 3614215976Sjmallett * (4) If the status bit corresponding to the value of the TYPE field is not set the SYN field is not 3615215976Sjmallett * associated with the errors currently logged by the status bits and should be ignored. This can 3616215976Sjmallett * occur, for example, because of a race between a write to clear a VDBE and a new, lower priority, 3617215976Sjmallett * VSBE error occuring. If the VSBE arrives prior to the VDBE clear the SYN field will still be 3618215976Sjmallett * locked, but the new VSBE error status bit will still be set. 3619215976Sjmallett */ 3620232812Sjmallettunion cvmx_l2c_err_vbfx { 3621215976Sjmallett uint64_t u64; 3622232812Sjmallett struct cvmx_l2c_err_vbfx_s { 3623232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3624215976Sjmallett uint64_t reserved_62_63 : 2; 3625215976Sjmallett uint64_t vdbe : 1; /**< VBF Double-Bit error has occurred */ 3626215976Sjmallett uint64_t vsbe : 1; /**< VBF Single-Bit error has occurred */ 3627215976Sjmallett uint64_t vsyn : 10; /**< VBF syndrome (valid only if VSBE/VDBE is set) */ 3628215976Sjmallett uint64_t reserved_2_49 : 48; 3629215976Sjmallett uint64_t type : 2; /**< The type of error the SYN were latched for. 3630215976Sjmallett 0 - VSBE 3631215976Sjmallett 1 - VDBE */ 3632215976Sjmallett#else 3633215976Sjmallett uint64_t type : 2; 3634215976Sjmallett uint64_t reserved_2_49 : 48; 3635215976Sjmallett uint64_t vsyn : 10; 3636215976Sjmallett uint64_t vsbe : 1; 3637215976Sjmallett uint64_t vdbe : 1; 3638215976Sjmallett uint64_t reserved_62_63 : 2; 3639215976Sjmallett#endif 3640215976Sjmallett } s; 3641232812Sjmallett struct cvmx_l2c_err_vbfx_s cn61xx; 3642215976Sjmallett struct cvmx_l2c_err_vbfx_s cn63xx; 3643215976Sjmallett struct cvmx_l2c_err_vbfx_s cn63xxp1; 3644232812Sjmallett struct cvmx_l2c_err_vbfx_s cn66xx; 3645232812Sjmallett struct cvmx_l2c_err_vbfx_s cn68xx; 3646232812Sjmallett struct cvmx_l2c_err_vbfx_s cn68xxp1; 3647232812Sjmallett struct cvmx_l2c_err_vbfx_s cnf71xx; 3648215976Sjmallett}; 3649215976Sjmalletttypedef union cvmx_l2c_err_vbfx cvmx_l2c_err_vbfx_t; 3650215976Sjmallett 3651215976Sjmallett/** 3652215976Sjmallett * cvmx_l2c_err_xmc 3653215976Sjmallett * 3654215976Sjmallett * L2C_ERR_XMC = L2C XMC request error 3655215976Sjmallett * 3656215976Sjmallett * Description: records error information for HOLE*, BIG* and VRT* interrupts. 3657215976Sjmallett * 3658215976Sjmallett * Notes: 3659215976Sjmallett * (1) The first BIGWR/HOLEWR/VRT* interrupt will lock the register until L2C_INT_REG[6:1] are 3660215976Sjmallett * cleared. 3661215976Sjmallett * 3662215976Sjmallett * (2) ADDR<15:0> will always be zero for VRT* interrupts. 3663215976Sjmallett * 3664215976Sjmallett * (3) ADDR is the 38-bit OCTEON physical address after hole removal. (The hole is between DR0 3665215976Sjmallett * and DR1. Remove the hole by subtracting 256MB from all 38-bit OCTEON L2/DRAM physical addresses 3666215976Sjmallett * >= 512 MB.) 3667215976Sjmallett * 3668215976Sjmallett * (4) For 63xx pass 2.0 and all 68xx ADDR<15:0> will ALWAYS be zero. 3669215976Sjmallett */ 3670232812Sjmallettunion cvmx_l2c_err_xmc { 3671215976Sjmallett uint64_t u64; 3672232812Sjmallett struct cvmx_l2c_err_xmc_s { 3673232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3674215976Sjmallett uint64_t cmd : 6; /**< XMC command or request causing error */ 3675232812Sjmallett uint64_t reserved_54_57 : 4; 3676232812Sjmallett uint64_t sid : 6; /**< XMC sid of request causing error */ 3677232812Sjmallett uint64_t reserved_38_47 : 10; 3678232812Sjmallett uint64_t addr : 38; /**< XMC address causing the error (see Notes 2 and 3) */ 3679232812Sjmallett#else 3680232812Sjmallett uint64_t addr : 38; 3681232812Sjmallett uint64_t reserved_38_47 : 10; 3682232812Sjmallett uint64_t sid : 6; 3683232812Sjmallett uint64_t reserved_54_57 : 4; 3684232812Sjmallett uint64_t cmd : 6; 3685232812Sjmallett#endif 3686232812Sjmallett } s; 3687232812Sjmallett struct cvmx_l2c_err_xmc_cn61xx { 3688232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3689232812Sjmallett uint64_t cmd : 6; /**< XMC command or request causing error */ 3690215976Sjmallett uint64_t reserved_52_57 : 6; 3691215976Sjmallett uint64_t sid : 4; /**< XMC sid of request causing error */ 3692215976Sjmallett uint64_t reserved_38_47 : 10; 3693215976Sjmallett uint64_t addr : 38; /**< XMC address causing the error (see Notes 2 and 3) */ 3694215976Sjmallett#else 3695215976Sjmallett uint64_t addr : 38; 3696215976Sjmallett uint64_t reserved_38_47 : 10; 3697215976Sjmallett uint64_t sid : 4; 3698215976Sjmallett uint64_t reserved_52_57 : 6; 3699215976Sjmallett uint64_t cmd : 6; 3700215976Sjmallett#endif 3701232812Sjmallett } cn61xx; 3702232812Sjmallett struct cvmx_l2c_err_xmc_cn61xx cn63xx; 3703232812Sjmallett struct cvmx_l2c_err_xmc_cn61xx cn63xxp1; 3704232812Sjmallett struct cvmx_l2c_err_xmc_cn66xx { 3705232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3706232812Sjmallett uint64_t cmd : 6; /**< XMC command or request causing error */ 3707232812Sjmallett uint64_t reserved_53_57 : 5; 3708232812Sjmallett uint64_t sid : 5; /**< XMC sid of request causing error */ 3709232812Sjmallett uint64_t reserved_38_47 : 10; 3710232812Sjmallett uint64_t addr : 38; /**< XMC address causing the error (see Notes 2 and 3) */ 3711232812Sjmallett#else 3712232812Sjmallett uint64_t addr : 38; 3713232812Sjmallett uint64_t reserved_38_47 : 10; 3714232812Sjmallett uint64_t sid : 5; 3715232812Sjmallett uint64_t reserved_53_57 : 5; 3716232812Sjmallett uint64_t cmd : 6; 3717232812Sjmallett#endif 3718232812Sjmallett } cn66xx; 3719232812Sjmallett struct cvmx_l2c_err_xmc_s cn68xx; 3720232812Sjmallett struct cvmx_l2c_err_xmc_s cn68xxp1; 3721232812Sjmallett struct cvmx_l2c_err_xmc_cn61xx cnf71xx; 3722215976Sjmallett}; 3723215976Sjmalletttypedef union cvmx_l2c_err_xmc cvmx_l2c_err_xmc_t; 3724215976Sjmallett 3725215976Sjmallett/** 3726215976Sjmallett * cvmx_l2c_grpwrr0 3727215976Sjmallett * 3728215976Sjmallett * L2C_GRPWRR0 = L2C PP Weighted Round \#0 Register 3729215976Sjmallett * 3730215976Sjmallett * Description: Defines Weighted rounds(32) for Group PLC0,PLC1 3731215976Sjmallett * 3732215976Sjmallett * Notes: 3733215976Sjmallett * - Starvation of a group 'could' occur, unless SW takes the precaution to ensure that each GROUP 3734215976Sjmallett * participates in at least 1(of 32) rounds (ie: At least 1 bit(of 32) should be clear). 3735215976Sjmallett */ 3736232812Sjmallettunion cvmx_l2c_grpwrr0 { 3737215976Sjmallett uint64_t u64; 3738232812Sjmallett struct cvmx_l2c_grpwrr0_s { 3739232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3740215976Sjmallett uint64_t plc1rmsk : 32; /**< PLC1 Group#1 Weighted Round Mask 3741215976Sjmallett Each bit represents 1 of 32 rounds 3742215976Sjmallett for Group \#1's participation. When a 'round' bit is 3743215976Sjmallett set, Group#1 is 'masked' and DOES NOT participate. 3744215976Sjmallett When a 'round' bit is clear, Group#1 WILL 3745215976Sjmallett participate in the arbitration for this round. */ 3746215976Sjmallett uint64_t plc0rmsk : 32; /**< PLC Group#0 Weighted Round Mask 3747215976Sjmallett Each bit represents 1 of 32 rounds 3748215976Sjmallett for Group \#0's participation. When a 'round' bit is 3749215976Sjmallett set, Group#0 is 'masked' and DOES NOT participate. 3750215976Sjmallett When a 'round' bit is clear, Group#0 WILL 3751215976Sjmallett participate in the arbitration for this round. */ 3752215976Sjmallett#else 3753215976Sjmallett uint64_t plc0rmsk : 32; 3754215976Sjmallett uint64_t plc1rmsk : 32; 3755215976Sjmallett#endif 3756215976Sjmallett } s; 3757215976Sjmallett struct cvmx_l2c_grpwrr0_s cn52xx; 3758215976Sjmallett struct cvmx_l2c_grpwrr0_s cn52xxp1; 3759215976Sjmallett struct cvmx_l2c_grpwrr0_s cn56xx; 3760215976Sjmallett struct cvmx_l2c_grpwrr0_s cn56xxp1; 3761215976Sjmallett}; 3762215976Sjmalletttypedef union cvmx_l2c_grpwrr0 cvmx_l2c_grpwrr0_t; 3763215976Sjmallett 3764215976Sjmallett/** 3765215976Sjmallett * cvmx_l2c_grpwrr1 3766215976Sjmallett * 3767215976Sjmallett * L2C_GRPWRR1 = L2C PP Weighted Round \#1 Register 3768215976Sjmallett * 3769215976Sjmallett * Description: Defines Weighted Rounds(32) for Group PLC2,ILC 3770215976Sjmallett * 3771215976Sjmallett * Notes: 3772215976Sjmallett * - Starvation of a group 'could' occur, unless SW takes the precaution to ensure that each GROUP 3773215976Sjmallett * participates in at least 1(of 32) rounds (ie: At least 1 bit(of 32) should be clear). 3774215976Sjmallett */ 3775232812Sjmallettunion cvmx_l2c_grpwrr1 { 3776215976Sjmallett uint64_t u64; 3777232812Sjmallett struct cvmx_l2c_grpwrr1_s { 3778232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3779215976Sjmallett uint64_t ilcrmsk : 32; /**< ILC (IOB) Weighted Round Mask 3780215976Sjmallett Each bit represents 1 of 32 rounds 3781215976Sjmallett for IOB participation. When a 'round' bit is 3782215976Sjmallett set, IOB is 'masked' and DOES NOT participate. 3783215976Sjmallett When a 'round' bit is clear, IOB WILL 3784215976Sjmallett participate in the arbitration for this round. */ 3785215976Sjmallett uint64_t plc2rmsk : 32; /**< PLC Group#2 Weighted Round Mask 3786215976Sjmallett Each bit represents 1 of 32 rounds 3787215976Sjmallett for Group \#2's participation. When a 'round' bit is 3788215976Sjmallett set, Group#2 is 'masked' and DOES NOT participate. 3789215976Sjmallett When a 'round' bit is clear, Group#2 WILL 3790215976Sjmallett participate in the arbitration for this round. */ 3791215976Sjmallett#else 3792215976Sjmallett uint64_t plc2rmsk : 32; 3793215976Sjmallett uint64_t ilcrmsk : 32; 3794215976Sjmallett#endif 3795215976Sjmallett } s; 3796215976Sjmallett struct cvmx_l2c_grpwrr1_s cn52xx; 3797215976Sjmallett struct cvmx_l2c_grpwrr1_s cn52xxp1; 3798215976Sjmallett struct cvmx_l2c_grpwrr1_s cn56xx; 3799215976Sjmallett struct cvmx_l2c_grpwrr1_s cn56xxp1; 3800215976Sjmallett}; 3801215976Sjmalletttypedef union cvmx_l2c_grpwrr1 cvmx_l2c_grpwrr1_t; 3802215976Sjmallett 3803215976Sjmallett/** 3804215976Sjmallett * cvmx_l2c_int_en 3805215976Sjmallett * 3806215976Sjmallett * L2C_INT_EN = L2C Global Interrupt Enable Register 3807215976Sjmallett * 3808215976Sjmallett * Description: 3809215976Sjmallett */ 3810232812Sjmallettunion cvmx_l2c_int_en { 3811215976Sjmallett uint64_t u64; 3812232812Sjmallett struct cvmx_l2c_int_en_s { 3813232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3814215976Sjmallett uint64_t reserved_9_63 : 55; 3815215976Sjmallett uint64_t lck2ena : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit 3816215976Sjmallett NOTE: This is the 'same' bit as L2T_ERR[LCK_INTENA2] */ 3817215976Sjmallett uint64_t lckena : 1; /**< L2 Tag Lock Error Interrupt Enable bit 3818215976Sjmallett NOTE: This is the 'same' bit as L2T_ERR[LCK_INTENA] */ 3819215976Sjmallett uint64_t l2ddeden : 1; /**< L2 Data ECC Double Error Detect(DED) Interrupt Enable bit 3820215976Sjmallett When set, allows interrupts to be reported on double bit 3821215976Sjmallett (uncorrectable) errors from the L2 Data Arrays. 3822215976Sjmallett NOTE: This is the 'same' bit as L2D_ERR[DED_INTENA] */ 3823215976Sjmallett uint64_t l2dsecen : 1; /**< L2 Data ECC Single Error Correct(SEC) Interrupt Enable bit 3824215976Sjmallett When set, allows interrupts to be reported on single bit 3825215976Sjmallett (correctable) errors from the L2 Data Arrays. 3826215976Sjmallett NOTE: This is the 'same' bit as L2D_ERR[SEC_INTENA] */ 3827215976Sjmallett uint64_t l2tdeden : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 3828215976Sjmallett NOTE: This is the 'same' bit as L2T_ERR[DED_INTENA] */ 3829215976Sjmallett uint64_t l2tsecen : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 3830215976Sjmallett Enable bit. When set, allows interrupts to be 3831215976Sjmallett reported on single bit (correctable) errors from 3832215976Sjmallett the L2 Tag Arrays. 3833215976Sjmallett NOTE: This is the 'same' bit as L2T_ERR[SEC_INTENA] */ 3834215976Sjmallett uint64_t oob3en : 1; /**< DMA Out of Bounds Interrupt Enable Range#3 */ 3835215976Sjmallett uint64_t oob2en : 1; /**< DMA Out of Bounds Interrupt Enable Range#2 */ 3836215976Sjmallett uint64_t oob1en : 1; /**< DMA Out of Bounds Interrupt Enable Range#1 */ 3837215976Sjmallett#else 3838215976Sjmallett uint64_t oob1en : 1; 3839215976Sjmallett uint64_t oob2en : 1; 3840215976Sjmallett uint64_t oob3en : 1; 3841215976Sjmallett uint64_t l2tsecen : 1; 3842215976Sjmallett uint64_t l2tdeden : 1; 3843215976Sjmallett uint64_t l2dsecen : 1; 3844215976Sjmallett uint64_t l2ddeden : 1; 3845215976Sjmallett uint64_t lckena : 1; 3846215976Sjmallett uint64_t lck2ena : 1; 3847215976Sjmallett uint64_t reserved_9_63 : 55; 3848215976Sjmallett#endif 3849215976Sjmallett } s; 3850215976Sjmallett struct cvmx_l2c_int_en_s cn52xx; 3851215976Sjmallett struct cvmx_l2c_int_en_s cn52xxp1; 3852215976Sjmallett struct cvmx_l2c_int_en_s cn56xx; 3853215976Sjmallett struct cvmx_l2c_int_en_s cn56xxp1; 3854215976Sjmallett}; 3855215976Sjmalletttypedef union cvmx_l2c_int_en cvmx_l2c_int_en_t; 3856215976Sjmallett 3857215976Sjmallett/** 3858215976Sjmallett * cvmx_l2c_int_ena 3859215976Sjmallett * 3860215976Sjmallett * L2C_INT_ENA = L2C Interrupt Enable 3861215976Sjmallett * 3862215976Sjmallett */ 3863232812Sjmallettunion cvmx_l2c_int_ena { 3864215976Sjmallett uint64_t u64; 3865232812Sjmallett struct cvmx_l2c_int_ena_s { 3866232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3867215976Sjmallett uint64_t reserved_8_63 : 56; 3868215976Sjmallett uint64_t bigrd : 1; /**< Read reference past MAXDRAM enable */ 3869215976Sjmallett uint64_t bigwr : 1; /**< Write reference past MAXDRAM enable */ 3870215976Sjmallett uint64_t vrtpe : 1; /**< Virtualization memory parity error */ 3871215976Sjmallett uint64_t vrtadrng : 1; /**< Address outside of virtualization range enable */ 3872215976Sjmallett uint64_t vrtidrng : 1; /**< Virtualization ID out of range enable */ 3873215976Sjmallett uint64_t vrtwr : 1; /**< Virtualization ID prevented a write enable */ 3874215976Sjmallett uint64_t holewr : 1; /**< Write reference to 256MB hole enable */ 3875215976Sjmallett uint64_t holerd : 1; /**< Read reference to 256MB hole enable */ 3876215976Sjmallett#else 3877215976Sjmallett uint64_t holerd : 1; 3878215976Sjmallett uint64_t holewr : 1; 3879215976Sjmallett uint64_t vrtwr : 1; 3880215976Sjmallett uint64_t vrtidrng : 1; 3881215976Sjmallett uint64_t vrtadrng : 1; 3882215976Sjmallett uint64_t vrtpe : 1; 3883215976Sjmallett uint64_t bigwr : 1; 3884215976Sjmallett uint64_t bigrd : 1; 3885215976Sjmallett uint64_t reserved_8_63 : 56; 3886215976Sjmallett#endif 3887215976Sjmallett } s; 3888232812Sjmallett struct cvmx_l2c_int_ena_s cn61xx; 3889215976Sjmallett struct cvmx_l2c_int_ena_s cn63xx; 3890232812Sjmallett struct cvmx_l2c_int_ena_cn63xxp1 { 3891232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3892215976Sjmallett uint64_t reserved_6_63 : 58; 3893215976Sjmallett uint64_t vrtpe : 1; /**< Virtualization memory parity error */ 3894215976Sjmallett uint64_t vrtadrng : 1; /**< Address outside of virtualization range enable */ 3895215976Sjmallett uint64_t vrtidrng : 1; /**< Virtualization ID out of range enable */ 3896215976Sjmallett uint64_t vrtwr : 1; /**< Virtualization ID prevented a write enable */ 3897215976Sjmallett uint64_t holewr : 1; /**< Write reference to 256MB hole enable */ 3898215976Sjmallett uint64_t holerd : 1; /**< Read reference to 256MB hole enable */ 3899215976Sjmallett#else 3900215976Sjmallett uint64_t holerd : 1; 3901215976Sjmallett uint64_t holewr : 1; 3902215976Sjmallett uint64_t vrtwr : 1; 3903215976Sjmallett uint64_t vrtidrng : 1; 3904215976Sjmallett uint64_t vrtadrng : 1; 3905215976Sjmallett uint64_t vrtpe : 1; 3906215976Sjmallett uint64_t reserved_6_63 : 58; 3907215976Sjmallett#endif 3908215976Sjmallett } cn63xxp1; 3909232812Sjmallett struct cvmx_l2c_int_ena_s cn66xx; 3910232812Sjmallett struct cvmx_l2c_int_ena_s cn68xx; 3911232812Sjmallett struct cvmx_l2c_int_ena_s cn68xxp1; 3912232812Sjmallett struct cvmx_l2c_int_ena_s cnf71xx; 3913215976Sjmallett}; 3914215976Sjmalletttypedef union cvmx_l2c_int_ena cvmx_l2c_int_ena_t; 3915215976Sjmallett 3916215976Sjmallett/** 3917215976Sjmallett * cvmx_l2c_int_reg 3918215976Sjmallett * 3919215976Sjmallett * L2C_INT_REG = L2C Interrupt Register 3920215976Sjmallett * 3921215976Sjmallett */ 3922232812Sjmallettunion cvmx_l2c_int_reg { 3923215976Sjmallett uint64_t u64; 3924232812Sjmallett struct cvmx_l2c_int_reg_s { 3925232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3926232812Sjmallett uint64_t reserved_20_63 : 44; 3927232812Sjmallett uint64_t tad3 : 1; /**< When set, the enabled interrupt is in 3928232812Sjmallett the L2C_TAD3_INT CSR */ 3929232812Sjmallett uint64_t tad2 : 1; /**< When set, the enabled interrupt is in 3930232812Sjmallett the L2C_TAD2_INT CSR */ 3931232812Sjmallett uint64_t tad1 : 1; /**< When set, the enabled interrupt is in 3932232812Sjmallett the L2C_TAD1_INT CSR */ 3933232812Sjmallett uint64_t tad0 : 1; /**< When set, the enabled interrupt is in 3934232812Sjmallett the L2C_TAD0_INT CSR */ 3935232812Sjmallett uint64_t reserved_8_15 : 8; 3936232812Sjmallett uint64_t bigrd : 1; /**< Read reference past L2C_BIG_CTL[MAXDRAM] occurred */ 3937232812Sjmallett uint64_t bigwr : 1; /**< Write reference past L2C_BIG_CTL[MAXDRAM] occurred */ 3938232812Sjmallett uint64_t vrtpe : 1; /**< L2C_VRT_MEM read found a parity error 3939232812Sjmallett Whenever an L2C_VRT_MEM read finds a parity error, 3940232812Sjmallett that L2C_VRT_MEM cannot cause stores to be blocked. 3941232812Sjmallett Software should correct the error. */ 3942232812Sjmallett uint64_t vrtadrng : 1; /**< Address outside of virtualization range 3943232812Sjmallett Set when a L2C_VRT_CTL[MEMSZ] violation blocked a 3944232812Sjmallett store. 3945232812Sjmallett L2C_VRT_CTL[OOBERR] must be set for L2C to set this. */ 3946232812Sjmallett uint64_t vrtidrng : 1; /**< Virtualization ID out of range 3947232812Sjmallett Set when a L2C_VRT_CTL[NUMID] violation blocked a 3948232812Sjmallett store. */ 3949232812Sjmallett uint64_t vrtwr : 1; /**< Virtualization ID prevented a write 3950232812Sjmallett Set when L2C_VRT_MEM blocked a store. */ 3951232812Sjmallett uint64_t holewr : 1; /**< Write reference to 256MB hole occurred */ 3952232812Sjmallett uint64_t holerd : 1; /**< Read reference to 256MB hole occurred */ 3953232812Sjmallett#else 3954232812Sjmallett uint64_t holerd : 1; 3955232812Sjmallett uint64_t holewr : 1; 3956232812Sjmallett uint64_t vrtwr : 1; 3957232812Sjmallett uint64_t vrtidrng : 1; 3958232812Sjmallett uint64_t vrtadrng : 1; 3959232812Sjmallett uint64_t vrtpe : 1; 3960232812Sjmallett uint64_t bigwr : 1; 3961232812Sjmallett uint64_t bigrd : 1; 3962232812Sjmallett uint64_t reserved_8_15 : 8; 3963232812Sjmallett uint64_t tad0 : 1; 3964232812Sjmallett uint64_t tad1 : 1; 3965232812Sjmallett uint64_t tad2 : 1; 3966232812Sjmallett uint64_t tad3 : 1; 3967232812Sjmallett uint64_t reserved_20_63 : 44; 3968232812Sjmallett#endif 3969232812Sjmallett } s; 3970232812Sjmallett struct cvmx_l2c_int_reg_cn61xx { 3971232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3972215976Sjmallett uint64_t reserved_17_63 : 47; 3973232812Sjmallett uint64_t tad0 : 1; /**< When set, the enabled interrupt is in 3974232812Sjmallett the L2C_TAD0_INT CSR */ 3975215976Sjmallett uint64_t reserved_8_15 : 8; 3976215976Sjmallett uint64_t bigrd : 1; /**< Read reference past L2C_BIG_CTL[MAXDRAM] occurred */ 3977215976Sjmallett uint64_t bigwr : 1; /**< Write reference past L2C_BIG_CTL[MAXDRAM] occurred */ 3978215976Sjmallett uint64_t vrtpe : 1; /**< L2C_VRT_MEM read found a parity error 3979215976Sjmallett Whenever an L2C_VRT_MEM read finds a parity error, 3980215976Sjmallett that L2C_VRT_MEM cannot cause stores to be blocked. 3981215976Sjmallett Software should correct the error. */ 3982215976Sjmallett uint64_t vrtadrng : 1; /**< Address outside of virtualization range 3983215976Sjmallett Set when a L2C_VRT_CTL[MEMSZ] violation blocked a 3984215976Sjmallett store. 3985215976Sjmallett L2C_VRT_CTL[OOBERR] must be set for L2C to set this. */ 3986215976Sjmallett uint64_t vrtidrng : 1; /**< Virtualization ID out of range 3987215976Sjmallett Set when a L2C_VRT_CTL[NUMID] violation blocked a 3988215976Sjmallett store. */ 3989215976Sjmallett uint64_t vrtwr : 1; /**< Virtualization ID prevented a write 3990215976Sjmallett Set when L2C_VRT_MEM blocked a store. */ 3991215976Sjmallett uint64_t holewr : 1; /**< Write reference to 256MB hole occurred */ 3992215976Sjmallett uint64_t holerd : 1; /**< Read reference to 256MB hole occurred */ 3993215976Sjmallett#else 3994215976Sjmallett uint64_t holerd : 1; 3995215976Sjmallett uint64_t holewr : 1; 3996215976Sjmallett uint64_t vrtwr : 1; 3997215976Sjmallett uint64_t vrtidrng : 1; 3998215976Sjmallett uint64_t vrtadrng : 1; 3999215976Sjmallett uint64_t vrtpe : 1; 4000215976Sjmallett uint64_t bigwr : 1; 4001215976Sjmallett uint64_t bigrd : 1; 4002215976Sjmallett uint64_t reserved_8_15 : 8; 4003215976Sjmallett uint64_t tad0 : 1; 4004215976Sjmallett uint64_t reserved_17_63 : 47; 4005215976Sjmallett#endif 4006232812Sjmallett } cn61xx; 4007232812Sjmallett struct cvmx_l2c_int_reg_cn61xx cn63xx; 4008232812Sjmallett struct cvmx_l2c_int_reg_cn63xxp1 { 4009232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4010215976Sjmallett uint64_t reserved_17_63 : 47; 4011215976Sjmallett uint64_t tad0 : 1; /**< When set, the enabled interrupt is in either 4012215976Sjmallett the L2C_ERR_TDT0 or L2C_ERR_TTG0 CSR */ 4013215976Sjmallett uint64_t reserved_6_15 : 10; 4014215976Sjmallett uint64_t vrtpe : 1; /**< L2C_VRT_MEM read found a parity error 4015215976Sjmallett Whenever an L2C_VRT_MEM read finds a parity error, 4016215976Sjmallett that L2C_VRT_MEM cannot cause stores to be blocked. 4017215976Sjmallett Software should correct the error. */ 4018215976Sjmallett uint64_t vrtadrng : 1; /**< Address outside of virtualization range 4019215976Sjmallett Set when a L2C_VRT_CTL[MEMSZ] violation blocked a 4020215976Sjmallett store. 4021215976Sjmallett L2C_VRT_CTL[OOBERR] must be set for L2C to set this. */ 4022215976Sjmallett uint64_t vrtidrng : 1; /**< Virtualization ID out of range 4023215976Sjmallett Set when a L2C_VRT_CTL[NUMID] violation blocked a 4024215976Sjmallett store. */ 4025215976Sjmallett uint64_t vrtwr : 1; /**< Virtualization ID prevented a write 4026215976Sjmallett Set when L2C_VRT_MEM blocked a store. */ 4027215976Sjmallett uint64_t holewr : 1; /**< Write reference to 256MB hole occurred */ 4028215976Sjmallett uint64_t holerd : 1; /**< Read reference to 256MB hole occurred */ 4029215976Sjmallett#else 4030215976Sjmallett uint64_t holerd : 1; 4031215976Sjmallett uint64_t holewr : 1; 4032215976Sjmallett uint64_t vrtwr : 1; 4033215976Sjmallett uint64_t vrtidrng : 1; 4034215976Sjmallett uint64_t vrtadrng : 1; 4035215976Sjmallett uint64_t vrtpe : 1; 4036215976Sjmallett uint64_t reserved_6_15 : 10; 4037215976Sjmallett uint64_t tad0 : 1; 4038215976Sjmallett uint64_t reserved_17_63 : 47; 4039215976Sjmallett#endif 4040215976Sjmallett } cn63xxp1; 4041232812Sjmallett struct cvmx_l2c_int_reg_cn61xx cn66xx; 4042232812Sjmallett struct cvmx_l2c_int_reg_s cn68xx; 4043232812Sjmallett struct cvmx_l2c_int_reg_s cn68xxp1; 4044232812Sjmallett struct cvmx_l2c_int_reg_cn61xx cnf71xx; 4045215976Sjmallett}; 4046215976Sjmalletttypedef union cvmx_l2c_int_reg cvmx_l2c_int_reg_t; 4047215976Sjmallett 4048215976Sjmallett/** 4049215976Sjmallett * cvmx_l2c_int_stat 4050215976Sjmallett * 4051215976Sjmallett * L2C_INT_STAT = L2C Global Interrupt Status Register 4052215976Sjmallett * 4053215976Sjmallett * Description: 4054215976Sjmallett */ 4055232812Sjmallettunion cvmx_l2c_int_stat { 4056215976Sjmallett uint64_t u64; 4057232812Sjmallett struct cvmx_l2c_int_stat_s { 4058232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4059215976Sjmallett uint64_t reserved_9_63 : 55; 4060215976Sjmallett uint64_t lck2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 4061215976Sjmallett could not find an available/unlocked set (for 4062215976Sjmallett replacement). 4063215976Sjmallett Most likely, this is a result of SW mixing SET 4064215976Sjmallett PARTITIONING with ADDRESS LOCKING. If SW allows 4065215976Sjmallett another PP to LOCKDOWN all SETs available to PP#n, 4066215976Sjmallett then a Rd/Wr Miss from PP#n will be unable 4067215976Sjmallett to determine a 'valid' replacement set (since LOCKED 4068215976Sjmallett addresses should NEVER be replaced). 4069215976Sjmallett If such an event occurs, the HW will select the smallest 4070215976Sjmallett available SET(specified by UMSK'x)' as the replacement 4071215976Sjmallett set, and the address is unlocked. 4072215976Sjmallett NOTE: This is the 'same' bit as L2T_ERR[LCKERR2] */ 4073215976Sjmallett uint64_t lck : 1; /**< SW attempted to LOCK DOWN the last available set of 4074215976Sjmallett the INDEX (which is ignored by HW - but reported to SW). 4075215976Sjmallett The LDD(L1 load-miss) for the LOCK operation is completed 4076215976Sjmallett successfully, however the address is NOT locked. 4077215976Sjmallett NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 4078215976Sjmallett into account. For example, if diagnostic PPx has 4079215976Sjmallett UMSKx defined to only use SETs [1:0], and SET1 had 4080215976Sjmallett been previously LOCKED, then an attempt to LOCK the 4081215976Sjmallett last available SET0 would result in a LCKERR. (This 4082215976Sjmallett is to ensure that at least 1 SET at each INDEX is 4083215976Sjmallett not LOCKED for general use by other PPs). 4084215976Sjmallett NOTE: This is the 'same' bit as L2T_ERR[LCKERR] */ 4085215976Sjmallett uint64_t l2dded : 1; /**< L2D Double Error detected (DED) 4086215976Sjmallett NOTE: This is the 'same' bit as L2D_ERR[DED_ERR] */ 4087215976Sjmallett uint64_t l2dsec : 1; /**< L2D Single Error corrected (SEC) 4088215976Sjmallett NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR] */ 4089215976Sjmallett uint64_t l2tded : 1; /**< L2T Double Bit Error detected (DED) 4090215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 4091215976Sjmallett given index) are checked for double bit errors(DBEs). 4092215976Sjmallett This bit is set if ANY of the 8 sets contains a DBE. 4093215976Sjmallett DBEs also generated an interrupt(if enabled). 4094215976Sjmallett NOTE: This is the 'same' bit as L2T_ERR[DED_ERR] */ 4095215976Sjmallett uint64_t l2tsec : 1; /**< L2T Single Bit Error corrected (SEC) status 4096215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 4097215976Sjmallett given index) are checked for single bit errors(SBEs). 4098215976Sjmallett This bit is set if ANY of the 8 sets contains an SBE. 4099215976Sjmallett SBEs are auto corrected in HW and generate an 4100215976Sjmallett interrupt(if enabled). 4101215976Sjmallett NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR] */ 4102215976Sjmallett uint64_t oob3 : 1; /**< DMA Out of Bounds Interrupt Status Range#3 */ 4103215976Sjmallett uint64_t oob2 : 1; /**< DMA Out of Bounds Interrupt Status Range#2 */ 4104215976Sjmallett uint64_t oob1 : 1; /**< DMA Out of Bounds Interrupt Status Range#1 */ 4105215976Sjmallett#else 4106215976Sjmallett uint64_t oob1 : 1; 4107215976Sjmallett uint64_t oob2 : 1; 4108215976Sjmallett uint64_t oob3 : 1; 4109215976Sjmallett uint64_t l2tsec : 1; 4110215976Sjmallett uint64_t l2tded : 1; 4111215976Sjmallett uint64_t l2dsec : 1; 4112215976Sjmallett uint64_t l2dded : 1; 4113215976Sjmallett uint64_t lck : 1; 4114215976Sjmallett uint64_t lck2 : 1; 4115215976Sjmallett uint64_t reserved_9_63 : 55; 4116215976Sjmallett#endif 4117215976Sjmallett } s; 4118215976Sjmallett struct cvmx_l2c_int_stat_s cn52xx; 4119215976Sjmallett struct cvmx_l2c_int_stat_s cn52xxp1; 4120215976Sjmallett struct cvmx_l2c_int_stat_s cn56xx; 4121215976Sjmallett struct cvmx_l2c_int_stat_s cn56xxp1; 4122215976Sjmallett}; 4123215976Sjmalletttypedef union cvmx_l2c_int_stat cvmx_l2c_int_stat_t; 4124215976Sjmallett 4125215976Sjmallett/** 4126215976Sjmallett * cvmx_l2c_ioc#_pfc 4127215976Sjmallett * 4128215976Sjmallett * L2C_IOC_PFC = L2C IOC Performance Counter(s) 4129215976Sjmallett * 4130215976Sjmallett */ 4131232812Sjmallettunion cvmx_l2c_iocx_pfc { 4132215976Sjmallett uint64_t u64; 4133232812Sjmallett struct cvmx_l2c_iocx_pfc_s { 4134232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4135215976Sjmallett uint64_t count : 64; /**< Current counter value */ 4136215976Sjmallett#else 4137215976Sjmallett uint64_t count : 64; 4138215976Sjmallett#endif 4139215976Sjmallett } s; 4140232812Sjmallett struct cvmx_l2c_iocx_pfc_s cn61xx; 4141215976Sjmallett struct cvmx_l2c_iocx_pfc_s cn63xx; 4142215976Sjmallett struct cvmx_l2c_iocx_pfc_s cn63xxp1; 4143232812Sjmallett struct cvmx_l2c_iocx_pfc_s cn66xx; 4144232812Sjmallett struct cvmx_l2c_iocx_pfc_s cn68xx; 4145232812Sjmallett struct cvmx_l2c_iocx_pfc_s cn68xxp1; 4146232812Sjmallett struct cvmx_l2c_iocx_pfc_s cnf71xx; 4147215976Sjmallett}; 4148215976Sjmalletttypedef union cvmx_l2c_iocx_pfc cvmx_l2c_iocx_pfc_t; 4149215976Sjmallett 4150215976Sjmallett/** 4151215976Sjmallett * cvmx_l2c_ior#_pfc 4152215976Sjmallett * 4153215976Sjmallett * L2C_IOR_PFC = L2C IOR Performance Counter(s) 4154215976Sjmallett * 4155215976Sjmallett */ 4156232812Sjmallettunion cvmx_l2c_iorx_pfc { 4157215976Sjmallett uint64_t u64; 4158232812Sjmallett struct cvmx_l2c_iorx_pfc_s { 4159232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4160215976Sjmallett uint64_t count : 64; /**< Current counter value */ 4161215976Sjmallett#else 4162215976Sjmallett uint64_t count : 64; 4163215976Sjmallett#endif 4164215976Sjmallett } s; 4165232812Sjmallett struct cvmx_l2c_iorx_pfc_s cn61xx; 4166215976Sjmallett struct cvmx_l2c_iorx_pfc_s cn63xx; 4167215976Sjmallett struct cvmx_l2c_iorx_pfc_s cn63xxp1; 4168232812Sjmallett struct cvmx_l2c_iorx_pfc_s cn66xx; 4169232812Sjmallett struct cvmx_l2c_iorx_pfc_s cn68xx; 4170232812Sjmallett struct cvmx_l2c_iorx_pfc_s cn68xxp1; 4171232812Sjmallett struct cvmx_l2c_iorx_pfc_s cnf71xx; 4172215976Sjmallett}; 4173215976Sjmalletttypedef union cvmx_l2c_iorx_pfc cvmx_l2c_iorx_pfc_t; 4174215976Sjmallett 4175215976Sjmallett/** 4176215976Sjmallett * cvmx_l2c_lckbase 4177215976Sjmallett * 4178215976Sjmallett * L2C_LCKBASE = L2C LockDown Base Register 4179215976Sjmallett * 4180215976Sjmallett * Description: L2C LockDown Base Register 4181215976Sjmallett * 4182215976Sjmallett * Notes: 4183215976Sjmallett * (1) SW RESTRICTION \#1: SW must manage the L2 Data Store lockdown space such that at least 1 4184215976Sjmallett * set per cache line remains in the 'unlocked' (normal) state to allow general caching operations. 4185215976Sjmallett * If SW violates this restriction, a status bit is set (LCK_ERR) and an interrupt is posted. 4186215976Sjmallett * [this limits the total lockdown space to 7/8ths of the total L2 data store = 896KB] 4187215976Sjmallett * (2) IOB initiated LDI commands are ignored (only PP initiated LDI/LDD commands are considered 4188215976Sjmallett * for lockdown). 4189215976Sjmallett * (3) To 'unlock' a locked cache line, SW can use the FLUSH-INVAL CSR mechanism (see L2C_DBG[FINV]). 4190215976Sjmallett * (4) LCK_ENA MUST only be activated when debug modes are disabled (L2C_DBG[L2T], L2C_DBG[L2D], L2C_DBG[FINV]). 4191215976Sjmallett */ 4192232812Sjmallettunion cvmx_l2c_lckbase { 4193215976Sjmallett uint64_t u64; 4194232812Sjmallett struct cvmx_l2c_lckbase_s { 4195232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4196215976Sjmallett uint64_t reserved_31_63 : 33; 4197215976Sjmallett uint64_t lck_base : 27; /**< Base Memory block address[33:7]. Specifies the 4198215976Sjmallett starting address of the lockdown region. */ 4199215976Sjmallett uint64_t reserved_1_3 : 3; 4200215976Sjmallett uint64_t lck_ena : 1; /**< L2 Cache Lock Enable 4201215976Sjmallett When the LCK_ENA=1, all LDI(I-stream Load) or 4202215976Sjmallett LDD(L1 load-miss) commands issued from the 4203215976Sjmallett diagnostic PP (specified by the L2C_DBG[PPNUM]), 4204215976Sjmallett which fall within a predefined lockdown address 4205215976Sjmallett range (specified by: [lck_base:lck_base+lck_offset]) 4206215976Sjmallett are LOCKED in the L2 cache. The LOCKED state is 4207215976Sjmallett denoted using an explicit L2 Tag bit (L=1). 4208215976Sjmallett If the LOCK request L2-Hits (on ANY SET), then data is 4209215976Sjmallett returned from the L2 and the hit set is updated to the 4210215976Sjmallett LOCKED state. NOTE: If the Hit Set# is outside the 4211215976Sjmallett available sets for a given PP (see UMSK'x'), the 4212215976Sjmallett the LOCK bit is still SET. If the programmer's intent 4213215976Sjmallett is to explicitly LOCK addresses into 'available' sets, 4214215976Sjmallett care must be taken to flush-invalidate the cache first 4215215976Sjmallett (to avoid such situations). Not following this procedure 4216215976Sjmallett can lead to LCKERR2 interrupts. 4217215976Sjmallett If the LOCK request L2-Misses, a replacment set is 4218215976Sjmallett chosen(from the available sets (UMSK'x'). 4219215976Sjmallett If the replacement set contains a dirty-victim it is 4220215976Sjmallett written back to memory. Memory read data is then written 4221215976Sjmallett into the replacement set, and the replacment SET is 4222215976Sjmallett updated to the LOCKED state(L=1). 4223215976Sjmallett NOTE: SETs that contain LOCKED addresses are 4224215976Sjmallett excluded from the replacement set selection algorithm. 4225215976Sjmallett NOTE: The LDD command will allocate the DuTag as normal. 4226215976Sjmallett NOTE: If L2C_CFG[IDXALIAS]=1, the address is 'aliased' first 4227215976Sjmallett before being checked against the lockdown address 4228215976Sjmallett range. To ensure an 'aliased' address is properly locked, 4229215976Sjmallett it is recommmended that SW preload the 'aliased' locked adddress 4230215976Sjmallett into the L2C_LCKBASE[LCK_BASE] register (while keeping 4231215976Sjmallett L2C_LCKOFF[LCK_OFFSET]=0). 4232215976Sjmallett NOTE: The OCTEON(N3) implementation only supports 16GB(MAX) of 4233215976Sjmallett physical memory. Therefore, only byte address[33:0] are used 4234215976Sjmallett (ie: address[35:34] are ignored). */ 4235215976Sjmallett#else 4236215976Sjmallett uint64_t lck_ena : 1; 4237215976Sjmallett uint64_t reserved_1_3 : 3; 4238215976Sjmallett uint64_t lck_base : 27; 4239215976Sjmallett uint64_t reserved_31_63 : 33; 4240215976Sjmallett#endif 4241215976Sjmallett } s; 4242215976Sjmallett struct cvmx_l2c_lckbase_s cn30xx; 4243215976Sjmallett struct cvmx_l2c_lckbase_s cn31xx; 4244215976Sjmallett struct cvmx_l2c_lckbase_s cn38xx; 4245215976Sjmallett struct cvmx_l2c_lckbase_s cn38xxp2; 4246215976Sjmallett struct cvmx_l2c_lckbase_s cn50xx; 4247215976Sjmallett struct cvmx_l2c_lckbase_s cn52xx; 4248215976Sjmallett struct cvmx_l2c_lckbase_s cn52xxp1; 4249215976Sjmallett struct cvmx_l2c_lckbase_s cn56xx; 4250215976Sjmallett struct cvmx_l2c_lckbase_s cn56xxp1; 4251215976Sjmallett struct cvmx_l2c_lckbase_s cn58xx; 4252215976Sjmallett struct cvmx_l2c_lckbase_s cn58xxp1; 4253215976Sjmallett}; 4254215976Sjmalletttypedef union cvmx_l2c_lckbase cvmx_l2c_lckbase_t; 4255215976Sjmallett 4256215976Sjmallett/** 4257215976Sjmallett * cvmx_l2c_lckoff 4258215976Sjmallett * 4259215976Sjmallett * L2C_LCKOFF = L2C LockDown OFFSET Register 4260215976Sjmallett * 4261215976Sjmallett * Description: L2C LockDown OFFSET Register 4262215976Sjmallett * 4263215976Sjmallett * Notes: 4264215976Sjmallett * (1) The generation of the end lockdown block address will 'wrap'. 4265215976Sjmallett * (2) The minimum granularity for lockdown is 1 cache line (= 128B block) 4266215976Sjmallett */ 4267232812Sjmallettunion cvmx_l2c_lckoff { 4268215976Sjmallett uint64_t u64; 4269232812Sjmallett struct cvmx_l2c_lckoff_s { 4270232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4271215976Sjmallett uint64_t reserved_10_63 : 54; 4272215976Sjmallett uint64_t lck_offset : 10; /**< LockDown block Offset. Used in determining 4273215976Sjmallett the ending block address of the lockdown 4274215976Sjmallett region: 4275215976Sjmallett End Lockdown block Address[33:7] = 4276215976Sjmallett LCK_BASE[33:7]+LCK_OFFSET[9:0] */ 4277215976Sjmallett#else 4278215976Sjmallett uint64_t lck_offset : 10; 4279215976Sjmallett uint64_t reserved_10_63 : 54; 4280215976Sjmallett#endif 4281215976Sjmallett } s; 4282215976Sjmallett struct cvmx_l2c_lckoff_s cn30xx; 4283215976Sjmallett struct cvmx_l2c_lckoff_s cn31xx; 4284215976Sjmallett struct cvmx_l2c_lckoff_s cn38xx; 4285215976Sjmallett struct cvmx_l2c_lckoff_s cn38xxp2; 4286215976Sjmallett struct cvmx_l2c_lckoff_s cn50xx; 4287215976Sjmallett struct cvmx_l2c_lckoff_s cn52xx; 4288215976Sjmallett struct cvmx_l2c_lckoff_s cn52xxp1; 4289215976Sjmallett struct cvmx_l2c_lckoff_s cn56xx; 4290215976Sjmallett struct cvmx_l2c_lckoff_s cn56xxp1; 4291215976Sjmallett struct cvmx_l2c_lckoff_s cn58xx; 4292215976Sjmallett struct cvmx_l2c_lckoff_s cn58xxp1; 4293215976Sjmallett}; 4294215976Sjmalletttypedef union cvmx_l2c_lckoff cvmx_l2c_lckoff_t; 4295215976Sjmallett 4296215976Sjmallett/** 4297215976Sjmallett * cvmx_l2c_lfb0 4298215976Sjmallett * 4299215976Sjmallett * L2C_LFB0 = L2C LFB DEBUG 0 Register 4300215976Sjmallett * 4301215976Sjmallett * Description: L2C LFB Contents (Status Bits) 4302215976Sjmallett */ 4303232812Sjmallettunion cvmx_l2c_lfb0 { 4304215976Sjmallett uint64_t u64; 4305232812Sjmallett struct cvmx_l2c_lfb0_s { 4306232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4307215976Sjmallett uint64_t reserved_32_63 : 32; 4308215976Sjmallett uint64_t stcpnd : 1; /**< LFB STC Pending Status */ 4309215976Sjmallett uint64_t stpnd : 1; /**< LFB ST* Pending Status */ 4310215976Sjmallett uint64_t stinv : 1; /**< LFB ST* Invalidate Status */ 4311215976Sjmallett uint64_t stcfl : 1; /**< LFB STC=FAIL Status */ 4312215976Sjmallett uint64_t vam : 1; /**< Valid Full Address Match Status */ 4313215976Sjmallett uint64_t inxt : 4; /**< Next LFB Pointer(invalid if ITL=1) */ 4314215976Sjmallett uint64_t itl : 1; /**< LFB Tail of List Indicator */ 4315215976Sjmallett uint64_t ihd : 1; /**< LFB Head of List Indicator */ 4316215976Sjmallett uint64_t set : 3; /**< SET# used for DS-OP (hit=hset/miss=rset) */ 4317215976Sjmallett uint64_t vabnum : 4; /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */ 4318215976Sjmallett uint64_t sid : 9; /**< LFB Source ID */ 4319215976Sjmallett uint64_t cmd : 4; /**< LFB Command */ 4320215976Sjmallett uint64_t vld : 1; /**< LFB Valid */ 4321215976Sjmallett#else 4322215976Sjmallett uint64_t vld : 1; 4323215976Sjmallett uint64_t cmd : 4; 4324215976Sjmallett uint64_t sid : 9; 4325215976Sjmallett uint64_t vabnum : 4; 4326215976Sjmallett uint64_t set : 3; 4327215976Sjmallett uint64_t ihd : 1; 4328215976Sjmallett uint64_t itl : 1; 4329215976Sjmallett uint64_t inxt : 4; 4330215976Sjmallett uint64_t vam : 1; 4331215976Sjmallett uint64_t stcfl : 1; 4332215976Sjmallett uint64_t stinv : 1; 4333215976Sjmallett uint64_t stpnd : 1; 4334215976Sjmallett uint64_t stcpnd : 1; 4335215976Sjmallett uint64_t reserved_32_63 : 32; 4336215976Sjmallett#endif 4337215976Sjmallett } s; 4338232812Sjmallett struct cvmx_l2c_lfb0_cn30xx { 4339232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4340215976Sjmallett uint64_t reserved_32_63 : 32; 4341215976Sjmallett uint64_t stcpnd : 1; /**< LFB STC Pending Status */ 4342215976Sjmallett uint64_t stpnd : 1; /**< LFB ST* Pending Status */ 4343215976Sjmallett uint64_t stinv : 1; /**< LFB ST* Invalidate Status */ 4344215976Sjmallett uint64_t stcfl : 1; /**< LFB STC=FAIL Status */ 4345215976Sjmallett uint64_t vam : 1; /**< Valid Full Address Match Status */ 4346215976Sjmallett uint64_t reserved_25_26 : 2; 4347215976Sjmallett uint64_t inxt : 2; /**< Next LFB Pointer(invalid if ITL=1) */ 4348215976Sjmallett uint64_t itl : 1; /**< LFB Tail of List Indicator */ 4349215976Sjmallett uint64_t ihd : 1; /**< LFB Head of List Indicator */ 4350215976Sjmallett uint64_t reserved_20_20 : 1; 4351215976Sjmallett uint64_t set : 2; /**< SET# used for DS-OP (hit=hset/miss=rset) */ 4352215976Sjmallett uint64_t reserved_16_17 : 2; 4353215976Sjmallett uint64_t vabnum : 2; /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */ 4354215976Sjmallett uint64_t sid : 9; /**< LFB Source ID */ 4355215976Sjmallett uint64_t cmd : 4; /**< LFB Command */ 4356215976Sjmallett uint64_t vld : 1; /**< LFB Valid */ 4357215976Sjmallett#else 4358215976Sjmallett uint64_t vld : 1; 4359215976Sjmallett uint64_t cmd : 4; 4360215976Sjmallett uint64_t sid : 9; 4361215976Sjmallett uint64_t vabnum : 2; 4362215976Sjmallett uint64_t reserved_16_17 : 2; 4363215976Sjmallett uint64_t set : 2; 4364215976Sjmallett uint64_t reserved_20_20 : 1; 4365215976Sjmallett uint64_t ihd : 1; 4366215976Sjmallett uint64_t itl : 1; 4367215976Sjmallett uint64_t inxt : 2; 4368215976Sjmallett uint64_t reserved_25_26 : 2; 4369215976Sjmallett uint64_t vam : 1; 4370215976Sjmallett uint64_t stcfl : 1; 4371215976Sjmallett uint64_t stinv : 1; 4372215976Sjmallett uint64_t stpnd : 1; 4373215976Sjmallett uint64_t stcpnd : 1; 4374215976Sjmallett uint64_t reserved_32_63 : 32; 4375215976Sjmallett#endif 4376215976Sjmallett } cn30xx; 4377232812Sjmallett struct cvmx_l2c_lfb0_cn31xx { 4378232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4379215976Sjmallett uint64_t reserved_32_63 : 32; 4380215976Sjmallett uint64_t stcpnd : 1; /**< LFB STC Pending Status */ 4381215976Sjmallett uint64_t stpnd : 1; /**< LFB ST* Pending Status */ 4382215976Sjmallett uint64_t stinv : 1; /**< LFB ST* Invalidate Status */ 4383215976Sjmallett uint64_t stcfl : 1; /**< LFB STC=FAIL Status */ 4384215976Sjmallett uint64_t vam : 1; /**< Valid Full Address Match Status */ 4385215976Sjmallett uint64_t reserved_26_26 : 1; 4386215976Sjmallett uint64_t inxt : 3; /**< Next LFB Pointer(invalid if ITL=1) */ 4387215976Sjmallett uint64_t itl : 1; /**< LFB Tail of List Indicator */ 4388215976Sjmallett uint64_t ihd : 1; /**< LFB Head of List Indicator */ 4389215976Sjmallett uint64_t reserved_20_20 : 1; 4390215976Sjmallett uint64_t set : 2; /**< SET# used for DS-OP (hit=hset/miss=rset) */ 4391215976Sjmallett uint64_t reserved_17_17 : 1; 4392215976Sjmallett uint64_t vabnum : 3; /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */ 4393215976Sjmallett uint64_t sid : 9; /**< LFB Source ID */ 4394215976Sjmallett uint64_t cmd : 4; /**< LFB Command */ 4395215976Sjmallett uint64_t vld : 1; /**< LFB Valid */ 4396215976Sjmallett#else 4397215976Sjmallett uint64_t vld : 1; 4398215976Sjmallett uint64_t cmd : 4; 4399215976Sjmallett uint64_t sid : 9; 4400215976Sjmallett uint64_t vabnum : 3; 4401215976Sjmallett uint64_t reserved_17_17 : 1; 4402215976Sjmallett uint64_t set : 2; 4403215976Sjmallett uint64_t reserved_20_20 : 1; 4404215976Sjmallett uint64_t ihd : 1; 4405215976Sjmallett uint64_t itl : 1; 4406215976Sjmallett uint64_t inxt : 3; 4407215976Sjmallett uint64_t reserved_26_26 : 1; 4408215976Sjmallett uint64_t vam : 1; 4409215976Sjmallett uint64_t stcfl : 1; 4410215976Sjmallett uint64_t stinv : 1; 4411215976Sjmallett uint64_t stpnd : 1; 4412215976Sjmallett uint64_t stcpnd : 1; 4413215976Sjmallett uint64_t reserved_32_63 : 32; 4414215976Sjmallett#endif 4415215976Sjmallett } cn31xx; 4416215976Sjmallett struct cvmx_l2c_lfb0_s cn38xx; 4417215976Sjmallett struct cvmx_l2c_lfb0_s cn38xxp2; 4418232812Sjmallett struct cvmx_l2c_lfb0_cn50xx { 4419232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4420215976Sjmallett uint64_t reserved_32_63 : 32; 4421215976Sjmallett uint64_t stcpnd : 1; /**< LFB STC Pending Status */ 4422215976Sjmallett uint64_t stpnd : 1; /**< LFB ST* Pending Status */ 4423215976Sjmallett uint64_t stinv : 1; /**< LFB ST* Invalidate Status */ 4424215976Sjmallett uint64_t stcfl : 1; /**< LFB STC=FAIL Status */ 4425215976Sjmallett uint64_t vam : 1; /**< Valid Full Address Match Status */ 4426215976Sjmallett uint64_t reserved_26_26 : 1; 4427215976Sjmallett uint64_t inxt : 3; /**< Next LFB Pointer(invalid if ITL=1) */ 4428215976Sjmallett uint64_t itl : 1; /**< LFB Tail of List Indicator */ 4429215976Sjmallett uint64_t ihd : 1; /**< LFB Head of List Indicator */ 4430215976Sjmallett uint64_t set : 3; /**< SET# used for DS-OP (hit=hset/miss=rset) */ 4431215976Sjmallett uint64_t reserved_17_17 : 1; 4432215976Sjmallett uint64_t vabnum : 3; /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */ 4433215976Sjmallett uint64_t sid : 9; /**< LFB Source ID */ 4434215976Sjmallett uint64_t cmd : 4; /**< LFB Command */ 4435215976Sjmallett uint64_t vld : 1; /**< LFB Valid */ 4436215976Sjmallett#else 4437215976Sjmallett uint64_t vld : 1; 4438215976Sjmallett uint64_t cmd : 4; 4439215976Sjmallett uint64_t sid : 9; 4440215976Sjmallett uint64_t vabnum : 3; 4441215976Sjmallett uint64_t reserved_17_17 : 1; 4442215976Sjmallett uint64_t set : 3; 4443215976Sjmallett uint64_t ihd : 1; 4444215976Sjmallett uint64_t itl : 1; 4445215976Sjmallett uint64_t inxt : 3; 4446215976Sjmallett uint64_t reserved_26_26 : 1; 4447215976Sjmallett uint64_t vam : 1; 4448215976Sjmallett uint64_t stcfl : 1; 4449215976Sjmallett uint64_t stinv : 1; 4450215976Sjmallett uint64_t stpnd : 1; 4451215976Sjmallett uint64_t stcpnd : 1; 4452215976Sjmallett uint64_t reserved_32_63 : 32; 4453215976Sjmallett#endif 4454215976Sjmallett } cn50xx; 4455215976Sjmallett struct cvmx_l2c_lfb0_cn50xx cn52xx; 4456215976Sjmallett struct cvmx_l2c_lfb0_cn50xx cn52xxp1; 4457215976Sjmallett struct cvmx_l2c_lfb0_s cn56xx; 4458215976Sjmallett struct cvmx_l2c_lfb0_s cn56xxp1; 4459215976Sjmallett struct cvmx_l2c_lfb0_s cn58xx; 4460215976Sjmallett struct cvmx_l2c_lfb0_s cn58xxp1; 4461215976Sjmallett}; 4462215976Sjmalletttypedef union cvmx_l2c_lfb0 cvmx_l2c_lfb0_t; 4463215976Sjmallett 4464215976Sjmallett/** 4465215976Sjmallett * cvmx_l2c_lfb1 4466215976Sjmallett * 4467215976Sjmallett * L2C_LFB1 = L2C LFB DEBUG 1 Register 4468215976Sjmallett * 4469215976Sjmallett * Description: L2C LFB Contents (Wait Bits) 4470215976Sjmallett */ 4471232812Sjmallettunion cvmx_l2c_lfb1 { 4472215976Sjmallett uint64_t u64; 4473232812Sjmallett struct cvmx_l2c_lfb1_s { 4474232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4475215976Sjmallett uint64_t reserved_19_63 : 45; 4476215976Sjmallett uint64_t dsgoing : 1; /**< LFB DS Going (in flight) */ 4477215976Sjmallett uint64_t bid : 2; /**< LFB DS Bid# */ 4478215976Sjmallett uint64_t wtrsp : 1; /**< LFB Waiting for RSC Response [FILL,STRSP] completion */ 4479215976Sjmallett uint64_t wtdw : 1; /**< LFB Waiting for DS-WR completion */ 4480215976Sjmallett uint64_t wtdq : 1; /**< LFB Waiting for LFB-DQ */ 4481215976Sjmallett uint64_t wtwhp : 1; /**< LFB Waiting for Write-Hit Partial L2 DS-WR completion */ 4482215976Sjmallett uint64_t wtwhf : 1; /**< LFB Waiting for Write-Hit Full L2 DS-WR completion */ 4483215976Sjmallett uint64_t wtwrm : 1; /**< LFB Waiting for Write-Miss L2 DS-WR completion */ 4484215976Sjmallett uint64_t wtstm : 1; /**< LFB Waiting for Write-Miss L2 DS-WR completion */ 4485215976Sjmallett uint64_t wtrda : 1; /**< LFB Waiting for Read-Miss L2 DS-WR completion */ 4486215976Sjmallett uint64_t wtstdt : 1; /**< LFB Waiting for all ST write Data to arrive on XMD bus */ 4487215976Sjmallett uint64_t wtstrsp : 1; /**< LFB Waiting for ST RSC/RSD to be issued on RSP 4488215976Sjmallett (with invalidates) */ 4489215976Sjmallett uint64_t wtstrsc : 1; /**< LFB Waiting for ST RSC-Only to be issued on RSP 4490215976Sjmallett (no-invalidates) */ 4491215976Sjmallett uint64_t wtvtm : 1; /**< LFB Waiting for Victim Read L2 DS-RD completion */ 4492215976Sjmallett uint64_t wtmfl : 1; /**< LFB Waiting for Memory Fill completion to MRB */ 4493215976Sjmallett uint64_t prbrty : 1; /**< Probe-Retry Detected - waiting for probe completion */ 4494215976Sjmallett uint64_t wtprb : 1; /**< LFB Waiting for Probe */ 4495215976Sjmallett uint64_t vld : 1; /**< LFB Valid */ 4496215976Sjmallett#else 4497215976Sjmallett uint64_t vld : 1; 4498215976Sjmallett uint64_t wtprb : 1; 4499215976Sjmallett uint64_t prbrty : 1; 4500215976Sjmallett uint64_t wtmfl : 1; 4501215976Sjmallett uint64_t wtvtm : 1; 4502215976Sjmallett uint64_t wtstrsc : 1; 4503215976Sjmallett uint64_t wtstrsp : 1; 4504215976Sjmallett uint64_t wtstdt : 1; 4505215976Sjmallett uint64_t wtrda : 1; 4506215976Sjmallett uint64_t wtstm : 1; 4507215976Sjmallett uint64_t wtwrm : 1; 4508215976Sjmallett uint64_t wtwhf : 1; 4509215976Sjmallett uint64_t wtwhp : 1; 4510215976Sjmallett uint64_t wtdq : 1; 4511215976Sjmallett uint64_t wtdw : 1; 4512215976Sjmallett uint64_t wtrsp : 1; 4513215976Sjmallett uint64_t bid : 2; 4514215976Sjmallett uint64_t dsgoing : 1; 4515215976Sjmallett uint64_t reserved_19_63 : 45; 4516215976Sjmallett#endif 4517215976Sjmallett } s; 4518215976Sjmallett struct cvmx_l2c_lfb1_s cn30xx; 4519215976Sjmallett struct cvmx_l2c_lfb1_s cn31xx; 4520215976Sjmallett struct cvmx_l2c_lfb1_s cn38xx; 4521215976Sjmallett struct cvmx_l2c_lfb1_s cn38xxp2; 4522215976Sjmallett struct cvmx_l2c_lfb1_s cn50xx; 4523215976Sjmallett struct cvmx_l2c_lfb1_s cn52xx; 4524215976Sjmallett struct cvmx_l2c_lfb1_s cn52xxp1; 4525215976Sjmallett struct cvmx_l2c_lfb1_s cn56xx; 4526215976Sjmallett struct cvmx_l2c_lfb1_s cn56xxp1; 4527215976Sjmallett struct cvmx_l2c_lfb1_s cn58xx; 4528215976Sjmallett struct cvmx_l2c_lfb1_s cn58xxp1; 4529215976Sjmallett}; 4530215976Sjmalletttypedef union cvmx_l2c_lfb1 cvmx_l2c_lfb1_t; 4531215976Sjmallett 4532215976Sjmallett/** 4533215976Sjmallett * cvmx_l2c_lfb2 4534215976Sjmallett * 4535215976Sjmallett * L2C_LFB2 = L2C LFB DEBUG 2 Register 4536215976Sjmallett * 4537215976Sjmallett * Description: L2C LFB Contents Tag/Index 4538215976Sjmallett */ 4539232812Sjmallettunion cvmx_l2c_lfb2 { 4540215976Sjmallett uint64_t u64; 4541232812Sjmallett struct cvmx_l2c_lfb2_s { 4542232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4543215976Sjmallett uint64_t reserved_0_63 : 64; 4544215976Sjmallett#else 4545215976Sjmallett uint64_t reserved_0_63 : 64; 4546215976Sjmallett#endif 4547215976Sjmallett } s; 4548232812Sjmallett struct cvmx_l2c_lfb2_cn30xx { 4549232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4550215976Sjmallett uint64_t reserved_27_63 : 37; 4551215976Sjmallett uint64_t lfb_tag : 19; /**< LFB TAG[33:15] */ 4552215976Sjmallett uint64_t lfb_idx : 8; /**< LFB IDX[14:7] */ 4553215976Sjmallett#else 4554215976Sjmallett uint64_t lfb_idx : 8; 4555215976Sjmallett uint64_t lfb_tag : 19; 4556215976Sjmallett uint64_t reserved_27_63 : 37; 4557215976Sjmallett#endif 4558215976Sjmallett } cn30xx; 4559232812Sjmallett struct cvmx_l2c_lfb2_cn31xx { 4560232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4561215976Sjmallett uint64_t reserved_27_63 : 37; 4562215976Sjmallett uint64_t lfb_tag : 17; /**< LFB TAG[33:16] */ 4563215976Sjmallett uint64_t lfb_idx : 10; /**< LFB IDX[15:7] */ 4564215976Sjmallett#else 4565215976Sjmallett uint64_t lfb_idx : 10; 4566215976Sjmallett uint64_t lfb_tag : 17; 4567215976Sjmallett uint64_t reserved_27_63 : 37; 4568215976Sjmallett#endif 4569215976Sjmallett } cn31xx; 4570215976Sjmallett struct cvmx_l2c_lfb2_cn31xx cn38xx; 4571215976Sjmallett struct cvmx_l2c_lfb2_cn31xx cn38xxp2; 4572232812Sjmallett struct cvmx_l2c_lfb2_cn50xx { 4573232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4574215976Sjmallett uint64_t reserved_27_63 : 37; 4575215976Sjmallett uint64_t lfb_tag : 20; /**< LFB TAG[33:14] */ 4576215976Sjmallett uint64_t lfb_idx : 7; /**< LFB IDX[13:7] */ 4577215976Sjmallett#else 4578215976Sjmallett uint64_t lfb_idx : 7; 4579215976Sjmallett uint64_t lfb_tag : 20; 4580215976Sjmallett uint64_t reserved_27_63 : 37; 4581215976Sjmallett#endif 4582215976Sjmallett } cn50xx; 4583232812Sjmallett struct cvmx_l2c_lfb2_cn52xx { 4584232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4585215976Sjmallett uint64_t reserved_27_63 : 37; 4586215976Sjmallett uint64_t lfb_tag : 18; /**< LFB TAG[33:16] */ 4587215976Sjmallett uint64_t lfb_idx : 9; /**< LFB IDX[15:7] */ 4588215976Sjmallett#else 4589215976Sjmallett uint64_t lfb_idx : 9; 4590215976Sjmallett uint64_t lfb_tag : 18; 4591215976Sjmallett uint64_t reserved_27_63 : 37; 4592215976Sjmallett#endif 4593215976Sjmallett } cn52xx; 4594215976Sjmallett struct cvmx_l2c_lfb2_cn52xx cn52xxp1; 4595232812Sjmallett struct cvmx_l2c_lfb2_cn56xx { 4596232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4597215976Sjmallett uint64_t reserved_27_63 : 37; 4598215976Sjmallett uint64_t lfb_tag : 16; /**< LFB TAG[33:18] */ 4599215976Sjmallett uint64_t lfb_idx : 11; /**< LFB IDX[17:7] */ 4600215976Sjmallett#else 4601215976Sjmallett uint64_t lfb_idx : 11; 4602215976Sjmallett uint64_t lfb_tag : 16; 4603215976Sjmallett uint64_t reserved_27_63 : 37; 4604215976Sjmallett#endif 4605215976Sjmallett } cn56xx; 4606215976Sjmallett struct cvmx_l2c_lfb2_cn56xx cn56xxp1; 4607215976Sjmallett struct cvmx_l2c_lfb2_cn56xx cn58xx; 4608215976Sjmallett struct cvmx_l2c_lfb2_cn56xx cn58xxp1; 4609215976Sjmallett}; 4610215976Sjmalletttypedef union cvmx_l2c_lfb2 cvmx_l2c_lfb2_t; 4611215976Sjmallett 4612215976Sjmallett/** 4613215976Sjmallett * cvmx_l2c_lfb3 4614215976Sjmallett * 4615215976Sjmallett * L2C_LFB3 = L2C LFB DEBUG 3 Register 4616215976Sjmallett * 4617215976Sjmallett * Description: LFB High Water Mark Register 4618215976Sjmallett */ 4619232812Sjmallettunion cvmx_l2c_lfb3 { 4620215976Sjmallett uint64_t u64; 4621232812Sjmallett struct cvmx_l2c_lfb3_s { 4622232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4623215976Sjmallett uint64_t reserved_5_63 : 59; 4624215976Sjmallett uint64_t stpartdis : 1; /**< STP/C Performance Enhancement Disable 4625215976Sjmallett When clear, all STP/C(store partials) will take 2 cycles 4626215976Sjmallett to complete (power-on default). 4627215976Sjmallett When set, all STP/C(store partials) will take 4 cycles 4628215976Sjmallett to complete. 4629215976Sjmallett NOTE: It is recommended to keep this bit ALWAYS ZERO. */ 4630215976Sjmallett uint64_t lfb_hwm : 4; /**< LFB High Water Mark 4631215976Sjmallett Determines \#of LFB Entries in use before backpressure 4632215976Sjmallett is asserted. 4633215976Sjmallett HWM=0: 1 LFB Entry available 4634215976Sjmallett - ... 4635215976Sjmallett HWM=15: 16 LFB Entries available */ 4636215976Sjmallett#else 4637215976Sjmallett uint64_t lfb_hwm : 4; 4638215976Sjmallett uint64_t stpartdis : 1; 4639215976Sjmallett uint64_t reserved_5_63 : 59; 4640215976Sjmallett#endif 4641215976Sjmallett } s; 4642232812Sjmallett struct cvmx_l2c_lfb3_cn30xx { 4643232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4644215976Sjmallett uint64_t reserved_5_63 : 59; 4645215976Sjmallett uint64_t stpartdis : 1; /**< STP/C Performance Enhancement Disable 4646215976Sjmallett When clear, all STP/C(store partials) will take 2 cycles 4647215976Sjmallett to complete (power-on default). 4648215976Sjmallett When set, all STP/C(store partials) will take 4 cycles 4649215976Sjmallett to complete. 4650215976Sjmallett NOTE: It is recommended to keep this bit ALWAYS ZERO. */ 4651215976Sjmallett uint64_t reserved_2_3 : 2; 4652215976Sjmallett uint64_t lfb_hwm : 2; /**< LFB High Water Mark 4653215976Sjmallett Determines \#of LFB Entries in use before backpressure 4654215976Sjmallett is asserted. 4655215976Sjmallett HWM=0: 1 LFB Entry available 4656215976Sjmallett - ... 4657215976Sjmallett HWM=3: 4 LFB Entries available */ 4658215976Sjmallett#else 4659215976Sjmallett uint64_t lfb_hwm : 2; 4660215976Sjmallett uint64_t reserved_2_3 : 2; 4661215976Sjmallett uint64_t stpartdis : 1; 4662215976Sjmallett uint64_t reserved_5_63 : 59; 4663215976Sjmallett#endif 4664215976Sjmallett } cn30xx; 4665232812Sjmallett struct cvmx_l2c_lfb3_cn31xx { 4666232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4667215976Sjmallett uint64_t reserved_5_63 : 59; 4668215976Sjmallett uint64_t stpartdis : 1; /**< STP/C Performance Enhancement Disable 4669215976Sjmallett When clear, all STP/C(store partials) will take 2 cycles 4670215976Sjmallett to complete (power-on default). 4671215976Sjmallett When set, all STP/C(store partials) will take 4 cycles 4672215976Sjmallett to complete. 4673215976Sjmallett NOTE: It is recommended to keep this bit ALWAYS ZERO. */ 4674215976Sjmallett uint64_t reserved_3_3 : 1; 4675215976Sjmallett uint64_t lfb_hwm : 3; /**< LFB High Water Mark 4676215976Sjmallett Determines \#of LFB Entries in use before backpressure 4677215976Sjmallett is asserted. 4678215976Sjmallett HWM=0: 1 LFB Entry available 4679215976Sjmallett - ... 4680215976Sjmallett HWM=7: 8 LFB Entries available */ 4681215976Sjmallett#else 4682215976Sjmallett uint64_t lfb_hwm : 3; 4683215976Sjmallett uint64_t reserved_3_3 : 1; 4684215976Sjmallett uint64_t stpartdis : 1; 4685215976Sjmallett uint64_t reserved_5_63 : 59; 4686215976Sjmallett#endif 4687215976Sjmallett } cn31xx; 4688215976Sjmallett struct cvmx_l2c_lfb3_s cn38xx; 4689215976Sjmallett struct cvmx_l2c_lfb3_s cn38xxp2; 4690215976Sjmallett struct cvmx_l2c_lfb3_cn31xx cn50xx; 4691215976Sjmallett struct cvmx_l2c_lfb3_cn31xx cn52xx; 4692215976Sjmallett struct cvmx_l2c_lfb3_cn31xx cn52xxp1; 4693215976Sjmallett struct cvmx_l2c_lfb3_s cn56xx; 4694215976Sjmallett struct cvmx_l2c_lfb3_s cn56xxp1; 4695215976Sjmallett struct cvmx_l2c_lfb3_s cn58xx; 4696215976Sjmallett struct cvmx_l2c_lfb3_s cn58xxp1; 4697215976Sjmallett}; 4698215976Sjmalletttypedef union cvmx_l2c_lfb3 cvmx_l2c_lfb3_t; 4699215976Sjmallett 4700215976Sjmallett/** 4701215976Sjmallett * cvmx_l2c_oob 4702215976Sjmallett * 4703215976Sjmallett * L2C_OOB = L2C Out of Bounds Global Enables 4704215976Sjmallett * 4705215976Sjmallett * Description: Defines DMA "Out of Bounds" global enables. 4706215976Sjmallett */ 4707232812Sjmallettunion cvmx_l2c_oob { 4708215976Sjmallett uint64_t u64; 4709232812Sjmallett struct cvmx_l2c_oob_s { 4710232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4711215976Sjmallett uint64_t reserved_2_63 : 62; 4712215976Sjmallett uint64_t dwbena : 1; /**< DMA Out of Bounds Range Checker for DMA DWB 4713215976Sjmallett commands (Don't WriteBack). 4714215976Sjmallett When enabled, any DMA DWB commands which hit 1-of-3 4715215976Sjmallett out of bounds regions will be logged into 4716215976Sjmallett L2C_INT_STAT[OOB*] CSRs and the DMA store WILL 4717215976Sjmallett NOT occur. If the corresponding L2C_INT_EN[OOB*] 4718215976Sjmallett is enabled, an interrupt will also be reported. */ 4719215976Sjmallett uint64_t stena : 1; /**< DMA Out of Bounds Range Checker for DMA store 4720215976Sjmallett commands (STF/P/T). 4721215976Sjmallett When enabled, any DMA store commands (STF/P/T) which 4722215976Sjmallett hit 1-of-3 out of bounds regions will be logged into 4723215976Sjmallett L2C_INT_STAT[OOB*] CSRs and the DMA store WILL 4724215976Sjmallett NOT occur. If the corresponding L2C_INT_EN[OOB*] 4725215976Sjmallett is enabled, an interrupt will also be reported. */ 4726215976Sjmallett#else 4727215976Sjmallett uint64_t stena : 1; 4728215976Sjmallett uint64_t dwbena : 1; 4729215976Sjmallett uint64_t reserved_2_63 : 62; 4730215976Sjmallett#endif 4731215976Sjmallett } s; 4732215976Sjmallett struct cvmx_l2c_oob_s cn52xx; 4733215976Sjmallett struct cvmx_l2c_oob_s cn52xxp1; 4734215976Sjmallett struct cvmx_l2c_oob_s cn56xx; 4735215976Sjmallett struct cvmx_l2c_oob_s cn56xxp1; 4736215976Sjmallett}; 4737215976Sjmalletttypedef union cvmx_l2c_oob cvmx_l2c_oob_t; 4738215976Sjmallett 4739215976Sjmallett/** 4740215976Sjmallett * cvmx_l2c_oob1 4741215976Sjmallett * 4742215976Sjmallett * L2C_OOB1 = L2C Out of Bounds Range Checker 4743215976Sjmallett * 4744215976Sjmallett * Description: Defines DMA "Out of Bounds" region \#1. If a DMA initiated write transaction generates an address 4745215976Sjmallett * within the specified region, the write is 'ignored' and an interrupt is generated to alert software. 4746215976Sjmallett */ 4747232812Sjmallettunion cvmx_l2c_oob1 { 4748215976Sjmallett uint64_t u64; 4749232812Sjmallett struct cvmx_l2c_oob1_s { 4750232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4751215976Sjmallett uint64_t fadr : 27; /**< DMA initated Memory Range Checker Failing Address 4752215976Sjmallett When L2C_INT_STAT[OOB1]=1, this field indicates the 4753215976Sjmallett DMA cacheline address. 4754215976Sjmallett (addr[33:7] = full cacheline address captured) 4755215976Sjmallett NOTE: FADR is locked down until L2C_INT_STAT[OOB1] 4756215976Sjmallett is cleared. */ 4757215976Sjmallett uint64_t fsrc : 1; /**< DMA Out of Bounds Failing Source Command 4758215976Sjmallett When L2C_INT_STAT[OOB1]=1, this field indicates the 4759215976Sjmallett type of DMA command. 4760215976Sjmallett - 0: ST* (STF/P/T) 4761215976Sjmallett - 1: DWB (Don't WriteBack) 4762215976Sjmallett NOTE: FSRC is locked down until L2C_INT_STAT[OOB1] 4763215976Sjmallett is cleared. */ 4764215976Sjmallett uint64_t reserved_34_35 : 2; 4765215976Sjmallett uint64_t sadr : 14; /**< DMA initated Memory Range Checker Starting Address 4766215976Sjmallett (1MB granularity) */ 4767215976Sjmallett uint64_t reserved_14_19 : 6; 4768215976Sjmallett uint64_t size : 14; /**< DMA Out of Bounds Range Checker Size 4769215976Sjmallett (1MB granularity) 4770215976Sjmallett Example: 0: 0MB / 1: 1MB 4771215976Sjmallett The range check is for: 4772215976Sjmallett (SADR<<20) <= addr[33:0] < (((SADR+SIZE) & 0x3FFF)<<20) 4773215976Sjmallett SW NOTE: SADR+SIZE could be setup to potentially wrap 4774215976Sjmallett the 34bit ending bounds address. */ 4775215976Sjmallett#else 4776215976Sjmallett uint64_t size : 14; 4777215976Sjmallett uint64_t reserved_14_19 : 6; 4778215976Sjmallett uint64_t sadr : 14; 4779215976Sjmallett uint64_t reserved_34_35 : 2; 4780215976Sjmallett uint64_t fsrc : 1; 4781215976Sjmallett uint64_t fadr : 27; 4782215976Sjmallett#endif 4783215976Sjmallett } s; 4784215976Sjmallett struct cvmx_l2c_oob1_s cn52xx; 4785215976Sjmallett struct cvmx_l2c_oob1_s cn52xxp1; 4786215976Sjmallett struct cvmx_l2c_oob1_s cn56xx; 4787215976Sjmallett struct cvmx_l2c_oob1_s cn56xxp1; 4788215976Sjmallett}; 4789215976Sjmalletttypedef union cvmx_l2c_oob1 cvmx_l2c_oob1_t; 4790215976Sjmallett 4791215976Sjmallett/** 4792215976Sjmallett * cvmx_l2c_oob2 4793215976Sjmallett * 4794215976Sjmallett * L2C_OOB2 = L2C Out of Bounds Range Checker 4795215976Sjmallett * 4796215976Sjmallett * Description: Defines DMA "Out of Bounds" region \#2. If a DMA initiated write transaction generates an address 4797215976Sjmallett * within the specified region, the write is 'ignored' and an interrupt is generated to alert software. 4798215976Sjmallett */ 4799232812Sjmallettunion cvmx_l2c_oob2 { 4800215976Sjmallett uint64_t u64; 4801232812Sjmallett struct cvmx_l2c_oob2_s { 4802232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4803215976Sjmallett uint64_t fadr : 27; /**< DMA initated Memory Range Checker Failing Address 4804215976Sjmallett When L2C_INT_STAT[OOB2]=1, this field indicates the 4805215976Sjmallett DMA cacheline address. 4806215976Sjmallett (addr[33:7] = full cacheline address captured) 4807215976Sjmallett NOTE: FADR is locked down until L2C_INT_STAT[OOB2] 4808215976Sjmallett is cleared. */ 4809215976Sjmallett uint64_t fsrc : 1; /**< DMA Out of Bounds Failing Source Command 4810215976Sjmallett When L2C_INT_STAT[OOB2]=1, this field indicates the 4811215976Sjmallett type of DMA command. 4812215976Sjmallett - 0: ST* (STF/P/T) 4813215976Sjmallett - 1: DWB (Don't WriteBack) 4814215976Sjmallett NOTE: FSRC is locked down until L2C_INT_STAT[OOB2] 4815215976Sjmallett is cleared. */ 4816215976Sjmallett uint64_t reserved_34_35 : 2; 4817215976Sjmallett uint64_t sadr : 14; /**< DMA initated Memory Range Checker Starting Address 4818215976Sjmallett (1MB granularity) */ 4819215976Sjmallett uint64_t reserved_14_19 : 6; 4820215976Sjmallett uint64_t size : 14; /**< DMA Out of Bounds Range Checker Size 4821215976Sjmallett (1MB granularity) 4822215976Sjmallett Example: 0: 0MB / 1: 1MB 4823215976Sjmallett The range check is for: 4824215976Sjmallett (SADR<<20) <= addr[33:0] < (((SADR+SIZE) & 0x3FFF)<<20) 4825215976Sjmallett SW NOTE: SADR+SIZE could be setup to potentially wrap 4826215976Sjmallett the 34bit ending bounds address. */ 4827215976Sjmallett#else 4828215976Sjmallett uint64_t size : 14; 4829215976Sjmallett uint64_t reserved_14_19 : 6; 4830215976Sjmallett uint64_t sadr : 14; 4831215976Sjmallett uint64_t reserved_34_35 : 2; 4832215976Sjmallett uint64_t fsrc : 1; 4833215976Sjmallett uint64_t fadr : 27; 4834215976Sjmallett#endif 4835215976Sjmallett } s; 4836215976Sjmallett struct cvmx_l2c_oob2_s cn52xx; 4837215976Sjmallett struct cvmx_l2c_oob2_s cn52xxp1; 4838215976Sjmallett struct cvmx_l2c_oob2_s cn56xx; 4839215976Sjmallett struct cvmx_l2c_oob2_s cn56xxp1; 4840215976Sjmallett}; 4841215976Sjmalletttypedef union cvmx_l2c_oob2 cvmx_l2c_oob2_t; 4842215976Sjmallett 4843215976Sjmallett/** 4844215976Sjmallett * cvmx_l2c_oob3 4845215976Sjmallett * 4846215976Sjmallett * L2C_OOB3 = L2C Out of Bounds Range Checker 4847215976Sjmallett * 4848215976Sjmallett * Description: Defines DMA "Out of Bounds" region \#3. If a DMA initiated write transaction generates an address 4849215976Sjmallett * within the specified region, the write is 'ignored' and an interrupt is generated to alert software. 4850215976Sjmallett */ 4851232812Sjmallettunion cvmx_l2c_oob3 { 4852215976Sjmallett uint64_t u64; 4853232812Sjmallett struct cvmx_l2c_oob3_s { 4854232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4855215976Sjmallett uint64_t fadr : 27; /**< DMA initated Memory Range Checker Failing Address 4856215976Sjmallett When L2C_INT_STAT[OOB3]=1, this field indicates the 4857215976Sjmallett DMA cacheline address. 4858215976Sjmallett (addr[33:7] = full cacheline address captured) 4859215976Sjmallett NOTE: FADR is locked down until L2C_INT_STAT[00B3] 4860215976Sjmallett is cleared. */ 4861215976Sjmallett uint64_t fsrc : 1; /**< DMA Out of Bounds Failing Source Command 4862215976Sjmallett When L2C_INT_STAT[OOB3]=1, this field indicates the 4863215976Sjmallett type of DMA command. 4864215976Sjmallett - 0: ST* (STF/P/T) 4865215976Sjmallett - 1: DWB (Don't WriteBack) 4866215976Sjmallett NOTE: FSRC is locked down until L2C_INT_STAT[00B3] 4867215976Sjmallett is cleared. */ 4868215976Sjmallett uint64_t reserved_34_35 : 2; 4869215976Sjmallett uint64_t sadr : 14; /**< DMA initated Memory Range Checker Starting Address 4870215976Sjmallett (1MB granularity) */ 4871215976Sjmallett uint64_t reserved_14_19 : 6; 4872215976Sjmallett uint64_t size : 14; /**< DMA Out of Bounds Range Checker Size 4873215976Sjmallett (1MB granularity) 4874215976Sjmallett Example: 0: 0MB / 1: 1MB 4875215976Sjmallett The range check is for: 4876215976Sjmallett (SADR<<20) <= addr[33:0] < (((SADR+SIZE) & 0x3FFF)<<20) 4877215976Sjmallett SW NOTE: SADR+SIZE could be setup to potentially wrap 4878215976Sjmallett the 34bit ending bounds address. */ 4879215976Sjmallett#else 4880215976Sjmallett uint64_t size : 14; 4881215976Sjmallett uint64_t reserved_14_19 : 6; 4882215976Sjmallett uint64_t sadr : 14; 4883215976Sjmallett uint64_t reserved_34_35 : 2; 4884215976Sjmallett uint64_t fsrc : 1; 4885215976Sjmallett uint64_t fadr : 27; 4886215976Sjmallett#endif 4887215976Sjmallett } s; 4888215976Sjmallett struct cvmx_l2c_oob3_s cn52xx; 4889215976Sjmallett struct cvmx_l2c_oob3_s cn52xxp1; 4890215976Sjmallett struct cvmx_l2c_oob3_s cn56xx; 4891215976Sjmallett struct cvmx_l2c_oob3_s cn56xxp1; 4892215976Sjmallett}; 4893215976Sjmalletttypedef union cvmx_l2c_oob3 cvmx_l2c_oob3_t; 4894215976Sjmallett 4895215976Sjmallett/** 4896215976Sjmallett * cvmx_l2c_pfc# 4897215976Sjmallett * 4898215976Sjmallett * L2C_PFC0 = L2 Performance Counter \#0 4899215976Sjmallett * 4900215976Sjmallett * Description: 4901215976Sjmallett */ 4902232812Sjmallettunion cvmx_l2c_pfcx { 4903215976Sjmallett uint64_t u64; 4904232812Sjmallett struct cvmx_l2c_pfcx_s { 4905232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4906215976Sjmallett uint64_t reserved_36_63 : 28; 4907215976Sjmallett uint64_t pfcnt0 : 36; /**< Performance Counter \#0 */ 4908215976Sjmallett#else 4909215976Sjmallett uint64_t pfcnt0 : 36; 4910215976Sjmallett uint64_t reserved_36_63 : 28; 4911215976Sjmallett#endif 4912215976Sjmallett } s; 4913215976Sjmallett struct cvmx_l2c_pfcx_s cn30xx; 4914215976Sjmallett struct cvmx_l2c_pfcx_s cn31xx; 4915215976Sjmallett struct cvmx_l2c_pfcx_s cn38xx; 4916215976Sjmallett struct cvmx_l2c_pfcx_s cn38xxp2; 4917215976Sjmallett struct cvmx_l2c_pfcx_s cn50xx; 4918215976Sjmallett struct cvmx_l2c_pfcx_s cn52xx; 4919215976Sjmallett struct cvmx_l2c_pfcx_s cn52xxp1; 4920215976Sjmallett struct cvmx_l2c_pfcx_s cn56xx; 4921215976Sjmallett struct cvmx_l2c_pfcx_s cn56xxp1; 4922215976Sjmallett struct cvmx_l2c_pfcx_s cn58xx; 4923215976Sjmallett struct cvmx_l2c_pfcx_s cn58xxp1; 4924215976Sjmallett}; 4925215976Sjmalletttypedef union cvmx_l2c_pfcx cvmx_l2c_pfcx_t; 4926215976Sjmallett 4927215976Sjmallett/** 4928215976Sjmallett * cvmx_l2c_pfctl 4929215976Sjmallett * 4930215976Sjmallett * L2C_PFCTL = L2 Performance Counter Control Register 4931215976Sjmallett * 4932215976Sjmallett * Description: Controls the actions of the 4 Performance Counters 4933215976Sjmallett * 4934215976Sjmallett * Notes: 4935215976Sjmallett * - There are four 36b performance counter registers which can simultaneously count events. 4936215976Sjmallett * Each Counter's event is programmably selected via the corresponding CNTxSEL field: 4937215976Sjmallett * CNTxSEL[5:0] Event 4938215976Sjmallett * -----------------+----------------------- 4939215976Sjmallett * 0 | Cycles 4940215976Sjmallett * 1 | L2 LDI Command Miss (NOTE: Both PP and IOB are cabable of generating LDI) 4941215976Sjmallett * 2 | L2 LDI Command Hit (NOTE: Both PP and IOB are cabable of generating LDI) 4942215976Sjmallett * 3 | L2 non-LDI Command Miss 4943215976Sjmallett * 4 | L2 non-LDI Command Hit 4944215976Sjmallett * 5 | L2 Miss (total) 4945215976Sjmallett * 6 | L2 Hit (total) 4946215976Sjmallett * 7 | L2 Victim Buffer Hit (Retry Probe) 4947215976Sjmallett * 8 | LFB-NQ Index Conflict 4948215976Sjmallett * 9 | L2 Tag Probe (issued - could be VB-Retried) 4949215976Sjmallett * 10 | L2 Tag Update (completed - note: some CMD types do not update) 4950215976Sjmallett * 11 | L2 Tag Probe Completed (beyond VB-RTY window) 4951215976Sjmallett * 12 | L2 Tag Dirty Victim 4952215976Sjmallett * 13 | L2 Data Store NOP 4953215976Sjmallett * 14 | L2 Data Store READ 4954215976Sjmallett * 15 | L2 Data Store WRITE 4955215976Sjmallett * 16 | Memory Fill Data valid (1 strobe/32B) 4956215976Sjmallett * 17 | Memory Write Request 4957215976Sjmallett * 18 | Memory Read Request 4958215976Sjmallett * 19 | Memory Write Data valid (1 strobe/32B) 4959215976Sjmallett * 20 | XMC NOP (XMC Bus Idle) 4960215976Sjmallett * 21 | XMC LDT (Load-Through Request) 4961215976Sjmallett * 22 | XMC LDI (L2 Load I-Stream Request) 4962215976Sjmallett * 23 | XMC LDD (L2 Load D-stream Request) 4963215976Sjmallett * 24 | XMC STF (L2 Store Full cacheline Request) 4964215976Sjmallett * 25 | XMC STT (L2 Store Through Request) 4965215976Sjmallett * 26 | XMC STP (L2 Store Partial Request) 4966215976Sjmallett * 27 | XMC STC (L2 Store Conditional Request) 4967215976Sjmallett * 28 | XMC DWB (L2 Don't WriteBack Request) 4968215976Sjmallett * 29 | XMC PL2 (L2 Prefetch Request) 4969215976Sjmallett * 30 | XMC PSL1 (L1 Prefetch Request) 4970215976Sjmallett * 31 | XMC IOBLD 4971215976Sjmallett * 32 | XMC IOBST 4972215976Sjmallett * 33 | XMC IOBDMA 4973215976Sjmallett * 34 | XMC IOBRSP 4974215976Sjmallett * 35 | XMD Bus valid (all) 4975215976Sjmallett * 36 | XMD Bus valid (DST=L2C) Memory Data 4976215976Sjmallett * 37 | XMD Bus valid (DST=IOB) REFL Data 4977215976Sjmallett * 38 | XMD Bus valid (DST=PP) IOBRSP Data 4978215976Sjmallett * 39 | RSC NOP 4979215976Sjmallett * 40 | RSC STDN 4980215976Sjmallett * 41 | RSC FILL 4981215976Sjmallett * 42 | RSC REFL 4982215976Sjmallett * 43 | RSC STIN 4983215976Sjmallett * 44 | RSC SCIN 4984215976Sjmallett * 45 | RSC SCFL 4985215976Sjmallett * 46 | RSC SCDN 4986215976Sjmallett * 47 | RSD Data Valid 4987215976Sjmallett * 48 | RSD Data Valid (FILL) 4988215976Sjmallett * 49 | RSD Data Valid (STRSP) 4989215976Sjmallett * 50 | RSD Data Valid (REFL) 4990215976Sjmallett * 51 | LRF-REQ (LFB-NQ) 4991215976Sjmallett * 52 | DT RD-ALLOC (LDD/PSL1 Commands) 4992215976Sjmallett * 53 | DT WR-INVAL (ST* Commands) 4993215976Sjmallett */ 4994232812Sjmallettunion cvmx_l2c_pfctl { 4995215976Sjmallett uint64_t u64; 4996232812Sjmallett struct cvmx_l2c_pfctl_s { 4997232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4998215976Sjmallett uint64_t reserved_36_63 : 28; 4999215976Sjmallett uint64_t cnt3rdclr : 1; /**< Performance Counter 3 Read Clear 5000215976Sjmallett When set, all CSR reads of the L2C_PFC3 5001215976Sjmallett register will auto-clear the counter. This allows 5002215976Sjmallett SW to maintain 'cumulative' counters in SW. 5003215976Sjmallett NOTE: If the CSR read occurs in the same cycle as 5004215976Sjmallett the 'event' to be counted, the counter will 5005215976Sjmallett properly reflect the event. */ 5006215976Sjmallett uint64_t cnt2rdclr : 1; /**< Performance Counter 2 Read Clear 5007215976Sjmallett When set, all CSR reads of the L2C_PFC2 5008215976Sjmallett register will auto-clear the counter. This allows 5009215976Sjmallett SW to maintain 'cumulative' counters in SW. 5010215976Sjmallett NOTE: If the CSR read occurs in the same cycle as 5011215976Sjmallett the 'event' to be counted, the counter will 5012215976Sjmallett properly reflect the event. */ 5013215976Sjmallett uint64_t cnt1rdclr : 1; /**< Performance Counter 1 Read Clear 5014215976Sjmallett When set, all CSR reads of the L2C_PFC1 5015215976Sjmallett register will auto-clear the counter. This allows 5016215976Sjmallett SW to maintain 'cumulative' counters in SW. 5017215976Sjmallett NOTE: If the CSR read occurs in the same cycle as 5018215976Sjmallett the 'event' to be counted, the counter will 5019215976Sjmallett properly reflect the event. */ 5020215976Sjmallett uint64_t cnt0rdclr : 1; /**< Performance Counter 0 Read Clear 5021215976Sjmallett When set, all CSR reads of the L2C_PFC0 5022215976Sjmallett register will 'auto-clear' the counter. This allows 5023215976Sjmallett SW to maintain accurate 'cumulative' counters. 5024215976Sjmallett NOTE: If the CSR read occurs in the same cycle as 5025215976Sjmallett the 'event' to be counted, the counter will 5026215976Sjmallett properly reflect the event. */ 5027215976Sjmallett uint64_t cnt3ena : 1; /**< Performance Counter 3 Enable 5028215976Sjmallett When this bit is set, the performance counter 5029215976Sjmallett is enabled. */ 5030215976Sjmallett uint64_t cnt3clr : 1; /**< Performance Counter 3 Clear 5031215976Sjmallett When the CSR write occurs, if this bit is set, 5032215976Sjmallett the performance counter is cleared. Otherwise, 5033215976Sjmallett it will resume counting from its current value. */ 5034215976Sjmallett uint64_t cnt3sel : 6; /**< Performance Counter 3 Event Selector 5035215976Sjmallett (see list of selectable events to count in NOTES) */ 5036215976Sjmallett uint64_t cnt2ena : 1; /**< Performance Counter 2 Enable 5037215976Sjmallett When this bit is set, the performance counter 5038215976Sjmallett is enabled. */ 5039215976Sjmallett uint64_t cnt2clr : 1; /**< Performance Counter 2 Clear 5040215976Sjmallett When the CSR write occurs, if this bit is set, 5041215976Sjmallett the performance counter is cleared. Otherwise, 5042215976Sjmallett it will resume counting from its current value. */ 5043215976Sjmallett uint64_t cnt2sel : 6; /**< Performance Counter 2 Event Selector 5044215976Sjmallett (see list of selectable events to count in NOTES) */ 5045215976Sjmallett uint64_t cnt1ena : 1; /**< Performance Counter 1 Enable 5046215976Sjmallett When this bit is set, the performance counter 5047215976Sjmallett is enabled. */ 5048215976Sjmallett uint64_t cnt1clr : 1; /**< Performance Counter 1 Clear 5049215976Sjmallett When the CSR write occurs, if this bit is set, 5050215976Sjmallett the performance counter is cleared. Otherwise, 5051215976Sjmallett it will resume counting from its current value. */ 5052215976Sjmallett uint64_t cnt1sel : 6; /**< Performance Counter 1 Event Selector 5053215976Sjmallett (see list of selectable events to count in NOTES) */ 5054215976Sjmallett uint64_t cnt0ena : 1; /**< Performance Counter 0 Enable 5055215976Sjmallett When this bit is set, the performance counter 5056215976Sjmallett is enabled. */ 5057215976Sjmallett uint64_t cnt0clr : 1; /**< Performance Counter 0 Clear 5058215976Sjmallett When the CSR write occurs, if this bit is set, 5059215976Sjmallett the performance counter is cleared. Otherwise, 5060215976Sjmallett it will resume counting from its current value. */ 5061215976Sjmallett uint64_t cnt0sel : 6; /**< Performance Counter 0 Event Selector 5062215976Sjmallett (see list of selectable events to count in NOTES) */ 5063215976Sjmallett#else 5064215976Sjmallett uint64_t cnt0sel : 6; 5065215976Sjmallett uint64_t cnt0clr : 1; 5066215976Sjmallett uint64_t cnt0ena : 1; 5067215976Sjmallett uint64_t cnt1sel : 6; 5068215976Sjmallett uint64_t cnt1clr : 1; 5069215976Sjmallett uint64_t cnt1ena : 1; 5070215976Sjmallett uint64_t cnt2sel : 6; 5071215976Sjmallett uint64_t cnt2clr : 1; 5072215976Sjmallett uint64_t cnt2ena : 1; 5073215976Sjmallett uint64_t cnt3sel : 6; 5074215976Sjmallett uint64_t cnt3clr : 1; 5075215976Sjmallett uint64_t cnt3ena : 1; 5076215976Sjmallett uint64_t cnt0rdclr : 1; 5077215976Sjmallett uint64_t cnt1rdclr : 1; 5078215976Sjmallett uint64_t cnt2rdclr : 1; 5079215976Sjmallett uint64_t cnt3rdclr : 1; 5080215976Sjmallett uint64_t reserved_36_63 : 28; 5081215976Sjmallett#endif 5082215976Sjmallett } s; 5083215976Sjmallett struct cvmx_l2c_pfctl_s cn30xx; 5084215976Sjmallett struct cvmx_l2c_pfctl_s cn31xx; 5085215976Sjmallett struct cvmx_l2c_pfctl_s cn38xx; 5086215976Sjmallett struct cvmx_l2c_pfctl_s cn38xxp2; 5087215976Sjmallett struct cvmx_l2c_pfctl_s cn50xx; 5088215976Sjmallett struct cvmx_l2c_pfctl_s cn52xx; 5089215976Sjmallett struct cvmx_l2c_pfctl_s cn52xxp1; 5090215976Sjmallett struct cvmx_l2c_pfctl_s cn56xx; 5091215976Sjmallett struct cvmx_l2c_pfctl_s cn56xxp1; 5092215976Sjmallett struct cvmx_l2c_pfctl_s cn58xx; 5093215976Sjmallett struct cvmx_l2c_pfctl_s cn58xxp1; 5094215976Sjmallett}; 5095215976Sjmalletttypedef union cvmx_l2c_pfctl cvmx_l2c_pfctl_t; 5096215976Sjmallett 5097215976Sjmallett/** 5098215976Sjmallett * cvmx_l2c_ppgrp 5099215976Sjmallett * 5100215976Sjmallett * L2C_PPGRP = L2C PP Group Number 5101215976Sjmallett * 5102215976Sjmallett * Description: Defines the PP(Packet Processor) PLC Group \# (0,1,2) 5103215976Sjmallett */ 5104232812Sjmallettunion cvmx_l2c_ppgrp { 5105215976Sjmallett uint64_t u64; 5106232812Sjmallett struct cvmx_l2c_ppgrp_s { 5107232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5108215976Sjmallett uint64_t reserved_24_63 : 40; 5109215976Sjmallett uint64_t pp11grp : 2; /**< PP11 PLC Group# (0,1,2) */ 5110215976Sjmallett uint64_t pp10grp : 2; /**< PP10 PLC Group# (0,1,2) */ 5111215976Sjmallett uint64_t pp9grp : 2; /**< PP9 PLC Group# (0,1,2) */ 5112215976Sjmallett uint64_t pp8grp : 2; /**< PP8 PLC Group# (0,1,2) */ 5113215976Sjmallett uint64_t pp7grp : 2; /**< PP7 PLC Group# (0,1,2) */ 5114215976Sjmallett uint64_t pp6grp : 2; /**< PP6 PLC Group# (0,1,2) */ 5115215976Sjmallett uint64_t pp5grp : 2; /**< PP5 PLC Group# (0,1,2) */ 5116215976Sjmallett uint64_t pp4grp : 2; /**< PP4 PLC Group# (0,1,2) */ 5117215976Sjmallett uint64_t pp3grp : 2; /**< PP3 PLC Group# (0,1,2) */ 5118215976Sjmallett uint64_t pp2grp : 2; /**< PP2 PLC Group# (0,1,2) */ 5119215976Sjmallett uint64_t pp1grp : 2; /**< PP1 PLC Group# (0,1,2) */ 5120215976Sjmallett uint64_t pp0grp : 2; /**< PP0 PLC Group# (0,1,2) */ 5121215976Sjmallett#else 5122215976Sjmallett uint64_t pp0grp : 2; 5123215976Sjmallett uint64_t pp1grp : 2; 5124215976Sjmallett uint64_t pp2grp : 2; 5125215976Sjmallett uint64_t pp3grp : 2; 5126215976Sjmallett uint64_t pp4grp : 2; 5127215976Sjmallett uint64_t pp5grp : 2; 5128215976Sjmallett uint64_t pp6grp : 2; 5129215976Sjmallett uint64_t pp7grp : 2; 5130215976Sjmallett uint64_t pp8grp : 2; 5131215976Sjmallett uint64_t pp9grp : 2; 5132215976Sjmallett uint64_t pp10grp : 2; 5133215976Sjmallett uint64_t pp11grp : 2; 5134215976Sjmallett uint64_t reserved_24_63 : 40; 5135215976Sjmallett#endif 5136215976Sjmallett } s; 5137232812Sjmallett struct cvmx_l2c_ppgrp_cn52xx { 5138232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5139215976Sjmallett uint64_t reserved_8_63 : 56; 5140215976Sjmallett uint64_t pp3grp : 2; /**< PP3 PLC Group# (0,1,2) */ 5141215976Sjmallett uint64_t pp2grp : 2; /**< PP2 PLC Group# (0,1,2) */ 5142215976Sjmallett uint64_t pp1grp : 2; /**< PP1 PLC Group# (0,1,2) */ 5143215976Sjmallett uint64_t pp0grp : 2; /**< PP0 PLC Group# (0,1,2) */ 5144215976Sjmallett#else 5145215976Sjmallett uint64_t pp0grp : 2; 5146215976Sjmallett uint64_t pp1grp : 2; 5147215976Sjmallett uint64_t pp2grp : 2; 5148215976Sjmallett uint64_t pp3grp : 2; 5149215976Sjmallett uint64_t reserved_8_63 : 56; 5150215976Sjmallett#endif 5151215976Sjmallett } cn52xx; 5152215976Sjmallett struct cvmx_l2c_ppgrp_cn52xx cn52xxp1; 5153215976Sjmallett struct cvmx_l2c_ppgrp_s cn56xx; 5154215976Sjmallett struct cvmx_l2c_ppgrp_s cn56xxp1; 5155215976Sjmallett}; 5156215976Sjmalletttypedef union cvmx_l2c_ppgrp cvmx_l2c_ppgrp_t; 5157215976Sjmallett 5158215976Sjmallett/** 5159215976Sjmallett * cvmx_l2c_qos_iob# 5160215976Sjmallett * 5161215976Sjmallett * L2C_QOS_IOB = L2C IOB QOS level 5162215976Sjmallett * 5163215976Sjmallett * Description: 5164215976Sjmallett */ 5165232812Sjmallettunion cvmx_l2c_qos_iobx { 5166215976Sjmallett uint64_t u64; 5167232812Sjmallett struct cvmx_l2c_qos_iobx_s { 5168232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5169232812Sjmallett uint64_t reserved_7_63 : 57; 5170232812Sjmallett uint64_t dwblvl : 3; /**< QOS level for DWB commands. */ 5171232812Sjmallett uint64_t reserved_3_3 : 1; 5172232812Sjmallett uint64_t lvl : 3; /**< QOS level for non-DWB commands. */ 5173232812Sjmallett#else 5174232812Sjmallett uint64_t lvl : 3; 5175232812Sjmallett uint64_t reserved_3_3 : 1; 5176232812Sjmallett uint64_t dwblvl : 3; 5177232812Sjmallett uint64_t reserved_7_63 : 57; 5178232812Sjmallett#endif 5179232812Sjmallett } s; 5180232812Sjmallett struct cvmx_l2c_qos_iobx_cn61xx { 5181232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5182215976Sjmallett uint64_t reserved_6_63 : 58; 5183215976Sjmallett uint64_t dwblvl : 2; /**< QOS level for DWB commands. */ 5184215976Sjmallett uint64_t reserved_2_3 : 2; 5185215976Sjmallett uint64_t lvl : 2; /**< QOS level for non-DWB commands. */ 5186215976Sjmallett#else 5187215976Sjmallett uint64_t lvl : 2; 5188215976Sjmallett uint64_t reserved_2_3 : 2; 5189215976Sjmallett uint64_t dwblvl : 2; 5190215976Sjmallett uint64_t reserved_6_63 : 58; 5191215976Sjmallett#endif 5192232812Sjmallett } cn61xx; 5193232812Sjmallett struct cvmx_l2c_qos_iobx_cn61xx cn63xx; 5194232812Sjmallett struct cvmx_l2c_qos_iobx_cn61xx cn63xxp1; 5195232812Sjmallett struct cvmx_l2c_qos_iobx_cn61xx cn66xx; 5196232812Sjmallett struct cvmx_l2c_qos_iobx_s cn68xx; 5197232812Sjmallett struct cvmx_l2c_qos_iobx_s cn68xxp1; 5198232812Sjmallett struct cvmx_l2c_qos_iobx_cn61xx cnf71xx; 5199215976Sjmallett}; 5200215976Sjmalletttypedef union cvmx_l2c_qos_iobx cvmx_l2c_qos_iobx_t; 5201215976Sjmallett 5202215976Sjmallett/** 5203215976Sjmallett * cvmx_l2c_qos_pp# 5204215976Sjmallett * 5205215976Sjmallett * L2C_QOS_PP = L2C PP QOS level 5206215976Sjmallett * 5207215976Sjmallett * Description: 5208215976Sjmallett */ 5209232812Sjmallettunion cvmx_l2c_qos_ppx { 5210215976Sjmallett uint64_t u64; 5211232812Sjmallett struct cvmx_l2c_qos_ppx_s { 5212232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5213232812Sjmallett uint64_t reserved_3_63 : 61; 5214232812Sjmallett uint64_t lvl : 3; /**< QOS level to use for this PP. */ 5215232812Sjmallett#else 5216232812Sjmallett uint64_t lvl : 3; 5217232812Sjmallett uint64_t reserved_3_63 : 61; 5218232812Sjmallett#endif 5219232812Sjmallett } s; 5220232812Sjmallett struct cvmx_l2c_qos_ppx_cn61xx { 5221232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5222215976Sjmallett uint64_t reserved_2_63 : 62; 5223215976Sjmallett uint64_t lvl : 2; /**< QOS level to use for this PP. */ 5224215976Sjmallett#else 5225215976Sjmallett uint64_t lvl : 2; 5226215976Sjmallett uint64_t reserved_2_63 : 62; 5227215976Sjmallett#endif 5228232812Sjmallett } cn61xx; 5229232812Sjmallett struct cvmx_l2c_qos_ppx_cn61xx cn63xx; 5230232812Sjmallett struct cvmx_l2c_qos_ppx_cn61xx cn63xxp1; 5231232812Sjmallett struct cvmx_l2c_qos_ppx_cn61xx cn66xx; 5232232812Sjmallett struct cvmx_l2c_qos_ppx_s cn68xx; 5233232812Sjmallett struct cvmx_l2c_qos_ppx_s cn68xxp1; 5234232812Sjmallett struct cvmx_l2c_qos_ppx_cn61xx cnf71xx; 5235215976Sjmallett}; 5236215976Sjmalletttypedef union cvmx_l2c_qos_ppx cvmx_l2c_qos_ppx_t; 5237215976Sjmallett 5238215976Sjmallett/** 5239215976Sjmallett * cvmx_l2c_qos_wgt 5240215976Sjmallett * 5241215976Sjmallett * L2C_QOS_WGT = L2C QOS weights 5242215976Sjmallett * 5243215976Sjmallett */ 5244232812Sjmallettunion cvmx_l2c_qos_wgt { 5245215976Sjmallett uint64_t u64; 5246232812Sjmallett struct cvmx_l2c_qos_wgt_s { 5247232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5248232812Sjmallett uint64_t wgt7 : 8; /**< Weight for QOS level 7 */ 5249232812Sjmallett uint64_t wgt6 : 8; /**< Weight for QOS level 6 */ 5250232812Sjmallett uint64_t wgt5 : 8; /**< Weight for QOS level 5 */ 5251232812Sjmallett uint64_t wgt4 : 8; /**< Weight for QOS level 4 */ 5252232812Sjmallett uint64_t wgt3 : 8; /**< Weight for QOS level 3 */ 5253232812Sjmallett uint64_t wgt2 : 8; /**< Weight for QOS level 2 */ 5254232812Sjmallett uint64_t wgt1 : 8; /**< Weight for QOS level 1 */ 5255232812Sjmallett uint64_t wgt0 : 8; /**< Weight for QOS level 0 */ 5256232812Sjmallett#else 5257232812Sjmallett uint64_t wgt0 : 8; 5258232812Sjmallett uint64_t wgt1 : 8; 5259232812Sjmallett uint64_t wgt2 : 8; 5260232812Sjmallett uint64_t wgt3 : 8; 5261232812Sjmallett uint64_t wgt4 : 8; 5262232812Sjmallett uint64_t wgt5 : 8; 5263232812Sjmallett uint64_t wgt6 : 8; 5264232812Sjmallett uint64_t wgt7 : 8; 5265232812Sjmallett#endif 5266232812Sjmallett } s; 5267232812Sjmallett struct cvmx_l2c_qos_wgt_cn61xx { 5268232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5269215976Sjmallett uint64_t reserved_32_63 : 32; 5270215976Sjmallett uint64_t wgt3 : 8; /**< Weight for QOS level 3 */ 5271215976Sjmallett uint64_t wgt2 : 8; /**< Weight for QOS level 2 */ 5272215976Sjmallett uint64_t wgt1 : 8; /**< Weight for QOS level 1 */ 5273215976Sjmallett uint64_t wgt0 : 8; /**< Weight for QOS level 0 */ 5274215976Sjmallett#else 5275215976Sjmallett uint64_t wgt0 : 8; 5276215976Sjmallett uint64_t wgt1 : 8; 5277215976Sjmallett uint64_t wgt2 : 8; 5278215976Sjmallett uint64_t wgt3 : 8; 5279215976Sjmallett uint64_t reserved_32_63 : 32; 5280215976Sjmallett#endif 5281232812Sjmallett } cn61xx; 5282232812Sjmallett struct cvmx_l2c_qos_wgt_cn61xx cn63xx; 5283232812Sjmallett struct cvmx_l2c_qos_wgt_cn61xx cn63xxp1; 5284232812Sjmallett struct cvmx_l2c_qos_wgt_cn61xx cn66xx; 5285232812Sjmallett struct cvmx_l2c_qos_wgt_s cn68xx; 5286232812Sjmallett struct cvmx_l2c_qos_wgt_s cn68xxp1; 5287232812Sjmallett struct cvmx_l2c_qos_wgt_cn61xx cnf71xx; 5288215976Sjmallett}; 5289215976Sjmalletttypedef union cvmx_l2c_qos_wgt cvmx_l2c_qos_wgt_t; 5290215976Sjmallett 5291215976Sjmallett/** 5292215976Sjmallett * cvmx_l2c_rsc#_pfc 5293215976Sjmallett * 5294215976Sjmallett * L2C_RSC_PFC = L2C RSC Performance Counter(s) 5295215976Sjmallett * 5296215976Sjmallett */ 5297232812Sjmallettunion cvmx_l2c_rscx_pfc { 5298215976Sjmallett uint64_t u64; 5299232812Sjmallett struct cvmx_l2c_rscx_pfc_s { 5300232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5301215976Sjmallett uint64_t count : 64; /**< Current counter value */ 5302215976Sjmallett#else 5303215976Sjmallett uint64_t count : 64; 5304215976Sjmallett#endif 5305215976Sjmallett } s; 5306232812Sjmallett struct cvmx_l2c_rscx_pfc_s cn61xx; 5307215976Sjmallett struct cvmx_l2c_rscx_pfc_s cn63xx; 5308215976Sjmallett struct cvmx_l2c_rscx_pfc_s cn63xxp1; 5309232812Sjmallett struct cvmx_l2c_rscx_pfc_s cn66xx; 5310232812Sjmallett struct cvmx_l2c_rscx_pfc_s cn68xx; 5311232812Sjmallett struct cvmx_l2c_rscx_pfc_s cn68xxp1; 5312232812Sjmallett struct cvmx_l2c_rscx_pfc_s cnf71xx; 5313215976Sjmallett}; 5314215976Sjmalletttypedef union cvmx_l2c_rscx_pfc cvmx_l2c_rscx_pfc_t; 5315215976Sjmallett 5316215976Sjmallett/** 5317215976Sjmallett * cvmx_l2c_rsd#_pfc 5318215976Sjmallett * 5319215976Sjmallett * L2C_RSD_PFC = L2C RSD Performance Counter(s) 5320215976Sjmallett * 5321215976Sjmallett */ 5322232812Sjmallettunion cvmx_l2c_rsdx_pfc { 5323215976Sjmallett uint64_t u64; 5324232812Sjmallett struct cvmx_l2c_rsdx_pfc_s { 5325232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5326215976Sjmallett uint64_t count : 64; /**< Current counter value */ 5327215976Sjmallett#else 5328215976Sjmallett uint64_t count : 64; 5329215976Sjmallett#endif 5330215976Sjmallett } s; 5331232812Sjmallett struct cvmx_l2c_rsdx_pfc_s cn61xx; 5332215976Sjmallett struct cvmx_l2c_rsdx_pfc_s cn63xx; 5333215976Sjmallett struct cvmx_l2c_rsdx_pfc_s cn63xxp1; 5334232812Sjmallett struct cvmx_l2c_rsdx_pfc_s cn66xx; 5335232812Sjmallett struct cvmx_l2c_rsdx_pfc_s cn68xx; 5336232812Sjmallett struct cvmx_l2c_rsdx_pfc_s cn68xxp1; 5337232812Sjmallett struct cvmx_l2c_rsdx_pfc_s cnf71xx; 5338215976Sjmallett}; 5339215976Sjmalletttypedef union cvmx_l2c_rsdx_pfc cvmx_l2c_rsdx_pfc_t; 5340215976Sjmallett 5341215976Sjmallett/** 5342215976Sjmallett * cvmx_l2c_spar0 5343215976Sjmallett * 5344215976Sjmallett * L2C_SPAR0 = L2 Set Partitioning Register (PP0-3) 5345215976Sjmallett * 5346215976Sjmallett * Description: L2 Set Partitioning Register 5347215976Sjmallett * 5348215976Sjmallett * Notes: 5349215976Sjmallett * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that 5350215976Sjmallett * set for replacement. 5351215976Sjmallett * - There MUST ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation 5352215976Sjmallett * - NOTES: When L2C FUSE[136] is blown(CRIP_256K), then SETS#7-4 are SET in all UMSK'x' registers 5353215976Sjmallett * When L2C FUSE[137] is blown(CRIP_128K), then SETS#7-2 are SET in all UMSK'x' registers 5354215976Sjmallett */ 5355232812Sjmallettunion cvmx_l2c_spar0 { 5356215976Sjmallett uint64_t u64; 5357232812Sjmallett struct cvmx_l2c_spar0_s { 5358232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5359215976Sjmallett uint64_t reserved_32_63 : 32; 5360215976Sjmallett uint64_t umsk3 : 8; /**< PP[3] L2 'DO NOT USE' set partition mask */ 5361215976Sjmallett uint64_t umsk2 : 8; /**< PP[2] L2 'DO NOT USE' set partition mask */ 5362215976Sjmallett uint64_t umsk1 : 8; /**< PP[1] L2 'DO NOT USE' set partition mask */ 5363215976Sjmallett uint64_t umsk0 : 8; /**< PP[0] L2 'DO NOT USE' set partition mask */ 5364215976Sjmallett#else 5365215976Sjmallett uint64_t umsk0 : 8; 5366215976Sjmallett uint64_t umsk1 : 8; 5367215976Sjmallett uint64_t umsk2 : 8; 5368215976Sjmallett uint64_t umsk3 : 8; 5369215976Sjmallett uint64_t reserved_32_63 : 32; 5370215976Sjmallett#endif 5371215976Sjmallett } s; 5372232812Sjmallett struct cvmx_l2c_spar0_cn30xx { 5373232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5374215976Sjmallett uint64_t reserved_4_63 : 60; 5375215976Sjmallett uint64_t umsk0 : 4; /**< PP[0] L2 'DO NOT USE' set partition mask */ 5376215976Sjmallett#else 5377215976Sjmallett uint64_t umsk0 : 4; 5378215976Sjmallett uint64_t reserved_4_63 : 60; 5379215976Sjmallett#endif 5380215976Sjmallett } cn30xx; 5381232812Sjmallett struct cvmx_l2c_spar0_cn31xx { 5382232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5383215976Sjmallett uint64_t reserved_12_63 : 52; 5384215976Sjmallett uint64_t umsk1 : 4; /**< PP[1] L2 'DO NOT USE' set partition mask */ 5385215976Sjmallett uint64_t reserved_4_7 : 4; 5386215976Sjmallett uint64_t umsk0 : 4; /**< PP[0] L2 'DO NOT USE' set partition mask */ 5387215976Sjmallett#else 5388215976Sjmallett uint64_t umsk0 : 4; 5389215976Sjmallett uint64_t reserved_4_7 : 4; 5390215976Sjmallett uint64_t umsk1 : 4; 5391215976Sjmallett uint64_t reserved_12_63 : 52; 5392215976Sjmallett#endif 5393215976Sjmallett } cn31xx; 5394215976Sjmallett struct cvmx_l2c_spar0_s cn38xx; 5395215976Sjmallett struct cvmx_l2c_spar0_s cn38xxp2; 5396232812Sjmallett struct cvmx_l2c_spar0_cn50xx { 5397232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5398215976Sjmallett uint64_t reserved_16_63 : 48; 5399215976Sjmallett uint64_t umsk1 : 8; /**< PP[1] L2 'DO NOT USE' set partition mask */ 5400215976Sjmallett uint64_t umsk0 : 8; /**< PP[0] L2 'DO NOT USE' set partition mask */ 5401215976Sjmallett#else 5402215976Sjmallett uint64_t umsk0 : 8; 5403215976Sjmallett uint64_t umsk1 : 8; 5404215976Sjmallett uint64_t reserved_16_63 : 48; 5405215976Sjmallett#endif 5406215976Sjmallett } cn50xx; 5407215976Sjmallett struct cvmx_l2c_spar0_s cn52xx; 5408215976Sjmallett struct cvmx_l2c_spar0_s cn52xxp1; 5409215976Sjmallett struct cvmx_l2c_spar0_s cn56xx; 5410215976Sjmallett struct cvmx_l2c_spar0_s cn56xxp1; 5411215976Sjmallett struct cvmx_l2c_spar0_s cn58xx; 5412215976Sjmallett struct cvmx_l2c_spar0_s cn58xxp1; 5413215976Sjmallett}; 5414215976Sjmalletttypedef union cvmx_l2c_spar0 cvmx_l2c_spar0_t; 5415215976Sjmallett 5416215976Sjmallett/** 5417215976Sjmallett * cvmx_l2c_spar1 5418215976Sjmallett * 5419215976Sjmallett * L2C_SPAR1 = L2 Set Partitioning Register (PP4-7) 5420215976Sjmallett * 5421215976Sjmallett * Description: L2 Set Partitioning Register 5422215976Sjmallett * 5423215976Sjmallett * Notes: 5424215976Sjmallett * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that 5425215976Sjmallett * set for replacement. 5426215976Sjmallett * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation 5427215976Sjmallett * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers 5428215976Sjmallett * When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers 5429215976Sjmallett */ 5430232812Sjmallettunion cvmx_l2c_spar1 { 5431215976Sjmallett uint64_t u64; 5432232812Sjmallett struct cvmx_l2c_spar1_s { 5433232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5434215976Sjmallett uint64_t reserved_32_63 : 32; 5435215976Sjmallett uint64_t umsk7 : 8; /**< PP[7] L2 'DO NOT USE' set partition mask */ 5436215976Sjmallett uint64_t umsk6 : 8; /**< PP[6] L2 'DO NOT USE' set partition mask */ 5437215976Sjmallett uint64_t umsk5 : 8; /**< PP[5] L2 'DO NOT USE' set partition mask */ 5438215976Sjmallett uint64_t umsk4 : 8; /**< PP[4] L2 'DO NOT USE' set partition mask */ 5439215976Sjmallett#else 5440215976Sjmallett uint64_t umsk4 : 8; 5441215976Sjmallett uint64_t umsk5 : 8; 5442215976Sjmallett uint64_t umsk6 : 8; 5443215976Sjmallett uint64_t umsk7 : 8; 5444215976Sjmallett uint64_t reserved_32_63 : 32; 5445215976Sjmallett#endif 5446215976Sjmallett } s; 5447215976Sjmallett struct cvmx_l2c_spar1_s cn38xx; 5448215976Sjmallett struct cvmx_l2c_spar1_s cn38xxp2; 5449215976Sjmallett struct cvmx_l2c_spar1_s cn56xx; 5450215976Sjmallett struct cvmx_l2c_spar1_s cn56xxp1; 5451215976Sjmallett struct cvmx_l2c_spar1_s cn58xx; 5452215976Sjmallett struct cvmx_l2c_spar1_s cn58xxp1; 5453215976Sjmallett}; 5454215976Sjmalletttypedef union cvmx_l2c_spar1 cvmx_l2c_spar1_t; 5455215976Sjmallett 5456215976Sjmallett/** 5457215976Sjmallett * cvmx_l2c_spar2 5458215976Sjmallett * 5459215976Sjmallett * L2C_SPAR2 = L2 Set Partitioning Register (PP8-11) 5460215976Sjmallett * 5461215976Sjmallett * Description: L2 Set Partitioning Register 5462215976Sjmallett * 5463215976Sjmallett * Notes: 5464215976Sjmallett * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that 5465215976Sjmallett * set for replacement. 5466215976Sjmallett * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation 5467215976Sjmallett * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers 5468215976Sjmallett * When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers 5469215976Sjmallett */ 5470232812Sjmallettunion cvmx_l2c_spar2 { 5471215976Sjmallett uint64_t u64; 5472232812Sjmallett struct cvmx_l2c_spar2_s { 5473232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5474215976Sjmallett uint64_t reserved_32_63 : 32; 5475215976Sjmallett uint64_t umsk11 : 8; /**< PP[11] L2 'DO NOT USE' set partition mask */ 5476215976Sjmallett uint64_t umsk10 : 8; /**< PP[10] L2 'DO NOT USE' set partition mask */ 5477215976Sjmallett uint64_t umsk9 : 8; /**< PP[9] L2 'DO NOT USE' set partition mask */ 5478215976Sjmallett uint64_t umsk8 : 8; /**< PP[8] L2 'DO NOT USE' set partition mask */ 5479215976Sjmallett#else 5480215976Sjmallett uint64_t umsk8 : 8; 5481215976Sjmallett uint64_t umsk9 : 8; 5482215976Sjmallett uint64_t umsk10 : 8; 5483215976Sjmallett uint64_t umsk11 : 8; 5484215976Sjmallett uint64_t reserved_32_63 : 32; 5485215976Sjmallett#endif 5486215976Sjmallett } s; 5487215976Sjmallett struct cvmx_l2c_spar2_s cn38xx; 5488215976Sjmallett struct cvmx_l2c_spar2_s cn38xxp2; 5489215976Sjmallett struct cvmx_l2c_spar2_s cn56xx; 5490215976Sjmallett struct cvmx_l2c_spar2_s cn56xxp1; 5491215976Sjmallett struct cvmx_l2c_spar2_s cn58xx; 5492215976Sjmallett struct cvmx_l2c_spar2_s cn58xxp1; 5493215976Sjmallett}; 5494215976Sjmalletttypedef union cvmx_l2c_spar2 cvmx_l2c_spar2_t; 5495215976Sjmallett 5496215976Sjmallett/** 5497215976Sjmallett * cvmx_l2c_spar3 5498215976Sjmallett * 5499215976Sjmallett * L2C_SPAR3 = L2 Set Partitioning Register (PP12-15) 5500215976Sjmallett * 5501215976Sjmallett * Description: L2 Set Partitioning Register 5502215976Sjmallett * 5503215976Sjmallett * Notes: 5504215976Sjmallett * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that 5505215976Sjmallett * set for replacement. 5506215976Sjmallett * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation 5507215976Sjmallett * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers 5508215976Sjmallett * When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers 5509215976Sjmallett */ 5510232812Sjmallettunion cvmx_l2c_spar3 { 5511215976Sjmallett uint64_t u64; 5512232812Sjmallett struct cvmx_l2c_spar3_s { 5513232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5514215976Sjmallett uint64_t reserved_32_63 : 32; 5515215976Sjmallett uint64_t umsk15 : 8; /**< PP[15] L2 'DO NOT USE' set partition mask */ 5516215976Sjmallett uint64_t umsk14 : 8; /**< PP[14] L2 'DO NOT USE' set partition mask */ 5517215976Sjmallett uint64_t umsk13 : 8; /**< PP[13] L2 'DO NOT USE' set partition mask */ 5518215976Sjmallett uint64_t umsk12 : 8; /**< PP[12] L2 'DO NOT USE' set partition mask */ 5519215976Sjmallett#else 5520215976Sjmallett uint64_t umsk12 : 8; 5521215976Sjmallett uint64_t umsk13 : 8; 5522215976Sjmallett uint64_t umsk14 : 8; 5523215976Sjmallett uint64_t umsk15 : 8; 5524215976Sjmallett uint64_t reserved_32_63 : 32; 5525215976Sjmallett#endif 5526215976Sjmallett } s; 5527215976Sjmallett struct cvmx_l2c_spar3_s cn38xx; 5528215976Sjmallett struct cvmx_l2c_spar3_s cn38xxp2; 5529215976Sjmallett struct cvmx_l2c_spar3_s cn58xx; 5530215976Sjmallett struct cvmx_l2c_spar3_s cn58xxp1; 5531215976Sjmallett}; 5532215976Sjmalletttypedef union cvmx_l2c_spar3 cvmx_l2c_spar3_t; 5533215976Sjmallett 5534215976Sjmallett/** 5535215976Sjmallett * cvmx_l2c_spar4 5536215976Sjmallett * 5537215976Sjmallett * L2C_SPAR4 = L2 Set Partitioning Register (IOB) 5538215976Sjmallett * 5539215976Sjmallett * Description: L2 Set Partitioning Register 5540215976Sjmallett * 5541215976Sjmallett * Notes: 5542215976Sjmallett * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that 5543215976Sjmallett * set for replacement. 5544215976Sjmallett * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation 5545215976Sjmallett * - NOTES: When L2C FUSE[136] is blown(CRIP_256K), then SETS#7-4 are SET in all UMSK'x' registers 5546215976Sjmallett * When L2C FUSE[137] is blown(CRIP_128K), then SETS#7-2 are SET in all UMSK'x' registers 5547215976Sjmallett */ 5548232812Sjmallettunion cvmx_l2c_spar4 { 5549215976Sjmallett uint64_t u64; 5550232812Sjmallett struct cvmx_l2c_spar4_s { 5551232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5552215976Sjmallett uint64_t reserved_8_63 : 56; 5553215976Sjmallett uint64_t umskiob : 8; /**< IOB L2 'DO NOT USE' set partition mask */ 5554215976Sjmallett#else 5555215976Sjmallett uint64_t umskiob : 8; 5556215976Sjmallett uint64_t reserved_8_63 : 56; 5557215976Sjmallett#endif 5558215976Sjmallett } s; 5559232812Sjmallett struct cvmx_l2c_spar4_cn30xx { 5560232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5561215976Sjmallett uint64_t reserved_4_63 : 60; 5562215976Sjmallett uint64_t umskiob : 4; /**< IOB L2 'DO NOT USE' set partition mask */ 5563215976Sjmallett#else 5564215976Sjmallett uint64_t umskiob : 4; 5565215976Sjmallett uint64_t reserved_4_63 : 60; 5566215976Sjmallett#endif 5567215976Sjmallett } cn30xx; 5568215976Sjmallett struct cvmx_l2c_spar4_cn30xx cn31xx; 5569215976Sjmallett struct cvmx_l2c_spar4_s cn38xx; 5570215976Sjmallett struct cvmx_l2c_spar4_s cn38xxp2; 5571215976Sjmallett struct cvmx_l2c_spar4_s cn50xx; 5572215976Sjmallett struct cvmx_l2c_spar4_s cn52xx; 5573215976Sjmallett struct cvmx_l2c_spar4_s cn52xxp1; 5574215976Sjmallett struct cvmx_l2c_spar4_s cn56xx; 5575215976Sjmallett struct cvmx_l2c_spar4_s cn56xxp1; 5576215976Sjmallett struct cvmx_l2c_spar4_s cn58xx; 5577215976Sjmallett struct cvmx_l2c_spar4_s cn58xxp1; 5578215976Sjmallett}; 5579215976Sjmalletttypedef union cvmx_l2c_spar4 cvmx_l2c_spar4_t; 5580215976Sjmallett 5581215976Sjmallett/** 5582215976Sjmallett * cvmx_l2c_tad#_ecc0 5583215976Sjmallett * 5584215976Sjmallett * L2C_TAD_ECC0 = L2C ECC logging 5585215976Sjmallett * 5586215976Sjmallett * Description: holds the syndromes for a L2D read generated from L2C_XMC_CMD 5587215976Sjmallett */ 5588232812Sjmallettunion cvmx_l2c_tadx_ecc0 { 5589215976Sjmallett uint64_t u64; 5590232812Sjmallett struct cvmx_l2c_tadx_ecc0_s { 5591232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5592215976Sjmallett uint64_t reserved_58_63 : 6; 5593215976Sjmallett uint64_t ow3ecc : 10; /**< ECC for OW3 of cache block */ 5594215976Sjmallett uint64_t reserved_42_47 : 6; 5595215976Sjmallett uint64_t ow2ecc : 10; /**< ECC for OW2 of cache block */ 5596215976Sjmallett uint64_t reserved_26_31 : 6; 5597215976Sjmallett uint64_t ow1ecc : 10; /**< ECC for OW1 of cache block */ 5598215976Sjmallett uint64_t reserved_10_15 : 6; 5599215976Sjmallett uint64_t ow0ecc : 10; /**< ECC for OW0 of cache block */ 5600215976Sjmallett#else 5601215976Sjmallett uint64_t ow0ecc : 10; 5602215976Sjmallett uint64_t reserved_10_15 : 6; 5603215976Sjmallett uint64_t ow1ecc : 10; 5604215976Sjmallett uint64_t reserved_26_31 : 6; 5605215976Sjmallett uint64_t ow2ecc : 10; 5606215976Sjmallett uint64_t reserved_42_47 : 6; 5607215976Sjmallett uint64_t ow3ecc : 10; 5608215976Sjmallett uint64_t reserved_58_63 : 6; 5609215976Sjmallett#endif 5610215976Sjmallett } s; 5611232812Sjmallett struct cvmx_l2c_tadx_ecc0_s cn61xx; 5612215976Sjmallett struct cvmx_l2c_tadx_ecc0_s cn63xx; 5613215976Sjmallett struct cvmx_l2c_tadx_ecc0_s cn63xxp1; 5614232812Sjmallett struct cvmx_l2c_tadx_ecc0_s cn66xx; 5615232812Sjmallett struct cvmx_l2c_tadx_ecc0_s cn68xx; 5616232812Sjmallett struct cvmx_l2c_tadx_ecc0_s cn68xxp1; 5617232812Sjmallett struct cvmx_l2c_tadx_ecc0_s cnf71xx; 5618215976Sjmallett}; 5619215976Sjmalletttypedef union cvmx_l2c_tadx_ecc0 cvmx_l2c_tadx_ecc0_t; 5620215976Sjmallett 5621215976Sjmallett/** 5622215976Sjmallett * cvmx_l2c_tad#_ecc1 5623215976Sjmallett * 5624215976Sjmallett * L2C_TAD_ECC1 = L2C ECC logging 5625215976Sjmallett * 5626215976Sjmallett * Description: holds the syndromes for a L2D read generated from L2C_XMC_CMD 5627215976Sjmallett */ 5628232812Sjmallettunion cvmx_l2c_tadx_ecc1 { 5629215976Sjmallett uint64_t u64; 5630232812Sjmallett struct cvmx_l2c_tadx_ecc1_s { 5631232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5632215976Sjmallett uint64_t reserved_58_63 : 6; 5633215976Sjmallett uint64_t ow7ecc : 10; /**< ECC for OW7 of cache block */ 5634215976Sjmallett uint64_t reserved_42_47 : 6; 5635215976Sjmallett uint64_t ow6ecc : 10; /**< ECC for OW6 of cache block */ 5636215976Sjmallett uint64_t reserved_26_31 : 6; 5637215976Sjmallett uint64_t ow5ecc : 10; /**< ECC for OW5 of cache block */ 5638215976Sjmallett uint64_t reserved_10_15 : 6; 5639215976Sjmallett uint64_t ow4ecc : 10; /**< ECC for OW4 of cache block */ 5640215976Sjmallett#else 5641215976Sjmallett uint64_t ow4ecc : 10; 5642215976Sjmallett uint64_t reserved_10_15 : 6; 5643215976Sjmallett uint64_t ow5ecc : 10; 5644215976Sjmallett uint64_t reserved_26_31 : 6; 5645215976Sjmallett uint64_t ow6ecc : 10; 5646215976Sjmallett uint64_t reserved_42_47 : 6; 5647215976Sjmallett uint64_t ow7ecc : 10; 5648215976Sjmallett uint64_t reserved_58_63 : 6; 5649215976Sjmallett#endif 5650215976Sjmallett } s; 5651232812Sjmallett struct cvmx_l2c_tadx_ecc1_s cn61xx; 5652215976Sjmallett struct cvmx_l2c_tadx_ecc1_s cn63xx; 5653215976Sjmallett struct cvmx_l2c_tadx_ecc1_s cn63xxp1; 5654232812Sjmallett struct cvmx_l2c_tadx_ecc1_s cn66xx; 5655232812Sjmallett struct cvmx_l2c_tadx_ecc1_s cn68xx; 5656232812Sjmallett struct cvmx_l2c_tadx_ecc1_s cn68xxp1; 5657232812Sjmallett struct cvmx_l2c_tadx_ecc1_s cnf71xx; 5658215976Sjmallett}; 5659215976Sjmalletttypedef union cvmx_l2c_tadx_ecc1 cvmx_l2c_tadx_ecc1_t; 5660215976Sjmallett 5661215976Sjmallett/** 5662215976Sjmallett * cvmx_l2c_tad#_ien 5663215976Sjmallett * 5664215976Sjmallett * L2C_TAD_IEN = L2C TAD Interrupt Enable 5665215976Sjmallett * 5666215976Sjmallett */ 5667232812Sjmallettunion cvmx_l2c_tadx_ien { 5668215976Sjmallett uint64_t u64; 5669232812Sjmallett struct cvmx_l2c_tadx_ien_s { 5670232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5671215976Sjmallett uint64_t reserved_9_63 : 55; 5672215976Sjmallett uint64_t wrdislmc : 1; /**< Illegal Write to Disabled LMC Error enable 5673215976Sjmallett Enables L2C_TADX_INT[WRDISLMC] to 5674215976Sjmallett assert L2C_INT_REG[TADX] (and cause an interrupt) */ 5675215976Sjmallett uint64_t rddislmc : 1; /**< Illegal Read to Disabled LMC Error enable 5676215976Sjmallett Enables L2C_TADX_INT[RDDISLMC] to 5677215976Sjmallett assert L2C_INT_REG[TADX] (and cause an interrupt) */ 5678215976Sjmallett uint64_t noway : 1; /**< No way available interrupt enable 5679232812Sjmallett Enables L2C_ERR_TTGX[NOWAY]/L2C_TADX_INT[NOWAY] to 5680232812Sjmallett assert L2C_INT_REG[TADX] (and cause an interrupt) */ 5681215976Sjmallett uint64_t vbfdbe : 1; /**< VBF Double-Bit Error enable 5682232812Sjmallett Enables L2C_ERR_TDTX[VDBE]/L2C_TADX_INT[VBFSBE] to 5683232812Sjmallett assert L2C_INT_REG[TADX] (and cause an interrupt) */ 5684215976Sjmallett uint64_t vbfsbe : 1; /**< VBF Single-Bit Error enable 5685232812Sjmallett Enables L2C_ERR_TDTX[VSBE]/L2C_TADX_INT[VBFSBE] to 5686232812Sjmallett assert L2C_INT_REG[TADX] (and cause an interrupt) */ 5687215976Sjmallett uint64_t tagdbe : 1; /**< TAG Double-Bit Error enable 5688232812Sjmallett Enables L2C_ERR_TTGX[DBE]/L2C_TADX_INT[TAGDBE] to 5689232812Sjmallett assert L2C_INT_REG[TADX] (and cause an interrupt) */ 5690215976Sjmallett uint64_t tagsbe : 1; /**< TAG Single-Bit Error enable 5691232812Sjmallett Enables L2C_ERR_TTGX[SBE]/L2C_TADX_INT[TAGSBE] to 5692232812Sjmallett assert L2C_INT_REG[TADX] (and cause an interrupt) */ 5693215976Sjmallett uint64_t l2ddbe : 1; /**< L2D Double-Bit Error enable 5694232812Sjmallett Enables L2C_ERR_TDTX[DBE]/L2C_TADX_INT[L2DDBE] to 5695232812Sjmallett assert L2C_INT_REG[TADX] (and cause an interrupt) */ 5696215976Sjmallett uint64_t l2dsbe : 1; /**< L2D Single-Bit Error enable 5697232812Sjmallett Enables L2C_ERR_TDTX[SBE]/L2C_TADX_INT[L2DSBE] to 5698232812Sjmallett assert L2C_INT_REG[TADX] (and cause an interrupt) */ 5699215976Sjmallett#else 5700215976Sjmallett uint64_t l2dsbe : 1; 5701215976Sjmallett uint64_t l2ddbe : 1; 5702215976Sjmallett uint64_t tagsbe : 1; 5703215976Sjmallett uint64_t tagdbe : 1; 5704215976Sjmallett uint64_t vbfsbe : 1; 5705215976Sjmallett uint64_t vbfdbe : 1; 5706215976Sjmallett uint64_t noway : 1; 5707215976Sjmallett uint64_t rddislmc : 1; 5708215976Sjmallett uint64_t wrdislmc : 1; 5709215976Sjmallett uint64_t reserved_9_63 : 55; 5710215976Sjmallett#endif 5711215976Sjmallett } s; 5712232812Sjmallett struct cvmx_l2c_tadx_ien_s cn61xx; 5713215976Sjmallett struct cvmx_l2c_tadx_ien_s cn63xx; 5714232812Sjmallett struct cvmx_l2c_tadx_ien_cn63xxp1 { 5715232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5716215976Sjmallett uint64_t reserved_7_63 : 57; 5717215976Sjmallett uint64_t noway : 1; /**< No way available interrupt enable 5718215976Sjmallett Enables L2C_ERR_TTGX[NOWAY] to assert 5719215976Sjmallett L2C_INT_REG[TADX] (and cause an interrupt) */ 5720215976Sjmallett uint64_t vbfdbe : 1; /**< VBF Double-Bit Error enable 5721215976Sjmallett Enables L2C_ERR_TDTX[VSBE] to assert 5722215976Sjmallett L2C_INT_REG[TADX] (and cause an interrupt) */ 5723215976Sjmallett uint64_t vbfsbe : 1; /**< VBF Single-Bit Error enable 5724215976Sjmallett Enables L2C_ERR_TDTX[VSBE] to assert 5725215976Sjmallett L2C_INT_REG[TADX] (and cause an interrupt) */ 5726215976Sjmallett uint64_t tagdbe : 1; /**< TAG Double-Bit Error enable 5727215976Sjmallett Enables L2C_ERR_TTGX[DBE] to assert 5728215976Sjmallett L2C_INT_REG[TADX] (and cause an interrupt) */ 5729215976Sjmallett uint64_t tagsbe : 1; /**< TAG Single-Bit Error enable 5730215976Sjmallett Enables L2C_ERR_TTGX[SBE] to assert 5731215976Sjmallett L2C_INT_REG[TADX] (and cause an interrupt) */ 5732215976Sjmallett uint64_t l2ddbe : 1; /**< L2D Double-Bit Error enable 5733215976Sjmallett Enables L2C_ERR_TDTX[DBE] to assert 5734215976Sjmallett L2C_INT_REG[TADX] (and cause an interrupt) */ 5735215976Sjmallett uint64_t l2dsbe : 1; /**< L2D Single-Bit Error enable 5736215976Sjmallett Enables L2C_ERR_TDTX[SBE] to assert 5737215976Sjmallett L2C_INT_REG[TADX] (and cause an interrupt) */ 5738215976Sjmallett#else 5739215976Sjmallett uint64_t l2dsbe : 1; 5740215976Sjmallett uint64_t l2ddbe : 1; 5741215976Sjmallett uint64_t tagsbe : 1; 5742215976Sjmallett uint64_t tagdbe : 1; 5743215976Sjmallett uint64_t vbfsbe : 1; 5744215976Sjmallett uint64_t vbfdbe : 1; 5745215976Sjmallett uint64_t noway : 1; 5746215976Sjmallett uint64_t reserved_7_63 : 57; 5747215976Sjmallett#endif 5748215976Sjmallett } cn63xxp1; 5749232812Sjmallett struct cvmx_l2c_tadx_ien_s cn66xx; 5750232812Sjmallett struct cvmx_l2c_tadx_ien_s cn68xx; 5751232812Sjmallett struct cvmx_l2c_tadx_ien_s cn68xxp1; 5752232812Sjmallett struct cvmx_l2c_tadx_ien_s cnf71xx; 5753215976Sjmallett}; 5754215976Sjmalletttypedef union cvmx_l2c_tadx_ien cvmx_l2c_tadx_ien_t; 5755215976Sjmallett 5756215976Sjmallett/** 5757215976Sjmallett * cvmx_l2c_tad#_int 5758215976Sjmallett * 5759215976Sjmallett * L2C_TAD_INT = L2C TAD Interrupt Register (not present in pass 1 O63) 5760215976Sjmallett * 5761215976Sjmallett * 5762215976Sjmallett * Notes: 5763215976Sjmallett * L2C_TAD_IEN is the interrupt enable register corresponding to this register. 5764215976Sjmallett * 5765215976Sjmallett */ 5766232812Sjmallettunion cvmx_l2c_tadx_int { 5767215976Sjmallett uint64_t u64; 5768232812Sjmallett struct cvmx_l2c_tadx_int_s { 5769232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5770215976Sjmallett uint64_t reserved_9_63 : 55; 5771215976Sjmallett uint64_t wrdislmc : 1; /**< Illegal Write to Disabled LMC Error 5772215976Sjmallett A DRAM write arrived before the LMC(s) were enabled */ 5773215976Sjmallett uint64_t rddislmc : 1; /**< Illegal Read to Disabled LMC Error 5774215976Sjmallett A DRAM read arrived before the LMC(s) were enabled */ 5775215976Sjmallett uint64_t noway : 1; /**< No way available interrupt 5776215976Sjmallett Shadow copy of L2C_ERR_TTGX[NOWAY] 5777215976Sjmallett Writes of 1 also clear L2C_ERR_TTGX[NOWAY] */ 5778215976Sjmallett uint64_t vbfdbe : 1; /**< VBF Double-Bit Error 5779215976Sjmallett Shadow copy of L2C_ERR_TDTX[VDBE] 5780215976Sjmallett Writes of 1 also clear L2C_ERR_TDTX[VDBE] */ 5781215976Sjmallett uint64_t vbfsbe : 1; /**< VBF Single-Bit Error 5782215976Sjmallett Shadow copy of L2C_ERR_TDTX[VSBE] 5783215976Sjmallett Writes of 1 also clear L2C_ERR_TDTX[VSBE] */ 5784215976Sjmallett uint64_t tagdbe : 1; /**< TAG Double-Bit Error 5785215976Sjmallett Shadow copy of L2C_ERR_TTGX[DBE] 5786215976Sjmallett Writes of 1 also clear L2C_ERR_TTGX[DBE] */ 5787215976Sjmallett uint64_t tagsbe : 1; /**< TAG Single-Bit Error 5788215976Sjmallett Shadow copy of L2C_ERR_TTGX[SBE] 5789215976Sjmallett Writes of 1 also clear L2C_ERR_TTGX[SBE] */ 5790215976Sjmallett uint64_t l2ddbe : 1; /**< L2D Double-Bit Error 5791215976Sjmallett Shadow copy of L2C_ERR_TDTX[DBE] 5792215976Sjmallett Writes of 1 also clear L2C_ERR_TDTX[DBE] */ 5793215976Sjmallett uint64_t l2dsbe : 1; /**< L2D Single-Bit Error 5794215976Sjmallett Shadow copy of L2C_ERR_TDTX[SBE] 5795215976Sjmallett Writes of 1 also clear L2C_ERR_TDTX[SBE] */ 5796215976Sjmallett#else 5797215976Sjmallett uint64_t l2dsbe : 1; 5798215976Sjmallett uint64_t l2ddbe : 1; 5799215976Sjmallett uint64_t tagsbe : 1; 5800215976Sjmallett uint64_t tagdbe : 1; 5801215976Sjmallett uint64_t vbfsbe : 1; 5802215976Sjmallett uint64_t vbfdbe : 1; 5803215976Sjmallett uint64_t noway : 1; 5804215976Sjmallett uint64_t rddislmc : 1; 5805215976Sjmallett uint64_t wrdislmc : 1; 5806215976Sjmallett uint64_t reserved_9_63 : 55; 5807215976Sjmallett#endif 5808215976Sjmallett } s; 5809232812Sjmallett struct cvmx_l2c_tadx_int_s cn61xx; 5810215976Sjmallett struct cvmx_l2c_tadx_int_s cn63xx; 5811232812Sjmallett struct cvmx_l2c_tadx_int_s cn66xx; 5812232812Sjmallett struct cvmx_l2c_tadx_int_s cn68xx; 5813232812Sjmallett struct cvmx_l2c_tadx_int_s cn68xxp1; 5814232812Sjmallett struct cvmx_l2c_tadx_int_s cnf71xx; 5815215976Sjmallett}; 5816215976Sjmalletttypedef union cvmx_l2c_tadx_int cvmx_l2c_tadx_int_t; 5817215976Sjmallett 5818215976Sjmallett/** 5819215976Sjmallett * cvmx_l2c_tad#_pfc0 5820215976Sjmallett * 5821215976Sjmallett * L2C_TAD_PFC0 = L2C TAD Performance Counter 0 5822215976Sjmallett * 5823215976Sjmallett */ 5824232812Sjmallettunion cvmx_l2c_tadx_pfc0 { 5825215976Sjmallett uint64_t u64; 5826232812Sjmallett struct cvmx_l2c_tadx_pfc0_s { 5827232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5828215976Sjmallett uint64_t count : 64; /**< Current counter value */ 5829215976Sjmallett#else 5830215976Sjmallett uint64_t count : 64; 5831215976Sjmallett#endif 5832215976Sjmallett } s; 5833232812Sjmallett struct cvmx_l2c_tadx_pfc0_s cn61xx; 5834215976Sjmallett struct cvmx_l2c_tadx_pfc0_s cn63xx; 5835215976Sjmallett struct cvmx_l2c_tadx_pfc0_s cn63xxp1; 5836232812Sjmallett struct cvmx_l2c_tadx_pfc0_s cn66xx; 5837232812Sjmallett struct cvmx_l2c_tadx_pfc0_s cn68xx; 5838232812Sjmallett struct cvmx_l2c_tadx_pfc0_s cn68xxp1; 5839232812Sjmallett struct cvmx_l2c_tadx_pfc0_s cnf71xx; 5840215976Sjmallett}; 5841215976Sjmalletttypedef union cvmx_l2c_tadx_pfc0 cvmx_l2c_tadx_pfc0_t; 5842215976Sjmallett 5843215976Sjmallett/** 5844215976Sjmallett * cvmx_l2c_tad#_pfc1 5845215976Sjmallett * 5846215976Sjmallett * L2C_TAD_PFC1 = L2C TAD Performance Counter 1 5847215976Sjmallett * 5848215976Sjmallett */ 5849232812Sjmallettunion cvmx_l2c_tadx_pfc1 { 5850215976Sjmallett uint64_t u64; 5851232812Sjmallett struct cvmx_l2c_tadx_pfc1_s { 5852232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5853215976Sjmallett uint64_t count : 64; /**< Current counter value */ 5854215976Sjmallett#else 5855215976Sjmallett uint64_t count : 64; 5856215976Sjmallett#endif 5857215976Sjmallett } s; 5858232812Sjmallett struct cvmx_l2c_tadx_pfc1_s cn61xx; 5859215976Sjmallett struct cvmx_l2c_tadx_pfc1_s cn63xx; 5860215976Sjmallett struct cvmx_l2c_tadx_pfc1_s cn63xxp1; 5861232812Sjmallett struct cvmx_l2c_tadx_pfc1_s cn66xx; 5862232812Sjmallett struct cvmx_l2c_tadx_pfc1_s cn68xx; 5863232812Sjmallett struct cvmx_l2c_tadx_pfc1_s cn68xxp1; 5864232812Sjmallett struct cvmx_l2c_tadx_pfc1_s cnf71xx; 5865215976Sjmallett}; 5866215976Sjmalletttypedef union cvmx_l2c_tadx_pfc1 cvmx_l2c_tadx_pfc1_t; 5867215976Sjmallett 5868215976Sjmallett/** 5869215976Sjmallett * cvmx_l2c_tad#_pfc2 5870215976Sjmallett * 5871215976Sjmallett * L2C_TAD_PFC2 = L2C TAD Performance Counter 2 5872215976Sjmallett * 5873215976Sjmallett */ 5874232812Sjmallettunion cvmx_l2c_tadx_pfc2 { 5875215976Sjmallett uint64_t u64; 5876232812Sjmallett struct cvmx_l2c_tadx_pfc2_s { 5877232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5878215976Sjmallett uint64_t count : 64; /**< Current counter value */ 5879215976Sjmallett#else 5880215976Sjmallett uint64_t count : 64; 5881215976Sjmallett#endif 5882215976Sjmallett } s; 5883232812Sjmallett struct cvmx_l2c_tadx_pfc2_s cn61xx; 5884215976Sjmallett struct cvmx_l2c_tadx_pfc2_s cn63xx; 5885215976Sjmallett struct cvmx_l2c_tadx_pfc2_s cn63xxp1; 5886232812Sjmallett struct cvmx_l2c_tadx_pfc2_s cn66xx; 5887232812Sjmallett struct cvmx_l2c_tadx_pfc2_s cn68xx; 5888232812Sjmallett struct cvmx_l2c_tadx_pfc2_s cn68xxp1; 5889232812Sjmallett struct cvmx_l2c_tadx_pfc2_s cnf71xx; 5890215976Sjmallett}; 5891215976Sjmalletttypedef union cvmx_l2c_tadx_pfc2 cvmx_l2c_tadx_pfc2_t; 5892215976Sjmallett 5893215976Sjmallett/** 5894215976Sjmallett * cvmx_l2c_tad#_pfc3 5895215976Sjmallett * 5896215976Sjmallett * L2C_TAD_PFC3 = L2C TAD Performance Counter 3 5897215976Sjmallett * 5898215976Sjmallett */ 5899232812Sjmallettunion cvmx_l2c_tadx_pfc3 { 5900215976Sjmallett uint64_t u64; 5901232812Sjmallett struct cvmx_l2c_tadx_pfc3_s { 5902232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5903215976Sjmallett uint64_t count : 64; /**< Current counter value */ 5904215976Sjmallett#else 5905215976Sjmallett uint64_t count : 64; 5906215976Sjmallett#endif 5907215976Sjmallett } s; 5908232812Sjmallett struct cvmx_l2c_tadx_pfc3_s cn61xx; 5909215976Sjmallett struct cvmx_l2c_tadx_pfc3_s cn63xx; 5910215976Sjmallett struct cvmx_l2c_tadx_pfc3_s cn63xxp1; 5911232812Sjmallett struct cvmx_l2c_tadx_pfc3_s cn66xx; 5912232812Sjmallett struct cvmx_l2c_tadx_pfc3_s cn68xx; 5913232812Sjmallett struct cvmx_l2c_tadx_pfc3_s cn68xxp1; 5914232812Sjmallett struct cvmx_l2c_tadx_pfc3_s cnf71xx; 5915215976Sjmallett}; 5916215976Sjmalletttypedef union cvmx_l2c_tadx_pfc3 cvmx_l2c_tadx_pfc3_t; 5917215976Sjmallett 5918215976Sjmallett/** 5919215976Sjmallett * cvmx_l2c_tad#_prf 5920215976Sjmallett * 5921215976Sjmallett * L2C_TAD_PRF = L2C TAD Performance Counter Control 5922215976Sjmallett * 5923215976Sjmallett * 5924215976Sjmallett * Notes: 5925215976Sjmallett * (1) All four counters are equivalent and can use any of the defined selects. 5926215976Sjmallett * 5927215976Sjmallett * (2) the CNTnSEL legal values are: 5928215976Sjmallett * 0x00 -- Nothing (disabled) 5929215976Sjmallett * 0x01 -- L2 Tag Hit 5930215976Sjmallett * 0x02 -- L2 Tag Miss 5931215976Sjmallett * 0x03 -- L2 Tag NoAlloc (forced no-allocate) 5932215976Sjmallett * 0x04 -- L2 Victim 5933215976Sjmallett * 0x05 -- SC Fail 5934215976Sjmallett * 0x06 -- SC Pass 5935215976Sjmallett * 0x07 -- LFB Occupancy (each cycle adds \# of LFBs valid) 5936215976Sjmallett * 0x08 -- LFB Wait LFB (each cycle adds \# LFBs waiting for other LFBs) 5937215976Sjmallett * 0x09 -- LFB Wait VAB (each cycle adds \# LFBs waiting for VAB) 5938215976Sjmallett * 0x80 -- Quad 0 index bus inuse 5939215976Sjmallett * 0x81 -- Quad 0 read data bus inuse 5940215976Sjmallett * 0x82 -- Quad 0 \# banks inuse (0-4/cycle) 5941215976Sjmallett * 0x83 -- Quad 0 wdat flops inuse (0-4/cycle) 5942215976Sjmallett * 0x90 -- Quad 1 index bus inuse 5943215976Sjmallett * 0x91 -- Quad 1 read data bus inuse 5944215976Sjmallett * 0x92 -- Quad 1 \# banks inuse (0-4/cycle) 5945215976Sjmallett * 0x93 -- Quad 1 wdat flops inuse (0-4/cycle) 5946215976Sjmallett * 0xA0 -- Quad 2 index bus inuse 5947215976Sjmallett * 0xA1 -- Quad 2 read data bus inuse 5948215976Sjmallett * 0xA2 -- Quad 2 \# banks inuse (0-4/cycle) 5949215976Sjmallett * 0xA3 -- Quad 2 wdat flops inuse (0-4/cycle) 5950215976Sjmallett * 0xB0 -- Quad 3 index bus inuse 5951215976Sjmallett * 0xB1 -- Quad 3 read data bus inuse 5952215976Sjmallett * 0xB2 -- Quad 3 \# banks inuse (0-4/cycle) 5953215976Sjmallett * 0xB3 -- Quad 3 wdat flops inuse (0-4/cycle) 5954215976Sjmallett */ 5955232812Sjmallettunion cvmx_l2c_tadx_prf { 5956215976Sjmallett uint64_t u64; 5957232812Sjmallett struct cvmx_l2c_tadx_prf_s { 5958232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5959215976Sjmallett uint64_t reserved_32_63 : 32; 5960215976Sjmallett uint64_t cnt3sel : 8; /**< Selects event to count for L2C_TAD_PFC3 */ 5961215976Sjmallett uint64_t cnt2sel : 8; /**< Selects event to count for L2C_TAD_PFC2 */ 5962215976Sjmallett uint64_t cnt1sel : 8; /**< Selects event to count for L2C_TAD_PFC1 */ 5963215976Sjmallett uint64_t cnt0sel : 8; /**< Selects event to count for L2C_TAD_PFC0 */ 5964215976Sjmallett#else 5965215976Sjmallett uint64_t cnt0sel : 8; 5966215976Sjmallett uint64_t cnt1sel : 8; 5967215976Sjmallett uint64_t cnt2sel : 8; 5968215976Sjmallett uint64_t cnt3sel : 8; 5969215976Sjmallett uint64_t reserved_32_63 : 32; 5970215976Sjmallett#endif 5971215976Sjmallett } s; 5972232812Sjmallett struct cvmx_l2c_tadx_prf_s cn61xx; 5973215976Sjmallett struct cvmx_l2c_tadx_prf_s cn63xx; 5974215976Sjmallett struct cvmx_l2c_tadx_prf_s cn63xxp1; 5975232812Sjmallett struct cvmx_l2c_tadx_prf_s cn66xx; 5976232812Sjmallett struct cvmx_l2c_tadx_prf_s cn68xx; 5977232812Sjmallett struct cvmx_l2c_tadx_prf_s cn68xxp1; 5978232812Sjmallett struct cvmx_l2c_tadx_prf_s cnf71xx; 5979215976Sjmallett}; 5980215976Sjmalletttypedef union cvmx_l2c_tadx_prf cvmx_l2c_tadx_prf_t; 5981215976Sjmallett 5982215976Sjmallett/** 5983215976Sjmallett * cvmx_l2c_tad#_tag 5984215976Sjmallett * 5985215976Sjmallett * L2C_TAD_TAG = L2C tag data 5986215976Sjmallett * 5987215976Sjmallett * Description: holds the tag information for LTGL2I and STGL2I commands 5988215976Sjmallett * 5989215976Sjmallett * Notes: 5990215976Sjmallett * (1) For 63xx TAG[35] must be written zero for STGL2I's or operation is undefined. During normal 5991215976Sjmallett * operation, TAG[35] will also read 0. 5992215976Sjmallett * 5993215976Sjmallett * (2) If setting the LOCK bit, the USE bit should also be set or operation is undefined. 5994215976Sjmallett * 5995215976Sjmallett * (3) The tag is the corresponding bits from the L2C+LMC internal L2/DRAM byte address. 5996215976Sjmallett */ 5997232812Sjmallettunion cvmx_l2c_tadx_tag { 5998215976Sjmallett uint64_t u64; 5999232812Sjmallett struct cvmx_l2c_tadx_tag_s { 6000232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6001215976Sjmallett uint64_t reserved_46_63 : 18; 6002215976Sjmallett uint64_t ecc : 6; /**< The tag ECC */ 6003215976Sjmallett uint64_t reserved_36_39 : 4; 6004215976Sjmallett uint64_t tag : 19; /**< The tag (see notes 1 and 3) */ 6005215976Sjmallett uint64_t reserved_4_16 : 13; 6006215976Sjmallett uint64_t use : 1; /**< The LRU use bit */ 6007215976Sjmallett uint64_t valid : 1; /**< The valid bit */ 6008215976Sjmallett uint64_t dirty : 1; /**< The dirty bit */ 6009215976Sjmallett uint64_t lock : 1; /**< The lock bit */ 6010215976Sjmallett#else 6011215976Sjmallett uint64_t lock : 1; 6012215976Sjmallett uint64_t dirty : 1; 6013215976Sjmallett uint64_t valid : 1; 6014215976Sjmallett uint64_t use : 1; 6015215976Sjmallett uint64_t reserved_4_16 : 13; 6016215976Sjmallett uint64_t tag : 19; 6017215976Sjmallett uint64_t reserved_36_39 : 4; 6018215976Sjmallett uint64_t ecc : 6; 6019215976Sjmallett uint64_t reserved_46_63 : 18; 6020215976Sjmallett#endif 6021215976Sjmallett } s; 6022232812Sjmallett struct cvmx_l2c_tadx_tag_s cn61xx; 6023215976Sjmallett struct cvmx_l2c_tadx_tag_s cn63xx; 6024215976Sjmallett struct cvmx_l2c_tadx_tag_s cn63xxp1; 6025232812Sjmallett struct cvmx_l2c_tadx_tag_s cn66xx; 6026232812Sjmallett struct cvmx_l2c_tadx_tag_s cn68xx; 6027232812Sjmallett struct cvmx_l2c_tadx_tag_s cn68xxp1; 6028232812Sjmallett struct cvmx_l2c_tadx_tag_s cnf71xx; 6029215976Sjmallett}; 6030215976Sjmalletttypedef union cvmx_l2c_tadx_tag cvmx_l2c_tadx_tag_t; 6031215976Sjmallett 6032215976Sjmallett/** 6033215976Sjmallett * cvmx_l2c_ver_id 6034215976Sjmallett * 6035215976Sjmallett * L2C_VER_ID = L2C Virtualization ID Error Register 6036215976Sjmallett * 6037215976Sjmallett * Description: records virtualization IDs associated with HOLEWR/BIGWR/VRTWR/VRTIDRNG/VRTADRNG interrupts. 6038215976Sjmallett */ 6039232812Sjmallettunion cvmx_l2c_ver_id { 6040215976Sjmallett uint64_t u64; 6041232812Sjmallett struct cvmx_l2c_ver_id_s { 6042232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6043232812Sjmallett uint64_t mask : 64; /**< Mask of virtualization IDs which had a 6044232812Sjmallett HOLEWR/BIGWR/VRTWR error */ 6045215976Sjmallett#else 6046215976Sjmallett uint64_t mask : 64; 6047215976Sjmallett#endif 6048215976Sjmallett } s; 6049232812Sjmallett struct cvmx_l2c_ver_id_s cn61xx; 6050215976Sjmallett struct cvmx_l2c_ver_id_s cn63xx; 6051215976Sjmallett struct cvmx_l2c_ver_id_s cn63xxp1; 6052232812Sjmallett struct cvmx_l2c_ver_id_s cn66xx; 6053232812Sjmallett struct cvmx_l2c_ver_id_s cn68xx; 6054232812Sjmallett struct cvmx_l2c_ver_id_s cn68xxp1; 6055232812Sjmallett struct cvmx_l2c_ver_id_s cnf71xx; 6056215976Sjmallett}; 6057215976Sjmalletttypedef union cvmx_l2c_ver_id cvmx_l2c_ver_id_t; 6058215976Sjmallett 6059215976Sjmallett/** 6060215976Sjmallett * cvmx_l2c_ver_iob 6061215976Sjmallett * 6062215976Sjmallett * L2C_VER_IOB = L2C Virtualization ID IOB Error Register 6063215976Sjmallett * 6064215976Sjmallett * Description: records IOBs associated with HOLEWR/BIGWR/VRTWR/VRTIDRNG/VRTADRNG interrupts. 6065215976Sjmallett */ 6066232812Sjmallettunion cvmx_l2c_ver_iob { 6067215976Sjmallett uint64_t u64; 6068232812Sjmallett struct cvmx_l2c_ver_iob_s { 6069232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6070232812Sjmallett uint64_t reserved_2_63 : 62; 6071232812Sjmallett uint64_t mask : 2; /**< Mask of IOBs which had a HOLEWR/BIGWR/VRTWR error */ 6072232812Sjmallett#else 6073232812Sjmallett uint64_t mask : 2; 6074232812Sjmallett uint64_t reserved_2_63 : 62; 6075232812Sjmallett#endif 6076232812Sjmallett } s; 6077232812Sjmallett struct cvmx_l2c_ver_iob_cn61xx { 6078232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6079215976Sjmallett uint64_t reserved_1_63 : 63; 6080232812Sjmallett uint64_t mask : 1; /**< Mask of IOBs which had a HOLEWR/BIGWR/VRTWR error */ 6081215976Sjmallett#else 6082215976Sjmallett uint64_t mask : 1; 6083215976Sjmallett uint64_t reserved_1_63 : 63; 6084215976Sjmallett#endif 6085232812Sjmallett } cn61xx; 6086232812Sjmallett struct cvmx_l2c_ver_iob_cn61xx cn63xx; 6087232812Sjmallett struct cvmx_l2c_ver_iob_cn61xx cn63xxp1; 6088232812Sjmallett struct cvmx_l2c_ver_iob_cn61xx cn66xx; 6089232812Sjmallett struct cvmx_l2c_ver_iob_s cn68xx; 6090232812Sjmallett struct cvmx_l2c_ver_iob_s cn68xxp1; 6091232812Sjmallett struct cvmx_l2c_ver_iob_cn61xx cnf71xx; 6092215976Sjmallett}; 6093215976Sjmalletttypedef union cvmx_l2c_ver_iob cvmx_l2c_ver_iob_t; 6094215976Sjmallett 6095215976Sjmallett/** 6096215976Sjmallett * cvmx_l2c_ver_msc 6097215976Sjmallett * 6098215976Sjmallett * L2C_VER_MSC = L2C Virtualization Miscellaneous Error Register (not in 63xx pass 1.x) 6099215976Sjmallett * 6100215976Sjmallett * Description: records type of command associated with HOLEWR/BIGWR/VRTWR/VRTIDRNG/VRTADRNG interrupts 6101215976Sjmallett */ 6102232812Sjmallettunion cvmx_l2c_ver_msc { 6103215976Sjmallett uint64_t u64; 6104232812Sjmallett struct cvmx_l2c_ver_msc_s { 6105232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6106215976Sjmallett uint64_t reserved_2_63 : 62; 6107215976Sjmallett uint64_t invl2 : 1; /**< If set, a INVL2 caused HOLEWR/BIGWR/VRT* to set */ 6108215976Sjmallett uint64_t dwb : 1; /**< If set, a DWB caused HOLEWR/BIGWR/VRT* to set */ 6109215976Sjmallett#else 6110215976Sjmallett uint64_t dwb : 1; 6111215976Sjmallett uint64_t invl2 : 1; 6112215976Sjmallett uint64_t reserved_2_63 : 62; 6113215976Sjmallett#endif 6114215976Sjmallett } s; 6115232812Sjmallett struct cvmx_l2c_ver_msc_s cn61xx; 6116215976Sjmallett struct cvmx_l2c_ver_msc_s cn63xx; 6117232812Sjmallett struct cvmx_l2c_ver_msc_s cn66xx; 6118232812Sjmallett struct cvmx_l2c_ver_msc_s cn68xx; 6119232812Sjmallett struct cvmx_l2c_ver_msc_s cn68xxp1; 6120232812Sjmallett struct cvmx_l2c_ver_msc_s cnf71xx; 6121215976Sjmallett}; 6122215976Sjmalletttypedef union cvmx_l2c_ver_msc cvmx_l2c_ver_msc_t; 6123215976Sjmallett 6124215976Sjmallett/** 6125215976Sjmallett * cvmx_l2c_ver_pp 6126215976Sjmallett * 6127215976Sjmallett * L2C_VER_PP = L2C Virtualization ID PP Error Register 6128215976Sjmallett * 6129215976Sjmallett * Description: records PPs associated with HOLEWR/BIGWR/VRTWR/VRTIDRNG/VRTADRNG interrupts. 6130215976Sjmallett */ 6131232812Sjmallettunion cvmx_l2c_ver_pp { 6132215976Sjmallett uint64_t u64; 6133232812Sjmallett struct cvmx_l2c_ver_pp_s { 6134232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6135232812Sjmallett uint64_t reserved_32_63 : 32; 6136232812Sjmallett uint64_t mask : 32; /**< Mask of PPs which had a HOLEWR/BIGWR/VRTWR error */ 6137232812Sjmallett#else 6138232812Sjmallett uint64_t mask : 32; 6139232812Sjmallett uint64_t reserved_32_63 : 32; 6140232812Sjmallett#endif 6141232812Sjmallett } s; 6142232812Sjmallett struct cvmx_l2c_ver_pp_cn61xx { 6143232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6144232812Sjmallett uint64_t reserved_4_63 : 60; 6145232812Sjmallett uint64_t mask : 4; /**< Mask of PPs which had a HOLEWR/BIGWR/VRTWR error */ 6146232812Sjmallett#else 6147232812Sjmallett uint64_t mask : 4; 6148232812Sjmallett uint64_t reserved_4_63 : 60; 6149232812Sjmallett#endif 6150232812Sjmallett } cn61xx; 6151232812Sjmallett struct cvmx_l2c_ver_pp_cn63xx { 6152232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6153215976Sjmallett uint64_t reserved_6_63 : 58; 6154232812Sjmallett uint64_t mask : 6; /**< Mask of PPs which had a HOLEWR/BIGWR/VRTWR error */ 6155215976Sjmallett#else 6156215976Sjmallett uint64_t mask : 6; 6157215976Sjmallett uint64_t reserved_6_63 : 58; 6158215976Sjmallett#endif 6159232812Sjmallett } cn63xx; 6160232812Sjmallett struct cvmx_l2c_ver_pp_cn63xx cn63xxp1; 6161232812Sjmallett struct cvmx_l2c_ver_pp_cn66xx { 6162232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6163232812Sjmallett uint64_t reserved_10_63 : 54; 6164232812Sjmallett uint64_t mask : 10; /**< Mask of PPs which had a HOLEWR/BIGWR/VRTWR error */ 6165232812Sjmallett#else 6166232812Sjmallett uint64_t mask : 10; 6167232812Sjmallett uint64_t reserved_10_63 : 54; 6168232812Sjmallett#endif 6169232812Sjmallett } cn66xx; 6170232812Sjmallett struct cvmx_l2c_ver_pp_s cn68xx; 6171232812Sjmallett struct cvmx_l2c_ver_pp_s cn68xxp1; 6172232812Sjmallett struct cvmx_l2c_ver_pp_cn61xx cnf71xx; 6173215976Sjmallett}; 6174215976Sjmalletttypedef union cvmx_l2c_ver_pp cvmx_l2c_ver_pp_t; 6175215976Sjmallett 6176215976Sjmallett/** 6177215976Sjmallett * cvmx_l2c_virtid_iob# 6178215976Sjmallett * 6179215976Sjmallett * L2C_VIRTID_IOB = L2C IOB virtualization ID 6180215976Sjmallett * 6181215976Sjmallett * Description: 6182215976Sjmallett */ 6183232812Sjmallettunion cvmx_l2c_virtid_iobx { 6184215976Sjmallett uint64_t u64; 6185232812Sjmallett struct cvmx_l2c_virtid_iobx_s { 6186232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6187215976Sjmallett uint64_t reserved_14_63 : 50; 6188215976Sjmallett uint64_t dwbid : 6; /**< Virtualization ID to use for DWB commands */ 6189215976Sjmallett uint64_t reserved_6_7 : 2; 6190215976Sjmallett uint64_t id : 6; /**< Virtualization ID to use for non-DWB commands */ 6191215976Sjmallett#else 6192215976Sjmallett uint64_t id : 6; 6193215976Sjmallett uint64_t reserved_6_7 : 2; 6194215976Sjmallett uint64_t dwbid : 6; 6195215976Sjmallett uint64_t reserved_14_63 : 50; 6196215976Sjmallett#endif 6197215976Sjmallett } s; 6198232812Sjmallett struct cvmx_l2c_virtid_iobx_s cn61xx; 6199215976Sjmallett struct cvmx_l2c_virtid_iobx_s cn63xx; 6200215976Sjmallett struct cvmx_l2c_virtid_iobx_s cn63xxp1; 6201232812Sjmallett struct cvmx_l2c_virtid_iobx_s cn66xx; 6202232812Sjmallett struct cvmx_l2c_virtid_iobx_s cn68xx; 6203232812Sjmallett struct cvmx_l2c_virtid_iobx_s cn68xxp1; 6204232812Sjmallett struct cvmx_l2c_virtid_iobx_s cnf71xx; 6205215976Sjmallett}; 6206215976Sjmalletttypedef union cvmx_l2c_virtid_iobx cvmx_l2c_virtid_iobx_t; 6207215976Sjmallett 6208215976Sjmallett/** 6209215976Sjmallett * cvmx_l2c_virtid_pp# 6210215976Sjmallett * 6211215976Sjmallett * L2C_VIRTID_PP = L2C PP virtualization ID 6212215976Sjmallett * 6213215976Sjmallett * Description: 6214215976Sjmallett */ 6215232812Sjmallettunion cvmx_l2c_virtid_ppx { 6216215976Sjmallett uint64_t u64; 6217232812Sjmallett struct cvmx_l2c_virtid_ppx_s { 6218232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6219215976Sjmallett uint64_t reserved_6_63 : 58; 6220215976Sjmallett uint64_t id : 6; /**< Virtualization ID to use for this PP. */ 6221215976Sjmallett#else 6222215976Sjmallett uint64_t id : 6; 6223215976Sjmallett uint64_t reserved_6_63 : 58; 6224215976Sjmallett#endif 6225215976Sjmallett } s; 6226232812Sjmallett struct cvmx_l2c_virtid_ppx_s cn61xx; 6227215976Sjmallett struct cvmx_l2c_virtid_ppx_s cn63xx; 6228215976Sjmallett struct cvmx_l2c_virtid_ppx_s cn63xxp1; 6229232812Sjmallett struct cvmx_l2c_virtid_ppx_s cn66xx; 6230232812Sjmallett struct cvmx_l2c_virtid_ppx_s cn68xx; 6231232812Sjmallett struct cvmx_l2c_virtid_ppx_s cn68xxp1; 6232232812Sjmallett struct cvmx_l2c_virtid_ppx_s cnf71xx; 6233215976Sjmallett}; 6234215976Sjmalletttypedef union cvmx_l2c_virtid_ppx cvmx_l2c_virtid_ppx_t; 6235215976Sjmallett 6236215976Sjmallett/** 6237215976Sjmallett * cvmx_l2c_vrt_ctl 6238215976Sjmallett * 6239215976Sjmallett * L2C_VRT_CTL = L2C Virtualization control register 6240215976Sjmallett * 6241215976Sjmallett */ 6242232812Sjmallettunion cvmx_l2c_vrt_ctl { 6243215976Sjmallett uint64_t u64; 6244232812Sjmallett struct cvmx_l2c_vrt_ctl_s { 6245232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6246215976Sjmallett uint64_t reserved_9_63 : 55; 6247215976Sjmallett uint64_t ooberr : 1; /**< Whether out of bounds writes are an error 6248215976Sjmallett Determines virtualization hardware behavior for 6249215976Sjmallett a store to an L2/DRAM address larger than 6250215976Sjmallett indicated by MEMSZ. If OOBERR is set, all these 6251215976Sjmallett stores (from any virtualization ID) are blocked. If 6252215976Sjmallett OOBERR is clear, none of these stores are blocked. */ 6253215976Sjmallett uint64_t reserved_7_7 : 1; 6254215976Sjmallett uint64_t memsz : 3; /**< Memory space coverage of L2C_VRT_MEM (encoded) 6255215976Sjmallett 0 = 1GB 6256215976Sjmallett 1 = 2GB 6257215976Sjmallett 2 = 4GB 6258215976Sjmallett 3 = 8GB 6259215976Sjmallett 4 = 16GB 6260215976Sjmallett 5 = 32GB 6261215976Sjmallett 6 = 64GB (**reserved in 63xx**) 6262215976Sjmallett 7 = 128GB (**reserved in 63xx**) */ 6263215976Sjmallett uint64_t numid : 3; /**< Number of allowed virtualization IDs (encoded) 6264215976Sjmallett 0 = 2 6265215976Sjmallett 1 = 4 6266215976Sjmallett 2 = 8 6267215976Sjmallett 3 = 16 6268215976Sjmallett 4 = 32 6269215976Sjmallett 5 = 64 6270215976Sjmallett 6,7 illegal 6271215976Sjmallett Violations of this limit causes 6272215976Sjmallett L2C to set L2C_INT_REG[VRTIDRNG]. */ 6273215976Sjmallett uint64_t enable : 1; /**< Global virtualization enable 6274215976Sjmallett When ENABLE is clear, stores are never blocked by 6275215976Sjmallett the L2C virtualization hardware and none of NUMID, 6276215976Sjmallett MEMSZ, OOBERR are used. */ 6277215976Sjmallett#else 6278215976Sjmallett uint64_t enable : 1; 6279215976Sjmallett uint64_t numid : 3; 6280215976Sjmallett uint64_t memsz : 3; 6281215976Sjmallett uint64_t reserved_7_7 : 1; 6282215976Sjmallett uint64_t ooberr : 1; 6283215976Sjmallett uint64_t reserved_9_63 : 55; 6284215976Sjmallett#endif 6285215976Sjmallett } s; 6286232812Sjmallett struct cvmx_l2c_vrt_ctl_s cn61xx; 6287215976Sjmallett struct cvmx_l2c_vrt_ctl_s cn63xx; 6288215976Sjmallett struct cvmx_l2c_vrt_ctl_s cn63xxp1; 6289232812Sjmallett struct cvmx_l2c_vrt_ctl_s cn66xx; 6290232812Sjmallett struct cvmx_l2c_vrt_ctl_s cn68xx; 6291232812Sjmallett struct cvmx_l2c_vrt_ctl_s cn68xxp1; 6292232812Sjmallett struct cvmx_l2c_vrt_ctl_s cnf71xx; 6293215976Sjmallett}; 6294215976Sjmalletttypedef union cvmx_l2c_vrt_ctl cvmx_l2c_vrt_ctl_t; 6295215976Sjmallett 6296215976Sjmallett/** 6297215976Sjmallett * cvmx_l2c_vrt_mem# 6298215976Sjmallett * 6299215976Sjmallett * L2C_VRT_MEM = L2C Virtualization Memory 6300215976Sjmallett * 6301215976Sjmallett * Description: Virtualization memory mapped region. There are 1024 32b 6302215976Sjmallett * byte-parity protected entries. 6303215976Sjmallett * 6304215976Sjmallett * Notes: 6305215976Sjmallett * When a DATA bit is set in L2C_VRT_MEM when L2C virtualization is enabled, L2C 6306215976Sjmallett * prevents the selected virtual machine from storing to the selected L2/DRAM region. 6307215976Sjmallett * L2C uses L2C_VRT_MEM to block stores when: 6308215976Sjmallett * - L2C_VRT_CTL[ENABLE] is set, and 6309215976Sjmallett * - the address of the store exists in L2C+LMC internal L2/DRAM Address space 6310215976Sjmallett * and is within the L2C_VRT_CTL[MEMSZ] bounds, and 6311215976Sjmallett * - the virtID of the store is within the L2C_VRT_CTL[NUMID] bounds 6312215976Sjmallett * 6313215976Sjmallett * L2C_VRT_MEM is never used for these L2C transactions which are always allowed: 6314215976Sjmallett * - L2C CMI L2/DRAM transactions that cannot modify L2/DRAM, and 6315215976Sjmallett * - any L2/DRAM transaction originated from L2C_XMC_CMD 6316215976Sjmallett * 6317215976Sjmallett * L2C_VRT_MEM contains one DATA bit per L2C+LMC internal L2/DRAM region and virtID indicating whether the store 6318215976Sjmallett * to the region is allowed. The granularity of the checking is the region size, which is: 6319215976Sjmallett * 2 ^^ (L2C_VRT_CTL[NUMID]+L2C_VRT_CTL[MEMSZ]+16) 6320215976Sjmallett * which ranges from a minimum of 64KB to a maximum of 256MB, depending on the size 6321215976Sjmallett * of L2/DRAM that is protected and the number of virtual machines. 6322215976Sjmallett * 6323215976Sjmallett * The L2C_VRT_MEM DATA bit that L2C uses is: 6324215976Sjmallett * 6325215976Sjmallett * l2c_vrt_mem_bit_index = address >> (L2C_VRT_CTL[MEMSZ]+L2C_VRT_CTL[NUMID]+16); // address is a byte address 6326215976Sjmallett * l2c_vrt_mem_bit_index = l2c_vrt_mem_bit_index | (virtID << (14-L2C_VRT_CTL[NUMID])); 6327215976Sjmallett * 6328215976Sjmallett * L2C_VRT_MEM(l2c_vrt_mem_bit_index >> 5)[DATA<l2c_vrt_mem_bit_index & 0x1F>] is used 6329215976Sjmallett * 6330215976Sjmallett * A specific example: 6331215976Sjmallett * 6332215976Sjmallett * L2C_VRT_CTL[NUMID]=2 (i.e. 8 virtual machine ID's used) 6333215976Sjmallett * L2C_VRT_CTL[MEMSZ]=4 (i.e. L2C_VRT_MEM covers 16 GB) 6334215976Sjmallett * 6335215976Sjmallett * L2/DRAM region size (granularity) is 4MB 6336215976Sjmallett * 6337215976Sjmallett * l2c_vrt_mem_bit_index<14:12> = virtID<2:0> 6338215976Sjmallett * l2c_vrt_mem_bit_index<11:0> = address<33:22> 6339215976Sjmallett * 6340215976Sjmallett * For L2/DRAM physical address 0x51000000 with virtID=5: 6341215976Sjmallett * L2C_VRT_MEM648[DATA<4>] determines when the store is allowed (648 is decimal, not hex) 6342215976Sjmallett */ 6343232812Sjmallettunion cvmx_l2c_vrt_memx { 6344215976Sjmallett uint64_t u64; 6345232812Sjmallett struct cvmx_l2c_vrt_memx_s { 6346232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6347215976Sjmallett uint64_t reserved_36_63 : 28; 6348215976Sjmallett uint64_t parity : 4; /**< Parity to write into (or read from) the 6349215976Sjmallett virtualization memory. 6350215976Sjmallett PARITY<i> is the even parity of DATA<(i*8)+7:i*8> */ 6351215976Sjmallett uint64_t data : 32; /**< Data to write into (or read from) the 6352215976Sjmallett virtualization memory. */ 6353215976Sjmallett#else 6354215976Sjmallett uint64_t data : 32; 6355215976Sjmallett uint64_t parity : 4; 6356215976Sjmallett uint64_t reserved_36_63 : 28; 6357215976Sjmallett#endif 6358215976Sjmallett } s; 6359232812Sjmallett struct cvmx_l2c_vrt_memx_s cn61xx; 6360215976Sjmallett struct cvmx_l2c_vrt_memx_s cn63xx; 6361215976Sjmallett struct cvmx_l2c_vrt_memx_s cn63xxp1; 6362232812Sjmallett struct cvmx_l2c_vrt_memx_s cn66xx; 6363232812Sjmallett struct cvmx_l2c_vrt_memx_s cn68xx; 6364232812Sjmallett struct cvmx_l2c_vrt_memx_s cn68xxp1; 6365232812Sjmallett struct cvmx_l2c_vrt_memx_s cnf71xx; 6366215976Sjmallett}; 6367215976Sjmalletttypedef union cvmx_l2c_vrt_memx cvmx_l2c_vrt_memx_t; 6368215976Sjmallett 6369215976Sjmallett/** 6370215976Sjmallett * cvmx_l2c_wpar_iob# 6371215976Sjmallett * 6372215976Sjmallett * L2C_WPAR_IOB = L2C IOB way partitioning 6373215976Sjmallett * 6374215976Sjmallett * 6375215976Sjmallett * Notes: 6376215976Sjmallett * (1) The read value of MASK will include bits set because of the L2C cripple fuses. 6377215976Sjmallett * 6378215976Sjmallett */ 6379232812Sjmallettunion cvmx_l2c_wpar_iobx { 6380215976Sjmallett uint64_t u64; 6381232812Sjmallett struct cvmx_l2c_wpar_iobx_s { 6382232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6383215976Sjmallett uint64_t reserved_16_63 : 48; 6384215976Sjmallett uint64_t mask : 16; /**< Way partitioning mask. (1 means do not use) */ 6385215976Sjmallett#else 6386215976Sjmallett uint64_t mask : 16; 6387215976Sjmallett uint64_t reserved_16_63 : 48; 6388215976Sjmallett#endif 6389215976Sjmallett } s; 6390232812Sjmallett struct cvmx_l2c_wpar_iobx_s cn61xx; 6391215976Sjmallett struct cvmx_l2c_wpar_iobx_s cn63xx; 6392215976Sjmallett struct cvmx_l2c_wpar_iobx_s cn63xxp1; 6393232812Sjmallett struct cvmx_l2c_wpar_iobx_s cn66xx; 6394232812Sjmallett struct cvmx_l2c_wpar_iobx_s cn68xx; 6395232812Sjmallett struct cvmx_l2c_wpar_iobx_s cn68xxp1; 6396232812Sjmallett struct cvmx_l2c_wpar_iobx_s cnf71xx; 6397215976Sjmallett}; 6398215976Sjmalletttypedef union cvmx_l2c_wpar_iobx cvmx_l2c_wpar_iobx_t; 6399215976Sjmallett 6400215976Sjmallett/** 6401215976Sjmallett * cvmx_l2c_wpar_pp# 6402215976Sjmallett * 6403215976Sjmallett * L2C_WPAR_PP = L2C PP way partitioning 6404215976Sjmallett * 6405215976Sjmallett * 6406215976Sjmallett * Notes: 6407215976Sjmallett * (1) The read value of MASK will include bits set because of the L2C cripple fuses. 6408215976Sjmallett * 6409215976Sjmallett */ 6410232812Sjmallettunion cvmx_l2c_wpar_ppx { 6411215976Sjmallett uint64_t u64; 6412232812Sjmallett struct cvmx_l2c_wpar_ppx_s { 6413232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6414215976Sjmallett uint64_t reserved_16_63 : 48; 6415215976Sjmallett uint64_t mask : 16; /**< Way partitioning mask. (1 means do not use) */ 6416215976Sjmallett#else 6417215976Sjmallett uint64_t mask : 16; 6418215976Sjmallett uint64_t reserved_16_63 : 48; 6419215976Sjmallett#endif 6420215976Sjmallett } s; 6421232812Sjmallett struct cvmx_l2c_wpar_ppx_s cn61xx; 6422215976Sjmallett struct cvmx_l2c_wpar_ppx_s cn63xx; 6423215976Sjmallett struct cvmx_l2c_wpar_ppx_s cn63xxp1; 6424232812Sjmallett struct cvmx_l2c_wpar_ppx_s cn66xx; 6425232812Sjmallett struct cvmx_l2c_wpar_ppx_s cn68xx; 6426232812Sjmallett struct cvmx_l2c_wpar_ppx_s cn68xxp1; 6427232812Sjmallett struct cvmx_l2c_wpar_ppx_s cnf71xx; 6428215976Sjmallett}; 6429215976Sjmalletttypedef union cvmx_l2c_wpar_ppx cvmx_l2c_wpar_ppx_t; 6430215976Sjmallett 6431215976Sjmallett/** 6432215976Sjmallett * cvmx_l2c_xmc#_pfc 6433215976Sjmallett * 6434215976Sjmallett * L2C_XMC_PFC = L2C XMC Performance Counter(s) 6435215976Sjmallett * 6436215976Sjmallett */ 6437232812Sjmallettunion cvmx_l2c_xmcx_pfc { 6438215976Sjmallett uint64_t u64; 6439232812Sjmallett struct cvmx_l2c_xmcx_pfc_s { 6440232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6441215976Sjmallett uint64_t count : 64; /**< Current counter value */ 6442215976Sjmallett#else 6443215976Sjmallett uint64_t count : 64; 6444215976Sjmallett#endif 6445215976Sjmallett } s; 6446232812Sjmallett struct cvmx_l2c_xmcx_pfc_s cn61xx; 6447215976Sjmallett struct cvmx_l2c_xmcx_pfc_s cn63xx; 6448215976Sjmallett struct cvmx_l2c_xmcx_pfc_s cn63xxp1; 6449232812Sjmallett struct cvmx_l2c_xmcx_pfc_s cn66xx; 6450232812Sjmallett struct cvmx_l2c_xmcx_pfc_s cn68xx; 6451232812Sjmallett struct cvmx_l2c_xmcx_pfc_s cn68xxp1; 6452232812Sjmallett struct cvmx_l2c_xmcx_pfc_s cnf71xx; 6453215976Sjmallett}; 6454215976Sjmalletttypedef union cvmx_l2c_xmcx_pfc cvmx_l2c_xmcx_pfc_t; 6455215976Sjmallett 6456215976Sjmallett/** 6457215976Sjmallett * cvmx_l2c_xmc_cmd 6458215976Sjmallett * 6459215976Sjmallett * L2C_XMC_CMD = L2C XMC command register 6460215976Sjmallett * 6461215976Sjmallett * 6462215976Sjmallett * Notes: 6463215976Sjmallett * (1) the XMC command chosen MUST NOT be a IOB destined command or operation is UNDEFINED. 6464215976Sjmallett * 6465215976Sjmallett * (2) the XMC command will have sid forced to IOB, did forced to L2C, no virtualization checks 6466215976Sjmallett * performed (always pass), and xmdmsk forced to 0. Note that this implies that commands which 6467215976Sjmallett * REQUIRE an XMD cycle (STP,STC,SAA,FAA,FAS) should not be used or the results are unpredictable. 6468215976Sjmallett * The sid=IOB means that the way partitioning used for the command is L2C_WPAR_IOB. 6469215976Sjmallett * None of L2C_QOS_IOB, L2C_QOS_PP, L2C_VIRTID_IOB, L2C_VIRTID_PP are used for these commands. 6470215976Sjmallett * 6471215976Sjmallett * (3) any responses generated by the XMC command will be forced to PP7 (a non-existant PP) effectively 6472215976Sjmallett * causing them to be ignored. Generated STINs, however, will correctly invalidate the required 6473215976Sjmallett * PPs. 6474215976Sjmallett * 6475215976Sjmallett * (4) any L2D read generated by the XMC command will record the syndrome information in 6476215976Sjmallett * L2C_TAD_ECC0/1. If ECC is disabled prior to the CSR write this provides the ability to read the 6477215976Sjmallett * ECC bits directly. If ECC is not disabled this should log 0's (assuming no ECC errors were 6478215976Sjmallett * found in the block). 6479215976Sjmallett * 6480215976Sjmallett * (5) A write which arrives while the INUSE bit is set will block until the INUSE bit clears. This 6481215976Sjmallett * gives software 2 options when needing to issue a stream of writes to L2C_XMC_CMD: polling on the 6482215976Sjmallett * INUSE bit, or allowing HW to handle the interlock -- at the expense of locking up the RSL bus 6483215976Sjmallett * for potentially tens of cycles at a time while waiting for an available LFB/VAB entry. 6484215976Sjmallett * 6485215976Sjmallett * (6) The address written to L2C_XMC_CMD is a 38-bit OCTEON physical address. L2C performs hole removal and 6486215976Sjmallett * index aliasing (if enabled) on the written address and uses that for the command. This hole 6487215976Sjmallett * removed/index aliased 38-bit address is what is returned on a read of the L2C_XMC_CMD register. 6488215976Sjmallett */ 6489232812Sjmallettunion cvmx_l2c_xmc_cmd { 6490215976Sjmallett uint64_t u64; 6491232812Sjmallett struct cvmx_l2c_xmc_cmd_s { 6492232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6493215976Sjmallett uint64_t inuse : 1; /**< Set to 1 by HW upon receiving a write, cleared when 6494215976Sjmallett command has issued (not necessarily completed, but 6495215976Sjmallett ordered relative to other traffic) and HW can accept 6496215976Sjmallett another command. */ 6497215976Sjmallett uint64_t cmd : 6; /**< Command to use for simulated XMC request 6498215976Sjmallett a new request can be accepted */ 6499215976Sjmallett uint64_t reserved_38_56 : 19; 6500215976Sjmallett uint64_t addr : 38; /**< Address to use for simulated XMC request (see Note 6) */ 6501215976Sjmallett#else 6502215976Sjmallett uint64_t addr : 38; 6503215976Sjmallett uint64_t reserved_38_56 : 19; 6504215976Sjmallett uint64_t cmd : 6; 6505215976Sjmallett uint64_t inuse : 1; 6506215976Sjmallett#endif 6507215976Sjmallett } s; 6508232812Sjmallett struct cvmx_l2c_xmc_cmd_s cn61xx; 6509215976Sjmallett struct cvmx_l2c_xmc_cmd_s cn63xx; 6510215976Sjmallett struct cvmx_l2c_xmc_cmd_s cn63xxp1; 6511232812Sjmallett struct cvmx_l2c_xmc_cmd_s cn66xx; 6512232812Sjmallett struct cvmx_l2c_xmc_cmd_s cn68xx; 6513232812Sjmallett struct cvmx_l2c_xmc_cmd_s cn68xxp1; 6514232812Sjmallett struct cvmx_l2c_xmc_cmd_s cnf71xx; 6515215976Sjmallett}; 6516215976Sjmalletttypedef union cvmx_l2c_xmc_cmd cvmx_l2c_xmc_cmd_t; 6517215976Sjmallett 6518215976Sjmallett/** 6519215976Sjmallett * cvmx_l2c_xmd#_pfc 6520215976Sjmallett * 6521215976Sjmallett * L2C_XMD_PFC = L2C XMD Performance Counter(s) 6522215976Sjmallett * 6523215976Sjmallett */ 6524232812Sjmallettunion cvmx_l2c_xmdx_pfc { 6525215976Sjmallett uint64_t u64; 6526232812Sjmallett struct cvmx_l2c_xmdx_pfc_s { 6527232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6528215976Sjmallett uint64_t count : 64; /**< Current counter value */ 6529215976Sjmallett#else 6530215976Sjmallett uint64_t count : 64; 6531215976Sjmallett#endif 6532215976Sjmallett } s; 6533232812Sjmallett struct cvmx_l2c_xmdx_pfc_s cn61xx; 6534215976Sjmallett struct cvmx_l2c_xmdx_pfc_s cn63xx; 6535215976Sjmallett struct cvmx_l2c_xmdx_pfc_s cn63xxp1; 6536232812Sjmallett struct cvmx_l2c_xmdx_pfc_s cn66xx; 6537232812Sjmallett struct cvmx_l2c_xmdx_pfc_s cn68xx; 6538232812Sjmallett struct cvmx_l2c_xmdx_pfc_s cn68xxp1; 6539232812Sjmallett struct cvmx_l2c_xmdx_pfc_s cnf71xx; 6540215976Sjmallett}; 6541215976Sjmalletttypedef union cvmx_l2c_xmdx_pfc cvmx_l2c_xmdx_pfc_t; 6542215976Sjmallett 6543215976Sjmallett#endif 6544