1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-dfm-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon dfm. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_DFM_DEFS_H__ 53232812Sjmallett#define __CVMX_DFM_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_DFM_CHAR_CTL CVMX_DFM_CHAR_CTL_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_DFM_CHAR_CTL_FUNC(void) 58215976Sjmallett{ 59232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 60215976Sjmallett cvmx_warn("CVMX_DFM_CHAR_CTL not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000220ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_DFM_CHAR_CTL (CVMX_ADD_IO_SEG(0x00011800D4000220ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_DFM_CHAR_MASK0 CVMX_DFM_CHAR_MASK0_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_DFM_CHAR_MASK0_FUNC(void) 69215976Sjmallett{ 70232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 71215976Sjmallett cvmx_warn("CVMX_DFM_CHAR_MASK0 not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000228ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_DFM_CHAR_MASK0 (CVMX_ADD_IO_SEG(0x00011800D4000228ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_DFM_CHAR_MASK2 CVMX_DFM_CHAR_MASK2_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_DFM_CHAR_MASK2_FUNC(void) 80215976Sjmallett{ 81232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 82215976Sjmallett cvmx_warn("CVMX_DFM_CHAR_MASK2 not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000238ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_DFM_CHAR_MASK2 (CVMX_ADD_IO_SEG(0x00011800D4000238ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallett#define CVMX_DFM_CHAR_MASK4 CVMX_DFM_CHAR_MASK4_FUNC() 90215976Sjmallettstatic inline uint64_t CVMX_DFM_CHAR_MASK4_FUNC(void) 91215976Sjmallett{ 92232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 93215976Sjmallett cvmx_warn("CVMX_DFM_CHAR_MASK4 not supported on this chip\n"); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000318ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_DFM_CHAR_MASK4 (CVMX_ADD_IO_SEG(0x00011800D4000318ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallett#define CVMX_DFM_COMP_CTL2 CVMX_DFM_COMP_CTL2_FUNC() 101215976Sjmallettstatic inline uint64_t CVMX_DFM_COMP_CTL2_FUNC(void) 102215976Sjmallett{ 103232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 104215976Sjmallett cvmx_warn("CVMX_DFM_COMP_CTL2 not supported on this chip\n"); 105215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D40001B8ull); 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_DFM_COMP_CTL2 (CVMX_ADD_IO_SEG(0x00011800D40001B8ull)) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallett#define CVMX_DFM_CONFIG CVMX_DFM_CONFIG_FUNC() 112215976Sjmallettstatic inline uint64_t CVMX_DFM_CONFIG_FUNC(void) 113215976Sjmallett{ 114232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 115215976Sjmallett cvmx_warn("CVMX_DFM_CONFIG not supported on this chip\n"); 116215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000188ull); 117215976Sjmallett} 118215976Sjmallett#else 119215976Sjmallett#define CVMX_DFM_CONFIG (CVMX_ADD_IO_SEG(0x00011800D4000188ull)) 120215976Sjmallett#endif 121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallett#define CVMX_DFM_CONTROL CVMX_DFM_CONTROL_FUNC() 123215976Sjmallettstatic inline uint64_t CVMX_DFM_CONTROL_FUNC(void) 124215976Sjmallett{ 125232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 126215976Sjmallett cvmx_warn("CVMX_DFM_CONTROL not supported on this chip\n"); 127215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000190ull); 128215976Sjmallett} 129215976Sjmallett#else 130215976Sjmallett#define CVMX_DFM_CONTROL (CVMX_ADD_IO_SEG(0x00011800D4000190ull)) 131215976Sjmallett#endif 132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133215976Sjmallett#define CVMX_DFM_DLL_CTL2 CVMX_DFM_DLL_CTL2_FUNC() 134215976Sjmallettstatic inline uint64_t CVMX_DFM_DLL_CTL2_FUNC(void) 135215976Sjmallett{ 136232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 137215976Sjmallett cvmx_warn("CVMX_DFM_DLL_CTL2 not supported on this chip\n"); 138215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D40001C8ull); 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_DFM_DLL_CTL2 (CVMX_ADD_IO_SEG(0x00011800D40001C8ull)) 142215976Sjmallett#endif 143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144215976Sjmallett#define CVMX_DFM_DLL_CTL3 CVMX_DFM_DLL_CTL3_FUNC() 145215976Sjmallettstatic inline uint64_t CVMX_DFM_DLL_CTL3_FUNC(void) 146215976Sjmallett{ 147232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 148215976Sjmallett cvmx_warn("CVMX_DFM_DLL_CTL3 not supported on this chip\n"); 149215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000218ull); 150215976Sjmallett} 151215976Sjmallett#else 152215976Sjmallett#define CVMX_DFM_DLL_CTL3 (CVMX_ADD_IO_SEG(0x00011800D4000218ull)) 153215976Sjmallett#endif 154215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155215976Sjmallett#define CVMX_DFM_FCLK_CNT CVMX_DFM_FCLK_CNT_FUNC() 156215976Sjmallettstatic inline uint64_t CVMX_DFM_FCLK_CNT_FUNC(void) 157215976Sjmallett{ 158232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 159215976Sjmallett cvmx_warn("CVMX_DFM_FCLK_CNT not supported on this chip\n"); 160215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D40001E0ull); 161215976Sjmallett} 162215976Sjmallett#else 163215976Sjmallett#define CVMX_DFM_FCLK_CNT (CVMX_ADD_IO_SEG(0x00011800D40001E0ull)) 164215976Sjmallett#endif 165215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166215976Sjmallett#define CVMX_DFM_FNT_BIST CVMX_DFM_FNT_BIST_FUNC() 167215976Sjmallettstatic inline uint64_t CVMX_DFM_FNT_BIST_FUNC(void) 168215976Sjmallett{ 169232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 170215976Sjmallett cvmx_warn("CVMX_DFM_FNT_BIST not supported on this chip\n"); 171215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D40007F8ull); 172215976Sjmallett} 173215976Sjmallett#else 174215976Sjmallett#define CVMX_DFM_FNT_BIST (CVMX_ADD_IO_SEG(0x00011800D40007F8ull)) 175215976Sjmallett#endif 176215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177215976Sjmallett#define CVMX_DFM_FNT_CTL CVMX_DFM_FNT_CTL_FUNC() 178215976Sjmallettstatic inline uint64_t CVMX_DFM_FNT_CTL_FUNC(void) 179215976Sjmallett{ 180232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 181215976Sjmallett cvmx_warn("CVMX_DFM_FNT_CTL not supported on this chip\n"); 182215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000400ull); 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_DFM_FNT_CTL (CVMX_ADD_IO_SEG(0x00011800D4000400ull)) 186215976Sjmallett#endif 187215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188215976Sjmallett#define CVMX_DFM_FNT_IENA CVMX_DFM_FNT_IENA_FUNC() 189215976Sjmallettstatic inline uint64_t CVMX_DFM_FNT_IENA_FUNC(void) 190215976Sjmallett{ 191232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 192215976Sjmallett cvmx_warn("CVMX_DFM_FNT_IENA not supported on this chip\n"); 193215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000410ull); 194215976Sjmallett} 195215976Sjmallett#else 196215976Sjmallett#define CVMX_DFM_FNT_IENA (CVMX_ADD_IO_SEG(0x00011800D4000410ull)) 197215976Sjmallett#endif 198215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199215976Sjmallett#define CVMX_DFM_FNT_SCLK CVMX_DFM_FNT_SCLK_FUNC() 200215976Sjmallettstatic inline uint64_t CVMX_DFM_FNT_SCLK_FUNC(void) 201215976Sjmallett{ 202232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 203215976Sjmallett cvmx_warn("CVMX_DFM_FNT_SCLK not supported on this chip\n"); 204215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000418ull); 205215976Sjmallett} 206215976Sjmallett#else 207215976Sjmallett#define CVMX_DFM_FNT_SCLK (CVMX_ADD_IO_SEG(0x00011800D4000418ull)) 208215976Sjmallett#endif 209215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210215976Sjmallett#define CVMX_DFM_FNT_STAT CVMX_DFM_FNT_STAT_FUNC() 211215976Sjmallettstatic inline uint64_t CVMX_DFM_FNT_STAT_FUNC(void) 212215976Sjmallett{ 213232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 214215976Sjmallett cvmx_warn("CVMX_DFM_FNT_STAT not supported on this chip\n"); 215215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000408ull); 216215976Sjmallett} 217215976Sjmallett#else 218215976Sjmallett#define CVMX_DFM_FNT_STAT (CVMX_ADD_IO_SEG(0x00011800D4000408ull)) 219215976Sjmallett#endif 220215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221215976Sjmallett#define CVMX_DFM_IFB_CNT CVMX_DFM_IFB_CNT_FUNC() 222215976Sjmallettstatic inline uint64_t CVMX_DFM_IFB_CNT_FUNC(void) 223215976Sjmallett{ 224232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 225215976Sjmallett cvmx_warn("CVMX_DFM_IFB_CNT not supported on this chip\n"); 226215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D40001D0ull); 227215976Sjmallett} 228215976Sjmallett#else 229215976Sjmallett#define CVMX_DFM_IFB_CNT (CVMX_ADD_IO_SEG(0x00011800D40001D0ull)) 230215976Sjmallett#endif 231215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232215976Sjmallett#define CVMX_DFM_MODEREG_PARAMS0 CVMX_DFM_MODEREG_PARAMS0_FUNC() 233215976Sjmallettstatic inline uint64_t CVMX_DFM_MODEREG_PARAMS0_FUNC(void) 234215976Sjmallett{ 235232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 236215976Sjmallett cvmx_warn("CVMX_DFM_MODEREG_PARAMS0 not supported on this chip\n"); 237215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D40001A8ull); 238215976Sjmallett} 239215976Sjmallett#else 240215976Sjmallett#define CVMX_DFM_MODEREG_PARAMS0 (CVMX_ADD_IO_SEG(0x00011800D40001A8ull)) 241215976Sjmallett#endif 242215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243215976Sjmallett#define CVMX_DFM_MODEREG_PARAMS1 CVMX_DFM_MODEREG_PARAMS1_FUNC() 244215976Sjmallettstatic inline uint64_t CVMX_DFM_MODEREG_PARAMS1_FUNC(void) 245215976Sjmallett{ 246232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 247215976Sjmallett cvmx_warn("CVMX_DFM_MODEREG_PARAMS1 not supported on this chip\n"); 248215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000260ull); 249215976Sjmallett} 250215976Sjmallett#else 251215976Sjmallett#define CVMX_DFM_MODEREG_PARAMS1 (CVMX_ADD_IO_SEG(0x00011800D4000260ull)) 252215976Sjmallett#endif 253215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254215976Sjmallett#define CVMX_DFM_OPS_CNT CVMX_DFM_OPS_CNT_FUNC() 255215976Sjmallettstatic inline uint64_t CVMX_DFM_OPS_CNT_FUNC(void) 256215976Sjmallett{ 257232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 258215976Sjmallett cvmx_warn("CVMX_DFM_OPS_CNT not supported on this chip\n"); 259215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D40001D8ull); 260215976Sjmallett} 261215976Sjmallett#else 262215976Sjmallett#define CVMX_DFM_OPS_CNT (CVMX_ADD_IO_SEG(0x00011800D40001D8ull)) 263215976Sjmallett#endif 264215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265215976Sjmallett#define CVMX_DFM_PHY_CTL CVMX_DFM_PHY_CTL_FUNC() 266215976Sjmallettstatic inline uint64_t CVMX_DFM_PHY_CTL_FUNC(void) 267215976Sjmallett{ 268232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 269215976Sjmallett cvmx_warn("CVMX_DFM_PHY_CTL not supported on this chip\n"); 270215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000210ull); 271215976Sjmallett} 272215976Sjmallett#else 273215976Sjmallett#define CVMX_DFM_PHY_CTL (CVMX_ADD_IO_SEG(0x00011800D4000210ull)) 274215976Sjmallett#endif 275215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276215976Sjmallett#define CVMX_DFM_RESET_CTL CVMX_DFM_RESET_CTL_FUNC() 277215976Sjmallettstatic inline uint64_t CVMX_DFM_RESET_CTL_FUNC(void) 278215976Sjmallett{ 279232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 280215976Sjmallett cvmx_warn("CVMX_DFM_RESET_CTL not supported on this chip\n"); 281215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000180ull); 282215976Sjmallett} 283215976Sjmallett#else 284215976Sjmallett#define CVMX_DFM_RESET_CTL (CVMX_ADD_IO_SEG(0x00011800D4000180ull)) 285215976Sjmallett#endif 286215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287215976Sjmallett#define CVMX_DFM_RLEVEL_CTL CVMX_DFM_RLEVEL_CTL_FUNC() 288215976Sjmallettstatic inline uint64_t CVMX_DFM_RLEVEL_CTL_FUNC(void) 289215976Sjmallett{ 290232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 291215976Sjmallett cvmx_warn("CVMX_DFM_RLEVEL_CTL not supported on this chip\n"); 292215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D40002A0ull); 293215976Sjmallett} 294215976Sjmallett#else 295215976Sjmallett#define CVMX_DFM_RLEVEL_CTL (CVMX_ADD_IO_SEG(0x00011800D40002A0ull)) 296215976Sjmallett#endif 297215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298215976Sjmallett#define CVMX_DFM_RLEVEL_DBG CVMX_DFM_RLEVEL_DBG_FUNC() 299215976Sjmallettstatic inline uint64_t CVMX_DFM_RLEVEL_DBG_FUNC(void) 300215976Sjmallett{ 301232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 302215976Sjmallett cvmx_warn("CVMX_DFM_RLEVEL_DBG not supported on this chip\n"); 303215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D40002A8ull); 304215976Sjmallett} 305215976Sjmallett#else 306215976Sjmallett#define CVMX_DFM_RLEVEL_DBG (CVMX_ADD_IO_SEG(0x00011800D40002A8ull)) 307215976Sjmallett#endif 308215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309215976Sjmallettstatic inline uint64_t CVMX_DFM_RLEVEL_RANKX(unsigned long offset) 310215976Sjmallett{ 311215976Sjmallett if (!( 312232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 313232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))))) 314215976Sjmallett cvmx_warn("CVMX_DFM_RLEVEL_RANKX(%lu) is invalid on this chip\n", offset); 315215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000280ull) + ((offset) & 1) * 8; 316215976Sjmallett} 317215976Sjmallett#else 318215976Sjmallett#define CVMX_DFM_RLEVEL_RANKX(offset) (CVMX_ADD_IO_SEG(0x00011800D4000280ull) + ((offset) & 1) * 8) 319215976Sjmallett#endif 320215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 321215976Sjmallett#define CVMX_DFM_RODT_MASK CVMX_DFM_RODT_MASK_FUNC() 322215976Sjmallettstatic inline uint64_t CVMX_DFM_RODT_MASK_FUNC(void) 323215976Sjmallett{ 324232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 325215976Sjmallett cvmx_warn("CVMX_DFM_RODT_MASK not supported on this chip\n"); 326215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000268ull); 327215976Sjmallett} 328215976Sjmallett#else 329215976Sjmallett#define CVMX_DFM_RODT_MASK (CVMX_ADD_IO_SEG(0x00011800D4000268ull)) 330215976Sjmallett#endif 331215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 332215976Sjmallett#define CVMX_DFM_SLOT_CTL0 CVMX_DFM_SLOT_CTL0_FUNC() 333215976Sjmallettstatic inline uint64_t CVMX_DFM_SLOT_CTL0_FUNC(void) 334215976Sjmallett{ 335232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 336215976Sjmallett cvmx_warn("CVMX_DFM_SLOT_CTL0 not supported on this chip\n"); 337215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D40001F8ull); 338215976Sjmallett} 339215976Sjmallett#else 340215976Sjmallett#define CVMX_DFM_SLOT_CTL0 (CVMX_ADD_IO_SEG(0x00011800D40001F8ull)) 341215976Sjmallett#endif 342215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 343215976Sjmallett#define CVMX_DFM_SLOT_CTL1 CVMX_DFM_SLOT_CTL1_FUNC() 344215976Sjmallettstatic inline uint64_t CVMX_DFM_SLOT_CTL1_FUNC(void) 345215976Sjmallett{ 346232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 347215976Sjmallett cvmx_warn("CVMX_DFM_SLOT_CTL1 not supported on this chip\n"); 348215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000200ull); 349215976Sjmallett} 350215976Sjmallett#else 351215976Sjmallett#define CVMX_DFM_SLOT_CTL1 (CVMX_ADD_IO_SEG(0x00011800D4000200ull)) 352215976Sjmallett#endif 353215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 354215976Sjmallett#define CVMX_DFM_TIMING_PARAMS0 CVMX_DFM_TIMING_PARAMS0_FUNC() 355215976Sjmallettstatic inline uint64_t CVMX_DFM_TIMING_PARAMS0_FUNC(void) 356215976Sjmallett{ 357232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 358215976Sjmallett cvmx_warn("CVMX_DFM_TIMING_PARAMS0 not supported on this chip\n"); 359215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000198ull); 360215976Sjmallett} 361215976Sjmallett#else 362215976Sjmallett#define CVMX_DFM_TIMING_PARAMS0 (CVMX_ADD_IO_SEG(0x00011800D4000198ull)) 363215976Sjmallett#endif 364215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 365215976Sjmallett#define CVMX_DFM_TIMING_PARAMS1 CVMX_DFM_TIMING_PARAMS1_FUNC() 366215976Sjmallettstatic inline uint64_t CVMX_DFM_TIMING_PARAMS1_FUNC(void) 367215976Sjmallett{ 368232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 369215976Sjmallett cvmx_warn("CVMX_DFM_TIMING_PARAMS1 not supported on this chip\n"); 370215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D40001A0ull); 371215976Sjmallett} 372215976Sjmallett#else 373215976Sjmallett#define CVMX_DFM_TIMING_PARAMS1 (CVMX_ADD_IO_SEG(0x00011800D40001A0ull)) 374215976Sjmallett#endif 375215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 376215976Sjmallett#define CVMX_DFM_WLEVEL_CTL CVMX_DFM_WLEVEL_CTL_FUNC() 377215976Sjmallettstatic inline uint64_t CVMX_DFM_WLEVEL_CTL_FUNC(void) 378215976Sjmallett{ 379232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 380215976Sjmallett cvmx_warn("CVMX_DFM_WLEVEL_CTL not supported on this chip\n"); 381215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000300ull); 382215976Sjmallett} 383215976Sjmallett#else 384215976Sjmallett#define CVMX_DFM_WLEVEL_CTL (CVMX_ADD_IO_SEG(0x00011800D4000300ull)) 385215976Sjmallett#endif 386215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 387215976Sjmallett#define CVMX_DFM_WLEVEL_DBG CVMX_DFM_WLEVEL_DBG_FUNC() 388215976Sjmallettstatic inline uint64_t CVMX_DFM_WLEVEL_DBG_FUNC(void) 389215976Sjmallett{ 390232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 391215976Sjmallett cvmx_warn("CVMX_DFM_WLEVEL_DBG not supported on this chip\n"); 392215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D4000308ull); 393215976Sjmallett} 394215976Sjmallett#else 395215976Sjmallett#define CVMX_DFM_WLEVEL_DBG (CVMX_ADD_IO_SEG(0x00011800D4000308ull)) 396215976Sjmallett#endif 397215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 398215976Sjmallettstatic inline uint64_t CVMX_DFM_WLEVEL_RANKX(unsigned long offset) 399215976Sjmallett{ 400215976Sjmallett if (!( 401232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 402232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))))) 403215976Sjmallett cvmx_warn("CVMX_DFM_WLEVEL_RANKX(%lu) is invalid on this chip\n", offset); 404215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D40002B0ull) + ((offset) & 1) * 8; 405215976Sjmallett} 406215976Sjmallett#else 407215976Sjmallett#define CVMX_DFM_WLEVEL_RANKX(offset) (CVMX_ADD_IO_SEG(0x00011800D40002B0ull) + ((offset) & 1) * 8) 408215976Sjmallett#endif 409215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 410215976Sjmallett#define CVMX_DFM_WODT_MASK CVMX_DFM_WODT_MASK_FUNC() 411215976Sjmallettstatic inline uint64_t CVMX_DFM_WODT_MASK_FUNC(void) 412215976Sjmallett{ 413232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))) 414215976Sjmallett cvmx_warn("CVMX_DFM_WODT_MASK not supported on this chip\n"); 415215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800D40001B0ull); 416215976Sjmallett} 417215976Sjmallett#else 418215976Sjmallett#define CVMX_DFM_WODT_MASK (CVMX_ADD_IO_SEG(0x00011800D40001B0ull)) 419215976Sjmallett#endif 420215976Sjmallett 421215976Sjmallett/** 422215976Sjmallett * cvmx_dfm_char_ctl 423215976Sjmallett * 424215976Sjmallett * DFM_CHAR_CTL = DFM Characterization Control 425215976Sjmallett * This register is an assortment of various control fields needed to charecterize the DDR3 interface 426232812Sjmallett * 427232812Sjmallett * Notes: 428232812Sjmallett * DR bit applies on the DQ port 429232812Sjmallett * 430215976Sjmallett */ 431232812Sjmallettunion cvmx_dfm_char_ctl { 432215976Sjmallett uint64_t u64; 433232812Sjmallett struct cvmx_dfm_char_ctl_s { 434232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 435232812Sjmallett uint64_t reserved_44_63 : 20; 436232812Sjmallett uint64_t dr : 1; /**< Pattern at Data Rate (not Clock Rate) */ 437232812Sjmallett uint64_t skew_on : 1; /**< Skew adjacent bits */ 438232812Sjmallett uint64_t en : 1; /**< Enable characterization */ 439232812Sjmallett uint64_t sel : 1; /**< Pattern select 440232812Sjmallett 0 = PRBS 441232812Sjmallett 1 = Programmable pattern */ 442232812Sjmallett uint64_t prog : 8; /**< Programmable pattern */ 443232812Sjmallett uint64_t prbs : 32; /**< PRBS Polynomial */ 444232812Sjmallett#else 445232812Sjmallett uint64_t prbs : 32; 446232812Sjmallett uint64_t prog : 8; 447232812Sjmallett uint64_t sel : 1; 448232812Sjmallett uint64_t en : 1; 449232812Sjmallett uint64_t skew_on : 1; 450232812Sjmallett uint64_t dr : 1; 451232812Sjmallett uint64_t reserved_44_63 : 20; 452232812Sjmallett#endif 453232812Sjmallett } s; 454232812Sjmallett struct cvmx_dfm_char_ctl_cn63xx { 455232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 456215976Sjmallett uint64_t reserved_42_63 : 22; 457215976Sjmallett uint64_t en : 1; /**< Enable characterization */ 458215976Sjmallett uint64_t sel : 1; /**< Pattern select 459215976Sjmallett 0 = PRBS 460215976Sjmallett 1 = Programmable pattern */ 461215976Sjmallett uint64_t prog : 8; /**< Programmable pattern */ 462215976Sjmallett uint64_t prbs : 32; /**< PRBS Polynomial */ 463215976Sjmallett#else 464215976Sjmallett uint64_t prbs : 32; 465215976Sjmallett uint64_t prog : 8; 466215976Sjmallett uint64_t sel : 1; 467215976Sjmallett uint64_t en : 1; 468215976Sjmallett uint64_t reserved_42_63 : 22; 469215976Sjmallett#endif 470232812Sjmallett } cn63xx; 471232812Sjmallett struct cvmx_dfm_char_ctl_cn63xx cn63xxp1; 472232812Sjmallett struct cvmx_dfm_char_ctl_s cn66xx; 473215976Sjmallett}; 474215976Sjmalletttypedef union cvmx_dfm_char_ctl cvmx_dfm_char_ctl_t; 475215976Sjmallett 476215976Sjmallett/** 477215976Sjmallett * cvmx_dfm_char_mask0 478215976Sjmallett * 479215976Sjmallett * DFM_CHAR_MASK0 = DFM Characterization Control Mask0 480215976Sjmallett * This register is an assortment of various control fields needed to charecterize the DDR3 interface 481215976Sjmallett */ 482232812Sjmallettunion cvmx_dfm_char_mask0 { 483215976Sjmallett uint64_t u64; 484232812Sjmallett struct cvmx_dfm_char_mask0_s { 485232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 486215976Sjmallett uint64_t reserved_16_63 : 48; 487215976Sjmallett uint64_t mask : 16; /**< Mask for DQ0[15:0] */ 488215976Sjmallett#else 489215976Sjmallett uint64_t mask : 16; 490215976Sjmallett uint64_t reserved_16_63 : 48; 491215976Sjmallett#endif 492215976Sjmallett } s; 493215976Sjmallett struct cvmx_dfm_char_mask0_s cn63xx; 494215976Sjmallett struct cvmx_dfm_char_mask0_s cn63xxp1; 495232812Sjmallett struct cvmx_dfm_char_mask0_s cn66xx; 496215976Sjmallett}; 497215976Sjmalletttypedef union cvmx_dfm_char_mask0 cvmx_dfm_char_mask0_t; 498215976Sjmallett 499215976Sjmallett/** 500215976Sjmallett * cvmx_dfm_char_mask2 501215976Sjmallett * 502215976Sjmallett * DFM_CHAR_MASK2 = DFM Characterization Control Mask2 503215976Sjmallett * This register is an assortment of various control fields needed to charecterize the DDR3 interface 504215976Sjmallett */ 505232812Sjmallettunion cvmx_dfm_char_mask2 { 506215976Sjmallett uint64_t u64; 507232812Sjmallett struct cvmx_dfm_char_mask2_s { 508232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 509215976Sjmallett uint64_t reserved_16_63 : 48; 510215976Sjmallett uint64_t mask : 16; /**< Mask for DQ1[15:0] */ 511215976Sjmallett#else 512215976Sjmallett uint64_t mask : 16; 513215976Sjmallett uint64_t reserved_16_63 : 48; 514215976Sjmallett#endif 515215976Sjmallett } s; 516215976Sjmallett struct cvmx_dfm_char_mask2_s cn63xx; 517215976Sjmallett struct cvmx_dfm_char_mask2_s cn63xxp1; 518232812Sjmallett struct cvmx_dfm_char_mask2_s cn66xx; 519215976Sjmallett}; 520215976Sjmalletttypedef union cvmx_dfm_char_mask2 cvmx_dfm_char_mask2_t; 521215976Sjmallett 522215976Sjmallett/** 523215976Sjmallett * cvmx_dfm_char_mask4 524215976Sjmallett * 525215976Sjmallett * DFM_CHAR_MASK4 = DFM Characterization Mask4 526215976Sjmallett * This register is an assortment of various control fields needed to charecterize the DDR3 interface 527215976Sjmallett */ 528232812Sjmallettunion cvmx_dfm_char_mask4 { 529215976Sjmallett uint64_t u64; 530232812Sjmallett struct cvmx_dfm_char_mask4_s { 531232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 532215976Sjmallett uint64_t reserved_33_63 : 31; 533215976Sjmallett uint64_t reset_n_mask : 1; /**< Mask for RESET_N */ 534215976Sjmallett uint64_t a_mask : 16; /**< Mask for A[15:0] */ 535215976Sjmallett uint64_t ba_mask : 3; /**< Mask for BA[2:0] */ 536215976Sjmallett uint64_t we_n_mask : 1; /**< Mask for WE_N */ 537215976Sjmallett uint64_t cas_n_mask : 1; /**< Mask for CAS_N */ 538215976Sjmallett uint64_t ras_n_mask : 1; /**< Mask for RAS_N */ 539215976Sjmallett uint64_t odt1_mask : 2; /**< Mask for ODT1 540215976Sjmallett For DFM, ODT1 is reserved. */ 541215976Sjmallett uint64_t odt0_mask : 2; /**< Mask for ODT0 */ 542215976Sjmallett uint64_t cs1_n_mask : 2; /**< Mask for CS1_N 543215976Sjmallett For DFM, CS1_N is reserved. */ 544215976Sjmallett uint64_t cs0_n_mask : 2; /**< Mask for CS0_N */ 545215976Sjmallett uint64_t cke_mask : 2; /**< Mask for CKE 546215976Sjmallett For DFM, CKE_MASK[1] is reserved. */ 547215976Sjmallett#else 548215976Sjmallett uint64_t cke_mask : 2; 549215976Sjmallett uint64_t cs0_n_mask : 2; 550215976Sjmallett uint64_t cs1_n_mask : 2; 551215976Sjmallett uint64_t odt0_mask : 2; 552215976Sjmallett uint64_t odt1_mask : 2; 553215976Sjmallett uint64_t ras_n_mask : 1; 554215976Sjmallett uint64_t cas_n_mask : 1; 555215976Sjmallett uint64_t we_n_mask : 1; 556215976Sjmallett uint64_t ba_mask : 3; 557215976Sjmallett uint64_t a_mask : 16; 558215976Sjmallett uint64_t reset_n_mask : 1; 559215976Sjmallett uint64_t reserved_33_63 : 31; 560215976Sjmallett#endif 561215976Sjmallett } s; 562215976Sjmallett struct cvmx_dfm_char_mask4_s cn63xx; 563232812Sjmallett struct cvmx_dfm_char_mask4_s cn66xx; 564215976Sjmallett}; 565215976Sjmalletttypedef union cvmx_dfm_char_mask4 cvmx_dfm_char_mask4_t; 566215976Sjmallett 567215976Sjmallett/** 568215976Sjmallett * cvmx_dfm_comp_ctl2 569215976Sjmallett * 570215976Sjmallett * DFM_COMP_CTL2 = DFM Compensation control2 571215976Sjmallett * 572215976Sjmallett */ 573232812Sjmallettunion cvmx_dfm_comp_ctl2 { 574215976Sjmallett uint64_t u64; 575232812Sjmallett struct cvmx_dfm_comp_ctl2_s { 576232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 577215976Sjmallett uint64_t reserved_34_63 : 30; 578215976Sjmallett uint64_t ddr__ptune : 4; /**< DDR pctl from compensation circuit 579215976Sjmallett The encoded value provides debug information for the 580215976Sjmallett compensation impedance on P-pullup */ 581215976Sjmallett uint64_t ddr__ntune : 4; /**< DDR nctl from compensation circuit 582215976Sjmallett The encoded value provides debug information for the 583215976Sjmallett compensation impedance on N-pulldown */ 584215976Sjmallett uint64_t m180 : 1; /**< Cap impedance at 180 ohm (instead of 240 ohm) */ 585215976Sjmallett uint64_t byp : 1; /**< Bypass mode 586215976Sjmallett Use compensation setting from PTUNE,NTUNE */ 587215976Sjmallett uint64_t ptune : 4; /**< PCTL impedance control in bypass mode */ 588215976Sjmallett uint64_t ntune : 4; /**< NCTL impedance control in bypass mode */ 589215976Sjmallett uint64_t rodt_ctl : 4; /**< NCTL RODT impedance control bits 590215976Sjmallett 0000 = No ODT 591215976Sjmallett 0001 = 20 ohm 592215976Sjmallett 0010 = 30 ohm 593215976Sjmallett 0011 = 40 ohm 594215976Sjmallett 0100 = 60 ohm 595215976Sjmallett 0101 = 120 ohm 596215976Sjmallett 0110-1111 = Reserved */ 597215976Sjmallett uint64_t cmd_ctl : 4; /**< Drive strength control for CMD/A/RESET_N/CKE drivers 598215976Sjmallett 0001 = 24 ohm 599215976Sjmallett 0010 = 26.67 ohm 600215976Sjmallett 0011 = 30 ohm 601215976Sjmallett 0100 = 34.3 ohm 602215976Sjmallett 0101 = 40 ohm 603215976Sjmallett 0110 = 48 ohm 604215976Sjmallett 0111 = 60 ohm 605215976Sjmallett 0000,1000-1111 = Reserved */ 606215976Sjmallett uint64_t ck_ctl : 4; /**< Drive strength control for CK/CS_N/ODT drivers 607215976Sjmallett 0001 = 24 ohm 608215976Sjmallett 0010 = 26.67 ohm 609215976Sjmallett 0011 = 30 ohm 610215976Sjmallett 0100 = 34.3 ohm 611215976Sjmallett 0101 = 40 ohm 612215976Sjmallett 0110 = 48 ohm 613215976Sjmallett 0111 = 60 ohm 614215976Sjmallett 0000,1000-1111 = Reserved */ 615215976Sjmallett uint64_t dqx_ctl : 4; /**< Drive strength control for DQ/DQS drivers 616215976Sjmallett 0001 = 24 ohm 617215976Sjmallett 0010 = 26.67 ohm 618215976Sjmallett 0011 = 30 ohm 619215976Sjmallett 0100 = 34.3 ohm 620215976Sjmallett 0101 = 40 ohm 621215976Sjmallett 0110 = 48 ohm 622215976Sjmallett 0111 = 60 ohm 623215976Sjmallett 0000,1000-1111 = Reserved */ 624215976Sjmallett#else 625215976Sjmallett uint64_t dqx_ctl : 4; 626215976Sjmallett uint64_t ck_ctl : 4; 627215976Sjmallett uint64_t cmd_ctl : 4; 628215976Sjmallett uint64_t rodt_ctl : 4; 629215976Sjmallett uint64_t ntune : 4; 630215976Sjmallett uint64_t ptune : 4; 631215976Sjmallett uint64_t byp : 1; 632215976Sjmallett uint64_t m180 : 1; 633215976Sjmallett uint64_t ddr__ntune : 4; 634215976Sjmallett uint64_t ddr__ptune : 4; 635215976Sjmallett uint64_t reserved_34_63 : 30; 636215976Sjmallett#endif 637215976Sjmallett } s; 638215976Sjmallett struct cvmx_dfm_comp_ctl2_s cn63xx; 639215976Sjmallett struct cvmx_dfm_comp_ctl2_s cn63xxp1; 640232812Sjmallett struct cvmx_dfm_comp_ctl2_s cn66xx; 641215976Sjmallett}; 642215976Sjmalletttypedef union cvmx_dfm_comp_ctl2 cvmx_dfm_comp_ctl2_t; 643215976Sjmallett 644215976Sjmallett/** 645215976Sjmallett * cvmx_dfm_config 646215976Sjmallett * 647215976Sjmallett * DFM_CONFIG = DFM Memory Configuration Register 648215976Sjmallett * 649215976Sjmallett * This register controls certain parameters of Memory Configuration 650215976Sjmallett * 651215976Sjmallett * Notes: 652215976Sjmallett * a. The self refresh entry sequence(s) power the DLL up/down (depending on DFM_MODEREG_PARAMS[DLL]) 653215976Sjmallett * when DFM_CONFIG[SREF_WITH_DLL] is set 654215976Sjmallett * b. Prior to the self-refresh exit sequence, DFM_MODEREG_PARAMS should be re-programmed (if needed) to the 655215976Sjmallett * appropriate values 656215976Sjmallett * 657215976Sjmallett * DFM Bringup Sequence: 658215976Sjmallett * 1. SW must ensure there are no pending DRAM transactions and that the DDR PLL and the DLL have been initialized. 659215976Sjmallett * 2. Write DFM_COMP_CTL2, DFM_CONTROL, DFM_WODT_MASK, DFM_RODT_MASK, DFM_DUAL_MEMCFG, DFM_TIMING_PARAMS0, DFM_TIMING_PARAMS1, 660215976Sjmallett * DFM_MODEREG_PARAMS0, DFM_MODEREG_PARAMS1, DFM_RESET_CTL (with DDR3RST=0), DFM_CONFIG (with INIT_START=0) 661215976Sjmallett * with appropriate values, if necessary. 662215976Sjmallett * 3. Wait 200us, then write DFM_RESET_CTL[DDR3RST] = 1. 663215976Sjmallett * 4. Initialize all ranks at once by writing DFM_CONFIG[RANKMASK][n] = 1, DFM_CONFIG[INIT_STATUS][n] = 1, and DFM_CONFIG[INIT_START] = 1 664215976Sjmallett * where n is a valid rank index for the specific board configuration. 665215976Sjmallett * 5. for each rank n to be write-leveled [ 666215976Sjmallett * if auto write-leveling is desired [ 667215976Sjmallett * write DFM_CONFIG[RANKMASK][n] = 1, DFM_WLEVEL_CTL appropriately and DFM_CONFIG[INIT_START] = 1 668215976Sjmallett * wait until DFM_WLEVEL_RANKn[STATUS] = 3 669215976Sjmallett * ] else [ 670215976Sjmallett * write DFM_WLEVEL_RANKn with appropriate values 671215976Sjmallett * ] 672215976Sjmallett * ] 673215976Sjmallett * 6. for each rank n to be read-leveled [ 674215976Sjmallett * if auto read-leveling is desired [ 675215976Sjmallett * write DFM_CONFIG[RANKMASK][n] = 1, DFM_RLEVEL_CTL appropriately and DFM_CONFIG[INIT_START] = 1 676215976Sjmallett * wait until DFM_RLEVEL_RANKn[STATUS] = 3 677215976Sjmallett * ] else [ 678215976Sjmallett * write DFM_RLEVEL_RANKn with appropriate values 679215976Sjmallett * ] 680215976Sjmallett * ] 681215976Sjmallett */ 682232812Sjmallettunion cvmx_dfm_config { 683215976Sjmallett uint64_t u64; 684232812Sjmallett struct cvmx_dfm_config_s { 685232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 686215976Sjmallett uint64_t reserved_59_63 : 5; 687215976Sjmallett uint64_t early_unload_d1_r1 : 1; /**< Reserved */ 688215976Sjmallett uint64_t early_unload_d1_r0 : 1; /**< Reserved */ 689215976Sjmallett uint64_t early_unload_d0_r1 : 1; /**< When set, unload the PHY silo one cycle early for Rank 1 690215976Sjmallett reads. 691215976Sjmallett The recommended EARLY_UNLOAD_D0_R1 value can be calculated 692215976Sjmallett after the final DFM_RLEVEL_RANK1[BYTE*] values are 693215976Sjmallett selected (as part of read-leveling initialization). 694215976Sjmallett Then, determine the largest read-leveling setting 695215976Sjmallett for rank 1 (i.e. calculate maxset=MAX(DFM_RLEVEL_RANK1[BYTEi]) 696215976Sjmallett across all i), then set EARLY_UNLOAD_D0_R1 697215976Sjmallett when the low two bits of this largest setting is not 698215976Sjmallett 3 (i.e. EARLY_UNLOAD_D0_R1 = (maxset<1:0>!=3)). */ 699215976Sjmallett uint64_t early_unload_d0_r0 : 1; /**< When set, unload the PHY silo one cycle early for Rank 0 700215976Sjmallett reads. 701215976Sjmallett The recommended EARLY_UNLOAD_D0_R0 value can be calculated 702215976Sjmallett after the final DFM_RLEVEL_RANK0[BYTE*] values are 703215976Sjmallett selected (as part of read-leveling initialization). 704215976Sjmallett Then, determine the largest read-leveling setting 705215976Sjmallett for rank 0 (i.e. calculate maxset=MAX(DFM_RLEVEL_RANK0[BYTEi]) 706215976Sjmallett across all i), then set EARLY_UNLOAD_D0_R0 707215976Sjmallett when the low two bits of this largest setting is not 708215976Sjmallett 3 (i.e. EARLY_UNLOAD_D0_R0 = (maxset<1:0>!=3)). */ 709215976Sjmallett uint64_t init_status : 4; /**< Indicates status of initialization 710215976Sjmallett INIT_STATUS[n] = 1 implies rank n has been initialized 711215976Sjmallett SW must set necessary INIT_STATUS bits with the 712215976Sjmallett same DFM_CONFIG write that initiates 713215976Sjmallett power-up/init and self-refresh exit sequences 714215976Sjmallett (if the required INIT_STATUS bits are not already 715215976Sjmallett set before DFM initiates the sequence). 716215976Sjmallett INIT_STATUS determines the chip-selects that assert 717215976Sjmallett during refresh, ZQCS, and precharge power-down and 718215976Sjmallett self-refresh entry/exit SEQUENCE's. 719215976Sjmallett INIT_STATUS<3:2> must be zero. */ 720215976Sjmallett uint64_t mirrmask : 4; /**< Mask determining which ranks are address-mirrored. 721215976Sjmallett MIRRMASK<n> = 1 means Rank n addresses are mirrored 722215976Sjmallett for 0 <= n <= 1 723215976Sjmallett A mirrored read/write has these differences: 724215976Sjmallett - DDR_BA<1> is swapped with DDR_BA<0> 725215976Sjmallett - DDR_A<8> is swapped with DDR_A<7> 726215976Sjmallett - DDR_A<6> is swapped with DDR_A<5> 727215976Sjmallett - DDR_A<4> is swapped with DDR_A<3> 728215976Sjmallett MIRRMASK<3:2> must be zero. 729215976Sjmallett When RANK_ENA=0, MIRRMASK<1> MBZ */ 730215976Sjmallett uint64_t rankmask : 4; /**< Mask to select rank to be leveled/initialized. 731215976Sjmallett To write-level/read-level/initialize rank i, set RANKMASK<i> 732215976Sjmallett RANK_ENA=1 RANK_ENA=0 733215976Sjmallett RANKMASK<0> = CS0 CS0 and CS1 734215976Sjmallett RANKMASK<1> = CS1 MBZ 735215976Sjmallett For read/write leveling, each rank has to be leveled separately, 736215976Sjmallett so RANKMASK should only have one bit set. 737215976Sjmallett RANKMASK is not used during self-refresh entry/exit and 738215976Sjmallett precharge power-down entry/exit instruction sequences. 739215976Sjmallett RANKMASK<3:2> must be zero. 740215976Sjmallett When RANK_ENA=0, RANKMASK<1> MBZ */ 741215976Sjmallett uint64_t rank_ena : 1; /**< RANK enable (for use with multiple ranks) 742215976Sjmallett The RANK_ENA bit enables 743215976Sjmallett the drive of the CS_N[1:0] and ODT_<1:0> pins differently based on the 744215976Sjmallett (PBANK_LSB-1) address bit. */ 745215976Sjmallett uint64_t sref_with_dll : 1; /**< Self-refresh entry/exit write MR1 and MR2 746215976Sjmallett When set, self-refresh entry and exit instruction sequences 747215976Sjmallett write MR1 and MR2 (in all ranks). (The writes occur before 748215976Sjmallett self-refresh entry, and after self-refresh exit.) 749215976Sjmallett When clear, self-refresh entry and exit instruction sequences 750215976Sjmallett do not write any registers in the DDR3 parts. */ 751215976Sjmallett uint64_t early_dqx : 1; /**< Send DQx signals one CK cycle earlier for the case when 752215976Sjmallett the shortest DQx lines have a larger delay than the CK line */ 753215976Sjmallett uint64_t sequence : 3; /**< Instruction sequence that is run after a 0->1 754215976Sjmallett transition on DFM_CONFIG[INIT_START]. Self-refresh entry and 755215976Sjmallett precharge power-down entry and exit SEQUENCE's can also 756215976Sjmallett be initiated automatically by hardware. 757215976Sjmallett 0=power-up/init (RANKMASK used, MR0, MR1, MR2, and MR3 written) 758215976Sjmallett 1=read-leveling (RANKMASK used, MR3 written) 759215976Sjmallett 2=self-refresh entry (all ranks participate, MR1 and MR2 written if SREF_WITH_DLL=1) 760215976Sjmallett 3=self-refresh exit, (all ranks participate, MR1 and MR2 written if SREF_WITH_DLL=1) 761215976Sjmallett 4=precharge power-down entry (all ranks participate) 762215976Sjmallett 5=precharge power-down exit (all ranks participate) 763215976Sjmallett 6=write-leveling (RANKMASK used, MR1 written) 764215976Sjmallett 7=illegal 765215976Sjmallett Precharge power-down entry and exit SEQUENCE's may 766215976Sjmallett be automatically generated by the HW when IDLEPOWER!=0. 767215976Sjmallett Self-refresh entry SEQUENCE's may be automatically 768215976Sjmallett generated by hardware upon a chip warm or soft reset 769215976Sjmallett sequence when DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT] are set. 770215976Sjmallett DFM writes the DFM_MODEREG_PARAMS0 and DFM_MODEREG_PARAMS1 CSR field values 771215976Sjmallett to the Mode registers in the DRAM parts (MR0, MR1, MR2, and MR3) as part of some of these sequences. 772215976Sjmallett Refer to the DFM_MODEREG_PARAMS0 and DFM_MODEREG_PARAMS1 descriptions for more details. 773215976Sjmallett The DFR_CKE pin gets activated as part of power-up/init, 774215976Sjmallett self-refresh exit, and precharge power-down exit sequences. 775215976Sjmallett The DFR_CKE pin gets de-activated as part of self-refresh entry, 776215976Sjmallett precharge power-down entry, or DRESET assertion. 777215976Sjmallett If there are two consecutive power-up/init's without 778215976Sjmallett a DRESET assertion between them, DFM asserts DFR_CKE as part of 779215976Sjmallett the first power-up/init, and continues to assert DFR_CKE 780215976Sjmallett through the remainder of the first and the second power-up/init. 781215976Sjmallett If DFR_CKE deactivation and reactivation is needed for 782215976Sjmallett a second power-up/init, a DRESET assertion is required 783215976Sjmallett between the first and the second. */ 784215976Sjmallett uint64_t ref_zqcs_int : 19; /**< Refresh & ZQCS interval represented in \#of 512 fclk 785215976Sjmallett increments. A Refresh sequence is triggered when bits 786215976Sjmallett [24:18] are equal to 0, and a ZQCS sequence is triggered 787215976Sjmallett when [36:18] are equal to 0. 788215976Sjmallett Program [24:18] to RND-DN(tREFI/clkPeriod/512) 789215976Sjmallett Program [36:25] to RND-DN(ZQCS_Interval/clkPeriod/(512*64)). Note 790215976Sjmallett that this value should always be greater than 32, to account for 791215976Sjmallett resistor calibration delays. 792215976Sjmallett 000_00000000_00000000: RESERVED 793215976Sjmallett Max Refresh interval = 127 * 512 = 65024 fclks 794215976Sjmallett Max ZQCS interval = (8*256*256-1) * 512 = 268434944 fclks ~ 335ms for a 1.25 ns clock 795215976Sjmallett DFM_CONFIG[INIT_STATUS] determines which ranks receive 796215976Sjmallett the REF / ZQCS. DFM does not send any refreshes / ZQCS's 797215976Sjmallett when DFM_CONFIG[INIT_STATUS]=0. */ 798215976Sjmallett uint64_t reset : 1; /**< Reset oneshot pulse for refresh counter, 799215976Sjmallett and DFM_OPS_CNT, DFM_IFB_CNT, and DFM_FCLK_CNT 800215976Sjmallett CSR's. SW should write this to a one, then re-write 801215976Sjmallett it to a zero to cause the reset. */ 802215976Sjmallett uint64_t ecc_adr : 1; /**< Must be zero. */ 803215976Sjmallett uint64_t forcewrite : 4; /**< Force the oldest outstanding write to complete after 804215976Sjmallett having waited for 2^FORCEWRITE cycles. 0=disabled. */ 805215976Sjmallett uint64_t idlepower : 3; /**< Enter precharge power-down mode after the memory 806215976Sjmallett controller has been idle for 2^(2+IDLEPOWER) cycles. 807215976Sjmallett 0=disabled. 808215976Sjmallett This field should only be programmed after initialization. 809215976Sjmallett DFM_MODEREG_PARAMS0[PPD] determines whether the DRAM DLL 810215976Sjmallett is disabled during the precharge power-down. */ 811215976Sjmallett uint64_t pbank_lsb : 4; /**< Physical bank address bit select 812215976Sjmallett Encoding used to determine which memory address 813215976Sjmallett bit position represents the rank(or bunk) bit used to enable 1(of 2) 814215976Sjmallett ranks(via chip enables) supported by the DFM DDR3 interface. 815215976Sjmallett Reverting to the explanation for ROW_LSB, PBANK_LSB would be ROW_LSB bit + 816215976Sjmallett \#rowbits + \#rankbits. 817215976Sjmallett PBANK_LSB 818215976Sjmallett - 0: rank = mem_adr[24] 819215976Sjmallett - 1: rank = mem_adr[25] 820215976Sjmallett - 2: rank = mem_adr[26] 821215976Sjmallett - 3: rank = mem_adr[27] 822215976Sjmallett - 4: rank = mem_adr[28] 823215976Sjmallett - 5: rank = mem_adr[29] 824215976Sjmallett - 6: rank = mem_adr[30] 825215976Sjmallett - 7: rank = mem_adr[31] 826215976Sjmallett - 8-15: RESERVED 827215976Sjmallett DESIGN NOTE: The DFM DDR3 memory bus is 16b wide, therefore DOES NOT 828215976Sjmallett support standard 64b/72b DDR3 DIMM modules. The board designer should 829215976Sjmallett populate the DFM DDR3 interface using either TWO x8bit DDR3 devices 830215976Sjmallett (or a single x16bit device if available) to fully populate the 16b 831215976Sjmallett DFM DDR3 data bus. 832215976Sjmallett The DFM DDR3 memory controller supports either 1(or 2) rank(s) based 833215976Sjmallett on how much total memory is desired for the DFA application. See 834215976Sjmallett RANK_ENA CSR bit when enabling for dual-ranks. 835215976Sjmallett SW NOTE: 836215976Sjmallett 1) When RANK_ENA=0, SW must properly configure the PBANK_LSB to 837215976Sjmallett reference upper unused memory address bits. 838215976Sjmallett 2) When RANK_ENA=1 (dual ranks), SW must configure PBANK_LSB to 839215976Sjmallett reference the upper most address bit based on the total size 840215976Sjmallett of the rank. 841215976Sjmallett For example, for a DFM DDR3 memory populated using Samsung's k4b1g0846c-f7 842215976Sjmallett 1Gb(256MB) (16M x 8 bit x 8 bank) DDR3 parts, the column address width = 10 and 843215976Sjmallett the device row address width = 14b. The single x8bit device contains 128MB, and 844215976Sjmallett requires TWO such parts to populate the DFM 16b DDR3 interface. This then yields 845215976Sjmallett a total rank size = 256MB = 2^28. 846215976Sjmallett For a single-rank configuration (RANK_ENA=0), SW would program PBANK_LSB>=3 to 847215976Sjmallett select mem_adr[x] bits above the legal DFM address range for mem_adr[27:0]=256MB. 848215976Sjmallett For a dual-rank configuration (RANK_ENA=1), SW would program PBANK_LSB=4 to select 849215976Sjmallett rank=mem_adr[28] as the bit used to determine which 256MB rank (of 512MB total) to 850215976Sjmallett access (via rank chip enables - see: DFM DDR3 CS0[1:0] pins for connection to 851215976Sjmallett upper and lower rank). */ 852215976Sjmallett uint64_t row_lsb : 3; /**< Row Address bit select 853215976Sjmallett Encoding used to determine which memory address 854215976Sjmallett bit position represents the low order DDR ROW address. 855215976Sjmallett The DFM memory address [31:4] which references octawords 856215976Sjmallett needs to be translated to DRAM addresses (bnk,row,col,bunk) 857215976Sjmallett mem_adr[31:4]: 858215976Sjmallett 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 859215976Sjmallett 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 860215976Sjmallett +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 861215976Sjmallett | ROW[m:n] | COL[13:3] | BA 862215976Sjmallett +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 863215976Sjmallett See: 864215976Sjmallett BA[2:0]: mem_adr[6:4] 865215976Sjmallett COL[13:0]: [mem_adr[17:7],3'd0] 866215976Sjmallett NOTE: The extracted COL address is always 14b fixed size width, 867215976Sjmallett and upper unused bits are ignored by the DRAM device. 868215976Sjmallett ROW[15:0]: Extraction of ROW starting address bit is programmable, 869215976Sjmallett and is dependent on the \#column bits supported by the DRAM device. 870215976Sjmallett The actual starting bit of the ROW can actually span into the 871215976Sjmallett high order bits of the COL[13:3] field described above. 872215976Sjmallett ROW_LSB ROW[15:0] 873215976Sjmallett -------------------------- 874215976Sjmallett - 0: mem_adr[26:11] 875215976Sjmallett - 1: mem_adr[27:12] 876215976Sjmallett - 2: mem_adr[28:13] 877215976Sjmallett - 3: mem_adr[29:14] 878215976Sjmallett - 4: mem_adr[30:15] 879215976Sjmallett - 5: mem_adr[31:16] 880215976Sjmallett 6,7: [1'b0, mem_adr[31:17]] For current DDR3 Jedec spec - UNSUPPORTED 881215976Sjmallett For example, for Samsung's k4b1g0846c-f7 1Gb (16M x 8 bit x 8 bank) 882215976Sjmallett DDR3 parts, the column address width = 10. Therefore, 883215976Sjmallett BA[3:0] = mem_adr[6:4] / COL[9:0] = [mem_adr[13:7],3'd0], and 884215976Sjmallett we would want the row starting address to be extracted from mem_adr[14]. 885215976Sjmallett Therefore, a ROW_LSB=3, will extract the row from mem_adr[29:14]. */ 886215976Sjmallett uint64_t ecc_ena : 1; /**< Must be zero. */ 887215976Sjmallett uint64_t init_start : 1; /**< A 0->1 transition starts the DDR memory sequence that is 888215976Sjmallett selected by DFM_CONFIG[SEQUENCE]. This register is a 889215976Sjmallett oneshot and clears itself each time it is set. */ 890215976Sjmallett#else 891215976Sjmallett uint64_t init_start : 1; 892215976Sjmallett uint64_t ecc_ena : 1; 893215976Sjmallett uint64_t row_lsb : 3; 894215976Sjmallett uint64_t pbank_lsb : 4; 895215976Sjmallett uint64_t idlepower : 3; 896215976Sjmallett uint64_t forcewrite : 4; 897215976Sjmallett uint64_t ecc_adr : 1; 898215976Sjmallett uint64_t reset : 1; 899215976Sjmallett uint64_t ref_zqcs_int : 19; 900215976Sjmallett uint64_t sequence : 3; 901215976Sjmallett uint64_t early_dqx : 1; 902215976Sjmallett uint64_t sref_with_dll : 1; 903215976Sjmallett uint64_t rank_ena : 1; 904215976Sjmallett uint64_t rankmask : 4; 905215976Sjmallett uint64_t mirrmask : 4; 906215976Sjmallett uint64_t init_status : 4; 907215976Sjmallett uint64_t early_unload_d0_r0 : 1; 908215976Sjmallett uint64_t early_unload_d0_r1 : 1; 909215976Sjmallett uint64_t early_unload_d1_r0 : 1; 910215976Sjmallett uint64_t early_unload_d1_r1 : 1; 911215976Sjmallett uint64_t reserved_59_63 : 5; 912215976Sjmallett#endif 913215976Sjmallett } s; 914215976Sjmallett struct cvmx_dfm_config_s cn63xx; 915232812Sjmallett struct cvmx_dfm_config_cn63xxp1 { 916232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 917215976Sjmallett uint64_t reserved_55_63 : 9; 918215976Sjmallett uint64_t init_status : 4; /**< Indicates status of initialization 919215976Sjmallett INIT_STATUS[n] = 1 implies rank n has been initialized 920215976Sjmallett SW must set necessary INIT_STATUS bits with the 921215976Sjmallett same DFM_CONFIG write that initiates 922215976Sjmallett power-up/init and self-refresh exit sequences 923215976Sjmallett (if the required INIT_STATUS bits are not already 924215976Sjmallett set before DFM initiates the sequence). 925215976Sjmallett INIT_STATUS determines the chip-selects that assert 926215976Sjmallett during refresh, ZQCS, and precharge power-down and 927215976Sjmallett self-refresh entry/exit SEQUENCE's. 928215976Sjmallett INIT_STATUS<3:2> must be zero. */ 929215976Sjmallett uint64_t mirrmask : 4; /**< Mask determining which ranks are address-mirrored. 930215976Sjmallett MIRRMASK<n> = 1 means Rank n addresses are mirrored 931215976Sjmallett for 0 <= n <= 1 932215976Sjmallett A mirrored read/write has these differences: 933215976Sjmallett - DDR_BA<1> is swapped with DDR_BA<0> 934215976Sjmallett - DDR_A<8> is swapped with DDR_A<7> 935215976Sjmallett - DDR_A<6> is swapped with DDR_A<5> 936215976Sjmallett - DDR_A<4> is swapped with DDR_A<3> 937215976Sjmallett MIRRMASK<3:2> must be zero. 938215976Sjmallett When RANK_ENA=0, MIRRMASK<1> MBZ */ 939215976Sjmallett uint64_t rankmask : 4; /**< Mask to select rank to be leveled/initialized. 940215976Sjmallett To write-level/read-level/initialize rank i, set RANKMASK<i> 941215976Sjmallett RANK_ENA=1 RANK_ENA=0 942215976Sjmallett RANKMASK<0> = CS0 CS0 and CS1 943215976Sjmallett RANKMASK<1> = CS1 MBZ 944215976Sjmallett For read/write leveling, each rank has to be leveled separately, 945215976Sjmallett so RANKMASK should only have one bit set. 946215976Sjmallett RANKMASK is not used during self-refresh entry/exit and 947215976Sjmallett precharge power-down entry/exit instruction sequences. 948215976Sjmallett RANKMASK<3:2> must be zero. 949215976Sjmallett When RANK_ENA=0, RANKMASK<1> MBZ */ 950215976Sjmallett uint64_t rank_ena : 1; /**< RANK enable (for use with multiple ranks) 951215976Sjmallett The RANK_ENA bit enables 952215976Sjmallett the drive of the CS_N[1:0] and ODT_<1:0> pins differently based on the 953215976Sjmallett (PBANK_LSB-1) address bit. */ 954215976Sjmallett uint64_t sref_with_dll : 1; /**< Self-refresh entry/exit write MR1 and MR2 955215976Sjmallett When set, self-refresh entry and exit instruction sequences 956215976Sjmallett write MR1 and MR2 (in all ranks). (The writes occur before 957215976Sjmallett self-refresh entry, and after self-refresh exit.) 958215976Sjmallett When clear, self-refresh entry and exit instruction sequences 959215976Sjmallett do not write any registers in the DDR3 parts. */ 960215976Sjmallett uint64_t early_dqx : 1; /**< Send DQx signals one CK cycle earlier for the case when 961215976Sjmallett the shortest DQx lines have a larger delay than the CK line */ 962215976Sjmallett uint64_t sequence : 3; /**< Instruction sequence that is run after a 0->1 963215976Sjmallett transition on DFM_CONFIG[INIT_START]. Self-refresh entry and 964215976Sjmallett precharge power-down entry and exit SEQUENCE's can also 965215976Sjmallett be initiated automatically by hardware. 966215976Sjmallett 0=power-up/init (RANKMASK used, MR0, MR1, MR2, and MR3 written) 967215976Sjmallett 1=read-leveling (RANKMASK used, MR3 written) 968215976Sjmallett 2=self-refresh entry (all ranks participate, MR1 and MR2 written if SREF_WITH_DLL=1) 969215976Sjmallett 3=self-refresh exit, (all ranks participate, MR1 and MR2 written if SREF_WITH_DLL=1) 970215976Sjmallett 4=precharge power-down entry (all ranks participate) 971215976Sjmallett 5=precharge power-down exit (all ranks participate) 972215976Sjmallett 6=write-leveling (RANKMASK used, MR1 written) 973215976Sjmallett 7=illegal 974215976Sjmallett Precharge power-down entry and exit SEQUENCE's may 975215976Sjmallett be automatically generated by the HW when IDLEPOWER!=0. 976215976Sjmallett Self-refresh entry SEQUENCE's may be automatically 977215976Sjmallett generated by hardware upon a chip warm or soft reset 978215976Sjmallett sequence when DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT] are set. 979215976Sjmallett DFM writes the DFM_MODEREG_PARAMS0 and DFM_MODEREG_PARAMS1 CSR field values 980215976Sjmallett to the Mode registers in the DRAM parts (MR0, MR1, MR2, and MR3) as part of some of these sequences. 981215976Sjmallett Refer to the DFM_MODEREG_PARAMS0 and DFM_MODEREG_PARAMS1 descriptions for more details. 982215976Sjmallett The DFR_CKE pin gets activated as part of power-up/init, 983215976Sjmallett self-refresh exit, and precharge power-down exit sequences. 984215976Sjmallett The DFR_CKE pin gets de-activated as part of self-refresh entry, 985215976Sjmallett precharge power-down entry, or DRESET assertion. 986215976Sjmallett If there are two consecutive power-up/init's without 987215976Sjmallett a DRESET assertion between them, DFM asserts DFR_CKE as part of 988215976Sjmallett the first power-up/init, and continues to assert DFR_CKE 989215976Sjmallett through the remainder of the first and the second power-up/init. 990215976Sjmallett If DFR_CKE deactivation and reactivation is needed for 991215976Sjmallett a second power-up/init, a DRESET assertion is required 992215976Sjmallett between the first and the second. */ 993215976Sjmallett uint64_t ref_zqcs_int : 19; /**< Refresh & ZQCS interval represented in \#of 512 fclk 994215976Sjmallett increments. A Refresh sequence is triggered when bits 995215976Sjmallett [24:18] are equal to 0, and a ZQCS sequence is triggered 996215976Sjmallett when [36:18] are equal to 0. 997215976Sjmallett Program [24:18] to RND-DN(tREFI/clkPeriod/512) 998215976Sjmallett Program [36:25] to RND-DN(ZQCS_Interval/clkPeriod/(512*64)). Note 999215976Sjmallett that this value should always be greater than 32, to account for 1000215976Sjmallett resistor calibration delays. 1001215976Sjmallett 000_00000000_00000000: RESERVED 1002215976Sjmallett Max Refresh interval = 127 * 512 = 65024 fclks 1003215976Sjmallett Max ZQCS interval = (8*256*256-1) * 512 = 268434944 fclks ~ 335ms for a 1.25 ns clock 1004215976Sjmallett DFM_CONFIG[INIT_STATUS] determines which ranks receive 1005215976Sjmallett the REF / ZQCS. DFM does not send any refreshes / ZQCS's 1006215976Sjmallett when DFM_CONFIG[INIT_STATUS]=0. */ 1007215976Sjmallett uint64_t reset : 1; /**< Reset oneshot pulse for refresh counter, 1008215976Sjmallett and DFM_OPS_CNT, DFM_IFB_CNT, and DFM_FCLK_CNT 1009215976Sjmallett CSR's. SW should write this to a one, then re-write 1010215976Sjmallett it to a zero to cause the reset. */ 1011215976Sjmallett uint64_t ecc_adr : 1; /**< Must be zero. */ 1012215976Sjmallett uint64_t forcewrite : 4; /**< Force the oldest outstanding write to complete after 1013215976Sjmallett having waited for 2^FORCEWRITE cycles. 0=disabled. */ 1014215976Sjmallett uint64_t idlepower : 3; /**< Enter precharge power-down mode after the memory 1015215976Sjmallett controller has been idle for 2^(2+IDLEPOWER) cycles. 1016215976Sjmallett 0=disabled. 1017215976Sjmallett This field should only be programmed after initialization. 1018215976Sjmallett DFM_MODEREG_PARAMS0[PPD] determines whether the DRAM DLL 1019215976Sjmallett is disabled during the precharge power-down. */ 1020215976Sjmallett uint64_t pbank_lsb : 4; /**< Physical bank address bit select 1021215976Sjmallett Encoding used to determine which memory address 1022215976Sjmallett bit position represents the rank(or bunk) bit used to enable 1(of 2) 1023215976Sjmallett ranks(via chip enables) supported by the DFM DDR3 interface. 1024215976Sjmallett Reverting to the explanation for ROW_LSB, PBANK_LSB would be ROW_LSB bit + 1025215976Sjmallett \#rowbits + \#rankbits. 1026215976Sjmallett PBANK_LSB 1027215976Sjmallett - 0: rank = mem_adr[24] 1028215976Sjmallett - 1: rank = mem_adr[25] 1029215976Sjmallett - 2: rank = mem_adr[26] 1030215976Sjmallett - 3: rank = mem_adr[27] 1031215976Sjmallett - 4: rank = mem_adr[28] 1032215976Sjmallett - 5: rank = mem_adr[29] 1033215976Sjmallett - 6: rank = mem_adr[30] 1034215976Sjmallett - 7: rank = mem_adr[31] 1035215976Sjmallett - 8-15: RESERVED 1036215976Sjmallett DESIGN NOTE: The DFM DDR3 memory bus is 16b wide, therefore DOES NOT 1037215976Sjmallett support standard 64b/72b DDR3 DIMM modules. The board designer should 1038215976Sjmallett populate the DFM DDR3 interface using either TWO x8bit DDR3 devices 1039215976Sjmallett (or a single x16bit device if available) to fully populate the 16b 1040215976Sjmallett DFM DDR3 data bus. 1041215976Sjmallett The DFM DDR3 memory controller supports either 1(or 2) rank(s) based 1042215976Sjmallett on how much total memory is desired for the DFA application. See 1043215976Sjmallett RANK_ENA CSR bit when enabling for dual-ranks. 1044215976Sjmallett SW NOTE: 1045215976Sjmallett 1) When RANK_ENA=0, SW must properly configure the PBANK_LSB to 1046215976Sjmallett reference upper unused memory address bits. 1047215976Sjmallett 2) When RANK_ENA=1 (dual ranks), SW must configure PBANK_LSB to 1048215976Sjmallett reference the upper most address bit based on the total size 1049215976Sjmallett of the rank. 1050215976Sjmallett For example, for a DFM DDR3 memory populated using Samsung's k4b1g0846c-f7 1051215976Sjmallett 1Gb(256MB) (16M x 8 bit x 8 bank) DDR3 parts, the column address width = 10 and 1052215976Sjmallett the device row address width = 14b. The single x8bit device contains 128MB, and 1053215976Sjmallett requires TWO such parts to populate the DFM 16b DDR3 interface. This then yields 1054215976Sjmallett a total rank size = 256MB = 2^28. 1055215976Sjmallett For a single-rank configuration (RANK_ENA=0), SW would program PBANK_LSB>=3 to 1056215976Sjmallett select mem_adr[x] bits above the legal DFM address range for mem_adr[27:0]=256MB. 1057215976Sjmallett For a dual-rank configuration (RANK_ENA=1), SW would program PBANK_LSB=4 to select 1058215976Sjmallett rank=mem_adr[28] as the bit used to determine which 256MB rank (of 512MB total) to 1059215976Sjmallett access (via rank chip enables - see: DFM DDR3 CS0[1:0] pins for connection to 1060215976Sjmallett upper and lower rank). */ 1061215976Sjmallett uint64_t row_lsb : 3; /**< Row Address bit select 1062215976Sjmallett Encoding used to determine which memory address 1063215976Sjmallett bit position represents the low order DDR ROW address. 1064215976Sjmallett The DFM memory address [31:4] which references octawords 1065215976Sjmallett needs to be translated to DRAM addresses (bnk,row,col,bunk) 1066215976Sjmallett mem_adr[31:4]: 1067215976Sjmallett 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1068215976Sjmallett 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 1069215976Sjmallett +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1070215976Sjmallett | ROW[m:n] | COL[13:3] | BA 1071215976Sjmallett +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1072215976Sjmallett See: 1073215976Sjmallett BA[2:0]: mem_adr[6:4] 1074215976Sjmallett COL[13:0]: [mem_adr[17:7],3'd0] 1075215976Sjmallett NOTE: The extracted COL address is always 14b fixed size width, 1076215976Sjmallett and upper unused bits are ignored by the DRAM device. 1077215976Sjmallett ROW[15:0]: Extraction of ROW starting address bit is programmable, 1078215976Sjmallett and is dependent on the \#column bits supported by the DRAM device. 1079215976Sjmallett The actual starting bit of the ROW can actually span into the 1080215976Sjmallett high order bits of the COL[13:3] field described above. 1081215976Sjmallett ROW_LSB ROW[15:0] 1082215976Sjmallett -------------------------- 1083215976Sjmallett - 0: mem_adr[26:11] 1084215976Sjmallett - 1: mem_adr[27:12] 1085215976Sjmallett - 2: mem_adr[28:13] 1086215976Sjmallett - 3: mem_adr[29:14] 1087215976Sjmallett - 4: mem_adr[30:15] 1088215976Sjmallett - 5: mem_adr[31:16] 1089215976Sjmallett 6,7: [1'b0, mem_adr[31:17]] For current DDR3 Jedec spec - UNSUPPORTED 1090215976Sjmallett For example, for Samsung's k4b1g0846c-f7 1Gb (16M x 8 bit x 8 bank) 1091215976Sjmallett DDR3 parts, the column address width = 10. Therefore, 1092215976Sjmallett BA[3:0] = mem_adr[6:4] / COL[9:0] = [mem_adr[13:7],3'd0], and 1093215976Sjmallett we would want the row starting address to be extracted from mem_adr[14]. 1094215976Sjmallett Therefore, a ROW_LSB=3, will extract the row from mem_adr[29:14]. */ 1095215976Sjmallett uint64_t ecc_ena : 1; /**< Must be zero. */ 1096215976Sjmallett uint64_t init_start : 1; /**< A 0->1 transition starts the DDR memory sequence that is 1097215976Sjmallett selected by DFM_CONFIG[SEQUENCE]. This register is a 1098215976Sjmallett oneshot and clears itself each time it is set. */ 1099215976Sjmallett#else 1100215976Sjmallett uint64_t init_start : 1; 1101215976Sjmallett uint64_t ecc_ena : 1; 1102215976Sjmallett uint64_t row_lsb : 3; 1103215976Sjmallett uint64_t pbank_lsb : 4; 1104215976Sjmallett uint64_t idlepower : 3; 1105215976Sjmallett uint64_t forcewrite : 4; 1106215976Sjmallett uint64_t ecc_adr : 1; 1107215976Sjmallett uint64_t reset : 1; 1108215976Sjmallett uint64_t ref_zqcs_int : 19; 1109215976Sjmallett uint64_t sequence : 3; 1110215976Sjmallett uint64_t early_dqx : 1; 1111215976Sjmallett uint64_t sref_with_dll : 1; 1112215976Sjmallett uint64_t rank_ena : 1; 1113215976Sjmallett uint64_t rankmask : 4; 1114215976Sjmallett uint64_t mirrmask : 4; 1115215976Sjmallett uint64_t init_status : 4; 1116215976Sjmallett uint64_t reserved_55_63 : 9; 1117215976Sjmallett#endif 1118215976Sjmallett } cn63xxp1; 1119232812Sjmallett struct cvmx_dfm_config_s cn66xx; 1120215976Sjmallett}; 1121215976Sjmalletttypedef union cvmx_dfm_config cvmx_dfm_config_t; 1122215976Sjmallett 1123215976Sjmallett/** 1124215976Sjmallett * cvmx_dfm_control 1125215976Sjmallett * 1126215976Sjmallett * DFM_CONTROL = DFM Control 1127215976Sjmallett * This register is an assortment of various control fields needed by the memory controller 1128215976Sjmallett */ 1129232812Sjmallettunion cvmx_dfm_control { 1130215976Sjmallett uint64_t u64; 1131232812Sjmallett struct cvmx_dfm_control_s { 1132232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1133215976Sjmallett uint64_t reserved_24_63 : 40; 1134215976Sjmallett uint64_t rodt_bprch : 1; /**< When set, the turn-off time for the ODT pin during a 1135215976Sjmallett RD cmd is delayed an additional DCLK cycle. */ 1136215976Sjmallett uint64_t wodt_bprch : 1; /**< When set, the turn-off time for the ODT pin during a 1137215976Sjmallett WR cmd is delayed an additional DCLK cycle. */ 1138215976Sjmallett uint64_t bprch : 2; /**< Back Porch Enable: When set, the turn-on time for 1139215976Sjmallett the default DDR_DQ/DQS drivers is delayed an additional BPRCH FCLK 1140215976Sjmallett cycles. 1141215976Sjmallett 00 = 0 fclks 1142215976Sjmallett 01 = 1 fclks 1143215976Sjmallett 10 = 2 fclks 1144215976Sjmallett 11 = 3 fclks */ 1145215976Sjmallett uint64_t ext_zqcs_dis : 1; /**< Disable (external) auto-zqcs calibration 1146215976Sjmallett When clear, DFM runs external ZQ calibration */ 1147215976Sjmallett uint64_t int_zqcs_dis : 1; /**< Disable (internal) auto-zqcs calibration 1148215976Sjmallett When counter is re-enabled, ZQCS is run immediately, 1149215976Sjmallett and then every DFM_CONFIG[REF_ZQCS_INT] fclk cycles. */ 1150215976Sjmallett uint64_t auto_fclkdis : 1; /**< When 1, DFM will automatically shut off its internal 1151215976Sjmallett clock to conserve power when there is no traffic. Note 1152215976Sjmallett that this has no effect on the DDR3 PHY and pads clocks. */ 1153215976Sjmallett uint64_t xor_bank : 1; /**< Must be zero. */ 1154215976Sjmallett uint64_t max_write_batch : 4; /**< Must be set to value 8 */ 1155215976Sjmallett uint64_t nxm_write_en : 1; /**< Must be zero. */ 1156215976Sjmallett uint64_t elev_prio_dis : 1; /**< Must be zero. */ 1157215976Sjmallett uint64_t inorder_wr : 1; /**< Must be zero. */ 1158215976Sjmallett uint64_t inorder_rd : 1; /**< Must be zero. */ 1159215976Sjmallett uint64_t throttle_wr : 1; /**< When set, use at most one IFB for writes 1160215976Sjmallett THROTTLE_RD and THROTTLE_WR must be the same value. */ 1161215976Sjmallett uint64_t throttle_rd : 1; /**< When set, use at most one IFB for reads 1162215976Sjmallett THROTTLE_RD and THROTTLE_WR must be the same value. */ 1163215976Sjmallett uint64_t fprch2 : 2; /**< Front Porch Enable: When set, the turn-off 1164215976Sjmallett time for the default DDR_DQ/DQS drivers is FPRCH2 fclks earlier. 1165215976Sjmallett 00 = 0 fclks 1166215976Sjmallett 01 = 1 fclks 1167215976Sjmallett 10 = 2 fclks 1168215976Sjmallett 11 = RESERVED */ 1169215976Sjmallett uint64_t pocas : 1; /**< Enable the Posted CAS feature of DDR3. 1170215976Sjmallett This bit should be set in conjunction with DFM_MODEREG_PARAMS[AL] */ 1171215976Sjmallett uint64_t ddr2t : 1; /**< Turn on the DDR 2T mode. 2 cycle window for CMD and 1172215976Sjmallett address. This mode helps relieve setup time pressure 1173215976Sjmallett on the Address and command bus which nominally have 1174215976Sjmallett a very large fanout. Please refer to Micron's tech 1175215976Sjmallett note tn_47_01 titled "DDR2-533 Memory Design Guide 1176215976Sjmallett for Two Dimm Unbuffered Systems" for physical details. */ 1177215976Sjmallett uint64_t bwcnt : 1; /**< Bus utilization counter Clear. 1178215976Sjmallett Clears the DFM_OPS_CNT, DFM_IFB_CNT, and 1179215976Sjmallett DFM_FCLK_CNT registers. SW should first write this 1180215976Sjmallett field to a one, then write this field to a zero to 1181215976Sjmallett clear the CSR's. */ 1182215976Sjmallett uint64_t rdimm_ena : 1; /**< Must be zero. */ 1183215976Sjmallett#else 1184215976Sjmallett uint64_t rdimm_ena : 1; 1185215976Sjmallett uint64_t bwcnt : 1; 1186215976Sjmallett uint64_t ddr2t : 1; 1187215976Sjmallett uint64_t pocas : 1; 1188215976Sjmallett uint64_t fprch2 : 2; 1189215976Sjmallett uint64_t throttle_rd : 1; 1190215976Sjmallett uint64_t throttle_wr : 1; 1191215976Sjmallett uint64_t inorder_rd : 1; 1192215976Sjmallett uint64_t inorder_wr : 1; 1193215976Sjmallett uint64_t elev_prio_dis : 1; 1194215976Sjmallett uint64_t nxm_write_en : 1; 1195215976Sjmallett uint64_t max_write_batch : 4; 1196215976Sjmallett uint64_t xor_bank : 1; 1197215976Sjmallett uint64_t auto_fclkdis : 1; 1198215976Sjmallett uint64_t int_zqcs_dis : 1; 1199215976Sjmallett uint64_t ext_zqcs_dis : 1; 1200215976Sjmallett uint64_t bprch : 2; 1201215976Sjmallett uint64_t wodt_bprch : 1; 1202215976Sjmallett uint64_t rodt_bprch : 1; 1203215976Sjmallett uint64_t reserved_24_63 : 40; 1204215976Sjmallett#endif 1205215976Sjmallett } s; 1206215976Sjmallett struct cvmx_dfm_control_s cn63xx; 1207232812Sjmallett struct cvmx_dfm_control_cn63xxp1 { 1208232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1209215976Sjmallett uint64_t reserved_22_63 : 42; 1210215976Sjmallett uint64_t bprch : 2; /**< Back Porch Enable: When set, the turn-on time for 1211215976Sjmallett the default DDR_DQ/DQS drivers is delayed an additional BPRCH FCLK 1212215976Sjmallett cycles. 1213215976Sjmallett 00 = 0 fclks 1214215976Sjmallett 01 = 1 fclks 1215215976Sjmallett 10 = 2 fclks 1216215976Sjmallett 11 = 3 fclks */ 1217215976Sjmallett uint64_t ext_zqcs_dis : 1; /**< Disable (external) auto-zqcs calibration 1218215976Sjmallett When clear, DFM runs external ZQ calibration */ 1219215976Sjmallett uint64_t int_zqcs_dis : 1; /**< Disable (internal) auto-zqcs calibration 1220215976Sjmallett When counter is re-enabled, ZQCS is run immediately, 1221215976Sjmallett and then every DFM_CONFIG[REF_ZQCS_INT] fclk cycles. */ 1222215976Sjmallett uint64_t auto_fclkdis : 1; /**< When 1, DFM will automatically shut off its internal 1223215976Sjmallett clock to conserve power when there is no traffic. Note 1224215976Sjmallett that this has no effect on the DDR3 PHY and pads clocks. */ 1225215976Sjmallett uint64_t xor_bank : 1; /**< Must be zero. */ 1226215976Sjmallett uint64_t max_write_batch : 4; /**< Must be set to value 8 */ 1227215976Sjmallett uint64_t nxm_write_en : 1; /**< Must be zero. */ 1228215976Sjmallett uint64_t elev_prio_dis : 1; /**< Must be zero. */ 1229215976Sjmallett uint64_t inorder_wr : 1; /**< Must be zero. */ 1230215976Sjmallett uint64_t inorder_rd : 1; /**< Must be zero. */ 1231215976Sjmallett uint64_t throttle_wr : 1; /**< When set, use at most one IFB for writes 1232215976Sjmallett THROTTLE_RD and THROTTLE_WR must be the same value. */ 1233215976Sjmallett uint64_t throttle_rd : 1; /**< When set, use at most one IFB for reads 1234215976Sjmallett THROTTLE_RD and THROTTLE_WR must be the same value. */ 1235215976Sjmallett uint64_t fprch2 : 2; /**< Front Porch Enable: When set, the turn-off 1236215976Sjmallett time for the default DDR_DQ/DQS drivers is FPRCH2 fclks earlier. 1237215976Sjmallett 00 = 0 fclks 1238215976Sjmallett 01 = 1 fclks 1239215976Sjmallett 10 = 2 fclks 1240215976Sjmallett 11 = RESERVED */ 1241215976Sjmallett uint64_t pocas : 1; /**< Enable the Posted CAS feature of DDR3. 1242215976Sjmallett This bit should be set in conjunction with DFM_MODEREG_PARAMS[AL] */ 1243215976Sjmallett uint64_t ddr2t : 1; /**< Turn on the DDR 2T mode. 2 cycle window for CMD and 1244215976Sjmallett address. This mode helps relieve setup time pressure 1245215976Sjmallett on the Address and command bus which nominally have 1246215976Sjmallett a very large fanout. Please refer to Micron's tech 1247215976Sjmallett note tn_47_01 titled "DDR2-533 Memory Design Guide 1248215976Sjmallett for Two Dimm Unbuffered Systems" for physical details. */ 1249215976Sjmallett uint64_t bwcnt : 1; /**< Bus utilization counter Clear. 1250215976Sjmallett Clears the DFM_OPS_CNT, DFM_IFB_CNT, and 1251215976Sjmallett DFM_FCLK_CNT registers. SW should first write this 1252215976Sjmallett field to a one, then write this field to a zero to 1253215976Sjmallett clear the CSR's. */ 1254215976Sjmallett uint64_t rdimm_ena : 1; /**< Must be zero. */ 1255215976Sjmallett#else 1256215976Sjmallett uint64_t rdimm_ena : 1; 1257215976Sjmallett uint64_t bwcnt : 1; 1258215976Sjmallett uint64_t ddr2t : 1; 1259215976Sjmallett uint64_t pocas : 1; 1260215976Sjmallett uint64_t fprch2 : 2; 1261215976Sjmallett uint64_t throttle_rd : 1; 1262215976Sjmallett uint64_t throttle_wr : 1; 1263215976Sjmallett uint64_t inorder_rd : 1; 1264215976Sjmallett uint64_t inorder_wr : 1; 1265215976Sjmallett uint64_t elev_prio_dis : 1; 1266215976Sjmallett uint64_t nxm_write_en : 1; 1267215976Sjmallett uint64_t max_write_batch : 4; 1268215976Sjmallett uint64_t xor_bank : 1; 1269215976Sjmallett uint64_t auto_fclkdis : 1; 1270215976Sjmallett uint64_t int_zqcs_dis : 1; 1271215976Sjmallett uint64_t ext_zqcs_dis : 1; 1272215976Sjmallett uint64_t bprch : 2; 1273215976Sjmallett uint64_t reserved_22_63 : 42; 1274215976Sjmallett#endif 1275215976Sjmallett } cn63xxp1; 1276232812Sjmallett struct cvmx_dfm_control_s cn66xx; 1277215976Sjmallett}; 1278215976Sjmalletttypedef union cvmx_dfm_control cvmx_dfm_control_t; 1279215976Sjmallett 1280215976Sjmallett/** 1281215976Sjmallett * cvmx_dfm_dll_ctl2 1282215976Sjmallett * 1283215976Sjmallett * DFM_DLL_CTL2 = DFM (Octeon) DLL control and FCLK reset 1284215976Sjmallett * 1285215976Sjmallett * 1286215976Sjmallett * Notes: 1287215976Sjmallett * DLL Bringup sequence: 1288215976Sjmallett * 1. If not done already, set DFM_DLL_CTL2 = 0, except when DFM_DLL_CTL2[DRESET] = 1. 1289215976Sjmallett * 2. Write 1 to DFM_DLL_CTL2[DLL_BRINGUP] 1290215976Sjmallett * 3. Wait for 10 FCLK cycles, then write 1 to DFM_DLL_CTL2[QUAD_DLL_ENA]. It may not be feasible to count 10 FCLK cycles, but the 1291215976Sjmallett * idea is to configure the delay line into DLL mode by asserting DLL_BRING_UP earlier than [QUAD_DLL_ENA], even if it is one 1292215976Sjmallett * cycle early. DFM_DLL_CTL2[QUAD_DLL_ENA] must not change after this point without restarting the DFM and/or DRESET initialization 1293215976Sjmallett * sequence. 1294215976Sjmallett * 4. Read L2D_BST0 and wait for the result. (L2D_BST0 is subject to change depending on how it called in o63. It is still ok to go 1295215976Sjmallett * without step 4, since step 5 has enough time) 1296215976Sjmallett * 5. Wait 10 us. 1297215976Sjmallett * 6. Write 0 to DFM_DLL_CTL2[DLL_BRINGUP]. DFM_DLL_CTL2[DLL_BRINGUP] must not change after this point without restarting the DFM 1298215976Sjmallett * and/or DRESET initialization sequence. 1299215976Sjmallett * 7. Read L2D_BST0 and wait for the result. (same as step 4, but the idea here is the wait some time before going to step 8, even it 1300215976Sjmallett * is one cycle is fine) 1301215976Sjmallett * 8. Write 0 to DFM_DLL_CTL2[DRESET]. DFM_DLL_CTL2[DRESET] must not change after this point without restarting the DFM and/or 1302215976Sjmallett * DRESET initialization sequence. 1303215976Sjmallett */ 1304232812Sjmallettunion cvmx_dfm_dll_ctl2 { 1305215976Sjmallett uint64_t u64; 1306232812Sjmallett struct cvmx_dfm_dll_ctl2_s { 1307232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1308215976Sjmallett uint64_t reserved_15_63 : 49; 1309215976Sjmallett uint64_t dll_bringup : 1; /**< DLL Bringup */ 1310215976Sjmallett uint64_t dreset : 1; /**< Fclk domain reset. The reset signal that is used by the 1311215976Sjmallett Fclk domain is (DRESET || ECLK_RESET). */ 1312215976Sjmallett uint64_t quad_dll_ena : 1; /**< DLL Enable */ 1313215976Sjmallett uint64_t byp_sel : 4; /**< Bypass select 1314215976Sjmallett 0000 : no byte 1315215976Sjmallett 0001 : byte 0 1316215976Sjmallett - ... 1317215976Sjmallett 1001 : byte 8 1318215976Sjmallett 1010 : all bytes 1319215976Sjmallett 1011-1111 : Reserved */ 1320215976Sjmallett uint64_t byp_setting : 8; /**< Bypass setting 1321215976Sjmallett DDR3-1600: 00100010 1322215976Sjmallett DDR3-1333: 00110010 1323215976Sjmallett DDR3-1066: 01001011 1324215976Sjmallett DDR3-800 : 01110101 1325215976Sjmallett DDR3-667 : 10010110 1326215976Sjmallett DDR3-600 : 10101100 */ 1327215976Sjmallett#else 1328215976Sjmallett uint64_t byp_setting : 8; 1329215976Sjmallett uint64_t byp_sel : 4; 1330215976Sjmallett uint64_t quad_dll_ena : 1; 1331215976Sjmallett uint64_t dreset : 1; 1332215976Sjmallett uint64_t dll_bringup : 1; 1333215976Sjmallett uint64_t reserved_15_63 : 49; 1334215976Sjmallett#endif 1335215976Sjmallett } s; 1336215976Sjmallett struct cvmx_dfm_dll_ctl2_s cn63xx; 1337215976Sjmallett struct cvmx_dfm_dll_ctl2_s cn63xxp1; 1338232812Sjmallett struct cvmx_dfm_dll_ctl2_s cn66xx; 1339215976Sjmallett}; 1340215976Sjmalletttypedef union cvmx_dfm_dll_ctl2 cvmx_dfm_dll_ctl2_t; 1341215976Sjmallett 1342215976Sjmallett/** 1343215976Sjmallett * cvmx_dfm_dll_ctl3 1344215976Sjmallett * 1345215976Sjmallett * DFM_DLL_CTL3 = DFM DLL control and FCLK reset 1346215976Sjmallett * 1347215976Sjmallett */ 1348232812Sjmallettunion cvmx_dfm_dll_ctl3 { 1349215976Sjmallett uint64_t u64; 1350232812Sjmallett struct cvmx_dfm_dll_ctl3_s { 1351232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1352215976Sjmallett uint64_t reserved_29_63 : 35; 1353215976Sjmallett uint64_t dll_fast : 1; /**< DLL lock 1354215976Sjmallett 0 = DLL locked */ 1355215976Sjmallett uint64_t dll90_setting : 8; /**< Encoded DLL settings. Works in conjuction with 1356215976Sjmallett DLL90_BYTE_SEL */ 1357215976Sjmallett uint64_t fine_tune_mode : 1; /**< Fine Tune Mode */ 1358215976Sjmallett uint64_t dll_mode : 1; /**< DLL Mode */ 1359215976Sjmallett uint64_t dll90_byte_sel : 4; /**< Observe DLL settings for selected byte 1360215976Sjmallett 0001 : byte 0 1361215976Sjmallett - ... 1362215976Sjmallett 1001 : byte 8 1363215976Sjmallett 0000,1010-1111 : Reserved */ 1364215976Sjmallett uint64_t offset_ena : 1; /**< Offset enable 1365215976Sjmallett 0 = disable 1366215976Sjmallett 1 = enable */ 1367215976Sjmallett uint64_t load_offset : 1; /**< Load offset 1368215976Sjmallett 0 : disable 1369215976Sjmallett 1 : load (generates a 1 cycle pulse to the PHY) 1370215976Sjmallett This register is oneshot and clears itself each time 1371215976Sjmallett it is set */ 1372215976Sjmallett uint64_t mode_sel : 2; /**< Mode select 1373215976Sjmallett 00 : reset 1374215976Sjmallett 01 : write 1375215976Sjmallett 10 : read 1376215976Sjmallett 11 : write & read */ 1377215976Sjmallett uint64_t byte_sel : 4; /**< Byte select 1378215976Sjmallett 0000 : no byte 1379215976Sjmallett 0001 : byte 0 1380215976Sjmallett - ... 1381215976Sjmallett 1001 : byte 8 1382215976Sjmallett 1010 : all bytes 1383215976Sjmallett 1011-1111 : Reserved */ 1384215976Sjmallett uint64_t offset : 6; /**< Write/read offset setting 1385215976Sjmallett [4:0] : offset 1386215976Sjmallett [5] : 0 = increment, 1 = decrement 1387215976Sjmallett Not a 2's complement value */ 1388215976Sjmallett#else 1389215976Sjmallett uint64_t offset : 6; 1390215976Sjmallett uint64_t byte_sel : 4; 1391215976Sjmallett uint64_t mode_sel : 2; 1392215976Sjmallett uint64_t load_offset : 1; 1393215976Sjmallett uint64_t offset_ena : 1; 1394215976Sjmallett uint64_t dll90_byte_sel : 4; 1395215976Sjmallett uint64_t dll_mode : 1; 1396215976Sjmallett uint64_t fine_tune_mode : 1; 1397215976Sjmallett uint64_t dll90_setting : 8; 1398215976Sjmallett uint64_t dll_fast : 1; 1399215976Sjmallett uint64_t reserved_29_63 : 35; 1400215976Sjmallett#endif 1401215976Sjmallett } s; 1402215976Sjmallett struct cvmx_dfm_dll_ctl3_s cn63xx; 1403215976Sjmallett struct cvmx_dfm_dll_ctl3_s cn63xxp1; 1404232812Sjmallett struct cvmx_dfm_dll_ctl3_s cn66xx; 1405215976Sjmallett}; 1406215976Sjmalletttypedef union cvmx_dfm_dll_ctl3 cvmx_dfm_dll_ctl3_t; 1407215976Sjmallett 1408215976Sjmallett/** 1409215976Sjmallett * cvmx_dfm_fclk_cnt 1410215976Sjmallett * 1411215976Sjmallett * DFM_FCLK_CNT = Performance Counters 1412215976Sjmallett * 1413215976Sjmallett */ 1414232812Sjmallettunion cvmx_dfm_fclk_cnt { 1415215976Sjmallett uint64_t u64; 1416232812Sjmallett struct cvmx_dfm_fclk_cnt_s { 1417232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1418215976Sjmallett uint64_t fclkcnt : 64; /**< Performance Counter that counts fclks 1419215976Sjmallett 64-bit counter. */ 1420215976Sjmallett#else 1421215976Sjmallett uint64_t fclkcnt : 64; 1422215976Sjmallett#endif 1423215976Sjmallett } s; 1424215976Sjmallett struct cvmx_dfm_fclk_cnt_s cn63xx; 1425215976Sjmallett struct cvmx_dfm_fclk_cnt_s cn63xxp1; 1426232812Sjmallett struct cvmx_dfm_fclk_cnt_s cn66xx; 1427215976Sjmallett}; 1428215976Sjmalletttypedef union cvmx_dfm_fclk_cnt cvmx_dfm_fclk_cnt_t; 1429215976Sjmallett 1430215976Sjmallett/** 1431215976Sjmallett * cvmx_dfm_fnt_bist 1432215976Sjmallett * 1433215976Sjmallett * DFM_FNT_BIST = DFM Front BIST Status 1434215976Sjmallett * 1435215976Sjmallett * This register contains Bist Status for DFM Front 1436215976Sjmallett */ 1437232812Sjmallettunion cvmx_dfm_fnt_bist { 1438215976Sjmallett uint64_t u64; 1439232812Sjmallett struct cvmx_dfm_fnt_bist_s { 1440232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1441215976Sjmallett uint64_t reserved_5_63 : 59; 1442215976Sjmallett uint64_t cab : 1; /**< Bist Results for CAB RAM 1443215976Sjmallett - 0: GOOD (or bist in progress/never run) 1444215976Sjmallett - 1: BAD */ 1445215976Sjmallett uint64_t mrq : 1; /**< Bist Results for MRQ RAM 1446215976Sjmallett - 0: GOOD (or bist in progress/never run) 1447215976Sjmallett - 1: BAD */ 1448215976Sjmallett uint64_t mff : 1; /**< Bist Results for MFF RAM 1449215976Sjmallett - 0: GOOD (or bist in progress/never run) 1450215976Sjmallett - 1: BAD */ 1451215976Sjmallett uint64_t rpb : 1; /**< Bist Results for RPB RAM 1452215976Sjmallett - 0: GOOD (or bist in progress/never run) 1453215976Sjmallett - 1: BAD */ 1454215976Sjmallett uint64_t mwb : 1; /**< Bist Results for MWB RAM 1455215976Sjmallett - 0: GOOD (or bist in progress/never run) 1456215976Sjmallett - 1: BAD */ 1457215976Sjmallett#else 1458215976Sjmallett uint64_t mwb : 1; 1459215976Sjmallett uint64_t rpb : 1; 1460215976Sjmallett uint64_t mff : 1; 1461215976Sjmallett uint64_t mrq : 1; 1462215976Sjmallett uint64_t cab : 1; 1463215976Sjmallett uint64_t reserved_5_63 : 59; 1464215976Sjmallett#endif 1465215976Sjmallett } s; 1466215976Sjmallett struct cvmx_dfm_fnt_bist_s cn63xx; 1467232812Sjmallett struct cvmx_dfm_fnt_bist_cn63xxp1 { 1468232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1469215976Sjmallett uint64_t reserved_4_63 : 60; 1470215976Sjmallett uint64_t mrq : 1; /**< Bist Results for MRQ RAM 1471215976Sjmallett - 0: GOOD (or bist in progress/never run) 1472215976Sjmallett - 1: BAD */ 1473215976Sjmallett uint64_t mff : 1; /**< Bist Results for MFF RAM 1474215976Sjmallett - 0: GOOD (or bist in progress/never run) 1475215976Sjmallett - 1: BAD */ 1476215976Sjmallett uint64_t rpb : 1; /**< Bist Results for RPB RAM 1477215976Sjmallett - 0: GOOD (or bist in progress/never run) 1478215976Sjmallett - 1: BAD */ 1479215976Sjmallett uint64_t mwb : 1; /**< Bist Results for MWB RAM 1480215976Sjmallett - 0: GOOD (or bist in progress/never run) 1481215976Sjmallett - 1: BAD */ 1482215976Sjmallett#else 1483215976Sjmallett uint64_t mwb : 1; 1484215976Sjmallett uint64_t rpb : 1; 1485215976Sjmallett uint64_t mff : 1; 1486215976Sjmallett uint64_t mrq : 1; 1487215976Sjmallett uint64_t reserved_4_63 : 60; 1488215976Sjmallett#endif 1489215976Sjmallett } cn63xxp1; 1490232812Sjmallett struct cvmx_dfm_fnt_bist_s cn66xx; 1491215976Sjmallett}; 1492215976Sjmalletttypedef union cvmx_dfm_fnt_bist cvmx_dfm_fnt_bist_t; 1493215976Sjmallett 1494215976Sjmallett/** 1495215976Sjmallett * cvmx_dfm_fnt_ctl 1496215976Sjmallett * 1497215976Sjmallett * Specify the RSL base addresses for the block 1498215976Sjmallett * 1499215976Sjmallett * DFM_FNT_CTL = DFM Front Control Register 1500215976Sjmallett * 1501215976Sjmallett * This register contains control registers for the DFM Front Section of Logic. 1502215976Sjmallett */ 1503232812Sjmallettunion cvmx_dfm_fnt_ctl { 1504215976Sjmallett uint64_t u64; 1505232812Sjmallett struct cvmx_dfm_fnt_ctl_s { 1506232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1507215976Sjmallett uint64_t reserved_4_63 : 60; 1508215976Sjmallett uint64_t sbe_ena : 1; /**< If SBE_ENA=1 & RECC_ENA=1 then all single bit errors 1509215976Sjmallett which have been detected/corrected during GWALK reads, 1510215976Sjmallett will be reported through RWORD0[REA]=ERR code in system 1511215976Sjmallett memory at the conclusion of the DFA instruction. 1512215976Sjmallett SWNOTE: The application user may wish to report single 1513215976Sjmallett bit errors that were corrected through the 1514215976Sjmallett RWORD0[REA]=ERR codeword. 1515215976Sjmallett NOTE: This DOES NOT effect the reporting of SBEs in 1516215976Sjmallett DFM_FNT_STAT[SBE] (which were corrected if RECC_ENA=1). 1517215976Sjmallett This bit is only here for applications which 'MAY' want 1518215976Sjmallett to be alerted with an ERR completion code if there were 1519215976Sjmallett SBEs that were auto-corrected during GWALK instructions. 1520215976Sjmallett Recap: If there is a SBE and SBE_ENA==1, the "err" field 1521215976Sjmallett in the data returned to DFA will be set. If SBE_ENA==0, 1522215976Sjmallett the "err" is always 0 when there is a SBE; however, 1523215976Sjmallett regardless of SBE_ENA, DBE will cause "err" to be 1. */ 1524215976Sjmallett uint64_t wecc_ena : 1; /**< If WECC_ENA=1, HW will auto-generate(overwrite) the 10b 1525215976Sjmallett OWECC codeword during Memory Writes sourced by 1526215976Sjmallett 1) DFA MLOAD instructions, or by 2) NCB-Direct CSR 1527215976Sjmallett mode writes to DFA memory space. The HW will insert 1528215976Sjmallett the 10b OWECC inband into OW-DATA[127:118]. 1529215976Sjmallett If WECC_ENA=0, SW is responsible for generating the 1530215976Sjmallett 10b OWECC codeword inband in the upper OW-data[127:118] 1531215976Sjmallett during Memory writes (to provide SEC/DED coverage for 1532215976Sjmallett the data during subsequent Memory reads-see RECC_ENA). */ 1533215976Sjmallett uint64_t recc_ena : 1; /**< If RECC_ENA=1, all DFA memory reads sourced by 1) DFA 1534215976Sjmallett GWALK instructions or by 2) NCB-Direct CSR mode reads 1535215976Sjmallett to DFA memory space, will be protected by an inband 10b 1536215976Sjmallett OWECC SEC/DED codeword. The inband OW-DATA[127:118] 1537215976Sjmallett represents the inband OWECC codeword which offers single 1538215976Sjmallett bit error correction(SEC)/double bit error detection(DED). 1539215976Sjmallett [see also DFM_FNT_STAT[SBE,DBE,FADR,FSYN] status fields]. 1540215976Sjmallett The FSYN field contains an encoded value which determines 1541215976Sjmallett which bit was corrected(for SBE) or detected(for DBE) to 1542215976Sjmallett help in bit isolation of the error. 1543215976Sjmallett SW NOTE: If RECC_ENA=1: An NCB-Direct CSR mode read of the 1544215976Sjmallett upper QW in memory will return ZEROES in the upper 10b of the 1545215976Sjmallett data word. 1546215976Sjmallett If RECC_ENA=0: An NCB-Direct CSR mode read of the upper QW in 1547215976Sjmallett memory will return the RAW 64bits from memory. During memory 1548215976Sjmallett debug, writing RECC_ENA=0 provides visibility into the raw ECC 1549215976Sjmallett stored in memory at that time. */ 1550215976Sjmallett uint64_t dfr_ena : 1; /**< DFM Memory Interface Enable 1551215976Sjmallett The DFM powers up with the DDR3 interface disabled. 1552215976Sjmallett If the DFA function is required, then after poweron 1553215976Sjmallett software configures a stable DFM DDR3 memory clock 1554215976Sjmallett (see: LMCx_DDR_PLL_CTL[DFM_PS_EN, DFM_DIV_RESET]), 1555215976Sjmallett the DFM DDR3 memory interface can be enabled. 1556215976Sjmallett When disabled (DFR_ENA=0), all DFM DDR3 memory 1557215976Sjmallett output and bidirectional pins will be tristated. 1558215976Sjmallett SW NOTE: The DFR_ENA=1 write MUST occur sometime after 1559215976Sjmallett the DFM is brought out of reset (ie: after the 1560215976Sjmallett DFM_DLL_CTL2[DRESET]=0 write). */ 1561215976Sjmallett#else 1562215976Sjmallett uint64_t dfr_ena : 1; 1563215976Sjmallett uint64_t recc_ena : 1; 1564215976Sjmallett uint64_t wecc_ena : 1; 1565215976Sjmallett uint64_t sbe_ena : 1; 1566215976Sjmallett uint64_t reserved_4_63 : 60; 1567215976Sjmallett#endif 1568215976Sjmallett } s; 1569215976Sjmallett struct cvmx_dfm_fnt_ctl_s cn63xx; 1570215976Sjmallett struct cvmx_dfm_fnt_ctl_s cn63xxp1; 1571232812Sjmallett struct cvmx_dfm_fnt_ctl_s cn66xx; 1572215976Sjmallett}; 1573215976Sjmalletttypedef union cvmx_dfm_fnt_ctl cvmx_dfm_fnt_ctl_t; 1574215976Sjmallett 1575215976Sjmallett/** 1576215976Sjmallett * cvmx_dfm_fnt_iena 1577215976Sjmallett * 1578215976Sjmallett * DFM_FNT_IENA = DFM Front Interrupt Enable Mask 1579215976Sjmallett * 1580215976Sjmallett * This register contains error interrupt enable information for the DFM Front Section of Logic. 1581215976Sjmallett */ 1582232812Sjmallettunion cvmx_dfm_fnt_iena { 1583215976Sjmallett uint64_t u64; 1584232812Sjmallett struct cvmx_dfm_fnt_iena_s { 1585232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1586215976Sjmallett uint64_t reserved_2_63 : 62; 1587215976Sjmallett uint64_t dbe_intena : 1; /**< OWECC Double Error Detected(DED) Interrupt Enable 1588215976Sjmallett When set, the memory controller raises a processor 1589215976Sjmallett interrupt on detecting an uncorrectable double bit 1590215976Sjmallett OWECC during a memory read. */ 1591215976Sjmallett uint64_t sbe_intena : 1; /**< OWECC Single Error Corrected(SEC) Interrupt Enable 1592215976Sjmallett When set, the memory controller raises a processor 1593215976Sjmallett interrupt on detecting a correctable single bit 1594215976Sjmallett OWECC error which was corrected during a memory 1595215976Sjmallett read. */ 1596215976Sjmallett#else 1597215976Sjmallett uint64_t sbe_intena : 1; 1598215976Sjmallett uint64_t dbe_intena : 1; 1599215976Sjmallett uint64_t reserved_2_63 : 62; 1600215976Sjmallett#endif 1601215976Sjmallett } s; 1602215976Sjmallett struct cvmx_dfm_fnt_iena_s cn63xx; 1603215976Sjmallett struct cvmx_dfm_fnt_iena_s cn63xxp1; 1604232812Sjmallett struct cvmx_dfm_fnt_iena_s cn66xx; 1605215976Sjmallett}; 1606215976Sjmalletttypedef union cvmx_dfm_fnt_iena cvmx_dfm_fnt_iena_t; 1607215976Sjmallett 1608215976Sjmallett/** 1609215976Sjmallett * cvmx_dfm_fnt_sclk 1610215976Sjmallett * 1611215976Sjmallett * DFM_FNT_SCLK = DFM Front SCLK Control Register 1612215976Sjmallett * 1613215976Sjmallett * This register contains control registers for the DFM Front Section of Logic. 1614215976Sjmallett * NOTE: This register is in USCLK domain and is ised to enable the conditional SCLK grid, as well as 1615215976Sjmallett * to start a software BiST sequence for the DFM sub-block. (note: the DFM has conditional clocks which 1616215976Sjmallett * prevent BiST to run under reset automatically). 1617215976Sjmallett */ 1618232812Sjmallettunion cvmx_dfm_fnt_sclk { 1619215976Sjmallett uint64_t u64; 1620232812Sjmallett struct cvmx_dfm_fnt_sclk_s { 1621232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1622215976Sjmallett uint64_t reserved_3_63 : 61; 1623215976Sjmallett uint64_t clear_bist : 1; /**< When START_BIST is written 0->1, if CLEAR_BIST=1, all 1624215976Sjmallett previous BiST state is cleared. 1625215976Sjmallett NOTES: 1626215976Sjmallett 1) CLEAR_BIST must be written to 1 before START_BIST 1627215976Sjmallett is written to 1 using a separate CSR write. 1628215976Sjmallett 2) CLEAR_BIST must not be changed after writing START_BIST 1629215976Sjmallett 0->1 until the BIST operation completes. */ 1630215976Sjmallett uint64_t bist_start : 1; /**< When software writes BIST_START=0->1, a BiST is executed 1631215976Sjmallett for the DFM sub-block. 1632215976Sjmallett NOTES: 1633215976Sjmallett 1) This bit should only be written after BOTH sclk 1634215976Sjmallett and fclk have been enabled by software and are stable 1635215976Sjmallett (see: DFM_FNT_SCLK[SCLKDIS] and instructions on how to 1636215976Sjmallett enable the DFM DDR3 memory (fclk) - which requires LMC 1637215976Sjmallett PLL init, DFM clock divider and proper DFM DLL 1638215976Sjmallett initialization sequence). */ 1639215976Sjmallett uint64_t sclkdis : 1; /**< DFM sclk disable Source 1640215976Sjmallett When SET, the DFM sclk are disabled (to conserve overall 1641215976Sjmallett chip clocking power when the DFM function is not used). 1642215976Sjmallett NOTE: This should only be written to a different value 1643215976Sjmallett during power-on SW initialization. */ 1644215976Sjmallett#else 1645215976Sjmallett uint64_t sclkdis : 1; 1646215976Sjmallett uint64_t bist_start : 1; 1647215976Sjmallett uint64_t clear_bist : 1; 1648215976Sjmallett uint64_t reserved_3_63 : 61; 1649215976Sjmallett#endif 1650215976Sjmallett } s; 1651215976Sjmallett struct cvmx_dfm_fnt_sclk_s cn63xx; 1652215976Sjmallett struct cvmx_dfm_fnt_sclk_s cn63xxp1; 1653232812Sjmallett struct cvmx_dfm_fnt_sclk_s cn66xx; 1654215976Sjmallett}; 1655215976Sjmalletttypedef union cvmx_dfm_fnt_sclk cvmx_dfm_fnt_sclk_t; 1656215976Sjmallett 1657215976Sjmallett/** 1658215976Sjmallett * cvmx_dfm_fnt_stat 1659215976Sjmallett * 1660215976Sjmallett * DFM_FNT_STAT = DFM Front Status Register 1661215976Sjmallett * 1662215976Sjmallett * This register contains error status information for the DFM Front Section of Logic. 1663215976Sjmallett */ 1664232812Sjmallettunion cvmx_dfm_fnt_stat { 1665215976Sjmallett uint64_t u64; 1666232812Sjmallett struct cvmx_dfm_fnt_stat_s { 1667232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1668215976Sjmallett uint64_t reserved_42_63 : 22; 1669215976Sjmallett uint64_t fsyn : 10; /**< Failing Syndrome 1670215976Sjmallett If SBE_ERR=1, the FSYN code determines which bit was 1671215976Sjmallett corrected during the OWECC check/correct. 1672215976Sjmallett NOTE: If both DBE_ERR/SBE_ERR are set, the DBE_ERR has 1673215976Sjmallett higher priority and FSYN captured will always be for the 1674215976Sjmallett DBE_ERR detected. 1675215976Sjmallett The FSYN is "locked down" when either DBE_ERR/SBE_ERR 1676215976Sjmallett are detected (until these bits are cleared (W1C)). 1677215976Sjmallett However, if an SBE_ERR occurs first, followed by a 1678215976Sjmallett DBE_ERR, the higher priority DBE_ERR will re-capture 1679215976Sjmallett the FSYN for the higher priority error case. */ 1680215976Sjmallett uint64_t fadr : 28; /**< Failing Memory octaword address 1681215976Sjmallett If either SBE_ERR or DBE_ERR are set, the FADR 1682215976Sjmallett represents the failing octaword address. 1683215976Sjmallett NOTE: If both DBE_ERR/SBE_ERR are set, the DBE_ERR has 1684215976Sjmallett higher priority and the FADR captured will always be 1685215976Sjmallett with the DBE_ERR detected. 1686215976Sjmallett The FADR is "locked down" when either DBE_ERR/SBE_ERR 1687215976Sjmallett are detected (until these bits are cleared (W1C)). 1688215976Sjmallett However, if an SBE_ERR occurs first, followed by a 1689215976Sjmallett DBE_ERR, the higher priority DBE_ERR will re-capture 1690215976Sjmallett the FADR for the higher priority error case. */ 1691215976Sjmallett uint64_t reserved_2_3 : 2; 1692215976Sjmallett uint64_t dbe_err : 1; /**< Double bit error detected(uncorrectable) during 1693215976Sjmallett Memory Read. 1694215976Sjmallett Write of 1 will clear the corresponding error bit */ 1695215976Sjmallett uint64_t sbe_err : 1; /**< Single bit error detected(corrected) during 1696215976Sjmallett Memory Read. 1697215976Sjmallett Write of 1 will clear the corresponding error bit */ 1698215976Sjmallett#else 1699215976Sjmallett uint64_t sbe_err : 1; 1700215976Sjmallett uint64_t dbe_err : 1; 1701215976Sjmallett uint64_t reserved_2_3 : 2; 1702215976Sjmallett uint64_t fadr : 28; 1703215976Sjmallett uint64_t fsyn : 10; 1704215976Sjmallett uint64_t reserved_42_63 : 22; 1705215976Sjmallett#endif 1706215976Sjmallett } s; 1707215976Sjmallett struct cvmx_dfm_fnt_stat_s cn63xx; 1708215976Sjmallett struct cvmx_dfm_fnt_stat_s cn63xxp1; 1709232812Sjmallett struct cvmx_dfm_fnt_stat_s cn66xx; 1710215976Sjmallett}; 1711215976Sjmalletttypedef union cvmx_dfm_fnt_stat cvmx_dfm_fnt_stat_t; 1712215976Sjmallett 1713215976Sjmallett/** 1714215976Sjmallett * cvmx_dfm_ifb_cnt 1715215976Sjmallett * 1716215976Sjmallett * DFM_IFB_CNT = Performance Counters 1717215976Sjmallett * 1718215976Sjmallett */ 1719232812Sjmallettunion cvmx_dfm_ifb_cnt { 1720215976Sjmallett uint64_t u64; 1721232812Sjmallett struct cvmx_dfm_ifb_cnt_s { 1722232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1723215976Sjmallett uint64_t ifbcnt : 64; /**< Performance Counter 1724215976Sjmallett 64-bit counter that increments every 1725232812Sjmallett cycle there is something in the in-flight buffer. 1726232812Sjmallett Before using, clear counter via DFM_CONTROL.BWCNT. */ 1727215976Sjmallett#else 1728215976Sjmallett uint64_t ifbcnt : 64; 1729215976Sjmallett#endif 1730215976Sjmallett } s; 1731215976Sjmallett struct cvmx_dfm_ifb_cnt_s cn63xx; 1732215976Sjmallett struct cvmx_dfm_ifb_cnt_s cn63xxp1; 1733232812Sjmallett struct cvmx_dfm_ifb_cnt_s cn66xx; 1734215976Sjmallett}; 1735215976Sjmalletttypedef union cvmx_dfm_ifb_cnt cvmx_dfm_ifb_cnt_t; 1736215976Sjmallett 1737215976Sjmallett/** 1738215976Sjmallett * cvmx_dfm_modereg_params0 1739215976Sjmallett * 1740215976Sjmallett * Notes: 1741215976Sjmallett * These parameters are written into the DDR3 MR0, MR1, MR2 and MR3 registers. 1742215976Sjmallett * 1743215976Sjmallett */ 1744232812Sjmallettunion cvmx_dfm_modereg_params0 { 1745215976Sjmallett uint64_t u64; 1746232812Sjmallett struct cvmx_dfm_modereg_params0_s { 1747232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1748215976Sjmallett uint64_t reserved_25_63 : 39; 1749215976Sjmallett uint64_t ppd : 1; /**< DLL Control for precharge powerdown 1750215976Sjmallett 0 = Slow exit (DLL off) 1751215976Sjmallett 1 = Fast exit (DLL on) 1752215976Sjmallett DFM writes this value to MR0[PPD] in the selected DDR3 parts 1753215976Sjmallett during power-up/init instruction sequencing. 1754215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK]. 1755215976Sjmallett This value must equal the MR0[PPD] value in all the DDR3 1756215976Sjmallett parts attached to all ranks during normal operation. */ 1757215976Sjmallett uint64_t wrp : 3; /**< Write recovery for auto precharge 1758215976Sjmallett Should be programmed to be equal to or greater than 1759215976Sjmallett RNDUP[tWR(ns)/tCYC(ns)] 1760232812Sjmallett 000 = 5 1761215976Sjmallett 001 = 5 1762215976Sjmallett 010 = 6 1763215976Sjmallett 011 = 7 1764215976Sjmallett 100 = 8 1765215976Sjmallett 101 = 10 1766215976Sjmallett 110 = 12 1767232812Sjmallett 111 = 14 1768215976Sjmallett DFM writes this value to MR0[WR] in the selected DDR3 parts 1769215976Sjmallett during power-up/init instruction sequencing. 1770215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK]. 1771215976Sjmallett This value must equal the MR0[WR] value in all the DDR3 1772215976Sjmallett parts attached to all ranks during normal operation. */ 1773215976Sjmallett uint64_t dllr : 1; /**< DLL Reset 1774215976Sjmallett DFM writes this value to MR0[DLL] in the selected DDR3 parts 1775215976Sjmallett during power-up/init instruction sequencing. 1776215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK]. 1777215976Sjmallett The MR0[DLL] value must be 0 in all the DDR3 1778215976Sjmallett parts attached to all ranks during normal operation. */ 1779215976Sjmallett uint64_t tm : 1; /**< Test Mode 1780215976Sjmallett DFM writes this value to MR0[TM] in the selected DDR3 parts 1781215976Sjmallett during power-up/init instruction sequencing. 1782215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK]. 1783215976Sjmallett The MR0[TM] value must be 0 in all the DDR3 1784215976Sjmallett parts attached to all ranks during normal operation. */ 1785215976Sjmallett uint64_t rbt : 1; /**< Read Burst Type 1786215976Sjmallett 1 = interleaved (fixed) 1787215976Sjmallett DFM writes this value to MR0[RBT] in the selected DDR3 parts 1788215976Sjmallett during power-up/init instruction sequencing. 1789215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK]. 1790215976Sjmallett The MR0[RBT] value must be 1 in all the DDR3 1791215976Sjmallett parts attached to all ranks during normal operation. */ 1792215976Sjmallett uint64_t cl : 4; /**< CAS Latency 1793215976Sjmallett 0010 = 5 1794215976Sjmallett 0100 = 6 1795215976Sjmallett 0110 = 7 1796215976Sjmallett 1000 = 8 1797215976Sjmallett 1010 = 9 1798215976Sjmallett 1100 = 10 1799215976Sjmallett 1110 = 11 1800232812Sjmallett 0001 = 12 1801232812Sjmallett 0011 = 13 1802232812Sjmallett 0101 = 14 1803232812Sjmallett 0111 = 15 1804232812Sjmallett 1001 = 16 1805232812Sjmallett 0000, 1011, 1101, 1111 = Reserved 1806215976Sjmallett DFM writes this value to MR0[CAS Latency / CL] in the selected DDR3 parts 1807215976Sjmallett during power-up/init instruction sequencing. 1808215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK]. 1809215976Sjmallett This value must equal the MR0[CAS Latency / CL] value in all the DDR3 1810215976Sjmallett parts attached to all ranks during normal operation. */ 1811215976Sjmallett uint64_t bl : 2; /**< Burst Length 1812215976Sjmallett 0 = 8 (fixed) 1813215976Sjmallett DFM writes this value to MR0[BL] in the selected DDR3 parts 1814215976Sjmallett during power-up/init instruction sequencing. 1815215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK]. 1816215976Sjmallett The MR0[BL] value must be 0 in all the DDR3 1817215976Sjmallett parts attached to all ranks during normal operation. */ 1818215976Sjmallett uint64_t qoff : 1; /**< Qoff Enable 1819215976Sjmallett 0 = enable 1820215976Sjmallett DFM writes this value to MR1[Qoff] in the selected DDR3 parts 1821215976Sjmallett during power-up/init and write-leveling instruction sequencing. 1822215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 1823215976Sjmallett this value to MR1[Qoff] in all DRAM parts in DFM_CONFIG[INIT_STATUS] ranks during self-refresh 1824215976Sjmallett entry and exit instruction sequences. 1825215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 1826215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. 1827215976Sjmallett The MR1[Qoff] value must be 0 in all the DDR3 1828215976Sjmallett parts attached to all ranks during normal operation. */ 1829215976Sjmallett uint64_t tdqs : 1; /**< TDQS Enable 1830215976Sjmallett 0 = disable 1831215976Sjmallett DFM writes this value to MR1[TDQS] in the selected DDR3 parts 1832215976Sjmallett during power-up/init and write-leveling instruction sequencing. 1833215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 1834215976Sjmallett this value to MR1[TDQS] in all DRAM parts in DFM_CONFIG[INIT_STATUS] ranks during self-refresh 1835215976Sjmallett entry and exit instruction sequences. 1836215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 1837215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 1838215976Sjmallett uint64_t wlev : 1; /**< Write Leveling Enable 1839215976Sjmallett 0 = disable 1840215976Sjmallett DFM writes MR1[Level]=0 in the selected DDR3 parts 1841215976Sjmallett during power-up/init and write-leveling instruction sequencing. 1842215976Sjmallett (DFM also writes MR1[Level]=1 at the beginning of a 1843215976Sjmallett write-leveling instruction sequence. Write-leveling can only be initiated via the 1844215976Sjmallett write-leveling instruction sequence.) 1845215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 1846215976Sjmallett MR1[Level]=0 in all DRAM parts in DFM_CONFIG[INIT_STATUS] ranks during self-refresh 1847215976Sjmallett entry and exit instruction sequences. 1848215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 1849215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 1850215976Sjmallett uint64_t al : 2; /**< Additive Latency 1851215976Sjmallett 00 = 0 1852215976Sjmallett 01 = CL-1 1853215976Sjmallett 10 = CL-2 1854215976Sjmallett 11 = Reserved 1855215976Sjmallett DFM writes this value to MR1[AL] in the selected DDR3 parts 1856215976Sjmallett during power-up/init and write-leveling instruction sequencing. 1857215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 1858215976Sjmallett this value to MR1[AL] in all DRAM parts in DFM_CONFIG[INIT_STATUS] ranks during self-refresh 1859215976Sjmallett entry and exit instruction sequences. 1860215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 1861215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. 1862215976Sjmallett This value must equal the MR1[AL] value in all the DDR3 1863215976Sjmallett parts attached to all ranks during normal operation. 1864215976Sjmallett See also DFM_CONTROL[POCAS]. */ 1865215976Sjmallett uint64_t dll : 1; /**< DLL Enable 1866215976Sjmallett 0 = enable 1867215976Sjmallett 1 = disable 1868215976Sjmallett DFM writes this value to MR1[DLL] in the selected DDR3 parts 1869215976Sjmallett during power-up/init and write-leveling instruction sequencing. 1870215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 1871215976Sjmallett this value to MR1[DLL] in all DRAM parts in DFM_CONFIG[INIT_STATUS] ranks during self-refresh 1872215976Sjmallett entry and exit instruction sequences. 1873215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 1874215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. 1875215976Sjmallett This value must equal the MR1[DLL] value in all the DDR3 1876215976Sjmallett parts attached to all ranks during normal operation. 1877215976Sjmallett In dll-off mode, CL/CWL must be programmed 1878215976Sjmallett equal to 6/6, respectively, as per the DDR3 specifications. */ 1879215976Sjmallett uint64_t mpr : 1; /**< MPR 1880215976Sjmallett DFM writes this value to MR3[MPR] in the selected DDR3 parts 1881215976Sjmallett during power-up/init and read-leveling instruction sequencing. 1882215976Sjmallett (DFM also writes MR3[MPR]=1 at the beginning of a 1883215976Sjmallett read-leveling instruction sequence. Read-leveling can only be initiated via the 1884215976Sjmallett read-leveling instruction sequence.) 1885215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK]. 1886215976Sjmallett The MR3[MPR] value must be 0 in all the DDR3 1887215976Sjmallett parts attached to all ranks during normal operation. */ 1888215976Sjmallett uint64_t mprloc : 2; /**< MPR Location 1889215976Sjmallett DFM writes this value to MR3[MPRLoc] in the selected DDR3 parts 1890215976Sjmallett during power-up/init and read-leveling instruction sequencing. 1891215976Sjmallett (DFM also writes MR3[MPRLoc]=0 at the beginning of the 1892215976Sjmallett read-leveling instruction sequence.) 1893215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK]. 1894215976Sjmallett The MR3[MPRLoc] value must be 0 in all the DDR3 1895215976Sjmallett parts attached to all ranks during normal operation. */ 1896215976Sjmallett uint64_t cwl : 3; /**< CAS Write Latency 1897215976Sjmallett - 000: 5 1898215976Sjmallett - 001: 6 1899215976Sjmallett - 010: 7 1900215976Sjmallett - 011: 8 1901232812Sjmallett - 100: 9 1902232812Sjmallett - 101: 10 1903232812Sjmallett - 110: 11 1904232812Sjmallett - 111: 12 1905215976Sjmallett DFM writes this value to MR2[CWL] in the selected DDR3 parts 1906215976Sjmallett during power-up/init instruction sequencing. 1907215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 1908215976Sjmallett this value to MR2[CWL] in all DRAM parts in DFM_CONFIG[INIT_STATUS] ranks during self-refresh 1909215976Sjmallett entry and exit instruction sequences. 1910215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 1911215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. 1912215976Sjmallett This value must equal the MR2[CWL] value in all the DDR3 1913215976Sjmallett parts attached to all ranks during normal operation. */ 1914215976Sjmallett#else 1915215976Sjmallett uint64_t cwl : 3; 1916215976Sjmallett uint64_t mprloc : 2; 1917215976Sjmallett uint64_t mpr : 1; 1918215976Sjmallett uint64_t dll : 1; 1919215976Sjmallett uint64_t al : 2; 1920215976Sjmallett uint64_t wlev : 1; 1921215976Sjmallett uint64_t tdqs : 1; 1922215976Sjmallett uint64_t qoff : 1; 1923215976Sjmallett uint64_t bl : 2; 1924215976Sjmallett uint64_t cl : 4; 1925215976Sjmallett uint64_t rbt : 1; 1926215976Sjmallett uint64_t tm : 1; 1927215976Sjmallett uint64_t dllr : 1; 1928215976Sjmallett uint64_t wrp : 3; 1929215976Sjmallett uint64_t ppd : 1; 1930215976Sjmallett uint64_t reserved_25_63 : 39; 1931215976Sjmallett#endif 1932215976Sjmallett } s; 1933215976Sjmallett struct cvmx_dfm_modereg_params0_s cn63xx; 1934215976Sjmallett struct cvmx_dfm_modereg_params0_s cn63xxp1; 1935232812Sjmallett struct cvmx_dfm_modereg_params0_s cn66xx; 1936215976Sjmallett}; 1937215976Sjmalletttypedef union cvmx_dfm_modereg_params0 cvmx_dfm_modereg_params0_t; 1938215976Sjmallett 1939215976Sjmallett/** 1940215976Sjmallett * cvmx_dfm_modereg_params1 1941215976Sjmallett * 1942215976Sjmallett * Notes: 1943215976Sjmallett * These parameters are written into the DDR3 MR0, MR1, MR2 and MR3 registers. 1944215976Sjmallett * 1945215976Sjmallett */ 1946232812Sjmallettunion cvmx_dfm_modereg_params1 { 1947215976Sjmallett uint64_t u64; 1948232812Sjmallett struct cvmx_dfm_modereg_params1_s { 1949232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1950215976Sjmallett uint64_t reserved_48_63 : 16; 1951215976Sjmallett uint64_t rtt_nom_11 : 3; /**< Must be zero */ 1952215976Sjmallett uint64_t dic_11 : 2; /**< Must be zero */ 1953215976Sjmallett uint64_t rtt_wr_11 : 2; /**< Must be zero */ 1954215976Sjmallett uint64_t srt_11 : 1; /**< Must be zero */ 1955215976Sjmallett uint64_t asr_11 : 1; /**< Must be zero */ 1956215976Sjmallett uint64_t pasr_11 : 3; /**< Must be zero */ 1957215976Sjmallett uint64_t rtt_nom_10 : 3; /**< Must be zero */ 1958215976Sjmallett uint64_t dic_10 : 2; /**< Must be zero */ 1959215976Sjmallett uint64_t rtt_wr_10 : 2; /**< Must be zero */ 1960215976Sjmallett uint64_t srt_10 : 1; /**< Must be zero */ 1961215976Sjmallett uint64_t asr_10 : 1; /**< Must be zero */ 1962215976Sjmallett uint64_t pasr_10 : 3; /**< Must be zero */ 1963215976Sjmallett uint64_t rtt_nom_01 : 3; /**< RTT_NOM Rank 1 1964215976Sjmallett DFM writes this value to MR1[Rtt_Nom] in the rank 1 (i.e. CS1) DDR3 parts 1965215976Sjmallett when selected during power-up/init instruction sequencing. 1966215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 1967215976Sjmallett this value to MR1[Rtt_Nom] in all DRAM parts in rank 1 during self-refresh 1968215976Sjmallett entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<1>]=1). 1969215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 1970215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 1971215976Sjmallett uint64_t dic_01 : 2; /**< Output Driver Impedance Control Rank 1 1972215976Sjmallett DFM writes this value to MR1[D.I.C.] in the rank 1 (i.e. CS1) DDR3 parts 1973215976Sjmallett when selected during power-up/init and write-leveling instruction sequencing. 1974215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 1975215976Sjmallett this value to MR1[D.I.C.] in all DRAM parts in rank 1 during self-refresh 1976215976Sjmallett entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<1>]=1). 1977215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 1978215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 1979215976Sjmallett uint64_t rtt_wr_01 : 2; /**< RTT_WR Rank 1 1980215976Sjmallett DFM writes this value to MR2[Rtt_WR] in the rank 1 (i.e. CS1) DDR3 parts 1981215976Sjmallett when selected during power-up/init instruction sequencing. 1982215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 1983215976Sjmallett this value to MR2[Rtt_WR] in all DRAM parts in rank 1 during self-refresh 1984215976Sjmallett entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<1>]=1). 1985215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 1986215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 1987215976Sjmallett uint64_t srt_01 : 1; /**< Self-refresh temperature range Rank 1 1988215976Sjmallett DFM writes this value to MR2[SRT] in the rank 1 (i.e. CS1) DDR3 parts 1989215976Sjmallett when selected during power-up/init instruction sequencing. 1990215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 1991215976Sjmallett this value to MR2[SRT] in all DRAM parts in rank 1 during self-refresh 1992215976Sjmallett entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<1>]=1). 1993215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 1994215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 1995215976Sjmallett uint64_t asr_01 : 1; /**< Auto self-refresh Rank 1 1996215976Sjmallett DFM writes this value to MR2[ASR] in the rank 1 (i.e. CS1) DDR3 parts 1997215976Sjmallett when selected during power-up/init instruction sequencing. 1998215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 1999215976Sjmallett this value to MR2[ASR] in all DRAM parts in rank 1 during self-refresh 2000215976Sjmallett entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<1>]=1). 2001215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 2002215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 2003215976Sjmallett uint64_t pasr_01 : 3; /**< Partial array self-refresh Rank 1 2004215976Sjmallett DFM writes this value to MR2[PASR] in the rank 1 (i.e. CS1) DDR3 parts 2005215976Sjmallett when selected during power-up/init instruction sequencing. 2006215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 2007215976Sjmallett this value to MR2[PASR] in all DRAM parts in rank 1 during self-refresh 2008215976Sjmallett entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<1>]=1). 2009215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 2010215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 2011215976Sjmallett uint64_t rtt_nom_00 : 3; /**< RTT_NOM Rank 0 2012215976Sjmallett DFM writes this value to MR1[Rtt_Nom] in the rank 0 (i.e. CS0) DDR3 parts 2013215976Sjmallett when selected during power-up/init instruction sequencing. 2014215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 2015215976Sjmallett this value to MR1[Rtt_Nom] in all DRAM parts in rank 0 during self-refresh 2016215976Sjmallett entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<0>]=1). 2017215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 2018215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 2019215976Sjmallett uint64_t dic_00 : 2; /**< Output Driver Impedance Control Rank 0 2020215976Sjmallett DFM writes this value to MR1[D.I.C.] in the rank 0 (i.e. CS0) DDR3 parts 2021215976Sjmallett when selected during power-up/init and write-leveling instruction sequencing. 2022215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 2023215976Sjmallett this value to MR1[D.I.C.] in all DRAM parts in rank 0 during self-refresh 2024215976Sjmallett entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<0>]=1). 2025215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 2026215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 2027215976Sjmallett uint64_t rtt_wr_00 : 2; /**< RTT_WR Rank 0 2028215976Sjmallett DFM writes this value to MR2[Rtt_WR] in the rank 0 (i.e. CS0) DDR3 parts 2029215976Sjmallett when selected during power-up/init instruction sequencing. 2030215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 2031215976Sjmallett this value to MR2[Rtt_WR] in all DRAM parts in rank 0 during self-refresh 2032215976Sjmallett entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<0>]=1). 2033215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 2034215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 2035215976Sjmallett uint64_t srt_00 : 1; /**< Self-refresh temperature range Rank 0 2036215976Sjmallett DFM writes this value to MR2[SRT] in the rank 0 (i.e. CS0) DDR3 parts 2037215976Sjmallett when selected during power-up/init instruction sequencing. 2038215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 2039215976Sjmallett this value to MR2[SRT] in all DRAM parts in rank 0 during self-refresh 2040215976Sjmallett entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<0>]=1). 2041215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 2042215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 2043215976Sjmallett uint64_t asr_00 : 1; /**< Auto self-refresh Rank 0 2044215976Sjmallett DFM writes this value to MR2[ASR] in the rank 0 (i.e. CS0) DDR3 parts 2045215976Sjmallett when selected during power-up/init instruction sequencing. 2046215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 2047215976Sjmallett this value to MR2[ASR] in all DRAM parts in rank 0 during self-refresh 2048215976Sjmallett entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<0>]=1). 2049215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 2050215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 2051215976Sjmallett uint64_t pasr_00 : 3; /**< Partial array self-refresh Rank 0 2052215976Sjmallett DFM writes this value to MR2[PASR] in the rank 0 (i.e. CS0) DDR3 parts 2053215976Sjmallett when selected during power-up/init instruction sequencing. 2054215976Sjmallett If DFM_CONFIG[SREF_WITH_DLL] is set, DFM also writes 2055215976Sjmallett this value to MR2[PASR] in all DRAM parts in rank 0 during self-refresh 2056215976Sjmallett entry and exit instruction sequences (when DFM_CONFIG[INIT_STATUS<0>]=1). 2057215976Sjmallett See DFM_CONFIG[SEQUENCE,INIT_START,RANKMASK] and 2058215976Sjmallett DFM_RESET_CTL[DDR3PWARM,DDR3PSOFT]. */ 2059215976Sjmallett#else 2060215976Sjmallett uint64_t pasr_00 : 3; 2061215976Sjmallett uint64_t asr_00 : 1; 2062215976Sjmallett uint64_t srt_00 : 1; 2063215976Sjmallett uint64_t rtt_wr_00 : 2; 2064215976Sjmallett uint64_t dic_00 : 2; 2065215976Sjmallett uint64_t rtt_nom_00 : 3; 2066215976Sjmallett uint64_t pasr_01 : 3; 2067215976Sjmallett uint64_t asr_01 : 1; 2068215976Sjmallett uint64_t srt_01 : 1; 2069215976Sjmallett uint64_t rtt_wr_01 : 2; 2070215976Sjmallett uint64_t dic_01 : 2; 2071215976Sjmallett uint64_t rtt_nom_01 : 3; 2072215976Sjmallett uint64_t pasr_10 : 3; 2073215976Sjmallett uint64_t asr_10 : 1; 2074215976Sjmallett uint64_t srt_10 : 1; 2075215976Sjmallett uint64_t rtt_wr_10 : 2; 2076215976Sjmallett uint64_t dic_10 : 2; 2077215976Sjmallett uint64_t rtt_nom_10 : 3; 2078215976Sjmallett uint64_t pasr_11 : 3; 2079215976Sjmallett uint64_t asr_11 : 1; 2080215976Sjmallett uint64_t srt_11 : 1; 2081215976Sjmallett uint64_t rtt_wr_11 : 2; 2082215976Sjmallett uint64_t dic_11 : 2; 2083215976Sjmallett uint64_t rtt_nom_11 : 3; 2084215976Sjmallett uint64_t reserved_48_63 : 16; 2085215976Sjmallett#endif 2086215976Sjmallett } s; 2087215976Sjmallett struct cvmx_dfm_modereg_params1_s cn63xx; 2088215976Sjmallett struct cvmx_dfm_modereg_params1_s cn63xxp1; 2089232812Sjmallett struct cvmx_dfm_modereg_params1_s cn66xx; 2090215976Sjmallett}; 2091215976Sjmalletttypedef union cvmx_dfm_modereg_params1 cvmx_dfm_modereg_params1_t; 2092215976Sjmallett 2093215976Sjmallett/** 2094215976Sjmallett * cvmx_dfm_ops_cnt 2095215976Sjmallett * 2096215976Sjmallett * DFM_OPS_CNT = Performance Counters 2097215976Sjmallett * 2098215976Sjmallett */ 2099232812Sjmallettunion cvmx_dfm_ops_cnt { 2100215976Sjmallett uint64_t u64; 2101232812Sjmallett struct cvmx_dfm_ops_cnt_s { 2102232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2103215976Sjmallett uint64_t opscnt : 64; /**< Performance Counter 2104215976Sjmallett 64-bit counter that increments when the DDR3 data bus 2105232812Sjmallett is being used. Before using, clear counter via 2106232812Sjmallett DFM_CONTROL.BWCNT 2107215976Sjmallett DRAM bus utilization = DFM_OPS_CNT/DFM_FCLK_CNT */ 2108215976Sjmallett#else 2109215976Sjmallett uint64_t opscnt : 64; 2110215976Sjmallett#endif 2111215976Sjmallett } s; 2112215976Sjmallett struct cvmx_dfm_ops_cnt_s cn63xx; 2113215976Sjmallett struct cvmx_dfm_ops_cnt_s cn63xxp1; 2114232812Sjmallett struct cvmx_dfm_ops_cnt_s cn66xx; 2115215976Sjmallett}; 2116215976Sjmalletttypedef union cvmx_dfm_ops_cnt cvmx_dfm_ops_cnt_t; 2117215976Sjmallett 2118215976Sjmallett/** 2119215976Sjmallett * cvmx_dfm_phy_ctl 2120215976Sjmallett * 2121215976Sjmallett * DFM_PHY_CTL = DFM PHY Control 2122215976Sjmallett * 2123215976Sjmallett */ 2124232812Sjmallettunion cvmx_dfm_phy_ctl { 2125215976Sjmallett uint64_t u64; 2126232812Sjmallett struct cvmx_dfm_phy_ctl_s { 2127232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2128215976Sjmallett uint64_t reserved_15_63 : 49; 2129215976Sjmallett uint64_t rx_always_on : 1; /**< Disable dynamic DDR3 IO Rx power gating */ 2130215976Sjmallett uint64_t lv_mode : 1; /**< Low Voltage Mode (1.35V) */ 2131215976Sjmallett uint64_t ck_tune1 : 1; /**< Clock Tune 2132215976Sjmallett 2133215976Sjmallett NOTE: DFM UNUSED */ 2134215976Sjmallett uint64_t ck_dlyout1 : 4; /**< Clock delay out setting 2135215976Sjmallett 2136215976Sjmallett NOTE: DFM UNUSED */ 2137215976Sjmallett uint64_t ck_tune0 : 1; /**< Clock Tune */ 2138215976Sjmallett uint64_t ck_dlyout0 : 4; /**< Clock delay out setting */ 2139215976Sjmallett uint64_t loopback : 1; /**< Loopback enable */ 2140215976Sjmallett uint64_t loopback_pos : 1; /**< Loopback pos mode */ 2141215976Sjmallett uint64_t ts_stagger : 1; /**< TS Staggermode 2142215976Sjmallett This mode configures output drivers with 2-stage drive 2143215976Sjmallett strength to avoid undershoot issues on the bus when strong 2144215976Sjmallett drivers are suddenly turned on. When this mode is asserted, 2145215976Sjmallett Octeon will configure output drivers to be weak drivers 2146215976Sjmallett (60 ohm output impedance) at the first FCLK cycle, and 2147215976Sjmallett change drivers to the designated drive strengths specified 2148215976Sjmallett in DFM_COMP_CTL2 [CMD_CTL/CK_CTL/DQX_CTL] starting 2149215976Sjmallett at the following cycle */ 2150215976Sjmallett#else 2151215976Sjmallett uint64_t ts_stagger : 1; 2152215976Sjmallett uint64_t loopback_pos : 1; 2153215976Sjmallett uint64_t loopback : 1; 2154215976Sjmallett uint64_t ck_dlyout0 : 4; 2155215976Sjmallett uint64_t ck_tune0 : 1; 2156215976Sjmallett uint64_t ck_dlyout1 : 4; 2157215976Sjmallett uint64_t ck_tune1 : 1; 2158215976Sjmallett uint64_t lv_mode : 1; 2159215976Sjmallett uint64_t rx_always_on : 1; 2160215976Sjmallett uint64_t reserved_15_63 : 49; 2161215976Sjmallett#endif 2162215976Sjmallett } s; 2163215976Sjmallett struct cvmx_dfm_phy_ctl_s cn63xx; 2164232812Sjmallett struct cvmx_dfm_phy_ctl_cn63xxp1 { 2165232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2166215976Sjmallett uint64_t reserved_14_63 : 50; 2167215976Sjmallett uint64_t lv_mode : 1; /**< Low Voltage Mode (1.35V) */ 2168215976Sjmallett uint64_t ck_tune1 : 1; /**< Clock Tune 2169215976Sjmallett 2170215976Sjmallett NOTE: DFM UNUSED */ 2171215976Sjmallett uint64_t ck_dlyout1 : 4; /**< Clock delay out setting 2172215976Sjmallett 2173215976Sjmallett NOTE: DFM UNUSED */ 2174215976Sjmallett uint64_t ck_tune0 : 1; /**< Clock Tune */ 2175215976Sjmallett uint64_t ck_dlyout0 : 4; /**< Clock delay out setting */ 2176215976Sjmallett uint64_t loopback : 1; /**< Loopback enable */ 2177215976Sjmallett uint64_t loopback_pos : 1; /**< Loopback pos mode */ 2178215976Sjmallett uint64_t ts_stagger : 1; /**< TS Staggermode 2179215976Sjmallett This mode configures output drivers with 2-stage drive 2180215976Sjmallett strength to avoid undershoot issues on the bus when strong 2181215976Sjmallett drivers are suddenly turned on. When this mode is asserted, 2182215976Sjmallett Octeon will configure output drivers to be weak drivers 2183215976Sjmallett (60 ohm output impedance) at the first FCLK cycle, and 2184215976Sjmallett change drivers to the designated drive strengths specified 2185215976Sjmallett in DFM_COMP_CTL2 [CMD_CTL/CK_CTL/DQX_CTL] starting 2186215976Sjmallett at the following cycle */ 2187215976Sjmallett#else 2188215976Sjmallett uint64_t ts_stagger : 1; 2189215976Sjmallett uint64_t loopback_pos : 1; 2190215976Sjmallett uint64_t loopback : 1; 2191215976Sjmallett uint64_t ck_dlyout0 : 4; 2192215976Sjmallett uint64_t ck_tune0 : 1; 2193215976Sjmallett uint64_t ck_dlyout1 : 4; 2194215976Sjmallett uint64_t ck_tune1 : 1; 2195215976Sjmallett uint64_t lv_mode : 1; 2196215976Sjmallett uint64_t reserved_14_63 : 50; 2197215976Sjmallett#endif 2198215976Sjmallett } cn63xxp1; 2199232812Sjmallett struct cvmx_dfm_phy_ctl_s cn66xx; 2200215976Sjmallett}; 2201215976Sjmalletttypedef union cvmx_dfm_phy_ctl cvmx_dfm_phy_ctl_t; 2202215976Sjmallett 2203215976Sjmallett/** 2204215976Sjmallett * cvmx_dfm_reset_ctl 2205215976Sjmallett * 2206215976Sjmallett * Specify the RSL base addresses for the block 2207215976Sjmallett * 2208215976Sjmallett * 2209215976Sjmallett * Notes: 2210215976Sjmallett * DDR3RST - DDR3 DRAM parts have a new RESET# 2211215976Sjmallett * pin that wasn't present in DDR2 parts. The 2212215976Sjmallett * DDR3RST CSR field controls the assertion of 2213232812Sjmallett * the new 6xxx pin that attaches to RESET#. 2214232812Sjmallett * When DDR3RST is set, 6xxx asserts RESET#. 2215232812Sjmallett * When DDR3RST is clear, 6xxx de-asserts 2216215976Sjmallett * RESET#. 2217215976Sjmallett * 2218215976Sjmallett * DDR3RST is set on a cold reset. Warm and 2219215976Sjmallett * soft chip resets do not affect the DDR3RST 2220215976Sjmallett * value. Outside of cold reset, only software 2221215976Sjmallett * CSR writes change the DDR3RST value. 2222215976Sjmallett */ 2223232812Sjmallettunion cvmx_dfm_reset_ctl { 2224215976Sjmallett uint64_t u64; 2225232812Sjmallett struct cvmx_dfm_reset_ctl_s { 2226232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2227215976Sjmallett uint64_t reserved_4_63 : 60; 2228215976Sjmallett uint64_t ddr3psv : 1; /**< Must be zero */ 2229215976Sjmallett uint64_t ddr3psoft : 1; /**< Must be zero */ 2230215976Sjmallett uint64_t ddr3pwarm : 1; /**< Must be zero */ 2231215976Sjmallett uint64_t ddr3rst : 1; /**< Memory Reset 2232215976Sjmallett 0 = Reset asserted 2233215976Sjmallett 1 = Reset de-asserted */ 2234215976Sjmallett#else 2235215976Sjmallett uint64_t ddr3rst : 1; 2236215976Sjmallett uint64_t ddr3pwarm : 1; 2237215976Sjmallett uint64_t ddr3psoft : 1; 2238215976Sjmallett uint64_t ddr3psv : 1; 2239215976Sjmallett uint64_t reserved_4_63 : 60; 2240215976Sjmallett#endif 2241215976Sjmallett } s; 2242215976Sjmallett struct cvmx_dfm_reset_ctl_s cn63xx; 2243215976Sjmallett struct cvmx_dfm_reset_ctl_s cn63xxp1; 2244232812Sjmallett struct cvmx_dfm_reset_ctl_s cn66xx; 2245215976Sjmallett}; 2246215976Sjmalletttypedef union cvmx_dfm_reset_ctl cvmx_dfm_reset_ctl_t; 2247215976Sjmallett 2248215976Sjmallett/** 2249215976Sjmallett * cvmx_dfm_rlevel_ctl 2250215976Sjmallett */ 2251232812Sjmallettunion cvmx_dfm_rlevel_ctl { 2252215976Sjmallett uint64_t u64; 2253232812Sjmallett struct cvmx_dfm_rlevel_ctl_s { 2254232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2255215976Sjmallett uint64_t reserved_22_63 : 42; 2256215976Sjmallett uint64_t delay_unload_3 : 1; /**< When set, unload the PHY silo one cycle later 2257215976Sjmallett during read-leveling if DFM_RLEVEL_RANKi[BYTE*<1:0>] = 3 2258215976Sjmallett DELAY_UNLOAD_3 should normally be set, particularly at higher speeds. */ 2259215976Sjmallett uint64_t delay_unload_2 : 1; /**< When set, unload the PHY silo one cycle later 2260215976Sjmallett during read-leveling if DFM_RLEVEL_RANKi[BYTE*<1:0>] = 2 2261215976Sjmallett DELAY_UNLOAD_2 should normally not be set. */ 2262215976Sjmallett uint64_t delay_unload_1 : 1; /**< When set, unload the PHY silo one cycle later 2263215976Sjmallett during read-leveling if DFM_RLEVEL_RANKi[BYTE*<1:0>] = 1 2264215976Sjmallett DELAY_UNLOAD_1 should normally not be set. */ 2265215976Sjmallett uint64_t delay_unload_0 : 1; /**< When set, unload the PHY silo one cycle later 2266215976Sjmallett during read-leveling if DFM_RLEVEL_RANKi[BYTE*<1:0>] = 0 2267215976Sjmallett DELAY_UNLOAD_0 should normally not be set. */ 2268215976Sjmallett uint64_t bitmask : 8; /**< Mask to select bit lanes on which read-leveling 2269215976Sjmallett feedback is returned when OR_DIS is set to 1 */ 2270215976Sjmallett uint64_t or_dis : 1; /**< Disable or'ing of bits in a byte lane when computing 2271215976Sjmallett the read-leveling bitmask 2272215976Sjmallett OR_DIS should normally not be set. */ 2273215976Sjmallett uint64_t offset_en : 1; /**< Use DFM_RLEVEL_CTL[OFFSET] to calibrate read 2274215976Sjmallett level dskew settings */ 2275215976Sjmallett uint64_t offset : 4; /**< Pick final_setting-offset (if set) for the read level 2276215976Sjmallett deskew setting instead of the middle of the largest 2277215976Sjmallett contiguous sequence of 1's in the bitmask */ 2278215976Sjmallett uint64_t byte : 4; /**< 0 <= BYTE <= 1 2279215976Sjmallett Byte index for which bitmask results are saved 2280215976Sjmallett in DFM_RLEVEL_DBG */ 2281215976Sjmallett#else 2282215976Sjmallett uint64_t byte : 4; 2283215976Sjmallett uint64_t offset : 4; 2284215976Sjmallett uint64_t offset_en : 1; 2285215976Sjmallett uint64_t or_dis : 1; 2286215976Sjmallett uint64_t bitmask : 8; 2287215976Sjmallett uint64_t delay_unload_0 : 1; 2288215976Sjmallett uint64_t delay_unload_1 : 1; 2289215976Sjmallett uint64_t delay_unload_2 : 1; 2290215976Sjmallett uint64_t delay_unload_3 : 1; 2291215976Sjmallett uint64_t reserved_22_63 : 42; 2292215976Sjmallett#endif 2293215976Sjmallett } s; 2294215976Sjmallett struct cvmx_dfm_rlevel_ctl_s cn63xx; 2295232812Sjmallett struct cvmx_dfm_rlevel_ctl_cn63xxp1 { 2296232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2297215976Sjmallett uint64_t reserved_9_63 : 55; 2298215976Sjmallett uint64_t offset_en : 1; /**< Use DFM_RLEVEL_CTL[OFFSET] to calibrate read 2299215976Sjmallett level dskew settings */ 2300215976Sjmallett uint64_t offset : 4; /**< Pick final_setting-offset (if set) for the read level 2301215976Sjmallett deskew setting instead of the middle of the largest 2302215976Sjmallett contiguous sequence of 1's in the bitmask */ 2303215976Sjmallett uint64_t byte : 4; /**< 0 <= BYTE <= 1 2304215976Sjmallett Byte index for which bitmask results are saved 2305215976Sjmallett in DFM_RLEVEL_DBG */ 2306215976Sjmallett#else 2307215976Sjmallett uint64_t byte : 4; 2308215976Sjmallett uint64_t offset : 4; 2309215976Sjmallett uint64_t offset_en : 1; 2310215976Sjmallett uint64_t reserved_9_63 : 55; 2311215976Sjmallett#endif 2312215976Sjmallett } cn63xxp1; 2313232812Sjmallett struct cvmx_dfm_rlevel_ctl_s cn66xx; 2314215976Sjmallett}; 2315215976Sjmalletttypedef union cvmx_dfm_rlevel_ctl cvmx_dfm_rlevel_ctl_t; 2316215976Sjmallett 2317215976Sjmallett/** 2318215976Sjmallett * cvmx_dfm_rlevel_dbg 2319215976Sjmallett * 2320215976Sjmallett * Notes: 2321215976Sjmallett * A given read of DFM_RLEVEL_DBG returns the read-leveling pass/fail results for all possible 2322215976Sjmallett * delay settings (i.e. the BITMASK) for only one byte in the last rank that the HW read-leveled. 2323215976Sjmallett * DFM_RLEVEL_CTL[BYTE] selects the particular byte. 2324215976Sjmallett * To get these pass/fail results for another different rank, you must run the hardware read-leveling 2325215976Sjmallett * again. For example, it is possible to get the BITMASK results for every byte of every rank 2326215976Sjmallett * if you run read-leveling separately for each rank, probing DFM_RLEVEL_DBG between each 2327215976Sjmallett * read-leveling. 2328215976Sjmallett */ 2329232812Sjmallettunion cvmx_dfm_rlevel_dbg { 2330215976Sjmallett uint64_t u64; 2331232812Sjmallett struct cvmx_dfm_rlevel_dbg_s { 2332232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2333215976Sjmallett uint64_t bitmask : 64; /**< Bitmask generated during deskew settings sweep 2334215976Sjmallett BITMASK[n]=0 means deskew setting n failed 2335215976Sjmallett BITMASK[n]=1 means deskew setting n passed 2336215976Sjmallett for 0 <= n <= 63 */ 2337215976Sjmallett#else 2338215976Sjmallett uint64_t bitmask : 64; 2339215976Sjmallett#endif 2340215976Sjmallett } s; 2341215976Sjmallett struct cvmx_dfm_rlevel_dbg_s cn63xx; 2342215976Sjmallett struct cvmx_dfm_rlevel_dbg_s cn63xxp1; 2343232812Sjmallett struct cvmx_dfm_rlevel_dbg_s cn66xx; 2344215976Sjmallett}; 2345215976Sjmalletttypedef union cvmx_dfm_rlevel_dbg cvmx_dfm_rlevel_dbg_t; 2346215976Sjmallett 2347215976Sjmallett/** 2348215976Sjmallett * cvmx_dfm_rlevel_rank# 2349215976Sjmallett * 2350215976Sjmallett * Notes: 2351215976Sjmallett * This is TWO CSRs per DFM, one per each rank. 2352215976Sjmallett * 2353215976Sjmallett * Deskew setting is measured in units of 1/4 FCLK, so the above BYTE* values can range over 16 FCLKs. 2354215976Sjmallett * 2355215976Sjmallett * Each CSR is written by HW during a read-leveling sequence for the rank. (HW sets STATUS==3 after HW read-leveling completes for the rank.) 2356215976Sjmallett * If HW is unable to find a match per DFM_RLEVEL_CTL[OFFSET_EN] and DFM_RLEVEL_CTL[OFFSET], then HW will set DFM_RLEVEL_RANKn[BYTE*<5:0>] 2357215976Sjmallett * to 0. 2358215976Sjmallett * 2359215976Sjmallett * Each CSR may also be written by SW, but not while a read-leveling sequence is in progress. (HW sets STATUS==1 after a CSR write.) 2360215976Sjmallett * 2361215976Sjmallett * SW initiates a HW read-leveling sequence by programming DFM_RLEVEL_CTL and writing INIT_START=1 with SEQUENCE=1 in DFM_CONFIG. 2362215976Sjmallett * See DFM_RLEVEL_CTL. 2363215976Sjmallett */ 2364232812Sjmallettunion cvmx_dfm_rlevel_rankx { 2365215976Sjmallett uint64_t u64; 2366232812Sjmallett struct cvmx_dfm_rlevel_rankx_s { 2367232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2368215976Sjmallett uint64_t reserved_56_63 : 8; 2369215976Sjmallett uint64_t status : 2; /**< Indicates status of the read-levelling and where 2370215976Sjmallett the BYTE* programmings in <35:0> came from: 2371215976Sjmallett 0 = BYTE* values are their reset value 2372215976Sjmallett 1 = BYTE* values were set via a CSR write to this register 2373215976Sjmallett 2 = read-leveling sequence currently in progress (BYTE* values are unpredictable) 2374215976Sjmallett 3 = BYTE* values came from a complete read-leveling sequence */ 2375215976Sjmallett uint64_t reserved_12_53 : 42; 2376215976Sjmallett uint64_t byte1 : 6; /**< Deskew setting */ 2377215976Sjmallett uint64_t byte0 : 6; /**< Deskew setting */ 2378215976Sjmallett#else 2379215976Sjmallett uint64_t byte0 : 6; 2380215976Sjmallett uint64_t byte1 : 6; 2381215976Sjmallett uint64_t reserved_12_53 : 42; 2382215976Sjmallett uint64_t status : 2; 2383215976Sjmallett uint64_t reserved_56_63 : 8; 2384215976Sjmallett#endif 2385215976Sjmallett } s; 2386215976Sjmallett struct cvmx_dfm_rlevel_rankx_s cn63xx; 2387215976Sjmallett struct cvmx_dfm_rlevel_rankx_s cn63xxp1; 2388232812Sjmallett struct cvmx_dfm_rlevel_rankx_s cn66xx; 2389215976Sjmallett}; 2390215976Sjmalletttypedef union cvmx_dfm_rlevel_rankx cvmx_dfm_rlevel_rankx_t; 2391215976Sjmallett 2392215976Sjmallett/** 2393215976Sjmallett * cvmx_dfm_rodt_mask 2394215976Sjmallett * 2395215976Sjmallett * DFM_RODT_MASK = DFM Read OnDieTermination mask 2396215976Sjmallett * System designers may desire to terminate DQ/DQS/DM lines for higher frequency DDR operations 2397215976Sjmallett * especially on a multi-rank system. DDR3 DQ/DM/DQS I/O's have built in 2398215976Sjmallett * Termination resistor that can be turned on or off by the controller, after meeting tAOND and tAOF 2399215976Sjmallett * timing requirements. Each Rank has its own ODT pin that fans out to all the memory parts 2400215976Sjmallett * in that rank. System designers may prefer different combinations of ODT ON's for reads 2401215976Sjmallett * into different ranks. Octeon supports full programmability by way of the mask register below. 2402215976Sjmallett * Each Rank position has its own 8-bit programmable field. 2403215976Sjmallett * When the controller does a read to that rank, it sets the 4 ODT pins to the MASK pins below. 2404215976Sjmallett * For eg., When doing a read into Rank0, a system designer may desire to terminate the lines 2405215976Sjmallett * with the resistor on Dimm0/Rank1. The mask RODT_D0_R0 would then be [00000010]. 2406215976Sjmallett * Octeon drives the appropriate mask values on the ODT pins by default. If this feature is not 2407215976Sjmallett * required, write 0 in this register. Note that, as per the DDR3 specifications, the ODT pin 2408215976Sjmallett * for the rank that is being read should always be 0. 2409215976Sjmallett * 2410215976Sjmallett * Notes: 2411215976Sjmallett * - Notice that when there is only one rank, all valid fields must be zero. This is because there is no 2412215976Sjmallett * "other" rank to terminate lines for. Read ODT is meant for multirank systems. 2413215976Sjmallett * - For a two rank system and a read op to rank0: use RODT_D0_R0<1> to terminate lines on rank1. 2414215976Sjmallett * - For a two rank system and a read op to rank1: use RODT_D0_R1<0> to terminate lines on rank0. 2415215976Sjmallett * - Therefore, when a given RANK is selected, the RODT mask for that RANK is used. 2416215976Sjmallett * 2417215976Sjmallett * DFM always reads 128-bit words independently via one read CAS operation per word. 2418215976Sjmallett * When a RODT mask bit is set, DFM asserts the OCTEON ODT output 2419215976Sjmallett * pin(s) starting (CL - CWL) CK's after the read CAS operation. Then, OCTEON 2420215976Sjmallett * normally continues to assert the ODT output pin(s) for 5+DFM_CONTROL[RODT_BPRCH] more CK's 2421215976Sjmallett * - for a total of 6+DFM_CONTROL[RODT_BPRCH] CK's for the entire 128-bit read - 2422215976Sjmallett * satisfying the 6 CK DDR3 ODTH8 requirements. 2423215976Sjmallett * 2424215976Sjmallett * But it is possible for OCTEON to issue two 128-bit reads separated by as few as 2425215976Sjmallett * RtR = 4 or 5 (6 if DFM_CONTROL[RODT_BPRCH]=1) CK's. In that case, OCTEON asserts the ODT output pin(s) 2426215976Sjmallett * for the RODT mask of the first 128-bit read for RtR CK's, then asserts 2427215976Sjmallett * the ODT output pin(s) for the RODT mask of the second 128-bit read for 6+DFM_CONTROL[RODT_BPRCH] CK's 2428215976Sjmallett * (or less if a third 128-bit read follows within 4 or 5 (or 6) CK's of this second 128-bit read). 2429215976Sjmallett * Note that it may be necessary to force DFM to space back-to-back 128-bit reads 2430215976Sjmallett * to different ranks apart by at least 6+DFM_CONTROL[RODT_BPRCH] CK's to prevent DDR3 ODTH8 violations. 2431215976Sjmallett */ 2432232812Sjmallettunion cvmx_dfm_rodt_mask { 2433215976Sjmallett uint64_t u64; 2434232812Sjmallett struct cvmx_dfm_rodt_mask_s { 2435232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2436215976Sjmallett uint64_t rodt_d3_r1 : 8; /**< Must be zero. */ 2437215976Sjmallett uint64_t rodt_d3_r0 : 8; /**< Must be zero. */ 2438215976Sjmallett uint64_t rodt_d2_r1 : 8; /**< Must be zero. */ 2439215976Sjmallett uint64_t rodt_d2_r0 : 8; /**< Must be zero. */ 2440215976Sjmallett uint64_t rodt_d1_r1 : 8; /**< Must be zero. */ 2441215976Sjmallett uint64_t rodt_d1_r0 : 8; /**< Must be zero. */ 2442215976Sjmallett uint64_t rodt_d0_r1 : 8; /**< Read ODT mask RANK1 2443215976Sjmallett RODT_D0_R1<7:1> must be zero in all cases. 2444215976Sjmallett RODT_D0_R1<0> must also be zero if RANK_ENA is not set. */ 2445215976Sjmallett uint64_t rodt_d0_r0 : 8; /**< Read ODT mask RANK0 2446215976Sjmallett RODT_D0_R0<7:2,0> must be zero in all cases. 2447215976Sjmallett RODT_D0_R0<1> must also be zero if RANK_ENA is not set. */ 2448215976Sjmallett#else 2449215976Sjmallett uint64_t rodt_d0_r0 : 8; 2450215976Sjmallett uint64_t rodt_d0_r1 : 8; 2451215976Sjmallett uint64_t rodt_d1_r0 : 8; 2452215976Sjmallett uint64_t rodt_d1_r1 : 8; 2453215976Sjmallett uint64_t rodt_d2_r0 : 8; 2454215976Sjmallett uint64_t rodt_d2_r1 : 8; 2455215976Sjmallett uint64_t rodt_d3_r0 : 8; 2456215976Sjmallett uint64_t rodt_d3_r1 : 8; 2457215976Sjmallett#endif 2458215976Sjmallett } s; 2459215976Sjmallett struct cvmx_dfm_rodt_mask_s cn63xx; 2460215976Sjmallett struct cvmx_dfm_rodt_mask_s cn63xxp1; 2461232812Sjmallett struct cvmx_dfm_rodt_mask_s cn66xx; 2462215976Sjmallett}; 2463215976Sjmalletttypedef union cvmx_dfm_rodt_mask cvmx_dfm_rodt_mask_t; 2464215976Sjmallett 2465215976Sjmallett/** 2466215976Sjmallett * cvmx_dfm_slot_ctl0 2467215976Sjmallett * 2468215976Sjmallett * DFM_SLOT_CTL0 = DFM Slot Control0 2469215976Sjmallett * This register is an assortment of various control fields needed by the memory controller 2470215976Sjmallett * 2471215976Sjmallett * Notes: 2472215976Sjmallett * HW will update this register if SW has not previously written to it and when any of DFM_RLEVEL_RANKn, DFM_WLEVEL_RANKn, DFM_CONTROL and 2473215976Sjmallett * DFM_MODEREG_PARAMS0 change.Ideally, this register should only be read after DFM has been initialized and DFM_RLEVEL_RANKn, DFM_WLEVEL_RANKn 2474215976Sjmallett * have valid data. 2475215976Sjmallett * R2W_INIT has 1 extra CK cycle built in for odt settling/channel turnaround time. 2476215976Sjmallett */ 2477232812Sjmallettunion cvmx_dfm_slot_ctl0 { 2478215976Sjmallett uint64_t u64; 2479232812Sjmallett struct cvmx_dfm_slot_ctl0_s { 2480232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2481215976Sjmallett uint64_t reserved_24_63 : 40; 2482215976Sjmallett uint64_t w2w_init : 6; /**< Write-to-write spacing control 2483215976Sjmallett for back to back accesses to the same rank and dimm */ 2484215976Sjmallett uint64_t w2r_init : 6; /**< Write-to-read spacing control 2485215976Sjmallett for back to back accesses to the same rank and dimm */ 2486215976Sjmallett uint64_t r2w_init : 6; /**< Read-to-write spacing control 2487215976Sjmallett for back to back accesses to the same rank and dimm */ 2488215976Sjmallett uint64_t r2r_init : 6; /**< Read-to-read spacing control 2489215976Sjmallett for back to back accesses to the same rank and dimm */ 2490215976Sjmallett#else 2491215976Sjmallett uint64_t r2r_init : 6; 2492215976Sjmallett uint64_t r2w_init : 6; 2493215976Sjmallett uint64_t w2r_init : 6; 2494215976Sjmallett uint64_t w2w_init : 6; 2495215976Sjmallett uint64_t reserved_24_63 : 40; 2496215976Sjmallett#endif 2497215976Sjmallett } s; 2498215976Sjmallett struct cvmx_dfm_slot_ctl0_s cn63xx; 2499215976Sjmallett struct cvmx_dfm_slot_ctl0_s cn63xxp1; 2500232812Sjmallett struct cvmx_dfm_slot_ctl0_s cn66xx; 2501215976Sjmallett}; 2502215976Sjmalletttypedef union cvmx_dfm_slot_ctl0 cvmx_dfm_slot_ctl0_t; 2503215976Sjmallett 2504215976Sjmallett/** 2505215976Sjmallett * cvmx_dfm_slot_ctl1 2506215976Sjmallett * 2507215976Sjmallett * DFM_SLOT_CTL1 = DFM Slot Control1 2508215976Sjmallett * This register is an assortment of various control fields needed by the memory controller 2509215976Sjmallett * 2510215976Sjmallett * Notes: 2511215976Sjmallett * HW will update this register if SW has not previously written to it and when any of DFM_RLEVEL_RANKn, DFM_WLEVEL_RANKn, DFM_CONTROL and 2512215976Sjmallett * DFM_MODEREG_PARAMS0 change.Ideally, this register should only be read after DFM has been initialized and DFM_RLEVEL_RANKn, DFM_WLEVEL_RANKn 2513215976Sjmallett * have valid data. 2514215976Sjmallett * R2W_XRANK_INIT, W2R_XRANK_INIT have 1 extra CK cycle built in for odt settling/channel turnaround time. 2515215976Sjmallett */ 2516232812Sjmallettunion cvmx_dfm_slot_ctl1 { 2517215976Sjmallett uint64_t u64; 2518232812Sjmallett struct cvmx_dfm_slot_ctl1_s { 2519232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2520215976Sjmallett uint64_t reserved_24_63 : 40; 2521215976Sjmallett uint64_t w2w_xrank_init : 6; /**< Write-to-write spacing control 2522215976Sjmallett for back to back accesses across ranks of the same dimm */ 2523215976Sjmallett uint64_t w2r_xrank_init : 6; /**< Write-to-read spacing control 2524215976Sjmallett for back to back accesses across ranks of the same dimm */ 2525215976Sjmallett uint64_t r2w_xrank_init : 6; /**< Read-to-write spacing control 2526215976Sjmallett for back to back accesses across ranks of the same dimm */ 2527215976Sjmallett uint64_t r2r_xrank_init : 6; /**< Read-to-read spacing control 2528215976Sjmallett for back to back accesses across ranks of the same dimm */ 2529215976Sjmallett#else 2530215976Sjmallett uint64_t r2r_xrank_init : 6; 2531215976Sjmallett uint64_t r2w_xrank_init : 6; 2532215976Sjmallett uint64_t w2r_xrank_init : 6; 2533215976Sjmallett uint64_t w2w_xrank_init : 6; 2534215976Sjmallett uint64_t reserved_24_63 : 40; 2535215976Sjmallett#endif 2536215976Sjmallett } s; 2537215976Sjmallett struct cvmx_dfm_slot_ctl1_s cn63xx; 2538215976Sjmallett struct cvmx_dfm_slot_ctl1_s cn63xxp1; 2539232812Sjmallett struct cvmx_dfm_slot_ctl1_s cn66xx; 2540215976Sjmallett}; 2541215976Sjmalletttypedef union cvmx_dfm_slot_ctl1 cvmx_dfm_slot_ctl1_t; 2542215976Sjmallett 2543215976Sjmallett/** 2544215976Sjmallett * cvmx_dfm_timing_params0 2545215976Sjmallett */ 2546232812Sjmallettunion cvmx_dfm_timing_params0 { 2547215976Sjmallett uint64_t u64; 2548232812Sjmallett struct cvmx_dfm_timing_params0_s { 2549232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2550215976Sjmallett uint64_t reserved_47_63 : 17; 2551215976Sjmallett uint64_t trp_ext : 1; /**< Indicates tRP constraints. 2552215976Sjmallett Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)] 2553215976Sjmallett + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1, 2554215976Sjmallett where tRP, tRTP are from the DDR3 spec, and tCYC(ns) 2555215976Sjmallett is the DDR clock frequency (not data rate). 2556215976Sjmallett TYP tRP=10-15ns 2557215976Sjmallett TYP tRTP=max(4nCK, 7.5ns) */ 2558215976Sjmallett uint64_t tcksre : 4; /**< Indicates tCKSRE constraints. 2559215976Sjmallett Set TCKSRE (CSR field) = RNDUP[tCKSRE(ns)/tCYC(ns)]-1, 2560215976Sjmallett where tCKSRE is from the DDR3 spec, and tCYC(ns) 2561215976Sjmallett is the DDR clock frequency (not data rate). 2562215976Sjmallett TYP=max(5nCK, 10ns) */ 2563215976Sjmallett uint64_t trp : 4; /**< Indicates tRP constraints. 2564232812Sjmallett Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)] 2565215976Sjmallett + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1, 2566215976Sjmallett where tRP, tRTP are from the DDR3 spec, and tCYC(ns) 2567215976Sjmallett is the DDR clock frequency (not data rate). 2568215976Sjmallett TYP tRP=10-15ns 2569215976Sjmallett TYP tRTP=max(4nCK, 7.5ns) */ 2570215976Sjmallett uint64_t tzqinit : 4; /**< Indicates tZQINIT constraints. 2571215976Sjmallett Set TZQINIT (CSR field) = RNDUP[tZQINIT(ns)/(256*tCYC(ns))], 2572215976Sjmallett where tZQINIT is from the DDR3 spec, and tCYC(ns) 2573215976Sjmallett is the DDR clock frequency (not data rate). 2574215976Sjmallett TYP=2 (equivalent to 512) */ 2575215976Sjmallett uint64_t tdllk : 4; /**< Indicates tDLLk constraints. 2576215976Sjmallett Set TDLLK (CSR field) = RNDUP[tDLLk(ns)/(256*tCYC(ns))], 2577215976Sjmallett where tDLLk is from the DDR3 spec, and tCYC(ns) 2578215976Sjmallett is the DDR clock frequency (not data rate). 2579215976Sjmallett TYP=2 (equivalent to 512) 2580215976Sjmallett This parameter is used in self-refresh exit 2581215976Sjmallett and assumed to be greater than tRFC */ 2582215976Sjmallett uint64_t tmod : 4; /**< Indicates tMOD constraints. 2583215976Sjmallett Set TMOD (CSR field) = RNDUP[tMOD(ns)/tCYC(ns)]-1, 2584215976Sjmallett where tMOD is from the DDR3 spec, and tCYC(ns) 2585215976Sjmallett is the DDR clock frequency (not data rate). 2586215976Sjmallett TYP=max(12nCK, 15ns) */ 2587215976Sjmallett uint64_t tmrd : 4; /**< Indicates tMRD constraints. 2588215976Sjmallett Set TMRD (CSR field) = RNDUP[tMRD(ns)/tCYC(ns)]-1, 2589215976Sjmallett where tMRD is from the DDR3 spec, and tCYC(ns) 2590215976Sjmallett is the DDR clock frequency (not data rate). 2591215976Sjmallett TYP=4nCK */ 2592215976Sjmallett uint64_t txpr : 4; /**< Indicates tXPR constraints. 2593215976Sjmallett Set TXPR (CSR field) = RNDUP[tXPR(ns)/(16*tCYC(ns))], 2594215976Sjmallett where tXPR is from the DDR3 spec, and tCYC(ns) 2595215976Sjmallett is the DDR clock frequency (not data rate). 2596215976Sjmallett TYP=max(5nCK, tRFC+10ns) */ 2597215976Sjmallett uint64_t tcke : 4; /**< Indicates tCKE constraints. 2598215976Sjmallett Set TCKE (CSR field) = RNDUP[tCKE(ns)/tCYC(ns)]-1, 2599215976Sjmallett where tCKE is from the DDR3 spec, and tCYC(ns) 2600215976Sjmallett is the DDR clock frequency (not data rate). 2601215976Sjmallett TYP=max(3nCK, 7.5/5.625/5.625/5ns) */ 2602215976Sjmallett uint64_t tzqcs : 4; /**< Indicates tZQCS constraints. 2603215976Sjmallett Set TZQCS (CSR field) = RNDUP[tZQCS(ns)/(16*tCYC(ns))], 2604215976Sjmallett where tZQCS is from the DDR3 spec, and tCYC(ns) 2605215976Sjmallett is the DDR clock frequency (not data rate). 2606215976Sjmallett TYP=4 (equivalent to 64) */ 2607215976Sjmallett uint64_t tckeon : 10; /**< Reserved. Should be written to zero. */ 2608215976Sjmallett#else 2609215976Sjmallett uint64_t tckeon : 10; 2610215976Sjmallett uint64_t tzqcs : 4; 2611215976Sjmallett uint64_t tcke : 4; 2612215976Sjmallett uint64_t txpr : 4; 2613215976Sjmallett uint64_t tmrd : 4; 2614215976Sjmallett uint64_t tmod : 4; 2615215976Sjmallett uint64_t tdllk : 4; 2616215976Sjmallett uint64_t tzqinit : 4; 2617215976Sjmallett uint64_t trp : 4; 2618215976Sjmallett uint64_t tcksre : 4; 2619215976Sjmallett uint64_t trp_ext : 1; 2620215976Sjmallett uint64_t reserved_47_63 : 17; 2621215976Sjmallett#endif 2622215976Sjmallett } s; 2623232812Sjmallett struct cvmx_dfm_timing_params0_cn63xx { 2624232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2625215976Sjmallett uint64_t reserved_47_63 : 17; 2626215976Sjmallett uint64_t trp_ext : 1; /**< Indicates tRP constraints. 2627215976Sjmallett Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)] 2628215976Sjmallett + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1, 2629215976Sjmallett where tRP, tRTP are from the DDR3 spec, and tCYC(ns) 2630215976Sjmallett is the DDR clock frequency (not data rate). 2631215976Sjmallett TYP tRP=10-15ns 2632215976Sjmallett TYP tRTP=max(4nCK, 7.5ns) */ 2633215976Sjmallett uint64_t tcksre : 4; /**< Indicates tCKSRE constraints. 2634215976Sjmallett Set TCKSRE (CSR field) = RNDUP[tCKSRE(ns)/tCYC(ns)]-1, 2635215976Sjmallett where tCKSRE is from the DDR3 spec, and tCYC(ns) 2636215976Sjmallett is the DDR clock frequency (not data rate). 2637215976Sjmallett TYP=max(5nCK, 10ns) */ 2638215976Sjmallett uint64_t trp : 4; /**< Indicates tRP constraints. 2639215976Sjmallett Set [TRP_EXT[0:0], TRP[3:0]] (CSR field) = RNDUP[tRP(ns)/tCYC(ns)] 2640215976Sjmallett + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1, 2641215976Sjmallett where tRP, tRTP are from the DDR3 spec, and tCYC(ns) 2642215976Sjmallett is the DDR clock frequency (not data rate). 2643215976Sjmallett TYP tRP=10-15ns 2644215976Sjmallett TYP tRTP=max(4nCK, 7.5ns) */ 2645215976Sjmallett uint64_t tzqinit : 4; /**< Indicates tZQINIT constraints. 2646215976Sjmallett Set TZQINIT (CSR field) = RNDUP[tZQINIT(ns)/(256*tCYC(ns))], 2647215976Sjmallett where tZQINIT is from the DDR3 spec, and tCYC(ns) 2648215976Sjmallett is the DDR clock frequency (not data rate). 2649215976Sjmallett TYP=2 (equivalent to 512) */ 2650215976Sjmallett uint64_t tdllk : 4; /**< Indicates tDLLk constraints. 2651215976Sjmallett Set TDLLK (CSR field) = RNDUP[tDLLk(ns)/(256*tCYC(ns))], 2652215976Sjmallett where tDLLk is from the DDR3 spec, and tCYC(ns) 2653215976Sjmallett is the DDR clock frequency (not data rate). 2654215976Sjmallett TYP=2 (equivalent to 512) 2655215976Sjmallett This parameter is used in self-refresh exit 2656215976Sjmallett and assumed to be greater than tRFC */ 2657215976Sjmallett uint64_t tmod : 4; /**< Indicates tMOD constraints. 2658215976Sjmallett Set TMOD (CSR field) = RNDUP[tMOD(ns)/tCYC(ns)]-1, 2659215976Sjmallett where tMOD is from the DDR3 spec, and tCYC(ns) 2660215976Sjmallett is the DDR clock frequency (not data rate). 2661215976Sjmallett TYP=max(12nCK, 15ns) */ 2662215976Sjmallett uint64_t tmrd : 4; /**< Indicates tMRD constraints. 2663215976Sjmallett Set TMRD (CSR field) = RNDUP[tMRD(ns)/tCYC(ns)]-1, 2664215976Sjmallett where tMRD is from the DDR3 spec, and tCYC(ns) 2665215976Sjmallett is the DDR clock frequency (not data rate). 2666215976Sjmallett TYP=4nCK */ 2667215976Sjmallett uint64_t txpr : 4; /**< Indicates tXPR constraints. 2668215976Sjmallett Set TXPR (CSR field) = RNDUP[tXPR(ns)/(16*tCYC(ns))], 2669215976Sjmallett where tXPR is from the DDR3 spec, and tCYC(ns) 2670215976Sjmallett is the DDR clock frequency (not data rate). 2671215976Sjmallett TYP=max(5nCK, tRFC+10ns) */ 2672215976Sjmallett uint64_t tcke : 4; /**< Indicates tCKE constraints. 2673215976Sjmallett Set TCKE (CSR field) = RNDUP[tCKE(ns)/tCYC(ns)]-1, 2674215976Sjmallett where tCKE is from the DDR3 spec, and tCYC(ns) 2675215976Sjmallett is the DDR clock frequency (not data rate). 2676215976Sjmallett TYP=max(3nCK, 7.5/5.625/5.625/5ns) */ 2677215976Sjmallett uint64_t tzqcs : 4; /**< Indicates tZQCS constraints. 2678215976Sjmallett Set TZQCS (CSR field) = RNDUP[tZQCS(ns)/(16*tCYC(ns))], 2679215976Sjmallett where tZQCS is from the DDR3 spec, and tCYC(ns) 2680215976Sjmallett is the DDR clock frequency (not data rate). 2681215976Sjmallett TYP=4 (equivalent to 64) */ 2682215976Sjmallett uint64_t reserved_0_9 : 10; 2683215976Sjmallett#else 2684215976Sjmallett uint64_t reserved_0_9 : 10; 2685215976Sjmallett uint64_t tzqcs : 4; 2686215976Sjmallett uint64_t tcke : 4; 2687215976Sjmallett uint64_t txpr : 4; 2688215976Sjmallett uint64_t tmrd : 4; 2689215976Sjmallett uint64_t tmod : 4; 2690215976Sjmallett uint64_t tdllk : 4; 2691215976Sjmallett uint64_t tzqinit : 4; 2692215976Sjmallett uint64_t trp : 4; 2693215976Sjmallett uint64_t tcksre : 4; 2694215976Sjmallett uint64_t trp_ext : 1; 2695215976Sjmallett uint64_t reserved_47_63 : 17; 2696215976Sjmallett#endif 2697215976Sjmallett } cn63xx; 2698232812Sjmallett struct cvmx_dfm_timing_params0_cn63xxp1 { 2699232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2700215976Sjmallett uint64_t reserved_46_63 : 18; 2701215976Sjmallett uint64_t tcksre : 4; /**< Indicates tCKSRE constraints. 2702215976Sjmallett Set TCKSRE (CSR field) = RNDUP[tCKSRE(ns)/tCYC(ns)]-1, 2703215976Sjmallett where tCKSRE is from the DDR3 spec, and tCYC(ns) 2704215976Sjmallett is the DDR clock frequency (not data rate). 2705215976Sjmallett TYP=max(5nCK, 10ns) */ 2706215976Sjmallett uint64_t trp : 4; /**< Indicates tRP constraints. 2707215976Sjmallett Set TRP (CSR field) = RNDUP[tRP(ns)/tCYC(ns)] 2708215976Sjmallett + (RNDUP[tRTP(ns)/tCYC(ns)])-4)-1, 2709215976Sjmallett where tRP, tRTP are from the DDR3 spec, and tCYC(ns) 2710215976Sjmallett is the DDR clock frequency (not data rate). 2711215976Sjmallett TYP tRP=10-15ns 2712215976Sjmallett TYP tRTP=max(4nCK, 7.5ns) */ 2713215976Sjmallett uint64_t tzqinit : 4; /**< Indicates tZQINIT constraints. 2714215976Sjmallett Set TZQINIT (CSR field) = RNDUP[tZQINIT(ns)/(256*tCYC(ns))], 2715215976Sjmallett where tZQINIT is from the DDR3 spec, and tCYC(ns) 2716215976Sjmallett is the DDR clock frequency (not data rate). 2717215976Sjmallett TYP=2 (equivalent to 512) */ 2718215976Sjmallett uint64_t tdllk : 4; /**< Indicates tDLLk constraints. 2719215976Sjmallett Set TDLLK (CSR field) = RNDUP[tDLLk(ns)/(256*tCYC(ns))], 2720215976Sjmallett where tDLLk is from the DDR3 spec, and tCYC(ns) 2721215976Sjmallett is the DDR clock frequency (not data rate). 2722215976Sjmallett TYP=2 (equivalent to 512) 2723215976Sjmallett This parameter is used in self-refresh exit 2724215976Sjmallett and assumed to be greater than tRFC */ 2725215976Sjmallett uint64_t tmod : 4; /**< Indicates tMOD constraints. 2726215976Sjmallett Set TMOD (CSR field) = RNDUP[tMOD(ns)/tCYC(ns)]-1, 2727215976Sjmallett where tMOD is from the DDR3 spec, and tCYC(ns) 2728215976Sjmallett is the DDR clock frequency (not data rate). 2729215976Sjmallett TYP=max(12nCK, 15ns) */ 2730215976Sjmallett uint64_t tmrd : 4; /**< Indicates tMRD constraints. 2731215976Sjmallett Set TMRD (CSR field) = RNDUP[tMRD(ns)/tCYC(ns)]-1, 2732215976Sjmallett where tMRD is from the DDR3 spec, and tCYC(ns) 2733215976Sjmallett is the DDR clock frequency (not data rate). 2734215976Sjmallett TYP=4nCK */ 2735215976Sjmallett uint64_t txpr : 4; /**< Indicates tXPR constraints. 2736215976Sjmallett Set TXPR (CSR field) = RNDUP[tXPR(ns)/(16*tCYC(ns))], 2737215976Sjmallett where tXPR is from the DDR3 spec, and tCYC(ns) 2738215976Sjmallett is the DDR clock frequency (not data rate). 2739215976Sjmallett TYP=max(5nCK, tRFC+10ns) */ 2740215976Sjmallett uint64_t tcke : 4; /**< Indicates tCKE constraints. 2741215976Sjmallett Set TCKE (CSR field) = RNDUP[tCKE(ns)/tCYC(ns)]-1, 2742215976Sjmallett where tCKE is from the DDR3 spec, and tCYC(ns) 2743215976Sjmallett is the DDR clock frequency (not data rate). 2744215976Sjmallett TYP=max(3nCK, 7.5/5.625/5.625/5ns) */ 2745215976Sjmallett uint64_t tzqcs : 4; /**< Indicates tZQCS constraints. 2746215976Sjmallett Set TZQCS (CSR field) = RNDUP[tZQCS(ns)/(16*tCYC(ns))], 2747215976Sjmallett where tZQCS is from the DDR3 spec, and tCYC(ns) 2748215976Sjmallett is the DDR clock frequency (not data rate). 2749215976Sjmallett TYP=4 (equivalent to 64) */ 2750215976Sjmallett uint64_t tckeon : 10; /**< Reserved. Should be written to zero. */ 2751215976Sjmallett#else 2752215976Sjmallett uint64_t tckeon : 10; 2753215976Sjmallett uint64_t tzqcs : 4; 2754215976Sjmallett uint64_t tcke : 4; 2755215976Sjmallett uint64_t txpr : 4; 2756215976Sjmallett uint64_t tmrd : 4; 2757215976Sjmallett uint64_t tmod : 4; 2758215976Sjmallett uint64_t tdllk : 4; 2759215976Sjmallett uint64_t tzqinit : 4; 2760215976Sjmallett uint64_t trp : 4; 2761215976Sjmallett uint64_t tcksre : 4; 2762215976Sjmallett uint64_t reserved_46_63 : 18; 2763215976Sjmallett#endif 2764215976Sjmallett } cn63xxp1; 2765232812Sjmallett struct cvmx_dfm_timing_params0_cn63xx cn66xx; 2766215976Sjmallett}; 2767215976Sjmalletttypedef union cvmx_dfm_timing_params0 cvmx_dfm_timing_params0_t; 2768215976Sjmallett 2769215976Sjmallett/** 2770215976Sjmallett * cvmx_dfm_timing_params1 2771215976Sjmallett */ 2772232812Sjmallettunion cvmx_dfm_timing_params1 { 2773215976Sjmallett uint64_t u64; 2774232812Sjmallett struct cvmx_dfm_timing_params1_s { 2775232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2776215976Sjmallett uint64_t reserved_47_63 : 17; 2777215976Sjmallett uint64_t tras_ext : 1; /**< Indicates tRAS constraints. 2778215976Sjmallett Set [TRAS_EXT[0:0], TRAS[4:0]] (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1, 2779215976Sjmallett where tRAS is from the DDR3 spec, and tCYC(ns) 2780215976Sjmallett is the DDR clock frequency (not data rate). 2781215976Sjmallett TYP=35ns-9*tREFI 2782215976Sjmallett - 000000: RESERVED 2783215976Sjmallett - 000001: 2 tCYC 2784215976Sjmallett - 000010: 3 tCYC 2785215976Sjmallett - ... 2786215976Sjmallett - 111111: 64 tCYC */ 2787215976Sjmallett uint64_t txpdll : 5; /**< Indicates tXPDLL constraints. 2788215976Sjmallett Set TXPDLL (CSR field) = RNDUP[tXPDLL(ns)/tCYC(ns)]-1, 2789215976Sjmallett where tXPDLL is from the DDR3 spec, and tCYC(ns) 2790215976Sjmallett is the DDR clock frequency (not data rate). 2791215976Sjmallett TYP=max(10nCK, 24ns) */ 2792215976Sjmallett uint64_t tfaw : 5; /**< Indicates tFAW constraints. 2793215976Sjmallett Set TFAW (CSR field) = RNDUP[tFAW(ns)/(4*tCYC(ns))], 2794215976Sjmallett where tFAW is from the DDR3 spec, and tCYC(ns) 2795215976Sjmallett is the DDR clock frequency (not data rate). 2796215976Sjmallett TYP=30-40ns */ 2797215976Sjmallett uint64_t twldqsen : 4; /**< Indicates tWLDQSEN constraints. 2798215976Sjmallett Set TWLDQSEN (CSR field) = RNDUP[tWLDQSEN(ns)/(4*tCYC(ns))], 2799215976Sjmallett where tWLDQSEN is from the DDR3 spec, and tCYC(ns) 2800215976Sjmallett is the DDR clock frequency (not data rate). 2801215976Sjmallett TYP=max(25nCK) */ 2802215976Sjmallett uint64_t twlmrd : 4; /**< Indicates tWLMRD constraints. 2803215976Sjmallett Set TWLMRD (CSR field) = RNDUP[tWLMRD(ns)/(4*tCYC(ns))], 2804215976Sjmallett where tWLMRD is from the DDR3 spec, and tCYC(ns) 2805215976Sjmallett is the DDR clock frequency (not data rate). 2806215976Sjmallett TYP=max(40nCK) */ 2807215976Sjmallett uint64_t txp : 3; /**< Indicates tXP constraints. 2808215976Sjmallett Set TXP (CSR field) = RNDUP[tXP(ns)/tCYC(ns)]-1, 2809215976Sjmallett where tXP is from the DDR3 spec, and tCYC(ns) 2810215976Sjmallett is the DDR clock frequency (not data rate). 2811215976Sjmallett TYP=max(3nCK, 7.5ns) */ 2812215976Sjmallett uint64_t trrd : 3; /**< Indicates tRRD constraints. 2813215976Sjmallett Set TRRD (CSR field) = RNDUP[tRRD(ns)/tCYC(ns)]-2, 2814215976Sjmallett where tRRD is from the DDR3 spec, and tCYC(ns) 2815215976Sjmallett is the DDR clock frequency (not data rate). 2816215976Sjmallett TYP=max(4nCK, 10ns) 2817215976Sjmallett - 000: RESERVED 2818215976Sjmallett - 001: 3 tCYC 2819215976Sjmallett - ... 2820215976Sjmallett - 110: 8 tCYC 2821215976Sjmallett - 111: 9 tCYC */ 2822215976Sjmallett uint64_t trfc : 5; /**< Indicates tRFC constraints. 2823215976Sjmallett Set TRFC (CSR field) = RNDUP[tRFC(ns)/(8*tCYC(ns))], 2824215976Sjmallett where tRFC is from the DDR3 spec, and tCYC(ns) 2825215976Sjmallett is the DDR clock frequency (not data rate). 2826215976Sjmallett TYP=90-350ns 2827215976Sjmallett - 00000: RESERVED 2828215976Sjmallett - 00001: 8 tCYC 2829215976Sjmallett - 00010: 16 tCYC 2830215976Sjmallett - 00011: 24 tCYC 2831215976Sjmallett - 00100: 32 tCYC 2832215976Sjmallett - ... 2833215976Sjmallett - 11110: 240 tCYC 2834215976Sjmallett - 11111: 248 tCYC */ 2835215976Sjmallett uint64_t twtr : 4; /**< Indicates tWTR constraints. 2836215976Sjmallett Set TWTR (CSR field) = RNDUP[tWTR(ns)/tCYC(ns)]-1, 2837215976Sjmallett where tWTR is from the DDR3 spec, and tCYC(ns) 2838215976Sjmallett is the DDR clock frequency (not data rate). 2839215976Sjmallett TYP=max(4nCK, 7.5ns) 2840215976Sjmallett - 0000: RESERVED 2841215976Sjmallett - 0001: 2 2842215976Sjmallett - ... 2843215976Sjmallett - 0111: 8 2844215976Sjmallett - 1000-1111: RESERVED */ 2845215976Sjmallett uint64_t trcd : 4; /**< Indicates tRCD constraints. 2846215976Sjmallett Set TRCD (CSR field) = RNDUP[tRCD(ns)/tCYC(ns)], 2847215976Sjmallett where tRCD is from the DDR3 spec, and tCYC(ns) 2848215976Sjmallett is the DDR clock frequency (not data rate). 2849215976Sjmallett TYP=10-15ns 2850215976Sjmallett - 0000: RESERVED 2851215976Sjmallett - 0001: 2 (2 is the smallest value allowed) 2852215976Sjmallett - 0002: 2 2853215976Sjmallett - ... 2854215976Sjmallett - 1001: 9 2855215976Sjmallett - 1010-1111: RESERVED 2856215976Sjmallett In 2T mode, make this register TRCD-1, not going 2857215976Sjmallett below 2. */ 2858215976Sjmallett uint64_t tras : 5; /**< Indicates tRAS constraints. 2859232812Sjmallett Set [TRAS_EXT[0:0], TRAS[4:0]] (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1, 2860215976Sjmallett where tRAS is from the DDR3 spec, and tCYC(ns) 2861215976Sjmallett is the DDR clock frequency (not data rate). 2862215976Sjmallett TYP=35ns-9*tREFI 2863232812Sjmallett - 000000: RESERVED 2864232812Sjmallett - 000001: 2 tCYC 2865232812Sjmallett - 000010: 3 tCYC 2866215976Sjmallett - ... 2867232812Sjmallett - 111111: 64 tCYC */ 2868215976Sjmallett uint64_t tmprr : 4; /**< Indicates tMPRR constraints. 2869215976Sjmallett Set TMPRR (CSR field) = RNDUP[tMPRR(ns)/tCYC(ns)]-1, 2870215976Sjmallett where tMPRR is from the DDR3 spec, and tCYC(ns) 2871215976Sjmallett is the DDR clock frequency (not data rate). 2872215976Sjmallett TYP=1nCK */ 2873215976Sjmallett#else 2874215976Sjmallett uint64_t tmprr : 4; 2875215976Sjmallett uint64_t tras : 5; 2876215976Sjmallett uint64_t trcd : 4; 2877215976Sjmallett uint64_t twtr : 4; 2878215976Sjmallett uint64_t trfc : 5; 2879215976Sjmallett uint64_t trrd : 3; 2880215976Sjmallett uint64_t txp : 3; 2881215976Sjmallett uint64_t twlmrd : 4; 2882215976Sjmallett uint64_t twldqsen : 4; 2883215976Sjmallett uint64_t tfaw : 5; 2884215976Sjmallett uint64_t txpdll : 5; 2885215976Sjmallett uint64_t tras_ext : 1; 2886215976Sjmallett uint64_t reserved_47_63 : 17; 2887215976Sjmallett#endif 2888215976Sjmallett } s; 2889215976Sjmallett struct cvmx_dfm_timing_params1_s cn63xx; 2890232812Sjmallett struct cvmx_dfm_timing_params1_cn63xxp1 { 2891232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2892215976Sjmallett uint64_t reserved_46_63 : 18; 2893215976Sjmallett uint64_t txpdll : 5; /**< Indicates tXPDLL constraints. 2894215976Sjmallett Set TXPDLL (CSR field) = RNDUP[tXPDLL(ns)/tCYC(ns)]-1, 2895215976Sjmallett where tXPDLL is from the DDR3 spec, and tCYC(ns) 2896215976Sjmallett is the DDR clock frequency (not data rate). 2897215976Sjmallett TYP=max(10nCK, 24ns) */ 2898215976Sjmallett uint64_t tfaw : 5; /**< Indicates tFAW constraints. 2899215976Sjmallett Set TFAW (CSR field) = RNDUP[tFAW(ns)/(4*tCYC(ns))], 2900215976Sjmallett where tFAW is from the DDR3 spec, and tCYC(ns) 2901215976Sjmallett is the DDR clock frequency (not data rate). 2902215976Sjmallett TYP=30-40ns */ 2903215976Sjmallett uint64_t twldqsen : 4; /**< Indicates tWLDQSEN constraints. 2904215976Sjmallett Set TWLDQSEN (CSR field) = RNDUP[tWLDQSEN(ns)/(4*tCYC(ns))], 2905215976Sjmallett where tWLDQSEN is from the DDR3 spec, and tCYC(ns) 2906215976Sjmallett is the DDR clock frequency (not data rate). 2907215976Sjmallett TYP=max(25nCK) */ 2908215976Sjmallett uint64_t twlmrd : 4; /**< Indicates tWLMRD constraints. 2909215976Sjmallett Set TWLMRD (CSR field) = RNDUP[tWLMRD(ns)/(4*tCYC(ns))], 2910215976Sjmallett where tWLMRD is from the DDR3 spec, and tCYC(ns) 2911215976Sjmallett is the DDR clock frequency (not data rate). 2912215976Sjmallett TYP=max(40nCK) */ 2913215976Sjmallett uint64_t txp : 3; /**< Indicates tXP constraints. 2914215976Sjmallett Set TXP (CSR field) = RNDUP[tXP(ns)/tCYC(ns)]-1, 2915215976Sjmallett where tXP is from the DDR3 spec, and tCYC(ns) 2916215976Sjmallett is the DDR clock frequency (not data rate). 2917215976Sjmallett TYP=max(3nCK, 7.5ns) */ 2918215976Sjmallett uint64_t trrd : 3; /**< Indicates tRRD constraints. 2919215976Sjmallett Set TRRD (CSR field) = RNDUP[tRRD(ns)/tCYC(ns)]-2, 2920215976Sjmallett where tRRD is from the DDR3 spec, and tCYC(ns) 2921215976Sjmallett is the DDR clock frequency (not data rate). 2922215976Sjmallett TYP=max(4nCK, 10ns) 2923215976Sjmallett - 000: RESERVED 2924215976Sjmallett - 001: 3 tCYC 2925215976Sjmallett - ... 2926215976Sjmallett - 110: 8 tCYC 2927215976Sjmallett - 111: 9 tCYC */ 2928215976Sjmallett uint64_t trfc : 5; /**< Indicates tRFC constraints. 2929215976Sjmallett Set TRFC (CSR field) = RNDUP[tRFC(ns)/(8*tCYC(ns))], 2930215976Sjmallett where tRFC is from the DDR3 spec, and tCYC(ns) 2931215976Sjmallett is the DDR clock frequency (not data rate). 2932215976Sjmallett TYP=90-350ns 2933215976Sjmallett - 00000: RESERVED 2934215976Sjmallett - 00001: 8 tCYC 2935215976Sjmallett - 00010: 16 tCYC 2936215976Sjmallett - 00011: 24 tCYC 2937215976Sjmallett - 00100: 32 tCYC 2938215976Sjmallett - ... 2939215976Sjmallett - 11110: 240 tCYC 2940215976Sjmallett - 11111: 248 tCYC */ 2941215976Sjmallett uint64_t twtr : 4; /**< Indicates tWTR constraints. 2942215976Sjmallett Set TWTR (CSR field) = RNDUP[tWTR(ns)/tCYC(ns)]-1, 2943215976Sjmallett where tWTR is from the DDR3 spec, and tCYC(ns) 2944215976Sjmallett is the DDR clock frequency (not data rate). 2945215976Sjmallett TYP=max(4nCK, 7.5ns) 2946215976Sjmallett - 0000: RESERVED 2947215976Sjmallett - 0001: 2 2948215976Sjmallett - ... 2949215976Sjmallett - 0111: 8 2950215976Sjmallett - 1000-1111: RESERVED */ 2951215976Sjmallett uint64_t trcd : 4; /**< Indicates tRCD constraints. 2952215976Sjmallett Set TRCD (CSR field) = RNDUP[tRCD(ns)/tCYC(ns)], 2953215976Sjmallett where tRCD is from the DDR3 spec, and tCYC(ns) 2954215976Sjmallett is the DDR clock frequency (not data rate). 2955215976Sjmallett TYP=10-15ns 2956215976Sjmallett - 0000: RESERVED 2957215976Sjmallett - 0001: 2 (2 is the smallest value allowed) 2958215976Sjmallett - 0002: 2 2959215976Sjmallett - ... 2960215976Sjmallett - 1001: 9 2961215976Sjmallett - 1010-1111: RESERVED 2962215976Sjmallett In 2T mode, make this register TRCD-1, not going 2963215976Sjmallett below 2. */ 2964215976Sjmallett uint64_t tras : 5; /**< Indicates tRAS constraints. 2965215976Sjmallett Set TRAS (CSR field) = RNDUP[tRAS(ns)/tCYC(ns)]-1, 2966215976Sjmallett where tRAS is from the DDR3 spec, and tCYC(ns) 2967215976Sjmallett is the DDR clock frequency (not data rate). 2968215976Sjmallett TYP=35ns-9*tREFI 2969215976Sjmallett - 00000: RESERVED 2970215976Sjmallett - 00001: 2 tCYC 2971215976Sjmallett - 00010: 3 tCYC 2972215976Sjmallett - ... 2973215976Sjmallett - 11111: 32 tCYC */ 2974215976Sjmallett uint64_t tmprr : 4; /**< Indicates tMPRR constraints. 2975215976Sjmallett Set TMPRR (CSR field) = RNDUP[tMPRR(ns)/tCYC(ns)]-1, 2976215976Sjmallett where tMPRR is from the DDR3 spec, and tCYC(ns) 2977215976Sjmallett is the DDR clock frequency (not data rate). 2978215976Sjmallett TYP=1nCK */ 2979215976Sjmallett#else 2980215976Sjmallett uint64_t tmprr : 4; 2981215976Sjmallett uint64_t tras : 5; 2982215976Sjmallett uint64_t trcd : 4; 2983215976Sjmallett uint64_t twtr : 4; 2984215976Sjmallett uint64_t trfc : 5; 2985215976Sjmallett uint64_t trrd : 3; 2986215976Sjmallett uint64_t txp : 3; 2987215976Sjmallett uint64_t twlmrd : 4; 2988215976Sjmallett uint64_t twldqsen : 4; 2989215976Sjmallett uint64_t tfaw : 5; 2990215976Sjmallett uint64_t txpdll : 5; 2991215976Sjmallett uint64_t reserved_46_63 : 18; 2992215976Sjmallett#endif 2993215976Sjmallett } cn63xxp1; 2994232812Sjmallett struct cvmx_dfm_timing_params1_s cn66xx; 2995215976Sjmallett}; 2996215976Sjmalletttypedef union cvmx_dfm_timing_params1 cvmx_dfm_timing_params1_t; 2997215976Sjmallett 2998215976Sjmallett/** 2999215976Sjmallett * cvmx_dfm_wlevel_ctl 3000215976Sjmallett */ 3001232812Sjmallettunion cvmx_dfm_wlevel_ctl { 3002215976Sjmallett uint64_t u64; 3003232812Sjmallett struct cvmx_dfm_wlevel_ctl_s { 3004232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3005215976Sjmallett uint64_t reserved_22_63 : 42; 3006215976Sjmallett uint64_t rtt_nom : 3; /**< RTT_NOM 3007215976Sjmallett DFM writes a decoded value to MR1[Rtt_Nom] of the rank during 3008215976Sjmallett write leveling. Per JEDEC DDR3 specifications, 3009215976Sjmallett only values MR1[Rtt_Nom] = 1 (RQZ/4), 2 (RQZ/2), or 3 (RQZ/6) 3010215976Sjmallett are allowed during write leveling with output buffer enabled. 3011215976Sjmallett 000 : DFM writes 001 (RZQ/4) to MR1[Rtt_Nom] 3012215976Sjmallett 001 : DFM writes 010 (RZQ/2) to MR1[Rtt_Nom] 3013215976Sjmallett 010 : DFM writes 011 (RZQ/6) to MR1[Rtt_Nom] 3014215976Sjmallett 011 : DFM writes 100 (RZQ/12) to MR1[Rtt_Nom] 3015215976Sjmallett 100 : DFM writes 101 (RZQ/8) to MR1[Rtt_Nom] 3016215976Sjmallett 101 : DFM writes 110 (Rsvd) to MR1[Rtt_Nom] 3017215976Sjmallett 110 : DFM writes 111 (Rsvd) to MR1[Rtt_Nom] 3018215976Sjmallett 111 : DFM writes 000 (Disabled) to MR1[Rtt_Nom] */ 3019215976Sjmallett uint64_t bitmask : 8; /**< Mask to select bit lanes on which write-leveling 3020215976Sjmallett feedback is returned when OR_DIS is set to 1 */ 3021215976Sjmallett uint64_t or_dis : 1; /**< Disable or'ing of bits in a byte lane when computing 3022215976Sjmallett the write-leveling bitmask */ 3023215976Sjmallett uint64_t sset : 1; /**< Run write-leveling on the current setting only. */ 3024215976Sjmallett uint64_t lanemask : 9; /**< One-hot mask to select byte lane to be leveled by 3025215976Sjmallett the write-leveling sequence 3026215976Sjmallett Used with x16 parts where the upper and lower byte 3027215976Sjmallett lanes need to be leveled independently 3028215976Sjmallett LANEMASK<8:2> must be zero. */ 3029215976Sjmallett#else 3030215976Sjmallett uint64_t lanemask : 9; 3031215976Sjmallett uint64_t sset : 1; 3032215976Sjmallett uint64_t or_dis : 1; 3033215976Sjmallett uint64_t bitmask : 8; 3034215976Sjmallett uint64_t rtt_nom : 3; 3035215976Sjmallett uint64_t reserved_22_63 : 42; 3036215976Sjmallett#endif 3037215976Sjmallett } s; 3038215976Sjmallett struct cvmx_dfm_wlevel_ctl_s cn63xx; 3039232812Sjmallett struct cvmx_dfm_wlevel_ctl_cn63xxp1 { 3040232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3041215976Sjmallett uint64_t reserved_10_63 : 54; 3042215976Sjmallett uint64_t sset : 1; /**< Run write-leveling on the current setting only. */ 3043215976Sjmallett uint64_t lanemask : 9; /**< One-hot mask to select byte lane to be leveled by 3044215976Sjmallett the write-leveling sequence 3045215976Sjmallett Used with x16 parts where the upper and lower byte 3046215976Sjmallett lanes need to be leveled independently 3047215976Sjmallett LANEMASK<8:2> must be zero. */ 3048215976Sjmallett#else 3049215976Sjmallett uint64_t lanemask : 9; 3050215976Sjmallett uint64_t sset : 1; 3051215976Sjmallett uint64_t reserved_10_63 : 54; 3052215976Sjmallett#endif 3053215976Sjmallett } cn63xxp1; 3054232812Sjmallett struct cvmx_dfm_wlevel_ctl_s cn66xx; 3055215976Sjmallett}; 3056215976Sjmalletttypedef union cvmx_dfm_wlevel_ctl cvmx_dfm_wlevel_ctl_t; 3057215976Sjmallett 3058215976Sjmallett/** 3059215976Sjmallett * cvmx_dfm_wlevel_dbg 3060215976Sjmallett * 3061215976Sjmallett * Notes: 3062215976Sjmallett * A given write of DFM_WLEVEL_DBG returns the write-leveling pass/fail results for all possible 3063215976Sjmallett * delay settings (i.e. the BITMASK) for only one byte in the last rank that the HW write-leveled. 3064215976Sjmallett * DFM_WLEVEL_DBG[BYTE] selects the particular byte. 3065215976Sjmallett * To get these pass/fail results for another different rank, you must run the hardware write-leveling 3066215976Sjmallett * again. For example, it is possible to get the BITMASK results for every byte of every rank 3067215976Sjmallett * if you run write-leveling separately for each rank, probing DFM_WLEVEL_DBG between each 3068215976Sjmallett * write-leveling. 3069215976Sjmallett */ 3070232812Sjmallettunion cvmx_dfm_wlevel_dbg { 3071215976Sjmallett uint64_t u64; 3072232812Sjmallett struct cvmx_dfm_wlevel_dbg_s { 3073232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3074215976Sjmallett uint64_t reserved_12_63 : 52; 3075215976Sjmallett uint64_t bitmask : 8; /**< Bitmask generated during deskew settings sweep 3076215976Sjmallett if DFM_WLEVEL_CTL[SSET]=0 3077215976Sjmallett BITMASK[n]=0 means deskew setting n failed 3078215976Sjmallett BITMASK[n]=1 means deskew setting n passed 3079215976Sjmallett for 0 <= n <= 7 3080215976Sjmallett BITMASK contains the first 8 results of the total 16 3081215976Sjmallett collected by DFM during the write-leveling sequence 3082215976Sjmallett else if DFM_WLEVEL_CTL[SSET]=1 3083215976Sjmallett BITMASK[0]=0 means curr deskew setting failed 3084215976Sjmallett BITMASK[0]=1 means curr deskew setting passed */ 3085215976Sjmallett uint64_t byte : 4; /**< 0 <= BYTE <= 8 */ 3086215976Sjmallett#else 3087215976Sjmallett uint64_t byte : 4; 3088215976Sjmallett uint64_t bitmask : 8; 3089215976Sjmallett uint64_t reserved_12_63 : 52; 3090215976Sjmallett#endif 3091215976Sjmallett } s; 3092215976Sjmallett struct cvmx_dfm_wlevel_dbg_s cn63xx; 3093215976Sjmallett struct cvmx_dfm_wlevel_dbg_s cn63xxp1; 3094232812Sjmallett struct cvmx_dfm_wlevel_dbg_s cn66xx; 3095215976Sjmallett}; 3096215976Sjmalletttypedef union cvmx_dfm_wlevel_dbg cvmx_dfm_wlevel_dbg_t; 3097215976Sjmallett 3098215976Sjmallett/** 3099215976Sjmallett * cvmx_dfm_wlevel_rank# 3100215976Sjmallett * 3101215976Sjmallett * Notes: 3102215976Sjmallett * This is TWO CSRs per DFM, one per each rank. (front bunk/back bunk) 3103215976Sjmallett * 3104215976Sjmallett * Deskew setting is measured in units of 1/8 FCLK, so the above BYTE* values can range over 4 FCLKs. 3105215976Sjmallett * 3106215976Sjmallett * Assuming DFM_WLEVEL_CTL[SSET]=0, the BYTE*<2:0> values are not used during write-leveling, and 3107215976Sjmallett * they are over-written by the hardware as part of the write-leveling sequence. (HW sets STATUS==3 3108215976Sjmallett * after HW write-leveling completes for the rank). SW needs to set BYTE*<4:3> bits. 3109215976Sjmallett * 3110215976Sjmallett * Each CSR may also be written by SW, but not while a write-leveling sequence is in progress. (HW sets STATUS==1 after a CSR write.) 3111215976Sjmallett * 3112215976Sjmallett * SW initiates a HW write-leveling sequence by programming DFM_WLEVEL_CTL and writing RANKMASK and INIT_START=1 with SEQUENCE=6 in DFM_CONFIG. 3113215976Sjmallett * DFM will then step through and accumulate write leveling results for 8 unique delay settings (twice), starting at a delay of 3114215976Sjmallett * DFM_WLEVEL_RANKn[BYTE*<4:3>]*8 CK increasing by 1/8 CK each setting. HW will then set DFM_WLEVEL_RANKn[BYTE*<2:0>] to indicate the 3115215976Sjmallett * first write leveling result of '1' that followed a reslt of '0' during the sequence by searching for a '1100' pattern in the generated 3116215976Sjmallett * bitmask, except that DFM will always write DFM_WLEVEL_RANKn[BYTE*<0>]=0. If HW is unable to find a match for a '1100' pattern, then HW will 3117215976Sjmallett * set DFM_WLEVEL_RANKn[BYTE*<2:0>] to 4. 3118215976Sjmallett * See DFM_WLEVEL_CTL. 3119215976Sjmallett */ 3120232812Sjmallettunion cvmx_dfm_wlevel_rankx { 3121215976Sjmallett uint64_t u64; 3122232812Sjmallett struct cvmx_dfm_wlevel_rankx_s { 3123232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3124215976Sjmallett uint64_t reserved_47_63 : 17; 3125215976Sjmallett uint64_t status : 2; /**< Indicates status of the write-leveling and where 3126215976Sjmallett the BYTE* programmings in <44:0> came from: 3127215976Sjmallett 0 = BYTE* values are their reset value 3128215976Sjmallett 1 = BYTE* values were set via a CSR write to this register 3129215976Sjmallett 2 = write-leveling sequence currently in progress (BYTE* values are unpredictable) 3130215976Sjmallett 3 = BYTE* values came from a complete write-leveling sequence, irrespective of 3131215976Sjmallett which lanes are masked via DFM_WLEVEL_CTL[LANEMASK] */ 3132215976Sjmallett uint64_t reserved_10_44 : 35; 3133215976Sjmallett uint64_t byte1 : 5; /**< Deskew setting 3134215976Sjmallett Bit 0 of BYTE1 must be zero during normal operation */ 3135215976Sjmallett uint64_t byte0 : 5; /**< Deskew setting 3136215976Sjmallett Bit 0 of BYTE0 must be zero during normal operation */ 3137215976Sjmallett#else 3138215976Sjmallett uint64_t byte0 : 5; 3139215976Sjmallett uint64_t byte1 : 5; 3140215976Sjmallett uint64_t reserved_10_44 : 35; 3141215976Sjmallett uint64_t status : 2; 3142215976Sjmallett uint64_t reserved_47_63 : 17; 3143215976Sjmallett#endif 3144215976Sjmallett } s; 3145215976Sjmallett struct cvmx_dfm_wlevel_rankx_s cn63xx; 3146215976Sjmallett struct cvmx_dfm_wlevel_rankx_s cn63xxp1; 3147232812Sjmallett struct cvmx_dfm_wlevel_rankx_s cn66xx; 3148215976Sjmallett}; 3149215976Sjmalletttypedef union cvmx_dfm_wlevel_rankx cvmx_dfm_wlevel_rankx_t; 3150215976Sjmallett 3151215976Sjmallett/** 3152215976Sjmallett * cvmx_dfm_wodt_mask 3153215976Sjmallett * 3154215976Sjmallett * DFM_WODT_MASK = DFM Write OnDieTermination mask 3155215976Sjmallett * System designers may desire to terminate DQ/DQS/DM lines for higher frequency DDR operations 3156215976Sjmallett * especially on a multi-rank system. DDR3 DQ/DM/DQS I/O's have built in 3157215976Sjmallett * Termination resistor that can be turned on or off by the controller, after meeting tAOND and tAOF 3158215976Sjmallett * timing requirements. Each Rank has its own ODT pin that fans out to all the memory parts 3159215976Sjmallett * in that rank. System designers may prefer different combinations of ODT ON's for writes 3160215976Sjmallett * into different ranks. Octeon supports full programmability by way of the mask register below. 3161215976Sjmallett * Each Rank position has its own 8-bit programmable field. 3162215976Sjmallett * When the controller does a write to that rank, it sets the 4 ODT pins to the MASK pins below. 3163215976Sjmallett * For eg., When doing a write into Rank0, a system designer may desire to terminate the lines 3164215976Sjmallett * with the resistor on Dimm0/Rank1. The mask WODT_D0_R0 would then be [00000010]. 3165215976Sjmallett * Octeon drives the appropriate mask values on the ODT pins by default. If this feature is not 3166215976Sjmallett * required, write 0 in this register. 3167215976Sjmallett * 3168215976Sjmallett * Notes: 3169215976Sjmallett * - DFM_WODT_MASK functions a little differently than DFM_RODT_MASK. While, in DFM_RODT_MASK, the other 3170215976Sjmallett * rank(s) are ODT-ed, in DFM_WODT_MASK, the rank in which the write CAS is issued can be ODT-ed as well. 3171215976Sjmallett * - For a two rank system and a write op to rank0: use RODT_D0_R0<1:0> to terminate lines on rank1 and/or rank0. 3172215976Sjmallett * - For a two rank system and a write op to rank1: use RODT_D0_R1<1:0> to terminate lines on rank1 and/or rank0. 3173215976Sjmallett * - When a given RANK is selected, the WODT mask for that RANK is used. 3174215976Sjmallett * 3175215976Sjmallett * DFM always writes 128-bit words independently via one write CAS operation per word. 3176215976Sjmallett * When a WODT mask bit is set, DFM asserts the OCTEON ODT output pin(s) starting the same cycle 3177215976Sjmallett * as the write CAS operation. Then, OCTEON normally continues to assert the ODT output pin(s) for five 3178215976Sjmallett * more cycles - for a total of 6 cycles for the entire word write - satisfying the 6 cycle DDR3 3179215976Sjmallett * ODTH8 requirements. But it is possible for DFM to issue two word writes separated by as few 3180215976Sjmallett * as WtW = 4 or 5 cycles. In that case, DFM asserts the ODT output pin(s) for the WODT mask of the 3181215976Sjmallett * first word write for WtW cycles, then asserts the ODT output pin(s) for the WODT mask of the 3182215976Sjmallett * second write for 6 cycles (or less if a third word write follows within 4 or 5 3183215976Sjmallett * cycles of this second word write). Note that it may be necessary to force DFM to space back-to-back 3184215976Sjmallett * word writes to different ranks apart by at least 6 cycles to prevent DDR3 ODTH8 violations. 3185215976Sjmallett */ 3186232812Sjmallettunion cvmx_dfm_wodt_mask { 3187215976Sjmallett uint64_t u64; 3188232812Sjmallett struct cvmx_dfm_wodt_mask_s { 3189232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3190215976Sjmallett uint64_t wodt_d3_r1 : 8; /**< Not used by DFM. */ 3191215976Sjmallett uint64_t wodt_d3_r0 : 8; /**< Not used by DFM. */ 3192215976Sjmallett uint64_t wodt_d2_r1 : 8; /**< Not used by DFM. */ 3193215976Sjmallett uint64_t wodt_d2_r0 : 8; /**< Not used by DFM. */ 3194215976Sjmallett uint64_t wodt_d1_r1 : 8; /**< Not used by DFM. */ 3195215976Sjmallett uint64_t wodt_d1_r0 : 8; /**< Not used by DFM. */ 3196215976Sjmallett uint64_t wodt_d0_r1 : 8; /**< Write ODT mask RANK1 3197215976Sjmallett WODT_D0_R1<7:2> not used by DFM. 3198215976Sjmallett WODT_D0_R1<1:0> is also not used by DFM when RANK_ENA is not set. */ 3199215976Sjmallett uint64_t wodt_d0_r0 : 8; /**< Write ODT mask RANK0 3200215976Sjmallett WODT_D0_R0<7:2> not used by DFM. */ 3201215976Sjmallett#else 3202215976Sjmallett uint64_t wodt_d0_r0 : 8; 3203215976Sjmallett uint64_t wodt_d0_r1 : 8; 3204215976Sjmallett uint64_t wodt_d1_r0 : 8; 3205215976Sjmallett uint64_t wodt_d1_r1 : 8; 3206215976Sjmallett uint64_t wodt_d2_r0 : 8; 3207215976Sjmallett uint64_t wodt_d2_r1 : 8; 3208215976Sjmallett uint64_t wodt_d3_r0 : 8; 3209215976Sjmallett uint64_t wodt_d3_r1 : 8; 3210215976Sjmallett#endif 3211215976Sjmallett } s; 3212215976Sjmallett struct cvmx_dfm_wodt_mask_s cn63xx; 3213215976Sjmallett struct cvmx_dfm_wodt_mask_s cn63xxp1; 3214232812Sjmallett struct cvmx_dfm_wodt_mask_s cn66xx; 3215215976Sjmallett}; 3216215976Sjmalletttypedef union cvmx_dfm_wodt_mask cvmx_dfm_wodt_mask_t; 3217215976Sjmallett 3218215976Sjmallett#endif 3219