1232809Sjmallett/***********************license start*************** 2232809Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3232809Sjmallett * reserved. 4232809Sjmallett * 5232809Sjmallett * 6232809Sjmallett * Redistribution and use in source and binary forms, with or without 7232809Sjmallett * modification, are permitted provided that the following conditions are 8232809Sjmallett * met: 9232809Sjmallett * 10232809Sjmallett * * Redistributions of source code must retain the above copyright 11232809Sjmallett * notice, this list of conditions and the following disclaimer. 12232809Sjmallett * 13232809Sjmallett * * Redistributions in binary form must reproduce the above 14232809Sjmallett * copyright notice, this list of conditions and the following 15232809Sjmallett * disclaimer in the documentation and/or other materials provided 16232809Sjmallett * with the distribution. 17232809Sjmallett 18232809Sjmallett * * Neither the name of Cavium Inc. nor the names of 19232809Sjmallett * its contributors may be used to endorse or promote products 20232809Sjmallett * derived from this software without specific prior written 21232809Sjmallett * permission. 22232809Sjmallett 23232809Sjmallett * This Software, including technical data, may be subject to U.S. export control 24232809Sjmallett * laws, including the U.S. Export Administration Act and its associated 25232809Sjmallett * regulations, and may be subject to export or import regulations in other 26232809Sjmallett * countries. 27232809Sjmallett 28232809Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232809Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30232809Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31232809Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32232809Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33232809Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34232809Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35232809Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36232809Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37232809Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38232809Sjmallett ***********************license end**************************************/ 39232809Sjmallett 40232809Sjmallett 41232809Sjmallett/** 42232809Sjmallett * cvmx-ciu2-defs.h 43232809Sjmallett * 44232809Sjmallett * Configuration and status register (CSR) type definitions for 45232809Sjmallett * Octeon ciu2. 46232809Sjmallett * 47232809Sjmallett * This file is auto generated. Do not edit. 48232809Sjmallett * 49232809Sjmallett * <hr>$Revision$<hr> 50232809Sjmallett * 51232809Sjmallett */ 52232809Sjmallett#ifndef __CVMX_CIU2_DEFS_H__ 53232809Sjmallett#define __CVMX_CIU2_DEFS_H__ 54232809Sjmallett 55232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56232809Sjmallettstatic inline uint64_t CVMX_CIU2_ACK_IOX_INT(unsigned long block_id) 57232809Sjmallett{ 58232809Sjmallett if (!( 59232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 60232809Sjmallett cvmx_warn("CVMX_CIU2_ACK_IOX_INT(%lu) is invalid on this chip\n", block_id); 61232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull; 62232809Sjmallett} 63232809Sjmallett#else 64232809Sjmallett#define CVMX_CIU2_ACK_IOX_INT(block_id) (CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull) 65232809Sjmallett#endif 66232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67232809Sjmallettstatic inline uint64_t CVMX_CIU2_ACK_PPX_IP2(unsigned long block_id) 68232809Sjmallett{ 69232809Sjmallett if (!( 70232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 71232809Sjmallett cvmx_warn("CVMX_CIU2_ACK_PPX_IP2(%lu) is invalid on this chip\n", block_id); 72232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull; 73232809Sjmallett} 74232809Sjmallett#else 75232809Sjmallett#define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull) 76232809Sjmallett#endif 77232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78232809Sjmallettstatic inline uint64_t CVMX_CIU2_ACK_PPX_IP3(unsigned long block_id) 79232809Sjmallett{ 80232809Sjmallett if (!( 81232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 82232809Sjmallett cvmx_warn("CVMX_CIU2_ACK_PPX_IP3(%lu) is invalid on this chip\n", block_id); 83232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull; 84232809Sjmallett} 85232809Sjmallett#else 86232809Sjmallett#define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull) 87232809Sjmallett#endif 88232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89232809Sjmallettstatic inline uint64_t CVMX_CIU2_ACK_PPX_IP4(unsigned long block_id) 90232809Sjmallett{ 91232809Sjmallett if (!( 92232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 93232809Sjmallett cvmx_warn("CVMX_CIU2_ACK_PPX_IP4(%lu) is invalid on this chip\n", block_id); 94232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull; 95232809Sjmallett} 96232809Sjmallett#else 97232809Sjmallett#define CVMX_CIU2_ACK_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull) 98232809Sjmallett#endif 99232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_GPIO(unsigned long block_id) 101232809Sjmallett{ 102232809Sjmallett if (!( 103232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 104232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_GPIO(%lu) is invalid on this chip\n", block_id); 105232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull; 106232809Sjmallett} 107232809Sjmallett#else 108232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull) 109232809Sjmallett#endif 110232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_GPIO_W1C(unsigned long block_id) 112232809Sjmallett{ 113232809Sjmallett if (!( 114232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 115232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_GPIO_W1C(%lu) is invalid on this chip\n", block_id); 116232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull; 117232809Sjmallett} 118232809Sjmallett#else 119232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull) 120232809Sjmallett#endif 121232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_GPIO_W1S(unsigned long block_id) 123232809Sjmallett{ 124232809Sjmallett if (!( 125232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 126232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_GPIO_W1S(%lu) is invalid on this chip\n", block_id); 127232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull; 128232809Sjmallett} 129232809Sjmallett#else 130232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull) 131232809Sjmallett#endif 132232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_IO(unsigned long block_id) 134232809Sjmallett{ 135232809Sjmallett if (!( 136232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 137232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_IO(%lu) is invalid on this chip\n", block_id); 138232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull; 139232809Sjmallett} 140232809Sjmallett#else 141232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull) 142232809Sjmallett#endif 143232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_IO_W1C(unsigned long block_id) 145232809Sjmallett{ 146232809Sjmallett if (!( 147232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 148232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_IO_W1C(%lu) is invalid on this chip\n", block_id); 149232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull; 150232809Sjmallett} 151232809Sjmallett#else 152232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull) 153232809Sjmallett#endif 154232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_IO_W1S(unsigned long block_id) 156232809Sjmallett{ 157232809Sjmallett if (!( 158232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 159232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_IO_W1S(%lu) is invalid on this chip\n", block_id); 160232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull; 161232809Sjmallett} 162232809Sjmallett#else 163232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull) 164232809Sjmallett#endif 165232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_MBOX(unsigned long block_id) 167232809Sjmallett{ 168232809Sjmallett if (!( 169232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 170232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_MBOX(%lu) is invalid on this chip\n", block_id); 171232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull; 172232809Sjmallett} 173232809Sjmallett#else 174232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull) 175232809Sjmallett#endif 176232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_MBOX_W1C(unsigned long block_id) 178232809Sjmallett{ 179232809Sjmallett if (!( 180232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 181232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_MBOX_W1C(%lu) is invalid on this chip\n", block_id); 182232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull; 183232809Sjmallett} 184232809Sjmallett#else 185232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull) 186232809Sjmallett#endif 187232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_MBOX_W1S(unsigned long block_id) 189232809Sjmallett{ 190232809Sjmallett if (!( 191232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 192232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_MBOX_W1S(%lu) is invalid on this chip\n", block_id); 193232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull; 194232809Sjmallett} 195232809Sjmallett#else 196232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull) 197232809Sjmallett#endif 198232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_MEM(unsigned long block_id) 200232809Sjmallett{ 201232809Sjmallett if (!( 202232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 203232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_MEM(%lu) is invalid on this chip\n", block_id); 204232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull; 205232809Sjmallett} 206232809Sjmallett#else 207232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull) 208232809Sjmallett#endif 209232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_MEM_W1C(unsigned long block_id) 211232809Sjmallett{ 212232809Sjmallett if (!( 213232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 214232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_MEM_W1C(%lu) is invalid on this chip\n", block_id); 215232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull; 216232809Sjmallett} 217232809Sjmallett#else 218232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull) 219232809Sjmallett#endif 220232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_MEM_W1S(unsigned long block_id) 222232809Sjmallett{ 223232809Sjmallett if (!( 224232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 225232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_MEM_W1S(%lu) is invalid on this chip\n", block_id); 226232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull; 227232809Sjmallett} 228232809Sjmallett#else 229232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull) 230232809Sjmallett#endif 231232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_MIO(unsigned long block_id) 233232809Sjmallett{ 234232809Sjmallett if (!( 235232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 236232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_MIO(%lu) is invalid on this chip\n", block_id); 237232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull; 238232809Sjmallett} 239232809Sjmallett#else 240232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull) 241232809Sjmallett#endif 242232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_MIO_W1C(unsigned long block_id) 244232809Sjmallett{ 245232809Sjmallett if (!( 246232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 247232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_MIO_W1C(%lu) is invalid on this chip\n", block_id); 248232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull; 249232809Sjmallett} 250232809Sjmallett#else 251232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull) 252232809Sjmallett#endif 253232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_MIO_W1S(unsigned long block_id) 255232809Sjmallett{ 256232809Sjmallett if (!( 257232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 258232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_MIO_W1S(%lu) is invalid on this chip\n", block_id); 259232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull; 260232809Sjmallett} 261232809Sjmallett#else 262232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull) 263232809Sjmallett#endif 264232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_PKT(unsigned long block_id) 266232809Sjmallett{ 267232809Sjmallett if (!( 268232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 269232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_PKT(%lu) is invalid on this chip\n", block_id); 270232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull; 271232809Sjmallett} 272232809Sjmallett#else 273232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull) 274232809Sjmallett#endif 275232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_PKT_W1C(unsigned long block_id) 277232809Sjmallett{ 278232809Sjmallett if (!( 279232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 280232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_PKT_W1C(%lu) is invalid on this chip\n", block_id); 281232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull; 282232809Sjmallett} 283232809Sjmallett#else 284232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull) 285232809Sjmallett#endif 286232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_PKT_W1S(unsigned long block_id) 288232809Sjmallett{ 289232809Sjmallett if (!( 290232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 291232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_PKT_W1S(%lu) is invalid on this chip\n", block_id); 292232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull; 293232809Sjmallett} 294232809Sjmallett#else 295232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull) 296232809Sjmallett#endif 297232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_RML(unsigned long block_id) 299232809Sjmallett{ 300232809Sjmallett if (!( 301232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 302232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_RML(%lu) is invalid on this chip\n", block_id); 303232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull; 304232809Sjmallett} 305232809Sjmallett#else 306232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull) 307232809Sjmallett#endif 308232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_RML_W1C(unsigned long block_id) 310232809Sjmallett{ 311232809Sjmallett if (!( 312232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 313232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_RML_W1C(%lu) is invalid on this chip\n", block_id); 314232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull; 315232809Sjmallett} 316232809Sjmallett#else 317232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull) 318232809Sjmallett#endif 319232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_RML_W1S(unsigned long block_id) 321232809Sjmallett{ 322232809Sjmallett if (!( 323232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 324232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_RML_W1S(%lu) is invalid on this chip\n", block_id); 325232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull; 326232809Sjmallett} 327232809Sjmallett#else 328232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull) 329232809Sjmallett#endif 330232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_WDOG(unsigned long block_id) 332232809Sjmallett{ 333232809Sjmallett if (!( 334232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 335232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_WDOG(%lu) is invalid on this chip\n", block_id); 336232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull; 337232809Sjmallett} 338232809Sjmallett#else 339232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull) 340232809Sjmallett#endif 341232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_WDOG_W1C(unsigned long block_id) 343232809Sjmallett{ 344232809Sjmallett if (!( 345232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 346232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_WDOG_W1C(%lu) is invalid on this chip\n", block_id); 347232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull; 348232809Sjmallett} 349232809Sjmallett#else 350232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull) 351232809Sjmallett#endif 352232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 353232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_WDOG_W1S(unsigned long block_id) 354232809Sjmallett{ 355232809Sjmallett if (!( 356232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 357232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_WDOG_W1S(%lu) is invalid on this chip\n", block_id); 358232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull; 359232809Sjmallett} 360232809Sjmallett#else 361232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull) 362232809Sjmallett#endif 363232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 364232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_WRKQ(unsigned long block_id) 365232809Sjmallett{ 366232809Sjmallett if (!( 367232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 368232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_WRKQ(%lu) is invalid on this chip\n", block_id); 369232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull; 370232809Sjmallett} 371232809Sjmallett#else 372232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull) 373232809Sjmallett#endif 374232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 375232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(unsigned long block_id) 376232809Sjmallett{ 377232809Sjmallett if (!( 378232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 379232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(%lu) is invalid on this chip\n", block_id); 380232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull; 381232809Sjmallett} 382232809Sjmallett#else 383232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull) 384232809Sjmallett#endif 385232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(unsigned long block_id) 387232809Sjmallett{ 388232809Sjmallett if (!( 389232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 390232809Sjmallett cvmx_warn("CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(%lu) is invalid on this chip\n", block_id); 391232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull; 392232809Sjmallett} 393232809Sjmallett#else 394232809Sjmallett#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull) 395232809Sjmallett#endif 396232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_GPIO(unsigned long block_id) 398232809Sjmallett{ 399232809Sjmallett if (!( 400232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 401232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_GPIO(%lu) is invalid on this chip\n", block_id); 402232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull; 403232809Sjmallett} 404232809Sjmallett#else 405232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull) 406232809Sjmallett#endif 407232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(unsigned long block_id) 409232809Sjmallett{ 410232809Sjmallett if (!( 411232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 412232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(%lu) is invalid on this chip\n", block_id); 413232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull; 414232809Sjmallett} 415232809Sjmallett#else 416232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull) 417232809Sjmallett#endif 418232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 419232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(unsigned long block_id) 420232809Sjmallett{ 421232809Sjmallett if (!( 422232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 423232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(%lu) is invalid on this chip\n", block_id); 424232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull; 425232809Sjmallett} 426232809Sjmallett#else 427232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull) 428232809Sjmallett#endif 429232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_IO(unsigned long block_id) 431232809Sjmallett{ 432232809Sjmallett if (!( 433232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 434232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_IO(%lu) is invalid on this chip\n", block_id); 435232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull; 436232809Sjmallett} 437232809Sjmallett#else 438232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull) 439232809Sjmallett#endif 440232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_IO_W1C(unsigned long block_id) 442232809Sjmallett{ 443232809Sjmallett if (!( 444232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 445232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_IO_W1C(%lu) is invalid on this chip\n", block_id); 446232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull; 447232809Sjmallett} 448232809Sjmallett#else 449232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull) 450232809Sjmallett#endif 451232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_IO_W1S(unsigned long block_id) 453232809Sjmallett{ 454232809Sjmallett if (!( 455232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 456232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_IO_W1S(%lu) is invalid on this chip\n", block_id); 457232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull; 458232809Sjmallett} 459232809Sjmallett#else 460232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull) 461232809Sjmallett#endif 462232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_MBOX(unsigned long block_id) 464232809Sjmallett{ 465232809Sjmallett if (!( 466232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 467232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MBOX(%lu) is invalid on this chip\n", block_id); 468232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull; 469232809Sjmallett} 470232809Sjmallett#else 471232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull) 472232809Sjmallett#endif 473232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(unsigned long block_id) 475232809Sjmallett{ 476232809Sjmallett if (!( 477232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 478232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(%lu) is invalid on this chip\n", block_id); 479232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull; 480232809Sjmallett} 481232809Sjmallett#else 482232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull) 483232809Sjmallett#endif 484232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(unsigned long block_id) 486232809Sjmallett{ 487232809Sjmallett if (!( 488232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 489232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(%lu) is invalid on this chip\n", block_id); 490232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull; 491232809Sjmallett} 492232809Sjmallett#else 493232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull) 494232809Sjmallett#endif 495232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_MEM(unsigned long block_id) 497232809Sjmallett{ 498232809Sjmallett if (!( 499232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 500232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MEM(%lu) is invalid on this chip\n", block_id); 501232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull; 502232809Sjmallett} 503232809Sjmallett#else 504232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull) 505232809Sjmallett#endif 506232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_MEM_W1C(unsigned long block_id) 508232809Sjmallett{ 509232809Sjmallett if (!( 510232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 511232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MEM_W1C(%lu) is invalid on this chip\n", block_id); 512232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull; 513232809Sjmallett} 514232809Sjmallett#else 515232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull) 516232809Sjmallett#endif 517232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_MEM_W1S(unsigned long block_id) 519232809Sjmallett{ 520232809Sjmallett if (!( 521232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 522232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MEM_W1S(%lu) is invalid on this chip\n", block_id); 523232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull; 524232809Sjmallett} 525232809Sjmallett#else 526232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull) 527232809Sjmallett#endif 528232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_MIO(unsigned long block_id) 530232809Sjmallett{ 531232809Sjmallett if (!( 532232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 533232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MIO(%lu) is invalid on this chip\n", block_id); 534232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull; 535232809Sjmallett} 536232809Sjmallett#else 537232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull) 538232809Sjmallett#endif 539232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_MIO_W1C(unsigned long block_id) 541232809Sjmallett{ 542232809Sjmallett if (!( 543232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 544232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MIO_W1C(%lu) is invalid on this chip\n", block_id); 545232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull; 546232809Sjmallett} 547232809Sjmallett#else 548232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull) 549232809Sjmallett#endif 550232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_MIO_W1S(unsigned long block_id) 552232809Sjmallett{ 553232809Sjmallett if (!( 554232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 555232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MIO_W1S(%lu) is invalid on this chip\n", block_id); 556232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull; 557232809Sjmallett} 558232809Sjmallett#else 559232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull) 560232809Sjmallett#endif 561232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_PKT(unsigned long block_id) 563232809Sjmallett{ 564232809Sjmallett if (!( 565232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 566232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_PKT(%lu) is invalid on this chip\n", block_id); 567232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull; 568232809Sjmallett} 569232809Sjmallett#else 570232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull) 571232809Sjmallett#endif 572232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 573232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_PKT_W1C(unsigned long block_id) 574232809Sjmallett{ 575232809Sjmallett if (!( 576232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 577232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_PKT_W1C(%lu) is invalid on this chip\n", block_id); 578232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull; 579232809Sjmallett} 580232809Sjmallett#else 581232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull) 582232809Sjmallett#endif 583232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 584232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_PKT_W1S(unsigned long block_id) 585232809Sjmallett{ 586232809Sjmallett if (!( 587232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 588232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_PKT_W1S(%lu) is invalid on this chip\n", block_id); 589232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull; 590232809Sjmallett} 591232809Sjmallett#else 592232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull) 593232809Sjmallett#endif 594232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 595232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_RML(unsigned long block_id) 596232809Sjmallett{ 597232809Sjmallett if (!( 598232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 599232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_RML(%lu) is invalid on this chip\n", block_id); 600232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull; 601232809Sjmallett} 602232809Sjmallett#else 603232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull) 604232809Sjmallett#endif 605232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 606232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_RML_W1C(unsigned long block_id) 607232809Sjmallett{ 608232809Sjmallett if (!( 609232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 610232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_RML_W1C(%lu) is invalid on this chip\n", block_id); 611232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull; 612232809Sjmallett} 613232809Sjmallett#else 614232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull) 615232809Sjmallett#endif 616232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_RML_W1S(unsigned long block_id) 618232809Sjmallett{ 619232809Sjmallett if (!( 620232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 621232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_RML_W1S(%lu) is invalid on this chip\n", block_id); 622232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull; 623232809Sjmallett} 624232809Sjmallett#else 625232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull) 626232809Sjmallett#endif 627232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_WDOG(unsigned long block_id) 629232809Sjmallett{ 630232809Sjmallett if (!( 631232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 632232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WDOG(%lu) is invalid on this chip\n", block_id); 633232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull; 634232809Sjmallett} 635232809Sjmallett#else 636232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull) 637232809Sjmallett#endif 638232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 639232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(unsigned long block_id) 640232809Sjmallett{ 641232809Sjmallett if (!( 642232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 643232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(%lu) is invalid on this chip\n", block_id); 644232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull; 645232809Sjmallett} 646232809Sjmallett#else 647232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull) 648232809Sjmallett#endif 649232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(unsigned long block_id) 651232809Sjmallett{ 652232809Sjmallett if (!( 653232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 654232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(%lu) is invalid on this chip\n", block_id); 655232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull; 656232809Sjmallett} 657232809Sjmallett#else 658232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull) 659232809Sjmallett#endif 660232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_WRKQ(unsigned long block_id) 662232809Sjmallett{ 663232809Sjmallett if (!( 664232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 665232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WRKQ(%lu) is invalid on this chip\n", block_id); 666232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull; 667232809Sjmallett} 668232809Sjmallett#else 669232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull) 670232809Sjmallett#endif 671232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(unsigned long block_id) 673232809Sjmallett{ 674232809Sjmallett if (!( 675232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 676232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(%lu) is invalid on this chip\n", block_id); 677232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull; 678232809Sjmallett} 679232809Sjmallett#else 680232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull) 681232809Sjmallett#endif 682232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 683232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(unsigned long block_id) 684232809Sjmallett{ 685232809Sjmallett if (!( 686232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 687232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(%lu) is invalid on this chip\n", block_id); 688232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull; 689232809Sjmallett} 690232809Sjmallett#else 691232809Sjmallett#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull) 692232809Sjmallett#endif 693232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 694232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_GPIO(unsigned long block_id) 695232809Sjmallett{ 696232809Sjmallett if (!( 697232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 698232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_GPIO(%lu) is invalid on this chip\n", block_id); 699232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull; 700232809Sjmallett} 701232809Sjmallett#else 702232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull) 703232809Sjmallett#endif 704232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 705232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(unsigned long block_id) 706232809Sjmallett{ 707232809Sjmallett if (!( 708232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 709232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(%lu) is invalid on this chip\n", block_id); 710232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull; 711232809Sjmallett} 712232809Sjmallett#else 713232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull) 714232809Sjmallett#endif 715232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(unsigned long block_id) 717232809Sjmallett{ 718232809Sjmallett if (!( 719232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 720232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(%lu) is invalid on this chip\n", block_id); 721232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull; 722232809Sjmallett} 723232809Sjmallett#else 724232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull) 725232809Sjmallett#endif 726232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 727232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_IO(unsigned long block_id) 728232809Sjmallett{ 729232809Sjmallett if (!( 730232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 731232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_IO(%lu) is invalid on this chip\n", block_id); 732232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull; 733232809Sjmallett} 734232809Sjmallett#else 735232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull) 736232809Sjmallett#endif 737232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 738232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_IO_W1C(unsigned long block_id) 739232809Sjmallett{ 740232809Sjmallett if (!( 741232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 742232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_IO_W1C(%lu) is invalid on this chip\n", block_id); 743232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull; 744232809Sjmallett} 745232809Sjmallett#else 746232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull) 747232809Sjmallett#endif 748232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 749232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_IO_W1S(unsigned long block_id) 750232809Sjmallett{ 751232809Sjmallett if (!( 752232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 753232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_IO_W1S(%lu) is invalid on this chip\n", block_id); 754232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull; 755232809Sjmallett} 756232809Sjmallett#else 757232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull) 758232809Sjmallett#endif 759232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 760232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_MBOX(unsigned long block_id) 761232809Sjmallett{ 762232809Sjmallett if (!( 763232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 764232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MBOX(%lu) is invalid on this chip\n", block_id); 765232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull; 766232809Sjmallett} 767232809Sjmallett#else 768232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull) 769232809Sjmallett#endif 770232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 771232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(unsigned long block_id) 772232809Sjmallett{ 773232809Sjmallett if (!( 774232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 775232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(%lu) is invalid on this chip\n", block_id); 776232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull; 777232809Sjmallett} 778232809Sjmallett#else 779232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull) 780232809Sjmallett#endif 781232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 782232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(unsigned long block_id) 783232809Sjmallett{ 784232809Sjmallett if (!( 785232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 786232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(%lu) is invalid on this chip\n", block_id); 787232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull; 788232809Sjmallett} 789232809Sjmallett#else 790232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull) 791232809Sjmallett#endif 792232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 793232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_MEM(unsigned long block_id) 794232809Sjmallett{ 795232809Sjmallett if (!( 796232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 797232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MEM(%lu) is invalid on this chip\n", block_id); 798232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull; 799232809Sjmallett} 800232809Sjmallett#else 801232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull) 802232809Sjmallett#endif 803232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 804232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_MEM_W1C(unsigned long block_id) 805232809Sjmallett{ 806232809Sjmallett if (!( 807232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 808232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MEM_W1C(%lu) is invalid on this chip\n", block_id); 809232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull; 810232809Sjmallett} 811232809Sjmallett#else 812232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull) 813232809Sjmallett#endif 814232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 815232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_MEM_W1S(unsigned long block_id) 816232809Sjmallett{ 817232809Sjmallett if (!( 818232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 819232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MEM_W1S(%lu) is invalid on this chip\n", block_id); 820232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull; 821232809Sjmallett} 822232809Sjmallett#else 823232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull) 824232809Sjmallett#endif 825232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 826232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_MIO(unsigned long block_id) 827232809Sjmallett{ 828232809Sjmallett if (!( 829232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 830232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MIO(%lu) is invalid on this chip\n", block_id); 831232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull; 832232809Sjmallett} 833232809Sjmallett#else 834232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull) 835232809Sjmallett#endif 836232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 837232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_MIO_W1C(unsigned long block_id) 838232809Sjmallett{ 839232809Sjmallett if (!( 840232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 841232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MIO_W1C(%lu) is invalid on this chip\n", block_id); 842232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull; 843232809Sjmallett} 844232809Sjmallett#else 845232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull) 846232809Sjmallett#endif 847232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 848232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_MIO_W1S(unsigned long block_id) 849232809Sjmallett{ 850232809Sjmallett if (!( 851232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 852232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MIO_W1S(%lu) is invalid on this chip\n", block_id); 853232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull; 854232809Sjmallett} 855232809Sjmallett#else 856232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull) 857232809Sjmallett#endif 858232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 859232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_PKT(unsigned long block_id) 860232809Sjmallett{ 861232809Sjmallett if (!( 862232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 863232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_PKT(%lu) is invalid on this chip\n", block_id); 864232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull; 865232809Sjmallett} 866232809Sjmallett#else 867232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull) 868232809Sjmallett#endif 869232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 870232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_PKT_W1C(unsigned long block_id) 871232809Sjmallett{ 872232809Sjmallett if (!( 873232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 874232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_PKT_W1C(%lu) is invalid on this chip\n", block_id); 875232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull; 876232809Sjmallett} 877232809Sjmallett#else 878232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull) 879232809Sjmallett#endif 880232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 881232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_PKT_W1S(unsigned long block_id) 882232809Sjmallett{ 883232809Sjmallett if (!( 884232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 885232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_PKT_W1S(%lu) is invalid on this chip\n", block_id); 886232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull; 887232809Sjmallett} 888232809Sjmallett#else 889232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull) 890232809Sjmallett#endif 891232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 892232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_RML(unsigned long block_id) 893232809Sjmallett{ 894232809Sjmallett if (!( 895232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 896232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_RML(%lu) is invalid on this chip\n", block_id); 897232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull; 898232809Sjmallett} 899232809Sjmallett#else 900232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull) 901232809Sjmallett#endif 902232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 903232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_RML_W1C(unsigned long block_id) 904232809Sjmallett{ 905232809Sjmallett if (!( 906232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 907232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_RML_W1C(%lu) is invalid on this chip\n", block_id); 908232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull; 909232809Sjmallett} 910232809Sjmallett#else 911232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull) 912232809Sjmallett#endif 913232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 914232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_RML_W1S(unsigned long block_id) 915232809Sjmallett{ 916232809Sjmallett if (!( 917232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 918232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_RML_W1S(%lu) is invalid on this chip\n", block_id); 919232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull; 920232809Sjmallett} 921232809Sjmallett#else 922232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull) 923232809Sjmallett#endif 924232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 925232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_WDOG(unsigned long block_id) 926232809Sjmallett{ 927232809Sjmallett if (!( 928232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 929232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WDOG(%lu) is invalid on this chip\n", block_id); 930232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull; 931232809Sjmallett} 932232809Sjmallett#else 933232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull) 934232809Sjmallett#endif 935232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 936232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(unsigned long block_id) 937232809Sjmallett{ 938232809Sjmallett if (!( 939232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 940232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(%lu) is invalid on this chip\n", block_id); 941232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull; 942232809Sjmallett} 943232809Sjmallett#else 944232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull) 945232809Sjmallett#endif 946232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 947232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(unsigned long block_id) 948232809Sjmallett{ 949232809Sjmallett if (!( 950232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 951232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(%lu) is invalid on this chip\n", block_id); 952232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull; 953232809Sjmallett} 954232809Sjmallett#else 955232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull) 956232809Sjmallett#endif 957232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 958232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_WRKQ(unsigned long block_id) 959232809Sjmallett{ 960232809Sjmallett if (!( 961232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 962232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WRKQ(%lu) is invalid on this chip\n", block_id); 963232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull; 964232809Sjmallett} 965232809Sjmallett#else 966232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull) 967232809Sjmallett#endif 968232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 969232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(unsigned long block_id) 970232809Sjmallett{ 971232809Sjmallett if (!( 972232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 973232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(%lu) is invalid on this chip\n", block_id); 974232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull; 975232809Sjmallett} 976232809Sjmallett#else 977232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull) 978232809Sjmallett#endif 979232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 980232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(unsigned long block_id) 981232809Sjmallett{ 982232809Sjmallett if (!( 983232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 984232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(%lu) is invalid on this chip\n", block_id); 985232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull; 986232809Sjmallett} 987232809Sjmallett#else 988232809Sjmallett#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull) 989232809Sjmallett#endif 990232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 991232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_GPIO(unsigned long block_id) 992232809Sjmallett{ 993232809Sjmallett if (!( 994232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 995232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_GPIO(%lu) is invalid on this chip\n", block_id); 996232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull; 997232809Sjmallett} 998232809Sjmallett#else 999232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull) 1000232809Sjmallett#endif 1001232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1002232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(unsigned long block_id) 1003232809Sjmallett{ 1004232809Sjmallett if (!( 1005232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1006232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(%lu) is invalid on this chip\n", block_id); 1007232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull; 1008232809Sjmallett} 1009232809Sjmallett#else 1010232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull) 1011232809Sjmallett#endif 1012232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1013232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(unsigned long block_id) 1014232809Sjmallett{ 1015232809Sjmallett if (!( 1016232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1017232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(%lu) is invalid on this chip\n", block_id); 1018232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull; 1019232809Sjmallett} 1020232809Sjmallett#else 1021232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull) 1022232809Sjmallett#endif 1023232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1024232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_IO(unsigned long block_id) 1025232809Sjmallett{ 1026232809Sjmallett if (!( 1027232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1028232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_IO(%lu) is invalid on this chip\n", block_id); 1029232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull; 1030232809Sjmallett} 1031232809Sjmallett#else 1032232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull) 1033232809Sjmallett#endif 1034232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1035232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_IO_W1C(unsigned long block_id) 1036232809Sjmallett{ 1037232809Sjmallett if (!( 1038232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1039232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_IO_W1C(%lu) is invalid on this chip\n", block_id); 1040232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull; 1041232809Sjmallett} 1042232809Sjmallett#else 1043232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull) 1044232809Sjmallett#endif 1045232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1046232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_IO_W1S(unsigned long block_id) 1047232809Sjmallett{ 1048232809Sjmallett if (!( 1049232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1050232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_IO_W1S(%lu) is invalid on this chip\n", block_id); 1051232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull; 1052232809Sjmallett} 1053232809Sjmallett#else 1054232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull) 1055232809Sjmallett#endif 1056232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1057232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_MBOX(unsigned long block_id) 1058232809Sjmallett{ 1059232809Sjmallett if (!( 1060232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1061232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MBOX(%lu) is invalid on this chip\n", block_id); 1062232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull; 1063232809Sjmallett} 1064232809Sjmallett#else 1065232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull) 1066232809Sjmallett#endif 1067232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1068232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(unsigned long block_id) 1069232809Sjmallett{ 1070232809Sjmallett if (!( 1071232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1072232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(%lu) is invalid on this chip\n", block_id); 1073232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull; 1074232809Sjmallett} 1075232809Sjmallett#else 1076232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull) 1077232809Sjmallett#endif 1078232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1079232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(unsigned long block_id) 1080232809Sjmallett{ 1081232809Sjmallett if (!( 1082232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1083232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(%lu) is invalid on this chip\n", block_id); 1084232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull; 1085232809Sjmallett} 1086232809Sjmallett#else 1087232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull) 1088232809Sjmallett#endif 1089232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1090232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_MEM(unsigned long block_id) 1091232809Sjmallett{ 1092232809Sjmallett if (!( 1093232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1094232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MEM(%lu) is invalid on this chip\n", block_id); 1095232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull; 1096232809Sjmallett} 1097232809Sjmallett#else 1098232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull) 1099232809Sjmallett#endif 1100232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1101232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_MEM_W1C(unsigned long block_id) 1102232809Sjmallett{ 1103232809Sjmallett if (!( 1104232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1105232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MEM_W1C(%lu) is invalid on this chip\n", block_id); 1106232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull; 1107232809Sjmallett} 1108232809Sjmallett#else 1109232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull) 1110232809Sjmallett#endif 1111232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1112232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_MEM_W1S(unsigned long block_id) 1113232809Sjmallett{ 1114232809Sjmallett if (!( 1115232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1116232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MEM_W1S(%lu) is invalid on this chip\n", block_id); 1117232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull; 1118232809Sjmallett} 1119232809Sjmallett#else 1120232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull) 1121232809Sjmallett#endif 1122232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1123232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_MIO(unsigned long block_id) 1124232809Sjmallett{ 1125232809Sjmallett if (!( 1126232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1127232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MIO(%lu) is invalid on this chip\n", block_id); 1128232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull; 1129232809Sjmallett} 1130232809Sjmallett#else 1131232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull) 1132232809Sjmallett#endif 1133232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1134232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_MIO_W1C(unsigned long block_id) 1135232809Sjmallett{ 1136232809Sjmallett if (!( 1137232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1138232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MIO_W1C(%lu) is invalid on this chip\n", block_id); 1139232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull; 1140232809Sjmallett} 1141232809Sjmallett#else 1142232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull) 1143232809Sjmallett#endif 1144232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1145232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_MIO_W1S(unsigned long block_id) 1146232809Sjmallett{ 1147232809Sjmallett if (!( 1148232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1149232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MIO_W1S(%lu) is invalid on this chip\n", block_id); 1150232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull; 1151232809Sjmallett} 1152232809Sjmallett#else 1153232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull) 1154232809Sjmallett#endif 1155232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1156232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_PKT(unsigned long block_id) 1157232809Sjmallett{ 1158232809Sjmallett if (!( 1159232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1160232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_PKT(%lu) is invalid on this chip\n", block_id); 1161232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull; 1162232809Sjmallett} 1163232809Sjmallett#else 1164232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull) 1165232809Sjmallett#endif 1166232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1167232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_PKT_W1C(unsigned long block_id) 1168232809Sjmallett{ 1169232809Sjmallett if (!( 1170232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1171232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_PKT_W1C(%lu) is invalid on this chip\n", block_id); 1172232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull; 1173232809Sjmallett} 1174232809Sjmallett#else 1175232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull) 1176232809Sjmallett#endif 1177232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1178232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_PKT_W1S(unsigned long block_id) 1179232809Sjmallett{ 1180232809Sjmallett if (!( 1181232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1182232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_PKT_W1S(%lu) is invalid on this chip\n", block_id); 1183232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull; 1184232809Sjmallett} 1185232809Sjmallett#else 1186232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull) 1187232809Sjmallett#endif 1188232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1189232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_RML(unsigned long block_id) 1190232809Sjmallett{ 1191232809Sjmallett if (!( 1192232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1193232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_RML(%lu) is invalid on this chip\n", block_id); 1194232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull; 1195232809Sjmallett} 1196232809Sjmallett#else 1197232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull) 1198232809Sjmallett#endif 1199232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1200232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_RML_W1C(unsigned long block_id) 1201232809Sjmallett{ 1202232809Sjmallett if (!( 1203232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1204232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_RML_W1C(%lu) is invalid on this chip\n", block_id); 1205232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull; 1206232809Sjmallett} 1207232809Sjmallett#else 1208232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull) 1209232809Sjmallett#endif 1210232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1211232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_RML_W1S(unsigned long block_id) 1212232809Sjmallett{ 1213232809Sjmallett if (!( 1214232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1215232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_RML_W1S(%lu) is invalid on this chip\n", block_id); 1216232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull; 1217232809Sjmallett} 1218232809Sjmallett#else 1219232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull) 1220232809Sjmallett#endif 1221232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1222232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_WDOG(unsigned long block_id) 1223232809Sjmallett{ 1224232809Sjmallett if (!( 1225232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1226232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WDOG(%lu) is invalid on this chip\n", block_id); 1227232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull; 1228232809Sjmallett} 1229232809Sjmallett#else 1230232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull) 1231232809Sjmallett#endif 1232232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1233232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(unsigned long block_id) 1234232809Sjmallett{ 1235232809Sjmallett if (!( 1236232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1237232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(%lu) is invalid on this chip\n", block_id); 1238232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull; 1239232809Sjmallett} 1240232809Sjmallett#else 1241232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull) 1242232809Sjmallett#endif 1243232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1244232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(unsigned long block_id) 1245232809Sjmallett{ 1246232809Sjmallett if (!( 1247232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1248232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(%lu) is invalid on this chip\n", block_id); 1249232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull; 1250232809Sjmallett} 1251232809Sjmallett#else 1252232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull) 1253232809Sjmallett#endif 1254232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1255232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_WRKQ(unsigned long block_id) 1256232809Sjmallett{ 1257232809Sjmallett if (!( 1258232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1259232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WRKQ(%lu) is invalid on this chip\n", block_id); 1260232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull; 1261232809Sjmallett} 1262232809Sjmallett#else 1263232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull) 1264232809Sjmallett#endif 1265232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1266232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(unsigned long block_id) 1267232809Sjmallett{ 1268232809Sjmallett if (!( 1269232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1270232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(%lu) is invalid on this chip\n", block_id); 1271232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull; 1272232809Sjmallett} 1273232809Sjmallett#else 1274232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull) 1275232809Sjmallett#endif 1276232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1277232809Sjmallettstatic inline uint64_t CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(unsigned long block_id) 1278232809Sjmallett{ 1279232809Sjmallett if (!( 1280232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1281232809Sjmallett cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(%lu) is invalid on this chip\n", block_id); 1282232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull; 1283232809Sjmallett} 1284232809Sjmallett#else 1285232809Sjmallett#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull) 1286232809Sjmallett#endif 1287232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1288232809Sjmallett#define CVMX_CIU2_INTR_CIU_READY CVMX_CIU2_INTR_CIU_READY_FUNC() 1289232809Sjmallettstatic inline uint64_t CVMX_CIU2_INTR_CIU_READY_FUNC(void) 1290232809Sjmallett{ 1291232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 1292232809Sjmallett cvmx_warn("CVMX_CIU2_INTR_CIU_READY not supported on this chip\n"); 1293232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100102008ull); 1294232809Sjmallett} 1295232809Sjmallett#else 1296232809Sjmallett#define CVMX_CIU2_INTR_CIU_READY (CVMX_ADD_IO_SEG(0x0001070100102008ull)) 1297232809Sjmallett#endif 1298232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1299232809Sjmallett#define CVMX_CIU2_INTR_RAM_ECC_CTL CVMX_CIU2_INTR_RAM_ECC_CTL_FUNC() 1300232809Sjmallettstatic inline uint64_t CVMX_CIU2_INTR_RAM_ECC_CTL_FUNC(void) 1301232809Sjmallett{ 1302232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 1303232809Sjmallett cvmx_warn("CVMX_CIU2_INTR_RAM_ECC_CTL not supported on this chip\n"); 1304232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100102010ull); 1305232809Sjmallett} 1306232809Sjmallett#else 1307232809Sjmallett#define CVMX_CIU2_INTR_RAM_ECC_CTL (CVMX_ADD_IO_SEG(0x0001070100102010ull)) 1308232809Sjmallett#endif 1309232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1310232809Sjmallett#define CVMX_CIU2_INTR_RAM_ECC_ST CVMX_CIU2_INTR_RAM_ECC_ST_FUNC() 1311232809Sjmallettstatic inline uint64_t CVMX_CIU2_INTR_RAM_ECC_ST_FUNC(void) 1312232809Sjmallett{ 1313232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 1314232809Sjmallett cvmx_warn("CVMX_CIU2_INTR_RAM_ECC_ST not supported on this chip\n"); 1315232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100102018ull); 1316232809Sjmallett} 1317232809Sjmallett#else 1318232809Sjmallett#define CVMX_CIU2_INTR_RAM_ECC_ST (CVMX_ADD_IO_SEG(0x0001070100102018ull)) 1319232809Sjmallett#endif 1320232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1321232809Sjmallett#define CVMX_CIU2_INTR_SLOWDOWN CVMX_CIU2_INTR_SLOWDOWN_FUNC() 1322232809Sjmallettstatic inline uint64_t CVMX_CIU2_INTR_SLOWDOWN_FUNC(void) 1323232809Sjmallett{ 1324232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 1325232809Sjmallett cvmx_warn("CVMX_CIU2_INTR_SLOWDOWN not supported on this chip\n"); 1326232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100102000ull); 1327232809Sjmallett} 1328232809Sjmallett#else 1329232809Sjmallett#define CVMX_CIU2_INTR_SLOWDOWN (CVMX_ADD_IO_SEG(0x0001070100102000ull)) 1330232809Sjmallett#endif 1331232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1332232809Sjmallettstatic inline uint64_t CVMX_CIU2_MSIRED_PPX_IP2(unsigned long block_id) 1333232809Sjmallett{ 1334232809Sjmallett if (!( 1335232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1336232809Sjmallett cvmx_warn("CVMX_CIU2_MSIRED_PPX_IP2(%lu) is invalid on this chip\n", block_id); 1337232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull; 1338232809Sjmallett} 1339232809Sjmallett#else 1340232809Sjmallett#define CVMX_CIU2_MSIRED_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull) 1341232809Sjmallett#endif 1342232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1343232809Sjmallettstatic inline uint64_t CVMX_CIU2_MSIRED_PPX_IP3(unsigned long block_id) 1344232809Sjmallett{ 1345232809Sjmallett if (!( 1346232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1347232809Sjmallett cvmx_warn("CVMX_CIU2_MSIRED_PPX_IP3(%lu) is invalid on this chip\n", block_id); 1348232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull; 1349232809Sjmallett} 1350232809Sjmallett#else 1351232809Sjmallett#define CVMX_CIU2_MSIRED_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull) 1352232809Sjmallett#endif 1353232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1354232809Sjmallettstatic inline uint64_t CVMX_CIU2_MSIRED_PPX_IP4(unsigned long block_id) 1355232809Sjmallett{ 1356232809Sjmallett if (!( 1357232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1358232809Sjmallett cvmx_warn("CVMX_CIU2_MSIRED_PPX_IP4(%lu) is invalid on this chip\n", block_id); 1359232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull; 1360232809Sjmallett} 1361232809Sjmallett#else 1362232809Sjmallett#define CVMX_CIU2_MSIRED_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull) 1363232809Sjmallett#endif 1364232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1365232809Sjmallettstatic inline uint64_t CVMX_CIU2_MSI_RCVX(unsigned long offset) 1366232809Sjmallett{ 1367232809Sjmallett if (!( 1368232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 255))))) 1369232809Sjmallett cvmx_warn("CVMX_CIU2_MSI_RCVX(%lu) is invalid on this chip\n", offset); 1370232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8; 1371232809Sjmallett} 1372232809Sjmallett#else 1373232809Sjmallett#define CVMX_CIU2_MSI_RCVX(offset) (CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8) 1374232809Sjmallett#endif 1375232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1376232809Sjmallettstatic inline uint64_t CVMX_CIU2_MSI_SELX(unsigned long offset) 1377232809Sjmallett{ 1378232809Sjmallett if (!( 1379232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 255))))) 1380232809Sjmallett cvmx_warn("CVMX_CIU2_MSI_SELX(%lu) is invalid on this chip\n", offset); 1381232809Sjmallett return CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8; 1382232809Sjmallett} 1383232809Sjmallett#else 1384232809Sjmallett#define CVMX_CIU2_MSI_SELX(offset) (CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8) 1385232809Sjmallett#endif 1386232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1387232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_IOX_INT_GPIO(unsigned long block_id) 1388232809Sjmallett{ 1389232809Sjmallett if (!( 1390232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1391232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_IOX_INT_GPIO(%lu) is invalid on this chip\n", block_id); 1392232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull; 1393232809Sjmallett} 1394232809Sjmallett#else 1395232809Sjmallett#define CVMX_CIU2_RAW_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull) 1396232809Sjmallett#endif 1397232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1398232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_IOX_INT_IO(unsigned long block_id) 1399232809Sjmallett{ 1400232809Sjmallett if (!( 1401232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1402232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_IOX_INT_IO(%lu) is invalid on this chip\n", block_id); 1403232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull; 1404232809Sjmallett} 1405232809Sjmallett#else 1406232809Sjmallett#define CVMX_CIU2_RAW_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull) 1407232809Sjmallett#endif 1408232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1409232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_IOX_INT_MEM(unsigned long block_id) 1410232809Sjmallett{ 1411232809Sjmallett if (!( 1412232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1413232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_IOX_INT_MEM(%lu) is invalid on this chip\n", block_id); 1414232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull; 1415232809Sjmallett} 1416232809Sjmallett#else 1417232809Sjmallett#define CVMX_CIU2_RAW_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull) 1418232809Sjmallett#endif 1419232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1420232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_IOX_INT_MIO(unsigned long block_id) 1421232809Sjmallett{ 1422232809Sjmallett if (!( 1423232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1424232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_IOX_INT_MIO(%lu) is invalid on this chip\n", block_id); 1425232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull; 1426232809Sjmallett} 1427232809Sjmallett#else 1428232809Sjmallett#define CVMX_CIU2_RAW_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull) 1429232809Sjmallett#endif 1430232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1431232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_IOX_INT_PKT(unsigned long block_id) 1432232809Sjmallett{ 1433232809Sjmallett if (!( 1434232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1435232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_IOX_INT_PKT(%lu) is invalid on this chip\n", block_id); 1436232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull; 1437232809Sjmallett} 1438232809Sjmallett#else 1439232809Sjmallett#define CVMX_CIU2_RAW_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull) 1440232809Sjmallett#endif 1441232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1442232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_IOX_INT_RML(unsigned long block_id) 1443232809Sjmallett{ 1444232809Sjmallett if (!( 1445232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1446232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_IOX_INT_RML(%lu) is invalid on this chip\n", block_id); 1447232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull; 1448232809Sjmallett} 1449232809Sjmallett#else 1450232809Sjmallett#define CVMX_CIU2_RAW_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull) 1451232809Sjmallett#endif 1452232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1453232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_IOX_INT_WDOG(unsigned long block_id) 1454232809Sjmallett{ 1455232809Sjmallett if (!( 1456232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1457232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_IOX_INT_WDOG(%lu) is invalid on this chip\n", block_id); 1458232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull; 1459232809Sjmallett} 1460232809Sjmallett#else 1461232809Sjmallett#define CVMX_CIU2_RAW_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull) 1462232809Sjmallett#endif 1463232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1464232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_IOX_INT_WRKQ(unsigned long block_id) 1465232809Sjmallett{ 1466232809Sjmallett if (!( 1467232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1468232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_IOX_INT_WRKQ(%lu) is invalid on this chip\n", block_id); 1469232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull; 1470232809Sjmallett} 1471232809Sjmallett#else 1472232809Sjmallett#define CVMX_CIU2_RAW_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull) 1473232809Sjmallett#endif 1474232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1475232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP2_GPIO(unsigned long block_id) 1476232809Sjmallett{ 1477232809Sjmallett if (!( 1478232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1479232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_GPIO(%lu) is invalid on this chip\n", block_id); 1480232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull; 1481232809Sjmallett} 1482232809Sjmallett#else 1483232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull) 1484232809Sjmallett#endif 1485232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1486232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP2_IO(unsigned long block_id) 1487232809Sjmallett{ 1488232809Sjmallett if (!( 1489232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1490232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_IO(%lu) is invalid on this chip\n", block_id); 1491232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull; 1492232809Sjmallett} 1493232809Sjmallett#else 1494232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull) 1495232809Sjmallett#endif 1496232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1497232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP2_MEM(unsigned long block_id) 1498232809Sjmallett{ 1499232809Sjmallett if (!( 1500232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1501232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_MEM(%lu) is invalid on this chip\n", block_id); 1502232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull; 1503232809Sjmallett} 1504232809Sjmallett#else 1505232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull) 1506232809Sjmallett#endif 1507232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1508232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP2_MIO(unsigned long block_id) 1509232809Sjmallett{ 1510232809Sjmallett if (!( 1511232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1512232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_MIO(%lu) is invalid on this chip\n", block_id); 1513232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull; 1514232809Sjmallett} 1515232809Sjmallett#else 1516232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull) 1517232809Sjmallett#endif 1518232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1519232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP2_PKT(unsigned long block_id) 1520232809Sjmallett{ 1521232809Sjmallett if (!( 1522232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1523232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_PKT(%lu) is invalid on this chip\n", block_id); 1524232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull; 1525232809Sjmallett} 1526232809Sjmallett#else 1527232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull) 1528232809Sjmallett#endif 1529232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1530232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP2_RML(unsigned long block_id) 1531232809Sjmallett{ 1532232809Sjmallett if (!( 1533232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1534232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_RML(%lu) is invalid on this chip\n", block_id); 1535232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull; 1536232809Sjmallett} 1537232809Sjmallett#else 1538232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull) 1539232809Sjmallett#endif 1540232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1541232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP2_WDOG(unsigned long block_id) 1542232809Sjmallett{ 1543232809Sjmallett if (!( 1544232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1545232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_WDOG(%lu) is invalid on this chip\n", block_id); 1546232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull; 1547232809Sjmallett} 1548232809Sjmallett#else 1549232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull) 1550232809Sjmallett#endif 1551232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1552232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP2_WRKQ(unsigned long block_id) 1553232809Sjmallett{ 1554232809Sjmallett if (!( 1555232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1556232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_WRKQ(%lu) is invalid on this chip\n", block_id); 1557232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull; 1558232809Sjmallett} 1559232809Sjmallett#else 1560232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull) 1561232809Sjmallett#endif 1562232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1563232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP3_GPIO(unsigned long block_id) 1564232809Sjmallett{ 1565232809Sjmallett if (!( 1566232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1567232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_GPIO(%lu) is invalid on this chip\n", block_id); 1568232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull; 1569232809Sjmallett} 1570232809Sjmallett#else 1571232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull) 1572232809Sjmallett#endif 1573232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1574232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP3_IO(unsigned long block_id) 1575232809Sjmallett{ 1576232809Sjmallett if (!( 1577232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1578232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_IO(%lu) is invalid on this chip\n", block_id); 1579232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull; 1580232809Sjmallett} 1581232809Sjmallett#else 1582232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull) 1583232809Sjmallett#endif 1584232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1585232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP3_MEM(unsigned long block_id) 1586232809Sjmallett{ 1587232809Sjmallett if (!( 1588232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1589232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_MEM(%lu) is invalid on this chip\n", block_id); 1590232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull; 1591232809Sjmallett} 1592232809Sjmallett#else 1593232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull) 1594232809Sjmallett#endif 1595232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1596232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP3_MIO(unsigned long block_id) 1597232809Sjmallett{ 1598232809Sjmallett if (!( 1599232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1600232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_MIO(%lu) is invalid on this chip\n", block_id); 1601232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull; 1602232809Sjmallett} 1603232809Sjmallett#else 1604232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull) 1605232809Sjmallett#endif 1606232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1607232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP3_PKT(unsigned long block_id) 1608232809Sjmallett{ 1609232809Sjmallett if (!( 1610232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1611232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_PKT(%lu) is invalid on this chip\n", block_id); 1612232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull; 1613232809Sjmallett} 1614232809Sjmallett#else 1615232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull) 1616232809Sjmallett#endif 1617232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1618232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP3_RML(unsigned long block_id) 1619232809Sjmallett{ 1620232809Sjmallett if (!( 1621232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1622232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_RML(%lu) is invalid on this chip\n", block_id); 1623232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull; 1624232809Sjmallett} 1625232809Sjmallett#else 1626232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull) 1627232809Sjmallett#endif 1628232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1629232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP3_WDOG(unsigned long block_id) 1630232809Sjmallett{ 1631232809Sjmallett if (!( 1632232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1633232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_WDOG(%lu) is invalid on this chip\n", block_id); 1634232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull; 1635232809Sjmallett} 1636232809Sjmallett#else 1637232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull) 1638232809Sjmallett#endif 1639232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1640232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP3_WRKQ(unsigned long block_id) 1641232809Sjmallett{ 1642232809Sjmallett if (!( 1643232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1644232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_WRKQ(%lu) is invalid on this chip\n", block_id); 1645232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull; 1646232809Sjmallett} 1647232809Sjmallett#else 1648232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull) 1649232809Sjmallett#endif 1650232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1651232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP4_GPIO(unsigned long block_id) 1652232809Sjmallett{ 1653232809Sjmallett if (!( 1654232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1655232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_GPIO(%lu) is invalid on this chip\n", block_id); 1656232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull; 1657232809Sjmallett} 1658232809Sjmallett#else 1659232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull) 1660232809Sjmallett#endif 1661232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1662232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP4_IO(unsigned long block_id) 1663232809Sjmallett{ 1664232809Sjmallett if (!( 1665232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1666232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_IO(%lu) is invalid on this chip\n", block_id); 1667232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull; 1668232809Sjmallett} 1669232809Sjmallett#else 1670232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull) 1671232809Sjmallett#endif 1672232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1673232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP4_MEM(unsigned long block_id) 1674232809Sjmallett{ 1675232809Sjmallett if (!( 1676232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1677232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_MEM(%lu) is invalid on this chip\n", block_id); 1678232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull; 1679232809Sjmallett} 1680232809Sjmallett#else 1681232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull) 1682232809Sjmallett#endif 1683232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1684232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP4_MIO(unsigned long block_id) 1685232809Sjmallett{ 1686232809Sjmallett if (!( 1687232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1688232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_MIO(%lu) is invalid on this chip\n", block_id); 1689232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull; 1690232809Sjmallett} 1691232809Sjmallett#else 1692232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull) 1693232809Sjmallett#endif 1694232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1695232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP4_PKT(unsigned long block_id) 1696232809Sjmallett{ 1697232809Sjmallett if (!( 1698232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1699232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_PKT(%lu) is invalid on this chip\n", block_id); 1700232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull; 1701232809Sjmallett} 1702232809Sjmallett#else 1703232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull) 1704232809Sjmallett#endif 1705232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1706232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP4_RML(unsigned long block_id) 1707232809Sjmallett{ 1708232809Sjmallett if (!( 1709232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1710232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_RML(%lu) is invalid on this chip\n", block_id); 1711232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull; 1712232809Sjmallett} 1713232809Sjmallett#else 1714232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull) 1715232809Sjmallett#endif 1716232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1717232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP4_WDOG(unsigned long block_id) 1718232809Sjmallett{ 1719232809Sjmallett if (!( 1720232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1721232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_WDOG(%lu) is invalid on this chip\n", block_id); 1722232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull; 1723232809Sjmallett} 1724232809Sjmallett#else 1725232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull) 1726232809Sjmallett#endif 1727232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1728232809Sjmallettstatic inline uint64_t CVMX_CIU2_RAW_PPX_IP4_WRKQ(unsigned long block_id) 1729232809Sjmallett{ 1730232809Sjmallett if (!( 1731232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1732232809Sjmallett cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_WRKQ(%lu) is invalid on this chip\n", block_id); 1733232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull; 1734232809Sjmallett} 1735232809Sjmallett#else 1736232809Sjmallett#define CVMX_CIU2_RAW_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull) 1737232809Sjmallett#endif 1738232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1739232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_IOX_INT_GPIO(unsigned long block_id) 1740232809Sjmallett{ 1741232809Sjmallett if (!( 1742232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1743232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_IOX_INT_GPIO(%lu) is invalid on this chip\n", block_id); 1744232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull; 1745232809Sjmallett} 1746232809Sjmallett#else 1747232809Sjmallett#define CVMX_CIU2_SRC_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull) 1748232809Sjmallett#endif 1749232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1750232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_IOX_INT_IO(unsigned long block_id) 1751232809Sjmallett{ 1752232809Sjmallett if (!( 1753232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1754232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_IOX_INT_IO(%lu) is invalid on this chip\n", block_id); 1755232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull; 1756232809Sjmallett} 1757232809Sjmallett#else 1758232809Sjmallett#define CVMX_CIU2_SRC_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull) 1759232809Sjmallett#endif 1760232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1761232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_IOX_INT_MBOX(unsigned long block_id) 1762232809Sjmallett{ 1763232809Sjmallett if (!( 1764232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1765232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_IOX_INT_MBOX(%lu) is invalid on this chip\n", block_id); 1766232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull; 1767232809Sjmallett} 1768232809Sjmallett#else 1769232809Sjmallett#define CVMX_CIU2_SRC_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull) 1770232809Sjmallett#endif 1771232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1772232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_IOX_INT_MEM(unsigned long block_id) 1773232809Sjmallett{ 1774232809Sjmallett if (!( 1775232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1776232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_IOX_INT_MEM(%lu) is invalid on this chip\n", block_id); 1777232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull; 1778232809Sjmallett} 1779232809Sjmallett#else 1780232809Sjmallett#define CVMX_CIU2_SRC_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull) 1781232809Sjmallett#endif 1782232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1783232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_IOX_INT_MIO(unsigned long block_id) 1784232809Sjmallett{ 1785232809Sjmallett if (!( 1786232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1787232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_IOX_INT_MIO(%lu) is invalid on this chip\n", block_id); 1788232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull; 1789232809Sjmallett} 1790232809Sjmallett#else 1791232809Sjmallett#define CVMX_CIU2_SRC_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull) 1792232809Sjmallett#endif 1793232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1794232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_IOX_INT_PKT(unsigned long block_id) 1795232809Sjmallett{ 1796232809Sjmallett if (!( 1797232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1798232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_IOX_INT_PKT(%lu) is invalid on this chip\n", block_id); 1799232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull; 1800232809Sjmallett} 1801232809Sjmallett#else 1802232809Sjmallett#define CVMX_CIU2_SRC_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull) 1803232809Sjmallett#endif 1804232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1805232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_IOX_INT_RML(unsigned long block_id) 1806232809Sjmallett{ 1807232809Sjmallett if (!( 1808232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1809232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_IOX_INT_RML(%lu) is invalid on this chip\n", block_id); 1810232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull; 1811232809Sjmallett} 1812232809Sjmallett#else 1813232809Sjmallett#define CVMX_CIU2_SRC_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull) 1814232809Sjmallett#endif 1815232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1816232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_IOX_INT_WDOG(unsigned long block_id) 1817232809Sjmallett{ 1818232809Sjmallett if (!( 1819232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1820232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_IOX_INT_WDOG(%lu) is invalid on this chip\n", block_id); 1821232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull; 1822232809Sjmallett} 1823232809Sjmallett#else 1824232809Sjmallett#define CVMX_CIU2_SRC_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull) 1825232809Sjmallett#endif 1826232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1827232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_IOX_INT_WRKQ(unsigned long block_id) 1828232809Sjmallett{ 1829232809Sjmallett if (!( 1830232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) 1831232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_IOX_INT_WRKQ(%lu) is invalid on this chip\n", block_id); 1832232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull; 1833232809Sjmallett} 1834232809Sjmallett#else 1835232809Sjmallett#define CVMX_CIU2_SRC_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull) 1836232809Sjmallett#endif 1837232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1838232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP2_GPIO(unsigned long block_id) 1839232809Sjmallett{ 1840232809Sjmallett if (!( 1841232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1842232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_GPIO(%lu) is invalid on this chip\n", block_id); 1843232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull; 1844232809Sjmallett} 1845232809Sjmallett#else 1846232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull) 1847232809Sjmallett#endif 1848232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1849232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP2_IO(unsigned long block_id) 1850232809Sjmallett{ 1851232809Sjmallett if (!( 1852232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1853232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_IO(%lu) is invalid on this chip\n", block_id); 1854232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull; 1855232809Sjmallett} 1856232809Sjmallett#else 1857232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull) 1858232809Sjmallett#endif 1859232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1860232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP2_MBOX(unsigned long block_id) 1861232809Sjmallett{ 1862232809Sjmallett if (!( 1863232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1864232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_MBOX(%lu) is invalid on this chip\n", block_id); 1865232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull; 1866232809Sjmallett} 1867232809Sjmallett#else 1868232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull) 1869232809Sjmallett#endif 1870232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1871232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP2_MEM(unsigned long block_id) 1872232809Sjmallett{ 1873232809Sjmallett if (!( 1874232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1875232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_MEM(%lu) is invalid on this chip\n", block_id); 1876232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull; 1877232809Sjmallett} 1878232809Sjmallett#else 1879232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull) 1880232809Sjmallett#endif 1881232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1882232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP2_MIO(unsigned long block_id) 1883232809Sjmallett{ 1884232809Sjmallett if (!( 1885232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1886232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_MIO(%lu) is invalid on this chip\n", block_id); 1887232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull; 1888232809Sjmallett} 1889232809Sjmallett#else 1890232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull) 1891232809Sjmallett#endif 1892232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1893232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP2_PKT(unsigned long block_id) 1894232809Sjmallett{ 1895232809Sjmallett if (!( 1896232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1897232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_PKT(%lu) is invalid on this chip\n", block_id); 1898232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull; 1899232809Sjmallett} 1900232809Sjmallett#else 1901232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull) 1902232809Sjmallett#endif 1903232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1904232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP2_RML(unsigned long block_id) 1905232809Sjmallett{ 1906232809Sjmallett if (!( 1907232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1908232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_RML(%lu) is invalid on this chip\n", block_id); 1909232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull; 1910232809Sjmallett} 1911232809Sjmallett#else 1912232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull) 1913232809Sjmallett#endif 1914232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1915232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP2_WDOG(unsigned long block_id) 1916232809Sjmallett{ 1917232809Sjmallett if (!( 1918232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1919232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_WDOG(%lu) is invalid on this chip\n", block_id); 1920232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull; 1921232809Sjmallett} 1922232809Sjmallett#else 1923232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull) 1924232809Sjmallett#endif 1925232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1926232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP2_WRKQ(unsigned long block_id) 1927232809Sjmallett{ 1928232809Sjmallett if (!( 1929232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1930232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_WRKQ(%lu) is invalid on this chip\n", block_id); 1931232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull; 1932232809Sjmallett} 1933232809Sjmallett#else 1934232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull) 1935232809Sjmallett#endif 1936232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1937232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP3_GPIO(unsigned long block_id) 1938232809Sjmallett{ 1939232809Sjmallett if (!( 1940232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1941232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_GPIO(%lu) is invalid on this chip\n", block_id); 1942232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull; 1943232809Sjmallett} 1944232809Sjmallett#else 1945232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull) 1946232809Sjmallett#endif 1947232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1948232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP3_IO(unsigned long block_id) 1949232809Sjmallett{ 1950232809Sjmallett if (!( 1951232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1952232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_IO(%lu) is invalid on this chip\n", block_id); 1953232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull; 1954232809Sjmallett} 1955232809Sjmallett#else 1956232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull) 1957232809Sjmallett#endif 1958232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1959232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP3_MBOX(unsigned long block_id) 1960232809Sjmallett{ 1961232809Sjmallett if (!( 1962232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1963232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_MBOX(%lu) is invalid on this chip\n", block_id); 1964232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull; 1965232809Sjmallett} 1966232809Sjmallett#else 1967232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull) 1968232809Sjmallett#endif 1969232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1970232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP3_MEM(unsigned long block_id) 1971232809Sjmallett{ 1972232809Sjmallett if (!( 1973232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1974232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_MEM(%lu) is invalid on this chip\n", block_id); 1975232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull; 1976232809Sjmallett} 1977232809Sjmallett#else 1978232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull) 1979232809Sjmallett#endif 1980232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1981232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP3_MIO(unsigned long block_id) 1982232809Sjmallett{ 1983232809Sjmallett if (!( 1984232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1985232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_MIO(%lu) is invalid on this chip\n", block_id); 1986232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull; 1987232809Sjmallett} 1988232809Sjmallett#else 1989232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull) 1990232809Sjmallett#endif 1991232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1992232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP3_PKT(unsigned long block_id) 1993232809Sjmallett{ 1994232809Sjmallett if (!( 1995232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 1996232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_PKT(%lu) is invalid on this chip\n", block_id); 1997232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull; 1998232809Sjmallett} 1999232809Sjmallett#else 2000232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull) 2001232809Sjmallett#endif 2002232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2003232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP3_RML(unsigned long block_id) 2004232809Sjmallett{ 2005232809Sjmallett if (!( 2006232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 2007232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_RML(%lu) is invalid on this chip\n", block_id); 2008232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull; 2009232809Sjmallett} 2010232809Sjmallett#else 2011232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull) 2012232809Sjmallett#endif 2013232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2014232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP3_WDOG(unsigned long block_id) 2015232809Sjmallett{ 2016232809Sjmallett if (!( 2017232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 2018232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_WDOG(%lu) is invalid on this chip\n", block_id); 2019232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull; 2020232809Sjmallett} 2021232809Sjmallett#else 2022232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull) 2023232809Sjmallett#endif 2024232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2025232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP3_WRKQ(unsigned long block_id) 2026232809Sjmallett{ 2027232809Sjmallett if (!( 2028232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 2029232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_WRKQ(%lu) is invalid on this chip\n", block_id); 2030232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull; 2031232809Sjmallett} 2032232809Sjmallett#else 2033232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull) 2034232809Sjmallett#endif 2035232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2036232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP4_GPIO(unsigned long block_id) 2037232809Sjmallett{ 2038232809Sjmallett if (!( 2039232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 2040232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_GPIO(%lu) is invalid on this chip\n", block_id); 2041232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull; 2042232809Sjmallett} 2043232809Sjmallett#else 2044232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull) 2045232809Sjmallett#endif 2046232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2047232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP4_IO(unsigned long block_id) 2048232809Sjmallett{ 2049232809Sjmallett if (!( 2050232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 2051232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_IO(%lu) is invalid on this chip\n", block_id); 2052232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull; 2053232809Sjmallett} 2054232809Sjmallett#else 2055232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull) 2056232809Sjmallett#endif 2057232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2058232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP4_MBOX(unsigned long block_id) 2059232809Sjmallett{ 2060232809Sjmallett if (!( 2061232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 2062232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_MBOX(%lu) is invalid on this chip\n", block_id); 2063232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull; 2064232809Sjmallett} 2065232809Sjmallett#else 2066232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull) 2067232809Sjmallett#endif 2068232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2069232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP4_MEM(unsigned long block_id) 2070232809Sjmallett{ 2071232809Sjmallett if (!( 2072232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 2073232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_MEM(%lu) is invalid on this chip\n", block_id); 2074232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull; 2075232809Sjmallett} 2076232809Sjmallett#else 2077232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull) 2078232809Sjmallett#endif 2079232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2080232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP4_MIO(unsigned long block_id) 2081232809Sjmallett{ 2082232809Sjmallett if (!( 2083232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 2084232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_MIO(%lu) is invalid on this chip\n", block_id); 2085232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull; 2086232809Sjmallett} 2087232809Sjmallett#else 2088232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull) 2089232809Sjmallett#endif 2090232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2091232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP4_PKT(unsigned long block_id) 2092232809Sjmallett{ 2093232809Sjmallett if (!( 2094232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 2095232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_PKT(%lu) is invalid on this chip\n", block_id); 2096232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull; 2097232809Sjmallett} 2098232809Sjmallett#else 2099232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull) 2100232809Sjmallett#endif 2101232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2102232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP4_RML(unsigned long block_id) 2103232809Sjmallett{ 2104232809Sjmallett if (!( 2105232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 2106232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_RML(%lu) is invalid on this chip\n", block_id); 2107232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull; 2108232809Sjmallett} 2109232809Sjmallett#else 2110232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull) 2111232809Sjmallett#endif 2112232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2113232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP4_WDOG(unsigned long block_id) 2114232809Sjmallett{ 2115232809Sjmallett if (!( 2116232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 2117232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_WDOG(%lu) is invalid on this chip\n", block_id); 2118232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull; 2119232809Sjmallett} 2120232809Sjmallett#else 2121232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull) 2122232809Sjmallett#endif 2123232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2124232809Sjmallettstatic inline uint64_t CVMX_CIU2_SRC_PPX_IP4_WRKQ(unsigned long block_id) 2125232809Sjmallett{ 2126232809Sjmallett if (!( 2127232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) 2128232809Sjmallett cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_WRKQ(%lu) is invalid on this chip\n", block_id); 2129232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull; 2130232809Sjmallett} 2131232809Sjmallett#else 2132232809Sjmallett#define CVMX_CIU2_SRC_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull) 2133232809Sjmallett#endif 2134232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2135232809Sjmallettstatic inline uint64_t CVMX_CIU2_SUM_IOX_INT(unsigned long offset) 2136232809Sjmallett{ 2137232809Sjmallett if (!( 2138232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 2139232809Sjmallett cvmx_warn("CVMX_CIU2_SUM_IOX_INT(%lu) is invalid on this chip\n", offset); 2140232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8; 2141232809Sjmallett} 2142232809Sjmallett#else 2143232809Sjmallett#define CVMX_CIU2_SUM_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8) 2144232809Sjmallett#endif 2145232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2146232809Sjmallettstatic inline uint64_t CVMX_CIU2_SUM_PPX_IP2(unsigned long offset) 2147232809Sjmallett{ 2148232809Sjmallett if (!( 2149232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))))) 2150232809Sjmallett cvmx_warn("CVMX_CIU2_SUM_PPX_IP2(%lu) is invalid on this chip\n", offset); 2151232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8; 2152232809Sjmallett} 2153232809Sjmallett#else 2154232809Sjmallett#define CVMX_CIU2_SUM_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8) 2155232809Sjmallett#endif 2156232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2157232809Sjmallettstatic inline uint64_t CVMX_CIU2_SUM_PPX_IP3(unsigned long offset) 2158232809Sjmallett{ 2159232809Sjmallett if (!( 2160232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))))) 2161232809Sjmallett cvmx_warn("CVMX_CIU2_SUM_PPX_IP3(%lu) is invalid on this chip\n", offset); 2162232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8; 2163232809Sjmallett} 2164232809Sjmallett#else 2165232809Sjmallett#define CVMX_CIU2_SUM_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8) 2166232809Sjmallett#endif 2167232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2168232809Sjmallettstatic inline uint64_t CVMX_CIU2_SUM_PPX_IP4(unsigned long offset) 2169232809Sjmallett{ 2170232809Sjmallett if (!( 2171232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))))) 2172232809Sjmallett cvmx_warn("CVMX_CIU2_SUM_PPX_IP4(%lu) is invalid on this chip\n", offset); 2173232809Sjmallett return CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8; 2174232809Sjmallett} 2175232809Sjmallett#else 2176232809Sjmallett#define CVMX_CIU2_SUM_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8) 2177232809Sjmallett#endif 2178232809Sjmallett 2179232809Sjmallett/** 2180232809Sjmallett * cvmx_ciu2_ack_io#_int 2181232809Sjmallett */ 2182232809Sjmallettunion cvmx_ciu2_ack_iox_int { 2183232809Sjmallett uint64_t u64; 2184232809Sjmallett struct cvmx_ciu2_ack_iox_int_s { 2185232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2186232809Sjmallett uint64_t reserved_1_63 : 63; 2187232809Sjmallett uint64_t ack : 1; /**< Read to clear the corresponding interrupt to 2188232809Sjmallett PP/IO. Without this read the interrupt will not 2189232809Sjmallett deassert until the next CIU interrupt scan, up to 2190232809Sjmallett 200 cycles away. */ 2191232809Sjmallett#else 2192232809Sjmallett uint64_t ack : 1; 2193232809Sjmallett uint64_t reserved_1_63 : 63; 2194232809Sjmallett#endif 2195232809Sjmallett } s; 2196232809Sjmallett struct cvmx_ciu2_ack_iox_int_s cn68xx; 2197232809Sjmallett struct cvmx_ciu2_ack_iox_int_s cn68xxp1; 2198232809Sjmallett}; 2199232809Sjmalletttypedef union cvmx_ciu2_ack_iox_int cvmx_ciu2_ack_iox_int_t; 2200232809Sjmallett 2201232809Sjmallett/** 2202232809Sjmallett * cvmx_ciu2_ack_pp#_ip2 2203232809Sjmallett * 2204232809Sjmallett * CIU2_ACK_PPX_IPx (Pass 2) 2205232809Sjmallett * 2206232809Sjmallett */ 2207232809Sjmallettunion cvmx_ciu2_ack_ppx_ip2 { 2208232809Sjmallett uint64_t u64; 2209232809Sjmallett struct cvmx_ciu2_ack_ppx_ip2_s { 2210232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2211232809Sjmallett uint64_t reserved_1_63 : 63; 2212232809Sjmallett uint64_t ack : 1; /**< Read to clear the corresponding interrupt to 2213232809Sjmallett PP/IO. Without this read the interrupt will not 2214232809Sjmallett deassert until the next CIU interrupt scan, up to 2215232809Sjmallett 200 cycles away. */ 2216232809Sjmallett#else 2217232809Sjmallett uint64_t ack : 1; 2218232809Sjmallett uint64_t reserved_1_63 : 63; 2219232809Sjmallett#endif 2220232809Sjmallett } s; 2221232809Sjmallett struct cvmx_ciu2_ack_ppx_ip2_s cn68xx; 2222232809Sjmallett struct cvmx_ciu2_ack_ppx_ip2_s cn68xxp1; 2223232809Sjmallett}; 2224232809Sjmalletttypedef union cvmx_ciu2_ack_ppx_ip2 cvmx_ciu2_ack_ppx_ip2_t; 2225232809Sjmallett 2226232809Sjmallett/** 2227232809Sjmallett * cvmx_ciu2_ack_pp#_ip3 2228232809Sjmallett */ 2229232809Sjmallettunion cvmx_ciu2_ack_ppx_ip3 { 2230232809Sjmallett uint64_t u64; 2231232809Sjmallett struct cvmx_ciu2_ack_ppx_ip3_s { 2232232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2233232809Sjmallett uint64_t reserved_1_63 : 63; 2234232809Sjmallett uint64_t ack : 1; /**< Read to clear the corresponding interrupt to 2235232809Sjmallett PP/IO. Without this read the interrupt will not 2236232809Sjmallett deassert until the next CIU interrupt scan, up to 2237232809Sjmallett 200 cycles away. */ 2238232809Sjmallett#else 2239232809Sjmallett uint64_t ack : 1; 2240232809Sjmallett uint64_t reserved_1_63 : 63; 2241232809Sjmallett#endif 2242232809Sjmallett } s; 2243232809Sjmallett struct cvmx_ciu2_ack_ppx_ip3_s cn68xx; 2244232809Sjmallett struct cvmx_ciu2_ack_ppx_ip3_s cn68xxp1; 2245232809Sjmallett}; 2246232809Sjmalletttypedef union cvmx_ciu2_ack_ppx_ip3 cvmx_ciu2_ack_ppx_ip3_t; 2247232809Sjmallett 2248232809Sjmallett/** 2249232809Sjmallett * cvmx_ciu2_ack_pp#_ip4 2250232809Sjmallett */ 2251232809Sjmallettunion cvmx_ciu2_ack_ppx_ip4 { 2252232809Sjmallett uint64_t u64; 2253232809Sjmallett struct cvmx_ciu2_ack_ppx_ip4_s { 2254232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2255232809Sjmallett uint64_t reserved_1_63 : 63; 2256232809Sjmallett uint64_t ack : 1; /**< Read to clear the corresponding interrupt to 2257232809Sjmallett PP/IO. Without this read the interrupt will not 2258232809Sjmallett deassert until the next CIU interrupt scan, up to 2259232809Sjmallett 200 cycles away. */ 2260232809Sjmallett#else 2261232809Sjmallett uint64_t ack : 1; 2262232809Sjmallett uint64_t reserved_1_63 : 63; 2263232809Sjmallett#endif 2264232809Sjmallett } s; 2265232809Sjmallett struct cvmx_ciu2_ack_ppx_ip4_s cn68xx; 2266232809Sjmallett struct cvmx_ciu2_ack_ppx_ip4_s cn68xxp1; 2267232809Sjmallett}; 2268232809Sjmalletttypedef union cvmx_ciu2_ack_ppx_ip4 cvmx_ciu2_ack_ppx_ip4_t; 2269232809Sjmallett 2270232809Sjmallett/** 2271232809Sjmallett * cvmx_ciu2_en_io#_int_gpio 2272232809Sjmallett */ 2273232809Sjmallettunion cvmx_ciu2_en_iox_int_gpio { 2274232809Sjmallett uint64_t u64; 2275232809Sjmallett struct cvmx_ciu2_en_iox_int_gpio_s { 2276232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2277232809Sjmallett uint64_t reserved_16_63 : 48; 2278232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupt-enable */ 2279232809Sjmallett#else 2280232809Sjmallett uint64_t gpio : 16; 2281232809Sjmallett uint64_t reserved_16_63 : 48; 2282232809Sjmallett#endif 2283232809Sjmallett } s; 2284232809Sjmallett struct cvmx_ciu2_en_iox_int_gpio_s cn68xx; 2285232809Sjmallett struct cvmx_ciu2_en_iox_int_gpio_s cn68xxp1; 2286232809Sjmallett}; 2287232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_gpio cvmx_ciu2_en_iox_int_gpio_t; 2288232809Sjmallett 2289232809Sjmallett/** 2290232809Sjmallett * cvmx_ciu2_en_io#_int_gpio_w1c 2291232809Sjmallett */ 2292232809Sjmallettunion cvmx_ciu2_en_iox_int_gpio_w1c { 2293232809Sjmallett uint64_t u64; 2294232809Sjmallett struct cvmx_ciu2_en_iox_int_gpio_w1c_s { 2295232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2296232809Sjmallett uint64_t reserved_16_63 : 48; 2297232809Sjmallett uint64_t gpio : 16; /**< Write 1 to clear CIU2_EN_xx_yy_GPIO[GPIO] */ 2298232809Sjmallett#else 2299232809Sjmallett uint64_t gpio : 16; 2300232809Sjmallett uint64_t reserved_16_63 : 48; 2301232809Sjmallett#endif 2302232809Sjmallett } s; 2303232809Sjmallett struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xx; 2304232809Sjmallett struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xxp1; 2305232809Sjmallett}; 2306232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_gpio_w1c cvmx_ciu2_en_iox_int_gpio_w1c_t; 2307232809Sjmallett 2308232809Sjmallett/** 2309232809Sjmallett * cvmx_ciu2_en_io#_int_gpio_w1s 2310232809Sjmallett */ 2311232809Sjmallettunion cvmx_ciu2_en_iox_int_gpio_w1s { 2312232809Sjmallett uint64_t u64; 2313232809Sjmallett struct cvmx_ciu2_en_iox_int_gpio_w1s_s { 2314232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2315232809Sjmallett uint64_t reserved_16_63 : 48; 2316232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupt enable,write 1 to enable CIU2_EN */ 2317232809Sjmallett#else 2318232809Sjmallett uint64_t gpio : 16; 2319232809Sjmallett uint64_t reserved_16_63 : 48; 2320232809Sjmallett#endif 2321232809Sjmallett } s; 2322232809Sjmallett struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xx; 2323232809Sjmallett struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xxp1; 2324232809Sjmallett}; 2325232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_gpio_w1s cvmx_ciu2_en_iox_int_gpio_w1s_t; 2326232809Sjmallett 2327232809Sjmallett/** 2328232809Sjmallett * cvmx_ciu2_en_io#_int_io 2329232809Sjmallett */ 2330232809Sjmallettunion cvmx_ciu2_en_iox_int_io { 2331232809Sjmallett uint64_t u64; 2332232809Sjmallett struct cvmx_ciu2_en_iox_int_io_s { 2333232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2334232809Sjmallett uint64_t reserved_34_63 : 30; 2335232809Sjmallett uint64_t pem : 2; /**< PEMx interrupt-enable */ 2336232809Sjmallett uint64_t reserved_18_31 : 14; 2337232809Sjmallett uint64_t pci_inta : 2; /**< PCI_INTA interrupt-enable */ 2338232809Sjmallett uint64_t reserved_13_15 : 3; 2339232809Sjmallett uint64_t msired : 1; /**< MSI summary bit interrupt-enable 2340232809Sjmallett This bit may not be functional in pass 1. */ 2341232809Sjmallett uint64_t pci_msi : 4; /**< PCIe/sRIO MSI interrupt-enable */ 2342232809Sjmallett uint64_t reserved_4_7 : 4; 2343232809Sjmallett uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt-enable */ 2344232809Sjmallett#else 2345232809Sjmallett uint64_t pci_intr : 4; 2346232809Sjmallett uint64_t reserved_4_7 : 4; 2347232809Sjmallett uint64_t pci_msi : 4; 2348232809Sjmallett uint64_t msired : 1; 2349232809Sjmallett uint64_t reserved_13_15 : 3; 2350232809Sjmallett uint64_t pci_inta : 2; 2351232809Sjmallett uint64_t reserved_18_31 : 14; 2352232809Sjmallett uint64_t pem : 2; 2353232809Sjmallett uint64_t reserved_34_63 : 30; 2354232809Sjmallett#endif 2355232809Sjmallett } s; 2356232809Sjmallett struct cvmx_ciu2_en_iox_int_io_s cn68xx; 2357232809Sjmallett struct cvmx_ciu2_en_iox_int_io_s cn68xxp1; 2358232809Sjmallett}; 2359232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_io cvmx_ciu2_en_iox_int_io_t; 2360232809Sjmallett 2361232809Sjmallett/** 2362232809Sjmallett * cvmx_ciu2_en_io#_int_io_w1c 2363232809Sjmallett */ 2364232809Sjmallettunion cvmx_ciu2_en_iox_int_io_w1c { 2365232809Sjmallett uint64_t u64; 2366232809Sjmallett struct cvmx_ciu2_en_iox_int_io_w1c_s { 2367232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2368232809Sjmallett uint64_t reserved_34_63 : 30; 2369232809Sjmallett uint64_t pem : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PEM] */ 2370232809Sjmallett uint64_t reserved_18_31 : 14; 2371232809Sjmallett uint64_t pci_inta : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTA] */ 2372232809Sjmallett uint64_t reserved_13_15 : 3; 2373232809Sjmallett uint64_t msired : 1; /**< Write 1 to clear CIU2_EN_xx_yy_IO[MSIRED] 2374232809Sjmallett This bit may not be functional in pass 1. */ 2375232809Sjmallett uint64_t pci_msi : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_MSI] */ 2376232809Sjmallett uint64_t reserved_4_7 : 4; 2377232809Sjmallett uint64_t pci_intr : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTR] */ 2378232809Sjmallett#else 2379232809Sjmallett uint64_t pci_intr : 4; 2380232809Sjmallett uint64_t reserved_4_7 : 4; 2381232809Sjmallett uint64_t pci_msi : 4; 2382232809Sjmallett uint64_t msired : 1; 2383232809Sjmallett uint64_t reserved_13_15 : 3; 2384232809Sjmallett uint64_t pci_inta : 2; 2385232809Sjmallett uint64_t reserved_18_31 : 14; 2386232809Sjmallett uint64_t pem : 2; 2387232809Sjmallett uint64_t reserved_34_63 : 30; 2388232809Sjmallett#endif 2389232809Sjmallett } s; 2390232809Sjmallett struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xx; 2391232809Sjmallett struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xxp1; 2392232809Sjmallett}; 2393232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_io_w1c cvmx_ciu2_en_iox_int_io_w1c_t; 2394232809Sjmallett 2395232809Sjmallett/** 2396232809Sjmallett * cvmx_ciu2_en_io#_int_io_w1s 2397232809Sjmallett */ 2398232809Sjmallettunion cvmx_ciu2_en_iox_int_io_w1s { 2399232809Sjmallett uint64_t u64; 2400232809Sjmallett struct cvmx_ciu2_en_iox_int_io_w1s_s { 2401232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2402232809Sjmallett uint64_t reserved_34_63 : 30; 2403232809Sjmallett uint64_t pem : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PEM] */ 2404232809Sjmallett uint64_t reserved_18_31 : 14; 2405232809Sjmallett uint64_t pci_inta : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTA] */ 2406232809Sjmallett uint64_t reserved_13_15 : 3; 2407232809Sjmallett uint64_t msired : 1; /**< Write 1 to enable CIU2_EN_xx_yy_IO[MSIRED] 2408232809Sjmallett This bit may not be functional in pass 1. */ 2409232809Sjmallett uint64_t pci_msi : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_MSI] */ 2410232809Sjmallett uint64_t reserved_4_7 : 4; 2411232809Sjmallett uint64_t pci_intr : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTR] */ 2412232809Sjmallett#else 2413232809Sjmallett uint64_t pci_intr : 4; 2414232809Sjmallett uint64_t reserved_4_7 : 4; 2415232809Sjmallett uint64_t pci_msi : 4; 2416232809Sjmallett uint64_t msired : 1; 2417232809Sjmallett uint64_t reserved_13_15 : 3; 2418232809Sjmallett uint64_t pci_inta : 2; 2419232809Sjmallett uint64_t reserved_18_31 : 14; 2420232809Sjmallett uint64_t pem : 2; 2421232809Sjmallett uint64_t reserved_34_63 : 30; 2422232809Sjmallett#endif 2423232809Sjmallett } s; 2424232809Sjmallett struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xx; 2425232809Sjmallett struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xxp1; 2426232809Sjmallett}; 2427232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_io_w1s cvmx_ciu2_en_iox_int_io_w1s_t; 2428232809Sjmallett 2429232809Sjmallett/** 2430232809Sjmallett * cvmx_ciu2_en_io#_int_mbox 2431232809Sjmallett */ 2432232809Sjmallettunion cvmx_ciu2_en_iox_int_mbox { 2433232809Sjmallett uint64_t u64; 2434232809Sjmallett struct cvmx_ciu2_en_iox_int_mbox_s { 2435232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2436232809Sjmallett uint64_t reserved_4_63 : 60; 2437232809Sjmallett uint64_t mbox : 4; /**< Mailbox interrupt-enable, use with CIU2_MBOX 2438232809Sjmallett to generate CIU2_SRC_xx_yy_MBOX */ 2439232809Sjmallett#else 2440232809Sjmallett uint64_t mbox : 4; 2441232809Sjmallett uint64_t reserved_4_63 : 60; 2442232809Sjmallett#endif 2443232809Sjmallett } s; 2444232809Sjmallett struct cvmx_ciu2_en_iox_int_mbox_s cn68xx; 2445232809Sjmallett struct cvmx_ciu2_en_iox_int_mbox_s cn68xxp1; 2446232809Sjmallett}; 2447232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_mbox cvmx_ciu2_en_iox_int_mbox_t; 2448232809Sjmallett 2449232809Sjmallett/** 2450232809Sjmallett * cvmx_ciu2_en_io#_int_mbox_w1c 2451232809Sjmallett */ 2452232809Sjmallettunion cvmx_ciu2_en_iox_int_mbox_w1c { 2453232809Sjmallett uint64_t u64; 2454232809Sjmallett struct cvmx_ciu2_en_iox_int_mbox_w1c_s { 2455232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2456232809Sjmallett uint64_t reserved_4_63 : 60; 2457232809Sjmallett uint64_t mbox : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MBOX[MBOX] */ 2458232809Sjmallett#else 2459232809Sjmallett uint64_t mbox : 4; 2460232809Sjmallett uint64_t reserved_4_63 : 60; 2461232809Sjmallett#endif 2462232809Sjmallett } s; 2463232809Sjmallett struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xx; 2464232809Sjmallett struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xxp1; 2465232809Sjmallett}; 2466232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_mbox_w1c cvmx_ciu2_en_iox_int_mbox_w1c_t; 2467232809Sjmallett 2468232809Sjmallett/** 2469232809Sjmallett * cvmx_ciu2_en_io#_int_mbox_w1s 2470232809Sjmallett */ 2471232809Sjmallettunion cvmx_ciu2_en_iox_int_mbox_w1s { 2472232809Sjmallett uint64_t u64; 2473232809Sjmallett struct cvmx_ciu2_en_iox_int_mbox_w1s_s { 2474232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2475232809Sjmallett uint64_t reserved_4_63 : 60; 2476232809Sjmallett uint64_t mbox : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MBOX[MBOX] */ 2477232809Sjmallett#else 2478232809Sjmallett uint64_t mbox : 4; 2479232809Sjmallett uint64_t reserved_4_63 : 60; 2480232809Sjmallett#endif 2481232809Sjmallett } s; 2482232809Sjmallett struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xx; 2483232809Sjmallett struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xxp1; 2484232809Sjmallett}; 2485232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_mbox_w1s cvmx_ciu2_en_iox_int_mbox_w1s_t; 2486232809Sjmallett 2487232809Sjmallett/** 2488232809Sjmallett * cvmx_ciu2_en_io#_int_mem 2489232809Sjmallett */ 2490232809Sjmallettunion cvmx_ciu2_en_iox_int_mem { 2491232809Sjmallett uint64_t u64; 2492232809Sjmallett struct cvmx_ciu2_en_iox_int_mem_s { 2493232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2494232809Sjmallett uint64_t reserved_4_63 : 60; 2495232809Sjmallett uint64_t lmc : 4; /**< LMC* interrupt-enable */ 2496232809Sjmallett#else 2497232809Sjmallett uint64_t lmc : 4; 2498232809Sjmallett uint64_t reserved_4_63 : 60; 2499232809Sjmallett#endif 2500232809Sjmallett } s; 2501232809Sjmallett struct cvmx_ciu2_en_iox_int_mem_s cn68xx; 2502232809Sjmallett struct cvmx_ciu2_en_iox_int_mem_s cn68xxp1; 2503232809Sjmallett}; 2504232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_mem cvmx_ciu2_en_iox_int_mem_t; 2505232809Sjmallett 2506232809Sjmallett/** 2507232809Sjmallett * cvmx_ciu2_en_io#_int_mem_w1c 2508232809Sjmallett */ 2509232809Sjmallettunion cvmx_ciu2_en_iox_int_mem_w1c { 2510232809Sjmallett uint64_t u64; 2511232809Sjmallett struct cvmx_ciu2_en_iox_int_mem_w1c_s { 2512232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2513232809Sjmallett uint64_t reserved_4_63 : 60; 2514232809Sjmallett uint64_t lmc : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MEM[LMC] */ 2515232809Sjmallett#else 2516232809Sjmallett uint64_t lmc : 4; 2517232809Sjmallett uint64_t reserved_4_63 : 60; 2518232809Sjmallett#endif 2519232809Sjmallett } s; 2520232809Sjmallett struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xx; 2521232809Sjmallett struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xxp1; 2522232809Sjmallett}; 2523232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_mem_w1c cvmx_ciu2_en_iox_int_mem_w1c_t; 2524232809Sjmallett 2525232809Sjmallett/** 2526232809Sjmallett * cvmx_ciu2_en_io#_int_mem_w1s 2527232809Sjmallett */ 2528232809Sjmallettunion cvmx_ciu2_en_iox_int_mem_w1s { 2529232809Sjmallett uint64_t u64; 2530232809Sjmallett struct cvmx_ciu2_en_iox_int_mem_w1s_s { 2531232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2532232809Sjmallett uint64_t reserved_4_63 : 60; 2533232809Sjmallett uint64_t lmc : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MEM[LMC] */ 2534232809Sjmallett#else 2535232809Sjmallett uint64_t lmc : 4; 2536232809Sjmallett uint64_t reserved_4_63 : 60; 2537232809Sjmallett#endif 2538232809Sjmallett } s; 2539232809Sjmallett struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xx; 2540232809Sjmallett struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xxp1; 2541232809Sjmallett}; 2542232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_mem_w1s cvmx_ciu2_en_iox_int_mem_w1s_t; 2543232809Sjmallett 2544232809Sjmallett/** 2545232809Sjmallett * cvmx_ciu2_en_io#_int_mio 2546232809Sjmallett */ 2547232809Sjmallettunion cvmx_ciu2_en_iox_int_mio { 2548232809Sjmallett uint64_t u64; 2549232809Sjmallett struct cvmx_ciu2_en_iox_int_mio_s { 2550232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2551232809Sjmallett uint64_t rst : 1; /**< MIO RST interrupt-enable */ 2552232809Sjmallett uint64_t reserved_49_62 : 14; 2553232809Sjmallett uint64_t ptp : 1; /**< PTP interrupt-enable */ 2554232809Sjmallett uint64_t reserved_45_47 : 3; 2555232809Sjmallett uint64_t usb_hci : 1; /**< USB HCI Interrupt-enable */ 2556232809Sjmallett uint64_t reserved_41_43 : 3; 2557232809Sjmallett uint64_t usb_uctl : 1; /**< USB UCTL* interrupt-enable */ 2558232809Sjmallett uint64_t reserved_38_39 : 2; 2559232809Sjmallett uint64_t uart : 2; /**< Two UART interrupt-enable */ 2560232809Sjmallett uint64_t reserved_34_35 : 2; 2561232809Sjmallett uint64_t twsi : 2; /**< TWSI x interrupt-enable */ 2562232809Sjmallett uint64_t reserved_19_31 : 13; 2563232809Sjmallett uint64_t bootdma : 1; /**< Boot bus DMA engines interrupt-enable */ 2564232809Sjmallett uint64_t mio : 1; /**< MIO boot interrupt-enable */ 2565232809Sjmallett uint64_t nand : 1; /**< NAND Flash Controller interrupt-enable */ 2566232809Sjmallett uint64_t reserved_12_15 : 4; 2567232809Sjmallett uint64_t timer : 4; /**< General timer interrupt-enable */ 2568232809Sjmallett uint64_t reserved_3_7 : 5; 2569232809Sjmallett uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt-enable */ 2570232809Sjmallett uint64_t ssoiq : 1; /**< SSO IQ interrupt-enable */ 2571232809Sjmallett uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt-enable */ 2572232809Sjmallett#else 2573232809Sjmallett uint64_t ipdppthr : 1; 2574232809Sjmallett uint64_t ssoiq : 1; 2575232809Sjmallett uint64_t ipd_drp : 1; 2576232809Sjmallett uint64_t reserved_3_7 : 5; 2577232809Sjmallett uint64_t timer : 4; 2578232809Sjmallett uint64_t reserved_12_15 : 4; 2579232809Sjmallett uint64_t nand : 1; 2580232809Sjmallett uint64_t mio : 1; 2581232809Sjmallett uint64_t bootdma : 1; 2582232809Sjmallett uint64_t reserved_19_31 : 13; 2583232809Sjmallett uint64_t twsi : 2; 2584232809Sjmallett uint64_t reserved_34_35 : 2; 2585232809Sjmallett uint64_t uart : 2; 2586232809Sjmallett uint64_t reserved_38_39 : 2; 2587232809Sjmallett uint64_t usb_uctl : 1; 2588232809Sjmallett uint64_t reserved_41_43 : 3; 2589232809Sjmallett uint64_t usb_hci : 1; 2590232809Sjmallett uint64_t reserved_45_47 : 3; 2591232809Sjmallett uint64_t ptp : 1; 2592232809Sjmallett uint64_t reserved_49_62 : 14; 2593232809Sjmallett uint64_t rst : 1; 2594232809Sjmallett#endif 2595232809Sjmallett } s; 2596232809Sjmallett struct cvmx_ciu2_en_iox_int_mio_s cn68xx; 2597232809Sjmallett struct cvmx_ciu2_en_iox_int_mio_s cn68xxp1; 2598232809Sjmallett}; 2599232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_mio cvmx_ciu2_en_iox_int_mio_t; 2600232809Sjmallett 2601232809Sjmallett/** 2602232809Sjmallett * cvmx_ciu2_en_io#_int_mio_w1c 2603232809Sjmallett */ 2604232809Sjmallettunion cvmx_ciu2_en_iox_int_mio_w1c { 2605232809Sjmallett uint64_t u64; 2606232809Sjmallett struct cvmx_ciu2_en_iox_int_mio_w1c_s { 2607232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2608232809Sjmallett uint64_t rst : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[RST] */ 2609232809Sjmallett uint64_t reserved_49_62 : 14; 2610232809Sjmallett uint64_t ptp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[PTP] */ 2611232809Sjmallett uint64_t reserved_45_47 : 3; 2612232809Sjmallett uint64_t usb_hci : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_HCI] */ 2613232809Sjmallett uint64_t reserved_41_43 : 3; 2614232809Sjmallett uint64_t usb_uctl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_UCTL] */ 2615232809Sjmallett uint64_t reserved_38_39 : 2; 2616232809Sjmallett uint64_t uart : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[UART] */ 2617232809Sjmallett uint64_t reserved_34_35 : 2; 2618232809Sjmallett uint64_t twsi : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TWSI] */ 2619232809Sjmallett uint64_t reserved_19_31 : 13; 2620232809Sjmallett uint64_t bootdma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[BOOTDMA] */ 2621232809Sjmallett uint64_t mio : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[MIO] */ 2622232809Sjmallett uint64_t nand : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[NAND] */ 2623232809Sjmallett uint64_t reserved_12_15 : 4; 2624232809Sjmallett uint64_t timer : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TIMER] */ 2625232809Sjmallett uint64_t reserved_3_7 : 5; 2626232809Sjmallett uint64_t ipd_drp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPD_DRP] */ 2627232809Sjmallett uint64_t ssoiq : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[SSQIQ] */ 2628232809Sjmallett uint64_t ipdppthr : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPDPPTHR] */ 2629232809Sjmallett#else 2630232809Sjmallett uint64_t ipdppthr : 1; 2631232809Sjmallett uint64_t ssoiq : 1; 2632232809Sjmallett uint64_t ipd_drp : 1; 2633232809Sjmallett uint64_t reserved_3_7 : 5; 2634232809Sjmallett uint64_t timer : 4; 2635232809Sjmallett uint64_t reserved_12_15 : 4; 2636232809Sjmallett uint64_t nand : 1; 2637232809Sjmallett uint64_t mio : 1; 2638232809Sjmallett uint64_t bootdma : 1; 2639232809Sjmallett uint64_t reserved_19_31 : 13; 2640232809Sjmallett uint64_t twsi : 2; 2641232809Sjmallett uint64_t reserved_34_35 : 2; 2642232809Sjmallett uint64_t uart : 2; 2643232809Sjmallett uint64_t reserved_38_39 : 2; 2644232809Sjmallett uint64_t usb_uctl : 1; 2645232809Sjmallett uint64_t reserved_41_43 : 3; 2646232809Sjmallett uint64_t usb_hci : 1; 2647232809Sjmallett uint64_t reserved_45_47 : 3; 2648232809Sjmallett uint64_t ptp : 1; 2649232809Sjmallett uint64_t reserved_49_62 : 14; 2650232809Sjmallett uint64_t rst : 1; 2651232809Sjmallett#endif 2652232809Sjmallett } s; 2653232809Sjmallett struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xx; 2654232809Sjmallett struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xxp1; 2655232809Sjmallett}; 2656232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_mio_w1c cvmx_ciu2_en_iox_int_mio_w1c_t; 2657232809Sjmallett 2658232809Sjmallett/** 2659232809Sjmallett * cvmx_ciu2_en_io#_int_mio_w1s 2660232809Sjmallett */ 2661232809Sjmallettunion cvmx_ciu2_en_iox_int_mio_w1s { 2662232809Sjmallett uint64_t u64; 2663232809Sjmallett struct cvmx_ciu2_en_iox_int_mio_w1s_s { 2664232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2665232809Sjmallett uint64_t rst : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[RST] */ 2666232809Sjmallett uint64_t reserved_49_62 : 14; 2667232809Sjmallett uint64_t ptp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[PTP] */ 2668232809Sjmallett uint64_t reserved_45_47 : 3; 2669232809Sjmallett uint64_t usb_hci : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_HCI] */ 2670232809Sjmallett uint64_t reserved_41_43 : 3; 2671232809Sjmallett uint64_t usb_uctl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_UCTL] */ 2672232809Sjmallett uint64_t reserved_38_39 : 2; 2673232809Sjmallett uint64_t uart : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[UART] */ 2674232809Sjmallett uint64_t reserved_34_35 : 2; 2675232809Sjmallett uint64_t twsi : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TWSI] */ 2676232809Sjmallett uint64_t reserved_19_31 : 13; 2677232809Sjmallett uint64_t bootdma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[BOOTDMA] */ 2678232809Sjmallett uint64_t mio : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[MIO] */ 2679232809Sjmallett uint64_t nand : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[NAND] */ 2680232809Sjmallett uint64_t reserved_12_15 : 4; 2681232809Sjmallett uint64_t timer : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TIMER] */ 2682232809Sjmallett uint64_t reserved_3_7 : 5; 2683232809Sjmallett uint64_t ipd_drp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPD_DRP] */ 2684232809Sjmallett uint64_t ssoiq : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[SSQIQ] */ 2685232809Sjmallett uint64_t ipdppthr : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPDPPTHR] */ 2686232809Sjmallett#else 2687232809Sjmallett uint64_t ipdppthr : 1; 2688232809Sjmallett uint64_t ssoiq : 1; 2689232809Sjmallett uint64_t ipd_drp : 1; 2690232809Sjmallett uint64_t reserved_3_7 : 5; 2691232809Sjmallett uint64_t timer : 4; 2692232809Sjmallett uint64_t reserved_12_15 : 4; 2693232809Sjmallett uint64_t nand : 1; 2694232809Sjmallett uint64_t mio : 1; 2695232809Sjmallett uint64_t bootdma : 1; 2696232809Sjmallett uint64_t reserved_19_31 : 13; 2697232809Sjmallett uint64_t twsi : 2; 2698232809Sjmallett uint64_t reserved_34_35 : 2; 2699232809Sjmallett uint64_t uart : 2; 2700232809Sjmallett uint64_t reserved_38_39 : 2; 2701232809Sjmallett uint64_t usb_uctl : 1; 2702232809Sjmallett uint64_t reserved_41_43 : 3; 2703232809Sjmallett uint64_t usb_hci : 1; 2704232809Sjmallett uint64_t reserved_45_47 : 3; 2705232809Sjmallett uint64_t ptp : 1; 2706232809Sjmallett uint64_t reserved_49_62 : 14; 2707232809Sjmallett uint64_t rst : 1; 2708232809Sjmallett#endif 2709232809Sjmallett } s; 2710232809Sjmallett struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xx; 2711232809Sjmallett struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xxp1; 2712232809Sjmallett}; 2713232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_mio_w1s cvmx_ciu2_en_iox_int_mio_w1s_t; 2714232809Sjmallett 2715232809Sjmallett/** 2716232809Sjmallett * cvmx_ciu2_en_io#_int_pkt 2717232809Sjmallett */ 2718232809Sjmallettunion cvmx_ciu2_en_iox_int_pkt { 2719232809Sjmallett uint64_t u64; 2720232809Sjmallett struct cvmx_ciu2_en_iox_int_pkt_s { 2721232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2722232809Sjmallett uint64_t reserved_54_63 : 10; 2723232809Sjmallett uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt-enable */ 2724232809Sjmallett uint64_t reserved_49_51 : 3; 2725232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupt-enable */ 2726232809Sjmallett uint64_t reserved_41_47 : 7; 2727232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */ 2728232809Sjmallett uint64_t reserved_33_39 : 7; 2729232809Sjmallett uint64_t agl : 1; /**< AGL interrupt-enable */ 2730232809Sjmallett uint64_t reserved_13_31 : 19; 2731232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */ 2732232809Sjmallett uint64_t reserved_5_7 : 3; 2733232809Sjmallett uint64_t agx : 5; /**< GMX interrupt-enable */ 2734232809Sjmallett#else 2735232809Sjmallett uint64_t agx : 5; 2736232809Sjmallett uint64_t reserved_5_7 : 3; 2737232809Sjmallett uint64_t gmx_drp : 5; 2738232809Sjmallett uint64_t reserved_13_31 : 19; 2739232809Sjmallett uint64_t agl : 1; 2740232809Sjmallett uint64_t reserved_33_39 : 7; 2741232809Sjmallett uint64_t mii : 1; 2742232809Sjmallett uint64_t reserved_41_47 : 7; 2743232809Sjmallett uint64_t ilk : 1; 2744232809Sjmallett uint64_t reserved_49_51 : 3; 2745232809Sjmallett uint64_t ilk_drp : 2; 2746232809Sjmallett uint64_t reserved_54_63 : 10; 2747232809Sjmallett#endif 2748232809Sjmallett } s; 2749232809Sjmallett struct cvmx_ciu2_en_iox_int_pkt_s cn68xx; 2750232809Sjmallett struct cvmx_ciu2_en_iox_int_pkt_cn68xxp1 { 2751232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2752232809Sjmallett uint64_t reserved_49_63 : 15; 2753232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupt-enable */ 2754232809Sjmallett uint64_t reserved_41_47 : 7; 2755232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */ 2756232809Sjmallett uint64_t reserved_33_39 : 7; 2757232809Sjmallett uint64_t agl : 1; /**< AGL interrupt-enable */ 2758232809Sjmallett uint64_t reserved_13_31 : 19; 2759232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */ 2760232809Sjmallett uint64_t reserved_5_7 : 3; 2761232809Sjmallett uint64_t agx : 5; /**< GMX interrupt-enable */ 2762232809Sjmallett#else 2763232809Sjmallett uint64_t agx : 5; 2764232809Sjmallett uint64_t reserved_5_7 : 3; 2765232809Sjmallett uint64_t gmx_drp : 5; 2766232809Sjmallett uint64_t reserved_13_31 : 19; 2767232809Sjmallett uint64_t agl : 1; 2768232809Sjmallett uint64_t reserved_33_39 : 7; 2769232809Sjmallett uint64_t mii : 1; 2770232809Sjmallett uint64_t reserved_41_47 : 7; 2771232809Sjmallett uint64_t ilk : 1; 2772232809Sjmallett uint64_t reserved_49_63 : 15; 2773232809Sjmallett#endif 2774232809Sjmallett } cn68xxp1; 2775232809Sjmallett}; 2776232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_pkt cvmx_ciu2_en_iox_int_pkt_t; 2777232809Sjmallett 2778232809Sjmallett/** 2779232809Sjmallett * cvmx_ciu2_en_io#_int_pkt_w1c 2780232809Sjmallett */ 2781232809Sjmallettunion cvmx_ciu2_en_iox_int_pkt_w1c { 2782232809Sjmallett uint64_t u64; 2783232809Sjmallett struct cvmx_ciu2_en_iox_int_pkt_w1c_s { 2784232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2785232809Sjmallett uint64_t reserved_54_63 : 10; 2786232809Sjmallett uint64_t ilk_drp : 2; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK_DRP] */ 2787232809Sjmallett uint64_t reserved_49_51 : 3; 2788232809Sjmallett uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */ 2789232809Sjmallett uint64_t reserved_41_47 : 7; 2790232809Sjmallett uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */ 2791232809Sjmallett uint64_t reserved_33_39 : 7; 2792232809Sjmallett uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */ 2793232809Sjmallett uint64_t reserved_13_31 : 19; 2794232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */ 2795232809Sjmallett uint64_t reserved_5_7 : 3; 2796232809Sjmallett uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */ 2797232809Sjmallett#else 2798232809Sjmallett uint64_t agx : 5; 2799232809Sjmallett uint64_t reserved_5_7 : 3; 2800232809Sjmallett uint64_t gmx_drp : 5; 2801232809Sjmallett uint64_t reserved_13_31 : 19; 2802232809Sjmallett uint64_t agl : 1; 2803232809Sjmallett uint64_t reserved_33_39 : 7; 2804232809Sjmallett uint64_t mii : 1; 2805232809Sjmallett uint64_t reserved_41_47 : 7; 2806232809Sjmallett uint64_t ilk : 1; 2807232809Sjmallett uint64_t reserved_49_51 : 3; 2808232809Sjmallett uint64_t ilk_drp : 2; 2809232809Sjmallett uint64_t reserved_54_63 : 10; 2810232809Sjmallett#endif 2811232809Sjmallett } s; 2812232809Sjmallett struct cvmx_ciu2_en_iox_int_pkt_w1c_s cn68xx; 2813232809Sjmallett struct cvmx_ciu2_en_iox_int_pkt_w1c_cn68xxp1 { 2814232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2815232809Sjmallett uint64_t reserved_49_63 : 15; 2816232809Sjmallett uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */ 2817232809Sjmallett uint64_t reserved_41_47 : 7; 2818232809Sjmallett uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */ 2819232809Sjmallett uint64_t reserved_33_39 : 7; 2820232809Sjmallett uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */ 2821232809Sjmallett uint64_t reserved_13_31 : 19; 2822232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */ 2823232809Sjmallett uint64_t reserved_5_7 : 3; 2824232809Sjmallett uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */ 2825232809Sjmallett#else 2826232809Sjmallett uint64_t agx : 5; 2827232809Sjmallett uint64_t reserved_5_7 : 3; 2828232809Sjmallett uint64_t gmx_drp : 5; 2829232809Sjmallett uint64_t reserved_13_31 : 19; 2830232809Sjmallett uint64_t agl : 1; 2831232809Sjmallett uint64_t reserved_33_39 : 7; 2832232809Sjmallett uint64_t mii : 1; 2833232809Sjmallett uint64_t reserved_41_47 : 7; 2834232809Sjmallett uint64_t ilk : 1; 2835232809Sjmallett uint64_t reserved_49_63 : 15; 2836232809Sjmallett#endif 2837232809Sjmallett } cn68xxp1; 2838232809Sjmallett}; 2839232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_pkt_w1c cvmx_ciu2_en_iox_int_pkt_w1c_t; 2840232809Sjmallett 2841232809Sjmallett/** 2842232809Sjmallett * cvmx_ciu2_en_io#_int_pkt_w1s 2843232809Sjmallett */ 2844232809Sjmallettunion cvmx_ciu2_en_iox_int_pkt_w1s { 2845232809Sjmallett uint64_t u64; 2846232809Sjmallett struct cvmx_ciu2_en_iox_int_pkt_w1s_s { 2847232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2848232809Sjmallett uint64_t reserved_54_63 : 10; 2849232809Sjmallett uint64_t ilk_drp : 2; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK_DRP] */ 2850232809Sjmallett uint64_t reserved_49_51 : 3; 2851232809Sjmallett uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */ 2852232809Sjmallett uint64_t reserved_41_47 : 7; 2853232809Sjmallett uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */ 2854232809Sjmallett uint64_t reserved_33_39 : 7; 2855232809Sjmallett uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */ 2856232809Sjmallett uint64_t reserved_13_31 : 19; 2857232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */ 2858232809Sjmallett uint64_t reserved_5_7 : 3; 2859232809Sjmallett uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */ 2860232809Sjmallett#else 2861232809Sjmallett uint64_t agx : 5; 2862232809Sjmallett uint64_t reserved_5_7 : 3; 2863232809Sjmallett uint64_t gmx_drp : 5; 2864232809Sjmallett uint64_t reserved_13_31 : 19; 2865232809Sjmallett uint64_t agl : 1; 2866232809Sjmallett uint64_t reserved_33_39 : 7; 2867232809Sjmallett uint64_t mii : 1; 2868232809Sjmallett uint64_t reserved_41_47 : 7; 2869232809Sjmallett uint64_t ilk : 1; 2870232809Sjmallett uint64_t reserved_49_51 : 3; 2871232809Sjmallett uint64_t ilk_drp : 2; 2872232809Sjmallett uint64_t reserved_54_63 : 10; 2873232809Sjmallett#endif 2874232809Sjmallett } s; 2875232809Sjmallett struct cvmx_ciu2_en_iox_int_pkt_w1s_s cn68xx; 2876232809Sjmallett struct cvmx_ciu2_en_iox_int_pkt_w1s_cn68xxp1 { 2877232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2878232809Sjmallett uint64_t reserved_49_63 : 15; 2879232809Sjmallett uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */ 2880232809Sjmallett uint64_t reserved_41_47 : 7; 2881232809Sjmallett uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */ 2882232809Sjmallett uint64_t reserved_33_39 : 7; 2883232809Sjmallett uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */ 2884232809Sjmallett uint64_t reserved_13_31 : 19; 2885232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */ 2886232809Sjmallett uint64_t reserved_5_7 : 3; 2887232809Sjmallett uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */ 2888232809Sjmallett#else 2889232809Sjmallett uint64_t agx : 5; 2890232809Sjmallett uint64_t reserved_5_7 : 3; 2891232809Sjmallett uint64_t gmx_drp : 5; 2892232809Sjmallett uint64_t reserved_13_31 : 19; 2893232809Sjmallett uint64_t agl : 1; 2894232809Sjmallett uint64_t reserved_33_39 : 7; 2895232809Sjmallett uint64_t mii : 1; 2896232809Sjmallett uint64_t reserved_41_47 : 7; 2897232809Sjmallett uint64_t ilk : 1; 2898232809Sjmallett uint64_t reserved_49_63 : 15; 2899232809Sjmallett#endif 2900232809Sjmallett } cn68xxp1; 2901232809Sjmallett}; 2902232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_pkt_w1s cvmx_ciu2_en_iox_int_pkt_w1s_t; 2903232809Sjmallett 2904232809Sjmallett/** 2905232809Sjmallett * cvmx_ciu2_en_io#_int_rml 2906232809Sjmallett */ 2907232809Sjmallettunion cvmx_ciu2_en_iox_int_rml { 2908232809Sjmallett uint64_t u64; 2909232809Sjmallett struct cvmx_ciu2_en_iox_int_rml_s { 2910232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2911232809Sjmallett uint64_t reserved_56_63 : 8; 2912232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt-enable */ 2913232809Sjmallett uint64_t reserved_49_51 : 3; 2914232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt-enable */ 2915232809Sjmallett uint64_t reserved_41_47 : 7; 2916232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt-enable */ 2917232809Sjmallett uint64_t reserved_37_39 : 3; 2918232809Sjmallett uint64_t dpi_dma : 1; /**< DPI DMA interrupt-enable */ 2919232809Sjmallett uint64_t reserved_34_35 : 2; 2920232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt-enable */ 2921232809Sjmallett uint64_t sli : 1; /**< SLI interrupt-enable */ 2922232809Sjmallett uint64_t reserved_31_31 : 1; 2923232809Sjmallett uint64_t key : 1; /**< KEY interrupt-enable */ 2924232809Sjmallett uint64_t rad : 1; /**< RAD interrupt-enable */ 2925232809Sjmallett uint64_t tim : 1; /**< TIM interrupt-enable */ 2926232809Sjmallett uint64_t reserved_25_27 : 3; 2927232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt-enable */ 2928232809Sjmallett uint64_t reserved_17_23 : 7; 2929232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt-enable */ 2930232809Sjmallett uint64_t reserved_8_15 : 8; 2931232809Sjmallett uint64_t pko : 1; /**< PKO interrupt-enable */ 2932232809Sjmallett uint64_t pip : 1; /**< PIP interrupt-enable */ 2933232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt-enable */ 2934232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt-enable */ 2935232809Sjmallett uint64_t reserved_1_3 : 3; 2936232809Sjmallett uint64_t iob : 1; /**< IOB interrupt-enable */ 2937232809Sjmallett#else 2938232809Sjmallett uint64_t iob : 1; 2939232809Sjmallett uint64_t reserved_1_3 : 3; 2940232809Sjmallett uint64_t fpa : 1; 2941232809Sjmallett uint64_t ipd : 1; 2942232809Sjmallett uint64_t pip : 1; 2943232809Sjmallett uint64_t pko : 1; 2944232809Sjmallett uint64_t reserved_8_15 : 8; 2945232809Sjmallett uint64_t sso : 1; 2946232809Sjmallett uint64_t reserved_17_23 : 7; 2947232809Sjmallett uint64_t zip : 1; 2948232809Sjmallett uint64_t reserved_25_27 : 3; 2949232809Sjmallett uint64_t tim : 1; 2950232809Sjmallett uint64_t rad : 1; 2951232809Sjmallett uint64_t key : 1; 2952232809Sjmallett uint64_t reserved_31_31 : 1; 2953232809Sjmallett uint64_t sli : 1; 2954232809Sjmallett uint64_t dpi : 1; 2955232809Sjmallett uint64_t reserved_34_35 : 2; 2956232809Sjmallett uint64_t dpi_dma : 1; 2957232809Sjmallett uint64_t reserved_37_39 : 3; 2958232809Sjmallett uint64_t dfa : 1; 2959232809Sjmallett uint64_t reserved_41_47 : 7; 2960232809Sjmallett uint64_t l2c : 1; 2961232809Sjmallett uint64_t reserved_49_51 : 3; 2962232809Sjmallett uint64_t trace : 4; 2963232809Sjmallett uint64_t reserved_56_63 : 8; 2964232809Sjmallett#endif 2965232809Sjmallett } s; 2966232809Sjmallett struct cvmx_ciu2_en_iox_int_rml_s cn68xx; 2967232809Sjmallett struct cvmx_ciu2_en_iox_int_rml_cn68xxp1 { 2968232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2969232809Sjmallett uint64_t reserved_56_63 : 8; 2970232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt-enable */ 2971232809Sjmallett uint64_t reserved_49_51 : 3; 2972232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt-enable */ 2973232809Sjmallett uint64_t reserved_41_47 : 7; 2974232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt-enable */ 2975232809Sjmallett uint64_t reserved_34_39 : 6; 2976232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt-enable */ 2977232809Sjmallett uint64_t sli : 1; /**< SLI interrupt-enable */ 2978232809Sjmallett uint64_t reserved_31_31 : 1; 2979232809Sjmallett uint64_t key : 1; /**< KEY interrupt-enable */ 2980232809Sjmallett uint64_t rad : 1; /**< RAD interrupt-enable */ 2981232809Sjmallett uint64_t tim : 1; /**< TIM interrupt-enable */ 2982232809Sjmallett uint64_t reserved_25_27 : 3; 2983232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt-enable */ 2984232809Sjmallett uint64_t reserved_17_23 : 7; 2985232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt-enable */ 2986232809Sjmallett uint64_t reserved_8_15 : 8; 2987232809Sjmallett uint64_t pko : 1; /**< PKO interrupt-enable */ 2988232809Sjmallett uint64_t pip : 1; /**< PIP interrupt-enable */ 2989232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt-enable */ 2990232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt-enable */ 2991232809Sjmallett uint64_t reserved_1_3 : 3; 2992232809Sjmallett uint64_t iob : 1; /**< IOB interrupt-enable */ 2993232809Sjmallett#else 2994232809Sjmallett uint64_t iob : 1; 2995232809Sjmallett uint64_t reserved_1_3 : 3; 2996232809Sjmallett uint64_t fpa : 1; 2997232809Sjmallett uint64_t ipd : 1; 2998232809Sjmallett uint64_t pip : 1; 2999232809Sjmallett uint64_t pko : 1; 3000232809Sjmallett uint64_t reserved_8_15 : 8; 3001232809Sjmallett uint64_t sso : 1; 3002232809Sjmallett uint64_t reserved_17_23 : 7; 3003232809Sjmallett uint64_t zip : 1; 3004232809Sjmallett uint64_t reserved_25_27 : 3; 3005232809Sjmallett uint64_t tim : 1; 3006232809Sjmallett uint64_t rad : 1; 3007232809Sjmallett uint64_t key : 1; 3008232809Sjmallett uint64_t reserved_31_31 : 1; 3009232809Sjmallett uint64_t sli : 1; 3010232809Sjmallett uint64_t dpi : 1; 3011232809Sjmallett uint64_t reserved_34_39 : 6; 3012232809Sjmallett uint64_t dfa : 1; 3013232809Sjmallett uint64_t reserved_41_47 : 7; 3014232809Sjmallett uint64_t l2c : 1; 3015232809Sjmallett uint64_t reserved_49_51 : 3; 3016232809Sjmallett uint64_t trace : 4; 3017232809Sjmallett uint64_t reserved_56_63 : 8; 3018232809Sjmallett#endif 3019232809Sjmallett } cn68xxp1; 3020232809Sjmallett}; 3021232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_rml cvmx_ciu2_en_iox_int_rml_t; 3022232809Sjmallett 3023232809Sjmallett/** 3024232809Sjmallett * cvmx_ciu2_en_io#_int_rml_w1c 3025232809Sjmallett */ 3026232809Sjmallettunion cvmx_ciu2_en_iox_int_rml_w1c { 3027232809Sjmallett uint64_t u64; 3028232809Sjmallett struct cvmx_ciu2_en_iox_int_rml_w1c_s { 3029232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3030232809Sjmallett uint64_t reserved_56_63 : 8; 3031232809Sjmallett uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */ 3032232809Sjmallett uint64_t reserved_49_51 : 3; 3033232809Sjmallett uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */ 3034232809Sjmallett uint64_t reserved_41_47 : 7; 3035232809Sjmallett uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */ 3036232809Sjmallett uint64_t reserved_37_39 : 3; 3037232809Sjmallett uint64_t dpi_dma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI_DMA] */ 3038232809Sjmallett uint64_t reserved_34_35 : 2; 3039232809Sjmallett uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */ 3040232809Sjmallett uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */ 3041232809Sjmallett uint64_t reserved_31_31 : 1; 3042232809Sjmallett uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */ 3043232809Sjmallett uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */ 3044232809Sjmallett uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */ 3045232809Sjmallett uint64_t reserved_25_27 : 3; 3046232809Sjmallett uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */ 3047232809Sjmallett uint64_t reserved_17_23 : 7; 3048232809Sjmallett uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */ 3049232809Sjmallett uint64_t reserved_8_15 : 8; 3050232809Sjmallett uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */ 3051232809Sjmallett uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */ 3052232809Sjmallett uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */ 3053232809Sjmallett uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */ 3054232809Sjmallett uint64_t reserved_1_3 : 3; 3055232809Sjmallett uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */ 3056232809Sjmallett#else 3057232809Sjmallett uint64_t iob : 1; 3058232809Sjmallett uint64_t reserved_1_3 : 3; 3059232809Sjmallett uint64_t fpa : 1; 3060232809Sjmallett uint64_t ipd : 1; 3061232809Sjmallett uint64_t pip : 1; 3062232809Sjmallett uint64_t pko : 1; 3063232809Sjmallett uint64_t reserved_8_15 : 8; 3064232809Sjmallett uint64_t sso : 1; 3065232809Sjmallett uint64_t reserved_17_23 : 7; 3066232809Sjmallett uint64_t zip : 1; 3067232809Sjmallett uint64_t reserved_25_27 : 3; 3068232809Sjmallett uint64_t tim : 1; 3069232809Sjmallett uint64_t rad : 1; 3070232809Sjmallett uint64_t key : 1; 3071232809Sjmallett uint64_t reserved_31_31 : 1; 3072232809Sjmallett uint64_t sli : 1; 3073232809Sjmallett uint64_t dpi : 1; 3074232809Sjmallett uint64_t reserved_34_35 : 2; 3075232809Sjmallett uint64_t dpi_dma : 1; 3076232809Sjmallett uint64_t reserved_37_39 : 3; 3077232809Sjmallett uint64_t dfa : 1; 3078232809Sjmallett uint64_t reserved_41_47 : 7; 3079232809Sjmallett uint64_t l2c : 1; 3080232809Sjmallett uint64_t reserved_49_51 : 3; 3081232809Sjmallett uint64_t trace : 4; 3082232809Sjmallett uint64_t reserved_56_63 : 8; 3083232809Sjmallett#endif 3084232809Sjmallett } s; 3085232809Sjmallett struct cvmx_ciu2_en_iox_int_rml_w1c_s cn68xx; 3086232809Sjmallett struct cvmx_ciu2_en_iox_int_rml_w1c_cn68xxp1 { 3087232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3088232809Sjmallett uint64_t reserved_56_63 : 8; 3089232809Sjmallett uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */ 3090232809Sjmallett uint64_t reserved_49_51 : 3; 3091232809Sjmallett uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */ 3092232809Sjmallett uint64_t reserved_41_47 : 7; 3093232809Sjmallett uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */ 3094232809Sjmallett uint64_t reserved_34_39 : 6; 3095232809Sjmallett uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */ 3096232809Sjmallett uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */ 3097232809Sjmallett uint64_t reserved_31_31 : 1; 3098232809Sjmallett uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */ 3099232809Sjmallett uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */ 3100232809Sjmallett uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */ 3101232809Sjmallett uint64_t reserved_25_27 : 3; 3102232809Sjmallett uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */ 3103232809Sjmallett uint64_t reserved_17_23 : 7; 3104232809Sjmallett uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */ 3105232809Sjmallett uint64_t reserved_8_15 : 8; 3106232809Sjmallett uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */ 3107232809Sjmallett uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */ 3108232809Sjmallett uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */ 3109232809Sjmallett uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */ 3110232809Sjmallett uint64_t reserved_1_3 : 3; 3111232809Sjmallett uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */ 3112232809Sjmallett#else 3113232809Sjmallett uint64_t iob : 1; 3114232809Sjmallett uint64_t reserved_1_3 : 3; 3115232809Sjmallett uint64_t fpa : 1; 3116232809Sjmallett uint64_t ipd : 1; 3117232809Sjmallett uint64_t pip : 1; 3118232809Sjmallett uint64_t pko : 1; 3119232809Sjmallett uint64_t reserved_8_15 : 8; 3120232809Sjmallett uint64_t sso : 1; 3121232809Sjmallett uint64_t reserved_17_23 : 7; 3122232809Sjmallett uint64_t zip : 1; 3123232809Sjmallett uint64_t reserved_25_27 : 3; 3124232809Sjmallett uint64_t tim : 1; 3125232809Sjmallett uint64_t rad : 1; 3126232809Sjmallett uint64_t key : 1; 3127232809Sjmallett uint64_t reserved_31_31 : 1; 3128232809Sjmallett uint64_t sli : 1; 3129232809Sjmallett uint64_t dpi : 1; 3130232809Sjmallett uint64_t reserved_34_39 : 6; 3131232809Sjmallett uint64_t dfa : 1; 3132232809Sjmallett uint64_t reserved_41_47 : 7; 3133232809Sjmallett uint64_t l2c : 1; 3134232809Sjmallett uint64_t reserved_49_51 : 3; 3135232809Sjmallett uint64_t trace : 4; 3136232809Sjmallett uint64_t reserved_56_63 : 8; 3137232809Sjmallett#endif 3138232809Sjmallett } cn68xxp1; 3139232809Sjmallett}; 3140232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_rml_w1c cvmx_ciu2_en_iox_int_rml_w1c_t; 3141232809Sjmallett 3142232809Sjmallett/** 3143232809Sjmallett * cvmx_ciu2_en_io#_int_rml_w1s 3144232809Sjmallett */ 3145232809Sjmallettunion cvmx_ciu2_en_iox_int_rml_w1s { 3146232809Sjmallett uint64_t u64; 3147232809Sjmallett struct cvmx_ciu2_en_iox_int_rml_w1s_s { 3148232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3149232809Sjmallett uint64_t reserved_56_63 : 8; 3150232809Sjmallett uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */ 3151232809Sjmallett uint64_t reserved_49_51 : 3; 3152232809Sjmallett uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */ 3153232809Sjmallett uint64_t reserved_41_47 : 7; 3154232809Sjmallett uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */ 3155232809Sjmallett uint64_t reserved_37_39 : 3; 3156232809Sjmallett uint64_t dpi_dma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI_DMA] */ 3157232809Sjmallett uint64_t reserved_34_35 : 2; 3158232809Sjmallett uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */ 3159232809Sjmallett uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */ 3160232809Sjmallett uint64_t reserved_31_31 : 1; 3161232809Sjmallett uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */ 3162232809Sjmallett uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */ 3163232809Sjmallett uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */ 3164232809Sjmallett uint64_t reserved_25_27 : 3; 3165232809Sjmallett uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */ 3166232809Sjmallett uint64_t reserved_17_23 : 7; 3167232809Sjmallett uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */ 3168232809Sjmallett uint64_t reserved_8_15 : 8; 3169232809Sjmallett uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */ 3170232809Sjmallett uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */ 3171232809Sjmallett uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */ 3172232809Sjmallett uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */ 3173232809Sjmallett uint64_t reserved_1_3 : 3; 3174232809Sjmallett uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */ 3175232809Sjmallett#else 3176232809Sjmallett uint64_t iob : 1; 3177232809Sjmallett uint64_t reserved_1_3 : 3; 3178232809Sjmallett uint64_t fpa : 1; 3179232809Sjmallett uint64_t ipd : 1; 3180232809Sjmallett uint64_t pip : 1; 3181232809Sjmallett uint64_t pko : 1; 3182232809Sjmallett uint64_t reserved_8_15 : 8; 3183232809Sjmallett uint64_t sso : 1; 3184232809Sjmallett uint64_t reserved_17_23 : 7; 3185232809Sjmallett uint64_t zip : 1; 3186232809Sjmallett uint64_t reserved_25_27 : 3; 3187232809Sjmallett uint64_t tim : 1; 3188232809Sjmallett uint64_t rad : 1; 3189232809Sjmallett uint64_t key : 1; 3190232809Sjmallett uint64_t reserved_31_31 : 1; 3191232809Sjmallett uint64_t sli : 1; 3192232809Sjmallett uint64_t dpi : 1; 3193232809Sjmallett uint64_t reserved_34_35 : 2; 3194232809Sjmallett uint64_t dpi_dma : 1; 3195232809Sjmallett uint64_t reserved_37_39 : 3; 3196232809Sjmallett uint64_t dfa : 1; 3197232809Sjmallett uint64_t reserved_41_47 : 7; 3198232809Sjmallett uint64_t l2c : 1; 3199232809Sjmallett uint64_t reserved_49_51 : 3; 3200232809Sjmallett uint64_t trace : 4; 3201232809Sjmallett uint64_t reserved_56_63 : 8; 3202232809Sjmallett#endif 3203232809Sjmallett } s; 3204232809Sjmallett struct cvmx_ciu2_en_iox_int_rml_w1s_s cn68xx; 3205232809Sjmallett struct cvmx_ciu2_en_iox_int_rml_w1s_cn68xxp1 { 3206232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3207232809Sjmallett uint64_t reserved_56_63 : 8; 3208232809Sjmallett uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */ 3209232809Sjmallett uint64_t reserved_49_51 : 3; 3210232809Sjmallett uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */ 3211232809Sjmallett uint64_t reserved_41_47 : 7; 3212232809Sjmallett uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */ 3213232809Sjmallett uint64_t reserved_34_39 : 6; 3214232809Sjmallett uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */ 3215232809Sjmallett uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */ 3216232809Sjmallett uint64_t reserved_31_31 : 1; 3217232809Sjmallett uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */ 3218232809Sjmallett uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */ 3219232809Sjmallett uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */ 3220232809Sjmallett uint64_t reserved_25_27 : 3; 3221232809Sjmallett uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */ 3222232809Sjmallett uint64_t reserved_17_23 : 7; 3223232809Sjmallett uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */ 3224232809Sjmallett uint64_t reserved_8_15 : 8; 3225232809Sjmallett uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */ 3226232809Sjmallett uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */ 3227232809Sjmallett uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */ 3228232809Sjmallett uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */ 3229232809Sjmallett uint64_t reserved_1_3 : 3; 3230232809Sjmallett uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */ 3231232809Sjmallett#else 3232232809Sjmallett uint64_t iob : 1; 3233232809Sjmallett uint64_t reserved_1_3 : 3; 3234232809Sjmallett uint64_t fpa : 1; 3235232809Sjmallett uint64_t ipd : 1; 3236232809Sjmallett uint64_t pip : 1; 3237232809Sjmallett uint64_t pko : 1; 3238232809Sjmallett uint64_t reserved_8_15 : 8; 3239232809Sjmallett uint64_t sso : 1; 3240232809Sjmallett uint64_t reserved_17_23 : 7; 3241232809Sjmallett uint64_t zip : 1; 3242232809Sjmallett uint64_t reserved_25_27 : 3; 3243232809Sjmallett uint64_t tim : 1; 3244232809Sjmallett uint64_t rad : 1; 3245232809Sjmallett uint64_t key : 1; 3246232809Sjmallett uint64_t reserved_31_31 : 1; 3247232809Sjmallett uint64_t sli : 1; 3248232809Sjmallett uint64_t dpi : 1; 3249232809Sjmallett uint64_t reserved_34_39 : 6; 3250232809Sjmallett uint64_t dfa : 1; 3251232809Sjmallett uint64_t reserved_41_47 : 7; 3252232809Sjmallett uint64_t l2c : 1; 3253232809Sjmallett uint64_t reserved_49_51 : 3; 3254232809Sjmallett uint64_t trace : 4; 3255232809Sjmallett uint64_t reserved_56_63 : 8; 3256232809Sjmallett#endif 3257232809Sjmallett } cn68xxp1; 3258232809Sjmallett}; 3259232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_rml_w1s cvmx_ciu2_en_iox_int_rml_w1s_t; 3260232809Sjmallett 3261232809Sjmallett/** 3262232809Sjmallett * cvmx_ciu2_en_io#_int_wdog 3263232809Sjmallett */ 3264232809Sjmallettunion cvmx_ciu2_en_iox_int_wdog { 3265232809Sjmallett uint64_t u64; 3266232809Sjmallett struct cvmx_ciu2_en_iox_int_wdog_s { 3267232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3268232809Sjmallett uint64_t reserved_32_63 : 32; 3269232809Sjmallett uint64_t wdog : 32; /**< 32 watchdog interrupt-enable */ 3270232809Sjmallett#else 3271232809Sjmallett uint64_t wdog : 32; 3272232809Sjmallett uint64_t reserved_32_63 : 32; 3273232809Sjmallett#endif 3274232809Sjmallett } s; 3275232809Sjmallett struct cvmx_ciu2_en_iox_int_wdog_s cn68xx; 3276232809Sjmallett struct cvmx_ciu2_en_iox_int_wdog_s cn68xxp1; 3277232809Sjmallett}; 3278232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_wdog cvmx_ciu2_en_iox_int_wdog_t; 3279232809Sjmallett 3280232809Sjmallett/** 3281232809Sjmallett * cvmx_ciu2_en_io#_int_wdog_w1c 3282232809Sjmallett */ 3283232809Sjmallettunion cvmx_ciu2_en_iox_int_wdog_w1c { 3284232809Sjmallett uint64_t u64; 3285232809Sjmallett struct cvmx_ciu2_en_iox_int_wdog_w1c_s { 3286232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3287232809Sjmallett uint64_t reserved_32_63 : 32; 3288232809Sjmallett uint64_t wdog : 32; /**< write 1 to clear CIU2_EN_xx_yy_WDOG */ 3289232809Sjmallett#else 3290232809Sjmallett uint64_t wdog : 32; 3291232809Sjmallett uint64_t reserved_32_63 : 32; 3292232809Sjmallett#endif 3293232809Sjmallett } s; 3294232809Sjmallett struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xx; 3295232809Sjmallett struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xxp1; 3296232809Sjmallett}; 3297232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_wdog_w1c cvmx_ciu2_en_iox_int_wdog_w1c_t; 3298232809Sjmallett 3299232809Sjmallett/** 3300232809Sjmallett * cvmx_ciu2_en_io#_int_wdog_w1s 3301232809Sjmallett */ 3302232809Sjmallettunion cvmx_ciu2_en_iox_int_wdog_w1s { 3303232809Sjmallett uint64_t u64; 3304232809Sjmallett struct cvmx_ciu2_en_iox_int_wdog_w1s_s { 3305232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3306232809Sjmallett uint64_t reserved_32_63 : 32; 3307232809Sjmallett uint64_t wdog : 32; /**< Write 1 to enable CIU2_EN_xx_yy_WDOG[WDOG] */ 3308232809Sjmallett#else 3309232809Sjmallett uint64_t wdog : 32; 3310232809Sjmallett uint64_t reserved_32_63 : 32; 3311232809Sjmallett#endif 3312232809Sjmallett } s; 3313232809Sjmallett struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xx; 3314232809Sjmallett struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xxp1; 3315232809Sjmallett}; 3316232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_wdog_w1s cvmx_ciu2_en_iox_int_wdog_w1s_t; 3317232809Sjmallett 3318232809Sjmallett/** 3319232809Sjmallett * cvmx_ciu2_en_io#_int_wrkq 3320232809Sjmallett */ 3321232809Sjmallettunion cvmx_ciu2_en_iox_int_wrkq { 3322232809Sjmallett uint64_t u64; 3323232809Sjmallett struct cvmx_ciu2_en_iox_int_wrkq_s { 3324232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3325232809Sjmallett uint64_t workq : 64; /**< 64 work queue interrupt-enable */ 3326232809Sjmallett#else 3327232809Sjmallett uint64_t workq : 64; 3328232809Sjmallett#endif 3329232809Sjmallett } s; 3330232809Sjmallett struct cvmx_ciu2_en_iox_int_wrkq_s cn68xx; 3331232809Sjmallett struct cvmx_ciu2_en_iox_int_wrkq_s cn68xxp1; 3332232809Sjmallett}; 3333232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_wrkq cvmx_ciu2_en_iox_int_wrkq_t; 3334232809Sjmallett 3335232809Sjmallett/** 3336232809Sjmallett * cvmx_ciu2_en_io#_int_wrkq_w1c 3337232809Sjmallett */ 3338232809Sjmallettunion cvmx_ciu2_en_iox_int_wrkq_w1c { 3339232809Sjmallett uint64_t u64; 3340232809Sjmallett struct cvmx_ciu2_en_iox_int_wrkq_w1c_s { 3341232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3342232809Sjmallett uint64_t workq : 64; /**< Write 1 to clear CIU2_EN_xx_yy_WRKQ[WORKQ] 3343232809Sjmallett For W1C bits, write 1 to clear the corresponding 3344232809Sjmallett CIU2_EN_xx_yy_WRKQ,write 0 to retain previous value */ 3345232809Sjmallett#else 3346232809Sjmallett uint64_t workq : 64; 3347232809Sjmallett#endif 3348232809Sjmallett } s; 3349232809Sjmallett struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xx; 3350232809Sjmallett struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xxp1; 3351232809Sjmallett}; 3352232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_wrkq_w1c cvmx_ciu2_en_iox_int_wrkq_w1c_t; 3353232809Sjmallett 3354232809Sjmallett/** 3355232809Sjmallett * cvmx_ciu2_en_io#_int_wrkq_w1s 3356232809Sjmallett */ 3357232809Sjmallettunion cvmx_ciu2_en_iox_int_wrkq_w1s { 3358232809Sjmallett uint64_t u64; 3359232809Sjmallett struct cvmx_ciu2_en_iox_int_wrkq_w1s_s { 3360232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3361232809Sjmallett uint64_t workq : 64; /**< Write 1 to enable CIU2_EN_xx_yy_WRKQ[WORKQ] 3362232809Sjmallett 1 bit/group. For all W1S bits, write 1 to enable 3363232809Sjmallett corresponding CIU2_EN_xx_yy_WRKQ[WORKQ] bit, 3364232809Sjmallett writing 0 to retain previous value. */ 3365232809Sjmallett#else 3366232809Sjmallett uint64_t workq : 64; 3367232809Sjmallett#endif 3368232809Sjmallett } s; 3369232809Sjmallett struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xx; 3370232809Sjmallett struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xxp1; 3371232809Sjmallett}; 3372232809Sjmalletttypedef union cvmx_ciu2_en_iox_int_wrkq_w1s cvmx_ciu2_en_iox_int_wrkq_w1s_t; 3373232809Sjmallett 3374232809Sjmallett/** 3375232809Sjmallett * cvmx_ciu2_en_pp#_ip2_gpio 3376232809Sjmallett */ 3377232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_gpio { 3378232809Sjmallett uint64_t u64; 3379232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_gpio_s { 3380232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3381232809Sjmallett uint64_t reserved_16_63 : 48; 3382232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupt-enable */ 3383232809Sjmallett#else 3384232809Sjmallett uint64_t gpio : 16; 3385232809Sjmallett uint64_t reserved_16_63 : 48; 3386232809Sjmallett#endif 3387232809Sjmallett } s; 3388232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xx; 3389232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xxp1; 3390232809Sjmallett}; 3391232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_gpio cvmx_ciu2_en_ppx_ip2_gpio_t; 3392232809Sjmallett 3393232809Sjmallett/** 3394232809Sjmallett * cvmx_ciu2_en_pp#_ip2_gpio_w1c 3395232809Sjmallett */ 3396232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_gpio_w1c { 3397232809Sjmallett uint64_t u64; 3398232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s { 3399232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3400232809Sjmallett uint64_t reserved_16_63 : 48; 3401232809Sjmallett uint64_t gpio : 16; /**< Write 1 to clear CIU2_EN_xx_yy_GPIO[GPIO] */ 3402232809Sjmallett#else 3403232809Sjmallett uint64_t gpio : 16; 3404232809Sjmallett uint64_t reserved_16_63 : 48; 3405232809Sjmallett#endif 3406232809Sjmallett } s; 3407232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xx; 3408232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xxp1; 3409232809Sjmallett}; 3410232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_gpio_w1c cvmx_ciu2_en_ppx_ip2_gpio_w1c_t; 3411232809Sjmallett 3412232809Sjmallett/** 3413232809Sjmallett * cvmx_ciu2_en_pp#_ip2_gpio_w1s 3414232809Sjmallett */ 3415232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_gpio_w1s { 3416232809Sjmallett uint64_t u64; 3417232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s { 3418232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3419232809Sjmallett uint64_t reserved_16_63 : 48; 3420232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupt enable,write 1 to enable CIU2_EN */ 3421232809Sjmallett#else 3422232809Sjmallett uint64_t gpio : 16; 3423232809Sjmallett uint64_t reserved_16_63 : 48; 3424232809Sjmallett#endif 3425232809Sjmallett } s; 3426232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xx; 3427232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xxp1; 3428232809Sjmallett}; 3429232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_gpio_w1s cvmx_ciu2_en_ppx_ip2_gpio_w1s_t; 3430232809Sjmallett 3431232809Sjmallett/** 3432232809Sjmallett * cvmx_ciu2_en_pp#_ip2_io 3433232809Sjmallett */ 3434232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_io { 3435232809Sjmallett uint64_t u64; 3436232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_io_s { 3437232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3438232809Sjmallett uint64_t reserved_34_63 : 30; 3439232809Sjmallett uint64_t pem : 2; /**< PEMx interrupt-enable */ 3440232809Sjmallett uint64_t reserved_18_31 : 14; 3441232809Sjmallett uint64_t pci_inta : 2; /**< PCI_INTA interrupt-enable */ 3442232809Sjmallett uint64_t reserved_13_15 : 3; 3443232809Sjmallett uint64_t msired : 1; /**< MSI summary bit interrupt-enable 3444232809Sjmallett This bit may not be functional in pass 1. */ 3445232809Sjmallett uint64_t pci_msi : 4; /**< PCIe/sRIO MSI interrupt-enable */ 3446232809Sjmallett uint64_t reserved_4_7 : 4; 3447232809Sjmallett uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt-enable */ 3448232809Sjmallett#else 3449232809Sjmallett uint64_t pci_intr : 4; 3450232809Sjmallett uint64_t reserved_4_7 : 4; 3451232809Sjmallett uint64_t pci_msi : 4; 3452232809Sjmallett uint64_t msired : 1; 3453232809Sjmallett uint64_t reserved_13_15 : 3; 3454232809Sjmallett uint64_t pci_inta : 2; 3455232809Sjmallett uint64_t reserved_18_31 : 14; 3456232809Sjmallett uint64_t pem : 2; 3457232809Sjmallett uint64_t reserved_34_63 : 30; 3458232809Sjmallett#endif 3459232809Sjmallett } s; 3460232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_io_s cn68xx; 3461232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_io_s cn68xxp1; 3462232809Sjmallett}; 3463232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_io cvmx_ciu2_en_ppx_ip2_io_t; 3464232809Sjmallett 3465232809Sjmallett/** 3466232809Sjmallett * cvmx_ciu2_en_pp#_ip2_io_w1c 3467232809Sjmallett */ 3468232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_io_w1c { 3469232809Sjmallett uint64_t u64; 3470232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_io_w1c_s { 3471232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3472232809Sjmallett uint64_t reserved_34_63 : 30; 3473232809Sjmallett uint64_t pem : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PEM] */ 3474232809Sjmallett uint64_t reserved_18_31 : 14; 3475232809Sjmallett uint64_t pci_inta : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTA] */ 3476232809Sjmallett uint64_t reserved_13_15 : 3; 3477232809Sjmallett uint64_t msired : 1; /**< Write 1 to clear CIU2_EN_xx_yy_IO[MSIRED] 3478232809Sjmallett This bit may not be functional in pass 1. */ 3479232809Sjmallett uint64_t pci_msi : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_MSI] */ 3480232809Sjmallett uint64_t reserved_4_7 : 4; 3481232809Sjmallett uint64_t pci_intr : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTR] */ 3482232809Sjmallett#else 3483232809Sjmallett uint64_t pci_intr : 4; 3484232809Sjmallett uint64_t reserved_4_7 : 4; 3485232809Sjmallett uint64_t pci_msi : 4; 3486232809Sjmallett uint64_t msired : 1; 3487232809Sjmallett uint64_t reserved_13_15 : 3; 3488232809Sjmallett uint64_t pci_inta : 2; 3489232809Sjmallett uint64_t reserved_18_31 : 14; 3490232809Sjmallett uint64_t pem : 2; 3491232809Sjmallett uint64_t reserved_34_63 : 30; 3492232809Sjmallett#endif 3493232809Sjmallett } s; 3494232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xx; 3495232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xxp1; 3496232809Sjmallett}; 3497232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_io_w1c cvmx_ciu2_en_ppx_ip2_io_w1c_t; 3498232809Sjmallett 3499232809Sjmallett/** 3500232809Sjmallett * cvmx_ciu2_en_pp#_ip2_io_w1s 3501232809Sjmallett */ 3502232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_io_w1s { 3503232809Sjmallett uint64_t u64; 3504232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_io_w1s_s { 3505232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3506232809Sjmallett uint64_t reserved_34_63 : 30; 3507232809Sjmallett uint64_t pem : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PEM] */ 3508232809Sjmallett uint64_t reserved_18_31 : 14; 3509232809Sjmallett uint64_t pci_inta : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTA] */ 3510232809Sjmallett uint64_t reserved_13_15 : 3; 3511232809Sjmallett uint64_t msired : 1; /**< Write 1 to enable CIU2_EN_xx_yy_IO[MSIRED] 3512232809Sjmallett This bit may not be functional in pass 1. */ 3513232809Sjmallett uint64_t pci_msi : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_MSI] */ 3514232809Sjmallett uint64_t reserved_4_7 : 4; 3515232809Sjmallett uint64_t pci_intr : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTR] */ 3516232809Sjmallett#else 3517232809Sjmallett uint64_t pci_intr : 4; 3518232809Sjmallett uint64_t reserved_4_7 : 4; 3519232809Sjmallett uint64_t pci_msi : 4; 3520232809Sjmallett uint64_t msired : 1; 3521232809Sjmallett uint64_t reserved_13_15 : 3; 3522232809Sjmallett uint64_t pci_inta : 2; 3523232809Sjmallett uint64_t reserved_18_31 : 14; 3524232809Sjmallett uint64_t pem : 2; 3525232809Sjmallett uint64_t reserved_34_63 : 30; 3526232809Sjmallett#endif 3527232809Sjmallett } s; 3528232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xx; 3529232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xxp1; 3530232809Sjmallett}; 3531232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_io_w1s cvmx_ciu2_en_ppx_ip2_io_w1s_t; 3532232809Sjmallett 3533232809Sjmallett/** 3534232809Sjmallett * cvmx_ciu2_en_pp#_ip2_mbox 3535232809Sjmallett */ 3536232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_mbox { 3537232809Sjmallett uint64_t u64; 3538232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mbox_s { 3539232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3540232809Sjmallett uint64_t reserved_4_63 : 60; 3541232809Sjmallett uint64_t mbox : 4; /**< Mailbox interrupt-enable, use with CIU2_MBOX 3542232809Sjmallett to generate CIU2_SRC_xx_yy_MBOX */ 3543232809Sjmallett#else 3544232809Sjmallett uint64_t mbox : 4; 3545232809Sjmallett uint64_t reserved_4_63 : 60; 3546232809Sjmallett#endif 3547232809Sjmallett } s; 3548232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xx; 3549232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xxp1; 3550232809Sjmallett}; 3551232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_mbox cvmx_ciu2_en_ppx_ip2_mbox_t; 3552232809Sjmallett 3553232809Sjmallett/** 3554232809Sjmallett * cvmx_ciu2_en_pp#_ip2_mbox_w1c 3555232809Sjmallett */ 3556232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_mbox_w1c { 3557232809Sjmallett uint64_t u64; 3558232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s { 3559232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3560232809Sjmallett uint64_t reserved_4_63 : 60; 3561232809Sjmallett uint64_t mbox : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MBOX[MBOX] */ 3562232809Sjmallett#else 3563232809Sjmallett uint64_t mbox : 4; 3564232809Sjmallett uint64_t reserved_4_63 : 60; 3565232809Sjmallett#endif 3566232809Sjmallett } s; 3567232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xx; 3568232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xxp1; 3569232809Sjmallett}; 3570232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_mbox_w1c cvmx_ciu2_en_ppx_ip2_mbox_w1c_t; 3571232809Sjmallett 3572232809Sjmallett/** 3573232809Sjmallett * cvmx_ciu2_en_pp#_ip2_mbox_w1s 3574232809Sjmallett */ 3575232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_mbox_w1s { 3576232809Sjmallett uint64_t u64; 3577232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s { 3578232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3579232809Sjmallett uint64_t reserved_4_63 : 60; 3580232809Sjmallett uint64_t mbox : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MBOX[MBOX] */ 3581232809Sjmallett#else 3582232809Sjmallett uint64_t mbox : 4; 3583232809Sjmallett uint64_t reserved_4_63 : 60; 3584232809Sjmallett#endif 3585232809Sjmallett } s; 3586232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xx; 3587232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xxp1; 3588232809Sjmallett}; 3589232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_mbox_w1s cvmx_ciu2_en_ppx_ip2_mbox_w1s_t; 3590232809Sjmallett 3591232809Sjmallett/** 3592232809Sjmallett * cvmx_ciu2_en_pp#_ip2_mem 3593232809Sjmallett */ 3594232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_mem { 3595232809Sjmallett uint64_t u64; 3596232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mem_s { 3597232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3598232809Sjmallett uint64_t reserved_4_63 : 60; 3599232809Sjmallett uint64_t lmc : 4; /**< LMC* interrupt-enable */ 3600232809Sjmallett#else 3601232809Sjmallett uint64_t lmc : 4; 3602232809Sjmallett uint64_t reserved_4_63 : 60; 3603232809Sjmallett#endif 3604232809Sjmallett } s; 3605232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xx; 3606232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xxp1; 3607232809Sjmallett}; 3608232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_mem cvmx_ciu2_en_ppx_ip2_mem_t; 3609232809Sjmallett 3610232809Sjmallett/** 3611232809Sjmallett * cvmx_ciu2_en_pp#_ip2_mem_w1c 3612232809Sjmallett */ 3613232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_mem_w1c { 3614232809Sjmallett uint64_t u64; 3615232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s { 3616232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3617232809Sjmallett uint64_t reserved_4_63 : 60; 3618232809Sjmallett uint64_t lmc : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MEM[LMC] */ 3619232809Sjmallett#else 3620232809Sjmallett uint64_t lmc : 4; 3621232809Sjmallett uint64_t reserved_4_63 : 60; 3622232809Sjmallett#endif 3623232809Sjmallett } s; 3624232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xx; 3625232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xxp1; 3626232809Sjmallett}; 3627232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_mem_w1c cvmx_ciu2_en_ppx_ip2_mem_w1c_t; 3628232809Sjmallett 3629232809Sjmallett/** 3630232809Sjmallett * cvmx_ciu2_en_pp#_ip2_mem_w1s 3631232809Sjmallett */ 3632232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_mem_w1s { 3633232809Sjmallett uint64_t u64; 3634232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s { 3635232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3636232809Sjmallett uint64_t reserved_4_63 : 60; 3637232809Sjmallett uint64_t lmc : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MEM[LMC] */ 3638232809Sjmallett#else 3639232809Sjmallett uint64_t lmc : 4; 3640232809Sjmallett uint64_t reserved_4_63 : 60; 3641232809Sjmallett#endif 3642232809Sjmallett } s; 3643232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xx; 3644232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xxp1; 3645232809Sjmallett}; 3646232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_mem_w1s cvmx_ciu2_en_ppx_ip2_mem_w1s_t; 3647232809Sjmallett 3648232809Sjmallett/** 3649232809Sjmallett * cvmx_ciu2_en_pp#_ip2_mio 3650232809Sjmallett */ 3651232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_mio { 3652232809Sjmallett uint64_t u64; 3653232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mio_s { 3654232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3655232809Sjmallett uint64_t rst : 1; /**< MIO RST interrupt-enable */ 3656232809Sjmallett uint64_t reserved_49_62 : 14; 3657232809Sjmallett uint64_t ptp : 1; /**< PTP interrupt-enable */ 3658232809Sjmallett uint64_t reserved_45_47 : 3; 3659232809Sjmallett uint64_t usb_hci : 1; /**< USB HCI Interrupt-enable */ 3660232809Sjmallett uint64_t reserved_41_43 : 3; 3661232809Sjmallett uint64_t usb_uctl : 1; /**< USB UCTL* interrupt-enable */ 3662232809Sjmallett uint64_t reserved_38_39 : 2; 3663232809Sjmallett uint64_t uart : 2; /**< Two UART interrupt-enable */ 3664232809Sjmallett uint64_t reserved_34_35 : 2; 3665232809Sjmallett uint64_t twsi : 2; /**< TWSI x interrupt-enable */ 3666232809Sjmallett uint64_t reserved_19_31 : 13; 3667232809Sjmallett uint64_t bootdma : 1; /**< Boot bus DMA engines interrupt-enable */ 3668232809Sjmallett uint64_t mio : 1; /**< MIO boot interrupt-enable */ 3669232809Sjmallett uint64_t nand : 1; /**< NAND Flash Controller interrupt-enable */ 3670232809Sjmallett uint64_t reserved_12_15 : 4; 3671232809Sjmallett uint64_t timer : 4; /**< General timer interrupt-enable */ 3672232809Sjmallett uint64_t reserved_3_7 : 5; 3673232809Sjmallett uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt-enable */ 3674232809Sjmallett uint64_t ssoiq : 1; /**< SSO IQ interrupt-enable */ 3675232809Sjmallett uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt-enable */ 3676232809Sjmallett#else 3677232809Sjmallett uint64_t ipdppthr : 1; 3678232809Sjmallett uint64_t ssoiq : 1; 3679232809Sjmallett uint64_t ipd_drp : 1; 3680232809Sjmallett uint64_t reserved_3_7 : 5; 3681232809Sjmallett uint64_t timer : 4; 3682232809Sjmallett uint64_t reserved_12_15 : 4; 3683232809Sjmallett uint64_t nand : 1; 3684232809Sjmallett uint64_t mio : 1; 3685232809Sjmallett uint64_t bootdma : 1; 3686232809Sjmallett uint64_t reserved_19_31 : 13; 3687232809Sjmallett uint64_t twsi : 2; 3688232809Sjmallett uint64_t reserved_34_35 : 2; 3689232809Sjmallett uint64_t uart : 2; 3690232809Sjmallett uint64_t reserved_38_39 : 2; 3691232809Sjmallett uint64_t usb_uctl : 1; 3692232809Sjmallett uint64_t reserved_41_43 : 3; 3693232809Sjmallett uint64_t usb_hci : 1; 3694232809Sjmallett uint64_t reserved_45_47 : 3; 3695232809Sjmallett uint64_t ptp : 1; 3696232809Sjmallett uint64_t reserved_49_62 : 14; 3697232809Sjmallett uint64_t rst : 1; 3698232809Sjmallett#endif 3699232809Sjmallett } s; 3700232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xx; 3701232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xxp1; 3702232809Sjmallett}; 3703232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_mio cvmx_ciu2_en_ppx_ip2_mio_t; 3704232809Sjmallett 3705232809Sjmallett/** 3706232809Sjmallett * cvmx_ciu2_en_pp#_ip2_mio_w1c 3707232809Sjmallett */ 3708232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_mio_w1c { 3709232809Sjmallett uint64_t u64; 3710232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s { 3711232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3712232809Sjmallett uint64_t rst : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[RST] */ 3713232809Sjmallett uint64_t reserved_49_62 : 14; 3714232809Sjmallett uint64_t ptp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[PTP] */ 3715232809Sjmallett uint64_t reserved_45_47 : 3; 3716232809Sjmallett uint64_t usb_hci : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_HCI] */ 3717232809Sjmallett uint64_t reserved_41_43 : 3; 3718232809Sjmallett uint64_t usb_uctl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_UCTL] */ 3719232809Sjmallett uint64_t reserved_38_39 : 2; 3720232809Sjmallett uint64_t uart : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[UART] */ 3721232809Sjmallett uint64_t reserved_34_35 : 2; 3722232809Sjmallett uint64_t twsi : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TWSI] */ 3723232809Sjmallett uint64_t reserved_19_31 : 13; 3724232809Sjmallett uint64_t bootdma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[BOOTDMA] */ 3725232809Sjmallett uint64_t mio : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[MIO] */ 3726232809Sjmallett uint64_t nand : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[NAND] */ 3727232809Sjmallett uint64_t reserved_12_15 : 4; 3728232809Sjmallett uint64_t timer : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TIMER] */ 3729232809Sjmallett uint64_t reserved_3_7 : 5; 3730232809Sjmallett uint64_t ipd_drp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPD_DRP] */ 3731232809Sjmallett uint64_t ssoiq : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[SSQIQ] */ 3732232809Sjmallett uint64_t ipdppthr : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPDPPTHR] */ 3733232809Sjmallett#else 3734232809Sjmallett uint64_t ipdppthr : 1; 3735232809Sjmallett uint64_t ssoiq : 1; 3736232809Sjmallett uint64_t ipd_drp : 1; 3737232809Sjmallett uint64_t reserved_3_7 : 5; 3738232809Sjmallett uint64_t timer : 4; 3739232809Sjmallett uint64_t reserved_12_15 : 4; 3740232809Sjmallett uint64_t nand : 1; 3741232809Sjmallett uint64_t mio : 1; 3742232809Sjmallett uint64_t bootdma : 1; 3743232809Sjmallett uint64_t reserved_19_31 : 13; 3744232809Sjmallett uint64_t twsi : 2; 3745232809Sjmallett uint64_t reserved_34_35 : 2; 3746232809Sjmallett uint64_t uart : 2; 3747232809Sjmallett uint64_t reserved_38_39 : 2; 3748232809Sjmallett uint64_t usb_uctl : 1; 3749232809Sjmallett uint64_t reserved_41_43 : 3; 3750232809Sjmallett uint64_t usb_hci : 1; 3751232809Sjmallett uint64_t reserved_45_47 : 3; 3752232809Sjmallett uint64_t ptp : 1; 3753232809Sjmallett uint64_t reserved_49_62 : 14; 3754232809Sjmallett uint64_t rst : 1; 3755232809Sjmallett#endif 3756232809Sjmallett } s; 3757232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xx; 3758232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xxp1; 3759232809Sjmallett}; 3760232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_mio_w1c cvmx_ciu2_en_ppx_ip2_mio_w1c_t; 3761232809Sjmallett 3762232809Sjmallett/** 3763232809Sjmallett * cvmx_ciu2_en_pp#_ip2_mio_w1s 3764232809Sjmallett */ 3765232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_mio_w1s { 3766232809Sjmallett uint64_t u64; 3767232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s { 3768232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3769232809Sjmallett uint64_t rst : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[RST] */ 3770232809Sjmallett uint64_t reserved_49_62 : 14; 3771232809Sjmallett uint64_t ptp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[PTP] */ 3772232809Sjmallett uint64_t reserved_45_47 : 3; 3773232809Sjmallett uint64_t usb_hci : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_HCI] */ 3774232809Sjmallett uint64_t reserved_41_43 : 3; 3775232809Sjmallett uint64_t usb_uctl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_UCTL] */ 3776232809Sjmallett uint64_t reserved_38_39 : 2; 3777232809Sjmallett uint64_t uart : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[UART] */ 3778232809Sjmallett uint64_t reserved_34_35 : 2; 3779232809Sjmallett uint64_t twsi : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TWSI] */ 3780232809Sjmallett uint64_t reserved_19_31 : 13; 3781232809Sjmallett uint64_t bootdma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[BOOTDMA] */ 3782232809Sjmallett uint64_t mio : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[MIO] */ 3783232809Sjmallett uint64_t nand : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[NAND] */ 3784232809Sjmallett uint64_t reserved_12_15 : 4; 3785232809Sjmallett uint64_t timer : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TIMER] */ 3786232809Sjmallett uint64_t reserved_3_7 : 5; 3787232809Sjmallett uint64_t ipd_drp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPD_DRP] */ 3788232809Sjmallett uint64_t ssoiq : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[SSQIQ] */ 3789232809Sjmallett uint64_t ipdppthr : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPDPPTHR] */ 3790232809Sjmallett#else 3791232809Sjmallett uint64_t ipdppthr : 1; 3792232809Sjmallett uint64_t ssoiq : 1; 3793232809Sjmallett uint64_t ipd_drp : 1; 3794232809Sjmallett uint64_t reserved_3_7 : 5; 3795232809Sjmallett uint64_t timer : 4; 3796232809Sjmallett uint64_t reserved_12_15 : 4; 3797232809Sjmallett uint64_t nand : 1; 3798232809Sjmallett uint64_t mio : 1; 3799232809Sjmallett uint64_t bootdma : 1; 3800232809Sjmallett uint64_t reserved_19_31 : 13; 3801232809Sjmallett uint64_t twsi : 2; 3802232809Sjmallett uint64_t reserved_34_35 : 2; 3803232809Sjmallett uint64_t uart : 2; 3804232809Sjmallett uint64_t reserved_38_39 : 2; 3805232809Sjmallett uint64_t usb_uctl : 1; 3806232809Sjmallett uint64_t reserved_41_43 : 3; 3807232809Sjmallett uint64_t usb_hci : 1; 3808232809Sjmallett uint64_t reserved_45_47 : 3; 3809232809Sjmallett uint64_t ptp : 1; 3810232809Sjmallett uint64_t reserved_49_62 : 14; 3811232809Sjmallett uint64_t rst : 1; 3812232809Sjmallett#endif 3813232809Sjmallett } s; 3814232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xx; 3815232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xxp1; 3816232809Sjmallett}; 3817232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_mio_w1s cvmx_ciu2_en_ppx_ip2_mio_w1s_t; 3818232809Sjmallett 3819232809Sjmallett/** 3820232809Sjmallett * cvmx_ciu2_en_pp#_ip2_pkt 3821232809Sjmallett */ 3822232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_pkt { 3823232809Sjmallett uint64_t u64; 3824232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_pkt_s { 3825232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3826232809Sjmallett uint64_t reserved_54_63 : 10; 3827232809Sjmallett uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt-enable */ 3828232809Sjmallett uint64_t reserved_49_51 : 3; 3829232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupt-enable */ 3830232809Sjmallett uint64_t reserved_41_47 : 7; 3831232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */ 3832232809Sjmallett uint64_t reserved_33_39 : 7; 3833232809Sjmallett uint64_t agl : 1; /**< AGL interrupt-enable */ 3834232809Sjmallett uint64_t reserved_13_31 : 19; 3835232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */ 3836232809Sjmallett uint64_t reserved_5_7 : 3; 3837232809Sjmallett uint64_t agx : 5; /**< GMX interrupt-enable */ 3838232809Sjmallett#else 3839232809Sjmallett uint64_t agx : 5; 3840232809Sjmallett uint64_t reserved_5_7 : 3; 3841232809Sjmallett uint64_t gmx_drp : 5; 3842232809Sjmallett uint64_t reserved_13_31 : 19; 3843232809Sjmallett uint64_t agl : 1; 3844232809Sjmallett uint64_t reserved_33_39 : 7; 3845232809Sjmallett uint64_t mii : 1; 3846232809Sjmallett uint64_t reserved_41_47 : 7; 3847232809Sjmallett uint64_t ilk : 1; 3848232809Sjmallett uint64_t reserved_49_51 : 3; 3849232809Sjmallett uint64_t ilk_drp : 2; 3850232809Sjmallett uint64_t reserved_54_63 : 10; 3851232809Sjmallett#endif 3852232809Sjmallett } s; 3853232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_pkt_s cn68xx; 3854232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_pkt_cn68xxp1 { 3855232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3856232809Sjmallett uint64_t reserved_49_63 : 15; 3857232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupt-enable */ 3858232809Sjmallett uint64_t reserved_41_47 : 7; 3859232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */ 3860232809Sjmallett uint64_t reserved_33_39 : 7; 3861232809Sjmallett uint64_t agl : 1; /**< AGL interrupt-enable */ 3862232809Sjmallett uint64_t reserved_13_31 : 19; 3863232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */ 3864232809Sjmallett uint64_t reserved_5_7 : 3; 3865232809Sjmallett uint64_t agx : 5; /**< GMX interrupt-enable */ 3866232809Sjmallett#else 3867232809Sjmallett uint64_t agx : 5; 3868232809Sjmallett uint64_t reserved_5_7 : 3; 3869232809Sjmallett uint64_t gmx_drp : 5; 3870232809Sjmallett uint64_t reserved_13_31 : 19; 3871232809Sjmallett uint64_t agl : 1; 3872232809Sjmallett uint64_t reserved_33_39 : 7; 3873232809Sjmallett uint64_t mii : 1; 3874232809Sjmallett uint64_t reserved_41_47 : 7; 3875232809Sjmallett uint64_t ilk : 1; 3876232809Sjmallett uint64_t reserved_49_63 : 15; 3877232809Sjmallett#endif 3878232809Sjmallett } cn68xxp1; 3879232809Sjmallett}; 3880232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_pkt cvmx_ciu2_en_ppx_ip2_pkt_t; 3881232809Sjmallett 3882232809Sjmallett/** 3883232809Sjmallett * cvmx_ciu2_en_pp#_ip2_pkt_w1c 3884232809Sjmallett */ 3885232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_pkt_w1c { 3886232809Sjmallett uint64_t u64; 3887232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s { 3888232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3889232809Sjmallett uint64_t reserved_54_63 : 10; 3890232809Sjmallett uint64_t ilk_drp : 2; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK_DRP] */ 3891232809Sjmallett uint64_t reserved_49_51 : 3; 3892232809Sjmallett uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */ 3893232809Sjmallett uint64_t reserved_41_47 : 7; 3894232809Sjmallett uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */ 3895232809Sjmallett uint64_t reserved_33_39 : 7; 3896232809Sjmallett uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */ 3897232809Sjmallett uint64_t reserved_13_31 : 19; 3898232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */ 3899232809Sjmallett uint64_t reserved_5_7 : 3; 3900232809Sjmallett uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */ 3901232809Sjmallett#else 3902232809Sjmallett uint64_t agx : 5; 3903232809Sjmallett uint64_t reserved_5_7 : 3; 3904232809Sjmallett uint64_t gmx_drp : 5; 3905232809Sjmallett uint64_t reserved_13_31 : 19; 3906232809Sjmallett uint64_t agl : 1; 3907232809Sjmallett uint64_t reserved_33_39 : 7; 3908232809Sjmallett uint64_t mii : 1; 3909232809Sjmallett uint64_t reserved_41_47 : 7; 3910232809Sjmallett uint64_t ilk : 1; 3911232809Sjmallett uint64_t reserved_49_51 : 3; 3912232809Sjmallett uint64_t ilk_drp : 2; 3913232809Sjmallett uint64_t reserved_54_63 : 10; 3914232809Sjmallett#endif 3915232809Sjmallett } s; 3916232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s cn68xx; 3917232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_cn68xxp1 { 3918232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3919232809Sjmallett uint64_t reserved_49_63 : 15; 3920232809Sjmallett uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */ 3921232809Sjmallett uint64_t reserved_41_47 : 7; 3922232809Sjmallett uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */ 3923232809Sjmallett uint64_t reserved_33_39 : 7; 3924232809Sjmallett uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */ 3925232809Sjmallett uint64_t reserved_13_31 : 19; 3926232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */ 3927232809Sjmallett uint64_t reserved_5_7 : 3; 3928232809Sjmallett uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */ 3929232809Sjmallett#else 3930232809Sjmallett uint64_t agx : 5; 3931232809Sjmallett uint64_t reserved_5_7 : 3; 3932232809Sjmallett uint64_t gmx_drp : 5; 3933232809Sjmallett uint64_t reserved_13_31 : 19; 3934232809Sjmallett uint64_t agl : 1; 3935232809Sjmallett uint64_t reserved_33_39 : 7; 3936232809Sjmallett uint64_t mii : 1; 3937232809Sjmallett uint64_t reserved_41_47 : 7; 3938232809Sjmallett uint64_t ilk : 1; 3939232809Sjmallett uint64_t reserved_49_63 : 15; 3940232809Sjmallett#endif 3941232809Sjmallett } cn68xxp1; 3942232809Sjmallett}; 3943232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_pkt_w1c cvmx_ciu2_en_ppx_ip2_pkt_w1c_t; 3944232809Sjmallett 3945232809Sjmallett/** 3946232809Sjmallett * cvmx_ciu2_en_pp#_ip2_pkt_w1s 3947232809Sjmallett */ 3948232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_pkt_w1s { 3949232809Sjmallett uint64_t u64; 3950232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s { 3951232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3952232809Sjmallett uint64_t reserved_54_63 : 10; 3953232809Sjmallett uint64_t ilk_drp : 2; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK_DRP] */ 3954232809Sjmallett uint64_t reserved_49_51 : 3; 3955232809Sjmallett uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */ 3956232809Sjmallett uint64_t reserved_41_47 : 7; 3957232809Sjmallett uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */ 3958232809Sjmallett uint64_t reserved_33_39 : 7; 3959232809Sjmallett uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */ 3960232809Sjmallett uint64_t reserved_13_31 : 19; 3961232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */ 3962232809Sjmallett uint64_t reserved_5_7 : 3; 3963232809Sjmallett uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */ 3964232809Sjmallett#else 3965232809Sjmallett uint64_t agx : 5; 3966232809Sjmallett uint64_t reserved_5_7 : 3; 3967232809Sjmallett uint64_t gmx_drp : 5; 3968232809Sjmallett uint64_t reserved_13_31 : 19; 3969232809Sjmallett uint64_t agl : 1; 3970232809Sjmallett uint64_t reserved_33_39 : 7; 3971232809Sjmallett uint64_t mii : 1; 3972232809Sjmallett uint64_t reserved_41_47 : 7; 3973232809Sjmallett uint64_t ilk : 1; 3974232809Sjmallett uint64_t reserved_49_51 : 3; 3975232809Sjmallett uint64_t ilk_drp : 2; 3976232809Sjmallett uint64_t reserved_54_63 : 10; 3977232809Sjmallett#endif 3978232809Sjmallett } s; 3979232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s cn68xx; 3980232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_cn68xxp1 { 3981232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3982232809Sjmallett uint64_t reserved_49_63 : 15; 3983232809Sjmallett uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */ 3984232809Sjmallett uint64_t reserved_41_47 : 7; 3985232809Sjmallett uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */ 3986232809Sjmallett uint64_t reserved_33_39 : 7; 3987232809Sjmallett uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */ 3988232809Sjmallett uint64_t reserved_13_31 : 19; 3989232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */ 3990232809Sjmallett uint64_t reserved_5_7 : 3; 3991232809Sjmallett uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */ 3992232809Sjmallett#else 3993232809Sjmallett uint64_t agx : 5; 3994232809Sjmallett uint64_t reserved_5_7 : 3; 3995232809Sjmallett uint64_t gmx_drp : 5; 3996232809Sjmallett uint64_t reserved_13_31 : 19; 3997232809Sjmallett uint64_t agl : 1; 3998232809Sjmallett uint64_t reserved_33_39 : 7; 3999232809Sjmallett uint64_t mii : 1; 4000232809Sjmallett uint64_t reserved_41_47 : 7; 4001232809Sjmallett uint64_t ilk : 1; 4002232809Sjmallett uint64_t reserved_49_63 : 15; 4003232809Sjmallett#endif 4004232809Sjmallett } cn68xxp1; 4005232809Sjmallett}; 4006232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_pkt_w1s cvmx_ciu2_en_ppx_ip2_pkt_w1s_t; 4007232809Sjmallett 4008232809Sjmallett/** 4009232809Sjmallett * cvmx_ciu2_en_pp#_ip2_rml 4010232809Sjmallett */ 4011232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_rml { 4012232809Sjmallett uint64_t u64; 4013232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_rml_s { 4014232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4015232809Sjmallett uint64_t reserved_56_63 : 8; 4016232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt-enable */ 4017232809Sjmallett uint64_t reserved_49_51 : 3; 4018232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt-enable */ 4019232809Sjmallett uint64_t reserved_41_47 : 7; 4020232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt-enable */ 4021232809Sjmallett uint64_t reserved_37_39 : 3; 4022232809Sjmallett uint64_t dpi_dma : 1; /**< DPI DMA interrupt-enable */ 4023232809Sjmallett uint64_t reserved_34_35 : 2; 4024232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt-enable */ 4025232809Sjmallett uint64_t sli : 1; /**< SLI interrupt-enable */ 4026232809Sjmallett uint64_t reserved_31_31 : 1; 4027232809Sjmallett uint64_t key : 1; /**< KEY interrupt-enable */ 4028232809Sjmallett uint64_t rad : 1; /**< RAD interrupt-enable */ 4029232809Sjmallett uint64_t tim : 1; /**< TIM interrupt-enable */ 4030232809Sjmallett uint64_t reserved_25_27 : 3; 4031232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt-enable */ 4032232809Sjmallett uint64_t reserved_17_23 : 7; 4033232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt-enable */ 4034232809Sjmallett uint64_t reserved_8_15 : 8; 4035232809Sjmallett uint64_t pko : 1; /**< PKO interrupt-enable */ 4036232809Sjmallett uint64_t pip : 1; /**< PIP interrupt-enable */ 4037232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt-enable */ 4038232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt-enable */ 4039232809Sjmallett uint64_t reserved_1_3 : 3; 4040232809Sjmallett uint64_t iob : 1; /**< IOB interrupt-enable */ 4041232809Sjmallett#else 4042232809Sjmallett uint64_t iob : 1; 4043232809Sjmallett uint64_t reserved_1_3 : 3; 4044232809Sjmallett uint64_t fpa : 1; 4045232809Sjmallett uint64_t ipd : 1; 4046232809Sjmallett uint64_t pip : 1; 4047232809Sjmallett uint64_t pko : 1; 4048232809Sjmallett uint64_t reserved_8_15 : 8; 4049232809Sjmallett uint64_t sso : 1; 4050232809Sjmallett uint64_t reserved_17_23 : 7; 4051232809Sjmallett uint64_t zip : 1; 4052232809Sjmallett uint64_t reserved_25_27 : 3; 4053232809Sjmallett uint64_t tim : 1; 4054232809Sjmallett uint64_t rad : 1; 4055232809Sjmallett uint64_t key : 1; 4056232809Sjmallett uint64_t reserved_31_31 : 1; 4057232809Sjmallett uint64_t sli : 1; 4058232809Sjmallett uint64_t dpi : 1; 4059232809Sjmallett uint64_t reserved_34_35 : 2; 4060232809Sjmallett uint64_t dpi_dma : 1; 4061232809Sjmallett uint64_t reserved_37_39 : 3; 4062232809Sjmallett uint64_t dfa : 1; 4063232809Sjmallett uint64_t reserved_41_47 : 7; 4064232809Sjmallett uint64_t l2c : 1; 4065232809Sjmallett uint64_t reserved_49_51 : 3; 4066232809Sjmallett uint64_t trace : 4; 4067232809Sjmallett uint64_t reserved_56_63 : 8; 4068232809Sjmallett#endif 4069232809Sjmallett } s; 4070232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_rml_s cn68xx; 4071232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_rml_cn68xxp1 { 4072232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4073232809Sjmallett uint64_t reserved_56_63 : 8; 4074232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt-enable */ 4075232809Sjmallett uint64_t reserved_49_51 : 3; 4076232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt-enable */ 4077232809Sjmallett uint64_t reserved_41_47 : 7; 4078232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt-enable */ 4079232809Sjmallett uint64_t reserved_34_39 : 6; 4080232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt-enable */ 4081232809Sjmallett uint64_t sli : 1; /**< SLI interrupt-enable */ 4082232809Sjmallett uint64_t reserved_31_31 : 1; 4083232809Sjmallett uint64_t key : 1; /**< KEY interrupt-enable */ 4084232809Sjmallett uint64_t rad : 1; /**< RAD interrupt-enable */ 4085232809Sjmallett uint64_t tim : 1; /**< TIM interrupt-enable */ 4086232809Sjmallett uint64_t reserved_25_27 : 3; 4087232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt-enable */ 4088232809Sjmallett uint64_t reserved_17_23 : 7; 4089232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt-enable */ 4090232809Sjmallett uint64_t reserved_8_15 : 8; 4091232809Sjmallett uint64_t pko : 1; /**< PKO interrupt-enable */ 4092232809Sjmallett uint64_t pip : 1; /**< PIP interrupt-enable */ 4093232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt-enable */ 4094232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt-enable */ 4095232809Sjmallett uint64_t reserved_1_3 : 3; 4096232809Sjmallett uint64_t iob : 1; /**< IOB interrupt-enable */ 4097232809Sjmallett#else 4098232809Sjmallett uint64_t iob : 1; 4099232809Sjmallett uint64_t reserved_1_3 : 3; 4100232809Sjmallett uint64_t fpa : 1; 4101232809Sjmallett uint64_t ipd : 1; 4102232809Sjmallett uint64_t pip : 1; 4103232809Sjmallett uint64_t pko : 1; 4104232809Sjmallett uint64_t reserved_8_15 : 8; 4105232809Sjmallett uint64_t sso : 1; 4106232809Sjmallett uint64_t reserved_17_23 : 7; 4107232809Sjmallett uint64_t zip : 1; 4108232809Sjmallett uint64_t reserved_25_27 : 3; 4109232809Sjmallett uint64_t tim : 1; 4110232809Sjmallett uint64_t rad : 1; 4111232809Sjmallett uint64_t key : 1; 4112232809Sjmallett uint64_t reserved_31_31 : 1; 4113232809Sjmallett uint64_t sli : 1; 4114232809Sjmallett uint64_t dpi : 1; 4115232809Sjmallett uint64_t reserved_34_39 : 6; 4116232809Sjmallett uint64_t dfa : 1; 4117232809Sjmallett uint64_t reserved_41_47 : 7; 4118232809Sjmallett uint64_t l2c : 1; 4119232809Sjmallett uint64_t reserved_49_51 : 3; 4120232809Sjmallett uint64_t trace : 4; 4121232809Sjmallett uint64_t reserved_56_63 : 8; 4122232809Sjmallett#endif 4123232809Sjmallett } cn68xxp1; 4124232809Sjmallett}; 4125232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_rml cvmx_ciu2_en_ppx_ip2_rml_t; 4126232809Sjmallett 4127232809Sjmallett/** 4128232809Sjmallett * cvmx_ciu2_en_pp#_ip2_rml_w1c 4129232809Sjmallett */ 4130232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_rml_w1c { 4131232809Sjmallett uint64_t u64; 4132232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s { 4133232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4134232809Sjmallett uint64_t reserved_56_63 : 8; 4135232809Sjmallett uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */ 4136232809Sjmallett uint64_t reserved_49_51 : 3; 4137232809Sjmallett uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */ 4138232809Sjmallett uint64_t reserved_41_47 : 7; 4139232809Sjmallett uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */ 4140232809Sjmallett uint64_t reserved_37_39 : 3; 4141232809Sjmallett uint64_t dpi_dma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI_DMA] */ 4142232809Sjmallett uint64_t reserved_34_35 : 2; 4143232809Sjmallett uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */ 4144232809Sjmallett uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */ 4145232809Sjmallett uint64_t reserved_31_31 : 1; 4146232809Sjmallett uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */ 4147232809Sjmallett uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */ 4148232809Sjmallett uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */ 4149232809Sjmallett uint64_t reserved_25_27 : 3; 4150232809Sjmallett uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */ 4151232809Sjmallett uint64_t reserved_17_23 : 7; 4152232809Sjmallett uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */ 4153232809Sjmallett uint64_t reserved_8_15 : 8; 4154232809Sjmallett uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */ 4155232809Sjmallett uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */ 4156232809Sjmallett uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */ 4157232809Sjmallett uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */ 4158232809Sjmallett uint64_t reserved_1_3 : 3; 4159232809Sjmallett uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */ 4160232809Sjmallett#else 4161232809Sjmallett uint64_t iob : 1; 4162232809Sjmallett uint64_t reserved_1_3 : 3; 4163232809Sjmallett uint64_t fpa : 1; 4164232809Sjmallett uint64_t ipd : 1; 4165232809Sjmallett uint64_t pip : 1; 4166232809Sjmallett uint64_t pko : 1; 4167232809Sjmallett uint64_t reserved_8_15 : 8; 4168232809Sjmallett uint64_t sso : 1; 4169232809Sjmallett uint64_t reserved_17_23 : 7; 4170232809Sjmallett uint64_t zip : 1; 4171232809Sjmallett uint64_t reserved_25_27 : 3; 4172232809Sjmallett uint64_t tim : 1; 4173232809Sjmallett uint64_t rad : 1; 4174232809Sjmallett uint64_t key : 1; 4175232809Sjmallett uint64_t reserved_31_31 : 1; 4176232809Sjmallett uint64_t sli : 1; 4177232809Sjmallett uint64_t dpi : 1; 4178232809Sjmallett uint64_t reserved_34_35 : 2; 4179232809Sjmallett uint64_t dpi_dma : 1; 4180232809Sjmallett uint64_t reserved_37_39 : 3; 4181232809Sjmallett uint64_t dfa : 1; 4182232809Sjmallett uint64_t reserved_41_47 : 7; 4183232809Sjmallett uint64_t l2c : 1; 4184232809Sjmallett uint64_t reserved_49_51 : 3; 4185232809Sjmallett uint64_t trace : 4; 4186232809Sjmallett uint64_t reserved_56_63 : 8; 4187232809Sjmallett#endif 4188232809Sjmallett } s; 4189232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s cn68xx; 4190232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_rml_w1c_cn68xxp1 { 4191232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4192232809Sjmallett uint64_t reserved_56_63 : 8; 4193232809Sjmallett uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */ 4194232809Sjmallett uint64_t reserved_49_51 : 3; 4195232809Sjmallett uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */ 4196232809Sjmallett uint64_t reserved_41_47 : 7; 4197232809Sjmallett uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */ 4198232809Sjmallett uint64_t reserved_34_39 : 6; 4199232809Sjmallett uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */ 4200232809Sjmallett uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */ 4201232809Sjmallett uint64_t reserved_31_31 : 1; 4202232809Sjmallett uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */ 4203232809Sjmallett uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */ 4204232809Sjmallett uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */ 4205232809Sjmallett uint64_t reserved_25_27 : 3; 4206232809Sjmallett uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */ 4207232809Sjmallett uint64_t reserved_17_23 : 7; 4208232809Sjmallett uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */ 4209232809Sjmallett uint64_t reserved_8_15 : 8; 4210232809Sjmallett uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */ 4211232809Sjmallett uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */ 4212232809Sjmallett uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */ 4213232809Sjmallett uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */ 4214232809Sjmallett uint64_t reserved_1_3 : 3; 4215232809Sjmallett uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */ 4216232809Sjmallett#else 4217232809Sjmallett uint64_t iob : 1; 4218232809Sjmallett uint64_t reserved_1_3 : 3; 4219232809Sjmallett uint64_t fpa : 1; 4220232809Sjmallett uint64_t ipd : 1; 4221232809Sjmallett uint64_t pip : 1; 4222232809Sjmallett uint64_t pko : 1; 4223232809Sjmallett uint64_t reserved_8_15 : 8; 4224232809Sjmallett uint64_t sso : 1; 4225232809Sjmallett uint64_t reserved_17_23 : 7; 4226232809Sjmallett uint64_t zip : 1; 4227232809Sjmallett uint64_t reserved_25_27 : 3; 4228232809Sjmallett uint64_t tim : 1; 4229232809Sjmallett uint64_t rad : 1; 4230232809Sjmallett uint64_t key : 1; 4231232809Sjmallett uint64_t reserved_31_31 : 1; 4232232809Sjmallett uint64_t sli : 1; 4233232809Sjmallett uint64_t dpi : 1; 4234232809Sjmallett uint64_t reserved_34_39 : 6; 4235232809Sjmallett uint64_t dfa : 1; 4236232809Sjmallett uint64_t reserved_41_47 : 7; 4237232809Sjmallett uint64_t l2c : 1; 4238232809Sjmallett uint64_t reserved_49_51 : 3; 4239232809Sjmallett uint64_t trace : 4; 4240232809Sjmallett uint64_t reserved_56_63 : 8; 4241232809Sjmallett#endif 4242232809Sjmallett } cn68xxp1; 4243232809Sjmallett}; 4244232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_rml_w1c cvmx_ciu2_en_ppx_ip2_rml_w1c_t; 4245232809Sjmallett 4246232809Sjmallett/** 4247232809Sjmallett * cvmx_ciu2_en_pp#_ip2_rml_w1s 4248232809Sjmallett */ 4249232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_rml_w1s { 4250232809Sjmallett uint64_t u64; 4251232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s { 4252232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4253232809Sjmallett uint64_t reserved_56_63 : 8; 4254232809Sjmallett uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */ 4255232809Sjmallett uint64_t reserved_49_51 : 3; 4256232809Sjmallett uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */ 4257232809Sjmallett uint64_t reserved_41_47 : 7; 4258232809Sjmallett uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */ 4259232809Sjmallett uint64_t reserved_37_39 : 3; 4260232809Sjmallett uint64_t dpi_dma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI_DMA] */ 4261232809Sjmallett uint64_t reserved_34_35 : 2; 4262232809Sjmallett uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */ 4263232809Sjmallett uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */ 4264232809Sjmallett uint64_t reserved_31_31 : 1; 4265232809Sjmallett uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */ 4266232809Sjmallett uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */ 4267232809Sjmallett uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */ 4268232809Sjmallett uint64_t reserved_25_27 : 3; 4269232809Sjmallett uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */ 4270232809Sjmallett uint64_t reserved_17_23 : 7; 4271232809Sjmallett uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */ 4272232809Sjmallett uint64_t reserved_8_15 : 8; 4273232809Sjmallett uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */ 4274232809Sjmallett uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */ 4275232809Sjmallett uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */ 4276232809Sjmallett uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */ 4277232809Sjmallett uint64_t reserved_1_3 : 3; 4278232809Sjmallett uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */ 4279232809Sjmallett#else 4280232809Sjmallett uint64_t iob : 1; 4281232809Sjmallett uint64_t reserved_1_3 : 3; 4282232809Sjmallett uint64_t fpa : 1; 4283232809Sjmallett uint64_t ipd : 1; 4284232809Sjmallett uint64_t pip : 1; 4285232809Sjmallett uint64_t pko : 1; 4286232809Sjmallett uint64_t reserved_8_15 : 8; 4287232809Sjmallett uint64_t sso : 1; 4288232809Sjmallett uint64_t reserved_17_23 : 7; 4289232809Sjmallett uint64_t zip : 1; 4290232809Sjmallett uint64_t reserved_25_27 : 3; 4291232809Sjmallett uint64_t tim : 1; 4292232809Sjmallett uint64_t rad : 1; 4293232809Sjmallett uint64_t key : 1; 4294232809Sjmallett uint64_t reserved_31_31 : 1; 4295232809Sjmallett uint64_t sli : 1; 4296232809Sjmallett uint64_t dpi : 1; 4297232809Sjmallett uint64_t reserved_34_35 : 2; 4298232809Sjmallett uint64_t dpi_dma : 1; 4299232809Sjmallett uint64_t reserved_37_39 : 3; 4300232809Sjmallett uint64_t dfa : 1; 4301232809Sjmallett uint64_t reserved_41_47 : 7; 4302232809Sjmallett uint64_t l2c : 1; 4303232809Sjmallett uint64_t reserved_49_51 : 3; 4304232809Sjmallett uint64_t trace : 4; 4305232809Sjmallett uint64_t reserved_56_63 : 8; 4306232809Sjmallett#endif 4307232809Sjmallett } s; 4308232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s cn68xx; 4309232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_rml_w1s_cn68xxp1 { 4310232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4311232809Sjmallett uint64_t reserved_56_63 : 8; 4312232809Sjmallett uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */ 4313232809Sjmallett uint64_t reserved_49_51 : 3; 4314232809Sjmallett uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */ 4315232809Sjmallett uint64_t reserved_41_47 : 7; 4316232809Sjmallett uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */ 4317232809Sjmallett uint64_t reserved_34_39 : 6; 4318232809Sjmallett uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */ 4319232809Sjmallett uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */ 4320232809Sjmallett uint64_t reserved_31_31 : 1; 4321232809Sjmallett uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */ 4322232809Sjmallett uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */ 4323232809Sjmallett uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */ 4324232809Sjmallett uint64_t reserved_25_27 : 3; 4325232809Sjmallett uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */ 4326232809Sjmallett uint64_t reserved_17_23 : 7; 4327232809Sjmallett uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */ 4328232809Sjmallett uint64_t reserved_8_15 : 8; 4329232809Sjmallett uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */ 4330232809Sjmallett uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */ 4331232809Sjmallett uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */ 4332232809Sjmallett uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */ 4333232809Sjmallett uint64_t reserved_1_3 : 3; 4334232809Sjmallett uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */ 4335232809Sjmallett#else 4336232809Sjmallett uint64_t iob : 1; 4337232809Sjmallett uint64_t reserved_1_3 : 3; 4338232809Sjmallett uint64_t fpa : 1; 4339232809Sjmallett uint64_t ipd : 1; 4340232809Sjmallett uint64_t pip : 1; 4341232809Sjmallett uint64_t pko : 1; 4342232809Sjmallett uint64_t reserved_8_15 : 8; 4343232809Sjmallett uint64_t sso : 1; 4344232809Sjmallett uint64_t reserved_17_23 : 7; 4345232809Sjmallett uint64_t zip : 1; 4346232809Sjmallett uint64_t reserved_25_27 : 3; 4347232809Sjmallett uint64_t tim : 1; 4348232809Sjmallett uint64_t rad : 1; 4349232809Sjmallett uint64_t key : 1; 4350232809Sjmallett uint64_t reserved_31_31 : 1; 4351232809Sjmallett uint64_t sli : 1; 4352232809Sjmallett uint64_t dpi : 1; 4353232809Sjmallett uint64_t reserved_34_39 : 6; 4354232809Sjmallett uint64_t dfa : 1; 4355232809Sjmallett uint64_t reserved_41_47 : 7; 4356232809Sjmallett uint64_t l2c : 1; 4357232809Sjmallett uint64_t reserved_49_51 : 3; 4358232809Sjmallett uint64_t trace : 4; 4359232809Sjmallett uint64_t reserved_56_63 : 8; 4360232809Sjmallett#endif 4361232809Sjmallett } cn68xxp1; 4362232809Sjmallett}; 4363232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_rml_w1s cvmx_ciu2_en_ppx_ip2_rml_w1s_t; 4364232809Sjmallett 4365232809Sjmallett/** 4366232809Sjmallett * cvmx_ciu2_en_pp#_ip2_wdog 4367232809Sjmallett */ 4368232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_wdog { 4369232809Sjmallett uint64_t u64; 4370232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wdog_s { 4371232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4372232809Sjmallett uint64_t reserved_32_63 : 32; 4373232809Sjmallett uint64_t wdog : 32; /**< 32 watchdog interrupt-enable */ 4374232809Sjmallett#else 4375232809Sjmallett uint64_t wdog : 32; 4376232809Sjmallett uint64_t reserved_32_63 : 32; 4377232809Sjmallett#endif 4378232809Sjmallett } s; 4379232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xx; 4380232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xxp1; 4381232809Sjmallett}; 4382232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_wdog cvmx_ciu2_en_ppx_ip2_wdog_t; 4383232809Sjmallett 4384232809Sjmallett/** 4385232809Sjmallett * cvmx_ciu2_en_pp#_ip2_wdog_w1c 4386232809Sjmallett */ 4387232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_wdog_w1c { 4388232809Sjmallett uint64_t u64; 4389232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s { 4390232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4391232809Sjmallett uint64_t reserved_32_63 : 32; 4392232809Sjmallett uint64_t wdog : 32; /**< write 1 to clear CIU2_EN_xx_yy_WDOG */ 4393232809Sjmallett#else 4394232809Sjmallett uint64_t wdog : 32; 4395232809Sjmallett uint64_t reserved_32_63 : 32; 4396232809Sjmallett#endif 4397232809Sjmallett } s; 4398232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xx; 4399232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xxp1; 4400232809Sjmallett}; 4401232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_wdog_w1c cvmx_ciu2_en_ppx_ip2_wdog_w1c_t; 4402232809Sjmallett 4403232809Sjmallett/** 4404232809Sjmallett * cvmx_ciu2_en_pp#_ip2_wdog_w1s 4405232809Sjmallett */ 4406232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_wdog_w1s { 4407232809Sjmallett uint64_t u64; 4408232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s { 4409232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4410232809Sjmallett uint64_t reserved_32_63 : 32; 4411232809Sjmallett uint64_t wdog : 32; /**< Write 1 to enable CIU2_EN_xx_yy_WDOG[WDOG] */ 4412232809Sjmallett#else 4413232809Sjmallett uint64_t wdog : 32; 4414232809Sjmallett uint64_t reserved_32_63 : 32; 4415232809Sjmallett#endif 4416232809Sjmallett } s; 4417232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xx; 4418232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xxp1; 4419232809Sjmallett}; 4420232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_wdog_w1s cvmx_ciu2_en_ppx_ip2_wdog_w1s_t; 4421232809Sjmallett 4422232809Sjmallett/** 4423232809Sjmallett * cvmx_ciu2_en_pp#_ip2_wrkq 4424232809Sjmallett */ 4425232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_wrkq { 4426232809Sjmallett uint64_t u64; 4427232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wrkq_s { 4428232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4429232809Sjmallett uint64_t workq : 64; /**< 64 work queue interrupt-enable */ 4430232809Sjmallett#else 4431232809Sjmallett uint64_t workq : 64; 4432232809Sjmallett#endif 4433232809Sjmallett } s; 4434232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xx; 4435232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xxp1; 4436232809Sjmallett}; 4437232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_wrkq cvmx_ciu2_en_ppx_ip2_wrkq_t; 4438232809Sjmallett 4439232809Sjmallett/** 4440232809Sjmallett * cvmx_ciu2_en_pp#_ip2_wrkq_w1c 4441232809Sjmallett */ 4442232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_wrkq_w1c { 4443232809Sjmallett uint64_t u64; 4444232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s { 4445232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4446232809Sjmallett uint64_t workq : 64; /**< Write 1 to clear CIU2_EN_xx_yy_WRKQ[WORKQ] 4447232809Sjmallett For W1C bits, write 1 to clear the corresponding 4448232809Sjmallett CIU2_EN_xx_yy_WRKQ,write 0 to retain previous value */ 4449232809Sjmallett#else 4450232809Sjmallett uint64_t workq : 64; 4451232809Sjmallett#endif 4452232809Sjmallett } s; 4453232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xx; 4454232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xxp1; 4455232809Sjmallett}; 4456232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_wrkq_w1c cvmx_ciu2_en_ppx_ip2_wrkq_w1c_t; 4457232809Sjmallett 4458232809Sjmallett/** 4459232809Sjmallett * cvmx_ciu2_en_pp#_ip2_wrkq_w1s 4460232809Sjmallett */ 4461232809Sjmallettunion cvmx_ciu2_en_ppx_ip2_wrkq_w1s { 4462232809Sjmallett uint64_t u64; 4463232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s { 4464232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4465232809Sjmallett uint64_t workq : 64; /**< Write 1 to enable CIU2_EN_xx_yy_WRKQ[WORKQ] 4466232809Sjmallett 1 bit/group. For all W1S bits, write 1 to enable 4467232809Sjmallett corresponding CIU2_EN_xx_yy_WRKQ[WORKQ] bit, 4468232809Sjmallett writing 0 to retain previous value. */ 4469232809Sjmallett#else 4470232809Sjmallett uint64_t workq : 64; 4471232809Sjmallett#endif 4472232809Sjmallett } s; 4473232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xx; 4474232809Sjmallett struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xxp1; 4475232809Sjmallett}; 4476232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip2_wrkq_w1s cvmx_ciu2_en_ppx_ip2_wrkq_w1s_t; 4477232809Sjmallett 4478232809Sjmallett/** 4479232809Sjmallett * cvmx_ciu2_en_pp#_ip3_gpio 4480232809Sjmallett */ 4481232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_gpio { 4482232809Sjmallett uint64_t u64; 4483232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_gpio_s { 4484232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4485232809Sjmallett uint64_t reserved_16_63 : 48; 4486232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupt-enable */ 4487232809Sjmallett#else 4488232809Sjmallett uint64_t gpio : 16; 4489232809Sjmallett uint64_t reserved_16_63 : 48; 4490232809Sjmallett#endif 4491232809Sjmallett } s; 4492232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xx; 4493232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xxp1; 4494232809Sjmallett}; 4495232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_gpio cvmx_ciu2_en_ppx_ip3_gpio_t; 4496232809Sjmallett 4497232809Sjmallett/** 4498232809Sjmallett * cvmx_ciu2_en_pp#_ip3_gpio_w1c 4499232809Sjmallett */ 4500232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_gpio_w1c { 4501232809Sjmallett uint64_t u64; 4502232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s { 4503232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4504232809Sjmallett uint64_t reserved_16_63 : 48; 4505232809Sjmallett uint64_t gpio : 16; /**< Write 1 to clear CIU2_EN_xx_yy_GPIO[GPIO] */ 4506232809Sjmallett#else 4507232809Sjmallett uint64_t gpio : 16; 4508232809Sjmallett uint64_t reserved_16_63 : 48; 4509232809Sjmallett#endif 4510232809Sjmallett } s; 4511232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xx; 4512232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xxp1; 4513232809Sjmallett}; 4514232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_gpio_w1c cvmx_ciu2_en_ppx_ip3_gpio_w1c_t; 4515232809Sjmallett 4516232809Sjmallett/** 4517232809Sjmallett * cvmx_ciu2_en_pp#_ip3_gpio_w1s 4518232809Sjmallett */ 4519232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_gpio_w1s { 4520232809Sjmallett uint64_t u64; 4521232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s { 4522232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4523232809Sjmallett uint64_t reserved_16_63 : 48; 4524232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupt enable,write 1 to enable CIU2_EN */ 4525232809Sjmallett#else 4526232809Sjmallett uint64_t gpio : 16; 4527232809Sjmallett uint64_t reserved_16_63 : 48; 4528232809Sjmallett#endif 4529232809Sjmallett } s; 4530232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xx; 4531232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xxp1; 4532232809Sjmallett}; 4533232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_gpio_w1s cvmx_ciu2_en_ppx_ip3_gpio_w1s_t; 4534232809Sjmallett 4535232809Sjmallett/** 4536232809Sjmallett * cvmx_ciu2_en_pp#_ip3_io 4537232809Sjmallett */ 4538232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_io { 4539232809Sjmallett uint64_t u64; 4540232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_io_s { 4541232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4542232809Sjmallett uint64_t reserved_34_63 : 30; 4543232809Sjmallett uint64_t pem : 2; /**< PEMx interrupt-enable */ 4544232809Sjmallett uint64_t reserved_18_31 : 14; 4545232809Sjmallett uint64_t pci_inta : 2; /**< PCI_INTA interrupt-enable */ 4546232809Sjmallett uint64_t reserved_13_15 : 3; 4547232809Sjmallett uint64_t msired : 1; /**< MSI summary bit interrupt-enable 4548232809Sjmallett This bit may not be functional in pass 1. */ 4549232809Sjmallett uint64_t pci_msi : 4; /**< PCIe/sRIO MSI interrupt-enable */ 4550232809Sjmallett uint64_t reserved_4_7 : 4; 4551232809Sjmallett uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt-enable */ 4552232809Sjmallett#else 4553232809Sjmallett uint64_t pci_intr : 4; 4554232809Sjmallett uint64_t reserved_4_7 : 4; 4555232809Sjmallett uint64_t pci_msi : 4; 4556232809Sjmallett uint64_t msired : 1; 4557232809Sjmallett uint64_t reserved_13_15 : 3; 4558232809Sjmallett uint64_t pci_inta : 2; 4559232809Sjmallett uint64_t reserved_18_31 : 14; 4560232809Sjmallett uint64_t pem : 2; 4561232809Sjmallett uint64_t reserved_34_63 : 30; 4562232809Sjmallett#endif 4563232809Sjmallett } s; 4564232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_io_s cn68xx; 4565232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_io_s cn68xxp1; 4566232809Sjmallett}; 4567232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_io cvmx_ciu2_en_ppx_ip3_io_t; 4568232809Sjmallett 4569232809Sjmallett/** 4570232809Sjmallett * cvmx_ciu2_en_pp#_ip3_io_w1c 4571232809Sjmallett */ 4572232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_io_w1c { 4573232809Sjmallett uint64_t u64; 4574232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_io_w1c_s { 4575232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4576232809Sjmallett uint64_t reserved_34_63 : 30; 4577232809Sjmallett uint64_t pem : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PEM] */ 4578232809Sjmallett uint64_t reserved_18_31 : 14; 4579232809Sjmallett uint64_t pci_inta : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTA] */ 4580232809Sjmallett uint64_t reserved_13_15 : 3; 4581232809Sjmallett uint64_t msired : 1; /**< Write 1 to clear CIU2_EN_xx_yy_IO[MSIRED] 4582232809Sjmallett This bit may not be functional in pass 1. */ 4583232809Sjmallett uint64_t pci_msi : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_MSI] */ 4584232809Sjmallett uint64_t reserved_4_7 : 4; 4585232809Sjmallett uint64_t pci_intr : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTR] */ 4586232809Sjmallett#else 4587232809Sjmallett uint64_t pci_intr : 4; 4588232809Sjmallett uint64_t reserved_4_7 : 4; 4589232809Sjmallett uint64_t pci_msi : 4; 4590232809Sjmallett uint64_t msired : 1; 4591232809Sjmallett uint64_t reserved_13_15 : 3; 4592232809Sjmallett uint64_t pci_inta : 2; 4593232809Sjmallett uint64_t reserved_18_31 : 14; 4594232809Sjmallett uint64_t pem : 2; 4595232809Sjmallett uint64_t reserved_34_63 : 30; 4596232809Sjmallett#endif 4597232809Sjmallett } s; 4598232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xx; 4599232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xxp1; 4600232809Sjmallett}; 4601232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_io_w1c cvmx_ciu2_en_ppx_ip3_io_w1c_t; 4602232809Sjmallett 4603232809Sjmallett/** 4604232809Sjmallett * cvmx_ciu2_en_pp#_ip3_io_w1s 4605232809Sjmallett */ 4606232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_io_w1s { 4607232809Sjmallett uint64_t u64; 4608232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_io_w1s_s { 4609232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4610232809Sjmallett uint64_t reserved_34_63 : 30; 4611232809Sjmallett uint64_t pem : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PEM] */ 4612232809Sjmallett uint64_t reserved_18_31 : 14; 4613232809Sjmallett uint64_t pci_inta : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTA] */ 4614232809Sjmallett uint64_t reserved_13_15 : 3; 4615232809Sjmallett uint64_t msired : 1; /**< Write 1 to enable CIU2_EN_xx_yy_IO[MSIRED] 4616232809Sjmallett This bit may not be functional in pass 1. */ 4617232809Sjmallett uint64_t pci_msi : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_MSI] */ 4618232809Sjmallett uint64_t reserved_4_7 : 4; 4619232809Sjmallett uint64_t pci_intr : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTR] */ 4620232809Sjmallett#else 4621232809Sjmallett uint64_t pci_intr : 4; 4622232809Sjmallett uint64_t reserved_4_7 : 4; 4623232809Sjmallett uint64_t pci_msi : 4; 4624232809Sjmallett uint64_t msired : 1; 4625232809Sjmallett uint64_t reserved_13_15 : 3; 4626232809Sjmallett uint64_t pci_inta : 2; 4627232809Sjmallett uint64_t reserved_18_31 : 14; 4628232809Sjmallett uint64_t pem : 2; 4629232809Sjmallett uint64_t reserved_34_63 : 30; 4630232809Sjmallett#endif 4631232809Sjmallett } s; 4632232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xx; 4633232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xxp1; 4634232809Sjmallett}; 4635232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_io_w1s cvmx_ciu2_en_ppx_ip3_io_w1s_t; 4636232809Sjmallett 4637232809Sjmallett/** 4638232809Sjmallett * cvmx_ciu2_en_pp#_ip3_mbox 4639232809Sjmallett */ 4640232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_mbox { 4641232809Sjmallett uint64_t u64; 4642232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mbox_s { 4643232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4644232809Sjmallett uint64_t reserved_4_63 : 60; 4645232809Sjmallett uint64_t mbox : 4; /**< Mailbox interrupt-enable, use with CIU2_MBOX 4646232809Sjmallett to generate CIU2_SRC_xx_yy_MBOX */ 4647232809Sjmallett#else 4648232809Sjmallett uint64_t mbox : 4; 4649232809Sjmallett uint64_t reserved_4_63 : 60; 4650232809Sjmallett#endif 4651232809Sjmallett } s; 4652232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xx; 4653232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xxp1; 4654232809Sjmallett}; 4655232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_mbox cvmx_ciu2_en_ppx_ip3_mbox_t; 4656232809Sjmallett 4657232809Sjmallett/** 4658232809Sjmallett * cvmx_ciu2_en_pp#_ip3_mbox_w1c 4659232809Sjmallett */ 4660232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_mbox_w1c { 4661232809Sjmallett uint64_t u64; 4662232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s { 4663232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4664232809Sjmallett uint64_t reserved_4_63 : 60; 4665232809Sjmallett uint64_t mbox : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MBOX[MBOX] */ 4666232809Sjmallett#else 4667232809Sjmallett uint64_t mbox : 4; 4668232809Sjmallett uint64_t reserved_4_63 : 60; 4669232809Sjmallett#endif 4670232809Sjmallett } s; 4671232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xx; 4672232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xxp1; 4673232809Sjmallett}; 4674232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_mbox_w1c cvmx_ciu2_en_ppx_ip3_mbox_w1c_t; 4675232809Sjmallett 4676232809Sjmallett/** 4677232809Sjmallett * cvmx_ciu2_en_pp#_ip3_mbox_w1s 4678232809Sjmallett */ 4679232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_mbox_w1s { 4680232809Sjmallett uint64_t u64; 4681232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s { 4682232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4683232809Sjmallett uint64_t reserved_4_63 : 60; 4684232809Sjmallett uint64_t mbox : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MBOX[MBOX] */ 4685232809Sjmallett#else 4686232809Sjmallett uint64_t mbox : 4; 4687232809Sjmallett uint64_t reserved_4_63 : 60; 4688232809Sjmallett#endif 4689232809Sjmallett } s; 4690232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xx; 4691232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xxp1; 4692232809Sjmallett}; 4693232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_mbox_w1s cvmx_ciu2_en_ppx_ip3_mbox_w1s_t; 4694232809Sjmallett 4695232809Sjmallett/** 4696232809Sjmallett * cvmx_ciu2_en_pp#_ip3_mem 4697232809Sjmallett */ 4698232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_mem { 4699232809Sjmallett uint64_t u64; 4700232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mem_s { 4701232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4702232809Sjmallett uint64_t reserved_4_63 : 60; 4703232809Sjmallett uint64_t lmc : 4; /**< LMC* interrupt-enable */ 4704232809Sjmallett#else 4705232809Sjmallett uint64_t lmc : 4; 4706232809Sjmallett uint64_t reserved_4_63 : 60; 4707232809Sjmallett#endif 4708232809Sjmallett } s; 4709232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xx; 4710232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xxp1; 4711232809Sjmallett}; 4712232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_mem cvmx_ciu2_en_ppx_ip3_mem_t; 4713232809Sjmallett 4714232809Sjmallett/** 4715232809Sjmallett * cvmx_ciu2_en_pp#_ip3_mem_w1c 4716232809Sjmallett */ 4717232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_mem_w1c { 4718232809Sjmallett uint64_t u64; 4719232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s { 4720232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4721232809Sjmallett uint64_t reserved_4_63 : 60; 4722232809Sjmallett uint64_t lmc : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MEM[LMC] */ 4723232809Sjmallett#else 4724232809Sjmallett uint64_t lmc : 4; 4725232809Sjmallett uint64_t reserved_4_63 : 60; 4726232809Sjmallett#endif 4727232809Sjmallett } s; 4728232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xx; 4729232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xxp1; 4730232809Sjmallett}; 4731232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_mem_w1c cvmx_ciu2_en_ppx_ip3_mem_w1c_t; 4732232809Sjmallett 4733232809Sjmallett/** 4734232809Sjmallett * cvmx_ciu2_en_pp#_ip3_mem_w1s 4735232809Sjmallett */ 4736232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_mem_w1s { 4737232809Sjmallett uint64_t u64; 4738232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s { 4739232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4740232809Sjmallett uint64_t reserved_4_63 : 60; 4741232809Sjmallett uint64_t lmc : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MEM[LMC] */ 4742232809Sjmallett#else 4743232809Sjmallett uint64_t lmc : 4; 4744232809Sjmallett uint64_t reserved_4_63 : 60; 4745232809Sjmallett#endif 4746232809Sjmallett } s; 4747232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xx; 4748232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xxp1; 4749232809Sjmallett}; 4750232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_mem_w1s cvmx_ciu2_en_ppx_ip3_mem_w1s_t; 4751232809Sjmallett 4752232809Sjmallett/** 4753232809Sjmallett * cvmx_ciu2_en_pp#_ip3_mio 4754232809Sjmallett */ 4755232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_mio { 4756232809Sjmallett uint64_t u64; 4757232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mio_s { 4758232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4759232809Sjmallett uint64_t rst : 1; /**< MIO RST interrupt-enable */ 4760232809Sjmallett uint64_t reserved_49_62 : 14; 4761232809Sjmallett uint64_t ptp : 1; /**< PTP interrupt-enable */ 4762232809Sjmallett uint64_t reserved_45_47 : 3; 4763232809Sjmallett uint64_t usb_hci : 1; /**< USB HCI Interrupt-enable */ 4764232809Sjmallett uint64_t reserved_41_43 : 3; 4765232809Sjmallett uint64_t usb_uctl : 1; /**< USB UCTL* interrupt-enable */ 4766232809Sjmallett uint64_t reserved_38_39 : 2; 4767232809Sjmallett uint64_t uart : 2; /**< Two UART interrupt-enable */ 4768232809Sjmallett uint64_t reserved_34_35 : 2; 4769232809Sjmallett uint64_t twsi : 2; /**< TWSI x interrupt-enable */ 4770232809Sjmallett uint64_t reserved_19_31 : 13; 4771232809Sjmallett uint64_t bootdma : 1; /**< Boot bus DMA engines interrupt-enable */ 4772232809Sjmallett uint64_t mio : 1; /**< MIO boot interrupt-enable */ 4773232809Sjmallett uint64_t nand : 1; /**< NAND Flash Controller interrupt-enable */ 4774232809Sjmallett uint64_t reserved_12_15 : 4; 4775232809Sjmallett uint64_t timer : 4; /**< General timer interrupt-enable */ 4776232809Sjmallett uint64_t reserved_3_7 : 5; 4777232809Sjmallett uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt-enable */ 4778232809Sjmallett uint64_t ssoiq : 1; /**< SSO IQ interrupt-enable */ 4779232809Sjmallett uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt-enable */ 4780232809Sjmallett#else 4781232809Sjmallett uint64_t ipdppthr : 1; 4782232809Sjmallett uint64_t ssoiq : 1; 4783232809Sjmallett uint64_t ipd_drp : 1; 4784232809Sjmallett uint64_t reserved_3_7 : 5; 4785232809Sjmallett uint64_t timer : 4; 4786232809Sjmallett uint64_t reserved_12_15 : 4; 4787232809Sjmallett uint64_t nand : 1; 4788232809Sjmallett uint64_t mio : 1; 4789232809Sjmallett uint64_t bootdma : 1; 4790232809Sjmallett uint64_t reserved_19_31 : 13; 4791232809Sjmallett uint64_t twsi : 2; 4792232809Sjmallett uint64_t reserved_34_35 : 2; 4793232809Sjmallett uint64_t uart : 2; 4794232809Sjmallett uint64_t reserved_38_39 : 2; 4795232809Sjmallett uint64_t usb_uctl : 1; 4796232809Sjmallett uint64_t reserved_41_43 : 3; 4797232809Sjmallett uint64_t usb_hci : 1; 4798232809Sjmallett uint64_t reserved_45_47 : 3; 4799232809Sjmallett uint64_t ptp : 1; 4800232809Sjmallett uint64_t reserved_49_62 : 14; 4801232809Sjmallett uint64_t rst : 1; 4802232809Sjmallett#endif 4803232809Sjmallett } s; 4804232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xx; 4805232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xxp1; 4806232809Sjmallett}; 4807232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_mio cvmx_ciu2_en_ppx_ip3_mio_t; 4808232809Sjmallett 4809232809Sjmallett/** 4810232809Sjmallett * cvmx_ciu2_en_pp#_ip3_mio_w1c 4811232809Sjmallett */ 4812232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_mio_w1c { 4813232809Sjmallett uint64_t u64; 4814232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s { 4815232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4816232809Sjmallett uint64_t rst : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[RST] */ 4817232809Sjmallett uint64_t reserved_49_62 : 14; 4818232809Sjmallett uint64_t ptp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[PTP] */ 4819232809Sjmallett uint64_t reserved_45_47 : 3; 4820232809Sjmallett uint64_t usb_hci : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_HCI] */ 4821232809Sjmallett uint64_t reserved_41_43 : 3; 4822232809Sjmallett uint64_t usb_uctl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_UCTL] */ 4823232809Sjmallett uint64_t reserved_38_39 : 2; 4824232809Sjmallett uint64_t uart : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[UART] */ 4825232809Sjmallett uint64_t reserved_34_35 : 2; 4826232809Sjmallett uint64_t twsi : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TWSI] */ 4827232809Sjmallett uint64_t reserved_19_31 : 13; 4828232809Sjmallett uint64_t bootdma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[BOOTDMA] */ 4829232809Sjmallett uint64_t mio : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[MIO] */ 4830232809Sjmallett uint64_t nand : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[NAND] */ 4831232809Sjmallett uint64_t reserved_12_15 : 4; 4832232809Sjmallett uint64_t timer : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TIMER] */ 4833232809Sjmallett uint64_t reserved_3_7 : 5; 4834232809Sjmallett uint64_t ipd_drp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPD_DRP] */ 4835232809Sjmallett uint64_t ssoiq : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[SSQIQ] */ 4836232809Sjmallett uint64_t ipdppthr : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPDPPTHR] */ 4837232809Sjmallett#else 4838232809Sjmallett uint64_t ipdppthr : 1; 4839232809Sjmallett uint64_t ssoiq : 1; 4840232809Sjmallett uint64_t ipd_drp : 1; 4841232809Sjmallett uint64_t reserved_3_7 : 5; 4842232809Sjmallett uint64_t timer : 4; 4843232809Sjmallett uint64_t reserved_12_15 : 4; 4844232809Sjmallett uint64_t nand : 1; 4845232809Sjmallett uint64_t mio : 1; 4846232809Sjmallett uint64_t bootdma : 1; 4847232809Sjmallett uint64_t reserved_19_31 : 13; 4848232809Sjmallett uint64_t twsi : 2; 4849232809Sjmallett uint64_t reserved_34_35 : 2; 4850232809Sjmallett uint64_t uart : 2; 4851232809Sjmallett uint64_t reserved_38_39 : 2; 4852232809Sjmallett uint64_t usb_uctl : 1; 4853232809Sjmallett uint64_t reserved_41_43 : 3; 4854232809Sjmallett uint64_t usb_hci : 1; 4855232809Sjmallett uint64_t reserved_45_47 : 3; 4856232809Sjmallett uint64_t ptp : 1; 4857232809Sjmallett uint64_t reserved_49_62 : 14; 4858232809Sjmallett uint64_t rst : 1; 4859232809Sjmallett#endif 4860232809Sjmallett } s; 4861232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xx; 4862232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xxp1; 4863232809Sjmallett}; 4864232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_mio_w1c cvmx_ciu2_en_ppx_ip3_mio_w1c_t; 4865232809Sjmallett 4866232809Sjmallett/** 4867232809Sjmallett * cvmx_ciu2_en_pp#_ip3_mio_w1s 4868232809Sjmallett */ 4869232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_mio_w1s { 4870232809Sjmallett uint64_t u64; 4871232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s { 4872232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4873232809Sjmallett uint64_t rst : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[RST] */ 4874232809Sjmallett uint64_t reserved_49_62 : 14; 4875232809Sjmallett uint64_t ptp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[PTP] */ 4876232809Sjmallett uint64_t reserved_45_47 : 3; 4877232809Sjmallett uint64_t usb_hci : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_HCI] */ 4878232809Sjmallett uint64_t reserved_41_43 : 3; 4879232809Sjmallett uint64_t usb_uctl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_UCTL] */ 4880232809Sjmallett uint64_t reserved_38_39 : 2; 4881232809Sjmallett uint64_t uart : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[UART] */ 4882232809Sjmallett uint64_t reserved_34_35 : 2; 4883232809Sjmallett uint64_t twsi : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TWSI] */ 4884232809Sjmallett uint64_t reserved_19_31 : 13; 4885232809Sjmallett uint64_t bootdma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[BOOTDMA] */ 4886232809Sjmallett uint64_t mio : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[MIO] */ 4887232809Sjmallett uint64_t nand : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[NAND] */ 4888232809Sjmallett uint64_t reserved_12_15 : 4; 4889232809Sjmallett uint64_t timer : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TIMER] */ 4890232809Sjmallett uint64_t reserved_3_7 : 5; 4891232809Sjmallett uint64_t ipd_drp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPD_DRP] */ 4892232809Sjmallett uint64_t ssoiq : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[SSQIQ] */ 4893232809Sjmallett uint64_t ipdppthr : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPDPPTHR] */ 4894232809Sjmallett#else 4895232809Sjmallett uint64_t ipdppthr : 1; 4896232809Sjmallett uint64_t ssoiq : 1; 4897232809Sjmallett uint64_t ipd_drp : 1; 4898232809Sjmallett uint64_t reserved_3_7 : 5; 4899232809Sjmallett uint64_t timer : 4; 4900232809Sjmallett uint64_t reserved_12_15 : 4; 4901232809Sjmallett uint64_t nand : 1; 4902232809Sjmallett uint64_t mio : 1; 4903232809Sjmallett uint64_t bootdma : 1; 4904232809Sjmallett uint64_t reserved_19_31 : 13; 4905232809Sjmallett uint64_t twsi : 2; 4906232809Sjmallett uint64_t reserved_34_35 : 2; 4907232809Sjmallett uint64_t uart : 2; 4908232809Sjmallett uint64_t reserved_38_39 : 2; 4909232809Sjmallett uint64_t usb_uctl : 1; 4910232809Sjmallett uint64_t reserved_41_43 : 3; 4911232809Sjmallett uint64_t usb_hci : 1; 4912232809Sjmallett uint64_t reserved_45_47 : 3; 4913232809Sjmallett uint64_t ptp : 1; 4914232809Sjmallett uint64_t reserved_49_62 : 14; 4915232809Sjmallett uint64_t rst : 1; 4916232809Sjmallett#endif 4917232809Sjmallett } s; 4918232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xx; 4919232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xxp1; 4920232809Sjmallett}; 4921232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_mio_w1s cvmx_ciu2_en_ppx_ip3_mio_w1s_t; 4922232809Sjmallett 4923232809Sjmallett/** 4924232809Sjmallett * cvmx_ciu2_en_pp#_ip3_pkt 4925232809Sjmallett */ 4926232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_pkt { 4927232809Sjmallett uint64_t u64; 4928232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_pkt_s { 4929232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4930232809Sjmallett uint64_t reserved_54_63 : 10; 4931232809Sjmallett uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt-enable */ 4932232809Sjmallett uint64_t reserved_49_51 : 3; 4933232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupt-enable */ 4934232809Sjmallett uint64_t reserved_41_47 : 7; 4935232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */ 4936232809Sjmallett uint64_t reserved_33_39 : 7; 4937232809Sjmallett uint64_t agl : 1; /**< AGL interrupt-enable */ 4938232809Sjmallett uint64_t reserved_13_31 : 19; 4939232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */ 4940232809Sjmallett uint64_t reserved_5_7 : 3; 4941232809Sjmallett uint64_t agx : 5; /**< GMX interrupt-enable */ 4942232809Sjmallett#else 4943232809Sjmallett uint64_t agx : 5; 4944232809Sjmallett uint64_t reserved_5_7 : 3; 4945232809Sjmallett uint64_t gmx_drp : 5; 4946232809Sjmallett uint64_t reserved_13_31 : 19; 4947232809Sjmallett uint64_t agl : 1; 4948232809Sjmallett uint64_t reserved_33_39 : 7; 4949232809Sjmallett uint64_t mii : 1; 4950232809Sjmallett uint64_t reserved_41_47 : 7; 4951232809Sjmallett uint64_t ilk : 1; 4952232809Sjmallett uint64_t reserved_49_51 : 3; 4953232809Sjmallett uint64_t ilk_drp : 2; 4954232809Sjmallett uint64_t reserved_54_63 : 10; 4955232809Sjmallett#endif 4956232809Sjmallett } s; 4957232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_pkt_s cn68xx; 4958232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_pkt_cn68xxp1 { 4959232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4960232809Sjmallett uint64_t reserved_49_63 : 15; 4961232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupt-enable */ 4962232809Sjmallett uint64_t reserved_41_47 : 7; 4963232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */ 4964232809Sjmallett uint64_t reserved_33_39 : 7; 4965232809Sjmallett uint64_t agl : 1; /**< AGL interrupt-enable */ 4966232809Sjmallett uint64_t reserved_13_31 : 19; 4967232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */ 4968232809Sjmallett uint64_t reserved_5_7 : 3; 4969232809Sjmallett uint64_t agx : 5; /**< GMX interrupt-enable */ 4970232809Sjmallett#else 4971232809Sjmallett uint64_t agx : 5; 4972232809Sjmallett uint64_t reserved_5_7 : 3; 4973232809Sjmallett uint64_t gmx_drp : 5; 4974232809Sjmallett uint64_t reserved_13_31 : 19; 4975232809Sjmallett uint64_t agl : 1; 4976232809Sjmallett uint64_t reserved_33_39 : 7; 4977232809Sjmallett uint64_t mii : 1; 4978232809Sjmallett uint64_t reserved_41_47 : 7; 4979232809Sjmallett uint64_t ilk : 1; 4980232809Sjmallett uint64_t reserved_49_63 : 15; 4981232809Sjmallett#endif 4982232809Sjmallett } cn68xxp1; 4983232809Sjmallett}; 4984232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_pkt cvmx_ciu2_en_ppx_ip3_pkt_t; 4985232809Sjmallett 4986232809Sjmallett/** 4987232809Sjmallett * cvmx_ciu2_en_pp#_ip3_pkt_w1c 4988232809Sjmallett */ 4989232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_pkt_w1c { 4990232809Sjmallett uint64_t u64; 4991232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s { 4992232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4993232809Sjmallett uint64_t reserved_54_63 : 10; 4994232809Sjmallett uint64_t ilk_drp : 2; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK_DRP] */ 4995232809Sjmallett uint64_t reserved_49_51 : 3; 4996232809Sjmallett uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */ 4997232809Sjmallett uint64_t reserved_41_47 : 7; 4998232809Sjmallett uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */ 4999232809Sjmallett uint64_t reserved_33_39 : 7; 5000232809Sjmallett uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */ 5001232809Sjmallett uint64_t reserved_13_31 : 19; 5002232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */ 5003232809Sjmallett uint64_t reserved_5_7 : 3; 5004232809Sjmallett uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */ 5005232809Sjmallett#else 5006232809Sjmallett uint64_t agx : 5; 5007232809Sjmallett uint64_t reserved_5_7 : 3; 5008232809Sjmallett uint64_t gmx_drp : 5; 5009232809Sjmallett uint64_t reserved_13_31 : 19; 5010232809Sjmallett uint64_t agl : 1; 5011232809Sjmallett uint64_t reserved_33_39 : 7; 5012232809Sjmallett uint64_t mii : 1; 5013232809Sjmallett uint64_t reserved_41_47 : 7; 5014232809Sjmallett uint64_t ilk : 1; 5015232809Sjmallett uint64_t reserved_49_51 : 3; 5016232809Sjmallett uint64_t ilk_drp : 2; 5017232809Sjmallett uint64_t reserved_54_63 : 10; 5018232809Sjmallett#endif 5019232809Sjmallett } s; 5020232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s cn68xx; 5021232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_cn68xxp1 { 5022232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5023232809Sjmallett uint64_t reserved_49_63 : 15; 5024232809Sjmallett uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */ 5025232809Sjmallett uint64_t reserved_41_47 : 7; 5026232809Sjmallett uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */ 5027232809Sjmallett uint64_t reserved_33_39 : 7; 5028232809Sjmallett uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */ 5029232809Sjmallett uint64_t reserved_13_31 : 19; 5030232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */ 5031232809Sjmallett uint64_t reserved_5_7 : 3; 5032232809Sjmallett uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */ 5033232809Sjmallett#else 5034232809Sjmallett uint64_t agx : 5; 5035232809Sjmallett uint64_t reserved_5_7 : 3; 5036232809Sjmallett uint64_t gmx_drp : 5; 5037232809Sjmallett uint64_t reserved_13_31 : 19; 5038232809Sjmallett uint64_t agl : 1; 5039232809Sjmallett uint64_t reserved_33_39 : 7; 5040232809Sjmallett uint64_t mii : 1; 5041232809Sjmallett uint64_t reserved_41_47 : 7; 5042232809Sjmallett uint64_t ilk : 1; 5043232809Sjmallett uint64_t reserved_49_63 : 15; 5044232809Sjmallett#endif 5045232809Sjmallett } cn68xxp1; 5046232809Sjmallett}; 5047232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_pkt_w1c cvmx_ciu2_en_ppx_ip3_pkt_w1c_t; 5048232809Sjmallett 5049232809Sjmallett/** 5050232809Sjmallett * cvmx_ciu2_en_pp#_ip3_pkt_w1s 5051232809Sjmallett */ 5052232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_pkt_w1s { 5053232809Sjmallett uint64_t u64; 5054232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s { 5055232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5056232809Sjmallett uint64_t reserved_54_63 : 10; 5057232809Sjmallett uint64_t ilk_drp : 2; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK_DRP] */ 5058232809Sjmallett uint64_t reserved_49_51 : 3; 5059232809Sjmallett uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */ 5060232809Sjmallett uint64_t reserved_41_47 : 7; 5061232809Sjmallett uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */ 5062232809Sjmallett uint64_t reserved_33_39 : 7; 5063232809Sjmallett uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */ 5064232809Sjmallett uint64_t reserved_13_31 : 19; 5065232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */ 5066232809Sjmallett uint64_t reserved_5_7 : 3; 5067232809Sjmallett uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */ 5068232809Sjmallett#else 5069232809Sjmallett uint64_t agx : 5; 5070232809Sjmallett uint64_t reserved_5_7 : 3; 5071232809Sjmallett uint64_t gmx_drp : 5; 5072232809Sjmallett uint64_t reserved_13_31 : 19; 5073232809Sjmallett uint64_t agl : 1; 5074232809Sjmallett uint64_t reserved_33_39 : 7; 5075232809Sjmallett uint64_t mii : 1; 5076232809Sjmallett uint64_t reserved_41_47 : 7; 5077232809Sjmallett uint64_t ilk : 1; 5078232809Sjmallett uint64_t reserved_49_51 : 3; 5079232809Sjmallett uint64_t ilk_drp : 2; 5080232809Sjmallett uint64_t reserved_54_63 : 10; 5081232809Sjmallett#endif 5082232809Sjmallett } s; 5083232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s cn68xx; 5084232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_cn68xxp1 { 5085232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5086232809Sjmallett uint64_t reserved_49_63 : 15; 5087232809Sjmallett uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */ 5088232809Sjmallett uint64_t reserved_41_47 : 7; 5089232809Sjmallett uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */ 5090232809Sjmallett uint64_t reserved_33_39 : 7; 5091232809Sjmallett uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */ 5092232809Sjmallett uint64_t reserved_13_31 : 19; 5093232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */ 5094232809Sjmallett uint64_t reserved_5_7 : 3; 5095232809Sjmallett uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */ 5096232809Sjmallett#else 5097232809Sjmallett uint64_t agx : 5; 5098232809Sjmallett uint64_t reserved_5_7 : 3; 5099232809Sjmallett uint64_t gmx_drp : 5; 5100232809Sjmallett uint64_t reserved_13_31 : 19; 5101232809Sjmallett uint64_t agl : 1; 5102232809Sjmallett uint64_t reserved_33_39 : 7; 5103232809Sjmallett uint64_t mii : 1; 5104232809Sjmallett uint64_t reserved_41_47 : 7; 5105232809Sjmallett uint64_t ilk : 1; 5106232809Sjmallett uint64_t reserved_49_63 : 15; 5107232809Sjmallett#endif 5108232809Sjmallett } cn68xxp1; 5109232809Sjmallett}; 5110232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_pkt_w1s cvmx_ciu2_en_ppx_ip3_pkt_w1s_t; 5111232809Sjmallett 5112232809Sjmallett/** 5113232809Sjmallett * cvmx_ciu2_en_pp#_ip3_rml 5114232809Sjmallett */ 5115232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_rml { 5116232809Sjmallett uint64_t u64; 5117232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_rml_s { 5118232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5119232809Sjmallett uint64_t reserved_56_63 : 8; 5120232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt-enable */ 5121232809Sjmallett uint64_t reserved_49_51 : 3; 5122232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt-enable */ 5123232809Sjmallett uint64_t reserved_41_47 : 7; 5124232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt-enable */ 5125232809Sjmallett uint64_t reserved_37_39 : 3; 5126232809Sjmallett uint64_t dpi_dma : 1; /**< DPI DMA interrupt-enable */ 5127232809Sjmallett uint64_t reserved_34_35 : 2; 5128232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt-enable */ 5129232809Sjmallett uint64_t sli : 1; /**< SLI interrupt-enable */ 5130232809Sjmallett uint64_t reserved_31_31 : 1; 5131232809Sjmallett uint64_t key : 1; /**< KEY interrupt-enable */ 5132232809Sjmallett uint64_t rad : 1; /**< RAD interrupt-enable */ 5133232809Sjmallett uint64_t tim : 1; /**< TIM interrupt-enable */ 5134232809Sjmallett uint64_t reserved_25_27 : 3; 5135232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt-enable */ 5136232809Sjmallett uint64_t reserved_17_23 : 7; 5137232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt-enable */ 5138232809Sjmallett uint64_t reserved_8_15 : 8; 5139232809Sjmallett uint64_t pko : 1; /**< PKO interrupt-enable */ 5140232809Sjmallett uint64_t pip : 1; /**< PIP interrupt-enable */ 5141232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt-enable */ 5142232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt-enable */ 5143232809Sjmallett uint64_t reserved_1_3 : 3; 5144232809Sjmallett uint64_t iob : 1; /**< IOB interrupt-enable */ 5145232809Sjmallett#else 5146232809Sjmallett uint64_t iob : 1; 5147232809Sjmallett uint64_t reserved_1_3 : 3; 5148232809Sjmallett uint64_t fpa : 1; 5149232809Sjmallett uint64_t ipd : 1; 5150232809Sjmallett uint64_t pip : 1; 5151232809Sjmallett uint64_t pko : 1; 5152232809Sjmallett uint64_t reserved_8_15 : 8; 5153232809Sjmallett uint64_t sso : 1; 5154232809Sjmallett uint64_t reserved_17_23 : 7; 5155232809Sjmallett uint64_t zip : 1; 5156232809Sjmallett uint64_t reserved_25_27 : 3; 5157232809Sjmallett uint64_t tim : 1; 5158232809Sjmallett uint64_t rad : 1; 5159232809Sjmallett uint64_t key : 1; 5160232809Sjmallett uint64_t reserved_31_31 : 1; 5161232809Sjmallett uint64_t sli : 1; 5162232809Sjmallett uint64_t dpi : 1; 5163232809Sjmallett uint64_t reserved_34_35 : 2; 5164232809Sjmallett uint64_t dpi_dma : 1; 5165232809Sjmallett uint64_t reserved_37_39 : 3; 5166232809Sjmallett uint64_t dfa : 1; 5167232809Sjmallett uint64_t reserved_41_47 : 7; 5168232809Sjmallett uint64_t l2c : 1; 5169232809Sjmallett uint64_t reserved_49_51 : 3; 5170232809Sjmallett uint64_t trace : 4; 5171232809Sjmallett uint64_t reserved_56_63 : 8; 5172232809Sjmallett#endif 5173232809Sjmallett } s; 5174232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_rml_s cn68xx; 5175232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_rml_cn68xxp1 { 5176232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5177232809Sjmallett uint64_t reserved_56_63 : 8; 5178232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt-enable */ 5179232809Sjmallett uint64_t reserved_49_51 : 3; 5180232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt-enable */ 5181232809Sjmallett uint64_t reserved_41_47 : 7; 5182232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt-enable */ 5183232809Sjmallett uint64_t reserved_34_39 : 6; 5184232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt-enable */ 5185232809Sjmallett uint64_t sli : 1; /**< SLI interrupt-enable */ 5186232809Sjmallett uint64_t reserved_31_31 : 1; 5187232809Sjmallett uint64_t key : 1; /**< KEY interrupt-enable */ 5188232809Sjmallett uint64_t rad : 1; /**< RAD interrupt-enable */ 5189232809Sjmallett uint64_t tim : 1; /**< TIM interrupt-enable */ 5190232809Sjmallett uint64_t reserved_25_27 : 3; 5191232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt-enable */ 5192232809Sjmallett uint64_t reserved_17_23 : 7; 5193232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt-enable */ 5194232809Sjmallett uint64_t reserved_8_15 : 8; 5195232809Sjmallett uint64_t pko : 1; /**< PKO interrupt-enable */ 5196232809Sjmallett uint64_t pip : 1; /**< PIP interrupt-enable */ 5197232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt-enable */ 5198232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt-enable */ 5199232809Sjmallett uint64_t reserved_1_3 : 3; 5200232809Sjmallett uint64_t iob : 1; /**< IOB interrupt-enable */ 5201232809Sjmallett#else 5202232809Sjmallett uint64_t iob : 1; 5203232809Sjmallett uint64_t reserved_1_3 : 3; 5204232809Sjmallett uint64_t fpa : 1; 5205232809Sjmallett uint64_t ipd : 1; 5206232809Sjmallett uint64_t pip : 1; 5207232809Sjmallett uint64_t pko : 1; 5208232809Sjmallett uint64_t reserved_8_15 : 8; 5209232809Sjmallett uint64_t sso : 1; 5210232809Sjmallett uint64_t reserved_17_23 : 7; 5211232809Sjmallett uint64_t zip : 1; 5212232809Sjmallett uint64_t reserved_25_27 : 3; 5213232809Sjmallett uint64_t tim : 1; 5214232809Sjmallett uint64_t rad : 1; 5215232809Sjmallett uint64_t key : 1; 5216232809Sjmallett uint64_t reserved_31_31 : 1; 5217232809Sjmallett uint64_t sli : 1; 5218232809Sjmallett uint64_t dpi : 1; 5219232809Sjmallett uint64_t reserved_34_39 : 6; 5220232809Sjmallett uint64_t dfa : 1; 5221232809Sjmallett uint64_t reserved_41_47 : 7; 5222232809Sjmallett uint64_t l2c : 1; 5223232809Sjmallett uint64_t reserved_49_51 : 3; 5224232809Sjmallett uint64_t trace : 4; 5225232809Sjmallett uint64_t reserved_56_63 : 8; 5226232809Sjmallett#endif 5227232809Sjmallett } cn68xxp1; 5228232809Sjmallett}; 5229232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_rml cvmx_ciu2_en_ppx_ip3_rml_t; 5230232809Sjmallett 5231232809Sjmallett/** 5232232809Sjmallett * cvmx_ciu2_en_pp#_ip3_rml_w1c 5233232809Sjmallett */ 5234232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_rml_w1c { 5235232809Sjmallett uint64_t u64; 5236232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s { 5237232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5238232809Sjmallett uint64_t reserved_56_63 : 8; 5239232809Sjmallett uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */ 5240232809Sjmallett uint64_t reserved_49_51 : 3; 5241232809Sjmallett uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */ 5242232809Sjmallett uint64_t reserved_41_47 : 7; 5243232809Sjmallett uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */ 5244232809Sjmallett uint64_t reserved_37_39 : 3; 5245232809Sjmallett uint64_t dpi_dma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI_DMA] */ 5246232809Sjmallett uint64_t reserved_34_35 : 2; 5247232809Sjmallett uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */ 5248232809Sjmallett uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */ 5249232809Sjmallett uint64_t reserved_31_31 : 1; 5250232809Sjmallett uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */ 5251232809Sjmallett uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */ 5252232809Sjmallett uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */ 5253232809Sjmallett uint64_t reserved_25_27 : 3; 5254232809Sjmallett uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */ 5255232809Sjmallett uint64_t reserved_17_23 : 7; 5256232809Sjmallett uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */ 5257232809Sjmallett uint64_t reserved_8_15 : 8; 5258232809Sjmallett uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */ 5259232809Sjmallett uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */ 5260232809Sjmallett uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */ 5261232809Sjmallett uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */ 5262232809Sjmallett uint64_t reserved_1_3 : 3; 5263232809Sjmallett uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */ 5264232809Sjmallett#else 5265232809Sjmallett uint64_t iob : 1; 5266232809Sjmallett uint64_t reserved_1_3 : 3; 5267232809Sjmallett uint64_t fpa : 1; 5268232809Sjmallett uint64_t ipd : 1; 5269232809Sjmallett uint64_t pip : 1; 5270232809Sjmallett uint64_t pko : 1; 5271232809Sjmallett uint64_t reserved_8_15 : 8; 5272232809Sjmallett uint64_t sso : 1; 5273232809Sjmallett uint64_t reserved_17_23 : 7; 5274232809Sjmallett uint64_t zip : 1; 5275232809Sjmallett uint64_t reserved_25_27 : 3; 5276232809Sjmallett uint64_t tim : 1; 5277232809Sjmallett uint64_t rad : 1; 5278232809Sjmallett uint64_t key : 1; 5279232809Sjmallett uint64_t reserved_31_31 : 1; 5280232809Sjmallett uint64_t sli : 1; 5281232809Sjmallett uint64_t dpi : 1; 5282232809Sjmallett uint64_t reserved_34_35 : 2; 5283232809Sjmallett uint64_t dpi_dma : 1; 5284232809Sjmallett uint64_t reserved_37_39 : 3; 5285232809Sjmallett uint64_t dfa : 1; 5286232809Sjmallett uint64_t reserved_41_47 : 7; 5287232809Sjmallett uint64_t l2c : 1; 5288232809Sjmallett uint64_t reserved_49_51 : 3; 5289232809Sjmallett uint64_t trace : 4; 5290232809Sjmallett uint64_t reserved_56_63 : 8; 5291232809Sjmallett#endif 5292232809Sjmallett } s; 5293232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s cn68xx; 5294232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_rml_w1c_cn68xxp1 { 5295232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5296232809Sjmallett uint64_t reserved_56_63 : 8; 5297232809Sjmallett uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */ 5298232809Sjmallett uint64_t reserved_49_51 : 3; 5299232809Sjmallett uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */ 5300232809Sjmallett uint64_t reserved_41_47 : 7; 5301232809Sjmallett uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */ 5302232809Sjmallett uint64_t reserved_34_39 : 6; 5303232809Sjmallett uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */ 5304232809Sjmallett uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */ 5305232809Sjmallett uint64_t reserved_31_31 : 1; 5306232809Sjmallett uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */ 5307232809Sjmallett uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */ 5308232809Sjmallett uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */ 5309232809Sjmallett uint64_t reserved_25_27 : 3; 5310232809Sjmallett uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */ 5311232809Sjmallett uint64_t reserved_17_23 : 7; 5312232809Sjmallett uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */ 5313232809Sjmallett uint64_t reserved_8_15 : 8; 5314232809Sjmallett uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */ 5315232809Sjmallett uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */ 5316232809Sjmallett uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */ 5317232809Sjmallett uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */ 5318232809Sjmallett uint64_t reserved_1_3 : 3; 5319232809Sjmallett uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */ 5320232809Sjmallett#else 5321232809Sjmallett uint64_t iob : 1; 5322232809Sjmallett uint64_t reserved_1_3 : 3; 5323232809Sjmallett uint64_t fpa : 1; 5324232809Sjmallett uint64_t ipd : 1; 5325232809Sjmallett uint64_t pip : 1; 5326232809Sjmallett uint64_t pko : 1; 5327232809Sjmallett uint64_t reserved_8_15 : 8; 5328232809Sjmallett uint64_t sso : 1; 5329232809Sjmallett uint64_t reserved_17_23 : 7; 5330232809Sjmallett uint64_t zip : 1; 5331232809Sjmallett uint64_t reserved_25_27 : 3; 5332232809Sjmallett uint64_t tim : 1; 5333232809Sjmallett uint64_t rad : 1; 5334232809Sjmallett uint64_t key : 1; 5335232809Sjmallett uint64_t reserved_31_31 : 1; 5336232809Sjmallett uint64_t sli : 1; 5337232809Sjmallett uint64_t dpi : 1; 5338232809Sjmallett uint64_t reserved_34_39 : 6; 5339232809Sjmallett uint64_t dfa : 1; 5340232809Sjmallett uint64_t reserved_41_47 : 7; 5341232809Sjmallett uint64_t l2c : 1; 5342232809Sjmallett uint64_t reserved_49_51 : 3; 5343232809Sjmallett uint64_t trace : 4; 5344232809Sjmallett uint64_t reserved_56_63 : 8; 5345232809Sjmallett#endif 5346232809Sjmallett } cn68xxp1; 5347232809Sjmallett}; 5348232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_rml_w1c cvmx_ciu2_en_ppx_ip3_rml_w1c_t; 5349232809Sjmallett 5350232809Sjmallett/** 5351232809Sjmallett * cvmx_ciu2_en_pp#_ip3_rml_w1s 5352232809Sjmallett */ 5353232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_rml_w1s { 5354232809Sjmallett uint64_t u64; 5355232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s { 5356232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5357232809Sjmallett uint64_t reserved_56_63 : 8; 5358232809Sjmallett uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */ 5359232809Sjmallett uint64_t reserved_49_51 : 3; 5360232809Sjmallett uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */ 5361232809Sjmallett uint64_t reserved_41_47 : 7; 5362232809Sjmallett uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */ 5363232809Sjmallett uint64_t reserved_37_39 : 3; 5364232809Sjmallett uint64_t dpi_dma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI_DMA] */ 5365232809Sjmallett uint64_t reserved_34_35 : 2; 5366232809Sjmallett uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */ 5367232809Sjmallett uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */ 5368232809Sjmallett uint64_t reserved_31_31 : 1; 5369232809Sjmallett uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */ 5370232809Sjmallett uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */ 5371232809Sjmallett uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */ 5372232809Sjmallett uint64_t reserved_25_27 : 3; 5373232809Sjmallett uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */ 5374232809Sjmallett uint64_t reserved_17_23 : 7; 5375232809Sjmallett uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */ 5376232809Sjmallett uint64_t reserved_8_15 : 8; 5377232809Sjmallett uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */ 5378232809Sjmallett uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */ 5379232809Sjmallett uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */ 5380232809Sjmallett uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */ 5381232809Sjmallett uint64_t reserved_1_3 : 3; 5382232809Sjmallett uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */ 5383232809Sjmallett#else 5384232809Sjmallett uint64_t iob : 1; 5385232809Sjmallett uint64_t reserved_1_3 : 3; 5386232809Sjmallett uint64_t fpa : 1; 5387232809Sjmallett uint64_t ipd : 1; 5388232809Sjmallett uint64_t pip : 1; 5389232809Sjmallett uint64_t pko : 1; 5390232809Sjmallett uint64_t reserved_8_15 : 8; 5391232809Sjmallett uint64_t sso : 1; 5392232809Sjmallett uint64_t reserved_17_23 : 7; 5393232809Sjmallett uint64_t zip : 1; 5394232809Sjmallett uint64_t reserved_25_27 : 3; 5395232809Sjmallett uint64_t tim : 1; 5396232809Sjmallett uint64_t rad : 1; 5397232809Sjmallett uint64_t key : 1; 5398232809Sjmallett uint64_t reserved_31_31 : 1; 5399232809Sjmallett uint64_t sli : 1; 5400232809Sjmallett uint64_t dpi : 1; 5401232809Sjmallett uint64_t reserved_34_35 : 2; 5402232809Sjmallett uint64_t dpi_dma : 1; 5403232809Sjmallett uint64_t reserved_37_39 : 3; 5404232809Sjmallett uint64_t dfa : 1; 5405232809Sjmallett uint64_t reserved_41_47 : 7; 5406232809Sjmallett uint64_t l2c : 1; 5407232809Sjmallett uint64_t reserved_49_51 : 3; 5408232809Sjmallett uint64_t trace : 4; 5409232809Sjmallett uint64_t reserved_56_63 : 8; 5410232809Sjmallett#endif 5411232809Sjmallett } s; 5412232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s cn68xx; 5413232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_rml_w1s_cn68xxp1 { 5414232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5415232809Sjmallett uint64_t reserved_56_63 : 8; 5416232809Sjmallett uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */ 5417232809Sjmallett uint64_t reserved_49_51 : 3; 5418232809Sjmallett uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */ 5419232809Sjmallett uint64_t reserved_41_47 : 7; 5420232809Sjmallett uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */ 5421232809Sjmallett uint64_t reserved_34_39 : 6; 5422232809Sjmallett uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */ 5423232809Sjmallett uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */ 5424232809Sjmallett uint64_t reserved_31_31 : 1; 5425232809Sjmallett uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */ 5426232809Sjmallett uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */ 5427232809Sjmallett uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */ 5428232809Sjmallett uint64_t reserved_25_27 : 3; 5429232809Sjmallett uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */ 5430232809Sjmallett uint64_t reserved_17_23 : 7; 5431232809Sjmallett uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */ 5432232809Sjmallett uint64_t reserved_8_15 : 8; 5433232809Sjmallett uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */ 5434232809Sjmallett uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */ 5435232809Sjmallett uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */ 5436232809Sjmallett uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */ 5437232809Sjmallett uint64_t reserved_1_3 : 3; 5438232809Sjmallett uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */ 5439232809Sjmallett#else 5440232809Sjmallett uint64_t iob : 1; 5441232809Sjmallett uint64_t reserved_1_3 : 3; 5442232809Sjmallett uint64_t fpa : 1; 5443232809Sjmallett uint64_t ipd : 1; 5444232809Sjmallett uint64_t pip : 1; 5445232809Sjmallett uint64_t pko : 1; 5446232809Sjmallett uint64_t reserved_8_15 : 8; 5447232809Sjmallett uint64_t sso : 1; 5448232809Sjmallett uint64_t reserved_17_23 : 7; 5449232809Sjmallett uint64_t zip : 1; 5450232809Sjmallett uint64_t reserved_25_27 : 3; 5451232809Sjmallett uint64_t tim : 1; 5452232809Sjmallett uint64_t rad : 1; 5453232809Sjmallett uint64_t key : 1; 5454232809Sjmallett uint64_t reserved_31_31 : 1; 5455232809Sjmallett uint64_t sli : 1; 5456232809Sjmallett uint64_t dpi : 1; 5457232809Sjmallett uint64_t reserved_34_39 : 6; 5458232809Sjmallett uint64_t dfa : 1; 5459232809Sjmallett uint64_t reserved_41_47 : 7; 5460232809Sjmallett uint64_t l2c : 1; 5461232809Sjmallett uint64_t reserved_49_51 : 3; 5462232809Sjmallett uint64_t trace : 4; 5463232809Sjmallett uint64_t reserved_56_63 : 8; 5464232809Sjmallett#endif 5465232809Sjmallett } cn68xxp1; 5466232809Sjmallett}; 5467232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_rml_w1s cvmx_ciu2_en_ppx_ip3_rml_w1s_t; 5468232809Sjmallett 5469232809Sjmallett/** 5470232809Sjmallett * cvmx_ciu2_en_pp#_ip3_wdog 5471232809Sjmallett */ 5472232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_wdog { 5473232809Sjmallett uint64_t u64; 5474232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wdog_s { 5475232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5476232809Sjmallett uint64_t reserved_32_63 : 32; 5477232809Sjmallett uint64_t wdog : 32; /**< 32 watchdog interrupt-enable */ 5478232809Sjmallett#else 5479232809Sjmallett uint64_t wdog : 32; 5480232809Sjmallett uint64_t reserved_32_63 : 32; 5481232809Sjmallett#endif 5482232809Sjmallett } s; 5483232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xx; 5484232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xxp1; 5485232809Sjmallett}; 5486232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_wdog cvmx_ciu2_en_ppx_ip3_wdog_t; 5487232809Sjmallett 5488232809Sjmallett/** 5489232809Sjmallett * cvmx_ciu2_en_pp#_ip3_wdog_w1c 5490232809Sjmallett */ 5491232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_wdog_w1c { 5492232809Sjmallett uint64_t u64; 5493232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s { 5494232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5495232809Sjmallett uint64_t reserved_32_63 : 32; 5496232809Sjmallett uint64_t wdog : 32; /**< write 1 to clear CIU2_EN_xx_yy_WDOG */ 5497232809Sjmallett#else 5498232809Sjmallett uint64_t wdog : 32; 5499232809Sjmallett uint64_t reserved_32_63 : 32; 5500232809Sjmallett#endif 5501232809Sjmallett } s; 5502232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xx; 5503232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xxp1; 5504232809Sjmallett}; 5505232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_wdog_w1c cvmx_ciu2_en_ppx_ip3_wdog_w1c_t; 5506232809Sjmallett 5507232809Sjmallett/** 5508232809Sjmallett * cvmx_ciu2_en_pp#_ip3_wdog_w1s 5509232809Sjmallett */ 5510232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_wdog_w1s { 5511232809Sjmallett uint64_t u64; 5512232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s { 5513232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5514232809Sjmallett uint64_t reserved_32_63 : 32; 5515232809Sjmallett uint64_t wdog : 32; /**< Write 1 to enable CIU2_EN_xx_yy_WDOG[WDOG] */ 5516232809Sjmallett#else 5517232809Sjmallett uint64_t wdog : 32; 5518232809Sjmallett uint64_t reserved_32_63 : 32; 5519232809Sjmallett#endif 5520232809Sjmallett } s; 5521232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xx; 5522232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xxp1; 5523232809Sjmallett}; 5524232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_wdog_w1s cvmx_ciu2_en_ppx_ip3_wdog_w1s_t; 5525232809Sjmallett 5526232809Sjmallett/** 5527232809Sjmallett * cvmx_ciu2_en_pp#_ip3_wrkq 5528232809Sjmallett */ 5529232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_wrkq { 5530232809Sjmallett uint64_t u64; 5531232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wrkq_s { 5532232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5533232809Sjmallett uint64_t workq : 64; /**< 64 work queue interrupt-enable */ 5534232809Sjmallett#else 5535232809Sjmallett uint64_t workq : 64; 5536232809Sjmallett#endif 5537232809Sjmallett } s; 5538232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xx; 5539232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xxp1; 5540232809Sjmallett}; 5541232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_wrkq cvmx_ciu2_en_ppx_ip3_wrkq_t; 5542232809Sjmallett 5543232809Sjmallett/** 5544232809Sjmallett * cvmx_ciu2_en_pp#_ip3_wrkq_w1c 5545232809Sjmallett */ 5546232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_wrkq_w1c { 5547232809Sjmallett uint64_t u64; 5548232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s { 5549232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5550232809Sjmallett uint64_t workq : 64; /**< Write 1 to clear CIU2_EN_xx_yy_WRKQ[WORKQ] 5551232809Sjmallett For W1C bits, write 1 to clear the corresponding 5552232809Sjmallett CIU2_EN_xx_yy_WRKQ,write 0 to retain previous value */ 5553232809Sjmallett#else 5554232809Sjmallett uint64_t workq : 64; 5555232809Sjmallett#endif 5556232809Sjmallett } s; 5557232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xx; 5558232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xxp1; 5559232809Sjmallett}; 5560232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_wrkq_w1c cvmx_ciu2_en_ppx_ip3_wrkq_w1c_t; 5561232809Sjmallett 5562232809Sjmallett/** 5563232809Sjmallett * cvmx_ciu2_en_pp#_ip3_wrkq_w1s 5564232809Sjmallett */ 5565232809Sjmallettunion cvmx_ciu2_en_ppx_ip3_wrkq_w1s { 5566232809Sjmallett uint64_t u64; 5567232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s { 5568232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5569232809Sjmallett uint64_t workq : 64; /**< Write 1 to enable CIU2_EN_xx_yy_WRKQ[WORKQ] 5570232809Sjmallett 1 bit/group. For all W1S bits, write 1 to enable 5571232809Sjmallett corresponding CIU2_EN_xx_yy_WRKQ[WORKQ] bit, 5572232809Sjmallett writing 0 to retain previous value. */ 5573232809Sjmallett#else 5574232809Sjmallett uint64_t workq : 64; 5575232809Sjmallett#endif 5576232809Sjmallett } s; 5577232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xx; 5578232809Sjmallett struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xxp1; 5579232809Sjmallett}; 5580232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip3_wrkq_w1s cvmx_ciu2_en_ppx_ip3_wrkq_w1s_t; 5581232809Sjmallett 5582232809Sjmallett/** 5583232809Sjmallett * cvmx_ciu2_en_pp#_ip4_gpio 5584232809Sjmallett */ 5585232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_gpio { 5586232809Sjmallett uint64_t u64; 5587232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_gpio_s { 5588232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5589232809Sjmallett uint64_t reserved_16_63 : 48; 5590232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupt-enable */ 5591232809Sjmallett#else 5592232809Sjmallett uint64_t gpio : 16; 5593232809Sjmallett uint64_t reserved_16_63 : 48; 5594232809Sjmallett#endif 5595232809Sjmallett } s; 5596232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xx; 5597232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xxp1; 5598232809Sjmallett}; 5599232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_gpio cvmx_ciu2_en_ppx_ip4_gpio_t; 5600232809Sjmallett 5601232809Sjmallett/** 5602232809Sjmallett * cvmx_ciu2_en_pp#_ip4_gpio_w1c 5603232809Sjmallett */ 5604232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_gpio_w1c { 5605232809Sjmallett uint64_t u64; 5606232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s { 5607232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5608232809Sjmallett uint64_t reserved_16_63 : 48; 5609232809Sjmallett uint64_t gpio : 16; /**< Write 1 to clear CIU2_EN_xx_yy_GPIO[GPIO] */ 5610232809Sjmallett#else 5611232809Sjmallett uint64_t gpio : 16; 5612232809Sjmallett uint64_t reserved_16_63 : 48; 5613232809Sjmallett#endif 5614232809Sjmallett } s; 5615232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xx; 5616232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xxp1; 5617232809Sjmallett}; 5618232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_gpio_w1c cvmx_ciu2_en_ppx_ip4_gpio_w1c_t; 5619232809Sjmallett 5620232809Sjmallett/** 5621232809Sjmallett * cvmx_ciu2_en_pp#_ip4_gpio_w1s 5622232809Sjmallett */ 5623232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_gpio_w1s { 5624232809Sjmallett uint64_t u64; 5625232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s { 5626232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5627232809Sjmallett uint64_t reserved_16_63 : 48; 5628232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupt enable,write 1 to enable CIU2_EN */ 5629232809Sjmallett#else 5630232809Sjmallett uint64_t gpio : 16; 5631232809Sjmallett uint64_t reserved_16_63 : 48; 5632232809Sjmallett#endif 5633232809Sjmallett } s; 5634232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xx; 5635232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xxp1; 5636232809Sjmallett}; 5637232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_gpio_w1s cvmx_ciu2_en_ppx_ip4_gpio_w1s_t; 5638232809Sjmallett 5639232809Sjmallett/** 5640232809Sjmallett * cvmx_ciu2_en_pp#_ip4_io 5641232809Sjmallett */ 5642232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_io { 5643232809Sjmallett uint64_t u64; 5644232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_io_s { 5645232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5646232809Sjmallett uint64_t reserved_34_63 : 30; 5647232809Sjmallett uint64_t pem : 2; /**< PEMx interrupt-enable */ 5648232809Sjmallett uint64_t reserved_18_31 : 14; 5649232809Sjmallett uint64_t pci_inta : 2; /**< PCI_INTA interrupt-enable */ 5650232809Sjmallett uint64_t reserved_13_15 : 3; 5651232809Sjmallett uint64_t msired : 1; /**< MSI summary bit interrupt-enable 5652232809Sjmallett This bit may not be functional in pass 1. */ 5653232809Sjmallett uint64_t pci_msi : 4; /**< PCIe/sRIO MSI interrupt-enable */ 5654232809Sjmallett uint64_t reserved_4_7 : 4; 5655232809Sjmallett uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt-enable */ 5656232809Sjmallett#else 5657232809Sjmallett uint64_t pci_intr : 4; 5658232809Sjmallett uint64_t reserved_4_7 : 4; 5659232809Sjmallett uint64_t pci_msi : 4; 5660232809Sjmallett uint64_t msired : 1; 5661232809Sjmallett uint64_t reserved_13_15 : 3; 5662232809Sjmallett uint64_t pci_inta : 2; 5663232809Sjmallett uint64_t reserved_18_31 : 14; 5664232809Sjmallett uint64_t pem : 2; 5665232809Sjmallett uint64_t reserved_34_63 : 30; 5666232809Sjmallett#endif 5667232809Sjmallett } s; 5668232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_io_s cn68xx; 5669232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_io_s cn68xxp1; 5670232809Sjmallett}; 5671232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_io cvmx_ciu2_en_ppx_ip4_io_t; 5672232809Sjmallett 5673232809Sjmallett/** 5674232809Sjmallett * cvmx_ciu2_en_pp#_ip4_io_w1c 5675232809Sjmallett */ 5676232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_io_w1c { 5677232809Sjmallett uint64_t u64; 5678232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_io_w1c_s { 5679232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5680232809Sjmallett uint64_t reserved_34_63 : 30; 5681232809Sjmallett uint64_t pem : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PEM] */ 5682232809Sjmallett uint64_t reserved_18_31 : 14; 5683232809Sjmallett uint64_t pci_inta : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTA] */ 5684232809Sjmallett uint64_t reserved_13_15 : 3; 5685232809Sjmallett uint64_t msired : 1; /**< Write 1 to clear CIU2_EN_xx_yy_IO[MSIRED] 5686232809Sjmallett This bit may not be functional in pass 1. */ 5687232809Sjmallett uint64_t pci_msi : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_MSI] */ 5688232809Sjmallett uint64_t reserved_4_7 : 4; 5689232809Sjmallett uint64_t pci_intr : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTR] */ 5690232809Sjmallett#else 5691232809Sjmallett uint64_t pci_intr : 4; 5692232809Sjmallett uint64_t reserved_4_7 : 4; 5693232809Sjmallett uint64_t pci_msi : 4; 5694232809Sjmallett uint64_t msired : 1; 5695232809Sjmallett uint64_t reserved_13_15 : 3; 5696232809Sjmallett uint64_t pci_inta : 2; 5697232809Sjmallett uint64_t reserved_18_31 : 14; 5698232809Sjmallett uint64_t pem : 2; 5699232809Sjmallett uint64_t reserved_34_63 : 30; 5700232809Sjmallett#endif 5701232809Sjmallett } s; 5702232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xx; 5703232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xxp1; 5704232809Sjmallett}; 5705232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_io_w1c cvmx_ciu2_en_ppx_ip4_io_w1c_t; 5706232809Sjmallett 5707232809Sjmallett/** 5708232809Sjmallett * cvmx_ciu2_en_pp#_ip4_io_w1s 5709232809Sjmallett */ 5710232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_io_w1s { 5711232809Sjmallett uint64_t u64; 5712232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_io_w1s_s { 5713232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5714232809Sjmallett uint64_t reserved_34_63 : 30; 5715232809Sjmallett uint64_t pem : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PEM] */ 5716232809Sjmallett uint64_t reserved_18_31 : 14; 5717232809Sjmallett uint64_t pci_inta : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTA] */ 5718232809Sjmallett uint64_t reserved_13_15 : 3; 5719232809Sjmallett uint64_t msired : 1; /**< Write 1 to enable CIU2_EN_xx_yy_IO[MSIRED] 5720232809Sjmallett This bit may not be functional in pass 1. */ 5721232809Sjmallett uint64_t pci_msi : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_MSI] */ 5722232809Sjmallett uint64_t reserved_4_7 : 4; 5723232809Sjmallett uint64_t pci_intr : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTR] */ 5724232809Sjmallett#else 5725232809Sjmallett uint64_t pci_intr : 4; 5726232809Sjmallett uint64_t reserved_4_7 : 4; 5727232809Sjmallett uint64_t pci_msi : 4; 5728232809Sjmallett uint64_t msired : 1; 5729232809Sjmallett uint64_t reserved_13_15 : 3; 5730232809Sjmallett uint64_t pci_inta : 2; 5731232809Sjmallett uint64_t reserved_18_31 : 14; 5732232809Sjmallett uint64_t pem : 2; 5733232809Sjmallett uint64_t reserved_34_63 : 30; 5734232809Sjmallett#endif 5735232809Sjmallett } s; 5736232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xx; 5737232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xxp1; 5738232809Sjmallett}; 5739232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_io_w1s cvmx_ciu2_en_ppx_ip4_io_w1s_t; 5740232809Sjmallett 5741232809Sjmallett/** 5742232809Sjmallett * cvmx_ciu2_en_pp#_ip4_mbox 5743232809Sjmallett */ 5744232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_mbox { 5745232809Sjmallett uint64_t u64; 5746232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mbox_s { 5747232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5748232809Sjmallett uint64_t reserved_4_63 : 60; 5749232809Sjmallett uint64_t mbox : 4; /**< Mailbox interrupt-enable, use with CIU2_MBOX 5750232809Sjmallett to generate CIU2_SRC_xx_yy_MBOX */ 5751232809Sjmallett#else 5752232809Sjmallett uint64_t mbox : 4; 5753232809Sjmallett uint64_t reserved_4_63 : 60; 5754232809Sjmallett#endif 5755232809Sjmallett } s; 5756232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xx; 5757232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xxp1; 5758232809Sjmallett}; 5759232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_mbox cvmx_ciu2_en_ppx_ip4_mbox_t; 5760232809Sjmallett 5761232809Sjmallett/** 5762232809Sjmallett * cvmx_ciu2_en_pp#_ip4_mbox_w1c 5763232809Sjmallett */ 5764232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_mbox_w1c { 5765232809Sjmallett uint64_t u64; 5766232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s { 5767232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5768232809Sjmallett uint64_t reserved_4_63 : 60; 5769232809Sjmallett uint64_t mbox : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MBOX[MBOX] */ 5770232809Sjmallett#else 5771232809Sjmallett uint64_t mbox : 4; 5772232809Sjmallett uint64_t reserved_4_63 : 60; 5773232809Sjmallett#endif 5774232809Sjmallett } s; 5775232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xx; 5776232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xxp1; 5777232809Sjmallett}; 5778232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_mbox_w1c cvmx_ciu2_en_ppx_ip4_mbox_w1c_t; 5779232809Sjmallett 5780232809Sjmallett/** 5781232809Sjmallett * cvmx_ciu2_en_pp#_ip4_mbox_w1s 5782232809Sjmallett */ 5783232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_mbox_w1s { 5784232809Sjmallett uint64_t u64; 5785232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s { 5786232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5787232809Sjmallett uint64_t reserved_4_63 : 60; 5788232809Sjmallett uint64_t mbox : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MBOX[MBOX] */ 5789232809Sjmallett#else 5790232809Sjmallett uint64_t mbox : 4; 5791232809Sjmallett uint64_t reserved_4_63 : 60; 5792232809Sjmallett#endif 5793232809Sjmallett } s; 5794232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xx; 5795232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xxp1; 5796232809Sjmallett}; 5797232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_mbox_w1s cvmx_ciu2_en_ppx_ip4_mbox_w1s_t; 5798232809Sjmallett 5799232809Sjmallett/** 5800232809Sjmallett * cvmx_ciu2_en_pp#_ip4_mem 5801232809Sjmallett */ 5802232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_mem { 5803232809Sjmallett uint64_t u64; 5804232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mem_s { 5805232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5806232809Sjmallett uint64_t reserved_4_63 : 60; 5807232809Sjmallett uint64_t lmc : 4; /**< LMC* interrupt-enable */ 5808232809Sjmallett#else 5809232809Sjmallett uint64_t lmc : 4; 5810232809Sjmallett uint64_t reserved_4_63 : 60; 5811232809Sjmallett#endif 5812232809Sjmallett } s; 5813232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xx; 5814232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xxp1; 5815232809Sjmallett}; 5816232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_mem cvmx_ciu2_en_ppx_ip4_mem_t; 5817232809Sjmallett 5818232809Sjmallett/** 5819232809Sjmallett * cvmx_ciu2_en_pp#_ip4_mem_w1c 5820232809Sjmallett */ 5821232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_mem_w1c { 5822232809Sjmallett uint64_t u64; 5823232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s { 5824232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5825232809Sjmallett uint64_t reserved_4_63 : 60; 5826232809Sjmallett uint64_t lmc : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MEM[LMC] */ 5827232809Sjmallett#else 5828232809Sjmallett uint64_t lmc : 4; 5829232809Sjmallett uint64_t reserved_4_63 : 60; 5830232809Sjmallett#endif 5831232809Sjmallett } s; 5832232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xx; 5833232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xxp1; 5834232809Sjmallett}; 5835232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_mem_w1c cvmx_ciu2_en_ppx_ip4_mem_w1c_t; 5836232809Sjmallett 5837232809Sjmallett/** 5838232809Sjmallett * cvmx_ciu2_en_pp#_ip4_mem_w1s 5839232809Sjmallett */ 5840232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_mem_w1s { 5841232809Sjmallett uint64_t u64; 5842232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s { 5843232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5844232809Sjmallett uint64_t reserved_4_63 : 60; 5845232809Sjmallett uint64_t lmc : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MEM[LMC] */ 5846232809Sjmallett#else 5847232809Sjmallett uint64_t lmc : 4; 5848232809Sjmallett uint64_t reserved_4_63 : 60; 5849232809Sjmallett#endif 5850232809Sjmallett } s; 5851232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xx; 5852232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xxp1; 5853232809Sjmallett}; 5854232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_mem_w1s cvmx_ciu2_en_ppx_ip4_mem_w1s_t; 5855232809Sjmallett 5856232809Sjmallett/** 5857232809Sjmallett * cvmx_ciu2_en_pp#_ip4_mio 5858232809Sjmallett */ 5859232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_mio { 5860232809Sjmallett uint64_t u64; 5861232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mio_s { 5862232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5863232809Sjmallett uint64_t rst : 1; /**< MIO RST interrupt-enable */ 5864232809Sjmallett uint64_t reserved_49_62 : 14; 5865232809Sjmallett uint64_t ptp : 1; /**< PTP interrupt-enable */ 5866232809Sjmallett uint64_t reserved_45_47 : 3; 5867232809Sjmallett uint64_t usb_hci : 1; /**< USB HCI Interrupt-enable */ 5868232809Sjmallett uint64_t reserved_41_43 : 3; 5869232809Sjmallett uint64_t usb_uctl : 1; /**< USB UCTL* interrupt-enable */ 5870232809Sjmallett uint64_t reserved_38_39 : 2; 5871232809Sjmallett uint64_t uart : 2; /**< Two UART interrupt-enable */ 5872232809Sjmallett uint64_t reserved_34_35 : 2; 5873232809Sjmallett uint64_t twsi : 2; /**< TWSI x interrupt-enable */ 5874232809Sjmallett uint64_t reserved_19_31 : 13; 5875232809Sjmallett uint64_t bootdma : 1; /**< Boot bus DMA engines interrupt-enable */ 5876232809Sjmallett uint64_t mio : 1; /**< MIO boot interrupt-enable */ 5877232809Sjmallett uint64_t nand : 1; /**< NAND Flash Controller interrupt-enable */ 5878232809Sjmallett uint64_t reserved_12_15 : 4; 5879232809Sjmallett uint64_t timer : 4; /**< General timer interrupt-enable */ 5880232809Sjmallett uint64_t reserved_3_7 : 5; 5881232809Sjmallett uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt-enable */ 5882232809Sjmallett uint64_t ssoiq : 1; /**< SSO IQ interrupt-enable */ 5883232809Sjmallett uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt-enable */ 5884232809Sjmallett#else 5885232809Sjmallett uint64_t ipdppthr : 1; 5886232809Sjmallett uint64_t ssoiq : 1; 5887232809Sjmallett uint64_t ipd_drp : 1; 5888232809Sjmallett uint64_t reserved_3_7 : 5; 5889232809Sjmallett uint64_t timer : 4; 5890232809Sjmallett uint64_t reserved_12_15 : 4; 5891232809Sjmallett uint64_t nand : 1; 5892232809Sjmallett uint64_t mio : 1; 5893232809Sjmallett uint64_t bootdma : 1; 5894232809Sjmallett uint64_t reserved_19_31 : 13; 5895232809Sjmallett uint64_t twsi : 2; 5896232809Sjmallett uint64_t reserved_34_35 : 2; 5897232809Sjmallett uint64_t uart : 2; 5898232809Sjmallett uint64_t reserved_38_39 : 2; 5899232809Sjmallett uint64_t usb_uctl : 1; 5900232809Sjmallett uint64_t reserved_41_43 : 3; 5901232809Sjmallett uint64_t usb_hci : 1; 5902232809Sjmallett uint64_t reserved_45_47 : 3; 5903232809Sjmallett uint64_t ptp : 1; 5904232809Sjmallett uint64_t reserved_49_62 : 14; 5905232809Sjmallett uint64_t rst : 1; 5906232809Sjmallett#endif 5907232809Sjmallett } s; 5908232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xx; 5909232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xxp1; 5910232809Sjmallett}; 5911232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_mio cvmx_ciu2_en_ppx_ip4_mio_t; 5912232809Sjmallett 5913232809Sjmallett/** 5914232809Sjmallett * cvmx_ciu2_en_pp#_ip4_mio_w1c 5915232809Sjmallett */ 5916232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_mio_w1c { 5917232809Sjmallett uint64_t u64; 5918232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s { 5919232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5920232809Sjmallett uint64_t rst : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[RST] */ 5921232809Sjmallett uint64_t reserved_49_62 : 14; 5922232809Sjmallett uint64_t ptp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[PTP] */ 5923232809Sjmallett uint64_t reserved_45_47 : 3; 5924232809Sjmallett uint64_t usb_hci : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_HCI] */ 5925232809Sjmallett uint64_t reserved_41_43 : 3; 5926232809Sjmallett uint64_t usb_uctl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_UCTL] */ 5927232809Sjmallett uint64_t reserved_38_39 : 2; 5928232809Sjmallett uint64_t uart : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[UART] */ 5929232809Sjmallett uint64_t reserved_34_35 : 2; 5930232809Sjmallett uint64_t twsi : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TWSI] */ 5931232809Sjmallett uint64_t reserved_19_31 : 13; 5932232809Sjmallett uint64_t bootdma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[BOOTDMA] */ 5933232809Sjmallett uint64_t mio : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[MIO] */ 5934232809Sjmallett uint64_t nand : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[NAND] */ 5935232809Sjmallett uint64_t reserved_12_15 : 4; 5936232809Sjmallett uint64_t timer : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TIMER] */ 5937232809Sjmallett uint64_t reserved_3_7 : 5; 5938232809Sjmallett uint64_t ipd_drp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPD_DRP] */ 5939232809Sjmallett uint64_t ssoiq : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[SSQIQ] */ 5940232809Sjmallett uint64_t ipdppthr : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPDPPTHR] */ 5941232809Sjmallett#else 5942232809Sjmallett uint64_t ipdppthr : 1; 5943232809Sjmallett uint64_t ssoiq : 1; 5944232809Sjmallett uint64_t ipd_drp : 1; 5945232809Sjmallett uint64_t reserved_3_7 : 5; 5946232809Sjmallett uint64_t timer : 4; 5947232809Sjmallett uint64_t reserved_12_15 : 4; 5948232809Sjmallett uint64_t nand : 1; 5949232809Sjmallett uint64_t mio : 1; 5950232809Sjmallett uint64_t bootdma : 1; 5951232809Sjmallett uint64_t reserved_19_31 : 13; 5952232809Sjmallett uint64_t twsi : 2; 5953232809Sjmallett uint64_t reserved_34_35 : 2; 5954232809Sjmallett uint64_t uart : 2; 5955232809Sjmallett uint64_t reserved_38_39 : 2; 5956232809Sjmallett uint64_t usb_uctl : 1; 5957232809Sjmallett uint64_t reserved_41_43 : 3; 5958232809Sjmallett uint64_t usb_hci : 1; 5959232809Sjmallett uint64_t reserved_45_47 : 3; 5960232809Sjmallett uint64_t ptp : 1; 5961232809Sjmallett uint64_t reserved_49_62 : 14; 5962232809Sjmallett uint64_t rst : 1; 5963232809Sjmallett#endif 5964232809Sjmallett } s; 5965232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xx; 5966232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xxp1; 5967232809Sjmallett}; 5968232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_mio_w1c cvmx_ciu2_en_ppx_ip4_mio_w1c_t; 5969232809Sjmallett 5970232809Sjmallett/** 5971232809Sjmallett * cvmx_ciu2_en_pp#_ip4_mio_w1s 5972232809Sjmallett */ 5973232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_mio_w1s { 5974232809Sjmallett uint64_t u64; 5975232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s { 5976232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5977232809Sjmallett uint64_t rst : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[RST] */ 5978232809Sjmallett uint64_t reserved_49_62 : 14; 5979232809Sjmallett uint64_t ptp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[PTP] */ 5980232809Sjmallett uint64_t reserved_45_47 : 3; 5981232809Sjmallett uint64_t usb_hci : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_HCI] */ 5982232809Sjmallett uint64_t reserved_41_43 : 3; 5983232809Sjmallett uint64_t usb_uctl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_UCTL] */ 5984232809Sjmallett uint64_t reserved_38_39 : 2; 5985232809Sjmallett uint64_t uart : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[UART] */ 5986232809Sjmallett uint64_t reserved_34_35 : 2; 5987232809Sjmallett uint64_t twsi : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TWSI] */ 5988232809Sjmallett uint64_t reserved_19_31 : 13; 5989232809Sjmallett uint64_t bootdma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[BOOTDMA] */ 5990232809Sjmallett uint64_t mio : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[MIO] */ 5991232809Sjmallett uint64_t nand : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[NAND] */ 5992232809Sjmallett uint64_t reserved_12_15 : 4; 5993232809Sjmallett uint64_t timer : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TIMER] */ 5994232809Sjmallett uint64_t reserved_3_7 : 5; 5995232809Sjmallett uint64_t ipd_drp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPD_DRP] */ 5996232809Sjmallett uint64_t ssoiq : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[SSQIQ] */ 5997232809Sjmallett uint64_t ipdppthr : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPDPPTHR] */ 5998232809Sjmallett#else 5999232809Sjmallett uint64_t ipdppthr : 1; 6000232809Sjmallett uint64_t ssoiq : 1; 6001232809Sjmallett uint64_t ipd_drp : 1; 6002232809Sjmallett uint64_t reserved_3_7 : 5; 6003232809Sjmallett uint64_t timer : 4; 6004232809Sjmallett uint64_t reserved_12_15 : 4; 6005232809Sjmallett uint64_t nand : 1; 6006232809Sjmallett uint64_t mio : 1; 6007232809Sjmallett uint64_t bootdma : 1; 6008232809Sjmallett uint64_t reserved_19_31 : 13; 6009232809Sjmallett uint64_t twsi : 2; 6010232809Sjmallett uint64_t reserved_34_35 : 2; 6011232809Sjmallett uint64_t uart : 2; 6012232809Sjmallett uint64_t reserved_38_39 : 2; 6013232809Sjmallett uint64_t usb_uctl : 1; 6014232809Sjmallett uint64_t reserved_41_43 : 3; 6015232809Sjmallett uint64_t usb_hci : 1; 6016232809Sjmallett uint64_t reserved_45_47 : 3; 6017232809Sjmallett uint64_t ptp : 1; 6018232809Sjmallett uint64_t reserved_49_62 : 14; 6019232809Sjmallett uint64_t rst : 1; 6020232809Sjmallett#endif 6021232809Sjmallett } s; 6022232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xx; 6023232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xxp1; 6024232809Sjmallett}; 6025232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_mio_w1s cvmx_ciu2_en_ppx_ip4_mio_w1s_t; 6026232809Sjmallett 6027232809Sjmallett/** 6028232809Sjmallett * cvmx_ciu2_en_pp#_ip4_pkt 6029232809Sjmallett */ 6030232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_pkt { 6031232809Sjmallett uint64_t u64; 6032232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_pkt_s { 6033232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6034232809Sjmallett uint64_t reserved_54_63 : 10; 6035232809Sjmallett uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt-enable */ 6036232809Sjmallett uint64_t reserved_49_51 : 3; 6037232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupt-enable */ 6038232809Sjmallett uint64_t reserved_41_47 : 7; 6039232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */ 6040232809Sjmallett uint64_t reserved_33_39 : 7; 6041232809Sjmallett uint64_t agl : 1; /**< AGL interrupt-enable */ 6042232809Sjmallett uint64_t reserved_13_31 : 19; 6043232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */ 6044232809Sjmallett uint64_t reserved_5_7 : 3; 6045232809Sjmallett uint64_t agx : 5; /**< GMX interrupt-enable */ 6046232809Sjmallett#else 6047232809Sjmallett uint64_t agx : 5; 6048232809Sjmallett uint64_t reserved_5_7 : 3; 6049232809Sjmallett uint64_t gmx_drp : 5; 6050232809Sjmallett uint64_t reserved_13_31 : 19; 6051232809Sjmallett uint64_t agl : 1; 6052232809Sjmallett uint64_t reserved_33_39 : 7; 6053232809Sjmallett uint64_t mii : 1; 6054232809Sjmallett uint64_t reserved_41_47 : 7; 6055232809Sjmallett uint64_t ilk : 1; 6056232809Sjmallett uint64_t reserved_49_51 : 3; 6057232809Sjmallett uint64_t ilk_drp : 2; 6058232809Sjmallett uint64_t reserved_54_63 : 10; 6059232809Sjmallett#endif 6060232809Sjmallett } s; 6061232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_pkt_s cn68xx; 6062232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_pkt_cn68xxp1 { 6063232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6064232809Sjmallett uint64_t reserved_49_63 : 15; 6065232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupt-enable */ 6066232809Sjmallett uint64_t reserved_41_47 : 7; 6067232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */ 6068232809Sjmallett uint64_t reserved_33_39 : 7; 6069232809Sjmallett uint64_t agl : 1; /**< AGL interrupt-enable */ 6070232809Sjmallett uint64_t reserved_13_31 : 19; 6071232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */ 6072232809Sjmallett uint64_t reserved_5_7 : 3; 6073232809Sjmallett uint64_t agx : 5; /**< GMX interrupt-enable */ 6074232809Sjmallett#else 6075232809Sjmallett uint64_t agx : 5; 6076232809Sjmallett uint64_t reserved_5_7 : 3; 6077232809Sjmallett uint64_t gmx_drp : 5; 6078232809Sjmallett uint64_t reserved_13_31 : 19; 6079232809Sjmallett uint64_t agl : 1; 6080232809Sjmallett uint64_t reserved_33_39 : 7; 6081232809Sjmallett uint64_t mii : 1; 6082232809Sjmallett uint64_t reserved_41_47 : 7; 6083232809Sjmallett uint64_t ilk : 1; 6084232809Sjmallett uint64_t reserved_49_63 : 15; 6085232809Sjmallett#endif 6086232809Sjmallett } cn68xxp1; 6087232809Sjmallett}; 6088232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_pkt cvmx_ciu2_en_ppx_ip4_pkt_t; 6089232809Sjmallett 6090232809Sjmallett/** 6091232809Sjmallett * cvmx_ciu2_en_pp#_ip4_pkt_w1c 6092232809Sjmallett */ 6093232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_pkt_w1c { 6094232809Sjmallett uint64_t u64; 6095232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s { 6096232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6097232809Sjmallett uint64_t reserved_54_63 : 10; 6098232809Sjmallett uint64_t ilk_drp : 2; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK_DRP] */ 6099232809Sjmallett uint64_t reserved_49_51 : 3; 6100232809Sjmallett uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */ 6101232809Sjmallett uint64_t reserved_41_47 : 7; 6102232809Sjmallett uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */ 6103232809Sjmallett uint64_t reserved_33_39 : 7; 6104232809Sjmallett uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */ 6105232809Sjmallett uint64_t reserved_13_31 : 19; 6106232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */ 6107232809Sjmallett uint64_t reserved_5_7 : 3; 6108232809Sjmallett uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */ 6109232809Sjmallett#else 6110232809Sjmallett uint64_t agx : 5; 6111232809Sjmallett uint64_t reserved_5_7 : 3; 6112232809Sjmallett uint64_t gmx_drp : 5; 6113232809Sjmallett uint64_t reserved_13_31 : 19; 6114232809Sjmallett uint64_t agl : 1; 6115232809Sjmallett uint64_t reserved_33_39 : 7; 6116232809Sjmallett uint64_t mii : 1; 6117232809Sjmallett uint64_t reserved_41_47 : 7; 6118232809Sjmallett uint64_t ilk : 1; 6119232809Sjmallett uint64_t reserved_49_51 : 3; 6120232809Sjmallett uint64_t ilk_drp : 2; 6121232809Sjmallett uint64_t reserved_54_63 : 10; 6122232809Sjmallett#endif 6123232809Sjmallett } s; 6124232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s cn68xx; 6125232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_cn68xxp1 { 6126232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6127232809Sjmallett uint64_t reserved_49_63 : 15; 6128232809Sjmallett uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */ 6129232809Sjmallett uint64_t reserved_41_47 : 7; 6130232809Sjmallett uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */ 6131232809Sjmallett uint64_t reserved_33_39 : 7; 6132232809Sjmallett uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */ 6133232809Sjmallett uint64_t reserved_13_31 : 19; 6134232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */ 6135232809Sjmallett uint64_t reserved_5_7 : 3; 6136232809Sjmallett uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */ 6137232809Sjmallett#else 6138232809Sjmallett uint64_t agx : 5; 6139232809Sjmallett uint64_t reserved_5_7 : 3; 6140232809Sjmallett uint64_t gmx_drp : 5; 6141232809Sjmallett uint64_t reserved_13_31 : 19; 6142232809Sjmallett uint64_t agl : 1; 6143232809Sjmallett uint64_t reserved_33_39 : 7; 6144232809Sjmallett uint64_t mii : 1; 6145232809Sjmallett uint64_t reserved_41_47 : 7; 6146232809Sjmallett uint64_t ilk : 1; 6147232809Sjmallett uint64_t reserved_49_63 : 15; 6148232809Sjmallett#endif 6149232809Sjmallett } cn68xxp1; 6150232809Sjmallett}; 6151232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_pkt_w1c cvmx_ciu2_en_ppx_ip4_pkt_w1c_t; 6152232809Sjmallett 6153232809Sjmallett/** 6154232809Sjmallett * cvmx_ciu2_en_pp#_ip4_pkt_w1s 6155232809Sjmallett */ 6156232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_pkt_w1s { 6157232809Sjmallett uint64_t u64; 6158232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s { 6159232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6160232809Sjmallett uint64_t reserved_54_63 : 10; 6161232809Sjmallett uint64_t ilk_drp : 2; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK_DRP] */ 6162232809Sjmallett uint64_t reserved_49_51 : 3; 6163232809Sjmallett uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */ 6164232809Sjmallett uint64_t reserved_41_47 : 7; 6165232809Sjmallett uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */ 6166232809Sjmallett uint64_t reserved_33_39 : 7; 6167232809Sjmallett uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */ 6168232809Sjmallett uint64_t reserved_13_31 : 19; 6169232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */ 6170232809Sjmallett uint64_t reserved_5_7 : 3; 6171232809Sjmallett uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */ 6172232809Sjmallett#else 6173232809Sjmallett uint64_t agx : 5; 6174232809Sjmallett uint64_t reserved_5_7 : 3; 6175232809Sjmallett uint64_t gmx_drp : 5; 6176232809Sjmallett uint64_t reserved_13_31 : 19; 6177232809Sjmallett uint64_t agl : 1; 6178232809Sjmallett uint64_t reserved_33_39 : 7; 6179232809Sjmallett uint64_t mii : 1; 6180232809Sjmallett uint64_t reserved_41_47 : 7; 6181232809Sjmallett uint64_t ilk : 1; 6182232809Sjmallett uint64_t reserved_49_51 : 3; 6183232809Sjmallett uint64_t ilk_drp : 2; 6184232809Sjmallett uint64_t reserved_54_63 : 10; 6185232809Sjmallett#endif 6186232809Sjmallett } s; 6187232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s cn68xx; 6188232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_cn68xxp1 { 6189232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6190232809Sjmallett uint64_t reserved_49_63 : 15; 6191232809Sjmallett uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */ 6192232809Sjmallett uint64_t reserved_41_47 : 7; 6193232809Sjmallett uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */ 6194232809Sjmallett uint64_t reserved_33_39 : 7; 6195232809Sjmallett uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */ 6196232809Sjmallett uint64_t reserved_13_31 : 19; 6197232809Sjmallett uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */ 6198232809Sjmallett uint64_t reserved_5_7 : 3; 6199232809Sjmallett uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */ 6200232809Sjmallett#else 6201232809Sjmallett uint64_t agx : 5; 6202232809Sjmallett uint64_t reserved_5_7 : 3; 6203232809Sjmallett uint64_t gmx_drp : 5; 6204232809Sjmallett uint64_t reserved_13_31 : 19; 6205232809Sjmallett uint64_t agl : 1; 6206232809Sjmallett uint64_t reserved_33_39 : 7; 6207232809Sjmallett uint64_t mii : 1; 6208232809Sjmallett uint64_t reserved_41_47 : 7; 6209232809Sjmallett uint64_t ilk : 1; 6210232809Sjmallett uint64_t reserved_49_63 : 15; 6211232809Sjmallett#endif 6212232809Sjmallett } cn68xxp1; 6213232809Sjmallett}; 6214232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_pkt_w1s cvmx_ciu2_en_ppx_ip4_pkt_w1s_t; 6215232809Sjmallett 6216232809Sjmallett/** 6217232809Sjmallett * cvmx_ciu2_en_pp#_ip4_rml 6218232809Sjmallett */ 6219232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_rml { 6220232809Sjmallett uint64_t u64; 6221232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_rml_s { 6222232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6223232809Sjmallett uint64_t reserved_56_63 : 8; 6224232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt-enable */ 6225232809Sjmallett uint64_t reserved_49_51 : 3; 6226232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt-enable */ 6227232809Sjmallett uint64_t reserved_41_47 : 7; 6228232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt-enable */ 6229232809Sjmallett uint64_t reserved_37_39 : 3; 6230232809Sjmallett uint64_t dpi_dma : 1; /**< DPI DMA interrupt-enable */ 6231232809Sjmallett uint64_t reserved_34_35 : 2; 6232232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt-enable */ 6233232809Sjmallett uint64_t sli : 1; /**< SLI interrupt-enable */ 6234232809Sjmallett uint64_t reserved_31_31 : 1; 6235232809Sjmallett uint64_t key : 1; /**< KEY interrupt-enable */ 6236232809Sjmallett uint64_t rad : 1; /**< RAD interrupt-enable */ 6237232809Sjmallett uint64_t tim : 1; /**< TIM interrupt-enable */ 6238232809Sjmallett uint64_t reserved_25_27 : 3; 6239232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt-enable */ 6240232809Sjmallett uint64_t reserved_17_23 : 7; 6241232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt-enable */ 6242232809Sjmallett uint64_t reserved_8_15 : 8; 6243232809Sjmallett uint64_t pko : 1; /**< PKO interrupt-enable */ 6244232809Sjmallett uint64_t pip : 1; /**< PIP interrupt-enable */ 6245232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt-enable */ 6246232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt-enable */ 6247232809Sjmallett uint64_t reserved_1_3 : 3; 6248232809Sjmallett uint64_t iob : 1; /**< IOB interrupt-enable */ 6249232809Sjmallett#else 6250232809Sjmallett uint64_t iob : 1; 6251232809Sjmallett uint64_t reserved_1_3 : 3; 6252232809Sjmallett uint64_t fpa : 1; 6253232809Sjmallett uint64_t ipd : 1; 6254232809Sjmallett uint64_t pip : 1; 6255232809Sjmallett uint64_t pko : 1; 6256232809Sjmallett uint64_t reserved_8_15 : 8; 6257232809Sjmallett uint64_t sso : 1; 6258232809Sjmallett uint64_t reserved_17_23 : 7; 6259232809Sjmallett uint64_t zip : 1; 6260232809Sjmallett uint64_t reserved_25_27 : 3; 6261232809Sjmallett uint64_t tim : 1; 6262232809Sjmallett uint64_t rad : 1; 6263232809Sjmallett uint64_t key : 1; 6264232809Sjmallett uint64_t reserved_31_31 : 1; 6265232809Sjmallett uint64_t sli : 1; 6266232809Sjmallett uint64_t dpi : 1; 6267232809Sjmallett uint64_t reserved_34_35 : 2; 6268232809Sjmallett uint64_t dpi_dma : 1; 6269232809Sjmallett uint64_t reserved_37_39 : 3; 6270232809Sjmallett uint64_t dfa : 1; 6271232809Sjmallett uint64_t reserved_41_47 : 7; 6272232809Sjmallett uint64_t l2c : 1; 6273232809Sjmallett uint64_t reserved_49_51 : 3; 6274232809Sjmallett uint64_t trace : 4; 6275232809Sjmallett uint64_t reserved_56_63 : 8; 6276232809Sjmallett#endif 6277232809Sjmallett } s; 6278232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_rml_s cn68xx; 6279232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_rml_cn68xxp1 { 6280232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6281232809Sjmallett uint64_t reserved_56_63 : 8; 6282232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt-enable */ 6283232809Sjmallett uint64_t reserved_49_51 : 3; 6284232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt-enable */ 6285232809Sjmallett uint64_t reserved_41_47 : 7; 6286232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt-enable */ 6287232809Sjmallett uint64_t reserved_34_39 : 6; 6288232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt-enable */ 6289232809Sjmallett uint64_t sli : 1; /**< SLI interrupt-enable */ 6290232809Sjmallett uint64_t reserved_31_31 : 1; 6291232809Sjmallett uint64_t key : 1; /**< KEY interrupt-enable */ 6292232809Sjmallett uint64_t rad : 1; /**< RAD interrupt-enable */ 6293232809Sjmallett uint64_t tim : 1; /**< TIM interrupt-enable */ 6294232809Sjmallett uint64_t reserved_25_27 : 3; 6295232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt-enable */ 6296232809Sjmallett uint64_t reserved_17_23 : 7; 6297232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt-enable */ 6298232809Sjmallett uint64_t reserved_8_15 : 8; 6299232809Sjmallett uint64_t pko : 1; /**< PKO interrupt-enable */ 6300232809Sjmallett uint64_t pip : 1; /**< PIP interrupt-enable */ 6301232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt-enable */ 6302232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt-enable */ 6303232809Sjmallett uint64_t reserved_1_3 : 3; 6304232809Sjmallett uint64_t iob : 1; /**< IOB interrupt-enable */ 6305232809Sjmallett#else 6306232809Sjmallett uint64_t iob : 1; 6307232809Sjmallett uint64_t reserved_1_3 : 3; 6308232809Sjmallett uint64_t fpa : 1; 6309232809Sjmallett uint64_t ipd : 1; 6310232809Sjmallett uint64_t pip : 1; 6311232809Sjmallett uint64_t pko : 1; 6312232809Sjmallett uint64_t reserved_8_15 : 8; 6313232809Sjmallett uint64_t sso : 1; 6314232809Sjmallett uint64_t reserved_17_23 : 7; 6315232809Sjmallett uint64_t zip : 1; 6316232809Sjmallett uint64_t reserved_25_27 : 3; 6317232809Sjmallett uint64_t tim : 1; 6318232809Sjmallett uint64_t rad : 1; 6319232809Sjmallett uint64_t key : 1; 6320232809Sjmallett uint64_t reserved_31_31 : 1; 6321232809Sjmallett uint64_t sli : 1; 6322232809Sjmallett uint64_t dpi : 1; 6323232809Sjmallett uint64_t reserved_34_39 : 6; 6324232809Sjmallett uint64_t dfa : 1; 6325232809Sjmallett uint64_t reserved_41_47 : 7; 6326232809Sjmallett uint64_t l2c : 1; 6327232809Sjmallett uint64_t reserved_49_51 : 3; 6328232809Sjmallett uint64_t trace : 4; 6329232809Sjmallett uint64_t reserved_56_63 : 8; 6330232809Sjmallett#endif 6331232809Sjmallett } cn68xxp1; 6332232809Sjmallett}; 6333232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_rml cvmx_ciu2_en_ppx_ip4_rml_t; 6334232809Sjmallett 6335232809Sjmallett/** 6336232809Sjmallett * cvmx_ciu2_en_pp#_ip4_rml_w1c 6337232809Sjmallett */ 6338232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_rml_w1c { 6339232809Sjmallett uint64_t u64; 6340232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s { 6341232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6342232809Sjmallett uint64_t reserved_56_63 : 8; 6343232809Sjmallett uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */ 6344232809Sjmallett uint64_t reserved_49_51 : 3; 6345232809Sjmallett uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */ 6346232809Sjmallett uint64_t reserved_41_47 : 7; 6347232809Sjmallett uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */ 6348232809Sjmallett uint64_t reserved_37_39 : 3; 6349232809Sjmallett uint64_t dpi_dma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI_DMA] */ 6350232809Sjmallett uint64_t reserved_34_35 : 2; 6351232809Sjmallett uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */ 6352232809Sjmallett uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */ 6353232809Sjmallett uint64_t reserved_31_31 : 1; 6354232809Sjmallett uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */ 6355232809Sjmallett uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */ 6356232809Sjmallett uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */ 6357232809Sjmallett uint64_t reserved_25_27 : 3; 6358232809Sjmallett uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */ 6359232809Sjmallett uint64_t reserved_17_23 : 7; 6360232809Sjmallett uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */ 6361232809Sjmallett uint64_t reserved_8_15 : 8; 6362232809Sjmallett uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */ 6363232809Sjmallett uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */ 6364232809Sjmallett uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */ 6365232809Sjmallett uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */ 6366232809Sjmallett uint64_t reserved_1_3 : 3; 6367232809Sjmallett uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */ 6368232809Sjmallett#else 6369232809Sjmallett uint64_t iob : 1; 6370232809Sjmallett uint64_t reserved_1_3 : 3; 6371232809Sjmallett uint64_t fpa : 1; 6372232809Sjmallett uint64_t ipd : 1; 6373232809Sjmallett uint64_t pip : 1; 6374232809Sjmallett uint64_t pko : 1; 6375232809Sjmallett uint64_t reserved_8_15 : 8; 6376232809Sjmallett uint64_t sso : 1; 6377232809Sjmallett uint64_t reserved_17_23 : 7; 6378232809Sjmallett uint64_t zip : 1; 6379232809Sjmallett uint64_t reserved_25_27 : 3; 6380232809Sjmallett uint64_t tim : 1; 6381232809Sjmallett uint64_t rad : 1; 6382232809Sjmallett uint64_t key : 1; 6383232809Sjmallett uint64_t reserved_31_31 : 1; 6384232809Sjmallett uint64_t sli : 1; 6385232809Sjmallett uint64_t dpi : 1; 6386232809Sjmallett uint64_t reserved_34_35 : 2; 6387232809Sjmallett uint64_t dpi_dma : 1; 6388232809Sjmallett uint64_t reserved_37_39 : 3; 6389232809Sjmallett uint64_t dfa : 1; 6390232809Sjmallett uint64_t reserved_41_47 : 7; 6391232809Sjmallett uint64_t l2c : 1; 6392232809Sjmallett uint64_t reserved_49_51 : 3; 6393232809Sjmallett uint64_t trace : 4; 6394232809Sjmallett uint64_t reserved_56_63 : 8; 6395232809Sjmallett#endif 6396232809Sjmallett } s; 6397232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s cn68xx; 6398232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_rml_w1c_cn68xxp1 { 6399232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6400232809Sjmallett uint64_t reserved_56_63 : 8; 6401232809Sjmallett uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */ 6402232809Sjmallett uint64_t reserved_49_51 : 3; 6403232809Sjmallett uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */ 6404232809Sjmallett uint64_t reserved_41_47 : 7; 6405232809Sjmallett uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */ 6406232809Sjmallett uint64_t reserved_34_39 : 6; 6407232809Sjmallett uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */ 6408232809Sjmallett uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */ 6409232809Sjmallett uint64_t reserved_31_31 : 1; 6410232809Sjmallett uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */ 6411232809Sjmallett uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */ 6412232809Sjmallett uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */ 6413232809Sjmallett uint64_t reserved_25_27 : 3; 6414232809Sjmallett uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */ 6415232809Sjmallett uint64_t reserved_17_23 : 7; 6416232809Sjmallett uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */ 6417232809Sjmallett uint64_t reserved_8_15 : 8; 6418232809Sjmallett uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */ 6419232809Sjmallett uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */ 6420232809Sjmallett uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */ 6421232809Sjmallett uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */ 6422232809Sjmallett uint64_t reserved_1_3 : 3; 6423232809Sjmallett uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */ 6424232809Sjmallett#else 6425232809Sjmallett uint64_t iob : 1; 6426232809Sjmallett uint64_t reserved_1_3 : 3; 6427232809Sjmallett uint64_t fpa : 1; 6428232809Sjmallett uint64_t ipd : 1; 6429232809Sjmallett uint64_t pip : 1; 6430232809Sjmallett uint64_t pko : 1; 6431232809Sjmallett uint64_t reserved_8_15 : 8; 6432232809Sjmallett uint64_t sso : 1; 6433232809Sjmallett uint64_t reserved_17_23 : 7; 6434232809Sjmallett uint64_t zip : 1; 6435232809Sjmallett uint64_t reserved_25_27 : 3; 6436232809Sjmallett uint64_t tim : 1; 6437232809Sjmallett uint64_t rad : 1; 6438232809Sjmallett uint64_t key : 1; 6439232809Sjmallett uint64_t reserved_31_31 : 1; 6440232809Sjmallett uint64_t sli : 1; 6441232809Sjmallett uint64_t dpi : 1; 6442232809Sjmallett uint64_t reserved_34_39 : 6; 6443232809Sjmallett uint64_t dfa : 1; 6444232809Sjmallett uint64_t reserved_41_47 : 7; 6445232809Sjmallett uint64_t l2c : 1; 6446232809Sjmallett uint64_t reserved_49_51 : 3; 6447232809Sjmallett uint64_t trace : 4; 6448232809Sjmallett uint64_t reserved_56_63 : 8; 6449232809Sjmallett#endif 6450232809Sjmallett } cn68xxp1; 6451232809Sjmallett}; 6452232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_rml_w1c cvmx_ciu2_en_ppx_ip4_rml_w1c_t; 6453232809Sjmallett 6454232809Sjmallett/** 6455232809Sjmallett * cvmx_ciu2_en_pp#_ip4_rml_w1s 6456232809Sjmallett */ 6457232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_rml_w1s { 6458232809Sjmallett uint64_t u64; 6459232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s { 6460232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6461232809Sjmallett uint64_t reserved_56_63 : 8; 6462232809Sjmallett uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */ 6463232809Sjmallett uint64_t reserved_49_51 : 3; 6464232809Sjmallett uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */ 6465232809Sjmallett uint64_t reserved_41_47 : 7; 6466232809Sjmallett uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */ 6467232809Sjmallett uint64_t reserved_37_39 : 3; 6468232809Sjmallett uint64_t dpi_dma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI_DMA] */ 6469232809Sjmallett uint64_t reserved_34_35 : 2; 6470232809Sjmallett uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */ 6471232809Sjmallett uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */ 6472232809Sjmallett uint64_t reserved_31_31 : 1; 6473232809Sjmallett uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */ 6474232809Sjmallett uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */ 6475232809Sjmallett uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */ 6476232809Sjmallett uint64_t reserved_25_27 : 3; 6477232809Sjmallett uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */ 6478232809Sjmallett uint64_t reserved_17_23 : 7; 6479232809Sjmallett uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */ 6480232809Sjmallett uint64_t reserved_8_15 : 8; 6481232809Sjmallett uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */ 6482232809Sjmallett uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */ 6483232809Sjmallett uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */ 6484232809Sjmallett uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */ 6485232809Sjmallett uint64_t reserved_1_3 : 3; 6486232809Sjmallett uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */ 6487232809Sjmallett#else 6488232809Sjmallett uint64_t iob : 1; 6489232809Sjmallett uint64_t reserved_1_3 : 3; 6490232809Sjmallett uint64_t fpa : 1; 6491232809Sjmallett uint64_t ipd : 1; 6492232809Sjmallett uint64_t pip : 1; 6493232809Sjmallett uint64_t pko : 1; 6494232809Sjmallett uint64_t reserved_8_15 : 8; 6495232809Sjmallett uint64_t sso : 1; 6496232809Sjmallett uint64_t reserved_17_23 : 7; 6497232809Sjmallett uint64_t zip : 1; 6498232809Sjmallett uint64_t reserved_25_27 : 3; 6499232809Sjmallett uint64_t tim : 1; 6500232809Sjmallett uint64_t rad : 1; 6501232809Sjmallett uint64_t key : 1; 6502232809Sjmallett uint64_t reserved_31_31 : 1; 6503232809Sjmallett uint64_t sli : 1; 6504232809Sjmallett uint64_t dpi : 1; 6505232809Sjmallett uint64_t reserved_34_35 : 2; 6506232809Sjmallett uint64_t dpi_dma : 1; 6507232809Sjmallett uint64_t reserved_37_39 : 3; 6508232809Sjmallett uint64_t dfa : 1; 6509232809Sjmallett uint64_t reserved_41_47 : 7; 6510232809Sjmallett uint64_t l2c : 1; 6511232809Sjmallett uint64_t reserved_49_51 : 3; 6512232809Sjmallett uint64_t trace : 4; 6513232809Sjmallett uint64_t reserved_56_63 : 8; 6514232809Sjmallett#endif 6515232809Sjmallett } s; 6516232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s cn68xx; 6517232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_rml_w1s_cn68xxp1 { 6518232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6519232809Sjmallett uint64_t reserved_56_63 : 8; 6520232809Sjmallett uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */ 6521232809Sjmallett uint64_t reserved_49_51 : 3; 6522232809Sjmallett uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */ 6523232809Sjmallett uint64_t reserved_41_47 : 7; 6524232809Sjmallett uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */ 6525232809Sjmallett uint64_t reserved_34_39 : 6; 6526232809Sjmallett uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */ 6527232809Sjmallett uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */ 6528232809Sjmallett uint64_t reserved_31_31 : 1; 6529232809Sjmallett uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */ 6530232809Sjmallett uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */ 6531232809Sjmallett uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */ 6532232809Sjmallett uint64_t reserved_25_27 : 3; 6533232809Sjmallett uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */ 6534232809Sjmallett uint64_t reserved_17_23 : 7; 6535232809Sjmallett uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */ 6536232809Sjmallett uint64_t reserved_8_15 : 8; 6537232809Sjmallett uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */ 6538232809Sjmallett uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */ 6539232809Sjmallett uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */ 6540232809Sjmallett uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */ 6541232809Sjmallett uint64_t reserved_1_3 : 3; 6542232809Sjmallett uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */ 6543232809Sjmallett#else 6544232809Sjmallett uint64_t iob : 1; 6545232809Sjmallett uint64_t reserved_1_3 : 3; 6546232809Sjmallett uint64_t fpa : 1; 6547232809Sjmallett uint64_t ipd : 1; 6548232809Sjmallett uint64_t pip : 1; 6549232809Sjmallett uint64_t pko : 1; 6550232809Sjmallett uint64_t reserved_8_15 : 8; 6551232809Sjmallett uint64_t sso : 1; 6552232809Sjmallett uint64_t reserved_17_23 : 7; 6553232809Sjmallett uint64_t zip : 1; 6554232809Sjmallett uint64_t reserved_25_27 : 3; 6555232809Sjmallett uint64_t tim : 1; 6556232809Sjmallett uint64_t rad : 1; 6557232809Sjmallett uint64_t key : 1; 6558232809Sjmallett uint64_t reserved_31_31 : 1; 6559232809Sjmallett uint64_t sli : 1; 6560232809Sjmallett uint64_t dpi : 1; 6561232809Sjmallett uint64_t reserved_34_39 : 6; 6562232809Sjmallett uint64_t dfa : 1; 6563232809Sjmallett uint64_t reserved_41_47 : 7; 6564232809Sjmallett uint64_t l2c : 1; 6565232809Sjmallett uint64_t reserved_49_51 : 3; 6566232809Sjmallett uint64_t trace : 4; 6567232809Sjmallett uint64_t reserved_56_63 : 8; 6568232809Sjmallett#endif 6569232809Sjmallett } cn68xxp1; 6570232809Sjmallett}; 6571232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_rml_w1s cvmx_ciu2_en_ppx_ip4_rml_w1s_t; 6572232809Sjmallett 6573232809Sjmallett/** 6574232809Sjmallett * cvmx_ciu2_en_pp#_ip4_wdog 6575232809Sjmallett */ 6576232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_wdog { 6577232809Sjmallett uint64_t u64; 6578232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wdog_s { 6579232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6580232809Sjmallett uint64_t reserved_32_63 : 32; 6581232809Sjmallett uint64_t wdog : 32; /**< 32 watchdog interrupt-enable */ 6582232809Sjmallett#else 6583232809Sjmallett uint64_t wdog : 32; 6584232809Sjmallett uint64_t reserved_32_63 : 32; 6585232809Sjmallett#endif 6586232809Sjmallett } s; 6587232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xx; 6588232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xxp1; 6589232809Sjmallett}; 6590232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_wdog cvmx_ciu2_en_ppx_ip4_wdog_t; 6591232809Sjmallett 6592232809Sjmallett/** 6593232809Sjmallett * cvmx_ciu2_en_pp#_ip4_wdog_w1c 6594232809Sjmallett */ 6595232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_wdog_w1c { 6596232809Sjmallett uint64_t u64; 6597232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s { 6598232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6599232809Sjmallett uint64_t reserved_32_63 : 32; 6600232809Sjmallett uint64_t wdog : 32; /**< write 1 to clear CIU2_EN_xx_yy_WDOG */ 6601232809Sjmallett#else 6602232809Sjmallett uint64_t wdog : 32; 6603232809Sjmallett uint64_t reserved_32_63 : 32; 6604232809Sjmallett#endif 6605232809Sjmallett } s; 6606232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xx; 6607232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xxp1; 6608232809Sjmallett}; 6609232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_wdog_w1c cvmx_ciu2_en_ppx_ip4_wdog_w1c_t; 6610232809Sjmallett 6611232809Sjmallett/** 6612232809Sjmallett * cvmx_ciu2_en_pp#_ip4_wdog_w1s 6613232809Sjmallett */ 6614232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_wdog_w1s { 6615232809Sjmallett uint64_t u64; 6616232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s { 6617232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6618232809Sjmallett uint64_t reserved_32_63 : 32; 6619232809Sjmallett uint64_t wdog : 32; /**< Write 1 to enable CIU2_EN_xx_yy_WDOG[WDOG] */ 6620232809Sjmallett#else 6621232809Sjmallett uint64_t wdog : 32; 6622232809Sjmallett uint64_t reserved_32_63 : 32; 6623232809Sjmallett#endif 6624232809Sjmallett } s; 6625232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xx; 6626232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xxp1; 6627232809Sjmallett}; 6628232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_wdog_w1s cvmx_ciu2_en_ppx_ip4_wdog_w1s_t; 6629232809Sjmallett 6630232809Sjmallett/** 6631232809Sjmallett * cvmx_ciu2_en_pp#_ip4_wrkq 6632232809Sjmallett */ 6633232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_wrkq { 6634232809Sjmallett uint64_t u64; 6635232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wrkq_s { 6636232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6637232809Sjmallett uint64_t workq : 64; /**< 64 work queue interrupt-enable */ 6638232809Sjmallett#else 6639232809Sjmallett uint64_t workq : 64; 6640232809Sjmallett#endif 6641232809Sjmallett } s; 6642232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xx; 6643232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xxp1; 6644232809Sjmallett}; 6645232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_wrkq cvmx_ciu2_en_ppx_ip4_wrkq_t; 6646232809Sjmallett 6647232809Sjmallett/** 6648232809Sjmallett * cvmx_ciu2_en_pp#_ip4_wrkq_w1c 6649232809Sjmallett */ 6650232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_wrkq_w1c { 6651232809Sjmallett uint64_t u64; 6652232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s { 6653232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6654232809Sjmallett uint64_t workq : 64; /**< Write 1 to clear CIU2_EN_xx_yy_WRKQ[WORKQ] 6655232809Sjmallett For W1C bits, write 1 to clear the corresponding 6656232809Sjmallett CIU2_EN_xx_yy_WRKQ,write 0 to retain previous value */ 6657232809Sjmallett#else 6658232809Sjmallett uint64_t workq : 64; 6659232809Sjmallett#endif 6660232809Sjmallett } s; 6661232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xx; 6662232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xxp1; 6663232809Sjmallett}; 6664232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_wrkq_w1c cvmx_ciu2_en_ppx_ip4_wrkq_w1c_t; 6665232809Sjmallett 6666232809Sjmallett/** 6667232809Sjmallett * cvmx_ciu2_en_pp#_ip4_wrkq_w1s 6668232809Sjmallett */ 6669232809Sjmallettunion cvmx_ciu2_en_ppx_ip4_wrkq_w1s { 6670232809Sjmallett uint64_t u64; 6671232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s { 6672232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6673232809Sjmallett uint64_t workq : 64; /**< Write 1 to enable CIU2_EN_xx_yy_WRKQ[WORKQ] 6674232809Sjmallett 1 bit/group. For all W1S bits, write 1 to enable 6675232809Sjmallett corresponding CIU2_EN_xx_yy_WRKQ[WORKQ] bit, 6676232809Sjmallett writing 0 to retain previous value. */ 6677232809Sjmallett#else 6678232809Sjmallett uint64_t workq : 64; 6679232809Sjmallett#endif 6680232809Sjmallett } s; 6681232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xx; 6682232809Sjmallett struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xxp1; 6683232809Sjmallett}; 6684232809Sjmalletttypedef union cvmx_ciu2_en_ppx_ip4_wrkq_w1s cvmx_ciu2_en_ppx_ip4_wrkq_w1s_t; 6685232809Sjmallett 6686232809Sjmallett/** 6687232809Sjmallett * cvmx_ciu2_intr_ciu_ready 6688232809Sjmallett */ 6689232809Sjmallettunion cvmx_ciu2_intr_ciu_ready { 6690232809Sjmallett uint64_t u64; 6691232809Sjmallett struct cvmx_ciu2_intr_ciu_ready_s { 6692232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6693232809Sjmallett uint64_t reserved_1_63 : 63; 6694232809Sjmallett uint64_t ready : 1; /**< Because of the delay of the IRQ updates which may 6695232809Sjmallett take about 200 sclk cycles, software should read 6696232809Sjmallett this register after servicing interrupts and wait 6697232809Sjmallett for response before enabling interrupt watching. 6698232809Sjmallett Or, the outdated interrupt will show up again. 6699232809Sjmallett The read back data return when all interrupts have 6700232809Sjmallett been serviced, and read back data is always zero. 6701232809Sjmallett In o68 pass2, CIU_READY gets replaced by CIU2_ACK 6702232809Sjmallett This becomes an internal debug feature. */ 6703232809Sjmallett#else 6704232809Sjmallett uint64_t ready : 1; 6705232809Sjmallett uint64_t reserved_1_63 : 63; 6706232809Sjmallett#endif 6707232809Sjmallett } s; 6708232809Sjmallett struct cvmx_ciu2_intr_ciu_ready_s cn68xx; 6709232809Sjmallett struct cvmx_ciu2_intr_ciu_ready_s cn68xxp1; 6710232809Sjmallett}; 6711232809Sjmalletttypedef union cvmx_ciu2_intr_ciu_ready cvmx_ciu2_intr_ciu_ready_t; 6712232809Sjmallett 6713232809Sjmallett/** 6714232809Sjmallett * cvmx_ciu2_intr_ram_ecc_ctl 6715232809Sjmallett */ 6716232809Sjmallettunion cvmx_ciu2_intr_ram_ecc_ctl { 6717232809Sjmallett uint64_t u64; 6718232809Sjmallett struct cvmx_ciu2_intr_ram_ecc_ctl_s { 6719232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6720232809Sjmallett uint64_t reserved_3_63 : 61; 6721232809Sjmallett uint64_t flip_synd : 2; /**< Testing feature. Flip Syndrom to generate single or 6722232809Sjmallett double bit error. FLIP_SYND[0] generate even number 6723232809Sjmallett -ed bits error,FLIP_SYND[1] generate odd bits error */ 6724232809Sjmallett uint64_t ecc_ena : 1; /**< ECC Enable: When set will enable the 9bit ECC 6725232809Sjmallett check/correct logic for CIU interrupt enable RAM. 6726232809Sjmallett With ECC enabled, the ECC code will be generated 6727232809Sjmallett and written in the memory and then later on reads, 6728232809Sjmallett used to check and correct Single bit error and 6729232809Sjmallett detect Double Bit error. */ 6730232809Sjmallett#else 6731232809Sjmallett uint64_t ecc_ena : 1; 6732232809Sjmallett uint64_t flip_synd : 2; 6733232809Sjmallett uint64_t reserved_3_63 : 61; 6734232809Sjmallett#endif 6735232809Sjmallett } s; 6736232809Sjmallett struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xx; 6737232809Sjmallett struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xxp1; 6738232809Sjmallett}; 6739232809Sjmalletttypedef union cvmx_ciu2_intr_ram_ecc_ctl cvmx_ciu2_intr_ram_ecc_ctl_t; 6740232809Sjmallett 6741232809Sjmallett/** 6742232809Sjmallett * cvmx_ciu2_intr_ram_ecc_st 6743232809Sjmallett */ 6744232809Sjmallettunion cvmx_ciu2_intr_ram_ecc_st { 6745232809Sjmallett uint64_t u64; 6746232809Sjmallett struct cvmx_ciu2_intr_ram_ecc_st_s { 6747232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6748232809Sjmallett uint64_t reserved_23_63 : 41; 6749232809Sjmallett uint64_t addr : 7; /**< Latch the address for latest sde/dde occured 6750232809Sjmallett The value only 0-98 indicates the different 98 IRQs 6751232809Sjmallett Software can read all corresponding corrected value 6752232809Sjmallett from CIU2_EN_PPX_IPx_*** or CIU2_EN_IOX_INT_*** and 6753232809Sjmallett rewite to the same address to corrected the bit err */ 6754232809Sjmallett uint64_t reserved_13_15 : 3; 6755232809Sjmallett uint64_t syndrom : 9; /**< Report the latest error syndrom */ 6756232809Sjmallett uint64_t reserved_2_3 : 2; 6757232809Sjmallett uint64_t dbe : 1; /**< Double bit error observed. Write '1' to clear */ 6758232809Sjmallett uint64_t sbe : 1; /**< Single bit error observed. Write '1' to clear */ 6759232809Sjmallett#else 6760232809Sjmallett uint64_t sbe : 1; 6761232809Sjmallett uint64_t dbe : 1; 6762232809Sjmallett uint64_t reserved_2_3 : 2; 6763232809Sjmallett uint64_t syndrom : 9; 6764232809Sjmallett uint64_t reserved_13_15 : 3; 6765232809Sjmallett uint64_t addr : 7; 6766232809Sjmallett uint64_t reserved_23_63 : 41; 6767232809Sjmallett#endif 6768232809Sjmallett } s; 6769232809Sjmallett struct cvmx_ciu2_intr_ram_ecc_st_s cn68xx; 6770232809Sjmallett struct cvmx_ciu2_intr_ram_ecc_st_s cn68xxp1; 6771232809Sjmallett}; 6772232809Sjmalletttypedef union cvmx_ciu2_intr_ram_ecc_st cvmx_ciu2_intr_ram_ecc_st_t; 6773232809Sjmallett 6774232809Sjmallett/** 6775232809Sjmallett * cvmx_ciu2_intr_slowdown 6776232809Sjmallett */ 6777232809Sjmallettunion cvmx_ciu2_intr_slowdown { 6778232809Sjmallett uint64_t u64; 6779232809Sjmallett struct cvmx_ciu2_intr_slowdown_s { 6780232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6781232809Sjmallett uint64_t reserved_3_63 : 61; 6782232809Sjmallett uint64_t ctl : 3; /**< Slowdown CIU interrupt walker processing time. 6783232809Sjmallett IRQ2/3/4 for all 32 PPs are sent to PP (MRC) in 6784232809Sjmallett a serial bus to reduce global routing. There is 6785232809Sjmallett no backpressure mechanism designed for this scheme. 6786232809Sjmallett It will be only a problem when sclk is faster, this 6787232809Sjmallett Control will process 1 interrupt in 2^(CTL) sclks 6788232809Sjmallett With different setting, clock rate ratio can handle 6789232809Sjmallett SLOWDOWN sclk_freq/aclk_freq ratio 6790232809Sjmallett 0 3 6791232809Sjmallett 1 6 6792232809Sjmallett n 3*2^(n) */ 6793232809Sjmallett#else 6794232809Sjmallett uint64_t ctl : 3; 6795232809Sjmallett uint64_t reserved_3_63 : 61; 6796232809Sjmallett#endif 6797232809Sjmallett } s; 6798232809Sjmallett struct cvmx_ciu2_intr_slowdown_s cn68xx; 6799232809Sjmallett struct cvmx_ciu2_intr_slowdown_s cn68xxp1; 6800232809Sjmallett}; 6801232809Sjmalletttypedef union cvmx_ciu2_intr_slowdown cvmx_ciu2_intr_slowdown_t; 6802232809Sjmallett 6803232809Sjmallett/** 6804232809Sjmallett * cvmx_ciu2_msi_rcv# 6805232809Sjmallett * 6806232809Sjmallett * CIU2_MSI_RCV Received MSI state bits (Pass 2) 6807232809Sjmallett * 6808232809Sjmallett */ 6809232809Sjmallettunion cvmx_ciu2_msi_rcvx { 6810232809Sjmallett uint64_t u64; 6811232809Sjmallett struct cvmx_ciu2_msi_rcvx_s { 6812232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6813232809Sjmallett uint64_t reserved_1_63 : 63; 6814232809Sjmallett uint64_t msi_rcv : 1; /**< MSI state bit, set on MSI delivery or by software 6815232809Sjmallett "write 1" to set or "write 0" to clear. 6816232809Sjmallett This register is used to create the 6817232809Sjmallett CIU2_RAW_xx_yy_IO[MSIRED] interrupt. See also 6818232809Sjmallett SLI_MSI_RCV. */ 6819232809Sjmallett#else 6820232809Sjmallett uint64_t msi_rcv : 1; 6821232809Sjmallett uint64_t reserved_1_63 : 63; 6822232809Sjmallett#endif 6823232809Sjmallett } s; 6824232809Sjmallett struct cvmx_ciu2_msi_rcvx_s cn68xx; 6825232809Sjmallett struct cvmx_ciu2_msi_rcvx_s cn68xxp1; 6826232809Sjmallett}; 6827232809Sjmalletttypedef union cvmx_ciu2_msi_rcvx cvmx_ciu2_msi_rcvx_t; 6828232809Sjmallett 6829232809Sjmallett/** 6830232809Sjmallett * cvmx_ciu2_msi_sel# 6831232809Sjmallett * 6832232809Sjmallett * CIU2_MSI_SEL Received MSI SEL enable (Pass 2) 6833232809Sjmallett * 6834232809Sjmallett */ 6835232809Sjmallettunion cvmx_ciu2_msi_selx { 6836232809Sjmallett uint64_t u64; 6837232809Sjmallett struct cvmx_ciu2_msi_selx_s { 6838232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6839232809Sjmallett uint64_t reserved_13_63 : 51; 6840232809Sjmallett uint64_t pp_num : 5; /**< Processor number to receive this MSI interrupt */ 6841232809Sjmallett uint64_t reserved_6_7 : 2; 6842232809Sjmallett uint64_t ip_num : 2; /**< Interrupt priority level to receive this MSI 6843232809Sjmallett interrupt (00=IP2, 01=IP3, 10=IP4, 11=rsvd) */ 6844232809Sjmallett uint64_t reserved_1_3 : 3; 6845232809Sjmallett uint64_t en : 1; /**< Enable interrupt delivery. 6846232809Sjmallett Must be set for PP_NUM and IP_NUM to have effect. */ 6847232809Sjmallett#else 6848232809Sjmallett uint64_t en : 1; 6849232809Sjmallett uint64_t reserved_1_3 : 3; 6850232809Sjmallett uint64_t ip_num : 2; 6851232809Sjmallett uint64_t reserved_6_7 : 2; 6852232809Sjmallett uint64_t pp_num : 5; 6853232809Sjmallett uint64_t reserved_13_63 : 51; 6854232809Sjmallett#endif 6855232809Sjmallett } s; 6856232809Sjmallett struct cvmx_ciu2_msi_selx_s cn68xx; 6857232809Sjmallett struct cvmx_ciu2_msi_selx_s cn68xxp1; 6858232809Sjmallett}; 6859232809Sjmalletttypedef union cvmx_ciu2_msi_selx cvmx_ciu2_msi_selx_t; 6860232809Sjmallett 6861232809Sjmallett/** 6862232809Sjmallett * cvmx_ciu2_msired_pp#_ip2 6863232809Sjmallett * 6864232809Sjmallett * CIU2_MSIRED_PPX_IPx (Pass 2) 6865232809Sjmallett * Contains reduced MSI interrupt numbers for delivery to software. 6866232809Sjmallett * Note MSIRED delivery can only be made to PPs, not to IO; thus there are no CIU2_MSIRED_IO registers. 6867232809Sjmallett */ 6868232809Sjmallettunion cvmx_ciu2_msired_ppx_ip2 { 6869232809Sjmallett uint64_t u64; 6870232809Sjmallett struct cvmx_ciu2_msired_ppx_ip2_s { 6871232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6872232809Sjmallett uint64_t reserved_21_63 : 43; 6873232809Sjmallett uint64_t intr : 1; /**< Interrupt pending */ 6874232809Sjmallett uint64_t reserved_17_19 : 3; 6875232809Sjmallett uint64_t newint : 1; /**< New interrupt to be delivered. 6876232809Sjmallett Internal state, for diagnostic use only. | $PR */ 6877232809Sjmallett uint64_t reserved_8_15 : 8; 6878232809Sjmallett uint64_t msi_num : 8; /**< MSI number causing this interrupt. 6879232809Sjmallett If multiple MSIs are pending to the same PP and IP, 6880232809Sjmallett then this contains the numerically lowest MSI number */ 6881232809Sjmallett#else 6882232809Sjmallett uint64_t msi_num : 8; 6883232809Sjmallett uint64_t reserved_8_15 : 8; 6884232809Sjmallett uint64_t newint : 1; 6885232809Sjmallett uint64_t reserved_17_19 : 3; 6886232809Sjmallett uint64_t intr : 1; 6887232809Sjmallett uint64_t reserved_21_63 : 43; 6888232809Sjmallett#endif 6889232809Sjmallett } s; 6890232809Sjmallett struct cvmx_ciu2_msired_ppx_ip2_s cn68xx; 6891232809Sjmallett struct cvmx_ciu2_msired_ppx_ip2_s cn68xxp1; 6892232809Sjmallett}; 6893232809Sjmalletttypedef union cvmx_ciu2_msired_ppx_ip2 cvmx_ciu2_msired_ppx_ip2_t; 6894232809Sjmallett 6895232809Sjmallett/** 6896232809Sjmallett * cvmx_ciu2_msired_pp#_ip3 6897232809Sjmallett */ 6898232809Sjmallettunion cvmx_ciu2_msired_ppx_ip3 { 6899232809Sjmallett uint64_t u64; 6900232809Sjmallett struct cvmx_ciu2_msired_ppx_ip3_s { 6901232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6902232809Sjmallett uint64_t reserved_21_63 : 43; 6903232809Sjmallett uint64_t intr : 1; /**< Interrupt pending */ 6904232809Sjmallett uint64_t reserved_17_19 : 3; 6905232809Sjmallett uint64_t newint : 1; /**< New interrupt to be delivered. 6906232809Sjmallett Internal state, for diagnostic use only. | $PR */ 6907232809Sjmallett uint64_t reserved_8_15 : 8; 6908232809Sjmallett uint64_t msi_num : 8; /**< MSI number causing this interrupt. 6909232809Sjmallett If multiple MSIs are pending to the same PP and IP, 6910232809Sjmallett then this contains the numerically lowest MSI number */ 6911232809Sjmallett#else 6912232809Sjmallett uint64_t msi_num : 8; 6913232809Sjmallett uint64_t reserved_8_15 : 8; 6914232809Sjmallett uint64_t newint : 1; 6915232809Sjmallett uint64_t reserved_17_19 : 3; 6916232809Sjmallett uint64_t intr : 1; 6917232809Sjmallett uint64_t reserved_21_63 : 43; 6918232809Sjmallett#endif 6919232809Sjmallett } s; 6920232809Sjmallett struct cvmx_ciu2_msired_ppx_ip3_s cn68xx; 6921232809Sjmallett struct cvmx_ciu2_msired_ppx_ip3_s cn68xxp1; 6922232809Sjmallett}; 6923232809Sjmalletttypedef union cvmx_ciu2_msired_ppx_ip3 cvmx_ciu2_msired_ppx_ip3_t; 6924232809Sjmallett 6925232809Sjmallett/** 6926232809Sjmallett * cvmx_ciu2_msired_pp#_ip4 6927232809Sjmallett */ 6928232809Sjmallettunion cvmx_ciu2_msired_ppx_ip4 { 6929232809Sjmallett uint64_t u64; 6930232809Sjmallett struct cvmx_ciu2_msired_ppx_ip4_s { 6931232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6932232809Sjmallett uint64_t reserved_21_63 : 43; 6933232809Sjmallett uint64_t intr : 1; /**< Interrupt pending */ 6934232809Sjmallett uint64_t reserved_17_19 : 3; 6935232809Sjmallett uint64_t newint : 1; /**< New interrupt to be delivered. 6936232809Sjmallett Internal state, for diagnostic use only. | $PR */ 6937232809Sjmallett uint64_t reserved_8_15 : 8; 6938232809Sjmallett uint64_t msi_num : 8; /**< MSI number causing this interrupt. 6939232809Sjmallett If multiple MSIs are pending to the same PP and IP, 6940232809Sjmallett then this contains the numerically lowest MSI number */ 6941232809Sjmallett#else 6942232809Sjmallett uint64_t msi_num : 8; 6943232809Sjmallett uint64_t reserved_8_15 : 8; 6944232809Sjmallett uint64_t newint : 1; 6945232809Sjmallett uint64_t reserved_17_19 : 3; 6946232809Sjmallett uint64_t intr : 1; 6947232809Sjmallett uint64_t reserved_21_63 : 43; 6948232809Sjmallett#endif 6949232809Sjmallett } s; 6950232809Sjmallett struct cvmx_ciu2_msired_ppx_ip4_s cn68xx; 6951232809Sjmallett struct cvmx_ciu2_msired_ppx_ip4_s cn68xxp1; 6952232809Sjmallett}; 6953232809Sjmalletttypedef union cvmx_ciu2_msired_ppx_ip4 cvmx_ciu2_msired_ppx_ip4_t; 6954232809Sjmallett 6955232809Sjmallett/** 6956232809Sjmallett * cvmx_ciu2_raw_io#_int_gpio 6957232809Sjmallett */ 6958232809Sjmallettunion cvmx_ciu2_raw_iox_int_gpio { 6959232809Sjmallett uint64_t u64; 6960232809Sjmallett struct cvmx_ciu2_raw_iox_int_gpio_s { 6961232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6962232809Sjmallett uint64_t reserved_16_63 : 48; 6963232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupts 6964232809Sjmallett For GPIO, all 98 RAW readout will be same value */ 6965232809Sjmallett#else 6966232809Sjmallett uint64_t gpio : 16; 6967232809Sjmallett uint64_t reserved_16_63 : 48; 6968232809Sjmallett#endif 6969232809Sjmallett } s; 6970232809Sjmallett struct cvmx_ciu2_raw_iox_int_gpio_s cn68xx; 6971232809Sjmallett struct cvmx_ciu2_raw_iox_int_gpio_s cn68xxp1; 6972232809Sjmallett}; 6973232809Sjmalletttypedef union cvmx_ciu2_raw_iox_int_gpio cvmx_ciu2_raw_iox_int_gpio_t; 6974232809Sjmallett 6975232809Sjmallett/** 6976232809Sjmallett * cvmx_ciu2_raw_io#_int_io 6977232809Sjmallett */ 6978232809Sjmallettunion cvmx_ciu2_raw_iox_int_io { 6979232809Sjmallett uint64_t u64; 6980232809Sjmallett struct cvmx_ciu2_raw_iox_int_io_s { 6981232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6982232809Sjmallett uint64_t reserved_34_63 : 30; 6983232809Sjmallett uint64_t pem : 2; /**< PEMx interrupt 6984232809Sjmallett See PEMx_INT_SUM (enabled by PEMx_INT_ENB) */ 6985232809Sjmallett uint64_t reserved_18_31 : 14; 6986232809Sjmallett uint64_t pci_inta : 2; /**< PCI_INTA software enable 6987232809Sjmallett See CIU_PCI_INTA */ 6988232809Sjmallett uint64_t reserved_13_15 : 3; 6989232809Sjmallett uint64_t msired : 1; /**< MSI summary bit, copy of 6990232809Sjmallett CIU2_MSIRED_PPx_IPy.INT, all IO interrupts 6991232809Sjmallett CIU2_RAW_IOX_INT_IO[MSIRED] always zero. 6992232809Sjmallett This bit may not be functional in pass 1. */ 6993232809Sjmallett uint64_t pci_msi : 4; /**< PCIe/sRIO MSI 6994232809Sjmallett See SLI_MSI_RCVn for bit <40+n> */ 6995232809Sjmallett uint64_t reserved_4_7 : 4; 6996232809Sjmallett uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D 6997232809Sjmallett PCI_INTR[3] = INTD 6998232809Sjmallett PCI_INTR[2] = INTC 6999232809Sjmallett PCI_INTR[1] = INTB 7000232809Sjmallett PCI_INTR[0] = INTA 7001232809Sjmallett Refer to "Receiving Emulated INTA/INTB/ 7002232809Sjmallett INTC/INTD" in the SLI chapter of the spec 7003232809Sjmallett For IO, all 98 RAW readout will be different */ 7004232809Sjmallett#else 7005232809Sjmallett uint64_t pci_intr : 4; 7006232809Sjmallett uint64_t reserved_4_7 : 4; 7007232809Sjmallett uint64_t pci_msi : 4; 7008232809Sjmallett uint64_t msired : 1; 7009232809Sjmallett uint64_t reserved_13_15 : 3; 7010232809Sjmallett uint64_t pci_inta : 2; 7011232809Sjmallett uint64_t reserved_18_31 : 14; 7012232809Sjmallett uint64_t pem : 2; 7013232809Sjmallett uint64_t reserved_34_63 : 30; 7014232809Sjmallett#endif 7015232809Sjmallett } s; 7016232809Sjmallett struct cvmx_ciu2_raw_iox_int_io_s cn68xx; 7017232809Sjmallett struct cvmx_ciu2_raw_iox_int_io_s cn68xxp1; 7018232809Sjmallett}; 7019232809Sjmalletttypedef union cvmx_ciu2_raw_iox_int_io cvmx_ciu2_raw_iox_int_io_t; 7020232809Sjmallett 7021232809Sjmallett/** 7022232809Sjmallett * cvmx_ciu2_raw_io#_int_mem 7023232809Sjmallett */ 7024232809Sjmallettunion cvmx_ciu2_raw_iox_int_mem { 7025232809Sjmallett uint64_t u64; 7026232809Sjmallett struct cvmx_ciu2_raw_iox_int_mem_s { 7027232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7028232809Sjmallett uint64_t reserved_4_63 : 60; 7029232809Sjmallett uint64_t lmc : 4; /**< LMC* interrupt 7030232809Sjmallett See LMC*_INT 7031232809Sjmallett For MEM, all 98 RAW readout will be same value */ 7032232809Sjmallett#else 7033232809Sjmallett uint64_t lmc : 4; 7034232809Sjmallett uint64_t reserved_4_63 : 60; 7035232809Sjmallett#endif 7036232809Sjmallett } s; 7037232809Sjmallett struct cvmx_ciu2_raw_iox_int_mem_s cn68xx; 7038232809Sjmallett struct cvmx_ciu2_raw_iox_int_mem_s cn68xxp1; 7039232809Sjmallett}; 7040232809Sjmalletttypedef union cvmx_ciu2_raw_iox_int_mem cvmx_ciu2_raw_iox_int_mem_t; 7041232809Sjmallett 7042232809Sjmallett/** 7043232809Sjmallett * cvmx_ciu2_raw_io#_int_mio 7044232809Sjmallett */ 7045232809Sjmallettunion cvmx_ciu2_raw_iox_int_mio { 7046232809Sjmallett uint64_t u64; 7047232809Sjmallett struct cvmx_ciu2_raw_iox_int_mio_s { 7048232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7049232809Sjmallett uint64_t rst : 1; /**< MIO RST interrupt 7050232809Sjmallett See MIO_RST_INT */ 7051232809Sjmallett uint64_t reserved_49_62 : 14; 7052232809Sjmallett uint64_t ptp : 1; /**< PTP interrupt 7053232809Sjmallett Set when HW decrements MIO_PTP_EVT_CNT to zero */ 7054232809Sjmallett uint64_t reserved_45_47 : 3; 7055232809Sjmallett uint64_t usb_hci : 1; /**< USB EHCI or OHCI Interrupt 7056232809Sjmallett See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 7057232809Sjmallett uint64_t reserved_41_43 : 3; 7058232809Sjmallett uint64_t usb_uctl : 1; /**< USB UCTL* interrupt 7059232809Sjmallett See UCTL*_INT_REG */ 7060232809Sjmallett uint64_t reserved_38_39 : 2; 7061232809Sjmallett uint64_t uart : 2; /**< Two UART interrupts 7062232809Sjmallett See MIO_UARTn_IIR[IID] for bit <34+n> */ 7063232809Sjmallett uint64_t reserved_34_35 : 2; 7064232809Sjmallett uint64_t twsi : 2; /**< TWSI x Interrupt 7065232809Sjmallett See MIO_TWSx_INT */ 7066232809Sjmallett uint64_t reserved_19_31 : 13; 7067232809Sjmallett uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 7068232809Sjmallett See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 7069232809Sjmallett uint64_t mio : 1; /**< MIO boot interrupt 7070232809Sjmallett See MIO_BOOT_ERR */ 7071232809Sjmallett uint64_t nand : 1; /**< NAND Flash Controller interrupt 7072232809Sjmallett See NDF_INT */ 7073232809Sjmallett uint64_t reserved_12_15 : 4; 7074232809Sjmallett uint64_t timer : 4; /**< General timer interrupts 7075232809Sjmallett Set any time the corresponding CIU timer expires */ 7076232809Sjmallett uint64_t reserved_3_7 : 5; 7077232809Sjmallett uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 7078232809Sjmallett Set any time PIP/IPD drops a packet */ 7079232809Sjmallett uint64_t ssoiq : 1; /**< SSO IQ interrupt 7080232809Sjmallett See SSO_IQ_INT */ 7081232809Sjmallett uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 7082232809Sjmallett See IPD_PORT_QOS_INT* 7083232809Sjmallett For MIO, all 98 RAW readout will be same value */ 7084232809Sjmallett#else 7085232809Sjmallett uint64_t ipdppthr : 1; 7086232809Sjmallett uint64_t ssoiq : 1; 7087232809Sjmallett uint64_t ipd_drp : 1; 7088232809Sjmallett uint64_t reserved_3_7 : 5; 7089232809Sjmallett uint64_t timer : 4; 7090232809Sjmallett uint64_t reserved_12_15 : 4; 7091232809Sjmallett uint64_t nand : 1; 7092232809Sjmallett uint64_t mio : 1; 7093232809Sjmallett uint64_t bootdma : 1; 7094232809Sjmallett uint64_t reserved_19_31 : 13; 7095232809Sjmallett uint64_t twsi : 2; 7096232809Sjmallett uint64_t reserved_34_35 : 2; 7097232809Sjmallett uint64_t uart : 2; 7098232809Sjmallett uint64_t reserved_38_39 : 2; 7099232809Sjmallett uint64_t usb_uctl : 1; 7100232809Sjmallett uint64_t reserved_41_43 : 3; 7101232809Sjmallett uint64_t usb_hci : 1; 7102232809Sjmallett uint64_t reserved_45_47 : 3; 7103232809Sjmallett uint64_t ptp : 1; 7104232809Sjmallett uint64_t reserved_49_62 : 14; 7105232809Sjmallett uint64_t rst : 1; 7106232809Sjmallett#endif 7107232809Sjmallett } s; 7108232809Sjmallett struct cvmx_ciu2_raw_iox_int_mio_s cn68xx; 7109232809Sjmallett struct cvmx_ciu2_raw_iox_int_mio_s cn68xxp1; 7110232809Sjmallett}; 7111232809Sjmalletttypedef union cvmx_ciu2_raw_iox_int_mio cvmx_ciu2_raw_iox_int_mio_t; 7112232809Sjmallett 7113232809Sjmallett/** 7114232809Sjmallett * cvmx_ciu2_raw_io#_int_pkt 7115232809Sjmallett */ 7116232809Sjmallettunion cvmx_ciu2_raw_iox_int_pkt { 7117232809Sjmallett uint64_t u64; 7118232809Sjmallett struct cvmx_ciu2_raw_iox_int_pkt_s { 7119232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7120232809Sjmallett uint64_t reserved_54_63 : 10; 7121232809Sjmallett uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt pulse */ 7122232809Sjmallett uint64_t reserved_49_51 : 3; 7123232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts */ 7124232809Sjmallett uint64_t reserved_41_47 : 7; 7125232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts 7126232809Sjmallett See MIX*_ISR */ 7127232809Sjmallett uint64_t reserved_33_39 : 7; 7128232809Sjmallett uint64_t agl : 1; /**< AGL interrupt 7129232809Sjmallett See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 7130232809Sjmallett uint64_t reserved_13_31 : 19; 7131232809Sjmallett uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse 7132232809Sjmallett Set any time corresponding GMX drops a packet */ 7133232809Sjmallett uint64_t reserved_5_7 : 3; 7134232809Sjmallett uint64_t agx : 5; /**< GMX 0-4 interrupt 7135232809Sjmallett See GMX*_RX*_INT_REG, GMX*_TX_INT_REG, 7136232809Sjmallett PCS0_INT*_REG, PCSX*_INT_REG 7137232809Sjmallett For PKT, all 98 RAW readout will be same value */ 7138232809Sjmallett#else 7139232809Sjmallett uint64_t agx : 5; 7140232809Sjmallett uint64_t reserved_5_7 : 3; 7141232809Sjmallett uint64_t gmx_drp : 5; 7142232809Sjmallett uint64_t reserved_13_31 : 19; 7143232809Sjmallett uint64_t agl : 1; 7144232809Sjmallett uint64_t reserved_33_39 : 7; 7145232809Sjmallett uint64_t mii : 1; 7146232809Sjmallett uint64_t reserved_41_47 : 7; 7147232809Sjmallett uint64_t ilk : 1; 7148232809Sjmallett uint64_t reserved_49_51 : 3; 7149232809Sjmallett uint64_t ilk_drp : 2; 7150232809Sjmallett uint64_t reserved_54_63 : 10; 7151232809Sjmallett#endif 7152232809Sjmallett } s; 7153232809Sjmallett struct cvmx_ciu2_raw_iox_int_pkt_s cn68xx; 7154232809Sjmallett struct cvmx_ciu2_raw_iox_int_pkt_cn68xxp1 { 7155232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7156232809Sjmallett uint64_t reserved_49_63 : 15; 7157232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts */ 7158232809Sjmallett uint64_t reserved_41_47 : 7; 7159232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts 7160232809Sjmallett See MIX*_ISR */ 7161232809Sjmallett uint64_t reserved_33_39 : 7; 7162232809Sjmallett uint64_t agl : 1; /**< AGL interrupt 7163232809Sjmallett See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 7164232809Sjmallett uint64_t reserved_13_31 : 19; 7165232809Sjmallett uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse 7166232809Sjmallett Set any time corresponding GMX drops a packet */ 7167232809Sjmallett uint64_t reserved_5_7 : 3; 7168232809Sjmallett uint64_t agx : 5; /**< GMX 0-4 interrupt 7169232809Sjmallett See GMX*_RX*_INT_REG, GMX*_TX_INT_REG, 7170232809Sjmallett PCS0_INT*_REG, PCSX*_INT_REG 7171232809Sjmallett For PKT, all 98 RAW readout will be same value */ 7172232809Sjmallett#else 7173232809Sjmallett uint64_t agx : 5; 7174232809Sjmallett uint64_t reserved_5_7 : 3; 7175232809Sjmallett uint64_t gmx_drp : 5; 7176232809Sjmallett uint64_t reserved_13_31 : 19; 7177232809Sjmallett uint64_t agl : 1; 7178232809Sjmallett uint64_t reserved_33_39 : 7; 7179232809Sjmallett uint64_t mii : 1; 7180232809Sjmallett uint64_t reserved_41_47 : 7; 7181232809Sjmallett uint64_t ilk : 1; 7182232809Sjmallett uint64_t reserved_49_63 : 15; 7183232809Sjmallett#endif 7184232809Sjmallett } cn68xxp1; 7185232809Sjmallett}; 7186232809Sjmalletttypedef union cvmx_ciu2_raw_iox_int_pkt cvmx_ciu2_raw_iox_int_pkt_t; 7187232809Sjmallett 7188232809Sjmallett/** 7189232809Sjmallett * cvmx_ciu2_raw_io#_int_rml 7190232809Sjmallett */ 7191232809Sjmallettunion cvmx_ciu2_raw_iox_int_rml { 7192232809Sjmallett uint64_t u64; 7193232809Sjmallett struct cvmx_ciu2_raw_iox_int_rml_s { 7194232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7195232809Sjmallett uint64_t reserved_56_63 : 8; 7196232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt 7197232809Sjmallett See TRA_INT_STATUS */ 7198232809Sjmallett uint64_t reserved_49_51 : 3; 7199232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt 7200232809Sjmallett See L2C_INT_REG */ 7201232809Sjmallett uint64_t reserved_41_47 : 7; 7202232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt 7203232809Sjmallett See DFA_ERROR */ 7204232809Sjmallett uint64_t reserved_37_39 : 3; 7205232809Sjmallett uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 7206232809Sjmallett See DPI DMA instruction completion */ 7207232809Sjmallett uint64_t reserved_34_35 : 2; 7208232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt 7209232809Sjmallett See DPI_INT_REG */ 7210232809Sjmallett uint64_t sli : 1; /**< SLI interrupt 7211232809Sjmallett See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 7212232809Sjmallett uint64_t reserved_31_31 : 1; 7213232809Sjmallett uint64_t key : 1; /**< KEY interrupt 7214232809Sjmallett See KEY_INT_SUM */ 7215232809Sjmallett uint64_t rad : 1; /**< RAD interrupt 7216232809Sjmallett See RAD_REG_ERROR */ 7217232809Sjmallett uint64_t tim : 1; /**< TIM interrupt 7218232809Sjmallett See TIM_INT_ECCERR, TIM_INT0 */ 7219232809Sjmallett uint64_t reserved_25_27 : 3; 7220232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt 7221232809Sjmallett See ZIP_INT_REG */ 7222232809Sjmallett uint64_t reserved_17_23 : 7; 7223232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt 7224232809Sjmallett See SSO_ERR */ 7225232809Sjmallett uint64_t reserved_8_15 : 8; 7226232809Sjmallett uint64_t pko : 1; /**< PKO interrupt 7227232809Sjmallett See PKO_REG_ERROR */ 7228232809Sjmallett uint64_t pip : 1; /**< PIP interrupt 7229232809Sjmallett See PIP_INT_REG */ 7230232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt 7231232809Sjmallett See IPD_INT_SUM */ 7232232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt 7233232809Sjmallett See FPA_INT_SUM */ 7234232809Sjmallett uint64_t reserved_1_3 : 3; 7235232809Sjmallett uint64_t iob : 1; /**< IOB interrupt 7236232809Sjmallett See IOB_INT_SUM 7237232809Sjmallett For RML, all 98 RAW readout will be same value */ 7238232809Sjmallett#else 7239232809Sjmallett uint64_t iob : 1; 7240232809Sjmallett uint64_t reserved_1_3 : 3; 7241232809Sjmallett uint64_t fpa : 1; 7242232809Sjmallett uint64_t ipd : 1; 7243232809Sjmallett uint64_t pip : 1; 7244232809Sjmallett uint64_t pko : 1; 7245232809Sjmallett uint64_t reserved_8_15 : 8; 7246232809Sjmallett uint64_t sso : 1; 7247232809Sjmallett uint64_t reserved_17_23 : 7; 7248232809Sjmallett uint64_t zip : 1; 7249232809Sjmallett uint64_t reserved_25_27 : 3; 7250232809Sjmallett uint64_t tim : 1; 7251232809Sjmallett uint64_t rad : 1; 7252232809Sjmallett uint64_t key : 1; 7253232809Sjmallett uint64_t reserved_31_31 : 1; 7254232809Sjmallett uint64_t sli : 1; 7255232809Sjmallett uint64_t dpi : 1; 7256232809Sjmallett uint64_t reserved_34_35 : 2; 7257232809Sjmallett uint64_t dpi_dma : 1; 7258232809Sjmallett uint64_t reserved_37_39 : 3; 7259232809Sjmallett uint64_t dfa : 1; 7260232809Sjmallett uint64_t reserved_41_47 : 7; 7261232809Sjmallett uint64_t l2c : 1; 7262232809Sjmallett uint64_t reserved_49_51 : 3; 7263232809Sjmallett uint64_t trace : 4; 7264232809Sjmallett uint64_t reserved_56_63 : 8; 7265232809Sjmallett#endif 7266232809Sjmallett } s; 7267232809Sjmallett struct cvmx_ciu2_raw_iox_int_rml_s cn68xx; 7268232809Sjmallett struct cvmx_ciu2_raw_iox_int_rml_cn68xxp1 { 7269232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7270232809Sjmallett uint64_t reserved_56_63 : 8; 7271232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt 7272232809Sjmallett See TRA_INT_STATUS */ 7273232809Sjmallett uint64_t reserved_49_51 : 3; 7274232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt 7275232809Sjmallett See L2C_INT_REG */ 7276232809Sjmallett uint64_t reserved_41_47 : 7; 7277232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt 7278232809Sjmallett See DFA_ERROR */ 7279232809Sjmallett uint64_t reserved_34_39 : 6; 7280232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt 7281232809Sjmallett See DPI_INT_REG */ 7282232809Sjmallett uint64_t sli : 1; /**< SLI interrupt 7283232809Sjmallett See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 7284232809Sjmallett uint64_t reserved_31_31 : 1; 7285232809Sjmallett uint64_t key : 1; /**< KEY interrupt 7286232809Sjmallett See KEY_INT_SUM */ 7287232809Sjmallett uint64_t rad : 1; /**< RAD interrupt 7288232809Sjmallett See RAD_REG_ERROR */ 7289232809Sjmallett uint64_t tim : 1; /**< TIM interrupt 7290232809Sjmallett See TIM_INT_ECCERR, TIM_INT0 */ 7291232809Sjmallett uint64_t reserved_25_27 : 3; 7292232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt 7293232809Sjmallett See ZIP_INT_REG */ 7294232809Sjmallett uint64_t reserved_17_23 : 7; 7295232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt 7296232809Sjmallett See SSO_ERR */ 7297232809Sjmallett uint64_t reserved_8_15 : 8; 7298232809Sjmallett uint64_t pko : 1; /**< PKO interrupt 7299232809Sjmallett See PKO_REG_ERROR */ 7300232809Sjmallett uint64_t pip : 1; /**< PIP interrupt 7301232809Sjmallett See PIP_INT_REG */ 7302232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt 7303232809Sjmallett See IPD_INT_SUM */ 7304232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt 7305232809Sjmallett See FPA_INT_SUM */ 7306232809Sjmallett uint64_t reserved_1_3 : 3; 7307232809Sjmallett uint64_t iob : 1; /**< IOB interrupt 7308232809Sjmallett See IOB_INT_SUM 7309232809Sjmallett For RML, all 98 RAW readout will be same value */ 7310232809Sjmallett#else 7311232809Sjmallett uint64_t iob : 1; 7312232809Sjmallett uint64_t reserved_1_3 : 3; 7313232809Sjmallett uint64_t fpa : 1; 7314232809Sjmallett uint64_t ipd : 1; 7315232809Sjmallett uint64_t pip : 1; 7316232809Sjmallett uint64_t pko : 1; 7317232809Sjmallett uint64_t reserved_8_15 : 8; 7318232809Sjmallett uint64_t sso : 1; 7319232809Sjmallett uint64_t reserved_17_23 : 7; 7320232809Sjmallett uint64_t zip : 1; 7321232809Sjmallett uint64_t reserved_25_27 : 3; 7322232809Sjmallett uint64_t tim : 1; 7323232809Sjmallett uint64_t rad : 1; 7324232809Sjmallett uint64_t key : 1; 7325232809Sjmallett uint64_t reserved_31_31 : 1; 7326232809Sjmallett uint64_t sli : 1; 7327232809Sjmallett uint64_t dpi : 1; 7328232809Sjmallett uint64_t reserved_34_39 : 6; 7329232809Sjmallett uint64_t dfa : 1; 7330232809Sjmallett uint64_t reserved_41_47 : 7; 7331232809Sjmallett uint64_t l2c : 1; 7332232809Sjmallett uint64_t reserved_49_51 : 3; 7333232809Sjmallett uint64_t trace : 4; 7334232809Sjmallett uint64_t reserved_56_63 : 8; 7335232809Sjmallett#endif 7336232809Sjmallett } cn68xxp1; 7337232809Sjmallett}; 7338232809Sjmalletttypedef union cvmx_ciu2_raw_iox_int_rml cvmx_ciu2_raw_iox_int_rml_t; 7339232809Sjmallett 7340232809Sjmallett/** 7341232809Sjmallett * cvmx_ciu2_raw_io#_int_wdog 7342232809Sjmallett */ 7343232809Sjmallettunion cvmx_ciu2_raw_iox_int_wdog { 7344232809Sjmallett uint64_t u64; 7345232809Sjmallett struct cvmx_ciu2_raw_iox_int_wdog_s { 7346232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7347232809Sjmallett uint64_t reserved_32_63 : 32; 7348232809Sjmallett uint64_t wdog : 32; /**< 32 watchdog interrupts 7349232809Sjmallett For WDOG, all 98 RAW readout will be same value */ 7350232809Sjmallett#else 7351232809Sjmallett uint64_t wdog : 32; 7352232809Sjmallett uint64_t reserved_32_63 : 32; 7353232809Sjmallett#endif 7354232809Sjmallett } s; 7355232809Sjmallett struct cvmx_ciu2_raw_iox_int_wdog_s cn68xx; 7356232809Sjmallett struct cvmx_ciu2_raw_iox_int_wdog_s cn68xxp1; 7357232809Sjmallett}; 7358232809Sjmalletttypedef union cvmx_ciu2_raw_iox_int_wdog cvmx_ciu2_raw_iox_int_wdog_t; 7359232809Sjmallett 7360232809Sjmallett/** 7361232809Sjmallett * cvmx_ciu2_raw_io#_int_wrkq 7362232809Sjmallett */ 7363232809Sjmallettunion cvmx_ciu2_raw_iox_int_wrkq { 7364232809Sjmallett uint64_t u64; 7365232809Sjmallett struct cvmx_ciu2_raw_iox_int_wrkq_s { 7366232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7367232809Sjmallett uint64_t workq : 64; /**< 64 work queue interrupts 7368232809Sjmallett See SSO_WQ_INT[WQ_INT] 7369232809Sjmallett 1 bit/group. A copy of the R/W1C bit in the SSO. 7370232809Sjmallett For WRKQ, all 98 RAW readout will be same value */ 7371232809Sjmallett#else 7372232809Sjmallett uint64_t workq : 64; 7373232809Sjmallett#endif 7374232809Sjmallett } s; 7375232809Sjmallett struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xx; 7376232809Sjmallett struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xxp1; 7377232809Sjmallett}; 7378232809Sjmalletttypedef union cvmx_ciu2_raw_iox_int_wrkq cvmx_ciu2_raw_iox_int_wrkq_t; 7379232809Sjmallett 7380232809Sjmallett/** 7381232809Sjmallett * cvmx_ciu2_raw_pp#_ip2_gpio 7382232809Sjmallett */ 7383232809Sjmallettunion cvmx_ciu2_raw_ppx_ip2_gpio { 7384232809Sjmallett uint64_t u64; 7385232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_gpio_s { 7386232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7387232809Sjmallett uint64_t reserved_16_63 : 48; 7388232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupts 7389232809Sjmallett For GPIO, all 98 RAW readout will be same value */ 7390232809Sjmallett#else 7391232809Sjmallett uint64_t gpio : 16; 7392232809Sjmallett uint64_t reserved_16_63 : 48; 7393232809Sjmallett#endif 7394232809Sjmallett } s; 7395232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xx; 7396232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xxp1; 7397232809Sjmallett}; 7398232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip2_gpio cvmx_ciu2_raw_ppx_ip2_gpio_t; 7399232809Sjmallett 7400232809Sjmallett/** 7401232809Sjmallett * cvmx_ciu2_raw_pp#_ip2_io 7402232809Sjmallett */ 7403232809Sjmallettunion cvmx_ciu2_raw_ppx_ip2_io { 7404232809Sjmallett uint64_t u64; 7405232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_io_s { 7406232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7407232809Sjmallett uint64_t reserved_34_63 : 30; 7408232809Sjmallett uint64_t pem : 2; /**< PEMx interrupt 7409232809Sjmallett See PEMx_INT_SUM (enabled by PEMx_INT_ENB) */ 7410232809Sjmallett uint64_t reserved_18_31 : 14; 7411232809Sjmallett uint64_t pci_inta : 2; /**< PCI_INTA software enable 7412232809Sjmallett See CIU_PCI_INTA */ 7413232809Sjmallett uint64_t reserved_13_15 : 3; 7414232809Sjmallett uint64_t msired : 1; /**< MSI summary bit, copy of 7415232809Sjmallett CIU2_MSIRED_PPx_IPy.INT, all IO interrupts 7416232809Sjmallett CIU2_RAW_IOX_INT_IO[MSIRED] always zero. 7417232809Sjmallett This bit may not be functional in pass 1. */ 7418232809Sjmallett uint64_t pci_msi : 4; /**< PCIe/sRIO MSI 7419232809Sjmallett See SLI_MSI_RCVn for bit <40+n> */ 7420232809Sjmallett uint64_t reserved_4_7 : 4; 7421232809Sjmallett uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D 7422232809Sjmallett PCI_INTR[3] = INTD 7423232809Sjmallett PCI_INTR[2] = INTC 7424232809Sjmallett PCI_INTR[1] = INTB 7425232809Sjmallett PCI_INTR[0] = INTA 7426232809Sjmallett Refer to "Receiving Emulated INTA/INTB/ 7427232809Sjmallett INTC/INTD" in the SLI chapter of the spec 7428232809Sjmallett For IO, all 98 RAW readout will be different */ 7429232809Sjmallett#else 7430232809Sjmallett uint64_t pci_intr : 4; 7431232809Sjmallett uint64_t reserved_4_7 : 4; 7432232809Sjmallett uint64_t pci_msi : 4; 7433232809Sjmallett uint64_t msired : 1; 7434232809Sjmallett uint64_t reserved_13_15 : 3; 7435232809Sjmallett uint64_t pci_inta : 2; 7436232809Sjmallett uint64_t reserved_18_31 : 14; 7437232809Sjmallett uint64_t pem : 2; 7438232809Sjmallett uint64_t reserved_34_63 : 30; 7439232809Sjmallett#endif 7440232809Sjmallett } s; 7441232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xx; 7442232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xxp1; 7443232809Sjmallett}; 7444232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip2_io cvmx_ciu2_raw_ppx_ip2_io_t; 7445232809Sjmallett 7446232809Sjmallett/** 7447232809Sjmallett * cvmx_ciu2_raw_pp#_ip2_mem 7448232809Sjmallett */ 7449232809Sjmallettunion cvmx_ciu2_raw_ppx_ip2_mem { 7450232809Sjmallett uint64_t u64; 7451232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_mem_s { 7452232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7453232809Sjmallett uint64_t reserved_4_63 : 60; 7454232809Sjmallett uint64_t lmc : 4; /**< LMC* interrupt 7455232809Sjmallett See LMC*_INT 7456232809Sjmallett For MEM, all 98 RAW readout will be same value */ 7457232809Sjmallett#else 7458232809Sjmallett uint64_t lmc : 4; 7459232809Sjmallett uint64_t reserved_4_63 : 60; 7460232809Sjmallett#endif 7461232809Sjmallett } s; 7462232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xx; 7463232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xxp1; 7464232809Sjmallett}; 7465232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip2_mem cvmx_ciu2_raw_ppx_ip2_mem_t; 7466232809Sjmallett 7467232809Sjmallett/** 7468232809Sjmallett * cvmx_ciu2_raw_pp#_ip2_mio 7469232809Sjmallett */ 7470232809Sjmallettunion cvmx_ciu2_raw_ppx_ip2_mio { 7471232809Sjmallett uint64_t u64; 7472232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_mio_s { 7473232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7474232809Sjmallett uint64_t rst : 1; /**< MIO RST interrupt 7475232809Sjmallett See MIO_RST_INT */ 7476232809Sjmallett uint64_t reserved_49_62 : 14; 7477232809Sjmallett uint64_t ptp : 1; /**< PTP interrupt 7478232809Sjmallett Set when HW decrements MIO_PTP_EVT_CNT to zero */ 7479232809Sjmallett uint64_t reserved_45_47 : 3; 7480232809Sjmallett uint64_t usb_hci : 1; /**< USB EHCI or OHCI Interrupt 7481232809Sjmallett See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 7482232809Sjmallett uint64_t reserved_41_43 : 3; 7483232809Sjmallett uint64_t usb_uctl : 1; /**< USB UCTL* interrupt 7484232809Sjmallett See UCTL*_INT_REG */ 7485232809Sjmallett uint64_t reserved_38_39 : 2; 7486232809Sjmallett uint64_t uart : 2; /**< Two UART interrupts 7487232809Sjmallett See MIO_UARTn_IIR[IID] for bit <34+n> */ 7488232809Sjmallett uint64_t reserved_34_35 : 2; 7489232809Sjmallett uint64_t twsi : 2; /**< TWSI x Interrupt 7490232809Sjmallett See MIO_TWSx_INT */ 7491232809Sjmallett uint64_t reserved_19_31 : 13; 7492232809Sjmallett uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 7493232809Sjmallett See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 7494232809Sjmallett uint64_t mio : 1; /**< MIO boot interrupt 7495232809Sjmallett See MIO_BOOT_ERR */ 7496232809Sjmallett uint64_t nand : 1; /**< NAND Flash Controller interrupt 7497232809Sjmallett See NDF_INT */ 7498232809Sjmallett uint64_t reserved_12_15 : 4; 7499232809Sjmallett uint64_t timer : 4; /**< General timer interrupts 7500232809Sjmallett Set any time the corresponding CIU timer expires */ 7501232809Sjmallett uint64_t reserved_3_7 : 5; 7502232809Sjmallett uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 7503232809Sjmallett Set any time PIP/IPD drops a packet */ 7504232809Sjmallett uint64_t ssoiq : 1; /**< SSO IQ interrupt 7505232809Sjmallett See SSO_IQ_INT */ 7506232809Sjmallett uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 7507232809Sjmallett See IPD_PORT_QOS_INT* 7508232809Sjmallett For MIO, all 98 RAW readout will be same value */ 7509232809Sjmallett#else 7510232809Sjmallett uint64_t ipdppthr : 1; 7511232809Sjmallett uint64_t ssoiq : 1; 7512232809Sjmallett uint64_t ipd_drp : 1; 7513232809Sjmallett uint64_t reserved_3_7 : 5; 7514232809Sjmallett uint64_t timer : 4; 7515232809Sjmallett uint64_t reserved_12_15 : 4; 7516232809Sjmallett uint64_t nand : 1; 7517232809Sjmallett uint64_t mio : 1; 7518232809Sjmallett uint64_t bootdma : 1; 7519232809Sjmallett uint64_t reserved_19_31 : 13; 7520232809Sjmallett uint64_t twsi : 2; 7521232809Sjmallett uint64_t reserved_34_35 : 2; 7522232809Sjmallett uint64_t uart : 2; 7523232809Sjmallett uint64_t reserved_38_39 : 2; 7524232809Sjmallett uint64_t usb_uctl : 1; 7525232809Sjmallett uint64_t reserved_41_43 : 3; 7526232809Sjmallett uint64_t usb_hci : 1; 7527232809Sjmallett uint64_t reserved_45_47 : 3; 7528232809Sjmallett uint64_t ptp : 1; 7529232809Sjmallett uint64_t reserved_49_62 : 14; 7530232809Sjmallett uint64_t rst : 1; 7531232809Sjmallett#endif 7532232809Sjmallett } s; 7533232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xx; 7534232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xxp1; 7535232809Sjmallett}; 7536232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip2_mio cvmx_ciu2_raw_ppx_ip2_mio_t; 7537232809Sjmallett 7538232809Sjmallett/** 7539232809Sjmallett * cvmx_ciu2_raw_pp#_ip2_pkt 7540232809Sjmallett */ 7541232809Sjmallettunion cvmx_ciu2_raw_ppx_ip2_pkt { 7542232809Sjmallett uint64_t u64; 7543232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_pkt_s { 7544232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7545232809Sjmallett uint64_t reserved_54_63 : 10; 7546232809Sjmallett uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt pulse */ 7547232809Sjmallett uint64_t reserved_49_51 : 3; 7548232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts */ 7549232809Sjmallett uint64_t reserved_41_47 : 7; 7550232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts 7551232809Sjmallett See MIX*_ISR */ 7552232809Sjmallett uint64_t reserved_33_39 : 7; 7553232809Sjmallett uint64_t agl : 1; /**< AGL interrupt 7554232809Sjmallett See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 7555232809Sjmallett uint64_t reserved_13_31 : 19; 7556232809Sjmallett uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse 7557232809Sjmallett Set any time corresponding GMX drops a packet */ 7558232809Sjmallett uint64_t reserved_5_7 : 3; 7559232809Sjmallett uint64_t agx : 5; /**< GMX 0-4 interrupt 7560232809Sjmallett See GMX*_RX*_INT_REG, GMX*_TX_INT_REG, 7561232809Sjmallett PCS0_INT*_REG, PCSX*_INT_REG 7562232809Sjmallett For PKT, all 98 RAW readout will be same value */ 7563232809Sjmallett#else 7564232809Sjmallett uint64_t agx : 5; 7565232809Sjmallett uint64_t reserved_5_7 : 3; 7566232809Sjmallett uint64_t gmx_drp : 5; 7567232809Sjmallett uint64_t reserved_13_31 : 19; 7568232809Sjmallett uint64_t agl : 1; 7569232809Sjmallett uint64_t reserved_33_39 : 7; 7570232809Sjmallett uint64_t mii : 1; 7571232809Sjmallett uint64_t reserved_41_47 : 7; 7572232809Sjmallett uint64_t ilk : 1; 7573232809Sjmallett uint64_t reserved_49_51 : 3; 7574232809Sjmallett uint64_t ilk_drp : 2; 7575232809Sjmallett uint64_t reserved_54_63 : 10; 7576232809Sjmallett#endif 7577232809Sjmallett } s; 7578232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_pkt_s cn68xx; 7579232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_pkt_cn68xxp1 { 7580232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7581232809Sjmallett uint64_t reserved_49_63 : 15; 7582232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts */ 7583232809Sjmallett uint64_t reserved_41_47 : 7; 7584232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts 7585232809Sjmallett See MIX*_ISR */ 7586232809Sjmallett uint64_t reserved_33_39 : 7; 7587232809Sjmallett uint64_t agl : 1; /**< AGL interrupt 7588232809Sjmallett See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 7589232809Sjmallett uint64_t reserved_13_31 : 19; 7590232809Sjmallett uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse 7591232809Sjmallett Set any time corresponding GMX drops a packet */ 7592232809Sjmallett uint64_t reserved_5_7 : 3; 7593232809Sjmallett uint64_t agx : 5; /**< GMX 0-4 interrupt 7594232809Sjmallett See GMX*_RX*_INT_REG, GMX*_TX_INT_REG, 7595232809Sjmallett PCS0_INT*_REG, PCSX*_INT_REG 7596232809Sjmallett For PKT, all 98 RAW readout will be same value */ 7597232809Sjmallett#else 7598232809Sjmallett uint64_t agx : 5; 7599232809Sjmallett uint64_t reserved_5_7 : 3; 7600232809Sjmallett uint64_t gmx_drp : 5; 7601232809Sjmallett uint64_t reserved_13_31 : 19; 7602232809Sjmallett uint64_t agl : 1; 7603232809Sjmallett uint64_t reserved_33_39 : 7; 7604232809Sjmallett uint64_t mii : 1; 7605232809Sjmallett uint64_t reserved_41_47 : 7; 7606232809Sjmallett uint64_t ilk : 1; 7607232809Sjmallett uint64_t reserved_49_63 : 15; 7608232809Sjmallett#endif 7609232809Sjmallett } cn68xxp1; 7610232809Sjmallett}; 7611232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip2_pkt cvmx_ciu2_raw_ppx_ip2_pkt_t; 7612232809Sjmallett 7613232809Sjmallett/** 7614232809Sjmallett * cvmx_ciu2_raw_pp#_ip2_rml 7615232809Sjmallett */ 7616232809Sjmallettunion cvmx_ciu2_raw_ppx_ip2_rml { 7617232809Sjmallett uint64_t u64; 7618232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_rml_s { 7619232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7620232809Sjmallett uint64_t reserved_56_63 : 8; 7621232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt 7622232809Sjmallett See TRA_INT_STATUS */ 7623232809Sjmallett uint64_t reserved_49_51 : 3; 7624232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt 7625232809Sjmallett See L2C_INT_REG */ 7626232809Sjmallett uint64_t reserved_41_47 : 7; 7627232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt 7628232809Sjmallett See DFA_ERROR */ 7629232809Sjmallett uint64_t reserved_37_39 : 3; 7630232809Sjmallett uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 7631232809Sjmallett See DPI DMA instruction completion */ 7632232809Sjmallett uint64_t reserved_34_35 : 2; 7633232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt 7634232809Sjmallett See DPI_INT_REG */ 7635232809Sjmallett uint64_t sli : 1; /**< SLI interrupt 7636232809Sjmallett See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 7637232809Sjmallett uint64_t reserved_31_31 : 1; 7638232809Sjmallett uint64_t key : 1; /**< KEY interrupt 7639232809Sjmallett See KEY_INT_SUM */ 7640232809Sjmallett uint64_t rad : 1; /**< RAD interrupt 7641232809Sjmallett See RAD_REG_ERROR */ 7642232809Sjmallett uint64_t tim : 1; /**< TIM interrupt 7643232809Sjmallett See TIM_INT_ECCERR, TIM_INT0 */ 7644232809Sjmallett uint64_t reserved_25_27 : 3; 7645232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt 7646232809Sjmallett See ZIP_INT_REG */ 7647232809Sjmallett uint64_t reserved_17_23 : 7; 7648232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt 7649232809Sjmallett See SSO_ERR */ 7650232809Sjmallett uint64_t reserved_8_15 : 8; 7651232809Sjmallett uint64_t pko : 1; /**< PKO interrupt 7652232809Sjmallett See PKO_REG_ERROR */ 7653232809Sjmallett uint64_t pip : 1; /**< PIP interrupt 7654232809Sjmallett See PIP_INT_REG */ 7655232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt 7656232809Sjmallett See IPD_INT_SUM */ 7657232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt 7658232809Sjmallett See FPA_INT_SUM */ 7659232809Sjmallett uint64_t reserved_1_3 : 3; 7660232809Sjmallett uint64_t iob : 1; /**< IOB interrupt 7661232809Sjmallett See IOB_INT_SUM 7662232809Sjmallett For RML, all 98 RAW readout will be same value */ 7663232809Sjmallett#else 7664232809Sjmallett uint64_t iob : 1; 7665232809Sjmallett uint64_t reserved_1_3 : 3; 7666232809Sjmallett uint64_t fpa : 1; 7667232809Sjmallett uint64_t ipd : 1; 7668232809Sjmallett uint64_t pip : 1; 7669232809Sjmallett uint64_t pko : 1; 7670232809Sjmallett uint64_t reserved_8_15 : 8; 7671232809Sjmallett uint64_t sso : 1; 7672232809Sjmallett uint64_t reserved_17_23 : 7; 7673232809Sjmallett uint64_t zip : 1; 7674232809Sjmallett uint64_t reserved_25_27 : 3; 7675232809Sjmallett uint64_t tim : 1; 7676232809Sjmallett uint64_t rad : 1; 7677232809Sjmallett uint64_t key : 1; 7678232809Sjmallett uint64_t reserved_31_31 : 1; 7679232809Sjmallett uint64_t sli : 1; 7680232809Sjmallett uint64_t dpi : 1; 7681232809Sjmallett uint64_t reserved_34_35 : 2; 7682232809Sjmallett uint64_t dpi_dma : 1; 7683232809Sjmallett uint64_t reserved_37_39 : 3; 7684232809Sjmallett uint64_t dfa : 1; 7685232809Sjmallett uint64_t reserved_41_47 : 7; 7686232809Sjmallett uint64_t l2c : 1; 7687232809Sjmallett uint64_t reserved_49_51 : 3; 7688232809Sjmallett uint64_t trace : 4; 7689232809Sjmallett uint64_t reserved_56_63 : 8; 7690232809Sjmallett#endif 7691232809Sjmallett } s; 7692232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_rml_s cn68xx; 7693232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_rml_cn68xxp1 { 7694232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7695232809Sjmallett uint64_t reserved_56_63 : 8; 7696232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt 7697232809Sjmallett See TRA_INT_STATUS */ 7698232809Sjmallett uint64_t reserved_49_51 : 3; 7699232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt 7700232809Sjmallett See L2C_INT_REG */ 7701232809Sjmallett uint64_t reserved_41_47 : 7; 7702232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt 7703232809Sjmallett See DFA_ERROR */ 7704232809Sjmallett uint64_t reserved_34_39 : 6; 7705232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt 7706232809Sjmallett See DPI_INT_REG */ 7707232809Sjmallett uint64_t sli : 1; /**< SLI interrupt 7708232809Sjmallett See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 7709232809Sjmallett uint64_t reserved_31_31 : 1; 7710232809Sjmallett uint64_t key : 1; /**< KEY interrupt 7711232809Sjmallett See KEY_INT_SUM */ 7712232809Sjmallett uint64_t rad : 1; /**< RAD interrupt 7713232809Sjmallett See RAD_REG_ERROR */ 7714232809Sjmallett uint64_t tim : 1; /**< TIM interrupt 7715232809Sjmallett See TIM_INT_ECCERR, TIM_INT0 */ 7716232809Sjmallett uint64_t reserved_25_27 : 3; 7717232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt 7718232809Sjmallett See ZIP_INT_REG */ 7719232809Sjmallett uint64_t reserved_17_23 : 7; 7720232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt 7721232809Sjmallett See SSO_ERR */ 7722232809Sjmallett uint64_t reserved_8_15 : 8; 7723232809Sjmallett uint64_t pko : 1; /**< PKO interrupt 7724232809Sjmallett See PKO_REG_ERROR */ 7725232809Sjmallett uint64_t pip : 1; /**< PIP interrupt 7726232809Sjmallett See PIP_INT_REG */ 7727232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt 7728232809Sjmallett See IPD_INT_SUM */ 7729232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt 7730232809Sjmallett See FPA_INT_SUM */ 7731232809Sjmallett uint64_t reserved_1_3 : 3; 7732232809Sjmallett uint64_t iob : 1; /**< IOB interrupt 7733232809Sjmallett See IOB_INT_SUM 7734232809Sjmallett For RML, all 98 RAW readout will be same value */ 7735232809Sjmallett#else 7736232809Sjmallett uint64_t iob : 1; 7737232809Sjmallett uint64_t reserved_1_3 : 3; 7738232809Sjmallett uint64_t fpa : 1; 7739232809Sjmallett uint64_t ipd : 1; 7740232809Sjmallett uint64_t pip : 1; 7741232809Sjmallett uint64_t pko : 1; 7742232809Sjmallett uint64_t reserved_8_15 : 8; 7743232809Sjmallett uint64_t sso : 1; 7744232809Sjmallett uint64_t reserved_17_23 : 7; 7745232809Sjmallett uint64_t zip : 1; 7746232809Sjmallett uint64_t reserved_25_27 : 3; 7747232809Sjmallett uint64_t tim : 1; 7748232809Sjmallett uint64_t rad : 1; 7749232809Sjmallett uint64_t key : 1; 7750232809Sjmallett uint64_t reserved_31_31 : 1; 7751232809Sjmallett uint64_t sli : 1; 7752232809Sjmallett uint64_t dpi : 1; 7753232809Sjmallett uint64_t reserved_34_39 : 6; 7754232809Sjmallett uint64_t dfa : 1; 7755232809Sjmallett uint64_t reserved_41_47 : 7; 7756232809Sjmallett uint64_t l2c : 1; 7757232809Sjmallett uint64_t reserved_49_51 : 3; 7758232809Sjmallett uint64_t trace : 4; 7759232809Sjmallett uint64_t reserved_56_63 : 8; 7760232809Sjmallett#endif 7761232809Sjmallett } cn68xxp1; 7762232809Sjmallett}; 7763232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip2_rml cvmx_ciu2_raw_ppx_ip2_rml_t; 7764232809Sjmallett 7765232809Sjmallett/** 7766232809Sjmallett * cvmx_ciu2_raw_pp#_ip2_wdog 7767232809Sjmallett */ 7768232809Sjmallettunion cvmx_ciu2_raw_ppx_ip2_wdog { 7769232809Sjmallett uint64_t u64; 7770232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_wdog_s { 7771232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7772232809Sjmallett uint64_t reserved_32_63 : 32; 7773232809Sjmallett uint64_t wdog : 32; /**< 32 watchdog interrupts 7774232809Sjmallett For WDOG, all 98 RAW readout will be same value */ 7775232809Sjmallett#else 7776232809Sjmallett uint64_t wdog : 32; 7777232809Sjmallett uint64_t reserved_32_63 : 32; 7778232809Sjmallett#endif 7779232809Sjmallett } s; 7780232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xx; 7781232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xxp1; 7782232809Sjmallett}; 7783232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip2_wdog cvmx_ciu2_raw_ppx_ip2_wdog_t; 7784232809Sjmallett 7785232809Sjmallett/** 7786232809Sjmallett * cvmx_ciu2_raw_pp#_ip2_wrkq 7787232809Sjmallett */ 7788232809Sjmallettunion cvmx_ciu2_raw_ppx_ip2_wrkq { 7789232809Sjmallett uint64_t u64; 7790232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_wrkq_s { 7791232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7792232809Sjmallett uint64_t workq : 64; /**< 64 work queue interrupts 7793232809Sjmallett See SSO_WQ_INT[WQ_INT] 7794232809Sjmallett 1 bit/group. A copy of the R/W1C bit in the SSO. 7795232809Sjmallett For WRKQ, all 98 RAW readout will be same value */ 7796232809Sjmallett#else 7797232809Sjmallett uint64_t workq : 64; 7798232809Sjmallett#endif 7799232809Sjmallett } s; 7800232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xx; 7801232809Sjmallett struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xxp1; 7802232809Sjmallett}; 7803232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip2_wrkq cvmx_ciu2_raw_ppx_ip2_wrkq_t; 7804232809Sjmallett 7805232809Sjmallett/** 7806232809Sjmallett * cvmx_ciu2_raw_pp#_ip3_gpio 7807232809Sjmallett */ 7808232809Sjmallettunion cvmx_ciu2_raw_ppx_ip3_gpio { 7809232809Sjmallett uint64_t u64; 7810232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_gpio_s { 7811232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7812232809Sjmallett uint64_t reserved_16_63 : 48; 7813232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupts 7814232809Sjmallett For GPIO, all 98 RAW readout will be same value */ 7815232809Sjmallett#else 7816232809Sjmallett uint64_t gpio : 16; 7817232809Sjmallett uint64_t reserved_16_63 : 48; 7818232809Sjmallett#endif 7819232809Sjmallett } s; 7820232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xx; 7821232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xxp1; 7822232809Sjmallett}; 7823232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip3_gpio cvmx_ciu2_raw_ppx_ip3_gpio_t; 7824232809Sjmallett 7825232809Sjmallett/** 7826232809Sjmallett * cvmx_ciu2_raw_pp#_ip3_io 7827232809Sjmallett */ 7828232809Sjmallettunion cvmx_ciu2_raw_ppx_ip3_io { 7829232809Sjmallett uint64_t u64; 7830232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_io_s { 7831232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7832232809Sjmallett uint64_t reserved_34_63 : 30; 7833232809Sjmallett uint64_t pem : 2; /**< PEMx interrupt 7834232809Sjmallett See PEMx_INT_SUM (enabled by PEMx_INT_ENB) */ 7835232809Sjmallett uint64_t reserved_18_31 : 14; 7836232809Sjmallett uint64_t pci_inta : 2; /**< PCI_INTA software enable 7837232809Sjmallett See CIU_PCI_INTA */ 7838232809Sjmallett uint64_t reserved_13_15 : 3; 7839232809Sjmallett uint64_t msired : 1; /**< MSI summary bit, copy of 7840232809Sjmallett CIU2_MSIRED_PPx_IPy.INT, all IO interrupts 7841232809Sjmallett CIU2_RAW_IOX_INT_IO[MSIRED] always zero. 7842232809Sjmallett This bit may not be functional in pass 1. */ 7843232809Sjmallett uint64_t pci_msi : 4; /**< PCIe/sRIO MSI 7844232809Sjmallett See SLI_MSI_RCVn for bit <40+n> */ 7845232809Sjmallett uint64_t reserved_4_7 : 4; 7846232809Sjmallett uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D 7847232809Sjmallett PCI_INTR[3] = INTD 7848232809Sjmallett PCI_INTR[2] = INTC 7849232809Sjmallett PCI_INTR[1] = INTB 7850232809Sjmallett PCI_INTR[0] = INTA 7851232809Sjmallett Refer to "Receiving Emulated INTA/INTB/ 7852232809Sjmallett INTC/INTD" in the SLI chapter of the spec 7853232809Sjmallett For IO, all 98 RAW readout will be different */ 7854232809Sjmallett#else 7855232809Sjmallett uint64_t pci_intr : 4; 7856232809Sjmallett uint64_t reserved_4_7 : 4; 7857232809Sjmallett uint64_t pci_msi : 4; 7858232809Sjmallett uint64_t msired : 1; 7859232809Sjmallett uint64_t reserved_13_15 : 3; 7860232809Sjmallett uint64_t pci_inta : 2; 7861232809Sjmallett uint64_t reserved_18_31 : 14; 7862232809Sjmallett uint64_t pem : 2; 7863232809Sjmallett uint64_t reserved_34_63 : 30; 7864232809Sjmallett#endif 7865232809Sjmallett } s; 7866232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xx; 7867232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xxp1; 7868232809Sjmallett}; 7869232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip3_io cvmx_ciu2_raw_ppx_ip3_io_t; 7870232809Sjmallett 7871232809Sjmallett/** 7872232809Sjmallett * cvmx_ciu2_raw_pp#_ip3_mem 7873232809Sjmallett */ 7874232809Sjmallettunion cvmx_ciu2_raw_ppx_ip3_mem { 7875232809Sjmallett uint64_t u64; 7876232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_mem_s { 7877232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7878232809Sjmallett uint64_t reserved_4_63 : 60; 7879232809Sjmallett uint64_t lmc : 4; /**< LMC* interrupt 7880232809Sjmallett See LMC*_INT 7881232809Sjmallett For MEM, all 98 RAW readout will be same value */ 7882232809Sjmallett#else 7883232809Sjmallett uint64_t lmc : 4; 7884232809Sjmallett uint64_t reserved_4_63 : 60; 7885232809Sjmallett#endif 7886232809Sjmallett } s; 7887232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xx; 7888232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xxp1; 7889232809Sjmallett}; 7890232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip3_mem cvmx_ciu2_raw_ppx_ip3_mem_t; 7891232809Sjmallett 7892232809Sjmallett/** 7893232809Sjmallett * cvmx_ciu2_raw_pp#_ip3_mio 7894232809Sjmallett */ 7895232809Sjmallettunion cvmx_ciu2_raw_ppx_ip3_mio { 7896232809Sjmallett uint64_t u64; 7897232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_mio_s { 7898232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7899232809Sjmallett uint64_t rst : 1; /**< MIO RST interrupt 7900232809Sjmallett See MIO_RST_INT */ 7901232809Sjmallett uint64_t reserved_49_62 : 14; 7902232809Sjmallett uint64_t ptp : 1; /**< PTP interrupt 7903232809Sjmallett Set when HW decrements MIO_PTP_EVT_CNT to zero */ 7904232809Sjmallett uint64_t reserved_45_47 : 3; 7905232809Sjmallett uint64_t usb_hci : 1; /**< USB EHCI or OHCI Interrupt 7906232809Sjmallett See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 7907232809Sjmallett uint64_t reserved_41_43 : 3; 7908232809Sjmallett uint64_t usb_uctl : 1; /**< USB UCTL* interrupt 7909232809Sjmallett See UCTL*_INT_REG */ 7910232809Sjmallett uint64_t reserved_38_39 : 2; 7911232809Sjmallett uint64_t uart : 2; /**< Two UART interrupts 7912232809Sjmallett See MIO_UARTn_IIR[IID] for bit <34+n> */ 7913232809Sjmallett uint64_t reserved_34_35 : 2; 7914232809Sjmallett uint64_t twsi : 2; /**< TWSI x Interrupt 7915232809Sjmallett See MIO_TWSx_INT */ 7916232809Sjmallett uint64_t reserved_19_31 : 13; 7917232809Sjmallett uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 7918232809Sjmallett See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 7919232809Sjmallett uint64_t mio : 1; /**< MIO boot interrupt 7920232809Sjmallett See MIO_BOOT_ERR */ 7921232809Sjmallett uint64_t nand : 1; /**< NAND Flash Controller interrupt 7922232809Sjmallett See NDF_INT */ 7923232809Sjmallett uint64_t reserved_12_15 : 4; 7924232809Sjmallett uint64_t timer : 4; /**< General timer interrupts 7925232809Sjmallett Set any time the corresponding CIU timer expires */ 7926232809Sjmallett uint64_t reserved_3_7 : 5; 7927232809Sjmallett uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 7928232809Sjmallett Set any time PIP/IPD drops a packet */ 7929232809Sjmallett uint64_t ssoiq : 1; /**< SSO IQ interrupt 7930232809Sjmallett See SSO_IQ_INT */ 7931232809Sjmallett uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 7932232809Sjmallett See IPD_PORT_QOS_INT* 7933232809Sjmallett For MIO, all 98 RAW readout will be same value */ 7934232809Sjmallett#else 7935232809Sjmallett uint64_t ipdppthr : 1; 7936232809Sjmallett uint64_t ssoiq : 1; 7937232809Sjmallett uint64_t ipd_drp : 1; 7938232809Sjmallett uint64_t reserved_3_7 : 5; 7939232809Sjmallett uint64_t timer : 4; 7940232809Sjmallett uint64_t reserved_12_15 : 4; 7941232809Sjmallett uint64_t nand : 1; 7942232809Sjmallett uint64_t mio : 1; 7943232809Sjmallett uint64_t bootdma : 1; 7944232809Sjmallett uint64_t reserved_19_31 : 13; 7945232809Sjmallett uint64_t twsi : 2; 7946232809Sjmallett uint64_t reserved_34_35 : 2; 7947232809Sjmallett uint64_t uart : 2; 7948232809Sjmallett uint64_t reserved_38_39 : 2; 7949232809Sjmallett uint64_t usb_uctl : 1; 7950232809Sjmallett uint64_t reserved_41_43 : 3; 7951232809Sjmallett uint64_t usb_hci : 1; 7952232809Sjmallett uint64_t reserved_45_47 : 3; 7953232809Sjmallett uint64_t ptp : 1; 7954232809Sjmallett uint64_t reserved_49_62 : 14; 7955232809Sjmallett uint64_t rst : 1; 7956232809Sjmallett#endif 7957232809Sjmallett } s; 7958232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xx; 7959232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xxp1; 7960232809Sjmallett}; 7961232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip3_mio cvmx_ciu2_raw_ppx_ip3_mio_t; 7962232809Sjmallett 7963232809Sjmallett/** 7964232809Sjmallett * cvmx_ciu2_raw_pp#_ip3_pkt 7965232809Sjmallett */ 7966232809Sjmallettunion cvmx_ciu2_raw_ppx_ip3_pkt { 7967232809Sjmallett uint64_t u64; 7968232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_pkt_s { 7969232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7970232809Sjmallett uint64_t reserved_54_63 : 10; 7971232809Sjmallett uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt pulse */ 7972232809Sjmallett uint64_t reserved_49_51 : 3; 7973232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts */ 7974232809Sjmallett uint64_t reserved_41_47 : 7; 7975232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts 7976232809Sjmallett See MIX*_ISR */ 7977232809Sjmallett uint64_t reserved_33_39 : 7; 7978232809Sjmallett uint64_t agl : 1; /**< AGL interrupt 7979232809Sjmallett See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 7980232809Sjmallett uint64_t reserved_13_31 : 19; 7981232809Sjmallett uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse 7982232809Sjmallett Set any time corresponding GMX drops a packet */ 7983232809Sjmallett uint64_t reserved_5_7 : 3; 7984232809Sjmallett uint64_t agx : 5; /**< GMX 0-4 interrupt 7985232809Sjmallett See GMX*_RX*_INT_REG, GMX*_TX_INT_REG, 7986232809Sjmallett PCS0_INT*_REG, PCSX*_INT_REG 7987232809Sjmallett For PKT, all 98 RAW readout will be same value */ 7988232809Sjmallett#else 7989232809Sjmallett uint64_t agx : 5; 7990232809Sjmallett uint64_t reserved_5_7 : 3; 7991232809Sjmallett uint64_t gmx_drp : 5; 7992232809Sjmallett uint64_t reserved_13_31 : 19; 7993232809Sjmallett uint64_t agl : 1; 7994232809Sjmallett uint64_t reserved_33_39 : 7; 7995232809Sjmallett uint64_t mii : 1; 7996232809Sjmallett uint64_t reserved_41_47 : 7; 7997232809Sjmallett uint64_t ilk : 1; 7998232809Sjmallett uint64_t reserved_49_51 : 3; 7999232809Sjmallett uint64_t ilk_drp : 2; 8000232809Sjmallett uint64_t reserved_54_63 : 10; 8001232809Sjmallett#endif 8002232809Sjmallett } s; 8003232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_pkt_s cn68xx; 8004232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_pkt_cn68xxp1 { 8005232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8006232809Sjmallett uint64_t reserved_49_63 : 15; 8007232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts */ 8008232809Sjmallett uint64_t reserved_41_47 : 7; 8009232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts 8010232809Sjmallett See MIX*_ISR */ 8011232809Sjmallett uint64_t reserved_33_39 : 7; 8012232809Sjmallett uint64_t agl : 1; /**< AGL interrupt 8013232809Sjmallett See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 8014232809Sjmallett uint64_t reserved_13_31 : 19; 8015232809Sjmallett uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse 8016232809Sjmallett Set any time corresponding GMX drops a packet */ 8017232809Sjmallett uint64_t reserved_5_7 : 3; 8018232809Sjmallett uint64_t agx : 5; /**< GMX 0-4 interrupt 8019232809Sjmallett See GMX*_RX*_INT_REG, GMX*_TX_INT_REG, 8020232809Sjmallett PCS0_INT*_REG, PCSX*_INT_REG 8021232809Sjmallett For PKT, all 98 RAW readout will be same value */ 8022232809Sjmallett#else 8023232809Sjmallett uint64_t agx : 5; 8024232809Sjmallett uint64_t reserved_5_7 : 3; 8025232809Sjmallett uint64_t gmx_drp : 5; 8026232809Sjmallett uint64_t reserved_13_31 : 19; 8027232809Sjmallett uint64_t agl : 1; 8028232809Sjmallett uint64_t reserved_33_39 : 7; 8029232809Sjmallett uint64_t mii : 1; 8030232809Sjmallett uint64_t reserved_41_47 : 7; 8031232809Sjmallett uint64_t ilk : 1; 8032232809Sjmallett uint64_t reserved_49_63 : 15; 8033232809Sjmallett#endif 8034232809Sjmallett } cn68xxp1; 8035232809Sjmallett}; 8036232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip3_pkt cvmx_ciu2_raw_ppx_ip3_pkt_t; 8037232809Sjmallett 8038232809Sjmallett/** 8039232809Sjmallett * cvmx_ciu2_raw_pp#_ip3_rml 8040232809Sjmallett */ 8041232809Sjmallettunion cvmx_ciu2_raw_ppx_ip3_rml { 8042232809Sjmallett uint64_t u64; 8043232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_rml_s { 8044232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8045232809Sjmallett uint64_t reserved_56_63 : 8; 8046232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt 8047232809Sjmallett See TRA_INT_STATUS */ 8048232809Sjmallett uint64_t reserved_49_51 : 3; 8049232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt 8050232809Sjmallett See L2C_INT_REG */ 8051232809Sjmallett uint64_t reserved_41_47 : 7; 8052232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt 8053232809Sjmallett See DFA_ERROR */ 8054232809Sjmallett uint64_t reserved_37_39 : 3; 8055232809Sjmallett uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 8056232809Sjmallett See DPI DMA instruction completion */ 8057232809Sjmallett uint64_t reserved_34_35 : 2; 8058232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt 8059232809Sjmallett See DPI_INT_REG */ 8060232809Sjmallett uint64_t sli : 1; /**< SLI interrupt 8061232809Sjmallett See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 8062232809Sjmallett uint64_t reserved_31_31 : 1; 8063232809Sjmallett uint64_t key : 1; /**< KEY interrupt 8064232809Sjmallett See KEY_INT_SUM */ 8065232809Sjmallett uint64_t rad : 1; /**< RAD interrupt 8066232809Sjmallett See RAD_REG_ERROR */ 8067232809Sjmallett uint64_t tim : 1; /**< TIM interrupt 8068232809Sjmallett See TIM_INT_ECCERR, TIM_INT0 */ 8069232809Sjmallett uint64_t reserved_25_27 : 3; 8070232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt 8071232809Sjmallett See ZIP_INT_REG */ 8072232809Sjmallett uint64_t reserved_17_23 : 7; 8073232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt 8074232809Sjmallett See SSO_ERR */ 8075232809Sjmallett uint64_t reserved_8_15 : 8; 8076232809Sjmallett uint64_t pko : 1; /**< PKO interrupt 8077232809Sjmallett See PKO_REG_ERROR */ 8078232809Sjmallett uint64_t pip : 1; /**< PIP interrupt 8079232809Sjmallett See PIP_INT_REG */ 8080232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt 8081232809Sjmallett See IPD_INT_SUM */ 8082232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt 8083232809Sjmallett See FPA_INT_SUM */ 8084232809Sjmallett uint64_t reserved_1_3 : 3; 8085232809Sjmallett uint64_t iob : 1; /**< IOB interrupt 8086232809Sjmallett See IOB_INT_SUM 8087232809Sjmallett For RML, all 98 RAW readout will be same value */ 8088232809Sjmallett#else 8089232809Sjmallett uint64_t iob : 1; 8090232809Sjmallett uint64_t reserved_1_3 : 3; 8091232809Sjmallett uint64_t fpa : 1; 8092232809Sjmallett uint64_t ipd : 1; 8093232809Sjmallett uint64_t pip : 1; 8094232809Sjmallett uint64_t pko : 1; 8095232809Sjmallett uint64_t reserved_8_15 : 8; 8096232809Sjmallett uint64_t sso : 1; 8097232809Sjmallett uint64_t reserved_17_23 : 7; 8098232809Sjmallett uint64_t zip : 1; 8099232809Sjmallett uint64_t reserved_25_27 : 3; 8100232809Sjmallett uint64_t tim : 1; 8101232809Sjmallett uint64_t rad : 1; 8102232809Sjmallett uint64_t key : 1; 8103232809Sjmallett uint64_t reserved_31_31 : 1; 8104232809Sjmallett uint64_t sli : 1; 8105232809Sjmallett uint64_t dpi : 1; 8106232809Sjmallett uint64_t reserved_34_35 : 2; 8107232809Sjmallett uint64_t dpi_dma : 1; 8108232809Sjmallett uint64_t reserved_37_39 : 3; 8109232809Sjmallett uint64_t dfa : 1; 8110232809Sjmallett uint64_t reserved_41_47 : 7; 8111232809Sjmallett uint64_t l2c : 1; 8112232809Sjmallett uint64_t reserved_49_51 : 3; 8113232809Sjmallett uint64_t trace : 4; 8114232809Sjmallett uint64_t reserved_56_63 : 8; 8115232809Sjmallett#endif 8116232809Sjmallett } s; 8117232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_rml_s cn68xx; 8118232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_rml_cn68xxp1 { 8119232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8120232809Sjmallett uint64_t reserved_56_63 : 8; 8121232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt 8122232809Sjmallett See TRA_INT_STATUS */ 8123232809Sjmallett uint64_t reserved_49_51 : 3; 8124232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt 8125232809Sjmallett See L2C_INT_REG */ 8126232809Sjmallett uint64_t reserved_41_47 : 7; 8127232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt 8128232809Sjmallett See DFA_ERROR */ 8129232809Sjmallett uint64_t reserved_34_39 : 6; 8130232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt 8131232809Sjmallett See DPI_INT_REG */ 8132232809Sjmallett uint64_t sli : 1; /**< SLI interrupt 8133232809Sjmallett See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 8134232809Sjmallett uint64_t reserved_31_31 : 1; 8135232809Sjmallett uint64_t key : 1; /**< KEY interrupt 8136232809Sjmallett See KEY_INT_SUM */ 8137232809Sjmallett uint64_t rad : 1; /**< RAD interrupt 8138232809Sjmallett See RAD_REG_ERROR */ 8139232809Sjmallett uint64_t tim : 1; /**< TIM interrupt 8140232809Sjmallett See TIM_INT_ECCERR, TIM_INT0 */ 8141232809Sjmallett uint64_t reserved_25_27 : 3; 8142232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt 8143232809Sjmallett See ZIP_INT_REG */ 8144232809Sjmallett uint64_t reserved_17_23 : 7; 8145232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt 8146232809Sjmallett See SSO_ERR */ 8147232809Sjmallett uint64_t reserved_8_15 : 8; 8148232809Sjmallett uint64_t pko : 1; /**< PKO interrupt 8149232809Sjmallett See PKO_REG_ERROR */ 8150232809Sjmallett uint64_t pip : 1; /**< PIP interrupt 8151232809Sjmallett See PIP_INT_REG */ 8152232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt 8153232809Sjmallett See IPD_INT_SUM */ 8154232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt 8155232809Sjmallett See FPA_INT_SUM */ 8156232809Sjmallett uint64_t reserved_1_3 : 3; 8157232809Sjmallett uint64_t iob : 1; /**< IOB interrupt 8158232809Sjmallett See IOB_INT_SUM 8159232809Sjmallett For RML, all 98 RAW readout will be same value */ 8160232809Sjmallett#else 8161232809Sjmallett uint64_t iob : 1; 8162232809Sjmallett uint64_t reserved_1_3 : 3; 8163232809Sjmallett uint64_t fpa : 1; 8164232809Sjmallett uint64_t ipd : 1; 8165232809Sjmallett uint64_t pip : 1; 8166232809Sjmallett uint64_t pko : 1; 8167232809Sjmallett uint64_t reserved_8_15 : 8; 8168232809Sjmallett uint64_t sso : 1; 8169232809Sjmallett uint64_t reserved_17_23 : 7; 8170232809Sjmallett uint64_t zip : 1; 8171232809Sjmallett uint64_t reserved_25_27 : 3; 8172232809Sjmallett uint64_t tim : 1; 8173232809Sjmallett uint64_t rad : 1; 8174232809Sjmallett uint64_t key : 1; 8175232809Sjmallett uint64_t reserved_31_31 : 1; 8176232809Sjmallett uint64_t sli : 1; 8177232809Sjmallett uint64_t dpi : 1; 8178232809Sjmallett uint64_t reserved_34_39 : 6; 8179232809Sjmallett uint64_t dfa : 1; 8180232809Sjmallett uint64_t reserved_41_47 : 7; 8181232809Sjmallett uint64_t l2c : 1; 8182232809Sjmallett uint64_t reserved_49_51 : 3; 8183232809Sjmallett uint64_t trace : 4; 8184232809Sjmallett uint64_t reserved_56_63 : 8; 8185232809Sjmallett#endif 8186232809Sjmallett } cn68xxp1; 8187232809Sjmallett}; 8188232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip3_rml cvmx_ciu2_raw_ppx_ip3_rml_t; 8189232809Sjmallett 8190232809Sjmallett/** 8191232809Sjmallett * cvmx_ciu2_raw_pp#_ip3_wdog 8192232809Sjmallett */ 8193232809Sjmallettunion cvmx_ciu2_raw_ppx_ip3_wdog { 8194232809Sjmallett uint64_t u64; 8195232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_wdog_s { 8196232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8197232809Sjmallett uint64_t reserved_32_63 : 32; 8198232809Sjmallett uint64_t wdog : 32; /**< 32 watchdog interrupts 8199232809Sjmallett For WDOG, all 98 RAW readout will be same value */ 8200232809Sjmallett#else 8201232809Sjmallett uint64_t wdog : 32; 8202232809Sjmallett uint64_t reserved_32_63 : 32; 8203232809Sjmallett#endif 8204232809Sjmallett } s; 8205232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xx; 8206232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xxp1; 8207232809Sjmallett}; 8208232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip3_wdog cvmx_ciu2_raw_ppx_ip3_wdog_t; 8209232809Sjmallett 8210232809Sjmallett/** 8211232809Sjmallett * cvmx_ciu2_raw_pp#_ip3_wrkq 8212232809Sjmallett */ 8213232809Sjmallettunion cvmx_ciu2_raw_ppx_ip3_wrkq { 8214232809Sjmallett uint64_t u64; 8215232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_wrkq_s { 8216232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8217232809Sjmallett uint64_t workq : 64; /**< 64 work queue interrupts 8218232809Sjmallett See SSO_WQ_INT[WQ_INT] 8219232809Sjmallett 1 bit/group. A copy of the R/W1C bit in the SSO. 8220232809Sjmallett For WRKQ, all 98 RAW readout will be same value */ 8221232809Sjmallett#else 8222232809Sjmallett uint64_t workq : 64; 8223232809Sjmallett#endif 8224232809Sjmallett } s; 8225232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xx; 8226232809Sjmallett struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xxp1; 8227232809Sjmallett}; 8228232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip3_wrkq cvmx_ciu2_raw_ppx_ip3_wrkq_t; 8229232809Sjmallett 8230232809Sjmallett/** 8231232809Sjmallett * cvmx_ciu2_raw_pp#_ip4_gpio 8232232809Sjmallett */ 8233232809Sjmallettunion cvmx_ciu2_raw_ppx_ip4_gpio { 8234232809Sjmallett uint64_t u64; 8235232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_gpio_s { 8236232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8237232809Sjmallett uint64_t reserved_16_63 : 48; 8238232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupts 8239232809Sjmallett For GPIO, all 98 RAW readout will be same value */ 8240232809Sjmallett#else 8241232809Sjmallett uint64_t gpio : 16; 8242232809Sjmallett uint64_t reserved_16_63 : 48; 8243232809Sjmallett#endif 8244232809Sjmallett } s; 8245232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xx; 8246232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xxp1; 8247232809Sjmallett}; 8248232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip4_gpio cvmx_ciu2_raw_ppx_ip4_gpio_t; 8249232809Sjmallett 8250232809Sjmallett/** 8251232809Sjmallett * cvmx_ciu2_raw_pp#_ip4_io 8252232809Sjmallett */ 8253232809Sjmallettunion cvmx_ciu2_raw_ppx_ip4_io { 8254232809Sjmallett uint64_t u64; 8255232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_io_s { 8256232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8257232809Sjmallett uint64_t reserved_34_63 : 30; 8258232809Sjmallett uint64_t pem : 2; /**< PEMx interrupt 8259232809Sjmallett See PEMx_INT_SUM (enabled by PEMx_INT_ENB) */ 8260232809Sjmallett uint64_t reserved_18_31 : 14; 8261232809Sjmallett uint64_t pci_inta : 2; /**< PCI_INTA software enable 8262232809Sjmallett See CIU_PCI_INTA */ 8263232809Sjmallett uint64_t reserved_13_15 : 3; 8264232809Sjmallett uint64_t msired : 1; /**< MSI summary bit, copy of 8265232809Sjmallett CIU2_MSIRED_PPx_IPy.INT, all IO interrupts 8266232809Sjmallett CIU2_RAW_IOX_INT_IO[MSIRED] always zero. 8267232809Sjmallett This bit may not be functional in pass 1. */ 8268232809Sjmallett uint64_t pci_msi : 4; /**< PCIe/sRIO MSI 8269232809Sjmallett See SLI_MSI_RCVn for bit <40+n> */ 8270232809Sjmallett uint64_t reserved_4_7 : 4; 8271232809Sjmallett uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D 8272232809Sjmallett PCI_INTR[3] = INTD 8273232809Sjmallett PCI_INTR[2] = INTC 8274232809Sjmallett PCI_INTR[1] = INTB 8275232809Sjmallett PCI_INTR[0] = INTA 8276232809Sjmallett Refer to "Receiving Emulated INTA/INTB/ 8277232809Sjmallett INTC/INTD" in the SLI chapter of the spec 8278232809Sjmallett For IO, all 98 RAW readout will be different */ 8279232809Sjmallett#else 8280232809Sjmallett uint64_t pci_intr : 4; 8281232809Sjmallett uint64_t reserved_4_7 : 4; 8282232809Sjmallett uint64_t pci_msi : 4; 8283232809Sjmallett uint64_t msired : 1; 8284232809Sjmallett uint64_t reserved_13_15 : 3; 8285232809Sjmallett uint64_t pci_inta : 2; 8286232809Sjmallett uint64_t reserved_18_31 : 14; 8287232809Sjmallett uint64_t pem : 2; 8288232809Sjmallett uint64_t reserved_34_63 : 30; 8289232809Sjmallett#endif 8290232809Sjmallett } s; 8291232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xx; 8292232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xxp1; 8293232809Sjmallett}; 8294232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip4_io cvmx_ciu2_raw_ppx_ip4_io_t; 8295232809Sjmallett 8296232809Sjmallett/** 8297232809Sjmallett * cvmx_ciu2_raw_pp#_ip4_mem 8298232809Sjmallett */ 8299232809Sjmallettunion cvmx_ciu2_raw_ppx_ip4_mem { 8300232809Sjmallett uint64_t u64; 8301232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_mem_s { 8302232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8303232809Sjmallett uint64_t reserved_4_63 : 60; 8304232809Sjmallett uint64_t lmc : 4; /**< LMC* interrupt 8305232809Sjmallett See LMC*_INT 8306232809Sjmallett For MEM, all 98 RAW readout will be same value */ 8307232809Sjmallett#else 8308232809Sjmallett uint64_t lmc : 4; 8309232809Sjmallett uint64_t reserved_4_63 : 60; 8310232809Sjmallett#endif 8311232809Sjmallett } s; 8312232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xx; 8313232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xxp1; 8314232809Sjmallett}; 8315232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip4_mem cvmx_ciu2_raw_ppx_ip4_mem_t; 8316232809Sjmallett 8317232809Sjmallett/** 8318232809Sjmallett * cvmx_ciu2_raw_pp#_ip4_mio 8319232809Sjmallett */ 8320232809Sjmallettunion cvmx_ciu2_raw_ppx_ip4_mio { 8321232809Sjmallett uint64_t u64; 8322232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_mio_s { 8323232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8324232809Sjmallett uint64_t rst : 1; /**< MIO RST interrupt 8325232809Sjmallett See MIO_RST_INT */ 8326232809Sjmallett uint64_t reserved_49_62 : 14; 8327232809Sjmallett uint64_t ptp : 1; /**< PTP interrupt 8328232809Sjmallett Set when HW decrements MIO_PTP_EVT_CNT to zero */ 8329232809Sjmallett uint64_t reserved_45_47 : 3; 8330232809Sjmallett uint64_t usb_hci : 1; /**< USB EHCI or OHCI Interrupt 8331232809Sjmallett See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 8332232809Sjmallett uint64_t reserved_41_43 : 3; 8333232809Sjmallett uint64_t usb_uctl : 1; /**< USB UCTL* interrupt 8334232809Sjmallett See UCTL*_INT_REG */ 8335232809Sjmallett uint64_t reserved_38_39 : 2; 8336232809Sjmallett uint64_t uart : 2; /**< Two UART interrupts 8337232809Sjmallett See MIO_UARTn_IIR[IID] for bit <34+n> */ 8338232809Sjmallett uint64_t reserved_34_35 : 2; 8339232809Sjmallett uint64_t twsi : 2; /**< TWSI x Interrupt 8340232809Sjmallett See MIO_TWSx_INT */ 8341232809Sjmallett uint64_t reserved_19_31 : 13; 8342232809Sjmallett uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 8343232809Sjmallett See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 8344232809Sjmallett uint64_t mio : 1; /**< MIO boot interrupt 8345232809Sjmallett See MIO_BOOT_ERR */ 8346232809Sjmallett uint64_t nand : 1; /**< NAND Flash Controller interrupt 8347232809Sjmallett See NDF_INT */ 8348232809Sjmallett uint64_t reserved_12_15 : 4; 8349232809Sjmallett uint64_t timer : 4; /**< General timer interrupts 8350232809Sjmallett Set any time the corresponding CIU timer expires */ 8351232809Sjmallett uint64_t reserved_3_7 : 5; 8352232809Sjmallett uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 8353232809Sjmallett Set any time PIP/IPD drops a packet */ 8354232809Sjmallett uint64_t ssoiq : 1; /**< SSO IQ interrupt 8355232809Sjmallett See SSO_IQ_INT */ 8356232809Sjmallett uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 8357232809Sjmallett See IPD_PORT_QOS_INT* 8358232809Sjmallett For MIO, all 98 RAW readout will be same value */ 8359232809Sjmallett#else 8360232809Sjmallett uint64_t ipdppthr : 1; 8361232809Sjmallett uint64_t ssoiq : 1; 8362232809Sjmallett uint64_t ipd_drp : 1; 8363232809Sjmallett uint64_t reserved_3_7 : 5; 8364232809Sjmallett uint64_t timer : 4; 8365232809Sjmallett uint64_t reserved_12_15 : 4; 8366232809Sjmallett uint64_t nand : 1; 8367232809Sjmallett uint64_t mio : 1; 8368232809Sjmallett uint64_t bootdma : 1; 8369232809Sjmallett uint64_t reserved_19_31 : 13; 8370232809Sjmallett uint64_t twsi : 2; 8371232809Sjmallett uint64_t reserved_34_35 : 2; 8372232809Sjmallett uint64_t uart : 2; 8373232809Sjmallett uint64_t reserved_38_39 : 2; 8374232809Sjmallett uint64_t usb_uctl : 1; 8375232809Sjmallett uint64_t reserved_41_43 : 3; 8376232809Sjmallett uint64_t usb_hci : 1; 8377232809Sjmallett uint64_t reserved_45_47 : 3; 8378232809Sjmallett uint64_t ptp : 1; 8379232809Sjmallett uint64_t reserved_49_62 : 14; 8380232809Sjmallett uint64_t rst : 1; 8381232809Sjmallett#endif 8382232809Sjmallett } s; 8383232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xx; 8384232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xxp1; 8385232809Sjmallett}; 8386232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip4_mio cvmx_ciu2_raw_ppx_ip4_mio_t; 8387232809Sjmallett 8388232809Sjmallett/** 8389232809Sjmallett * cvmx_ciu2_raw_pp#_ip4_pkt 8390232809Sjmallett */ 8391232809Sjmallettunion cvmx_ciu2_raw_ppx_ip4_pkt { 8392232809Sjmallett uint64_t u64; 8393232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_pkt_s { 8394232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8395232809Sjmallett uint64_t reserved_54_63 : 10; 8396232809Sjmallett uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt pulse */ 8397232809Sjmallett uint64_t reserved_49_51 : 3; 8398232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts */ 8399232809Sjmallett uint64_t reserved_41_47 : 7; 8400232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts 8401232809Sjmallett See MIX*_ISR */ 8402232809Sjmallett uint64_t reserved_33_39 : 7; 8403232809Sjmallett uint64_t agl : 1; /**< AGL interrupt 8404232809Sjmallett See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 8405232809Sjmallett uint64_t reserved_13_31 : 19; 8406232809Sjmallett uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse 8407232809Sjmallett Set any time corresponding GMX drops a packet */ 8408232809Sjmallett uint64_t reserved_5_7 : 3; 8409232809Sjmallett uint64_t agx : 5; /**< GMX 0-4 interrupt 8410232809Sjmallett See GMX*_RX*_INT_REG, GMX*_TX_INT_REG, 8411232809Sjmallett PCS0_INT*_REG, PCSX*_INT_REG 8412232809Sjmallett For PKT, all 98 RAW readout will be same value */ 8413232809Sjmallett#else 8414232809Sjmallett uint64_t agx : 5; 8415232809Sjmallett uint64_t reserved_5_7 : 3; 8416232809Sjmallett uint64_t gmx_drp : 5; 8417232809Sjmallett uint64_t reserved_13_31 : 19; 8418232809Sjmallett uint64_t agl : 1; 8419232809Sjmallett uint64_t reserved_33_39 : 7; 8420232809Sjmallett uint64_t mii : 1; 8421232809Sjmallett uint64_t reserved_41_47 : 7; 8422232809Sjmallett uint64_t ilk : 1; 8423232809Sjmallett uint64_t reserved_49_51 : 3; 8424232809Sjmallett uint64_t ilk_drp : 2; 8425232809Sjmallett uint64_t reserved_54_63 : 10; 8426232809Sjmallett#endif 8427232809Sjmallett } s; 8428232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_pkt_s cn68xx; 8429232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_pkt_cn68xxp1 { 8430232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8431232809Sjmallett uint64_t reserved_49_63 : 15; 8432232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts */ 8433232809Sjmallett uint64_t reserved_41_47 : 7; 8434232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts 8435232809Sjmallett See MIX*_ISR */ 8436232809Sjmallett uint64_t reserved_33_39 : 7; 8437232809Sjmallett uint64_t agl : 1; /**< AGL interrupt 8438232809Sjmallett See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 8439232809Sjmallett uint64_t reserved_13_31 : 19; 8440232809Sjmallett uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse 8441232809Sjmallett Set any time corresponding GMX drops a packet */ 8442232809Sjmallett uint64_t reserved_5_7 : 3; 8443232809Sjmallett uint64_t agx : 5; /**< GMX 0-4 interrupt 8444232809Sjmallett See GMX*_RX*_INT_REG, GMX*_TX_INT_REG, 8445232809Sjmallett PCS0_INT*_REG, PCSX*_INT_REG 8446232809Sjmallett For PKT, all 98 RAW readout will be same value */ 8447232809Sjmallett#else 8448232809Sjmallett uint64_t agx : 5; 8449232809Sjmallett uint64_t reserved_5_7 : 3; 8450232809Sjmallett uint64_t gmx_drp : 5; 8451232809Sjmallett uint64_t reserved_13_31 : 19; 8452232809Sjmallett uint64_t agl : 1; 8453232809Sjmallett uint64_t reserved_33_39 : 7; 8454232809Sjmallett uint64_t mii : 1; 8455232809Sjmallett uint64_t reserved_41_47 : 7; 8456232809Sjmallett uint64_t ilk : 1; 8457232809Sjmallett uint64_t reserved_49_63 : 15; 8458232809Sjmallett#endif 8459232809Sjmallett } cn68xxp1; 8460232809Sjmallett}; 8461232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip4_pkt cvmx_ciu2_raw_ppx_ip4_pkt_t; 8462232809Sjmallett 8463232809Sjmallett/** 8464232809Sjmallett * cvmx_ciu2_raw_pp#_ip4_rml 8465232809Sjmallett */ 8466232809Sjmallettunion cvmx_ciu2_raw_ppx_ip4_rml { 8467232809Sjmallett uint64_t u64; 8468232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_rml_s { 8469232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8470232809Sjmallett uint64_t reserved_56_63 : 8; 8471232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt 8472232809Sjmallett See TRA_INT_STATUS */ 8473232809Sjmallett uint64_t reserved_49_51 : 3; 8474232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt 8475232809Sjmallett See L2C_INT_REG */ 8476232809Sjmallett uint64_t reserved_41_47 : 7; 8477232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt 8478232809Sjmallett See DFA_ERROR */ 8479232809Sjmallett uint64_t reserved_37_39 : 3; 8480232809Sjmallett uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 8481232809Sjmallett See DPI DMA instruction completion */ 8482232809Sjmallett uint64_t reserved_34_35 : 2; 8483232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt 8484232809Sjmallett See DPI_INT_REG */ 8485232809Sjmallett uint64_t sli : 1; /**< SLI interrupt 8486232809Sjmallett See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 8487232809Sjmallett uint64_t reserved_31_31 : 1; 8488232809Sjmallett uint64_t key : 1; /**< KEY interrupt 8489232809Sjmallett See KEY_INT_SUM */ 8490232809Sjmallett uint64_t rad : 1; /**< RAD interrupt 8491232809Sjmallett See RAD_REG_ERROR */ 8492232809Sjmallett uint64_t tim : 1; /**< TIM interrupt 8493232809Sjmallett See TIM_INT_ECCERR, TIM_INT0 */ 8494232809Sjmallett uint64_t reserved_25_27 : 3; 8495232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt 8496232809Sjmallett See ZIP_INT_REG */ 8497232809Sjmallett uint64_t reserved_17_23 : 7; 8498232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt 8499232809Sjmallett See SSO_ERR */ 8500232809Sjmallett uint64_t reserved_8_15 : 8; 8501232809Sjmallett uint64_t pko : 1; /**< PKO interrupt 8502232809Sjmallett See PKO_REG_ERROR */ 8503232809Sjmallett uint64_t pip : 1; /**< PIP interrupt 8504232809Sjmallett See PIP_INT_REG */ 8505232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt 8506232809Sjmallett See IPD_INT_SUM */ 8507232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt 8508232809Sjmallett See FPA_INT_SUM */ 8509232809Sjmallett uint64_t reserved_1_3 : 3; 8510232809Sjmallett uint64_t iob : 1; /**< IOB interrupt 8511232809Sjmallett See IOB_INT_SUM 8512232809Sjmallett For RML, all 98 RAW readout will be same value */ 8513232809Sjmallett#else 8514232809Sjmallett uint64_t iob : 1; 8515232809Sjmallett uint64_t reserved_1_3 : 3; 8516232809Sjmallett uint64_t fpa : 1; 8517232809Sjmallett uint64_t ipd : 1; 8518232809Sjmallett uint64_t pip : 1; 8519232809Sjmallett uint64_t pko : 1; 8520232809Sjmallett uint64_t reserved_8_15 : 8; 8521232809Sjmallett uint64_t sso : 1; 8522232809Sjmallett uint64_t reserved_17_23 : 7; 8523232809Sjmallett uint64_t zip : 1; 8524232809Sjmallett uint64_t reserved_25_27 : 3; 8525232809Sjmallett uint64_t tim : 1; 8526232809Sjmallett uint64_t rad : 1; 8527232809Sjmallett uint64_t key : 1; 8528232809Sjmallett uint64_t reserved_31_31 : 1; 8529232809Sjmallett uint64_t sli : 1; 8530232809Sjmallett uint64_t dpi : 1; 8531232809Sjmallett uint64_t reserved_34_35 : 2; 8532232809Sjmallett uint64_t dpi_dma : 1; 8533232809Sjmallett uint64_t reserved_37_39 : 3; 8534232809Sjmallett uint64_t dfa : 1; 8535232809Sjmallett uint64_t reserved_41_47 : 7; 8536232809Sjmallett uint64_t l2c : 1; 8537232809Sjmallett uint64_t reserved_49_51 : 3; 8538232809Sjmallett uint64_t trace : 4; 8539232809Sjmallett uint64_t reserved_56_63 : 8; 8540232809Sjmallett#endif 8541232809Sjmallett } s; 8542232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_rml_s cn68xx; 8543232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_rml_cn68xxp1 { 8544232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8545232809Sjmallett uint64_t reserved_56_63 : 8; 8546232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt 8547232809Sjmallett See TRA_INT_STATUS */ 8548232809Sjmallett uint64_t reserved_49_51 : 3; 8549232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt 8550232809Sjmallett See L2C_INT_REG */ 8551232809Sjmallett uint64_t reserved_41_47 : 7; 8552232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt 8553232809Sjmallett See DFA_ERROR */ 8554232809Sjmallett uint64_t reserved_34_39 : 6; 8555232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt 8556232809Sjmallett See DPI_INT_REG */ 8557232809Sjmallett uint64_t sli : 1; /**< SLI interrupt 8558232809Sjmallett See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 8559232809Sjmallett uint64_t reserved_31_31 : 1; 8560232809Sjmallett uint64_t key : 1; /**< KEY interrupt 8561232809Sjmallett See KEY_INT_SUM */ 8562232809Sjmallett uint64_t rad : 1; /**< RAD interrupt 8563232809Sjmallett See RAD_REG_ERROR */ 8564232809Sjmallett uint64_t tim : 1; /**< TIM interrupt 8565232809Sjmallett See TIM_INT_ECCERR, TIM_INT0 */ 8566232809Sjmallett uint64_t reserved_25_27 : 3; 8567232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt 8568232809Sjmallett See ZIP_INT_REG */ 8569232809Sjmallett uint64_t reserved_17_23 : 7; 8570232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt 8571232809Sjmallett See SSO_ERR */ 8572232809Sjmallett uint64_t reserved_8_15 : 8; 8573232809Sjmallett uint64_t pko : 1; /**< PKO interrupt 8574232809Sjmallett See PKO_REG_ERROR */ 8575232809Sjmallett uint64_t pip : 1; /**< PIP interrupt 8576232809Sjmallett See PIP_INT_REG */ 8577232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt 8578232809Sjmallett See IPD_INT_SUM */ 8579232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt 8580232809Sjmallett See FPA_INT_SUM */ 8581232809Sjmallett uint64_t reserved_1_3 : 3; 8582232809Sjmallett uint64_t iob : 1; /**< IOB interrupt 8583232809Sjmallett See IOB_INT_SUM 8584232809Sjmallett For RML, all 98 RAW readout will be same value */ 8585232809Sjmallett#else 8586232809Sjmallett uint64_t iob : 1; 8587232809Sjmallett uint64_t reserved_1_3 : 3; 8588232809Sjmallett uint64_t fpa : 1; 8589232809Sjmallett uint64_t ipd : 1; 8590232809Sjmallett uint64_t pip : 1; 8591232809Sjmallett uint64_t pko : 1; 8592232809Sjmallett uint64_t reserved_8_15 : 8; 8593232809Sjmallett uint64_t sso : 1; 8594232809Sjmallett uint64_t reserved_17_23 : 7; 8595232809Sjmallett uint64_t zip : 1; 8596232809Sjmallett uint64_t reserved_25_27 : 3; 8597232809Sjmallett uint64_t tim : 1; 8598232809Sjmallett uint64_t rad : 1; 8599232809Sjmallett uint64_t key : 1; 8600232809Sjmallett uint64_t reserved_31_31 : 1; 8601232809Sjmallett uint64_t sli : 1; 8602232809Sjmallett uint64_t dpi : 1; 8603232809Sjmallett uint64_t reserved_34_39 : 6; 8604232809Sjmallett uint64_t dfa : 1; 8605232809Sjmallett uint64_t reserved_41_47 : 7; 8606232809Sjmallett uint64_t l2c : 1; 8607232809Sjmallett uint64_t reserved_49_51 : 3; 8608232809Sjmallett uint64_t trace : 4; 8609232809Sjmallett uint64_t reserved_56_63 : 8; 8610232809Sjmallett#endif 8611232809Sjmallett } cn68xxp1; 8612232809Sjmallett}; 8613232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip4_rml cvmx_ciu2_raw_ppx_ip4_rml_t; 8614232809Sjmallett 8615232809Sjmallett/** 8616232809Sjmallett * cvmx_ciu2_raw_pp#_ip4_wdog 8617232809Sjmallett */ 8618232809Sjmallettunion cvmx_ciu2_raw_ppx_ip4_wdog { 8619232809Sjmallett uint64_t u64; 8620232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_wdog_s { 8621232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8622232809Sjmallett uint64_t reserved_32_63 : 32; 8623232809Sjmallett uint64_t wdog : 32; /**< 32 watchdog interrupts 8624232809Sjmallett For WDOG, all 98 RAW readout will be same value */ 8625232809Sjmallett#else 8626232809Sjmallett uint64_t wdog : 32; 8627232809Sjmallett uint64_t reserved_32_63 : 32; 8628232809Sjmallett#endif 8629232809Sjmallett } s; 8630232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xx; 8631232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xxp1; 8632232809Sjmallett}; 8633232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip4_wdog cvmx_ciu2_raw_ppx_ip4_wdog_t; 8634232809Sjmallett 8635232809Sjmallett/** 8636232809Sjmallett * cvmx_ciu2_raw_pp#_ip4_wrkq 8637232809Sjmallett */ 8638232809Sjmallettunion cvmx_ciu2_raw_ppx_ip4_wrkq { 8639232809Sjmallett uint64_t u64; 8640232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_wrkq_s { 8641232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8642232809Sjmallett uint64_t workq : 64; /**< 64 work queue interrupts 8643232809Sjmallett See SSO_WQ_INT[WQ_INT] 8644232809Sjmallett 1 bit/group. A copy of the R/W1C bit in the SSO. 8645232809Sjmallett For WRKQ, all 98 RAW readout will be same value */ 8646232809Sjmallett#else 8647232809Sjmallett uint64_t workq : 64; 8648232809Sjmallett#endif 8649232809Sjmallett } s; 8650232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xx; 8651232809Sjmallett struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xxp1; 8652232809Sjmallett}; 8653232809Sjmalletttypedef union cvmx_ciu2_raw_ppx_ip4_wrkq cvmx_ciu2_raw_ppx_ip4_wrkq_t; 8654232809Sjmallett 8655232809Sjmallett/** 8656232809Sjmallett * cvmx_ciu2_src_io#_int_gpio 8657232809Sjmallett */ 8658232809Sjmallettunion cvmx_ciu2_src_iox_int_gpio { 8659232809Sjmallett uint64_t u64; 8660232809Sjmallett struct cvmx_ciu2_src_iox_int_gpio_s { 8661232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8662232809Sjmallett uint64_t reserved_16_63 : 48; 8663232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupts source */ 8664232809Sjmallett#else 8665232809Sjmallett uint64_t gpio : 16; 8666232809Sjmallett uint64_t reserved_16_63 : 48; 8667232809Sjmallett#endif 8668232809Sjmallett } s; 8669232809Sjmallett struct cvmx_ciu2_src_iox_int_gpio_s cn68xx; 8670232809Sjmallett struct cvmx_ciu2_src_iox_int_gpio_s cn68xxp1; 8671232809Sjmallett}; 8672232809Sjmalletttypedef union cvmx_ciu2_src_iox_int_gpio cvmx_ciu2_src_iox_int_gpio_t; 8673232809Sjmallett 8674232809Sjmallett/** 8675232809Sjmallett * cvmx_ciu2_src_io#_int_io 8676232809Sjmallett */ 8677232809Sjmallettunion cvmx_ciu2_src_iox_int_io { 8678232809Sjmallett uint64_t u64; 8679232809Sjmallett struct cvmx_ciu2_src_iox_int_io_s { 8680232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8681232809Sjmallett uint64_t reserved_34_63 : 30; 8682232809Sjmallett uint64_t pem : 2; /**< PEMx interrupt source 8683232809Sjmallett CIU2_RAW_IO[PEM] & CIU2_EN_xx_yy_IO[PEM] */ 8684232809Sjmallett uint64_t reserved_18_31 : 14; 8685232809Sjmallett uint64_t pci_inta : 2; /**< PCI_INTA source 8686232809Sjmallett CIU2_RAW_IO[PCI_INTA] & CIU2_EN_xx_yy_IO[PCI_INTA] */ 8687232809Sjmallett uint64_t reserved_13_15 : 3; 8688232809Sjmallett uint64_t msired : 1; /**< MSI summary bit source 8689232809Sjmallett CIU2_RAW_IO[MSIRED] & CIU2_EN_xx_yy_IO[MSIRED] 8690232809Sjmallett This bit may not be functional in pass 1. */ 8691232809Sjmallett uint64_t pci_msi : 4; /**< PCIe/sRIO MSI source 8692232809Sjmallett CIU2_RAW_IO[PCI_MSI] & CIU2_EN_xx_yy_IO[PCI_MSI] */ 8693232809Sjmallett uint64_t reserved_4_7 : 4; 8694232809Sjmallett uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt source 8695232809Sjmallett CIU2_RAW_IO[PCI_INTR] &CIU2_EN_xx_yy_IO[PCI_INTR] */ 8696232809Sjmallett#else 8697232809Sjmallett uint64_t pci_intr : 4; 8698232809Sjmallett uint64_t reserved_4_7 : 4; 8699232809Sjmallett uint64_t pci_msi : 4; 8700232809Sjmallett uint64_t msired : 1; 8701232809Sjmallett uint64_t reserved_13_15 : 3; 8702232809Sjmallett uint64_t pci_inta : 2; 8703232809Sjmallett uint64_t reserved_18_31 : 14; 8704232809Sjmallett uint64_t pem : 2; 8705232809Sjmallett uint64_t reserved_34_63 : 30; 8706232809Sjmallett#endif 8707232809Sjmallett } s; 8708232809Sjmallett struct cvmx_ciu2_src_iox_int_io_s cn68xx; 8709232809Sjmallett struct cvmx_ciu2_src_iox_int_io_s cn68xxp1; 8710232809Sjmallett}; 8711232809Sjmalletttypedef union cvmx_ciu2_src_iox_int_io cvmx_ciu2_src_iox_int_io_t; 8712232809Sjmallett 8713232809Sjmallett/** 8714232809Sjmallett * cvmx_ciu2_src_io#_int_mbox 8715232809Sjmallett */ 8716232809Sjmallettunion cvmx_ciu2_src_iox_int_mbox { 8717232809Sjmallett uint64_t u64; 8718232809Sjmallett struct cvmx_ciu2_src_iox_int_mbox_s { 8719232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8720232809Sjmallett uint64_t reserved_4_63 : 60; 8721232809Sjmallett uint64_t mbox : 4; /**< Mailbox interrupt Source (RAW & ENABLE) 8722232809Sjmallett For CIU2_SRC_PPX_IPx_MBOX: 8723232809Sjmallett Four mailbox interrupts for entries 0-31 8724232809Sjmallett RAW & ENABLE 8725232809Sjmallett [3] is the or of <31:24> of CIU2_MBOX 8726232809Sjmallett [2] is the or of <23:16> of CIU2_MBOX 8727232809Sjmallett [1] is the or of <15:8> of CIU2_MBOX 8728232809Sjmallett [0] is the or of <7:0> of CIU2_MBOX 8729232809Sjmallett CIU2_MBOX value can be read out via CSR address 8730232809Sjmallett CIU_MBOX_SET/CLR 8731232809Sjmallett For CIU2_SRC_IOX_INT_MBOX: 8732232809Sjmallett always zero */ 8733232809Sjmallett#else 8734232809Sjmallett uint64_t mbox : 4; 8735232809Sjmallett uint64_t reserved_4_63 : 60; 8736232809Sjmallett#endif 8737232809Sjmallett } s; 8738232809Sjmallett struct cvmx_ciu2_src_iox_int_mbox_s cn68xx; 8739232809Sjmallett struct cvmx_ciu2_src_iox_int_mbox_s cn68xxp1; 8740232809Sjmallett}; 8741232809Sjmalletttypedef union cvmx_ciu2_src_iox_int_mbox cvmx_ciu2_src_iox_int_mbox_t; 8742232809Sjmallett 8743232809Sjmallett/** 8744232809Sjmallett * cvmx_ciu2_src_io#_int_mem 8745232809Sjmallett */ 8746232809Sjmallettunion cvmx_ciu2_src_iox_int_mem { 8747232809Sjmallett uint64_t u64; 8748232809Sjmallett struct cvmx_ciu2_src_iox_int_mem_s { 8749232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8750232809Sjmallett uint64_t reserved_4_63 : 60; 8751232809Sjmallett uint64_t lmc : 4; /**< LMC* interrupt source 8752232809Sjmallett CIU2_RAW_MEM[LMC] & CIU2_EN_xx_yy_MEM[LMC] */ 8753232809Sjmallett#else 8754232809Sjmallett uint64_t lmc : 4; 8755232809Sjmallett uint64_t reserved_4_63 : 60; 8756232809Sjmallett#endif 8757232809Sjmallett } s; 8758232809Sjmallett struct cvmx_ciu2_src_iox_int_mem_s cn68xx; 8759232809Sjmallett struct cvmx_ciu2_src_iox_int_mem_s cn68xxp1; 8760232809Sjmallett}; 8761232809Sjmalletttypedef union cvmx_ciu2_src_iox_int_mem cvmx_ciu2_src_iox_int_mem_t; 8762232809Sjmallett 8763232809Sjmallett/** 8764232809Sjmallett * cvmx_ciu2_src_io#_int_mio 8765232809Sjmallett */ 8766232809Sjmallettunion cvmx_ciu2_src_iox_int_mio { 8767232809Sjmallett uint64_t u64; 8768232809Sjmallett struct cvmx_ciu2_src_iox_int_mio_s { 8769232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8770232809Sjmallett uint64_t rst : 1; /**< MIO RST interrupt source 8771232809Sjmallett CIU2_RAW_MIO[RST] & CIU2_EN_xx_yy_MIO[RST] */ 8772232809Sjmallett uint64_t reserved_49_62 : 14; 8773232809Sjmallett uint64_t ptp : 1; /**< PTP interrupt source 8774232809Sjmallett CIU2_RAW_MIO[PTP] & CIU2_EN_xx_yy_MIO[PTP] */ 8775232809Sjmallett uint64_t reserved_45_47 : 3; 8776232809Sjmallett uint64_t usb_hci : 1; /**< USB HCI Interrupt source 8777232809Sjmallett CIU2_RAW_MIO[USB_HCI] & CIU2_EN_xx_yy_MIO[USB_HCI] */ 8778232809Sjmallett uint64_t reserved_41_43 : 3; 8779232809Sjmallett uint64_t usb_uctl : 1; /**< USB UCTL* interrupt source 8780232809Sjmallett CIU2_RAW_MIO[USB_UCTL] &CIU2_EN_xx_yy_MIO[USB_UCTL] */ 8781232809Sjmallett uint64_t reserved_38_39 : 2; 8782232809Sjmallett uint64_t uart : 2; /**< Two UART interrupts source 8783232809Sjmallett CIU2_RAW_MIO[UART] & CIU2_EN_xx_yy_MIO[UART] */ 8784232809Sjmallett uint64_t reserved_34_35 : 2; 8785232809Sjmallett uint64_t twsi : 2; /**< TWSI x Interrupt source 8786232809Sjmallett CIU2_RAW_MIO[TWSI] & CIU2_EN_xx_yy_MIO[TWSI] */ 8787232809Sjmallett uint64_t reserved_19_31 : 13; 8788232809Sjmallett uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt source 8789232809Sjmallett CIU2_RAW_MIO[BOOTDMA] & CIU2_EN_xx_yy_MIO[BOOTDMA] */ 8790232809Sjmallett uint64_t mio : 1; /**< MIO boot interrupt source 8791232809Sjmallett CIU2_RAW_MIO[MIO] & CIU2_EN_xx_yy_MIO[MIO] */ 8792232809Sjmallett uint64_t nand : 1; /**< NAND Flash Controller interrupt source 8793232809Sjmallett CIU2_RAW_MIO[NAND] & CIU2_EN_xx_yy_MIO[NANAD] */ 8794232809Sjmallett uint64_t reserved_12_15 : 4; 8795232809Sjmallett uint64_t timer : 4; /**< General timer interrupts source 8796232809Sjmallett CIU2_RAW_MIO[TIMER] & CIU2_EN_xx_yy_MIO[TIMER] */ 8797232809Sjmallett uint64_t reserved_3_7 : 5; 8798232809Sjmallett uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt source 8799232809Sjmallett CIU2_RAW_MIO[IPD_DRP] & CIU2_EN_xx_yy_MIO[IPD_DRP] */ 8800232809Sjmallett uint64_t ssoiq : 1; /**< SSO IQ interrupt source 8801232809Sjmallett CIU2_RAW_MIO[SSOIQ] & CIU2_EN_xx_yy_MIO[SSOIQ] */ 8802232809Sjmallett uint64_t ipdppthr : 1; /**< IPD per-port cnt threshold interrupt source 8803232809Sjmallett CIU2_RAW_MIO[IPDPPTHR] &CIU2_EN_xx_yy_MIO[IPDPPTHR] */ 8804232809Sjmallett#else 8805232809Sjmallett uint64_t ipdppthr : 1; 8806232809Sjmallett uint64_t ssoiq : 1; 8807232809Sjmallett uint64_t ipd_drp : 1; 8808232809Sjmallett uint64_t reserved_3_7 : 5; 8809232809Sjmallett uint64_t timer : 4; 8810232809Sjmallett uint64_t reserved_12_15 : 4; 8811232809Sjmallett uint64_t nand : 1; 8812232809Sjmallett uint64_t mio : 1; 8813232809Sjmallett uint64_t bootdma : 1; 8814232809Sjmallett uint64_t reserved_19_31 : 13; 8815232809Sjmallett uint64_t twsi : 2; 8816232809Sjmallett uint64_t reserved_34_35 : 2; 8817232809Sjmallett uint64_t uart : 2; 8818232809Sjmallett uint64_t reserved_38_39 : 2; 8819232809Sjmallett uint64_t usb_uctl : 1; 8820232809Sjmallett uint64_t reserved_41_43 : 3; 8821232809Sjmallett uint64_t usb_hci : 1; 8822232809Sjmallett uint64_t reserved_45_47 : 3; 8823232809Sjmallett uint64_t ptp : 1; 8824232809Sjmallett uint64_t reserved_49_62 : 14; 8825232809Sjmallett uint64_t rst : 1; 8826232809Sjmallett#endif 8827232809Sjmallett } s; 8828232809Sjmallett struct cvmx_ciu2_src_iox_int_mio_s cn68xx; 8829232809Sjmallett struct cvmx_ciu2_src_iox_int_mio_s cn68xxp1; 8830232809Sjmallett}; 8831232809Sjmalletttypedef union cvmx_ciu2_src_iox_int_mio cvmx_ciu2_src_iox_int_mio_t; 8832232809Sjmallett 8833232809Sjmallett/** 8834232809Sjmallett * cvmx_ciu2_src_io#_int_pkt 8835232809Sjmallett */ 8836232809Sjmallettunion cvmx_ciu2_src_iox_int_pkt { 8837232809Sjmallett uint64_t u64; 8838232809Sjmallett struct cvmx_ciu2_src_iox_int_pkt_s { 8839232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8840232809Sjmallett uint64_t reserved_54_63 : 10; 8841232809Sjmallett uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupts source 8842232809Sjmallett CIU2_RAW_PKT[ILK_DRP] & CIU2_EN_xx_yy_PKT[ILK_DRP] */ 8843232809Sjmallett uint64_t reserved_49_51 : 3; 8844232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts source 8845232809Sjmallett CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */ 8846232809Sjmallett uint64_t reserved_41_47 : 7; 8847232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source 8848232809Sjmallett CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */ 8849232809Sjmallett uint64_t reserved_33_39 : 7; 8850232809Sjmallett uint64_t agl : 1; /**< AGL interrupt source 8851232809Sjmallett CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */ 8852232809Sjmallett uint64_t reserved_13_31 : 19; 8853232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE 8854232809Sjmallett CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */ 8855232809Sjmallett uint64_t reserved_5_7 : 3; 8856232809Sjmallett uint64_t agx : 5; /**< GMX interrupt source 8857232809Sjmallett CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */ 8858232809Sjmallett#else 8859232809Sjmallett uint64_t agx : 5; 8860232809Sjmallett uint64_t reserved_5_7 : 3; 8861232809Sjmallett uint64_t gmx_drp : 5; 8862232809Sjmallett uint64_t reserved_13_31 : 19; 8863232809Sjmallett uint64_t agl : 1; 8864232809Sjmallett uint64_t reserved_33_39 : 7; 8865232809Sjmallett uint64_t mii : 1; 8866232809Sjmallett uint64_t reserved_41_47 : 7; 8867232809Sjmallett uint64_t ilk : 1; 8868232809Sjmallett uint64_t reserved_49_51 : 3; 8869232809Sjmallett uint64_t ilk_drp : 2; 8870232809Sjmallett uint64_t reserved_54_63 : 10; 8871232809Sjmallett#endif 8872232809Sjmallett } s; 8873232809Sjmallett struct cvmx_ciu2_src_iox_int_pkt_s cn68xx; 8874232809Sjmallett struct cvmx_ciu2_src_iox_int_pkt_cn68xxp1 { 8875232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8876232809Sjmallett uint64_t reserved_49_63 : 15; 8877232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts source 8878232809Sjmallett CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */ 8879232809Sjmallett uint64_t reserved_41_47 : 7; 8880232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source 8881232809Sjmallett CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */ 8882232809Sjmallett uint64_t reserved_33_39 : 7; 8883232809Sjmallett uint64_t agl : 1; /**< AGL interrupt source 8884232809Sjmallett CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */ 8885232809Sjmallett uint64_t reserved_13_31 : 19; 8886232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE 8887232809Sjmallett CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */ 8888232809Sjmallett uint64_t reserved_5_7 : 3; 8889232809Sjmallett uint64_t agx : 5; /**< GMX interrupt source 8890232809Sjmallett CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */ 8891232809Sjmallett#else 8892232809Sjmallett uint64_t agx : 5; 8893232809Sjmallett uint64_t reserved_5_7 : 3; 8894232809Sjmallett uint64_t gmx_drp : 5; 8895232809Sjmallett uint64_t reserved_13_31 : 19; 8896232809Sjmallett uint64_t agl : 1; 8897232809Sjmallett uint64_t reserved_33_39 : 7; 8898232809Sjmallett uint64_t mii : 1; 8899232809Sjmallett uint64_t reserved_41_47 : 7; 8900232809Sjmallett uint64_t ilk : 1; 8901232809Sjmallett uint64_t reserved_49_63 : 15; 8902232809Sjmallett#endif 8903232809Sjmallett } cn68xxp1; 8904232809Sjmallett}; 8905232809Sjmalletttypedef union cvmx_ciu2_src_iox_int_pkt cvmx_ciu2_src_iox_int_pkt_t; 8906232809Sjmallett 8907232809Sjmallett/** 8908232809Sjmallett * cvmx_ciu2_src_io#_int_rml 8909232809Sjmallett */ 8910232809Sjmallettunion cvmx_ciu2_src_iox_int_rml { 8911232809Sjmallett uint64_t u64; 8912232809Sjmallett struct cvmx_ciu2_src_iox_int_rml_s { 8913232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8914232809Sjmallett uint64_t reserved_56_63 : 8; 8915232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt source 8916232809Sjmallett CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */ 8917232809Sjmallett uint64_t reserved_49_51 : 3; 8918232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt source 8919232809Sjmallett CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */ 8920232809Sjmallett uint64_t reserved_41_47 : 7; 8921232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt source 8922232809Sjmallett CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */ 8923232809Sjmallett uint64_t reserved_37_39 : 3; 8924232809Sjmallett uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 8925232809Sjmallett See DPI DMA instruction completion */ 8926232809Sjmallett uint64_t reserved_34_35 : 2; 8927232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt source 8928232809Sjmallett CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */ 8929232809Sjmallett uint64_t sli : 1; /**< SLI interrupt source 8930232809Sjmallett CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */ 8931232809Sjmallett uint64_t reserved_31_31 : 1; 8932232809Sjmallett uint64_t key : 1; /**< KEY interrupt source 8933232809Sjmallett CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */ 8934232809Sjmallett uint64_t rad : 1; /**< RAD interrupt source 8935232809Sjmallett CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */ 8936232809Sjmallett uint64_t tim : 1; /**< TIM interrupt source 8937232809Sjmallett CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */ 8938232809Sjmallett uint64_t reserved_25_27 : 3; 8939232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt source 8940232809Sjmallett CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */ 8941232809Sjmallett uint64_t reserved_17_23 : 7; 8942232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt source 8943232809Sjmallett CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */ 8944232809Sjmallett uint64_t reserved_8_15 : 8; 8945232809Sjmallett uint64_t pko : 1; /**< PKO interrupt source 8946232809Sjmallett CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */ 8947232809Sjmallett uint64_t pip : 1; /**< PIP interrupt source 8948232809Sjmallett CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */ 8949232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt source 8950232809Sjmallett CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */ 8951232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt source 8952232809Sjmallett CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */ 8953232809Sjmallett uint64_t reserved_1_3 : 3; 8954232809Sjmallett uint64_t iob : 1; /**< IOB interrupt source 8955232809Sjmallett CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */ 8956232809Sjmallett#else 8957232809Sjmallett uint64_t iob : 1; 8958232809Sjmallett uint64_t reserved_1_3 : 3; 8959232809Sjmallett uint64_t fpa : 1; 8960232809Sjmallett uint64_t ipd : 1; 8961232809Sjmallett uint64_t pip : 1; 8962232809Sjmallett uint64_t pko : 1; 8963232809Sjmallett uint64_t reserved_8_15 : 8; 8964232809Sjmallett uint64_t sso : 1; 8965232809Sjmallett uint64_t reserved_17_23 : 7; 8966232809Sjmallett uint64_t zip : 1; 8967232809Sjmallett uint64_t reserved_25_27 : 3; 8968232809Sjmallett uint64_t tim : 1; 8969232809Sjmallett uint64_t rad : 1; 8970232809Sjmallett uint64_t key : 1; 8971232809Sjmallett uint64_t reserved_31_31 : 1; 8972232809Sjmallett uint64_t sli : 1; 8973232809Sjmallett uint64_t dpi : 1; 8974232809Sjmallett uint64_t reserved_34_35 : 2; 8975232809Sjmallett uint64_t dpi_dma : 1; 8976232809Sjmallett uint64_t reserved_37_39 : 3; 8977232809Sjmallett uint64_t dfa : 1; 8978232809Sjmallett uint64_t reserved_41_47 : 7; 8979232809Sjmallett uint64_t l2c : 1; 8980232809Sjmallett uint64_t reserved_49_51 : 3; 8981232809Sjmallett uint64_t trace : 4; 8982232809Sjmallett uint64_t reserved_56_63 : 8; 8983232809Sjmallett#endif 8984232809Sjmallett } s; 8985232809Sjmallett struct cvmx_ciu2_src_iox_int_rml_s cn68xx; 8986232809Sjmallett struct cvmx_ciu2_src_iox_int_rml_cn68xxp1 { 8987232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8988232809Sjmallett uint64_t reserved_56_63 : 8; 8989232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt source 8990232809Sjmallett CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */ 8991232809Sjmallett uint64_t reserved_49_51 : 3; 8992232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt source 8993232809Sjmallett CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */ 8994232809Sjmallett uint64_t reserved_41_47 : 7; 8995232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt source 8996232809Sjmallett CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */ 8997232809Sjmallett uint64_t reserved_34_39 : 6; 8998232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt source 8999232809Sjmallett CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */ 9000232809Sjmallett uint64_t sli : 1; /**< SLI interrupt source 9001232809Sjmallett CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */ 9002232809Sjmallett uint64_t reserved_31_31 : 1; 9003232809Sjmallett uint64_t key : 1; /**< KEY interrupt source 9004232809Sjmallett CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */ 9005232809Sjmallett uint64_t rad : 1; /**< RAD interrupt source 9006232809Sjmallett CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */ 9007232809Sjmallett uint64_t tim : 1; /**< TIM interrupt source 9008232809Sjmallett CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */ 9009232809Sjmallett uint64_t reserved_25_27 : 3; 9010232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt source 9011232809Sjmallett CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */ 9012232809Sjmallett uint64_t reserved_17_23 : 7; 9013232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt source 9014232809Sjmallett CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */ 9015232809Sjmallett uint64_t reserved_8_15 : 8; 9016232809Sjmallett uint64_t pko : 1; /**< PKO interrupt source 9017232809Sjmallett CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */ 9018232809Sjmallett uint64_t pip : 1; /**< PIP interrupt source 9019232809Sjmallett CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */ 9020232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt source 9021232809Sjmallett CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */ 9022232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt source 9023232809Sjmallett CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */ 9024232809Sjmallett uint64_t reserved_1_3 : 3; 9025232809Sjmallett uint64_t iob : 1; /**< IOB interrupt source 9026232809Sjmallett CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */ 9027232809Sjmallett#else 9028232809Sjmallett uint64_t iob : 1; 9029232809Sjmallett uint64_t reserved_1_3 : 3; 9030232809Sjmallett uint64_t fpa : 1; 9031232809Sjmallett uint64_t ipd : 1; 9032232809Sjmallett uint64_t pip : 1; 9033232809Sjmallett uint64_t pko : 1; 9034232809Sjmallett uint64_t reserved_8_15 : 8; 9035232809Sjmallett uint64_t sso : 1; 9036232809Sjmallett uint64_t reserved_17_23 : 7; 9037232809Sjmallett uint64_t zip : 1; 9038232809Sjmallett uint64_t reserved_25_27 : 3; 9039232809Sjmallett uint64_t tim : 1; 9040232809Sjmallett uint64_t rad : 1; 9041232809Sjmallett uint64_t key : 1; 9042232809Sjmallett uint64_t reserved_31_31 : 1; 9043232809Sjmallett uint64_t sli : 1; 9044232809Sjmallett uint64_t dpi : 1; 9045232809Sjmallett uint64_t reserved_34_39 : 6; 9046232809Sjmallett uint64_t dfa : 1; 9047232809Sjmallett uint64_t reserved_41_47 : 7; 9048232809Sjmallett uint64_t l2c : 1; 9049232809Sjmallett uint64_t reserved_49_51 : 3; 9050232809Sjmallett uint64_t trace : 4; 9051232809Sjmallett uint64_t reserved_56_63 : 8; 9052232809Sjmallett#endif 9053232809Sjmallett } cn68xxp1; 9054232809Sjmallett}; 9055232809Sjmalletttypedef union cvmx_ciu2_src_iox_int_rml cvmx_ciu2_src_iox_int_rml_t; 9056232809Sjmallett 9057232809Sjmallett/** 9058232809Sjmallett * cvmx_ciu2_src_io#_int_wdog 9059232809Sjmallett */ 9060232809Sjmallettunion cvmx_ciu2_src_iox_int_wdog { 9061232809Sjmallett uint64_t u64; 9062232809Sjmallett struct cvmx_ciu2_src_iox_int_wdog_s { 9063232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9064232809Sjmallett uint64_t reserved_32_63 : 32; 9065232809Sjmallett uint64_t wdog : 32; /**< 32 watchdog interrupts source 9066232809Sjmallett CIU2_RAW_WDOG & CIU2_EN_xx_yy_WDOG */ 9067232809Sjmallett#else 9068232809Sjmallett uint64_t wdog : 32; 9069232809Sjmallett uint64_t reserved_32_63 : 32; 9070232809Sjmallett#endif 9071232809Sjmallett } s; 9072232809Sjmallett struct cvmx_ciu2_src_iox_int_wdog_s cn68xx; 9073232809Sjmallett struct cvmx_ciu2_src_iox_int_wdog_s cn68xxp1; 9074232809Sjmallett}; 9075232809Sjmalletttypedef union cvmx_ciu2_src_iox_int_wdog cvmx_ciu2_src_iox_int_wdog_t; 9076232809Sjmallett 9077232809Sjmallett/** 9078232809Sjmallett * cvmx_ciu2_src_io#_int_wrkq 9079232809Sjmallett */ 9080232809Sjmallettunion cvmx_ciu2_src_iox_int_wrkq { 9081232809Sjmallett uint64_t u64; 9082232809Sjmallett struct cvmx_ciu2_src_iox_int_wrkq_s { 9083232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9084232809Sjmallett uint64_t workq : 64; /**< 64 work queue intr source, 9085232809Sjmallett CIU2_RAW_WRKQ & CIU2_EN_xx_yy_WRKQ */ 9086232809Sjmallett#else 9087232809Sjmallett uint64_t workq : 64; 9088232809Sjmallett#endif 9089232809Sjmallett } s; 9090232809Sjmallett struct cvmx_ciu2_src_iox_int_wrkq_s cn68xx; 9091232809Sjmallett struct cvmx_ciu2_src_iox_int_wrkq_s cn68xxp1; 9092232809Sjmallett}; 9093232809Sjmalletttypedef union cvmx_ciu2_src_iox_int_wrkq cvmx_ciu2_src_iox_int_wrkq_t; 9094232809Sjmallett 9095232809Sjmallett/** 9096232809Sjmallett * cvmx_ciu2_src_pp#_ip2_gpio 9097232809Sjmallett */ 9098232809Sjmallettunion cvmx_ciu2_src_ppx_ip2_gpio { 9099232809Sjmallett uint64_t u64; 9100232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_gpio_s { 9101232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9102232809Sjmallett uint64_t reserved_16_63 : 48; 9103232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupts source */ 9104232809Sjmallett#else 9105232809Sjmallett uint64_t gpio : 16; 9106232809Sjmallett uint64_t reserved_16_63 : 48; 9107232809Sjmallett#endif 9108232809Sjmallett } s; 9109232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xx; 9110232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xxp1; 9111232809Sjmallett}; 9112232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip2_gpio cvmx_ciu2_src_ppx_ip2_gpio_t; 9113232809Sjmallett 9114232809Sjmallett/** 9115232809Sjmallett * cvmx_ciu2_src_pp#_ip2_io 9116232809Sjmallett */ 9117232809Sjmallettunion cvmx_ciu2_src_ppx_ip2_io { 9118232809Sjmallett uint64_t u64; 9119232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_io_s { 9120232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9121232809Sjmallett uint64_t reserved_34_63 : 30; 9122232809Sjmallett uint64_t pem : 2; /**< PEMx interrupt source 9123232809Sjmallett CIU2_RAW_IO[PEM] & CIU2_EN_xx_yy_IO[PEM] */ 9124232809Sjmallett uint64_t reserved_18_31 : 14; 9125232809Sjmallett uint64_t pci_inta : 2; /**< PCI_INTA source 9126232809Sjmallett CIU2_RAW_IO[PCI_INTA] & CIU2_EN_xx_yy_IO[PCI_INTA] */ 9127232809Sjmallett uint64_t reserved_13_15 : 3; 9128232809Sjmallett uint64_t msired : 1; /**< MSI summary bit source 9129232809Sjmallett CIU2_RAW_IO[MSIRED] & CIU2_EN_xx_yy_IO[MSIRED] 9130232809Sjmallett This bit may not be functional in pass 1. */ 9131232809Sjmallett uint64_t pci_msi : 4; /**< PCIe/sRIO MSI source 9132232809Sjmallett CIU2_RAW_IO[PCI_MSI] & CIU2_EN_xx_yy_IO[PCI_MSI] */ 9133232809Sjmallett uint64_t reserved_4_7 : 4; 9134232809Sjmallett uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt source 9135232809Sjmallett CIU2_RAW_IO[PCI_INTR] &CIU2_EN_xx_yy_IO[PCI_INTR] */ 9136232809Sjmallett#else 9137232809Sjmallett uint64_t pci_intr : 4; 9138232809Sjmallett uint64_t reserved_4_7 : 4; 9139232809Sjmallett uint64_t pci_msi : 4; 9140232809Sjmallett uint64_t msired : 1; 9141232809Sjmallett uint64_t reserved_13_15 : 3; 9142232809Sjmallett uint64_t pci_inta : 2; 9143232809Sjmallett uint64_t reserved_18_31 : 14; 9144232809Sjmallett uint64_t pem : 2; 9145232809Sjmallett uint64_t reserved_34_63 : 30; 9146232809Sjmallett#endif 9147232809Sjmallett } s; 9148232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_io_s cn68xx; 9149232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_io_s cn68xxp1; 9150232809Sjmallett}; 9151232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip2_io cvmx_ciu2_src_ppx_ip2_io_t; 9152232809Sjmallett 9153232809Sjmallett/** 9154232809Sjmallett * cvmx_ciu2_src_pp#_ip2_mbox 9155232809Sjmallett */ 9156232809Sjmallettunion cvmx_ciu2_src_ppx_ip2_mbox { 9157232809Sjmallett uint64_t u64; 9158232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_mbox_s { 9159232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9160232809Sjmallett uint64_t reserved_4_63 : 60; 9161232809Sjmallett uint64_t mbox : 4; /**< Mailbox interrupt Source (RAW & ENABLE) 9162232809Sjmallett For CIU2_SRC_PPX_IPx_MBOX: 9163232809Sjmallett Four mailbox interrupts for entries 0-31 9164232809Sjmallett RAW & ENABLE 9165232809Sjmallett [3] is the or of <31:24> of CIU2_MBOX 9166232809Sjmallett [2] is the or of <23:16> of CIU2_MBOX 9167232809Sjmallett [1] is the or of <15:8> of CIU2_MBOX 9168232809Sjmallett [0] is the or of <7:0> of CIU2_MBOX 9169232809Sjmallett CIU2_MBOX value can be read out via CSR address 9170232809Sjmallett CIU_MBOX_SET/CLR 9171232809Sjmallett For CIU2_SRC_IOX_INT_MBOX: 9172232809Sjmallett always zero */ 9173232809Sjmallett#else 9174232809Sjmallett uint64_t mbox : 4; 9175232809Sjmallett uint64_t reserved_4_63 : 60; 9176232809Sjmallett#endif 9177232809Sjmallett } s; 9178232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xx; 9179232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xxp1; 9180232809Sjmallett}; 9181232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip2_mbox cvmx_ciu2_src_ppx_ip2_mbox_t; 9182232809Sjmallett 9183232809Sjmallett/** 9184232809Sjmallett * cvmx_ciu2_src_pp#_ip2_mem 9185232809Sjmallett */ 9186232809Sjmallettunion cvmx_ciu2_src_ppx_ip2_mem { 9187232809Sjmallett uint64_t u64; 9188232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_mem_s { 9189232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9190232809Sjmallett uint64_t reserved_4_63 : 60; 9191232809Sjmallett uint64_t lmc : 4; /**< LMC* interrupt source 9192232809Sjmallett CIU2_RAW_MEM[LMC] & CIU2_EN_xx_yy_MEM[LMC] */ 9193232809Sjmallett#else 9194232809Sjmallett uint64_t lmc : 4; 9195232809Sjmallett uint64_t reserved_4_63 : 60; 9196232809Sjmallett#endif 9197232809Sjmallett } s; 9198232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xx; 9199232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xxp1; 9200232809Sjmallett}; 9201232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip2_mem cvmx_ciu2_src_ppx_ip2_mem_t; 9202232809Sjmallett 9203232809Sjmallett/** 9204232809Sjmallett * cvmx_ciu2_src_pp#_ip2_mio 9205232809Sjmallett */ 9206232809Sjmallettunion cvmx_ciu2_src_ppx_ip2_mio { 9207232809Sjmallett uint64_t u64; 9208232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_mio_s { 9209232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9210232809Sjmallett uint64_t rst : 1; /**< MIO RST interrupt source 9211232809Sjmallett CIU2_RAW_MIO[RST] & CIU2_EN_xx_yy_MIO[RST] */ 9212232809Sjmallett uint64_t reserved_49_62 : 14; 9213232809Sjmallett uint64_t ptp : 1; /**< PTP interrupt source 9214232809Sjmallett CIU2_RAW_MIO[PTP] & CIU2_EN_xx_yy_MIO[PTP] */ 9215232809Sjmallett uint64_t reserved_45_47 : 3; 9216232809Sjmallett uint64_t usb_hci : 1; /**< USB HCI Interrupt source 9217232809Sjmallett CIU2_RAW_MIO[USB_HCI] & CIU2_EN_xx_yy_MIO[USB_HCI] */ 9218232809Sjmallett uint64_t reserved_41_43 : 3; 9219232809Sjmallett uint64_t usb_uctl : 1; /**< USB UCTL* interrupt source 9220232809Sjmallett CIU2_RAW_MIO[USB_UCTL] &CIU2_EN_xx_yy_MIO[USB_UCTL] */ 9221232809Sjmallett uint64_t reserved_38_39 : 2; 9222232809Sjmallett uint64_t uart : 2; /**< Two UART interrupts source 9223232809Sjmallett CIU2_RAW_MIO[UART] & CIU2_EN_xx_yy_MIO[UART] */ 9224232809Sjmallett uint64_t reserved_34_35 : 2; 9225232809Sjmallett uint64_t twsi : 2; /**< TWSI x Interrupt source 9226232809Sjmallett CIU2_RAW_MIO[TWSI] & CIU2_EN_xx_yy_MIO[TWSI] */ 9227232809Sjmallett uint64_t reserved_19_31 : 13; 9228232809Sjmallett uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt source 9229232809Sjmallett CIU2_RAW_MIO[BOOTDMA] & CIU2_EN_xx_yy_MIO[BOOTDMA] */ 9230232809Sjmallett uint64_t mio : 1; /**< MIO boot interrupt source 9231232809Sjmallett CIU2_RAW_MIO[MIO] & CIU2_EN_xx_yy_MIO[MIO] */ 9232232809Sjmallett uint64_t nand : 1; /**< NAND Flash Controller interrupt source 9233232809Sjmallett CIU2_RAW_MIO[NAND] & CIU2_EN_xx_yy_MIO[NANAD] */ 9234232809Sjmallett uint64_t reserved_12_15 : 4; 9235232809Sjmallett uint64_t timer : 4; /**< General timer interrupts source 9236232809Sjmallett CIU2_RAW_MIO[TIMER] & CIU2_EN_xx_yy_MIO[TIMER] */ 9237232809Sjmallett uint64_t reserved_3_7 : 5; 9238232809Sjmallett uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt source 9239232809Sjmallett CIU2_RAW_MIO[IPD_DRP] & CIU2_EN_xx_yy_MIO[IPD_DRP] */ 9240232809Sjmallett uint64_t ssoiq : 1; /**< SSO IQ interrupt source 9241232809Sjmallett CIU2_RAW_MIO[SSOIQ] & CIU2_EN_xx_yy_MIO[SSOIQ] */ 9242232809Sjmallett uint64_t ipdppthr : 1; /**< IPD per-port cnt threshold interrupt source 9243232809Sjmallett CIU2_RAW_MIO[IPDPPTHR] &CIU2_EN_xx_yy_MIO[IPDPPTHR] */ 9244232809Sjmallett#else 9245232809Sjmallett uint64_t ipdppthr : 1; 9246232809Sjmallett uint64_t ssoiq : 1; 9247232809Sjmallett uint64_t ipd_drp : 1; 9248232809Sjmallett uint64_t reserved_3_7 : 5; 9249232809Sjmallett uint64_t timer : 4; 9250232809Sjmallett uint64_t reserved_12_15 : 4; 9251232809Sjmallett uint64_t nand : 1; 9252232809Sjmallett uint64_t mio : 1; 9253232809Sjmallett uint64_t bootdma : 1; 9254232809Sjmallett uint64_t reserved_19_31 : 13; 9255232809Sjmallett uint64_t twsi : 2; 9256232809Sjmallett uint64_t reserved_34_35 : 2; 9257232809Sjmallett uint64_t uart : 2; 9258232809Sjmallett uint64_t reserved_38_39 : 2; 9259232809Sjmallett uint64_t usb_uctl : 1; 9260232809Sjmallett uint64_t reserved_41_43 : 3; 9261232809Sjmallett uint64_t usb_hci : 1; 9262232809Sjmallett uint64_t reserved_45_47 : 3; 9263232809Sjmallett uint64_t ptp : 1; 9264232809Sjmallett uint64_t reserved_49_62 : 14; 9265232809Sjmallett uint64_t rst : 1; 9266232809Sjmallett#endif 9267232809Sjmallett } s; 9268232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xx; 9269232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xxp1; 9270232809Sjmallett}; 9271232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip2_mio cvmx_ciu2_src_ppx_ip2_mio_t; 9272232809Sjmallett 9273232809Sjmallett/** 9274232809Sjmallett * cvmx_ciu2_src_pp#_ip2_pkt 9275232809Sjmallett */ 9276232809Sjmallettunion cvmx_ciu2_src_ppx_ip2_pkt { 9277232809Sjmallett uint64_t u64; 9278232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_pkt_s { 9279232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9280232809Sjmallett uint64_t reserved_54_63 : 10; 9281232809Sjmallett uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupts source 9282232809Sjmallett CIU2_RAW_PKT[ILK_DRP] & CIU2_EN_xx_yy_PKT[ILK_DRP] */ 9283232809Sjmallett uint64_t reserved_49_51 : 3; 9284232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts source 9285232809Sjmallett CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */ 9286232809Sjmallett uint64_t reserved_41_47 : 7; 9287232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source 9288232809Sjmallett CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */ 9289232809Sjmallett uint64_t reserved_33_39 : 7; 9290232809Sjmallett uint64_t agl : 1; /**< AGL interrupt source 9291232809Sjmallett CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */ 9292232809Sjmallett uint64_t reserved_13_31 : 19; 9293232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE 9294232809Sjmallett CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */ 9295232809Sjmallett uint64_t reserved_5_7 : 3; 9296232809Sjmallett uint64_t agx : 5; /**< GMX interrupt source 9297232809Sjmallett CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */ 9298232809Sjmallett#else 9299232809Sjmallett uint64_t agx : 5; 9300232809Sjmallett uint64_t reserved_5_7 : 3; 9301232809Sjmallett uint64_t gmx_drp : 5; 9302232809Sjmallett uint64_t reserved_13_31 : 19; 9303232809Sjmallett uint64_t agl : 1; 9304232809Sjmallett uint64_t reserved_33_39 : 7; 9305232809Sjmallett uint64_t mii : 1; 9306232809Sjmallett uint64_t reserved_41_47 : 7; 9307232809Sjmallett uint64_t ilk : 1; 9308232809Sjmallett uint64_t reserved_49_51 : 3; 9309232809Sjmallett uint64_t ilk_drp : 2; 9310232809Sjmallett uint64_t reserved_54_63 : 10; 9311232809Sjmallett#endif 9312232809Sjmallett } s; 9313232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_pkt_s cn68xx; 9314232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_pkt_cn68xxp1 { 9315232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9316232809Sjmallett uint64_t reserved_49_63 : 15; 9317232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts source 9318232809Sjmallett CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */ 9319232809Sjmallett uint64_t reserved_41_47 : 7; 9320232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source 9321232809Sjmallett CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */ 9322232809Sjmallett uint64_t reserved_33_39 : 7; 9323232809Sjmallett uint64_t agl : 1; /**< AGL interrupt source 9324232809Sjmallett CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */ 9325232809Sjmallett uint64_t reserved_13_31 : 19; 9326232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE 9327232809Sjmallett CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */ 9328232809Sjmallett uint64_t reserved_5_7 : 3; 9329232809Sjmallett uint64_t agx : 5; /**< GMX interrupt source 9330232809Sjmallett CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */ 9331232809Sjmallett#else 9332232809Sjmallett uint64_t agx : 5; 9333232809Sjmallett uint64_t reserved_5_7 : 3; 9334232809Sjmallett uint64_t gmx_drp : 5; 9335232809Sjmallett uint64_t reserved_13_31 : 19; 9336232809Sjmallett uint64_t agl : 1; 9337232809Sjmallett uint64_t reserved_33_39 : 7; 9338232809Sjmallett uint64_t mii : 1; 9339232809Sjmallett uint64_t reserved_41_47 : 7; 9340232809Sjmallett uint64_t ilk : 1; 9341232809Sjmallett uint64_t reserved_49_63 : 15; 9342232809Sjmallett#endif 9343232809Sjmallett } cn68xxp1; 9344232809Sjmallett}; 9345232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip2_pkt cvmx_ciu2_src_ppx_ip2_pkt_t; 9346232809Sjmallett 9347232809Sjmallett/** 9348232809Sjmallett * cvmx_ciu2_src_pp#_ip2_rml 9349232809Sjmallett */ 9350232809Sjmallettunion cvmx_ciu2_src_ppx_ip2_rml { 9351232809Sjmallett uint64_t u64; 9352232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_rml_s { 9353232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9354232809Sjmallett uint64_t reserved_56_63 : 8; 9355232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt source 9356232809Sjmallett CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */ 9357232809Sjmallett uint64_t reserved_49_51 : 3; 9358232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt source 9359232809Sjmallett CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */ 9360232809Sjmallett uint64_t reserved_41_47 : 7; 9361232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt source 9362232809Sjmallett CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */ 9363232809Sjmallett uint64_t reserved_37_39 : 3; 9364232809Sjmallett uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 9365232809Sjmallett See DPI DMA instruction completion */ 9366232809Sjmallett uint64_t reserved_34_35 : 2; 9367232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt source 9368232809Sjmallett CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */ 9369232809Sjmallett uint64_t sli : 1; /**< SLI interrupt source 9370232809Sjmallett CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */ 9371232809Sjmallett uint64_t reserved_31_31 : 1; 9372232809Sjmallett uint64_t key : 1; /**< KEY interrupt source 9373232809Sjmallett CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */ 9374232809Sjmallett uint64_t rad : 1; /**< RAD interrupt source 9375232809Sjmallett CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */ 9376232809Sjmallett uint64_t tim : 1; /**< TIM interrupt source 9377232809Sjmallett CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */ 9378232809Sjmallett uint64_t reserved_25_27 : 3; 9379232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt source 9380232809Sjmallett CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */ 9381232809Sjmallett uint64_t reserved_17_23 : 7; 9382232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt source 9383232809Sjmallett CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */ 9384232809Sjmallett uint64_t reserved_8_15 : 8; 9385232809Sjmallett uint64_t pko : 1; /**< PKO interrupt source 9386232809Sjmallett CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */ 9387232809Sjmallett uint64_t pip : 1; /**< PIP interrupt source 9388232809Sjmallett CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */ 9389232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt source 9390232809Sjmallett CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */ 9391232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt source 9392232809Sjmallett CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */ 9393232809Sjmallett uint64_t reserved_1_3 : 3; 9394232809Sjmallett uint64_t iob : 1; /**< IOB interrupt source 9395232809Sjmallett CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */ 9396232809Sjmallett#else 9397232809Sjmallett uint64_t iob : 1; 9398232809Sjmallett uint64_t reserved_1_3 : 3; 9399232809Sjmallett uint64_t fpa : 1; 9400232809Sjmallett uint64_t ipd : 1; 9401232809Sjmallett uint64_t pip : 1; 9402232809Sjmallett uint64_t pko : 1; 9403232809Sjmallett uint64_t reserved_8_15 : 8; 9404232809Sjmallett uint64_t sso : 1; 9405232809Sjmallett uint64_t reserved_17_23 : 7; 9406232809Sjmallett uint64_t zip : 1; 9407232809Sjmallett uint64_t reserved_25_27 : 3; 9408232809Sjmallett uint64_t tim : 1; 9409232809Sjmallett uint64_t rad : 1; 9410232809Sjmallett uint64_t key : 1; 9411232809Sjmallett uint64_t reserved_31_31 : 1; 9412232809Sjmallett uint64_t sli : 1; 9413232809Sjmallett uint64_t dpi : 1; 9414232809Sjmallett uint64_t reserved_34_35 : 2; 9415232809Sjmallett uint64_t dpi_dma : 1; 9416232809Sjmallett uint64_t reserved_37_39 : 3; 9417232809Sjmallett uint64_t dfa : 1; 9418232809Sjmallett uint64_t reserved_41_47 : 7; 9419232809Sjmallett uint64_t l2c : 1; 9420232809Sjmallett uint64_t reserved_49_51 : 3; 9421232809Sjmallett uint64_t trace : 4; 9422232809Sjmallett uint64_t reserved_56_63 : 8; 9423232809Sjmallett#endif 9424232809Sjmallett } s; 9425232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_rml_s cn68xx; 9426232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_rml_cn68xxp1 { 9427232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9428232809Sjmallett uint64_t reserved_56_63 : 8; 9429232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt source 9430232809Sjmallett CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */ 9431232809Sjmallett uint64_t reserved_49_51 : 3; 9432232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt source 9433232809Sjmallett CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */ 9434232809Sjmallett uint64_t reserved_41_47 : 7; 9435232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt source 9436232809Sjmallett CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */ 9437232809Sjmallett uint64_t reserved_34_39 : 6; 9438232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt source 9439232809Sjmallett CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */ 9440232809Sjmallett uint64_t sli : 1; /**< SLI interrupt source 9441232809Sjmallett CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */ 9442232809Sjmallett uint64_t reserved_31_31 : 1; 9443232809Sjmallett uint64_t key : 1; /**< KEY interrupt source 9444232809Sjmallett CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */ 9445232809Sjmallett uint64_t rad : 1; /**< RAD interrupt source 9446232809Sjmallett CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */ 9447232809Sjmallett uint64_t tim : 1; /**< TIM interrupt source 9448232809Sjmallett CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */ 9449232809Sjmallett uint64_t reserved_25_27 : 3; 9450232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt source 9451232809Sjmallett CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */ 9452232809Sjmallett uint64_t reserved_17_23 : 7; 9453232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt source 9454232809Sjmallett CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */ 9455232809Sjmallett uint64_t reserved_8_15 : 8; 9456232809Sjmallett uint64_t pko : 1; /**< PKO interrupt source 9457232809Sjmallett CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */ 9458232809Sjmallett uint64_t pip : 1; /**< PIP interrupt source 9459232809Sjmallett CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */ 9460232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt source 9461232809Sjmallett CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */ 9462232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt source 9463232809Sjmallett CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */ 9464232809Sjmallett uint64_t reserved_1_3 : 3; 9465232809Sjmallett uint64_t iob : 1; /**< IOB interrupt source 9466232809Sjmallett CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */ 9467232809Sjmallett#else 9468232809Sjmallett uint64_t iob : 1; 9469232809Sjmallett uint64_t reserved_1_3 : 3; 9470232809Sjmallett uint64_t fpa : 1; 9471232809Sjmallett uint64_t ipd : 1; 9472232809Sjmallett uint64_t pip : 1; 9473232809Sjmallett uint64_t pko : 1; 9474232809Sjmallett uint64_t reserved_8_15 : 8; 9475232809Sjmallett uint64_t sso : 1; 9476232809Sjmallett uint64_t reserved_17_23 : 7; 9477232809Sjmallett uint64_t zip : 1; 9478232809Sjmallett uint64_t reserved_25_27 : 3; 9479232809Sjmallett uint64_t tim : 1; 9480232809Sjmallett uint64_t rad : 1; 9481232809Sjmallett uint64_t key : 1; 9482232809Sjmallett uint64_t reserved_31_31 : 1; 9483232809Sjmallett uint64_t sli : 1; 9484232809Sjmallett uint64_t dpi : 1; 9485232809Sjmallett uint64_t reserved_34_39 : 6; 9486232809Sjmallett uint64_t dfa : 1; 9487232809Sjmallett uint64_t reserved_41_47 : 7; 9488232809Sjmallett uint64_t l2c : 1; 9489232809Sjmallett uint64_t reserved_49_51 : 3; 9490232809Sjmallett uint64_t trace : 4; 9491232809Sjmallett uint64_t reserved_56_63 : 8; 9492232809Sjmallett#endif 9493232809Sjmallett } cn68xxp1; 9494232809Sjmallett}; 9495232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip2_rml cvmx_ciu2_src_ppx_ip2_rml_t; 9496232809Sjmallett 9497232809Sjmallett/** 9498232809Sjmallett * cvmx_ciu2_src_pp#_ip2_wdog 9499232809Sjmallett */ 9500232809Sjmallettunion cvmx_ciu2_src_ppx_ip2_wdog { 9501232809Sjmallett uint64_t u64; 9502232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_wdog_s { 9503232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9504232809Sjmallett uint64_t reserved_32_63 : 32; 9505232809Sjmallett uint64_t wdog : 32; /**< 32 watchdog interrupts source 9506232809Sjmallett CIU2_RAW_WDOG & CIU2_EN_xx_yy_WDOG */ 9507232809Sjmallett#else 9508232809Sjmallett uint64_t wdog : 32; 9509232809Sjmallett uint64_t reserved_32_63 : 32; 9510232809Sjmallett#endif 9511232809Sjmallett } s; 9512232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xx; 9513232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xxp1; 9514232809Sjmallett}; 9515232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip2_wdog cvmx_ciu2_src_ppx_ip2_wdog_t; 9516232809Sjmallett 9517232809Sjmallett/** 9518232809Sjmallett * cvmx_ciu2_src_pp#_ip2_wrkq 9519232809Sjmallett * 9520232809Sjmallett * All SRC values is generated by AND Raw value (CIU2_RAW_XXX) with CIU2_EN_PPX_IPx_XXX 9521232809Sjmallett * 9522232809Sjmallett */ 9523232809Sjmallettunion cvmx_ciu2_src_ppx_ip2_wrkq { 9524232809Sjmallett uint64_t u64; 9525232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_wrkq_s { 9526232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9527232809Sjmallett uint64_t workq : 64; /**< 64 work queue intr source, 9528232809Sjmallett CIU2_RAW_WRKQ & CIU2_EN_xx_yy_WRKQ */ 9529232809Sjmallett#else 9530232809Sjmallett uint64_t workq : 64; 9531232809Sjmallett#endif 9532232809Sjmallett } s; 9533232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xx; 9534232809Sjmallett struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xxp1; 9535232809Sjmallett}; 9536232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip2_wrkq cvmx_ciu2_src_ppx_ip2_wrkq_t; 9537232809Sjmallett 9538232809Sjmallett/** 9539232809Sjmallett * cvmx_ciu2_src_pp#_ip3_gpio 9540232809Sjmallett */ 9541232809Sjmallettunion cvmx_ciu2_src_ppx_ip3_gpio { 9542232809Sjmallett uint64_t u64; 9543232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_gpio_s { 9544232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9545232809Sjmallett uint64_t reserved_16_63 : 48; 9546232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupts source */ 9547232809Sjmallett#else 9548232809Sjmallett uint64_t gpio : 16; 9549232809Sjmallett uint64_t reserved_16_63 : 48; 9550232809Sjmallett#endif 9551232809Sjmallett } s; 9552232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xx; 9553232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xxp1; 9554232809Sjmallett}; 9555232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip3_gpio cvmx_ciu2_src_ppx_ip3_gpio_t; 9556232809Sjmallett 9557232809Sjmallett/** 9558232809Sjmallett * cvmx_ciu2_src_pp#_ip3_io 9559232809Sjmallett */ 9560232809Sjmallettunion cvmx_ciu2_src_ppx_ip3_io { 9561232809Sjmallett uint64_t u64; 9562232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_io_s { 9563232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9564232809Sjmallett uint64_t reserved_34_63 : 30; 9565232809Sjmallett uint64_t pem : 2; /**< PEMx interrupt source 9566232809Sjmallett CIU2_RAW_IO[PEM] & CIU2_EN_xx_yy_IO[PEM] */ 9567232809Sjmallett uint64_t reserved_18_31 : 14; 9568232809Sjmallett uint64_t pci_inta : 2; /**< PCI_INTA source 9569232809Sjmallett CIU2_RAW_IO[PCI_INTA] & CIU2_EN_xx_yy_IO[PCI_INTA] */ 9570232809Sjmallett uint64_t reserved_13_15 : 3; 9571232809Sjmallett uint64_t msired : 1; /**< MSI summary bit source 9572232809Sjmallett CIU2_RAW_IO[MSIRED] & CIU2_EN_xx_yy_IO[MSIRED] 9573232809Sjmallett This bit may not be functional in pass 1. */ 9574232809Sjmallett uint64_t pci_msi : 4; /**< PCIe/sRIO MSI source 9575232809Sjmallett CIU2_RAW_IO[PCI_MSI] & CIU2_EN_xx_yy_IO[PCI_MSI] */ 9576232809Sjmallett uint64_t reserved_4_7 : 4; 9577232809Sjmallett uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt source 9578232809Sjmallett CIU2_RAW_IO[PCI_INTR] &CIU2_EN_xx_yy_IO[PCI_INTR] */ 9579232809Sjmallett#else 9580232809Sjmallett uint64_t pci_intr : 4; 9581232809Sjmallett uint64_t reserved_4_7 : 4; 9582232809Sjmallett uint64_t pci_msi : 4; 9583232809Sjmallett uint64_t msired : 1; 9584232809Sjmallett uint64_t reserved_13_15 : 3; 9585232809Sjmallett uint64_t pci_inta : 2; 9586232809Sjmallett uint64_t reserved_18_31 : 14; 9587232809Sjmallett uint64_t pem : 2; 9588232809Sjmallett uint64_t reserved_34_63 : 30; 9589232809Sjmallett#endif 9590232809Sjmallett } s; 9591232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_io_s cn68xx; 9592232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_io_s cn68xxp1; 9593232809Sjmallett}; 9594232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip3_io cvmx_ciu2_src_ppx_ip3_io_t; 9595232809Sjmallett 9596232809Sjmallett/** 9597232809Sjmallett * cvmx_ciu2_src_pp#_ip3_mbox 9598232809Sjmallett */ 9599232809Sjmallettunion cvmx_ciu2_src_ppx_ip3_mbox { 9600232809Sjmallett uint64_t u64; 9601232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_mbox_s { 9602232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9603232809Sjmallett uint64_t reserved_4_63 : 60; 9604232809Sjmallett uint64_t mbox : 4; /**< Mailbox interrupt Source (RAW & ENABLE) 9605232809Sjmallett For CIU2_SRC_PPX_IPx_MBOX: 9606232809Sjmallett Four mailbox interrupts for entries 0-31 9607232809Sjmallett RAW & ENABLE 9608232809Sjmallett [3] is the or of <31:24> of CIU2_MBOX 9609232809Sjmallett [2] is the or of <23:16> of CIU2_MBOX 9610232809Sjmallett [1] is the or of <15:8> of CIU2_MBOX 9611232809Sjmallett [0] is the or of <7:0> of CIU2_MBOX 9612232809Sjmallett CIU2_MBOX value can be read out via CSR address 9613232809Sjmallett CIU_MBOX_SET/CLR 9614232809Sjmallett For CIU2_SRC_IOX_INT_MBOX: 9615232809Sjmallett always zero */ 9616232809Sjmallett#else 9617232809Sjmallett uint64_t mbox : 4; 9618232809Sjmallett uint64_t reserved_4_63 : 60; 9619232809Sjmallett#endif 9620232809Sjmallett } s; 9621232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xx; 9622232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xxp1; 9623232809Sjmallett}; 9624232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip3_mbox cvmx_ciu2_src_ppx_ip3_mbox_t; 9625232809Sjmallett 9626232809Sjmallett/** 9627232809Sjmallett * cvmx_ciu2_src_pp#_ip3_mem 9628232809Sjmallett */ 9629232809Sjmallettunion cvmx_ciu2_src_ppx_ip3_mem { 9630232809Sjmallett uint64_t u64; 9631232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_mem_s { 9632232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9633232809Sjmallett uint64_t reserved_4_63 : 60; 9634232809Sjmallett uint64_t lmc : 4; /**< LMC* interrupt source 9635232809Sjmallett CIU2_RAW_MEM[LMC] & CIU2_EN_xx_yy_MEM[LMC] */ 9636232809Sjmallett#else 9637232809Sjmallett uint64_t lmc : 4; 9638232809Sjmallett uint64_t reserved_4_63 : 60; 9639232809Sjmallett#endif 9640232809Sjmallett } s; 9641232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xx; 9642232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xxp1; 9643232809Sjmallett}; 9644232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip3_mem cvmx_ciu2_src_ppx_ip3_mem_t; 9645232809Sjmallett 9646232809Sjmallett/** 9647232809Sjmallett * cvmx_ciu2_src_pp#_ip3_mio 9648232809Sjmallett */ 9649232809Sjmallettunion cvmx_ciu2_src_ppx_ip3_mio { 9650232809Sjmallett uint64_t u64; 9651232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_mio_s { 9652232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9653232809Sjmallett uint64_t rst : 1; /**< MIO RST interrupt source 9654232809Sjmallett CIU2_RAW_MIO[RST] & CIU2_EN_xx_yy_MIO[RST] */ 9655232809Sjmallett uint64_t reserved_49_62 : 14; 9656232809Sjmallett uint64_t ptp : 1; /**< PTP interrupt source 9657232809Sjmallett CIU2_RAW_MIO[PTP] & CIU2_EN_xx_yy_MIO[PTP] */ 9658232809Sjmallett uint64_t reserved_45_47 : 3; 9659232809Sjmallett uint64_t usb_hci : 1; /**< USB HCI Interrupt source 9660232809Sjmallett CIU2_RAW_MIO[USB_HCI] & CIU2_EN_xx_yy_MIO[USB_HCI] */ 9661232809Sjmallett uint64_t reserved_41_43 : 3; 9662232809Sjmallett uint64_t usb_uctl : 1; /**< USB UCTL* interrupt source 9663232809Sjmallett CIU2_RAW_MIO[USB_UCTL] &CIU2_EN_xx_yy_MIO[USB_UCTL] */ 9664232809Sjmallett uint64_t reserved_38_39 : 2; 9665232809Sjmallett uint64_t uart : 2; /**< Two UART interrupts source 9666232809Sjmallett CIU2_RAW_MIO[UART] & CIU2_EN_xx_yy_MIO[UART] */ 9667232809Sjmallett uint64_t reserved_34_35 : 2; 9668232809Sjmallett uint64_t twsi : 2; /**< TWSI x Interrupt source 9669232809Sjmallett CIU2_RAW_MIO[TWSI] & CIU2_EN_xx_yy_MIO[TWSI] */ 9670232809Sjmallett uint64_t reserved_19_31 : 13; 9671232809Sjmallett uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt source 9672232809Sjmallett CIU2_RAW_MIO[BOOTDMA] & CIU2_EN_xx_yy_MIO[BOOTDMA] */ 9673232809Sjmallett uint64_t mio : 1; /**< MIO boot interrupt source 9674232809Sjmallett CIU2_RAW_MIO[MIO] & CIU2_EN_xx_yy_MIO[MIO] */ 9675232809Sjmallett uint64_t nand : 1; /**< NAND Flash Controller interrupt source 9676232809Sjmallett CIU2_RAW_MIO[NAND] & CIU2_EN_xx_yy_MIO[NANAD] */ 9677232809Sjmallett uint64_t reserved_12_15 : 4; 9678232809Sjmallett uint64_t timer : 4; /**< General timer interrupts source 9679232809Sjmallett CIU2_RAW_MIO[TIMER] & CIU2_EN_xx_yy_MIO[TIMER] */ 9680232809Sjmallett uint64_t reserved_3_7 : 5; 9681232809Sjmallett uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt source 9682232809Sjmallett CIU2_RAW_MIO[IPD_DRP] & CIU2_EN_xx_yy_MIO[IPD_DRP] */ 9683232809Sjmallett uint64_t ssoiq : 1; /**< SSO IQ interrupt source 9684232809Sjmallett CIU2_RAW_MIO[SSOIQ] & CIU2_EN_xx_yy_MIO[SSOIQ] */ 9685232809Sjmallett uint64_t ipdppthr : 1; /**< IPD per-port cnt threshold interrupt source 9686232809Sjmallett CIU2_RAW_MIO[IPDPPTHR] &CIU2_EN_xx_yy_MIO[IPDPPTHR] */ 9687232809Sjmallett#else 9688232809Sjmallett uint64_t ipdppthr : 1; 9689232809Sjmallett uint64_t ssoiq : 1; 9690232809Sjmallett uint64_t ipd_drp : 1; 9691232809Sjmallett uint64_t reserved_3_7 : 5; 9692232809Sjmallett uint64_t timer : 4; 9693232809Sjmallett uint64_t reserved_12_15 : 4; 9694232809Sjmallett uint64_t nand : 1; 9695232809Sjmallett uint64_t mio : 1; 9696232809Sjmallett uint64_t bootdma : 1; 9697232809Sjmallett uint64_t reserved_19_31 : 13; 9698232809Sjmallett uint64_t twsi : 2; 9699232809Sjmallett uint64_t reserved_34_35 : 2; 9700232809Sjmallett uint64_t uart : 2; 9701232809Sjmallett uint64_t reserved_38_39 : 2; 9702232809Sjmallett uint64_t usb_uctl : 1; 9703232809Sjmallett uint64_t reserved_41_43 : 3; 9704232809Sjmallett uint64_t usb_hci : 1; 9705232809Sjmallett uint64_t reserved_45_47 : 3; 9706232809Sjmallett uint64_t ptp : 1; 9707232809Sjmallett uint64_t reserved_49_62 : 14; 9708232809Sjmallett uint64_t rst : 1; 9709232809Sjmallett#endif 9710232809Sjmallett } s; 9711232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xx; 9712232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xxp1; 9713232809Sjmallett}; 9714232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip3_mio cvmx_ciu2_src_ppx_ip3_mio_t; 9715232809Sjmallett 9716232809Sjmallett/** 9717232809Sjmallett * cvmx_ciu2_src_pp#_ip3_pkt 9718232809Sjmallett */ 9719232809Sjmallettunion cvmx_ciu2_src_ppx_ip3_pkt { 9720232809Sjmallett uint64_t u64; 9721232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_pkt_s { 9722232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9723232809Sjmallett uint64_t reserved_54_63 : 10; 9724232809Sjmallett uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupts source 9725232809Sjmallett CIU2_RAW_PKT[ILK_DRP] & CIU2_EN_xx_yy_PKT[ILK_DRP] */ 9726232809Sjmallett uint64_t reserved_49_51 : 3; 9727232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts source 9728232809Sjmallett CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */ 9729232809Sjmallett uint64_t reserved_41_47 : 7; 9730232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source 9731232809Sjmallett CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */ 9732232809Sjmallett uint64_t reserved_33_39 : 7; 9733232809Sjmallett uint64_t agl : 1; /**< AGL interrupt source 9734232809Sjmallett CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */ 9735232809Sjmallett uint64_t reserved_13_31 : 19; 9736232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE 9737232809Sjmallett CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */ 9738232809Sjmallett uint64_t reserved_5_7 : 3; 9739232809Sjmallett uint64_t agx : 5; /**< GMX interrupt source 9740232809Sjmallett CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */ 9741232809Sjmallett#else 9742232809Sjmallett uint64_t agx : 5; 9743232809Sjmallett uint64_t reserved_5_7 : 3; 9744232809Sjmallett uint64_t gmx_drp : 5; 9745232809Sjmallett uint64_t reserved_13_31 : 19; 9746232809Sjmallett uint64_t agl : 1; 9747232809Sjmallett uint64_t reserved_33_39 : 7; 9748232809Sjmallett uint64_t mii : 1; 9749232809Sjmallett uint64_t reserved_41_47 : 7; 9750232809Sjmallett uint64_t ilk : 1; 9751232809Sjmallett uint64_t reserved_49_51 : 3; 9752232809Sjmallett uint64_t ilk_drp : 2; 9753232809Sjmallett uint64_t reserved_54_63 : 10; 9754232809Sjmallett#endif 9755232809Sjmallett } s; 9756232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_pkt_s cn68xx; 9757232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_pkt_cn68xxp1 { 9758232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9759232809Sjmallett uint64_t reserved_49_63 : 15; 9760232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts source 9761232809Sjmallett CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */ 9762232809Sjmallett uint64_t reserved_41_47 : 7; 9763232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source 9764232809Sjmallett CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */ 9765232809Sjmallett uint64_t reserved_33_39 : 7; 9766232809Sjmallett uint64_t agl : 1; /**< AGL interrupt source 9767232809Sjmallett CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */ 9768232809Sjmallett uint64_t reserved_13_31 : 19; 9769232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE 9770232809Sjmallett CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */ 9771232809Sjmallett uint64_t reserved_5_7 : 3; 9772232809Sjmallett uint64_t agx : 5; /**< GMX interrupt source 9773232809Sjmallett CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */ 9774232809Sjmallett#else 9775232809Sjmallett uint64_t agx : 5; 9776232809Sjmallett uint64_t reserved_5_7 : 3; 9777232809Sjmallett uint64_t gmx_drp : 5; 9778232809Sjmallett uint64_t reserved_13_31 : 19; 9779232809Sjmallett uint64_t agl : 1; 9780232809Sjmallett uint64_t reserved_33_39 : 7; 9781232809Sjmallett uint64_t mii : 1; 9782232809Sjmallett uint64_t reserved_41_47 : 7; 9783232809Sjmallett uint64_t ilk : 1; 9784232809Sjmallett uint64_t reserved_49_63 : 15; 9785232809Sjmallett#endif 9786232809Sjmallett } cn68xxp1; 9787232809Sjmallett}; 9788232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip3_pkt cvmx_ciu2_src_ppx_ip3_pkt_t; 9789232809Sjmallett 9790232809Sjmallett/** 9791232809Sjmallett * cvmx_ciu2_src_pp#_ip3_rml 9792232809Sjmallett */ 9793232809Sjmallettunion cvmx_ciu2_src_ppx_ip3_rml { 9794232809Sjmallett uint64_t u64; 9795232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_rml_s { 9796232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9797232809Sjmallett uint64_t reserved_56_63 : 8; 9798232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt source 9799232809Sjmallett CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */ 9800232809Sjmallett uint64_t reserved_49_51 : 3; 9801232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt source 9802232809Sjmallett CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */ 9803232809Sjmallett uint64_t reserved_41_47 : 7; 9804232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt source 9805232809Sjmallett CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */ 9806232809Sjmallett uint64_t reserved_37_39 : 3; 9807232809Sjmallett uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 9808232809Sjmallett See DPI DMA instruction completion */ 9809232809Sjmallett uint64_t reserved_34_35 : 2; 9810232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt source 9811232809Sjmallett CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */ 9812232809Sjmallett uint64_t sli : 1; /**< SLI interrupt source 9813232809Sjmallett CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */ 9814232809Sjmallett uint64_t reserved_31_31 : 1; 9815232809Sjmallett uint64_t key : 1; /**< KEY interrupt source 9816232809Sjmallett CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */ 9817232809Sjmallett uint64_t rad : 1; /**< RAD interrupt source 9818232809Sjmallett CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */ 9819232809Sjmallett uint64_t tim : 1; /**< TIM interrupt source 9820232809Sjmallett CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */ 9821232809Sjmallett uint64_t reserved_25_27 : 3; 9822232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt source 9823232809Sjmallett CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */ 9824232809Sjmallett uint64_t reserved_17_23 : 7; 9825232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt source 9826232809Sjmallett CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */ 9827232809Sjmallett uint64_t reserved_8_15 : 8; 9828232809Sjmallett uint64_t pko : 1; /**< PKO interrupt source 9829232809Sjmallett CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */ 9830232809Sjmallett uint64_t pip : 1; /**< PIP interrupt source 9831232809Sjmallett CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */ 9832232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt source 9833232809Sjmallett CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */ 9834232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt source 9835232809Sjmallett CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */ 9836232809Sjmallett uint64_t reserved_1_3 : 3; 9837232809Sjmallett uint64_t iob : 1; /**< IOB interrupt source 9838232809Sjmallett CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */ 9839232809Sjmallett#else 9840232809Sjmallett uint64_t iob : 1; 9841232809Sjmallett uint64_t reserved_1_3 : 3; 9842232809Sjmallett uint64_t fpa : 1; 9843232809Sjmallett uint64_t ipd : 1; 9844232809Sjmallett uint64_t pip : 1; 9845232809Sjmallett uint64_t pko : 1; 9846232809Sjmallett uint64_t reserved_8_15 : 8; 9847232809Sjmallett uint64_t sso : 1; 9848232809Sjmallett uint64_t reserved_17_23 : 7; 9849232809Sjmallett uint64_t zip : 1; 9850232809Sjmallett uint64_t reserved_25_27 : 3; 9851232809Sjmallett uint64_t tim : 1; 9852232809Sjmallett uint64_t rad : 1; 9853232809Sjmallett uint64_t key : 1; 9854232809Sjmallett uint64_t reserved_31_31 : 1; 9855232809Sjmallett uint64_t sli : 1; 9856232809Sjmallett uint64_t dpi : 1; 9857232809Sjmallett uint64_t reserved_34_35 : 2; 9858232809Sjmallett uint64_t dpi_dma : 1; 9859232809Sjmallett uint64_t reserved_37_39 : 3; 9860232809Sjmallett uint64_t dfa : 1; 9861232809Sjmallett uint64_t reserved_41_47 : 7; 9862232809Sjmallett uint64_t l2c : 1; 9863232809Sjmallett uint64_t reserved_49_51 : 3; 9864232809Sjmallett uint64_t trace : 4; 9865232809Sjmallett uint64_t reserved_56_63 : 8; 9866232809Sjmallett#endif 9867232809Sjmallett } s; 9868232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_rml_s cn68xx; 9869232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_rml_cn68xxp1 { 9870232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9871232809Sjmallett uint64_t reserved_56_63 : 8; 9872232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt source 9873232809Sjmallett CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */ 9874232809Sjmallett uint64_t reserved_49_51 : 3; 9875232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt source 9876232809Sjmallett CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */ 9877232809Sjmallett uint64_t reserved_41_47 : 7; 9878232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt source 9879232809Sjmallett CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */ 9880232809Sjmallett uint64_t reserved_34_39 : 6; 9881232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt source 9882232809Sjmallett CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */ 9883232809Sjmallett uint64_t sli : 1; /**< SLI interrupt source 9884232809Sjmallett CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */ 9885232809Sjmallett uint64_t reserved_31_31 : 1; 9886232809Sjmallett uint64_t key : 1; /**< KEY interrupt source 9887232809Sjmallett CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */ 9888232809Sjmallett uint64_t rad : 1; /**< RAD interrupt source 9889232809Sjmallett CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */ 9890232809Sjmallett uint64_t tim : 1; /**< TIM interrupt source 9891232809Sjmallett CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */ 9892232809Sjmallett uint64_t reserved_25_27 : 3; 9893232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt source 9894232809Sjmallett CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */ 9895232809Sjmallett uint64_t reserved_17_23 : 7; 9896232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt source 9897232809Sjmallett CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */ 9898232809Sjmallett uint64_t reserved_8_15 : 8; 9899232809Sjmallett uint64_t pko : 1; /**< PKO interrupt source 9900232809Sjmallett CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */ 9901232809Sjmallett uint64_t pip : 1; /**< PIP interrupt source 9902232809Sjmallett CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */ 9903232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt source 9904232809Sjmallett CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */ 9905232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt source 9906232809Sjmallett CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */ 9907232809Sjmallett uint64_t reserved_1_3 : 3; 9908232809Sjmallett uint64_t iob : 1; /**< IOB interrupt source 9909232809Sjmallett CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */ 9910232809Sjmallett#else 9911232809Sjmallett uint64_t iob : 1; 9912232809Sjmallett uint64_t reserved_1_3 : 3; 9913232809Sjmallett uint64_t fpa : 1; 9914232809Sjmallett uint64_t ipd : 1; 9915232809Sjmallett uint64_t pip : 1; 9916232809Sjmallett uint64_t pko : 1; 9917232809Sjmallett uint64_t reserved_8_15 : 8; 9918232809Sjmallett uint64_t sso : 1; 9919232809Sjmallett uint64_t reserved_17_23 : 7; 9920232809Sjmallett uint64_t zip : 1; 9921232809Sjmallett uint64_t reserved_25_27 : 3; 9922232809Sjmallett uint64_t tim : 1; 9923232809Sjmallett uint64_t rad : 1; 9924232809Sjmallett uint64_t key : 1; 9925232809Sjmallett uint64_t reserved_31_31 : 1; 9926232809Sjmallett uint64_t sli : 1; 9927232809Sjmallett uint64_t dpi : 1; 9928232809Sjmallett uint64_t reserved_34_39 : 6; 9929232809Sjmallett uint64_t dfa : 1; 9930232809Sjmallett uint64_t reserved_41_47 : 7; 9931232809Sjmallett uint64_t l2c : 1; 9932232809Sjmallett uint64_t reserved_49_51 : 3; 9933232809Sjmallett uint64_t trace : 4; 9934232809Sjmallett uint64_t reserved_56_63 : 8; 9935232809Sjmallett#endif 9936232809Sjmallett } cn68xxp1; 9937232809Sjmallett}; 9938232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip3_rml cvmx_ciu2_src_ppx_ip3_rml_t; 9939232809Sjmallett 9940232809Sjmallett/** 9941232809Sjmallett * cvmx_ciu2_src_pp#_ip3_wdog 9942232809Sjmallett */ 9943232809Sjmallettunion cvmx_ciu2_src_ppx_ip3_wdog { 9944232809Sjmallett uint64_t u64; 9945232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_wdog_s { 9946232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9947232809Sjmallett uint64_t reserved_32_63 : 32; 9948232809Sjmallett uint64_t wdog : 32; /**< 32 watchdog interrupts source 9949232809Sjmallett CIU2_RAW_WDOG & CIU2_EN_xx_yy_WDOG */ 9950232809Sjmallett#else 9951232809Sjmallett uint64_t wdog : 32; 9952232809Sjmallett uint64_t reserved_32_63 : 32; 9953232809Sjmallett#endif 9954232809Sjmallett } s; 9955232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xx; 9956232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xxp1; 9957232809Sjmallett}; 9958232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip3_wdog cvmx_ciu2_src_ppx_ip3_wdog_t; 9959232809Sjmallett 9960232809Sjmallett/** 9961232809Sjmallett * cvmx_ciu2_src_pp#_ip3_wrkq 9962232809Sjmallett */ 9963232809Sjmallettunion cvmx_ciu2_src_ppx_ip3_wrkq { 9964232809Sjmallett uint64_t u64; 9965232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_wrkq_s { 9966232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9967232809Sjmallett uint64_t workq : 64; /**< 64 work queue intr source, 9968232809Sjmallett CIU2_RAW_WRKQ & CIU2_EN_xx_yy_WRKQ */ 9969232809Sjmallett#else 9970232809Sjmallett uint64_t workq : 64; 9971232809Sjmallett#endif 9972232809Sjmallett } s; 9973232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xx; 9974232809Sjmallett struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xxp1; 9975232809Sjmallett}; 9976232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip3_wrkq cvmx_ciu2_src_ppx_ip3_wrkq_t; 9977232809Sjmallett 9978232809Sjmallett/** 9979232809Sjmallett * cvmx_ciu2_src_pp#_ip4_gpio 9980232809Sjmallett */ 9981232809Sjmallettunion cvmx_ciu2_src_ppx_ip4_gpio { 9982232809Sjmallett uint64_t u64; 9983232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_gpio_s { 9984232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9985232809Sjmallett uint64_t reserved_16_63 : 48; 9986232809Sjmallett uint64_t gpio : 16; /**< 16 GPIO interrupts source */ 9987232809Sjmallett#else 9988232809Sjmallett uint64_t gpio : 16; 9989232809Sjmallett uint64_t reserved_16_63 : 48; 9990232809Sjmallett#endif 9991232809Sjmallett } s; 9992232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xx; 9993232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xxp1; 9994232809Sjmallett}; 9995232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip4_gpio cvmx_ciu2_src_ppx_ip4_gpio_t; 9996232809Sjmallett 9997232809Sjmallett/** 9998232809Sjmallett * cvmx_ciu2_src_pp#_ip4_io 9999232809Sjmallett */ 10000232809Sjmallettunion cvmx_ciu2_src_ppx_ip4_io { 10001232809Sjmallett uint64_t u64; 10002232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_io_s { 10003232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10004232809Sjmallett uint64_t reserved_34_63 : 30; 10005232809Sjmallett uint64_t pem : 2; /**< PEMx interrupt source 10006232809Sjmallett CIU2_RAW_IO[PEM] & CIU2_EN_xx_yy_IO[PEM] */ 10007232809Sjmallett uint64_t reserved_18_31 : 14; 10008232809Sjmallett uint64_t pci_inta : 2; /**< PCI_INTA source 10009232809Sjmallett CIU2_RAW_IO[PCI_INTA] & CIU2_EN_xx_yy_IO[PCI_INTA] */ 10010232809Sjmallett uint64_t reserved_13_15 : 3; 10011232809Sjmallett uint64_t msired : 1; /**< MSI summary bit source 10012232809Sjmallett CIU2_RAW_IO[MSIRED] & CIU2_EN_xx_yy_IO[MSIRED] 10013232809Sjmallett This bit may not be functional in pass 1. */ 10014232809Sjmallett uint64_t pci_msi : 4; /**< PCIe/sRIO MSI source 10015232809Sjmallett CIU2_RAW_IO[PCI_MSI] & CIU2_EN_xx_yy_IO[PCI_MSI] */ 10016232809Sjmallett uint64_t reserved_4_7 : 4; 10017232809Sjmallett uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt source 10018232809Sjmallett CIU2_RAW_IO[PCI_INTR] &CIU2_EN_xx_yy_IO[PCI_INTR] */ 10019232809Sjmallett#else 10020232809Sjmallett uint64_t pci_intr : 4; 10021232809Sjmallett uint64_t reserved_4_7 : 4; 10022232809Sjmallett uint64_t pci_msi : 4; 10023232809Sjmallett uint64_t msired : 1; 10024232809Sjmallett uint64_t reserved_13_15 : 3; 10025232809Sjmallett uint64_t pci_inta : 2; 10026232809Sjmallett uint64_t reserved_18_31 : 14; 10027232809Sjmallett uint64_t pem : 2; 10028232809Sjmallett uint64_t reserved_34_63 : 30; 10029232809Sjmallett#endif 10030232809Sjmallett } s; 10031232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_io_s cn68xx; 10032232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_io_s cn68xxp1; 10033232809Sjmallett}; 10034232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip4_io cvmx_ciu2_src_ppx_ip4_io_t; 10035232809Sjmallett 10036232809Sjmallett/** 10037232809Sjmallett * cvmx_ciu2_src_pp#_ip4_mbox 10038232809Sjmallett */ 10039232809Sjmallettunion cvmx_ciu2_src_ppx_ip4_mbox { 10040232809Sjmallett uint64_t u64; 10041232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_mbox_s { 10042232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10043232809Sjmallett uint64_t reserved_4_63 : 60; 10044232809Sjmallett uint64_t mbox : 4; /**< Mailbox interrupt Source (RAW & ENABLE) 10045232809Sjmallett For CIU2_SRC_PPX_IPx_MBOX: 10046232809Sjmallett Four mailbox interrupts for entries 0-31 10047232809Sjmallett RAW & ENABLE 10048232809Sjmallett [3] is the or of <31:24> of CIU2_MBOX 10049232809Sjmallett [2] is the or of <23:16> of CIU2_MBOX 10050232809Sjmallett [1] is the or of <15:8> of CIU2_MBOX 10051232809Sjmallett [0] is the or of <7:0> of CIU2_MBOX 10052232809Sjmallett CIU2_MBOX value can be read out via CSR address 10053232809Sjmallett CIU_MBOX_SET/CLR 10054232809Sjmallett For CIU2_SRC_IOX_INT_MBOX: 10055232809Sjmallett always zero */ 10056232809Sjmallett#else 10057232809Sjmallett uint64_t mbox : 4; 10058232809Sjmallett uint64_t reserved_4_63 : 60; 10059232809Sjmallett#endif 10060232809Sjmallett } s; 10061232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xx; 10062232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xxp1; 10063232809Sjmallett}; 10064232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip4_mbox cvmx_ciu2_src_ppx_ip4_mbox_t; 10065232809Sjmallett 10066232809Sjmallett/** 10067232809Sjmallett * cvmx_ciu2_src_pp#_ip4_mem 10068232809Sjmallett */ 10069232809Sjmallettunion cvmx_ciu2_src_ppx_ip4_mem { 10070232809Sjmallett uint64_t u64; 10071232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_mem_s { 10072232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10073232809Sjmallett uint64_t reserved_4_63 : 60; 10074232809Sjmallett uint64_t lmc : 4; /**< LMC* interrupt source 10075232809Sjmallett CIU2_RAW_MEM[LMC] & CIU2_EN_xx_yy_MEM[LMC] */ 10076232809Sjmallett#else 10077232809Sjmallett uint64_t lmc : 4; 10078232809Sjmallett uint64_t reserved_4_63 : 60; 10079232809Sjmallett#endif 10080232809Sjmallett } s; 10081232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xx; 10082232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xxp1; 10083232809Sjmallett}; 10084232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip4_mem cvmx_ciu2_src_ppx_ip4_mem_t; 10085232809Sjmallett 10086232809Sjmallett/** 10087232809Sjmallett * cvmx_ciu2_src_pp#_ip4_mio 10088232809Sjmallett */ 10089232809Sjmallettunion cvmx_ciu2_src_ppx_ip4_mio { 10090232809Sjmallett uint64_t u64; 10091232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_mio_s { 10092232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10093232809Sjmallett uint64_t rst : 1; /**< MIO RST interrupt source 10094232809Sjmallett CIU2_RAW_MIO[RST] & CIU2_EN_xx_yy_MIO[RST] */ 10095232809Sjmallett uint64_t reserved_49_62 : 14; 10096232809Sjmallett uint64_t ptp : 1; /**< PTP interrupt source 10097232809Sjmallett CIU2_RAW_MIO[PTP] & CIU2_EN_xx_yy_MIO[PTP] */ 10098232809Sjmallett uint64_t reserved_45_47 : 3; 10099232809Sjmallett uint64_t usb_hci : 1; /**< USB HCI Interrupt source 10100232809Sjmallett CIU2_RAW_MIO[USB_HCI] & CIU2_EN_xx_yy_MIO[USB_HCI] */ 10101232809Sjmallett uint64_t reserved_41_43 : 3; 10102232809Sjmallett uint64_t usb_uctl : 1; /**< USB UCTL* interrupt source 10103232809Sjmallett CIU2_RAW_MIO[USB_UCTL] &CIU2_EN_xx_yy_MIO[USB_UCTL] */ 10104232809Sjmallett uint64_t reserved_38_39 : 2; 10105232809Sjmallett uint64_t uart : 2; /**< Two UART interrupts source 10106232809Sjmallett CIU2_RAW_MIO[UART] & CIU2_EN_xx_yy_MIO[UART] */ 10107232809Sjmallett uint64_t reserved_34_35 : 2; 10108232809Sjmallett uint64_t twsi : 2; /**< TWSI x Interrupt source 10109232809Sjmallett CIU2_RAW_MIO[TWSI] & CIU2_EN_xx_yy_MIO[TWSI] */ 10110232809Sjmallett uint64_t reserved_19_31 : 13; 10111232809Sjmallett uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt source 10112232809Sjmallett CIU2_RAW_MIO[BOOTDMA] & CIU2_EN_xx_yy_MIO[BOOTDMA] */ 10113232809Sjmallett uint64_t mio : 1; /**< MIO boot interrupt source 10114232809Sjmallett CIU2_RAW_MIO[MIO] & CIU2_EN_xx_yy_MIO[MIO] */ 10115232809Sjmallett uint64_t nand : 1; /**< NAND Flash Controller interrupt source 10116232809Sjmallett CIU2_RAW_MIO[NAND] & CIU2_EN_xx_yy_MIO[NANAD] */ 10117232809Sjmallett uint64_t reserved_12_15 : 4; 10118232809Sjmallett uint64_t timer : 4; /**< General timer interrupts source 10119232809Sjmallett CIU2_RAW_MIO[TIMER] & CIU2_EN_xx_yy_MIO[TIMER] */ 10120232809Sjmallett uint64_t reserved_3_7 : 5; 10121232809Sjmallett uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt source 10122232809Sjmallett CIU2_RAW_MIO[IPD_DRP] & CIU2_EN_xx_yy_MIO[IPD_DRP] */ 10123232809Sjmallett uint64_t ssoiq : 1; /**< SSO IQ interrupt source 10124232809Sjmallett CIU2_RAW_MIO[SSOIQ] & CIU2_EN_xx_yy_MIO[SSOIQ] */ 10125232809Sjmallett uint64_t ipdppthr : 1; /**< IPD per-port cnt threshold interrupt source 10126232809Sjmallett CIU2_RAW_MIO[IPDPPTHR] &CIU2_EN_xx_yy_MIO[IPDPPTHR] */ 10127232809Sjmallett#else 10128232809Sjmallett uint64_t ipdppthr : 1; 10129232809Sjmallett uint64_t ssoiq : 1; 10130232809Sjmallett uint64_t ipd_drp : 1; 10131232809Sjmallett uint64_t reserved_3_7 : 5; 10132232809Sjmallett uint64_t timer : 4; 10133232809Sjmallett uint64_t reserved_12_15 : 4; 10134232809Sjmallett uint64_t nand : 1; 10135232809Sjmallett uint64_t mio : 1; 10136232809Sjmallett uint64_t bootdma : 1; 10137232809Sjmallett uint64_t reserved_19_31 : 13; 10138232809Sjmallett uint64_t twsi : 2; 10139232809Sjmallett uint64_t reserved_34_35 : 2; 10140232809Sjmallett uint64_t uart : 2; 10141232809Sjmallett uint64_t reserved_38_39 : 2; 10142232809Sjmallett uint64_t usb_uctl : 1; 10143232809Sjmallett uint64_t reserved_41_43 : 3; 10144232809Sjmallett uint64_t usb_hci : 1; 10145232809Sjmallett uint64_t reserved_45_47 : 3; 10146232809Sjmallett uint64_t ptp : 1; 10147232809Sjmallett uint64_t reserved_49_62 : 14; 10148232809Sjmallett uint64_t rst : 1; 10149232809Sjmallett#endif 10150232809Sjmallett } s; 10151232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xx; 10152232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xxp1; 10153232809Sjmallett}; 10154232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip4_mio cvmx_ciu2_src_ppx_ip4_mio_t; 10155232809Sjmallett 10156232809Sjmallett/** 10157232809Sjmallett * cvmx_ciu2_src_pp#_ip4_pkt 10158232809Sjmallett */ 10159232809Sjmallettunion cvmx_ciu2_src_ppx_ip4_pkt { 10160232809Sjmallett uint64_t u64; 10161232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_pkt_s { 10162232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10163232809Sjmallett uint64_t reserved_54_63 : 10; 10164232809Sjmallett uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupts source 10165232809Sjmallett CIU2_RAW_PKT[ILK_DRP] & CIU2_EN_xx_yy_PKT[ILK_DRP] */ 10166232809Sjmallett uint64_t reserved_49_51 : 3; 10167232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts source 10168232809Sjmallett CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */ 10169232809Sjmallett uint64_t reserved_41_47 : 7; 10170232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source 10171232809Sjmallett CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */ 10172232809Sjmallett uint64_t reserved_33_39 : 7; 10173232809Sjmallett uint64_t agl : 1; /**< AGL interrupt source 10174232809Sjmallett CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */ 10175232809Sjmallett uint64_t reserved_13_31 : 19; 10176232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE 10177232809Sjmallett CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */ 10178232809Sjmallett uint64_t reserved_5_7 : 3; 10179232809Sjmallett uint64_t agx : 5; /**< GMX interrupt source 10180232809Sjmallett CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */ 10181232809Sjmallett#else 10182232809Sjmallett uint64_t agx : 5; 10183232809Sjmallett uint64_t reserved_5_7 : 3; 10184232809Sjmallett uint64_t gmx_drp : 5; 10185232809Sjmallett uint64_t reserved_13_31 : 19; 10186232809Sjmallett uint64_t agl : 1; 10187232809Sjmallett uint64_t reserved_33_39 : 7; 10188232809Sjmallett uint64_t mii : 1; 10189232809Sjmallett uint64_t reserved_41_47 : 7; 10190232809Sjmallett uint64_t ilk : 1; 10191232809Sjmallett uint64_t reserved_49_51 : 3; 10192232809Sjmallett uint64_t ilk_drp : 2; 10193232809Sjmallett uint64_t reserved_54_63 : 10; 10194232809Sjmallett#endif 10195232809Sjmallett } s; 10196232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_pkt_s cn68xx; 10197232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_pkt_cn68xxp1 { 10198232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10199232809Sjmallett uint64_t reserved_49_63 : 15; 10200232809Sjmallett uint64_t ilk : 1; /**< ILK interface interrupts source 10201232809Sjmallett CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */ 10202232809Sjmallett uint64_t reserved_41_47 : 7; 10203232809Sjmallett uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source 10204232809Sjmallett CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */ 10205232809Sjmallett uint64_t reserved_33_39 : 7; 10206232809Sjmallett uint64_t agl : 1; /**< AGL interrupt source 10207232809Sjmallett CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */ 10208232809Sjmallett uint64_t reserved_13_31 : 19; 10209232809Sjmallett uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE 10210232809Sjmallett CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */ 10211232809Sjmallett uint64_t reserved_5_7 : 3; 10212232809Sjmallett uint64_t agx : 5; /**< GMX interrupt source 10213232809Sjmallett CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */ 10214232809Sjmallett#else 10215232809Sjmallett uint64_t agx : 5; 10216232809Sjmallett uint64_t reserved_5_7 : 3; 10217232809Sjmallett uint64_t gmx_drp : 5; 10218232809Sjmallett uint64_t reserved_13_31 : 19; 10219232809Sjmallett uint64_t agl : 1; 10220232809Sjmallett uint64_t reserved_33_39 : 7; 10221232809Sjmallett uint64_t mii : 1; 10222232809Sjmallett uint64_t reserved_41_47 : 7; 10223232809Sjmallett uint64_t ilk : 1; 10224232809Sjmallett uint64_t reserved_49_63 : 15; 10225232809Sjmallett#endif 10226232809Sjmallett } cn68xxp1; 10227232809Sjmallett}; 10228232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip4_pkt cvmx_ciu2_src_ppx_ip4_pkt_t; 10229232809Sjmallett 10230232809Sjmallett/** 10231232809Sjmallett * cvmx_ciu2_src_pp#_ip4_rml 10232232809Sjmallett */ 10233232809Sjmallettunion cvmx_ciu2_src_ppx_ip4_rml { 10234232809Sjmallett uint64_t u64; 10235232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_rml_s { 10236232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10237232809Sjmallett uint64_t reserved_56_63 : 8; 10238232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt source 10239232809Sjmallett CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */ 10240232809Sjmallett uint64_t reserved_49_51 : 3; 10241232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt source 10242232809Sjmallett CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */ 10243232809Sjmallett uint64_t reserved_41_47 : 7; 10244232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt source 10245232809Sjmallett CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */ 10246232809Sjmallett uint64_t reserved_37_39 : 3; 10247232809Sjmallett uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 10248232809Sjmallett See DPI DMA instruction completion */ 10249232809Sjmallett uint64_t reserved_34_35 : 2; 10250232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt source 10251232809Sjmallett CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */ 10252232809Sjmallett uint64_t sli : 1; /**< SLI interrupt source 10253232809Sjmallett CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */ 10254232809Sjmallett uint64_t reserved_31_31 : 1; 10255232809Sjmallett uint64_t key : 1; /**< KEY interrupt source 10256232809Sjmallett CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */ 10257232809Sjmallett uint64_t rad : 1; /**< RAD interrupt source 10258232809Sjmallett CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */ 10259232809Sjmallett uint64_t tim : 1; /**< TIM interrupt source 10260232809Sjmallett CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */ 10261232809Sjmallett uint64_t reserved_25_27 : 3; 10262232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt source 10263232809Sjmallett CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */ 10264232809Sjmallett uint64_t reserved_17_23 : 7; 10265232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt source 10266232809Sjmallett CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */ 10267232809Sjmallett uint64_t reserved_8_15 : 8; 10268232809Sjmallett uint64_t pko : 1; /**< PKO interrupt source 10269232809Sjmallett CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */ 10270232809Sjmallett uint64_t pip : 1; /**< PIP interrupt source 10271232809Sjmallett CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */ 10272232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt source 10273232809Sjmallett CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */ 10274232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt source 10275232809Sjmallett CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */ 10276232809Sjmallett uint64_t reserved_1_3 : 3; 10277232809Sjmallett uint64_t iob : 1; /**< IOB interrupt source 10278232809Sjmallett CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */ 10279232809Sjmallett#else 10280232809Sjmallett uint64_t iob : 1; 10281232809Sjmallett uint64_t reserved_1_3 : 3; 10282232809Sjmallett uint64_t fpa : 1; 10283232809Sjmallett uint64_t ipd : 1; 10284232809Sjmallett uint64_t pip : 1; 10285232809Sjmallett uint64_t pko : 1; 10286232809Sjmallett uint64_t reserved_8_15 : 8; 10287232809Sjmallett uint64_t sso : 1; 10288232809Sjmallett uint64_t reserved_17_23 : 7; 10289232809Sjmallett uint64_t zip : 1; 10290232809Sjmallett uint64_t reserved_25_27 : 3; 10291232809Sjmallett uint64_t tim : 1; 10292232809Sjmallett uint64_t rad : 1; 10293232809Sjmallett uint64_t key : 1; 10294232809Sjmallett uint64_t reserved_31_31 : 1; 10295232809Sjmallett uint64_t sli : 1; 10296232809Sjmallett uint64_t dpi : 1; 10297232809Sjmallett uint64_t reserved_34_35 : 2; 10298232809Sjmallett uint64_t dpi_dma : 1; 10299232809Sjmallett uint64_t reserved_37_39 : 3; 10300232809Sjmallett uint64_t dfa : 1; 10301232809Sjmallett uint64_t reserved_41_47 : 7; 10302232809Sjmallett uint64_t l2c : 1; 10303232809Sjmallett uint64_t reserved_49_51 : 3; 10304232809Sjmallett uint64_t trace : 4; 10305232809Sjmallett uint64_t reserved_56_63 : 8; 10306232809Sjmallett#endif 10307232809Sjmallett } s; 10308232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_rml_s cn68xx; 10309232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_rml_cn68xxp1 { 10310232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10311232809Sjmallett uint64_t reserved_56_63 : 8; 10312232809Sjmallett uint64_t trace : 4; /**< Trace buffer interrupt source 10313232809Sjmallett CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */ 10314232809Sjmallett uint64_t reserved_49_51 : 3; 10315232809Sjmallett uint64_t l2c : 1; /**< L2C interrupt source 10316232809Sjmallett CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */ 10317232809Sjmallett uint64_t reserved_41_47 : 7; 10318232809Sjmallett uint64_t dfa : 1; /**< DFA interrupt source 10319232809Sjmallett CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */ 10320232809Sjmallett uint64_t reserved_34_39 : 6; 10321232809Sjmallett uint64_t dpi : 1; /**< DPI interrupt source 10322232809Sjmallett CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */ 10323232809Sjmallett uint64_t sli : 1; /**< SLI interrupt source 10324232809Sjmallett CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */ 10325232809Sjmallett uint64_t reserved_31_31 : 1; 10326232809Sjmallett uint64_t key : 1; /**< KEY interrupt source 10327232809Sjmallett CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */ 10328232809Sjmallett uint64_t rad : 1; /**< RAD interrupt source 10329232809Sjmallett CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */ 10330232809Sjmallett uint64_t tim : 1; /**< TIM interrupt source 10331232809Sjmallett CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */ 10332232809Sjmallett uint64_t reserved_25_27 : 3; 10333232809Sjmallett uint64_t zip : 1; /**< ZIP interrupt source 10334232809Sjmallett CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */ 10335232809Sjmallett uint64_t reserved_17_23 : 7; 10336232809Sjmallett uint64_t sso : 1; /**< SSO err interrupt source 10337232809Sjmallett CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */ 10338232809Sjmallett uint64_t reserved_8_15 : 8; 10339232809Sjmallett uint64_t pko : 1; /**< PKO interrupt source 10340232809Sjmallett CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */ 10341232809Sjmallett uint64_t pip : 1; /**< PIP interrupt source 10342232809Sjmallett CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */ 10343232809Sjmallett uint64_t ipd : 1; /**< IPD interrupt source 10344232809Sjmallett CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */ 10345232809Sjmallett uint64_t fpa : 1; /**< FPA interrupt source 10346232809Sjmallett CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */ 10347232809Sjmallett uint64_t reserved_1_3 : 3; 10348232809Sjmallett uint64_t iob : 1; /**< IOB interrupt source 10349232809Sjmallett CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */ 10350232809Sjmallett#else 10351232809Sjmallett uint64_t iob : 1; 10352232809Sjmallett uint64_t reserved_1_3 : 3; 10353232809Sjmallett uint64_t fpa : 1; 10354232809Sjmallett uint64_t ipd : 1; 10355232809Sjmallett uint64_t pip : 1; 10356232809Sjmallett uint64_t pko : 1; 10357232809Sjmallett uint64_t reserved_8_15 : 8; 10358232809Sjmallett uint64_t sso : 1; 10359232809Sjmallett uint64_t reserved_17_23 : 7; 10360232809Sjmallett uint64_t zip : 1; 10361232809Sjmallett uint64_t reserved_25_27 : 3; 10362232809Sjmallett uint64_t tim : 1; 10363232809Sjmallett uint64_t rad : 1; 10364232809Sjmallett uint64_t key : 1; 10365232809Sjmallett uint64_t reserved_31_31 : 1; 10366232809Sjmallett uint64_t sli : 1; 10367232809Sjmallett uint64_t dpi : 1; 10368232809Sjmallett uint64_t reserved_34_39 : 6; 10369232809Sjmallett uint64_t dfa : 1; 10370232809Sjmallett uint64_t reserved_41_47 : 7; 10371232809Sjmallett uint64_t l2c : 1; 10372232809Sjmallett uint64_t reserved_49_51 : 3; 10373232809Sjmallett uint64_t trace : 4; 10374232809Sjmallett uint64_t reserved_56_63 : 8; 10375232809Sjmallett#endif 10376232809Sjmallett } cn68xxp1; 10377232809Sjmallett}; 10378232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip4_rml cvmx_ciu2_src_ppx_ip4_rml_t; 10379232809Sjmallett 10380232809Sjmallett/** 10381232809Sjmallett * cvmx_ciu2_src_pp#_ip4_wdog 10382232809Sjmallett */ 10383232809Sjmallettunion cvmx_ciu2_src_ppx_ip4_wdog { 10384232809Sjmallett uint64_t u64; 10385232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_wdog_s { 10386232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10387232809Sjmallett uint64_t reserved_32_63 : 32; 10388232809Sjmallett uint64_t wdog : 32; /**< 32 watchdog interrupts source 10389232809Sjmallett CIU2_RAW_WDOG & CIU2_EN_xx_yy_WDOG */ 10390232809Sjmallett#else 10391232809Sjmallett uint64_t wdog : 32; 10392232809Sjmallett uint64_t reserved_32_63 : 32; 10393232809Sjmallett#endif 10394232809Sjmallett } s; 10395232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xx; 10396232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xxp1; 10397232809Sjmallett}; 10398232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip4_wdog cvmx_ciu2_src_ppx_ip4_wdog_t; 10399232809Sjmallett 10400232809Sjmallett/** 10401232809Sjmallett * cvmx_ciu2_src_pp#_ip4_wrkq 10402232809Sjmallett */ 10403232809Sjmallettunion cvmx_ciu2_src_ppx_ip4_wrkq { 10404232809Sjmallett uint64_t u64; 10405232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_wrkq_s { 10406232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10407232809Sjmallett uint64_t workq : 64; /**< 64 work queue intr source, 10408232809Sjmallett CIU2_RAW_WRKQ & CIU2_EN_xx_yy_WRKQ */ 10409232809Sjmallett#else 10410232809Sjmallett uint64_t workq : 64; 10411232809Sjmallett#endif 10412232809Sjmallett } s; 10413232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xx; 10414232809Sjmallett struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xxp1; 10415232809Sjmallett}; 10416232809Sjmalletttypedef union cvmx_ciu2_src_ppx_ip4_wrkq cvmx_ciu2_src_ppx_ip4_wrkq_t; 10417232809Sjmallett 10418232809Sjmallett/** 10419232809Sjmallett * cvmx_ciu2_sum_io#_int 10420232809Sjmallett */ 10421232809Sjmallettunion cvmx_ciu2_sum_iox_int { 10422232809Sjmallett uint64_t u64; 10423232809Sjmallett struct cvmx_ciu2_sum_iox_int_s { 10424232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10425232809Sjmallett uint64_t mbox : 4; /**< MBOX interrupt summary 10426232809Sjmallett Direct connect to CIU2_SRC_*_MBOX[MBOX] 10427232809Sjmallett See CIU_MBOX_SET/CLR / CIU2_SRC_*_MBOX */ 10428232809Sjmallett uint64_t reserved_8_59 : 52; 10429232809Sjmallett uint64_t gpio : 1; /**< GPIO interrupt summary, 10430232809Sjmallett Report ORed result of CIU2_SRC_*_GPIO[63:0] 10431232809Sjmallett See CIU2_RAW_GPIO / CIU2_SRC_*_GPIO */ 10432232809Sjmallett uint64_t pkt : 1; /**< Packet I/O interrupt summary 10433232809Sjmallett Report ORed result of CIU2_SRC_*_PKT[63:0] 10434232809Sjmallett See CIU2_RAW_PKT / CIU2_SRC_*_PKT */ 10435232809Sjmallett uint64_t mem : 1; /**< MEM interrupt Summary 10436232809Sjmallett Report ORed result of CIU2_SRC_*_MEM[63:0] 10437232809Sjmallett See CIU2_RAW_MEM / CIU2_SRC_*_MEM */ 10438232809Sjmallett uint64_t io : 1; /**< I/O interrupt summary 10439232809Sjmallett Report ORed result of CIU2_SRC_*_IO[63:0] 10440232809Sjmallett See CIU2_RAW_IO / CIU2_SRC_*_IO */ 10441232809Sjmallett uint64_t mio : 1; /**< MIO interrupt summary 10442232809Sjmallett Report ORed result of CIU2_SRC_*_MIO[63:0] 10443232809Sjmallett See CIU2_RAW_MIO / CIU2_SRC_*_MIO */ 10444232809Sjmallett uint64_t rml : 1; /**< RML Interrupt 10445232809Sjmallett Report ORed result of CIU2_SRC_*_RML[63:0] 10446232809Sjmallett See CIU2_RAW_RML / CIU2_SRC_*_RML */ 10447232809Sjmallett uint64_t wdog : 1; /**< WDOG summary bit 10448232809Sjmallett Report ORed result of CIU2_SRC_*_WDOG[63:0] 10449232809Sjmallett See CIU2_RAW_WDOG / CIU2_SRC_*_WDOG 10450232809Sjmallett This read-only bit reads as a one whenever 10451232809Sjmallett CIU2_RAW_WDOG bit is set and corresponding 10452232809Sjmallett enable bit in CIU2_EN_PPx_IPy_WDOG or 10453232809Sjmallett CIU2_EN_IOx_INT_WDOG is set, where x and y are 10454232809Sjmallett the same x and y in the CIU2_SUM_PPx_IPy or 10455232809Sjmallett CIU2_SUM_IOx_INT registers. 10456232809Sjmallett Alternatively, the CIU2_SRC_PPx_IPy_WDOG and 10457232809Sjmallett CIU2_SRC_IOx_INT_WDOG registers can be used. */ 10458232809Sjmallett uint64_t workq : 1; /**< 64 work queue interrupts 10459232809Sjmallett Report ORed result of CIU2_SRC_*_WRKQ[63:0] 10460232809Sjmallett See CIU2_RAW_WRKQ / CIU2_SRC_*_WRKQ 10461232809Sjmallett See SSO_WQ_INT[WQ_INT] 10462232809Sjmallett 1 bit/group. A copy of the R/W1C bit in the SSO. */ 10463232809Sjmallett#else 10464232809Sjmallett uint64_t workq : 1; 10465232809Sjmallett uint64_t wdog : 1; 10466232809Sjmallett uint64_t rml : 1; 10467232809Sjmallett uint64_t mio : 1; 10468232809Sjmallett uint64_t io : 1; 10469232809Sjmallett uint64_t mem : 1; 10470232809Sjmallett uint64_t pkt : 1; 10471232809Sjmallett uint64_t gpio : 1; 10472232809Sjmallett uint64_t reserved_8_59 : 52; 10473232809Sjmallett uint64_t mbox : 4; 10474232809Sjmallett#endif 10475232809Sjmallett } s; 10476232809Sjmallett struct cvmx_ciu2_sum_iox_int_s cn68xx; 10477232809Sjmallett struct cvmx_ciu2_sum_iox_int_s cn68xxp1; 10478232809Sjmallett}; 10479232809Sjmalletttypedef union cvmx_ciu2_sum_iox_int cvmx_ciu2_sum_iox_int_t; 10480232809Sjmallett 10481232809Sjmallett/** 10482232809Sjmallett * cvmx_ciu2_sum_pp#_ip2 10483232809Sjmallett */ 10484232809Sjmallettunion cvmx_ciu2_sum_ppx_ip2 { 10485232809Sjmallett uint64_t u64; 10486232809Sjmallett struct cvmx_ciu2_sum_ppx_ip2_s { 10487232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10488232809Sjmallett uint64_t mbox : 4; /**< MBOX interrupt summary 10489232809Sjmallett Direct connect to CIU2_SRC_*_MBOX[MBOX] 10490232809Sjmallett See CIU_MBOX_SET/CLR / CIU2_SRC_*_MBOX */ 10491232809Sjmallett uint64_t reserved_8_59 : 52; 10492232809Sjmallett uint64_t gpio : 1; /**< GPIO interrupt summary, 10493232809Sjmallett Report ORed result of CIU2_SRC_*_GPIO[63:0] 10494232809Sjmallett See CIU2_RAW_GPIO / CIU2_SRC_*_GPIO */ 10495232809Sjmallett uint64_t pkt : 1; /**< Packet I/O interrupt summary 10496232809Sjmallett Report ORed result of CIU2_SRC_*_PKT[63:0] 10497232809Sjmallett See CIU2_RAW_PKT / CIU2_SRC_*_PKT */ 10498232809Sjmallett uint64_t mem : 1; /**< MEM interrupt Summary 10499232809Sjmallett Report ORed result of CIU2_SRC_*_MEM[63:0] 10500232809Sjmallett See CIU2_RAW_MEM / CIU2_SRC_*_MEM */ 10501232809Sjmallett uint64_t io : 1; /**< I/O interrupt summary 10502232809Sjmallett Report ORed result of CIU2_SRC_*_IO[63:0] 10503232809Sjmallett See CIU2_RAW_IO / CIU2_SRC_*_IO */ 10504232809Sjmallett uint64_t mio : 1; /**< MIO interrupt summary 10505232809Sjmallett Report ORed result of CIU2_SRC_*_MIO[63:0] 10506232809Sjmallett See CIU2_RAW_MIO / CIU2_SRC_*_MIO */ 10507232809Sjmallett uint64_t rml : 1; /**< RML Interrupt 10508232809Sjmallett Report ORed result of CIU2_SRC_*_RML[63:0] 10509232809Sjmallett See CIU2_RAW_RML / CIU2_SRC_*_RML */ 10510232809Sjmallett uint64_t wdog : 1; /**< WDOG summary bit 10511232809Sjmallett Report ORed result of CIU2_SRC_*_WDOG[63:0] 10512232809Sjmallett See CIU2_RAW_WDOG / CIU2_SRC_*_WDOG 10513232809Sjmallett This read-only bit reads as a one whenever 10514232809Sjmallett CIU2_RAW_WDOG bit is set and corresponding 10515232809Sjmallett enable bit in CIU2_EN_PPx_IPy_WDOG or 10516232809Sjmallett CIU2_EN_IOx_INT_WDOG is set, where x and y are 10517232809Sjmallett the same x and y in the CIU2_SUM_PPx_IPy or 10518232809Sjmallett CIU2_SUM_IOx_INT registers. 10519232809Sjmallett Alternatively, the CIU2_SRC_PPx_IPy_WDOG and 10520232809Sjmallett CIU2_SRC_IOx_INT_WDOG registers can be used. */ 10521232809Sjmallett uint64_t workq : 1; /**< 64 work queue interrupts 10522232809Sjmallett Report ORed result of CIU2_SRC_*_WRKQ[63:0] 10523232809Sjmallett See CIU2_RAW_WRKQ / CIU2_SRC_*_WRKQ 10524232809Sjmallett See SSO_WQ_INT[WQ_INT] 10525232809Sjmallett 1 bit/group. A copy of the R/W1C bit in the SSO. */ 10526232809Sjmallett#else 10527232809Sjmallett uint64_t workq : 1; 10528232809Sjmallett uint64_t wdog : 1; 10529232809Sjmallett uint64_t rml : 1; 10530232809Sjmallett uint64_t mio : 1; 10531232809Sjmallett uint64_t io : 1; 10532232809Sjmallett uint64_t mem : 1; 10533232809Sjmallett uint64_t pkt : 1; 10534232809Sjmallett uint64_t gpio : 1; 10535232809Sjmallett uint64_t reserved_8_59 : 52; 10536232809Sjmallett uint64_t mbox : 4; 10537232809Sjmallett#endif 10538232809Sjmallett } s; 10539232809Sjmallett struct cvmx_ciu2_sum_ppx_ip2_s cn68xx; 10540232809Sjmallett struct cvmx_ciu2_sum_ppx_ip2_s cn68xxp1; 10541232809Sjmallett}; 10542232809Sjmalletttypedef union cvmx_ciu2_sum_ppx_ip2 cvmx_ciu2_sum_ppx_ip2_t; 10543232809Sjmallett 10544232809Sjmallett/** 10545232809Sjmallett * cvmx_ciu2_sum_pp#_ip3 10546232809Sjmallett */ 10547232809Sjmallettunion cvmx_ciu2_sum_ppx_ip3 { 10548232809Sjmallett uint64_t u64; 10549232809Sjmallett struct cvmx_ciu2_sum_ppx_ip3_s { 10550232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10551232809Sjmallett uint64_t mbox : 4; /**< MBOX interrupt summary 10552232809Sjmallett Direct connect to CIU2_SRC_*_MBOX[MBOX] 10553232809Sjmallett See CIU_MBOX_SET/CLR / CIU2_SRC_*_MBOX */ 10554232809Sjmallett uint64_t reserved_8_59 : 52; 10555232809Sjmallett uint64_t gpio : 1; /**< GPIO interrupt summary, 10556232809Sjmallett Report ORed result of CIU2_SRC_*_GPIO[63:0] 10557232809Sjmallett See CIU2_RAW_GPIO / CIU2_SRC_*_GPIO */ 10558232809Sjmallett uint64_t pkt : 1; /**< Packet I/O interrupt summary 10559232809Sjmallett Report ORed result of CIU2_SRC_*_PKT[63:0] 10560232809Sjmallett See CIU2_RAW_PKT / CIU2_SRC_*_PKT */ 10561232809Sjmallett uint64_t mem : 1; /**< MEM interrupt Summary 10562232809Sjmallett Report ORed result of CIU2_SRC_*_MEM[63:0] 10563232809Sjmallett See CIU2_RAW_MEM / CIU2_SRC_*_MEM */ 10564232809Sjmallett uint64_t io : 1; /**< I/O interrupt summary 10565232809Sjmallett Report ORed result of CIU2_SRC_*_IO[63:0] 10566232809Sjmallett See CIU2_RAW_IO / CIU2_SRC_*_IO */ 10567232809Sjmallett uint64_t mio : 1; /**< MIO interrupt summary 10568232809Sjmallett Report ORed result of CIU2_SRC_*_MIO[63:0] 10569232809Sjmallett See CIU2_RAW_MIO / CIU2_SRC_*_MIO */ 10570232809Sjmallett uint64_t rml : 1; /**< RML Interrupt 10571232809Sjmallett Report ORed result of CIU2_SRC_*_RML[63:0] 10572232809Sjmallett See CIU2_RAW_RML / CIU2_SRC_*_RML */ 10573232809Sjmallett uint64_t wdog : 1; /**< WDOG summary bit 10574232809Sjmallett Report ORed result of CIU2_SRC_*_WDOG[63:0] 10575232809Sjmallett See CIU2_RAW_WDOG / CIU2_SRC_*_WDOG 10576232809Sjmallett This read-only bit reads as a one whenever 10577232809Sjmallett CIU2_RAW_WDOG bit is set and corresponding 10578232809Sjmallett enable bit in CIU2_EN_PPx_IPy_WDOG or 10579232809Sjmallett CIU2_EN_IOx_INT_WDOG is set, where x and y are 10580232809Sjmallett the same x and y in the CIU2_SUM_PPx_IPy or 10581232809Sjmallett CIU2_SUM_IOx_INT registers. 10582232809Sjmallett Alternatively, the CIU2_SRC_PPx_IPy_WDOG and 10583232809Sjmallett CIU2_SRC_IOx_INT_WDOG registers can be used. */ 10584232809Sjmallett uint64_t workq : 1; /**< 64 work queue interrupts 10585232809Sjmallett Report ORed result of CIU2_SRC_*_WRKQ[63:0] 10586232809Sjmallett See CIU2_RAW_WRKQ / CIU2_SRC_*_WRKQ 10587232809Sjmallett See SSO_WQ_INT[WQ_INT] 10588232809Sjmallett 1 bit/group. A copy of the R/W1C bit in the SSO. */ 10589232809Sjmallett#else 10590232809Sjmallett uint64_t workq : 1; 10591232809Sjmallett uint64_t wdog : 1; 10592232809Sjmallett uint64_t rml : 1; 10593232809Sjmallett uint64_t mio : 1; 10594232809Sjmallett uint64_t io : 1; 10595232809Sjmallett uint64_t mem : 1; 10596232809Sjmallett uint64_t pkt : 1; 10597232809Sjmallett uint64_t gpio : 1; 10598232809Sjmallett uint64_t reserved_8_59 : 52; 10599232809Sjmallett uint64_t mbox : 4; 10600232809Sjmallett#endif 10601232809Sjmallett } s; 10602232809Sjmallett struct cvmx_ciu2_sum_ppx_ip3_s cn68xx; 10603232809Sjmallett struct cvmx_ciu2_sum_ppx_ip3_s cn68xxp1; 10604232809Sjmallett}; 10605232809Sjmalletttypedef union cvmx_ciu2_sum_ppx_ip3 cvmx_ciu2_sum_ppx_ip3_t; 10606232809Sjmallett 10607232809Sjmallett/** 10608232809Sjmallett * cvmx_ciu2_sum_pp#_ip4 10609232809Sjmallett */ 10610232809Sjmallettunion cvmx_ciu2_sum_ppx_ip4 { 10611232809Sjmallett uint64_t u64; 10612232809Sjmallett struct cvmx_ciu2_sum_ppx_ip4_s { 10613232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10614232809Sjmallett uint64_t mbox : 4; /**< MBOX interrupt summary 10615232809Sjmallett Direct connect to CIU2_SRC_*_MBOX[MBOX] 10616232809Sjmallett See CIU_MBOX_SET/CLR / CIU2_SRC_*_MBOX */ 10617232809Sjmallett uint64_t reserved_8_59 : 52; 10618232809Sjmallett uint64_t gpio : 1; /**< GPIO interrupt summary, 10619232809Sjmallett Report ORed result of CIU2_SRC_*_GPIO[63:0] 10620232809Sjmallett See CIU2_RAW_GPIO / CIU2_SRC_*_GPIO */ 10621232809Sjmallett uint64_t pkt : 1; /**< Packet I/O interrupt summary 10622232809Sjmallett Report ORed result of CIU2_SRC_*_PKT[63:0] 10623232809Sjmallett See CIU2_RAW_PKT / CIU2_SRC_*_PKT */ 10624232809Sjmallett uint64_t mem : 1; /**< MEM interrupt Summary 10625232809Sjmallett Report ORed result of CIU2_SRC_*_MEM[63:0] 10626232809Sjmallett See CIU2_RAW_MEM / CIU2_SRC_*_MEM */ 10627232809Sjmallett uint64_t io : 1; /**< I/O interrupt summary 10628232809Sjmallett Report ORed result of CIU2_SRC_*_IO[63:0] 10629232809Sjmallett See CIU2_RAW_IO / CIU2_SRC_*_IO */ 10630232809Sjmallett uint64_t mio : 1; /**< MIO interrupt summary 10631232809Sjmallett Report ORed result of CIU2_SRC_*_MIO[63:0] 10632232809Sjmallett See CIU2_RAW_MIO / CIU2_SRC_*_MIO */ 10633232809Sjmallett uint64_t rml : 1; /**< RML Interrupt 10634232809Sjmallett Report ORed result of CIU2_SRC_*_RML[63:0] 10635232809Sjmallett See CIU2_RAW_RML / CIU2_SRC_*_RML */ 10636232809Sjmallett uint64_t wdog : 1; /**< WDOG summary bit 10637232809Sjmallett Report ORed result of CIU2_SRC_*_WDOG[63:0] 10638232809Sjmallett See CIU2_RAW_WDOG / CIU2_SRC_*_WDOG 10639232809Sjmallett This read-only bit reads as a one whenever 10640232809Sjmallett CIU2_RAW_WDOG bit is set and corresponding 10641232809Sjmallett enable bit in CIU2_EN_PPx_IPy_WDOG or 10642232809Sjmallett CIU2_EN_IOx_INT_WDOG is set, where x and y are 10643232809Sjmallett the same x and y in the CIU2_SUM_PPx_IPy or 10644232809Sjmallett CIU2_SUM_IOx_INT registers. 10645232809Sjmallett Alternatively, the CIU2_SRC_PPx_IPy_WDOG and 10646232809Sjmallett CIU2_SRC_IOx_INT_WDOG registers can be used. */ 10647232809Sjmallett uint64_t workq : 1; /**< 64 work queue interrupts 10648232809Sjmallett Report ORed result of CIU2_SRC_*_WRKQ[63:0] 10649232809Sjmallett See CIU2_RAW_WRKQ / CIU2_SRC_*_WRKQ 10650232809Sjmallett See SSO_WQ_INT[WQ_INT] 10651232809Sjmallett 1 bit/group. A copy of the R/W1C bit in the SSO. */ 10652232809Sjmallett#else 10653232809Sjmallett uint64_t workq : 1; 10654232809Sjmallett uint64_t wdog : 1; 10655232809Sjmallett uint64_t rml : 1; 10656232809Sjmallett uint64_t mio : 1; 10657232809Sjmallett uint64_t io : 1; 10658232809Sjmallett uint64_t mem : 1; 10659232809Sjmallett uint64_t pkt : 1; 10660232809Sjmallett uint64_t gpio : 1; 10661232809Sjmallett uint64_t reserved_8_59 : 52; 10662232809Sjmallett uint64_t mbox : 4; 10663232809Sjmallett#endif 10664232809Sjmallett } s; 10665232809Sjmallett struct cvmx_ciu2_sum_ppx_ip4_s cn68xx; 10666232809Sjmallett struct cvmx_ciu2_sum_ppx_ip4_s cn68xxp1; 10667232809Sjmallett}; 10668232809Sjmalletttypedef union cvmx_ciu2_sum_ppx_ip4 cvmx_ciu2_sum_ppx_ip4_t; 10669232809Sjmallett 10670232809Sjmallett#endif 10671