cvmx-asxx-defs.h revision 215990
118316Swollman/***********************license start*************** 218316Swollman * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 318316Swollman * reserved. 418316Swollman * 518316Swollman * 618316Swollman * Redistribution and use in source and binary forms, with or without 718316Swollman * modification, are permitted provided that the following conditions are 818316Swollman * met: 918316Swollman * 1018316Swollman * * Redistributions of source code must retain the above copyright 1118316Swollman * notice, this list of conditions and the following disclaimer. 1218316Swollman * 1318316Swollman * * Redistributions in binary form must reproduce the above 1446303Smarkm * copyright notice, this list of conditions and the following 1518316Swollman * disclaimer in the documentation and/or other materials provided 1618316Swollman * with the distribution. 1718316Swollman 1818316Swollman * * Neither the name of Cavium Networks nor the names of 1918316Swollman * its contributors may be used to endorse or promote products 2018316Swollman * derived from this software without specific prior written 2118316Swollman * permission. 2218316Swollman 2318316Swollman * This Software, including technical data, may be subject to U.S. export control 2418316Swollman * laws, including the U.S. Export Administration Act and its associated 2518316Swollman * regulations, and may be subject to export or import regulations in other 2618316Swollman * countries. 2718316Swollman 2818316Swollman * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 2918316Swollman * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 3018316Swollman * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 3118316Swollman * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 3246303Smarkm * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 3350476Speter * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 3418316Swollman * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 3518316Swollman * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 3646303Smarkm * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 3746303Smarkm * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 3846303Smarkm ***********************license end**************************************/ 3946303Smarkm 4046303Smarkm 4146303Smarkm/** 4218316Swollman * cvmx-asxx-defs.h 4350476Speter * 4418316Swollman * Configuration and status register (CSR) type definitions for 4518316Swollman * Octeon asxx. 4646303Smarkm * 4718316Swollman * This file is auto generated. Do not edit. 4818316Swollman * 4918316Swollman * <hr>$Revision$<hr> 5018316Swollman * 5118316Swollman */ 5218316Swollman#ifndef __CVMX_ASXX_TYPEDEFS_H__ 5318316Swollman#define __CVMX_ASXX_TYPEDEFS_H__ 5418316Swollman 5518316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 5618316Swollmanstatic inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id) 5718316Swollman{ 5820339Swollman if (!( 5918316Swollman (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 6018316Swollman (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 6118316Swollman (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))))) 6218316Swollman cvmx_warn("CVMX_ASXX_GMII_RX_CLK_SET(%lu) is invalid on this chip\n", block_id); 6318316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000180ull); 6419880Swollman} 6519880Swollman#else 6619880Swollman#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull)) 6746303Smarkm#endif 6846303Smarkm#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 6946303Smarkmstatic inline uint64_t CVMX_ASXX_GMII_RX_DAT_SET(unsigned long block_id) 7018316Swollman{ 7118316Swollman if (!( 7218316Swollman (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 7319880Swollman (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 7418316Swollman (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))))) 7518316Swollman cvmx_warn("CVMX_ASXX_GMII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id); 7618316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000188ull); 7719880Swollman} 7818316Swollman#else 7918316Swollman#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull)) 8018316Swollman#endif 8118316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 8219880Swollmanstatic inline uint64_t CVMX_ASXX_INT_EN(unsigned long block_id) 8319880Swollman{ 8419880Swollman if (!( 8519880Swollman (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 8619880Swollman (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 8719880Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 8819880Swollman (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 8919880Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 9019880Swollman cvmx_warn("CVMX_ASXX_INT_EN(%lu) is invalid on this chip\n", block_id); 9119880Swollman return CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull; 9219880Swollman} 9319880Swollman#else 9419880Swollman#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull) 9519880Swollman#endif 9618316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 9718316Swollmanstatic inline uint64_t CVMX_ASXX_INT_REG(unsigned long block_id) 9818316Swollman{ 9918316Swollman if (!( 10018316Swollman (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 10118316Swollman (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 10218316Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 10318316Swollman (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 10418316Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 10518316Swollman cvmx_warn("CVMX_ASXX_INT_REG(%lu) is invalid on this chip\n", block_id); 10618316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull; 10746303Smarkm} 10818316Swollman#else 10918316Swollman#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull) 11018316Swollman#endif 11118316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 11218316Swollmanstatic inline uint64_t CVMX_ASXX_MII_RX_DAT_SET(unsigned long block_id) 11318316Swollman{ 11418316Swollman if (!( 11518316Swollman (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 11618316Swollman (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))))) 11718316Swollman cvmx_warn("CVMX_ASXX_MII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id); 11818316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000190ull); 11918316Swollman} 12018316Swollman#else 12118316Swollman#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull)) 12218316Swollman#endif 12318316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 12418316Swollmanstatic inline uint64_t CVMX_ASXX_PRT_LOOP(unsigned long block_id) 12518316Swollman{ 12618316Swollman if (!( 12718316Swollman (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 12818316Swollman (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 12918316Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 13018316Swollman (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 13118316Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 13218316Swollman cvmx_warn("CVMX_ASXX_PRT_LOOP(%lu) is invalid on this chip\n", block_id); 13318316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull; 13418316Swollman} 13518316Swollman#else 13618316Swollman#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull) 13718316Swollman#endif 13818316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 13918316Swollmanstatic inline uint64_t CVMX_ASXX_RLD_BYPASS(unsigned long block_id) 14018316Swollman{ 14118316Swollman if (!( 14218316Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 14318316Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 14418316Swollman cvmx_warn("CVMX_ASXX_RLD_BYPASS(%lu) is invalid on this chip\n", block_id); 14518316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull; 14618316Swollman} 14718316Swollman#else 14818316Swollman#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull) 14919880Swollman#endif 15018316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 15118316Swollmanstatic inline uint64_t CVMX_ASXX_RLD_BYPASS_SETTING(unsigned long block_id) 15218316Swollman{ 15318316Swollman if (!( 15418316Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 15518316Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 15637908Scharnier cvmx_warn("CVMX_ASXX_RLD_BYPASS_SETTING(%lu) is invalid on this chip\n", block_id); 15718316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull; 15818316Swollman} 15918316Swollman#else 16018316Swollman#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull) 16118316Swollman#endif 16218316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 16318316Swollmanstatic inline uint64_t CVMX_ASXX_RLD_COMP(unsigned long block_id) 16418316Swollman{ 16518316Swollman if (!( 16618316Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 16718316Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 16818316Swollman cvmx_warn("CVMX_ASXX_RLD_COMP(%lu) is invalid on this chip\n", block_id); 16918316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull; 17018316Swollman} 17118316Swollman#else 17218316Swollman#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull) 17318316Swollman#endif 17418316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 17518316Swollmanstatic inline uint64_t CVMX_ASXX_RLD_DATA_DRV(unsigned long block_id) 17618316Swollman{ 17718316Swollman if (!( 17818316Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 17918316Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 18018316Swollman cvmx_warn("CVMX_ASXX_RLD_DATA_DRV(%lu) is invalid on this chip\n", block_id); 18118316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull; 18218316Swollman} 18318316Swollman#else 18420339Swollman#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull) 18518316Swollman#endif 18618316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 18718316Swollmanstatic inline uint64_t CVMX_ASXX_RLD_FCRAM_MODE(unsigned long block_id) 18820339Swollman{ 18920339Swollman if (!( 19020339Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 19120339Swollman cvmx_warn("CVMX_ASXX_RLD_FCRAM_MODE(%lu) is invalid on this chip\n", block_id); 19220339Swollman return CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull; 19318316Swollman} 19418316Swollman#else 19518316Swollman#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull) 19618316Swollman#endif 19718316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 19818316Swollmanstatic inline uint64_t CVMX_ASXX_RLD_NCTL_STRONG(unsigned long block_id) 19918316Swollman{ 20018316Swollman if (!( 20118316Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 20218316Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 20318316Swollman cvmx_warn("CVMX_ASXX_RLD_NCTL_STRONG(%lu) is invalid on this chip\n", block_id); 20418316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull; 20518316Swollman} 20618316Swollman#else 20718316Swollman#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull) 20818316Swollman#endif 20918316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 21018316Swollmanstatic inline uint64_t CVMX_ASXX_RLD_NCTL_WEAK(unsigned long block_id) 21118316Swollman{ 21218316Swollman if (!( 21318316Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 21418316Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 21520339Swollman cvmx_warn("CVMX_ASXX_RLD_NCTL_WEAK(%lu) is invalid on this chip\n", block_id); 21637908Scharnier return CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull; 21719880Swollman} 21819880Swollman#else 21918316Swollman#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull) 22020339Swollman#endif 22119880Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 22218316Swollmanstatic inline uint64_t CVMX_ASXX_RLD_PCTL_STRONG(unsigned long block_id) 22320339Swollman{ 22419880Swollman if (!( 22519880Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 22619880Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 22720339Swollman cvmx_warn("CVMX_ASXX_RLD_PCTL_STRONG(%lu) is invalid on this chip\n", block_id); 22819880Swollman return CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull; 22920339Swollman} 23019880Swollman#else 23120339Swollman#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull) 23219880Swollman#endif 23320339Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 23420339Swollmanstatic inline uint64_t CVMX_ASXX_RLD_PCTL_WEAK(unsigned long block_id) 23520339Swollman{ 23646303Smarkm if (!( 23720339Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 23820339Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 23920339Swollman cvmx_warn("CVMX_ASXX_RLD_PCTL_WEAK(%lu) is invalid on this chip\n", block_id); 24020339Swollman return CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull; 24120339Swollman} 24220339Swollman#else 24320339Swollman#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull) 24420339Swollman#endif 24520339Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 24620339Swollmanstatic inline uint64_t CVMX_ASXX_RLD_SETTING(unsigned long block_id) 24720339Swollman{ 24820339Swollman if (!( 24920339Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 25019880Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 25118316Swollman cvmx_warn("CVMX_ASXX_RLD_SETTING(%lu) is invalid on this chip\n", block_id); 25219880Swollman return CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull; 25318316Swollman} 25418316Swollman#else 25518316Swollman#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull) 25619880Swollman#endif 25719880Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 25820339Swollmanstatic inline uint64_t CVMX_ASXX_RX_CLK_SETX(unsigned long offset, unsigned long block_id) 25919880Swollman{ 26019880Swollman if (!( 26119880Swollman (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) || 26219880Swollman (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) || 26319880Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) || 26446303Smarkm (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) || 26519880Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))))) 26646303Smarkm cvmx_warn("CVMX_ASXX_RX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id); 26719880Swollman return CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8; 26819880Swollman} 26919880Swollman#else 27046303Smarkm#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 27119880Swollman#endif 27220339Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 27319880Swollmanstatic inline uint64_t CVMX_ASXX_RX_PRT_EN(unsigned long block_id) 27419880Swollman{ 27546303Smarkm if (!( 27619880Swollman (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 27719880Swollman (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 27820339Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 27919880Swollman (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 28019880Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 28119880Swollman cvmx_warn("CVMX_ASXX_RX_PRT_EN(%lu) is invalid on this chip\n", block_id); 28246303Smarkm return CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull; 28346303Smarkm} 28419880Swollman#else 28519880Swollman#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull) 28619880Swollman#endif 28719880Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 28819880Swollmanstatic inline uint64_t CVMX_ASXX_RX_WOL(unsigned long block_id) 28919880Swollman{ 29019880Swollman if (!( 29119880Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 29220339Swollman cvmx_warn("CVMX_ASXX_RX_WOL(%lu) is invalid on this chip\n", block_id); 29319880Swollman return CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull; 29419880Swollman} 29519880Swollman#else 29646303Smarkm#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull) 29719880Swollman#endif 29819880Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 29919880Swollmanstatic inline uint64_t CVMX_ASXX_RX_WOL_MSK(unsigned long block_id) 30019880Swollman{ 30146303Smarkm if (!( 30219880Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 30346303Smarkm cvmx_warn("CVMX_ASXX_RX_WOL_MSK(%lu) is invalid on this chip\n", block_id); 30446303Smarkm return CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull; 30519880Swollman} 30646303Smarkm#else 30746303Smarkm#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull) 30819880Swollman#endif 30919880Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 31019880Swollmanstatic inline uint64_t CVMX_ASXX_RX_WOL_POWOK(unsigned long block_id) 31119880Swollman{ 31219880Swollman if (!( 31318316Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 31418316Swollman cvmx_warn("CVMX_ASXX_RX_WOL_POWOK(%lu) is invalid on this chip\n", block_id); 31518316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull; 31618316Swollman} 31718316Swollman#else 31818316Swollman#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull) 31937908Scharnier#endif 32018316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 32118316Swollmanstatic inline uint64_t CVMX_ASXX_RX_WOL_SIG(unsigned long block_id) 32218316Swollman{ 32318316Swollman if (!( 32419880Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 32518316Swollman cvmx_warn("CVMX_ASXX_RX_WOL_SIG(%lu) is invalid on this chip\n", block_id); 32618316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull; 32718316Swollman} 32818316Swollman#else 32918316Swollman#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull) 33020339Swollman#endif 33119880Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 33218316Swollmanstatic inline uint64_t CVMX_ASXX_TX_CLK_SETX(unsigned long offset, unsigned long block_id) 33318316Swollman{ 33418316Swollman if (!( 33518316Swollman (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) || 33618316Swollman (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) || 33718316Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) || 33818316Swollman (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) || 33918316Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))))) 34020339Swollman cvmx_warn("CVMX_ASXX_TX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id); 34118316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8; 34218316Swollman} 34318316Swollman#else 34418316Swollman#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 34518316Swollman#endif 34618316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 34718316Swollmanstatic inline uint64_t CVMX_ASXX_TX_COMP_BYP(unsigned long block_id) 34818316Swollman{ 34918316Swollman if (!( 35020339Swollman (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 35118316Swollman (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 35218316Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 35318316Swollman (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 35418316Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 35518316Swollman cvmx_warn("CVMX_ASXX_TX_COMP_BYP(%lu) is invalid on this chip\n", block_id); 35618316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull; 35718316Swollman} 35818316Swollman#else 35918316Swollman#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull) 36018316Swollman#endif 36118316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 36218316Swollmanstatic inline uint64_t CVMX_ASXX_TX_HI_WATERX(unsigned long offset, unsigned long block_id) 36318316Swollman{ 36418316Swollman if (!( 36518316Swollman (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) || 36618316Swollman (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) || 36718316Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) || 36818316Swollman (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) || 36918316Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))))) 37018316Swollman cvmx_warn("CVMX_ASXX_TX_HI_WATERX(%lu,%lu) is invalid on this chip\n", offset, block_id); 37118316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8; 37219880Swollman} 37318316Swollman#else 37419880Swollman#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 37518316Swollman#endif 37618316Swollman#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 37719880Swollmanstatic inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id) 37818316Swollman{ 37918316Swollman if (!( 38018316Swollman (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 38119880Swollman (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 38218316Swollman (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 38318316Swollman (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 38418316Swollman (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 38518316Swollman cvmx_warn("CVMX_ASXX_TX_PRT_EN(%lu) is invalid on this chip\n", block_id); 38618316Swollman return CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull; 38718316Swollman} 38818316Swollman#else 38918316Swollman#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull) 39018316Swollman#endif 39118316Swollman 39218316Swollman/** 39318316Swollman * cvmx_asx#_gmii_rx_clk_set 39418316Swollman * 39518316Swollman * ASX_GMII_RX_CLK_SET = GMII Clock delay setting 39646303Smarkm * 39746303Smarkm */ 39846303Smarkmunion cvmx_asxx_gmii_rx_clk_set 39946303Smarkm{ 40046303Smarkm uint64_t u64; 40146303Smarkm struct cvmx_asxx_gmii_rx_clk_set_s 40246303Smarkm { 40346303Smarkm#if __BYTE_ORDER == __BIG_ENDIAN 40418316Swollman uint64_t reserved_5_63 : 59; 40518316Swollman uint64_t setting : 5; /**< Setting to place on the RXCLK (GMII receive clk) 40618316Swollman delay line. The intrinsic delay can range from 40718316Swollman 50ps to 80ps per tap. */ 40818316Swollman#else 40918316Swollman uint64_t setting : 5; 41018316Swollman uint64_t reserved_5_63 : 59; 41118316Swollman#endif 41218316Swollman } s; 41318316Swollman struct cvmx_asxx_gmii_rx_clk_set_s cn30xx; 41418316Swollman struct cvmx_asxx_gmii_rx_clk_set_s cn31xx; 41518316Swollman struct cvmx_asxx_gmii_rx_clk_set_s cn50xx; 41618316Swollman}; 41718316Swollmantypedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t; 41818316Swollman 41918316Swollman/** 42018316Swollman * cvmx_asx#_gmii_rx_dat_set 42118316Swollman * 42218316Swollman * ASX_GMII_RX_DAT_SET = GMII Clock delay setting 42319880Swollman * 42419880Swollman */ 42519880Swollmanunion cvmx_asxx_gmii_rx_dat_set 42619880Swollman{ 42719880Swollman uint64_t u64; 42819880Swollman struct cvmx_asxx_gmii_rx_dat_set_s 42918316Swollman { 43018316Swollman#if __BYTE_ORDER == __BIG_ENDIAN 43118316Swollman uint64_t reserved_5_63 : 59; 43218316Swollman uint64_t setting : 5; /**< Setting to place on the RXD (GMII receive data) 43318316Swollman delay lines. The intrinsic delay can range from 43418316Swollman 50ps to 80ps per tap. */ 43518316Swollman#else 43619880Swollman uint64_t setting : 5; 43718316Swollman uint64_t reserved_5_63 : 59; 43818316Swollman#endif 43918316Swollman } s; 44018316Swollman struct cvmx_asxx_gmii_rx_dat_set_s cn30xx; 44118316Swollman struct cvmx_asxx_gmii_rx_dat_set_s cn31xx; 44218316Swollman struct cvmx_asxx_gmii_rx_dat_set_s cn50xx; 44318316Swollman}; 44418316Swollmantypedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t; 44518316Swollman 44618316Swollman/** 44718316Swollman * cvmx_asx#_int_en 44818316Swollman * 44918316Swollman * ASX_INT_EN = Interrupt Enable 45018316Swollman * 45118316Swollman */ 45246303Smarkmunion cvmx_asxx_int_en 45318316Swollman{ 45418316Swollman uint64_t u64; 45518316Swollman struct cvmx_asxx_int_en_s 45618316Swollman { 45718316Swollman#if __BYTE_ORDER == __BIG_ENDIAN 45846303Smarkm uint64_t reserved_12_63 : 52; 45946303Smarkm uint64_t txpsh : 4; /**< TX FIFO overflow on RMGII port */ 46018316Swollman uint64_t txpop : 4; /**< TX FIFO underflow on RMGII port */ 46118316Swollman uint64_t ovrflw : 4; /**< RX FIFO overflow on RMGII port */ 46219880Swollman#else 46318316Swollman uint64_t ovrflw : 4; 46418316Swollman uint64_t txpop : 4; 46518316Swollman uint64_t txpsh : 4; 46619880Swollman uint64_t reserved_12_63 : 52; 46718316Swollman#endif 46818316Swollman } s; 46918316Swollman struct cvmx_asxx_int_en_cn30xx 47018316Swollman { 47119880Swollman#if __BYTE_ORDER == __BIG_ENDIAN 47219880Swollman uint64_t reserved_11_63 : 53; 47318316Swollman uint64_t txpsh : 3; /**< TX FIFO overflow on RMGII port */ 47419880Swollman uint64_t reserved_7_7 : 1; 47519880Swollman uint64_t txpop : 3; /**< TX FIFO underflow on RMGII port */ 47618316Swollman uint64_t reserved_3_3 : 1; 47718316Swollman uint64_t ovrflw : 3; /**< RX FIFO overflow on RMGII port */ 47818316Swollman#else 47918316Swollman uint64_t ovrflw : 3; 48018316Swollman uint64_t reserved_3_3 : 1; 48118316Swollman uint64_t txpop : 3; 48218316Swollman uint64_t reserved_7_7 : 1; 48318316Swollman uint64_t txpsh : 3; 48418316Swollman uint64_t reserved_11_63 : 53; 48518316Swollman#endif 48618316Swollman } cn30xx; 48718316Swollman struct cvmx_asxx_int_en_cn30xx cn31xx; 48818316Swollman struct cvmx_asxx_int_en_s cn38xx; 48918316Swollman struct cvmx_asxx_int_en_s cn38xxp2; 49018316Swollman struct cvmx_asxx_int_en_cn30xx cn50xx; 49118316Swollman struct cvmx_asxx_int_en_s cn58xx; 49218316Swollman struct cvmx_asxx_int_en_s cn58xxp1; 49318316Swollman}; 49418316Swollmantypedef union cvmx_asxx_int_en cvmx_asxx_int_en_t; 49518316Swollman 49637908Scharnier/** 49718316Swollman * cvmx_asx#_int_reg 49818316Swollman * 49918316Swollman * ASX_INT_REG = Interrupt Register 50018316Swollman * 50118316Swollman */ 50218316Swollmanunion cvmx_asxx_int_reg 50318316Swollman{ 50418316Swollman uint64_t u64; 50518316Swollman struct cvmx_asxx_int_reg_s 50618316Swollman { 50718316Swollman#if __BYTE_ORDER == __BIG_ENDIAN 50818316Swollman uint64_t reserved_12_63 : 52; 50918316Swollman uint64_t txpsh : 4; /**< TX FIFO overflow on RMGII port */ 51018316Swollman uint64_t txpop : 4; /**< TX FIFO underflow on RMGII port */ 51118316Swollman uint64_t ovrflw : 4; /**< RX FIFO overflow on RMGII port */ 51218316Swollman#else 51318316Swollman uint64_t ovrflw : 4; 51418316Swollman uint64_t txpop : 4; 51546303Smarkm uint64_t txpsh : 4; 51618316Swollman uint64_t reserved_12_63 : 52; 51718316Swollman#endif 51818316Swollman } s; 51918316Swollman struct cvmx_asxx_int_reg_cn30xx 52018316Swollman { 52118316Swollman#if __BYTE_ORDER == __BIG_ENDIAN 52218316Swollman uint64_t reserved_11_63 : 53; 52318316Swollman uint64_t txpsh : 3; /**< TX FIFO overflow on RMGII port */ 52418316Swollman uint64_t reserved_7_7 : 1; 52518316Swollman uint64_t txpop : 3; /**< TX FIFO underflow on RMGII port */ 52618316Swollman uint64_t reserved_3_3 : 1; 52718316Swollman uint64_t ovrflw : 3; /**< RX FIFO overflow on RMGII port */ 52818316Swollman#else 52918316Swollman uint64_t ovrflw : 3; 53018316Swollman uint64_t reserved_3_3 : 1; 53118316Swollman uint64_t txpop : 3; 53218316Swollman uint64_t reserved_7_7 : 1; 53346303Smarkm uint64_t txpsh : 3; 53446303Smarkm uint64_t reserved_11_63 : 53; 53546303Smarkm#endif 53618316Swollman } cn30xx; 53718316Swollman struct cvmx_asxx_int_reg_cn30xx cn31xx; 53818316Swollman struct cvmx_asxx_int_reg_s cn38xx; 53918316Swollman struct cvmx_asxx_int_reg_s cn38xxp2; 54018316Swollman struct cvmx_asxx_int_reg_cn30xx cn50xx; 54118316Swollman struct cvmx_asxx_int_reg_s cn58xx; 54218316Swollman struct cvmx_asxx_int_reg_s cn58xxp1; 54318316Swollman}; 54418316Swollmantypedef union cvmx_asxx_int_reg cvmx_asxx_int_reg_t; 54546303Smarkm 54646303Smarkm/** 54746303Smarkm * cvmx_asx#_mii_rx_dat_set 54846303Smarkm * 54946303Smarkm * ASX_MII_RX_DAT_SET = GMII Clock delay setting 55046303Smarkm * 55146303Smarkm */ 55246303Smarkmunion cvmx_asxx_mii_rx_dat_set 55318316Swollman{ 55446303Smarkm uint64_t u64; 55546303Smarkm struct cvmx_asxx_mii_rx_dat_set_s 55646303Smarkm { 55718316Swollman#if __BYTE_ORDER == __BIG_ENDIAN 55818316Swollman uint64_t reserved_5_63 : 59; 55918316Swollman uint64_t setting : 5; /**< Setting to place on the RXD (MII receive data) 56018316Swollman delay lines. The intrinsic delay can range from 56118316Swollman 50ps to 80ps per tap. */ 56218316Swollman#else 56318316Swollman uint64_t setting : 5; 56418316Swollman uint64_t reserved_5_63 : 59; 56546303Smarkm#endif 56646303Smarkm } s; 56746303Smarkm struct cvmx_asxx_mii_rx_dat_set_s cn30xx; 56846303Smarkm struct cvmx_asxx_mii_rx_dat_set_s cn50xx; 56918316Swollman}; 57018316Swollmantypedef union cvmx_asxx_mii_rx_dat_set cvmx_asxx_mii_rx_dat_set_t; 57118316Swollman 57218316Swollman/** 57318316Swollman * cvmx_asx#_prt_loop 57418316Swollman * 57518316Swollman * ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins) 57646303Smarkm * 57746303Smarkm */ 57818316Swollmanunion cvmx_asxx_prt_loop 57946303Smarkm{ 58018316Swollman uint64_t u64; 58118316Swollman struct cvmx_asxx_prt_loop_s 58218316Swollman { 58318316Swollman#if __BYTE_ORDER == __BIG_ENDIAN 58418316Swollman uint64_t reserved_8_63 : 56; 58518316Swollman uint64_t ext_loop : 4; /**< External Loopback Enable 58618316Swollman 0 = No Loopback (TX FIFO is filled by RMGII) 58746303Smarkm 1 = RX FIFO drives the TX FIFO 58818316Swollman - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex) 58918316Swollman - GMX_PRT_CFG[SPEED] must be 1 (GigE speed) 59020339Swollman - core clock > 250MHZ 59120339Swollman - rxc must not deviate from the +-50ppm 59246303Smarkm - if txc>rxc, idle cycle may drop over time */ 59346303Smarkm uint64_t int_loop : 4; /**< Internal Loopback Enable 59446303Smarkm 0 = No Loopback (RX FIFO is filled by RMGII pins) 59518316Swollman 1 = TX FIFO drives the RX FIFO 59646303Smarkm Note, in internal loop-back mode, the RGMII link 59718316Swollman status is not used (since there is no real PHY). 59818316Swollman Software cannot use the inband status. */ 59918316Swollman#else 60018316Swollman uint64_t int_loop : 4; 60146303Smarkm uint64_t ext_loop : 4; 60246303Smarkm uint64_t reserved_8_63 : 56; 60346303Smarkm#endif 60446303Smarkm } s; 60546303Smarkm struct cvmx_asxx_prt_loop_cn30xx 60646303Smarkm { 60746303Smarkm#if __BYTE_ORDER == __BIG_ENDIAN 60846303Smarkm uint64_t reserved_7_63 : 57; 60946303Smarkm uint64_t ext_loop : 3; /**< External Loopback Enable 61046303Smarkm 0 = No Loopback (TX FIFO is filled by RMGII) 61146303Smarkm 1 = RX FIFO drives the TX FIFO 61246303Smarkm - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex) 61346303Smarkm - GMX_PRT_CFG[SPEED] must be 1 (GigE speed) 61446303Smarkm - core clock > 250MHZ 61546303Smarkm - rxc must not deviate from the +-50ppm 61646303Smarkm - if txc>rxc, idle cycle may drop over time */ 61746303Smarkm uint64_t reserved_3_3 : 1; 61846303Smarkm uint64_t int_loop : 3; /**< Internal Loopback Enable 61946303Smarkm 0 = No Loopback (RX FIFO is filled by RMGII pins) 62046303Smarkm 1 = TX FIFO drives the RX FIFO 62146303Smarkm - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex) 62246303Smarkm - GMX_PRT_CFG[SPEED] must be 1 (GigE speed) 62346303Smarkm - GMX_TX_CLK[CLK_CNT] must be 1 62446303Smarkm Note, in internal loop-back mode, the RGMII link 62546303Smarkm status is not used (since there is no real PHY). 62646303Smarkm Software cannot use the inband status. */ 62746303Smarkm#else 62818316Swollman uint64_t int_loop : 3; 62918316Swollman uint64_t reserved_3_3 : 1; 63018316Swollman uint64_t ext_loop : 3; 63146303Smarkm uint64_t reserved_7_63 : 57; 63246303Smarkm#endif 63346303Smarkm } cn30xx; 63446303Smarkm struct cvmx_asxx_prt_loop_cn30xx cn31xx; 63546303Smarkm struct cvmx_asxx_prt_loop_s cn38xx; 63646303Smarkm struct cvmx_asxx_prt_loop_s cn38xxp2; 63746303Smarkm struct cvmx_asxx_prt_loop_cn30xx cn50xx; 63846303Smarkm struct cvmx_asxx_prt_loop_s cn58xx; 63946303Smarkm struct cvmx_asxx_prt_loop_s cn58xxp1; 64018316Swollman}; 64146303Smarkmtypedef union cvmx_asxx_prt_loop cvmx_asxx_prt_loop_t; 64218316Swollman 64346303Smarkm/** 64446303Smarkm * cvmx_asx#_rld_bypass 64518316Swollman * 64646303Smarkm * ASX_RLD_BYPASS 64746303Smarkm * 64846303Smarkm */ 64946303Smarkmunion cvmx_asxx_rld_bypass 65046303Smarkm{ 65146303Smarkm uint64_t u64; 65246303Smarkm struct cvmx_asxx_rld_bypass_s 65319880Swollman { 65419880Swollman#if __BYTE_ORDER == __BIG_ENDIAN 65519880Swollman uint64_t reserved_1_63 : 63; 65618316Swollman uint64_t bypass : 1; /**< When set, the rld_dll setting is bypassed with 65718316Swollman ASX_RLD_BYPASS_SETTING */ 65818316Swollman#else 65918316Swollman uint64_t bypass : 1; 66018316Swollman uint64_t reserved_1_63 : 63; 66118316Swollman#endif 66218316Swollman } s; 66318316Swollman struct cvmx_asxx_rld_bypass_s cn38xx; 66418316Swollman struct cvmx_asxx_rld_bypass_s cn38xxp2; 66518316Swollman struct cvmx_asxx_rld_bypass_s cn58xx; 66618316Swollman struct cvmx_asxx_rld_bypass_s cn58xxp1; 66718316Swollman}; 66818316Swollmantypedef union cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_t; 66918316Swollman 67018316Swollman/** 67118316Swollman * cvmx_asx#_rld_bypass_setting 67218316Swollman * 67318316Swollman * ASX_RLD_BYPASS_SETTING 67418316Swollman * 67518316Swollman */ 67619880Swollmanunion cvmx_asxx_rld_bypass_setting 67719880Swollman{ 67818316Swollman uint64_t u64; 67918316Swollman struct cvmx_asxx_rld_bypass_setting_s 68019880Swollman { 68118316Swollman#if __BYTE_ORDER == __BIG_ENDIAN 68218316Swollman uint64_t reserved_5_63 : 59; 68318316Swollman uint64_t setting : 5; /**< The rld_dll setting bypass value */ 68418316Swollman#else 68518316Swollman uint64_t setting : 5; 68618316Swollman uint64_t reserved_5_63 : 59; 68718316Swollman#endif 68818316Swollman } s; 68918316Swollman struct cvmx_asxx_rld_bypass_setting_s cn38xx; 69018316Swollman struct cvmx_asxx_rld_bypass_setting_s cn38xxp2; 69118316Swollman struct cvmx_asxx_rld_bypass_setting_s cn58xx; 69218316Swollman struct cvmx_asxx_rld_bypass_setting_s cn58xxp1; 69318316Swollman}; 69418316Swollmantypedef union cvmx_asxx_rld_bypass_setting cvmx_asxx_rld_bypass_setting_t; 69518316Swollman 69618316Swollman/** 69718316Swollman * cvmx_asx#_rld_comp 69818316Swollman * 69918316Swollman * ASX_RLD_COMP 70018316Swollman * 70118316Swollman */ 70218316Swollmanunion cvmx_asxx_rld_comp 70318316Swollman{ 70418316Swollman uint64_t u64; 70518316Swollman struct cvmx_asxx_rld_comp_s 70618316Swollman { 70718316Swollman#if __BYTE_ORDER == __BIG_ENDIAN 70818316Swollman uint64_t reserved_9_63 : 55; 70918316Swollman uint64_t pctl : 5; /**< PCTL Compensation Value 71018316Swollman These bits reflect the computed compensation 71118316Swollman values from the built-in compensation circuit. */ 71218316Swollman uint64_t nctl : 4; /**< These bits reflect the computed compensation 71318316Swollman values from the built-in compensation circuit. */ 71418316Swollman#else 71518316Swollman uint64_t nctl : 4; 71618316Swollman uint64_t pctl : 5; 71718316Swollman uint64_t reserved_9_63 : 55; 71818316Swollman#endif 71918316Swollman } s; 72018316Swollman struct cvmx_asxx_rld_comp_cn38xx 72146303Smarkm { 72246303Smarkm#if __BYTE_ORDER == __BIG_ENDIAN 72346303Smarkm uint64_t reserved_8_63 : 56; 72446303Smarkm uint64_t pctl : 4; /**< These bits reflect the computed compensation 72519880Swollman values from the built-in compensation circuit. */ 72618316Swollman uint64_t nctl : 4; /**< These bits reflect the computed compensation 72746303Smarkm values from the built-in compensation circuit. */ 72846303Smarkm#else 72946303Smarkm uint64_t nctl : 4; 73046303Smarkm uint64_t pctl : 4; 73146303Smarkm uint64_t reserved_8_63 : 56; 73218316Swollman#endif 73319880Swollman } cn38xx; 73419880Swollman struct cvmx_asxx_rld_comp_cn38xx cn38xxp2; 73518316Swollman struct cvmx_asxx_rld_comp_s cn58xx; 73646303Smarkm struct cvmx_asxx_rld_comp_s cn58xxp1; 73746303Smarkm}; 73846303Smarkmtypedef union cvmx_asxx_rld_comp cvmx_asxx_rld_comp_t; 73946303Smarkm 74018316Swollman/** 74118316Swollman * cvmx_asx#_rld_data_drv 74218316Swollman * 74318316Swollman * ASX_RLD_DATA_DRV 74418316Swollman * 74518316Swollman */ 74646303Smarkmunion cvmx_asxx_rld_data_drv 74746303Smarkm{ 74818316Swollman uint64_t u64; 74919880Swollman struct cvmx_asxx_rld_data_drv_s 75018316Swollman { 75118316Swollman#if __BYTE_ORDER == __BIG_ENDIAN 75246303Smarkm uint64_t reserved_8_63 : 56; 75346303Smarkm uint64_t pctl : 4; /**< These bits specify a driving strength (positive 75418316Swollman integer) for the RLD I/Os when the built-in 75518316Swollman compensation circuit is bypassed. */ 75618316Swollman uint64_t nctl : 4; /**< These bits specify a driving strength (positive 75718316Swollman integer) for the RLD I/Os when the built-in 75819880Swollman compensation circuit is bypassed. */ 75920339Swollman#else 76019880Swollman uint64_t nctl : 4; 76120339Swollman uint64_t pctl : 4; 76220339Swollman uint64_t reserved_8_63 : 56; 76319880Swollman#endif 76419880Swollman } s; 76519880Swollman struct cvmx_asxx_rld_data_drv_s cn38xx; 76619880Swollman struct cvmx_asxx_rld_data_drv_s cn38xxp2; 76719880Swollman struct cvmx_asxx_rld_data_drv_s cn58xx; 76819880Swollman struct cvmx_asxx_rld_data_drv_s cn58xxp1; 76919880Swollman}; 77018316Swollmantypedef union cvmx_asxx_rld_data_drv cvmx_asxx_rld_data_drv_t; 77119880Swollman 77218316Swollman/** 77319880Swollman * cvmx_asx#_rld_fcram_mode 77419880Swollman * 77518316Swollman * ASX_RLD_FCRAM_MODE 77619880Swollman * 77719880Swollman */ 77819880Swollmanunion cvmx_asxx_rld_fcram_mode 77919880Swollman{ 78019880Swollman uint64_t u64; 78118316Swollman struct cvmx_asxx_rld_fcram_mode_s 78218316Swollman { 78318316Swollman#if __BYTE_ORDER == __BIG_ENDIAN 78419880Swollman uint64_t reserved_1_63 : 63; 78519880Swollman uint64_t mode : 1; /**< Memory Mode 78619880Swollman - 0: RLDRAM 78719880Swollman - 1: FCRAM */ 78818316Swollman#else 78918316Swollman uint64_t mode : 1; 79018316Swollman uint64_t reserved_1_63 : 63; 79118316Swollman#endif 79218316Swollman } s; 79318316Swollman struct cvmx_asxx_rld_fcram_mode_s cn38xx; 79418316Swollman struct cvmx_asxx_rld_fcram_mode_s cn38xxp2; 79518316Swollman}; 79618316Swollmantypedef union cvmx_asxx_rld_fcram_mode cvmx_asxx_rld_fcram_mode_t; 79719880Swollman 79819880Swollman/** 79919880Swollman * cvmx_asx#_rld_nctl_strong 80019880Swollman * 80119880Swollman * ASX_RLD_NCTL_STRONG 80219880Swollman * 80319880Swollman */ 80419880Swollmanunion cvmx_asxx_rld_nctl_strong 80518316Swollman{ 80618316Swollman uint64_t u64; 80718316Swollman struct cvmx_asxx_rld_nctl_strong_s 80818316Swollman { 80918316Swollman#if __BYTE_ORDER == __BIG_ENDIAN 81018316Swollman uint64_t reserved_5_63 : 59; 81119880Swollman uint64_t nctl : 5; /**< Duke's drive control */ 81218316Swollman#else 81318316Swollman uint64_t nctl : 5; 81418316Swollman uint64_t reserved_5_63 : 59; 81518316Swollman#endif 81618316Swollman } s; 81718316Swollman struct cvmx_asxx_rld_nctl_strong_s cn38xx; 81818316Swollman struct cvmx_asxx_rld_nctl_strong_s cn38xxp2; 81918316Swollman struct cvmx_asxx_rld_nctl_strong_s cn58xx; 82018316Swollman struct cvmx_asxx_rld_nctl_strong_s cn58xxp1; 82118316Swollman}; 82218316Swollmantypedef union cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_strong_t; 82318316Swollman 82418316Swollman/** 82518316Swollman * cvmx_asx#_rld_nctl_weak 82618316Swollman * 82718316Swollman * ASX_RLD_NCTL_WEAK 82818316Swollman * 82918316Swollman */ 83018316Swollmanunion cvmx_asxx_rld_nctl_weak 83118316Swollman{ 83218316Swollman uint64_t u64; 83318316Swollman struct cvmx_asxx_rld_nctl_weak_s 83418316Swollman { 83518316Swollman#if __BYTE_ORDER == __BIG_ENDIAN 83618316Swollman uint64_t reserved_5_63 : 59; 83718316Swollman uint64_t nctl : 5; /**< UNUSED (not needed for CN58XX) */ 83818316Swollman#else 83919880Swollman uint64_t nctl : 5; 84018316Swollman uint64_t reserved_5_63 : 59; 84118316Swollman#endif 84218316Swollman } s; 84318316Swollman struct cvmx_asxx_rld_nctl_weak_s cn38xx; 84419880Swollman struct cvmx_asxx_rld_nctl_weak_s cn38xxp2; 84519880Swollman struct cvmx_asxx_rld_nctl_weak_s cn58xx; 84618316Swollman struct cvmx_asxx_rld_nctl_weak_s cn58xxp1; 84719880Swollman}; 84818316Swollmantypedef union cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_nctl_weak_t; 84918316Swollman 85018316Swollman/** 85146303Smarkm * cvmx_asx#_rld_pctl_strong 85218316Swollman * 85318316Swollman * ASX_RLD_PCTL_STRONG 85419880Swollman * 85518316Swollman */ 85618316Swollmanunion cvmx_asxx_rld_pctl_strong 85718316Swollman{ 85818316Swollman uint64_t u64; 85919880Swollman struct cvmx_asxx_rld_pctl_strong_s 86018316Swollman { 86146303Smarkm#if __BYTE_ORDER == __BIG_ENDIAN 86218316Swollman uint64_t reserved_5_63 : 59; 86318316Swollman uint64_t pctl : 5; /**< Duke's drive control */ 86418316Swollman#else 86518316Swollman uint64_t pctl : 5; 86618316Swollman uint64_t reserved_5_63 : 59; 86718316Swollman#endif 86818316Swollman } s; 86918316Swollman struct cvmx_asxx_rld_pctl_strong_s cn38xx; 87018316Swollman struct cvmx_asxx_rld_pctl_strong_s cn38xxp2; 87118316Swollman struct cvmx_asxx_rld_pctl_strong_s cn58xx; 87219880Swollman struct cvmx_asxx_rld_pctl_strong_s cn58xxp1; 87318316Swollman}; 87418316Swollmantypedef union cvmx_asxx_rld_pctl_strong cvmx_asxx_rld_pctl_strong_t; 87518316Swollman 87619880Swollman/** 87719880Swollman * cvmx_asx#_rld_pctl_weak 87819880Swollman * 87919880Swollman * ASX_RLD_PCTL_WEAK 88018316Swollman * 88118316Swollman */ 88219880Swollmanunion cvmx_asxx_rld_pctl_weak 88318316Swollman{ 88418316Swollman uint64_t u64; 88518316Swollman struct cvmx_asxx_rld_pctl_weak_s 88618316Swollman { 88718316Swollman#if __BYTE_ORDER == __BIG_ENDIAN 88818316Swollman uint64_t reserved_5_63 : 59; 88918316Swollman uint64_t pctl : 5; /**< UNUSED (not needed for CN58XX) */ 89018316Swollman#else 89118316Swollman uint64_t pctl : 5; 89218316Swollman uint64_t reserved_5_63 : 59; 89318316Swollman#endif 89418316Swollman } s; 89518316Swollman struct cvmx_asxx_rld_pctl_weak_s cn38xx; 89618316Swollman struct cvmx_asxx_rld_pctl_weak_s cn38xxp2; 89718316Swollman struct cvmx_asxx_rld_pctl_weak_s cn58xx; 89818316Swollman struct cvmx_asxx_rld_pctl_weak_s cn58xxp1; 89918316Swollman}; 90018316Swollmantypedef union cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_pctl_weak_t; 90118316Swollman 90218316Swollman/** 90318316Swollman * cvmx_asx#_rld_setting 90418316Swollman * 90518316Swollman * ASX_RLD_SETTING 90618316Swollman * 90718316Swollman */ 90818316Swollmanunion cvmx_asxx_rld_setting 90946303Smarkm{ 91018316Swollman uint64_t u64; 91118316Swollman struct cvmx_asxx_rld_setting_s 91219880Swollman { 91319880Swollman#if __BYTE_ORDER == __BIG_ENDIAN 91419880Swollman uint64_t reserved_13_63 : 51; 91519880Swollman uint64_t dfaset : 5; /**< RLD ClkGen DLL Setting(debug) */ 91619880Swollman uint64_t dfalag : 1; /**< RLD ClkGen DLL Lag Error(debug) */ 91718316Swollman uint64_t dfalead : 1; /**< RLD ClkGen DLL Lead Error(debug) */ 91819880Swollman uint64_t dfalock : 1; /**< RLD ClkGen DLL Lock acquisition(debug) */ 91919880Swollman uint64_t setting : 5; /**< RLDCK90 DLL Setting(debug) */ 92018316Swollman#else 92118316Swollman uint64_t setting : 5; 92218316Swollman uint64_t dfalock : 1; 92346303Smarkm uint64_t dfalead : 1; 92418316Swollman uint64_t dfalag : 1; 92518316Swollman uint64_t dfaset : 5; 92619880Swollman uint64_t reserved_13_63 : 51; 92718316Swollman#endif 92818316Swollman } s; 92918316Swollman struct cvmx_asxx_rld_setting_cn38xx 93018316Swollman { 93146303Smarkm#if __BYTE_ORDER == __BIG_ENDIAN 93246303Smarkm uint64_t reserved_5_63 : 59; 93346303Smarkm uint64_t setting : 5; /**< This is the read-only true rld dll_setting. */ 93446303Smarkm#else 93546303Smarkm uint64_t setting : 5; 93646303Smarkm uint64_t reserved_5_63 : 59; 93746303Smarkm#endif 93846303Smarkm } cn38xx; 93946303Smarkm struct cvmx_asxx_rld_setting_cn38xx cn38xxp2; 94046303Smarkm struct cvmx_asxx_rld_setting_s cn58xx; 94118316Swollman struct cvmx_asxx_rld_setting_s cn58xxp1; 94218316Swollman}; 94318316Swollmantypedef union cvmx_asxx_rld_setting cvmx_asxx_rld_setting_t; 94446303Smarkm 94546303Smarkm/** 94646303Smarkm * cvmx_asx#_rx_clk_set# 94718316Swollman * 94818316Swollman * ASX_RX_CLK_SET = RGMII Clock delay setting 94946303Smarkm * 95046303Smarkm * 95118316Swollman * Notes: 95218316Swollman * Setting to place on the open-loop RXC (RGMII receive clk) 95318316Swollman * delay line, which can delay the recieved clock. This 95418316Swollman * can be used if the board and/or transmitting device 95518316Swollman * has not otherwise delayed the clock. 95618316Swollman * 95718316Swollman * A value of SETTING=0 disables the delay line. The delay 95818316Swollman * line should be disabled unless the transmitter or board 95918316Swollman * does not delay the clock. 96018316Swollman * 96119880Swollman * Note that this delay line provides only a coarse control 96218316Swollman * over the delay. Generally, it can only reliably provide 96318316Swollman * a delay in the range 1.25-2.5ns, which may not be adequate 96418316Swollman * for some system applications. 96519880Swollman * 96619880Swollman * The open loop delay line selects 96719880Swollman * from among a series of tap positions. Each incremental 96819880Swollman * tap position adds a delay of 50ps to 135ps per tap, depending 96918316Swollman * on the chip, its temperature, and the voltage. 97018316Swollman * To achieve from 1.25-2.5ns of delay on the recieved 97119880Swollman * clock, a fixed value of SETTING=24 may work. 97218316Swollman * For more precision, we recommend the following settings 97318316Swollman * based on the chip voltage: 97418316Swollman * 97518316Swollman * VDD SETTING 976 * ----------------------------- 977 * 1.0 18 978 * 1.05 19 979 * 1.1 21 980 * 1.15 22 981 * 1.2 23 982 * 1.25 24 983 * 1.3 25 984 */ 985union cvmx_asxx_rx_clk_setx 986{ 987 uint64_t u64; 988 struct cvmx_asxx_rx_clk_setx_s 989 { 990#if __BYTE_ORDER == __BIG_ENDIAN 991 uint64_t reserved_5_63 : 59; 992 uint64_t setting : 5; /**< Setting to place on the open-loop RXC delay line */ 993#else 994 uint64_t setting : 5; 995 uint64_t reserved_5_63 : 59; 996#endif 997 } s; 998 struct cvmx_asxx_rx_clk_setx_s cn30xx; 999 struct cvmx_asxx_rx_clk_setx_s cn31xx; 1000 struct cvmx_asxx_rx_clk_setx_s cn38xx; 1001 struct cvmx_asxx_rx_clk_setx_s cn38xxp2; 1002 struct cvmx_asxx_rx_clk_setx_s cn50xx; 1003 struct cvmx_asxx_rx_clk_setx_s cn58xx; 1004 struct cvmx_asxx_rx_clk_setx_s cn58xxp1; 1005}; 1006typedef union cvmx_asxx_rx_clk_setx cvmx_asxx_rx_clk_setx_t; 1007 1008/** 1009 * cvmx_asx#_rx_prt_en 1010 * 1011 * ASX_RX_PRT_EN = RGMII Port Enable 1012 * 1013 */ 1014union cvmx_asxx_rx_prt_en 1015{ 1016 uint64_t u64; 1017 struct cvmx_asxx_rx_prt_en_s 1018 { 1019#if __BYTE_ORDER == __BIG_ENDIAN 1020 uint64_t reserved_4_63 : 60; 1021 uint64_t prt_en : 4; /**< Port enable. Must be set for Octane to receive 1022 RMGII traffic. When this bit clear on a given 1023 port, then the all RGMII cycles will appear as 1024 inter-frame cycles. */ 1025#else 1026 uint64_t prt_en : 4; 1027 uint64_t reserved_4_63 : 60; 1028#endif 1029 } s; 1030 struct cvmx_asxx_rx_prt_en_cn30xx 1031 { 1032#if __BYTE_ORDER == __BIG_ENDIAN 1033 uint64_t reserved_3_63 : 61; 1034 uint64_t prt_en : 3; /**< Port enable. Must be set for Octane to receive 1035 RMGII traffic. When this bit clear on a given 1036 port, then the all RGMII cycles will appear as 1037 inter-frame cycles. */ 1038#else 1039 uint64_t prt_en : 3; 1040 uint64_t reserved_3_63 : 61; 1041#endif 1042 } cn30xx; 1043 struct cvmx_asxx_rx_prt_en_cn30xx cn31xx; 1044 struct cvmx_asxx_rx_prt_en_s cn38xx; 1045 struct cvmx_asxx_rx_prt_en_s cn38xxp2; 1046 struct cvmx_asxx_rx_prt_en_cn30xx cn50xx; 1047 struct cvmx_asxx_rx_prt_en_s cn58xx; 1048 struct cvmx_asxx_rx_prt_en_s cn58xxp1; 1049}; 1050typedef union cvmx_asxx_rx_prt_en cvmx_asxx_rx_prt_en_t; 1051 1052/** 1053 * cvmx_asx#_rx_wol 1054 * 1055 * ASX_RX_WOL = RGMII RX Wake on LAN status register 1056 * 1057 */ 1058union cvmx_asxx_rx_wol 1059{ 1060 uint64_t u64; 1061 struct cvmx_asxx_rx_wol_s 1062 { 1063#if __BYTE_ORDER == __BIG_ENDIAN 1064 uint64_t reserved_2_63 : 62; 1065 uint64_t status : 1; /**< Copy of PMCSR[15] - PME_status */ 1066 uint64_t enable : 1; /**< Copy of PMCSR[8] - PME_enable */ 1067#else 1068 uint64_t enable : 1; 1069 uint64_t status : 1; 1070 uint64_t reserved_2_63 : 62; 1071#endif 1072 } s; 1073 struct cvmx_asxx_rx_wol_s cn38xx; 1074 struct cvmx_asxx_rx_wol_s cn38xxp2; 1075}; 1076typedef union cvmx_asxx_rx_wol cvmx_asxx_rx_wol_t; 1077 1078/** 1079 * cvmx_asx#_rx_wol_msk 1080 * 1081 * ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask 1082 * 1083 */ 1084union cvmx_asxx_rx_wol_msk 1085{ 1086 uint64_t u64; 1087 struct cvmx_asxx_rx_wol_msk_s 1088 { 1089#if __BYTE_ORDER == __BIG_ENDIAN 1090 uint64_t msk : 64; /**< Bytes to include in the CRC signature */ 1091#else 1092 uint64_t msk : 64; 1093#endif 1094 } s; 1095 struct cvmx_asxx_rx_wol_msk_s cn38xx; 1096 struct cvmx_asxx_rx_wol_msk_s cn38xxp2; 1097}; 1098typedef union cvmx_asxx_rx_wol_msk cvmx_asxx_rx_wol_msk_t; 1099 1100/** 1101 * cvmx_asx#_rx_wol_powok 1102 * 1103 * ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK 1104 * 1105 */ 1106union cvmx_asxx_rx_wol_powok 1107{ 1108 uint64_t u64; 1109 struct cvmx_asxx_rx_wol_powok_s 1110 { 1111#if __BYTE_ORDER == __BIG_ENDIAN 1112 uint64_t reserved_1_63 : 63; 1113 uint64_t powerok : 1; /**< Power OK */ 1114#else 1115 uint64_t powerok : 1; 1116 uint64_t reserved_1_63 : 63; 1117#endif 1118 } s; 1119 struct cvmx_asxx_rx_wol_powok_s cn38xx; 1120 struct cvmx_asxx_rx_wol_powok_s cn38xxp2; 1121}; 1122typedef union cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_powok_t; 1123 1124/** 1125 * cvmx_asx#_rx_wol_sig 1126 * 1127 * ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature 1128 * 1129 */ 1130union cvmx_asxx_rx_wol_sig 1131{ 1132 uint64_t u64; 1133 struct cvmx_asxx_rx_wol_sig_s 1134 { 1135#if __BYTE_ORDER == __BIG_ENDIAN 1136 uint64_t reserved_32_63 : 32; 1137 uint64_t sig : 32; /**< CRC signature */ 1138#else 1139 uint64_t sig : 32; 1140 uint64_t reserved_32_63 : 32; 1141#endif 1142 } s; 1143 struct cvmx_asxx_rx_wol_sig_s cn38xx; 1144 struct cvmx_asxx_rx_wol_sig_s cn38xxp2; 1145}; 1146typedef union cvmx_asxx_rx_wol_sig cvmx_asxx_rx_wol_sig_t; 1147 1148/** 1149 * cvmx_asx#_tx_clk_set# 1150 * 1151 * ASX_TX_CLK_SET = RGMII Clock delay setting 1152 * 1153 * 1154 * Notes: 1155 * Setting to place on the open-loop TXC (RGMII transmit clk) 1156 * delay line, which can delay the transmited clock. This 1157 * can be used if the board and/or transmitting device 1158 * has not otherwise delayed the clock. 1159 * 1160 * A value of SETTING=0 disables the delay line. The delay 1161 * line should be disabled unless the transmitter or board 1162 * does not delay the clock. 1163 * 1164 * Note that this delay line provides only a coarse control 1165 * over the delay. Generally, it can only reliably provide 1166 * a delay in the range 1.25-2.5ns, which may not be adequate 1167 * for some system applications. 1168 * 1169 * The open loop delay line selects 1170 * from among a series of tap positions. Each incremental 1171 * tap position adds a delay of 50ps to 135ps per tap, depending 1172 * on the chip, its temperature, and the voltage. 1173 * To achieve from 1.25-2.5ns of delay on the recieved 1174 * clock, a fixed value of SETTING=24 may work. 1175 * For more precision, we recommend the following settings 1176 * based on the chip voltage: 1177 * 1178 * VDD SETTING 1179 * ----------------------------- 1180 * 1.0 18 1181 * 1.05 19 1182 * 1.1 21 1183 * 1.15 22 1184 * 1.2 23 1185 * 1.25 24 1186 * 1.3 25 1187 */ 1188union cvmx_asxx_tx_clk_setx 1189{ 1190 uint64_t u64; 1191 struct cvmx_asxx_tx_clk_setx_s 1192 { 1193#if __BYTE_ORDER == __BIG_ENDIAN 1194 uint64_t reserved_5_63 : 59; 1195 uint64_t setting : 5; /**< Setting to place on the open-loop TXC delay line */ 1196#else 1197 uint64_t setting : 5; 1198 uint64_t reserved_5_63 : 59; 1199#endif 1200 } s; 1201 struct cvmx_asxx_tx_clk_setx_s cn30xx; 1202 struct cvmx_asxx_tx_clk_setx_s cn31xx; 1203 struct cvmx_asxx_tx_clk_setx_s cn38xx; 1204 struct cvmx_asxx_tx_clk_setx_s cn38xxp2; 1205 struct cvmx_asxx_tx_clk_setx_s cn50xx; 1206 struct cvmx_asxx_tx_clk_setx_s cn58xx; 1207 struct cvmx_asxx_tx_clk_setx_s cn58xxp1; 1208}; 1209typedef union cvmx_asxx_tx_clk_setx cvmx_asxx_tx_clk_setx_t; 1210 1211/** 1212 * cvmx_asx#_tx_comp_byp 1213 * 1214 * ASX_TX_COMP_BYP = RGMII Clock delay setting 1215 * 1216 */ 1217union cvmx_asxx_tx_comp_byp 1218{ 1219 uint64_t u64; 1220 struct cvmx_asxx_tx_comp_byp_s 1221 { 1222#if __BYTE_ORDER == __BIG_ENDIAN 1223 uint64_t reserved_0_63 : 64; 1224#else 1225 uint64_t reserved_0_63 : 64; 1226#endif 1227 } s; 1228 struct cvmx_asxx_tx_comp_byp_cn30xx 1229 { 1230#if __BYTE_ORDER == __BIG_ENDIAN 1231 uint64_t reserved_9_63 : 55; 1232 uint64_t bypass : 1; /**< Compensation bypass */ 1233 uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */ 1234 uint64_t nctl : 4; /**< NCTL Compensation Value (see Duke) */ 1235#else 1236 uint64_t nctl : 4; 1237 uint64_t pctl : 4; 1238 uint64_t bypass : 1; 1239 uint64_t reserved_9_63 : 55; 1240#endif 1241 } cn30xx; 1242 struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx; 1243 struct cvmx_asxx_tx_comp_byp_cn38xx 1244 { 1245#if __BYTE_ORDER == __BIG_ENDIAN 1246 uint64_t reserved_8_63 : 56; 1247 uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */ 1248 uint64_t nctl : 4; /**< NCTL Compensation Value (see Duke) */ 1249#else 1250 uint64_t nctl : 4; 1251 uint64_t pctl : 4; 1252 uint64_t reserved_8_63 : 56; 1253#endif 1254 } cn38xx; 1255 struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2; 1256 struct cvmx_asxx_tx_comp_byp_cn50xx 1257 { 1258#if __BYTE_ORDER == __BIG_ENDIAN 1259 uint64_t reserved_17_63 : 47; 1260 uint64_t bypass : 1; /**< Compensation bypass */ 1261 uint64_t reserved_13_15 : 3; 1262 uint64_t pctl : 5; /**< PCTL Compensation Value (see Duke) */ 1263 uint64_t reserved_5_7 : 3; 1264 uint64_t nctl : 5; /**< NCTL Compensation Value (see Duke) */ 1265#else 1266 uint64_t nctl : 5; 1267 uint64_t reserved_5_7 : 3; 1268 uint64_t pctl : 5; 1269 uint64_t reserved_13_15 : 3; 1270 uint64_t bypass : 1; 1271 uint64_t reserved_17_63 : 47; 1272#endif 1273 } cn50xx; 1274 struct cvmx_asxx_tx_comp_byp_cn58xx 1275 { 1276#if __BYTE_ORDER == __BIG_ENDIAN 1277 uint64_t reserved_13_63 : 51; 1278 uint64_t pctl : 5; /**< PCTL Compensation Value (see Duke) */ 1279 uint64_t reserved_5_7 : 3; 1280 uint64_t nctl : 5; /**< NCTL Compensation Value (see Duke) */ 1281#else 1282 uint64_t nctl : 5; 1283 uint64_t reserved_5_7 : 3; 1284 uint64_t pctl : 5; 1285 uint64_t reserved_13_63 : 51; 1286#endif 1287 } cn58xx; 1288 struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1; 1289}; 1290typedef union cvmx_asxx_tx_comp_byp cvmx_asxx_tx_comp_byp_t; 1291 1292/** 1293 * cvmx_asx#_tx_hi_water# 1294 * 1295 * ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark 1296 * 1297 */ 1298union cvmx_asxx_tx_hi_waterx 1299{ 1300 uint64_t u64; 1301 struct cvmx_asxx_tx_hi_waterx_s 1302 { 1303#if __BYTE_ORDER == __BIG_ENDIAN 1304 uint64_t reserved_4_63 : 60; 1305 uint64_t mark : 4; /**< TX FIFO HiWatermark to stall GMX 1306 Value of 0 maps to 16 1307 Reset value changed from 10 in pass1 1308 Pass1 settings (assuming 125 tclk) 1309 - 325-375: 12 1310 - 375-437: 11 1311 - 437-550: 10 1312 - 550-687: 9 */ 1313#else 1314 uint64_t mark : 4; 1315 uint64_t reserved_4_63 : 60; 1316#endif 1317 } s; 1318 struct cvmx_asxx_tx_hi_waterx_cn30xx 1319 { 1320#if __BYTE_ORDER == __BIG_ENDIAN 1321 uint64_t reserved_3_63 : 61; 1322 uint64_t mark : 3; /**< TX FIFO HiWatermark to stall GMX 1323 Value 0 maps to 8. */ 1324#else 1325 uint64_t mark : 3; 1326 uint64_t reserved_3_63 : 61; 1327#endif 1328 } cn30xx; 1329 struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx; 1330 struct cvmx_asxx_tx_hi_waterx_s cn38xx; 1331 struct cvmx_asxx_tx_hi_waterx_s cn38xxp2; 1332 struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx; 1333 struct cvmx_asxx_tx_hi_waterx_s cn58xx; 1334 struct cvmx_asxx_tx_hi_waterx_s cn58xxp1; 1335}; 1336typedef union cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_hi_waterx_t; 1337 1338/** 1339 * cvmx_asx#_tx_prt_en 1340 * 1341 * ASX_TX_PRT_EN = RGMII Port Enable 1342 * 1343 */ 1344union cvmx_asxx_tx_prt_en 1345{ 1346 uint64_t u64; 1347 struct cvmx_asxx_tx_prt_en_s 1348 { 1349#if __BYTE_ORDER == __BIG_ENDIAN 1350 uint64_t reserved_4_63 : 60; 1351 uint64_t prt_en : 4; /**< Port enable. Must be set for Octane to send 1352 RMGII traffic. When this bit clear on a given 1353 port, then all RGMII cycles will appear as 1354 inter-frame cycles. */ 1355#else 1356 uint64_t prt_en : 4; 1357 uint64_t reserved_4_63 : 60; 1358#endif 1359 } s; 1360 struct cvmx_asxx_tx_prt_en_cn30xx 1361 { 1362#if __BYTE_ORDER == __BIG_ENDIAN 1363 uint64_t reserved_3_63 : 61; 1364 uint64_t prt_en : 3; /**< Port enable. Must be set for Octane to send 1365 RMGII traffic. When this bit clear on a given 1366 port, then all RGMII cycles will appear as 1367 inter-frame cycles. */ 1368#else 1369 uint64_t prt_en : 3; 1370 uint64_t reserved_3_63 : 61; 1371#endif 1372 } cn30xx; 1373 struct cvmx_asxx_tx_prt_en_cn30xx cn31xx; 1374 struct cvmx_asxx_tx_prt_en_s cn38xx; 1375 struct cvmx_asxx_tx_prt_en_s cn38xxp2; 1376 struct cvmx_asxx_tx_prt_en_cn30xx cn50xx; 1377 struct cvmx_asxx_tx_prt_en_s cn58xx; 1378 struct cvmx_asxx_tx_prt_en_s cn58xxp1; 1379}; 1380typedef union cvmx_asxx_tx_prt_en cvmx_asxx_tx_prt_en_t; 1381 1382#endif 1383