1/*- 2 * Copyright (c) 2007 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#include <machine/asm.h> 30 31 .text 32 33/* 34 * uint32_t atomic_cas_32(volatile uint32_t *p, uint32_t cmp, uint32_t v) 35 */ 36ENTRY(atomic_cas_32, 3) 37 mov ar.ccv = r33 38 ;; 39 cmpxchg4.acq r8 = [r32], r34, ar.ccv 40 ;; 41 br.ret.sptk rp 42END(atomic_cas_32) 43 44/* 45 * uint64_t atomic_cas_64(volatile uint64_t *p, uint64_t cmp, uint64_t v) 46 */ 47ENTRY(atomic_cas_64, 3) 48 mov ar.ccv = r33 49 ;; 50 cmpxchg8.acq r8 = [r32], r34, ar.ccv 51 ;; 52 br.ret.sptk rp 53END(atomic_cas_64) 54 55/* 56 * uint64_t atomic_add_64_nv(volatile uint64_t *p, uint64_t v) 57 */ 58ENTRY(atomic_add_64_nv, 2) 591: 60 ld8 r16 = [r32] 61 ;; 62 mov ar.ccv = r16 63 add r8 = r16, r33 64 ;; 65 cmpxchg8.acq r17 = [r32], r8, ar.ccv 66 ;; 67 cmp.eq p6, p7 = r16, r17 68(p6) br.ret.sptk rp 69(p7) br.cond.spnt 1b 70END(atomic_add_64_nv) 71 72/* 73 * uint8_t atomic_or_8_nv(volatile uint8_t *p, uint8_t v) 74 */ 75ENTRY(atomic_or_8_nv, 2) 761: 77 ld8 r16 = [r32] 78 ;; 79 mov ar.ccv = r16 80 or r8 = r16, r33 81 ;; 82 cmpxchg1.acq r17 = [r32], r8, ar.ccv 83 ;; 84 cmp.eq p6, p7 = r16, r17 85(p6) br.ret.sptk rp 86(p7) br.cond.spnt 1b 87END(atomic_or_8_nv) 88 89ENTRY(membar_producer, 0) 90 mf 91 ;; 92 br.ret.sptk rp 93END(membar_producer) 94