1161370Simp/*- 2161370Simp * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3161370Simp * 4161370Simp * Redistribution and use in source and binary forms, with or without 5161370Simp * modification, are permitted provided that the following conditions 6161370Simp * are met: 7161370Simp * 1. Redistributions of source code must retain the above copyright 8161370Simp * notice, this list of conditions and the following disclaimer. 9161370Simp * 2. Redistributions in binary form must reproduce the above copyright 10161370Simp * notice, this list of conditions and the following disclaimer in the 11161370Simp * documentation and/or other materials provided with the distribution. 12161370Simp * 13161370Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14161370Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15161370Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16161370Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17161370Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18161370Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19161370Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20161370Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21161370Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22161370Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23161370Simp * 24161370Simp * This software is derived from software provide by Kwikbyte who specifically 25161370Simp * disclaimed copyright on the code. 26161370Simp * 27161370Simp * $FreeBSD$ 28161370Simp */ 29161370Simp 30161370Simp#ifndef __LIBAT91RM9200_H 31161370Simp#define __LIBAT91RM9200_H 32161370Simp 33161370Simp#include "at91rm9200.h" 34161370Simp 35161370Simp//*---------------------------------------------------------------------------- 36161370Simp//* \fn AT91F_PMC_EnablePeriphClock 37161370Simp//* \brief Enable peripheral clock 38161370Simp//*---------------------------------------------------------------------------- 39161370Simpstatic inline void 40161370SimpAT91F_PMC_EnablePeriphClock ( 41163533Simp AT91PS_PMC pPMC, // \arg pointer to PMC controller 42163533Simp unsigned int periphIds) // \arg IDs of peripherals to enable 43161370Simp{ 44163533Simp pPMC->PMC_PCER = periphIds; 45161370Simp} 46161370Simp 47161370Simp/* ***************************************************************************** 48161370Simp SOFTWARE API FOR PIO 49161370Simp ***************************************************************************** */ 50161370Simp//*---------------------------------------------------------------------------- 51161370Simp//* \fn AT91F_PIO_CfgPeriph 52161370Simp//* \brief Enable pins to be drived by peripheral 53161370Simp//*---------------------------------------------------------------------------- 54161370Simpstatic inline 55161370Simpvoid AT91F_PIO_CfgPeriph( 56161370Simp AT91PS_PIO pPio, // \arg pointer to a PIO controller 57161370Simp unsigned int periphAEnable, // \arg PERIPH A to enable 58161370Simp unsigned int periphBEnable) // \arg PERIPH B to enable 59161370Simp 60161370Simp{ 61163533Simp if (periphAEnable) 62163533Simp pPio->PIO_ASR = periphAEnable; 63163533Simp if (periphBEnable) 64163533Simp pPio->PIO_BSR = periphBEnable; 65161370Simp pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode 66161370Simp} 67161370Simp 68161370Simp/* ***************************************************************************** 69161370Simp SOFTWARE API FOR MCI 70161370Simp ***************************************************************************** */ 71161370Simp//* Classic MCI Data Timeout Register Configuration with 1048576 MCK cycles between 2 data transfer 72161370Simp#define AT91C_MCI_DTOR_1MEGA_CYCLES (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL) 73161370Simp 74161370Simp//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot A 75161370Simp#define AT91C_MCI_MMC_SLOTA (AT91C_MCI_SCDSEL & 0x0) 76161370Simp 77161370Simp//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot B 78161370Simp#define AT91C_MCI_MMC_SLOTB (AT91C_MCI_SCDSEL) 79161370Simp 80161370Simp//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot A 81161370Simp#define AT91C_MCI_SDCARD_4BITS_SLOTA ( (AT91C_MCI_SCDSEL & 0x0) | AT91C_MCI_SCDBUS ) 82161370Simp 83161370Simp//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot B 84161370Simp#define AT91C_MCI_SDCARD_4BITS_SLOTB (AT91C_MCI_SCDSEL | AT91C_MCI_SCDBUS) 85161370Simp 86161370Simp 87161370Simp 88161370Simp//*---------------------------------------------------------------------------- 89161370Simp//* \fn AT91F_MCI_Configure 90161370Simp//* \brief Configure the MCI 91161370Simp//*---------------------------------------------------------------------------- 92161370Simpstatic inline 93161370Simpvoid AT91F_MCI_Configure( 94161370Simp AT91PS_MCI pMCI, // \arg pointer to a MCI controller 95161370Simp unsigned int DTOR_register, // \arg Data Timeout Register to be programmed 96161370Simp unsigned int MR_register, // \arg Mode Register to be programmed 97161370Simp unsigned int SDCR_register) // \arg SDCard Register to be programmed 98161370Simp{ 99161370Simp //* Reset the MCI 100161370Simp pMCI->MCI_CR = AT91C_MCI_MCIEN | AT91C_MCI_PWSEN; 101161370Simp 102161370Simp //* Disable all the interrupts 103161370Simp pMCI->MCI_IDR = 0xFFFFFFFF; 104161370Simp 105161370Simp //* Set the Data Timeout Register 106161370Simp pMCI->MCI_DTOR = DTOR_register; 107161370Simp 108161370Simp //* Set the Mode Register 109161370Simp pMCI->MCI_MR = MR_register; 110161370Simp 111161370Simp //* Set the SDCard Register 112161370Simp pMCI->MCI_SDCR = SDCR_register; 113161370Simp} 114161370Simp 115161370Simp//*---------------------------------------------------------------------------- 116161370Simp//* \fn AT91F_MCI_CfgPMC 117161370Simp//* \brief Enable Peripheral clock in PMC for MCI 118161370Simp//*---------------------------------------------------------------------------- 119161370Simpstatic inline void 120161370SimpAT91F_MCI_CfgPMC(void) 121161370Simp{ 122161370Simp AT91F_PMC_EnablePeriphClock( 123161370Simp AT91C_BASE_PMC, // PIO controller base address 124161370Simp ((unsigned int) 1 << AT91C_ID_MCI)); 125161370Simp} 126161370Simp 127161370Simp//*---------------------------------------------------------------------------- 128161370Simp//* \fn AT91F_MCI_CfgPIO 129161370Simp//* \brief Configure PIO controllers to drive MCI signals 130161370Simp//*---------------------------------------------------------------------------- 131161370Simpstatic inline void 132161370SimpAT91F_MCI_CfgPIO(void) 133161370Simp{ 134161370Simp // Configure PIO controllers to periph mode 135161370Simp AT91F_PIO_CfgPeriph( 136161370Simp AT91C_BASE_PIOA, // PIO controller base address 137238463Simp ((unsigned int) AT91C_PIO_PA28 ) | 138238463Simp ((unsigned int) AT91C_PIO_PA29 ) | 139238463Simp ((unsigned int) AT91C_PIO_PA27 ), // Peripheral A 140161370Simp 0); // Peripheral B 141161370Simp // Configure PIO controllers to periph mode 142161370Simp AT91F_PIO_CfgPeriph( 143161370Simp AT91C_BASE_PIOB, // PIO controller base address 144161370Simp 0, // Peripheral A 145238463Simp ((unsigned int) AT91C_PIO_PB5 ) | 146238463Simp ((unsigned int) AT91C_PIO_PB3 ) | 147238463Simp ((unsigned int) AT91C_PIO_PB4 )); // Peripheral B 148161370Simp} 149161370Simp 150161370Simp 151161370Simp/* ***************************************************************************** 152161370Simp SOFTWARE API FOR PDC 153161370Simp ***************************************************************************** */ 154161370Simp//*---------------------------------------------------------------------------- 155161370Simp//* \fn AT91F_PDC_SetNextRx 156161370Simp//* \brief Set the next receive transfer descriptor 157161370Simp//*---------------------------------------------------------------------------- 158161370Simpstatic inline void 159161370SimpAT91F_PDC_SetNextRx ( 160161370Simp AT91PS_PDC pPDC, // \arg pointer to a PDC controller 161161370Simp char *address, // \arg address to the next bloc to be received 162161370Simp unsigned int bytes) // \arg number of bytes to be received 163161370Simp{ 164161370Simp pPDC->PDC_RNPR = (unsigned int) address; 165161370Simp pPDC->PDC_RNCR = bytes; 166161370Simp} 167161370Simp 168161370Simp//*---------------------------------------------------------------------------- 169161370Simp//* \fn AT91F_PDC_SetNextTx 170161370Simp//* \brief Set the next transmit transfer descriptor 171161370Simp//*---------------------------------------------------------------------------- 172161370Simpstatic inline void 173161370SimpAT91F_PDC_SetNextTx( 174161370Simp AT91PS_PDC pPDC, // \arg pointer to a PDC controller 175161370Simp char *address, // \arg address to the next bloc to be transmitted 176161370Simp unsigned int bytes) // \arg number of bytes to be transmitted 177161370Simp{ 178161370Simp pPDC->PDC_TNPR = (unsigned int) address; 179161370Simp pPDC->PDC_TNCR = bytes; 180161370Simp} 181161370Simp 182161370Simp//*---------------------------------------------------------------------------- 183161370Simp//* \fn AT91F_PDC_SetRx 184161370Simp//* \brief Set the receive transfer descriptor 185161370Simp//*---------------------------------------------------------------------------- 186161370Simpstatic inline void 187161370SimpAT91F_PDC_SetRx( 188161370Simp AT91PS_PDC pPDC, // \arg pointer to a PDC controller 189161370Simp char *address, // \arg address to the next bloc to be received 190161370Simp unsigned int bytes) // \arg number of bytes to be received 191161370Simp{ 192161370Simp pPDC->PDC_RPR = (unsigned int) address; 193161370Simp pPDC->PDC_RCR = bytes; 194161370Simp} 195161370Simp 196161370Simp//*---------------------------------------------------------------------------- 197161370Simp//* \fn AT91F_PDC_SetTx 198161370Simp//* \brief Set the transmit transfer descriptor 199161370Simp//*---------------------------------------------------------------------------- 200161370Simpstatic inline void 201161370SimpAT91F_PDC_SetTx( 202161370Simp AT91PS_PDC pPDC, // \arg pointer to a PDC controller 203161370Simp char *address, // \arg address to the next bloc to be transmitted 204161370Simp unsigned int bytes) // \arg number of bytes to be transmitted 205161370Simp{ 206161370Simp pPDC->PDC_TPR = (unsigned int) address; 207161370Simp pPDC->PDC_TCR = bytes; 208161370Simp} 209161370Simp 210161370Simp//*---------------------------------------------------------------------------- 211161370Simp//* \fn AT91F_PDC_EnableTx 212161370Simp//* \brief Enable transmit 213161370Simp//*---------------------------------------------------------------------------- 214161370Simpstatic inline void 215161370SimpAT91F_PDC_EnableTx( 216161370Simp AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 217161370Simp{ 218161370Simp pPDC->PDC_PTCR = AT91C_PDC_TXTEN; 219161370Simp} 220161370Simp 221161370Simp//*---------------------------------------------------------------------------- 222161370Simp//* \fn AT91F_PDC_EnableRx 223161370Simp//* \brief Enable receive 224161370Simp//*---------------------------------------------------------------------------- 225161370Simpstatic inline void 226161370SimpAT91F_PDC_EnableRx( 227161370Simp AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 228161370Simp{ 229161370Simp pPDC->PDC_PTCR = AT91C_PDC_RXTEN; 230161370Simp} 231161370Simp 232161370Simp//*---------------------------------------------------------------------------- 233161370Simp//* \fn AT91F_PDC_DisableTx 234161370Simp//* \brief Disable transmit 235161370Simp//*---------------------------------------------------------------------------- 236161370Simpstatic inline void 237161370SimpAT91F_PDC_DisableTx( 238161370Simp AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 239161370Simp{ 240161370Simp pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; 241161370Simp} 242161370Simp 243161370Simp//*---------------------------------------------------------------------------- 244161370Simp//* \fn AT91F_PDC_DisableRx 245161370Simp//* \brief Disable receive 246161370Simp//*---------------------------------------------------------------------------- 247161370Simpstatic inline void 248161370SimpAT91F_PDC_DisableRx( 249161370Simp AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 250161370Simp{ 251161370Simp pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; 252161370Simp} 253161370Simp 254161370Simp//*---------------------------------------------------------------------------- 255161370Simp//* \fn AT91F_PDC_Open 256161370Simp//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX 257161370Simp//*---------------------------------------------------------------------------- 258161370Simpstatic inline void 259161370SimpAT91F_PDC_Open( 260161370Simp AT91PS_PDC pPDC) // \arg pointer to a PDC controller 261161370Simp{ 262161370Simp //* Disable the RX and TX PDC transfer requests 263161370Simp AT91F_PDC_DisableRx(pPDC); 264161370Simp AT91F_PDC_DisableTx(pPDC); 265161370Simp 266161370Simp //* Reset all Counter register Next buffer first 267161370Simp AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); 268161370Simp AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); 269161370Simp AT91F_PDC_SetTx(pPDC, (char *) 0, 0); 270161370Simp AT91F_PDC_SetRx(pPDC, (char *) 0, 0); 271161370Simp 272161370Simp //* Enable the RX and TX PDC transfer requests 273161370Simp AT91F_PDC_EnableRx(pPDC); 274161370Simp AT91F_PDC_EnableTx(pPDC); 275161370Simp} 276161370Simp 277161370Simp#endif 278