1/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */ 2 3/*- 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * machdep.c 40 * 41 * Machine dependant functions for kernel setup 42 * 43 * This file needs a lot of work. 44 * 45 * Created : 17/09/94 46 */ 47 48#include "opt_ddb.h" 49 50#include <sys/cdefs.h> 51__FBSDID("$FreeBSD$"); 52 53#define _ARM32_BUS_DMA_PRIVATE 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/sysproto.h> 57#include <sys/signalvar.h> 58#include <sys/imgact.h> 59#include <sys/kernel.h> 60#include <sys/ktr.h> 61#include <sys/linker.h> 62#include <sys/lock.h> 63#include <sys/malloc.h> 64#include <sys/mutex.h> 65#include <sys/pcpu.h> 66#include <sys/proc.h> 67#include <sys/ptrace.h> 68#include <sys/cons.h> 69#include <sys/bio.h> 70#include <sys/bus.h> 71#include <sys/buf.h> 72#include <sys/exec.h> 73#include <sys/kdb.h> 74#include <sys/msgbuf.h> 75#include <machine/reg.h> 76#include <machine/cpu.h> 77 78#include <vm/vm.h> 79#include <vm/pmap.h> 80#include <vm/vm_object.h> 81#include <vm/vm_page.h> 82#include <vm/vm_map.h> 83#include <machine/devmap.h> 84#include <machine/vmparam.h> 85#include <machine/pcb.h> 86#include <machine/undefined.h> 87#include <machine/machdep.h> 88#include <machine/metadata.h> 89#include <machine/armreg.h> 90#include <machine/bus.h> 91#include <machine/physmem.h> 92#include <sys/reboot.h> 93 94#include <arm/xscale/pxa/pxareg.h> 95#include <arm/xscale/pxa/pxavar.h> 96 97#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ 98#define KERNEL_PT_IOPXS 1 99#define KERNEL_PT_BEFOREKERN 2 100#define KERNEL_PT_AFKERNEL 3 /* L2 table for mapping after kernel */ 101#define KERNEL_PT_AFKERNEL_NUM 9 102 103/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ 104#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) 105 106struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; 107 108/* Physical and virtual addresses for some global pages */ 109 110struct pv_addr systempage; 111struct pv_addr msgbufpv; 112struct pv_addr irqstack; 113struct pv_addr undstack; 114struct pv_addr abtstack; 115struct pv_addr kernelstack; 116struct pv_addr minidataclean; 117 118static void pxa_probe_sdram(bus_space_tag_t, bus_space_handle_t, 119 uint32_t *, uint32_t *); 120 121/* Static device mappings. */ 122static const struct arm_devmap_entry pxa_devmap[] = { 123 /* 124 * Map the on-board devices up into the KVA region so we don't muck 125 * up user-space. 126 */ 127 { 128 PXA2X0_PERIPH_START + PXA2X0_PERIPH_OFFSET, 129 PXA2X0_PERIPH_START, 130 PXA250_PERIPH_END - PXA2X0_PERIPH_START, 131 VM_PROT_READ|VM_PROT_WRITE, 132 PTE_DEVICE, 133 }, 134 { 0, 0, 0, 0, 0, } 135}; 136 137#define SDRAM_START 0xa0000000 138 139extern vm_offset_t xscale_cache_clean_addr; 140 141void * 142initarm(struct arm_boot_params *abp) 143{ 144 struct pv_addr kernel_l1pt; 145 struct pv_addr dpcpu; 146 int loop; 147 u_int l1pagetable; 148 vm_offset_t freemempos; 149 vm_offset_t freemem_pt; 150 vm_offset_t afterkern; 151 vm_offset_t freemem_after; 152 vm_offset_t lastaddr; 153 int i, j; 154 uint32_t memsize[PXA2X0_SDRAM_BANKS], memstart[PXA2X0_SDRAM_BANKS]; 155 156 lastaddr = parse_boot_param(abp); 157 arm_physmem_kernaddr = abp->abp_physaddr; 158 set_cpufuncs(); 159 pcpu_init(pcpup, 0, sizeof(struct pcpu)); 160 PCPU_SET(curthread, &thread0); 161 162 /* Do basic tuning, hz etc */ 163 init_param1(); 164 165 freemempos = 0xa0200000; 166 /* Define a macro to simplify memory allocation */ 167#define valloc_pages(var, np) \ 168 alloc_pages((var).pv_pa, (np)); \ 169 (var).pv_va = (var).pv_pa + 0x20000000; 170 171#define alloc_pages(var, np) \ 172 freemempos -= (np * PAGE_SIZE); \ 173 (var) = freemempos; \ 174 memset((char *)(var), 0, ((np) * PAGE_SIZE)); 175 176 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) 177 freemempos -= PAGE_SIZE; 178 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 179 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { 180 if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { 181 valloc_pages(kernel_pt_table[loop], 182 L2_TABLE_SIZE / PAGE_SIZE); 183 } else { 184 kernel_pt_table[loop].pv_pa = freemempos + 185 (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * 186 L2_TABLE_SIZE_REAL; 187 kernel_pt_table[loop].pv_va = 188 kernel_pt_table[loop].pv_pa + 0x20000000; 189 } 190 } 191 freemem_pt = freemempos; 192 freemempos = 0xa0100000; 193 /* 194 * Allocate a page for the system page mapped to V0x00000000 195 * This page will just contain the system vectors and can be 196 * shared by all processes. 197 */ 198 valloc_pages(systempage, 1); 199 200 /* Allocate dynamic per-cpu area. */ 201 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 202 dpcpu_init((void *)dpcpu.pv_va, 0); 203 204 /* Allocate stacks for all modes */ 205 valloc_pages(irqstack, IRQ_STACK_SIZE); 206 valloc_pages(abtstack, ABT_STACK_SIZE); 207 valloc_pages(undstack, UND_STACK_SIZE); 208 valloc_pages(kernelstack, KSTACK_PAGES); 209 alloc_pages(minidataclean.pv_pa, 1); 210 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 211 /* 212 * Allocate memory for the l1 and l2 page tables. The scheme to avoid 213 * wasting memory by allocating the l1pt on the first 16k memory was 214 * taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for 215 * this to work (which is supposed to be the case). 216 */ 217 218 /* 219 * Now we start construction of the L1 page table 220 * We start by mapping the L2 page tables into the L1. 221 * This means that we can replace L1 mappings later on if necessary 222 */ 223 l1pagetable = kernel_l1pt.pv_va; 224 225 /* Map the L2 pages tables in the L1 page table */ 226 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1), 227 &kernel_pt_table[KERNEL_PT_SYS]); 228#if 0 /* XXXBJR: What is this? Don't know if there's an analogue. */ 229 pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE, 230 &kernel_pt_table[KERNEL_PT_IOPXS]); 231#endif 232 pmap_link_l2pt(l1pagetable, KERNBASE, 233 &kernel_pt_table[KERNEL_PT_BEFOREKERN]); 234 pmap_map_chunk(l1pagetable, KERNBASE, SDRAM_START, 0x100000, 235 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 236 pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, SDRAM_START + 0x100000, 237 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 238 pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, SDRAM_START + 0x200000, 239 (((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1), 240 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 241 freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1); 242 afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & 243 ~(L1_S_SIZE - 1)); 244 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { 245 pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, 246 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); 247 } 248 pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa, 249 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 250 251 252 /* Map the Mini-Data cache clean area. */ 253 xscale_setup_minidata(l1pagetable, afterkern, 254 minidataclean.pv_pa); 255 256 /* Map the vector page. */ 257 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, 258 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 259 arm_devmap_bootstrap(l1pagetable, pxa_devmap); 260 261 /* 262 * Give the XScale global cache clean code an appropriately 263 * sized chunk of unmapped VA space starting at 0xff000000 264 * (our device mappings end before this address). 265 */ 266 xscale_cache_clean_addr = 0xff000000U; 267 268 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 269 setttb(kernel_l1pt.pv_pa); 270 cpu_tlb_flushID(); 271 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); 272 273 /* 274 * Pages were allocated during the secondary bootstrap for the 275 * stacks for different CPU modes. 276 * We must now set the r13 registers in the different CPU modes to 277 * point to these stacks. 278 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 279 * of the stack memory. 280 */ 281 set_stackptrs(0); 282 283 /* 284 * We must now clean the cache again.... 285 * Cleaning may be done by reading new data to displace any 286 * dirty data in the cache. This will have happened in setttb() 287 * but since we are boot strapping the addresses used for the read 288 * may have just been remapped and thus the cache could be out 289 * of sync. A re-clean after the switch will cure this. 290 * After booting there are no gross relocations of the kernel thus 291 * this problem will not occur after initarm(). 292 */ 293 cpu_idcache_wbinv_all(); 294 cpu_setup(""); 295 296 /* 297 * Sort out bus_space for on-board devices. 298 */ 299 pxa_obio_tag_init(); 300 301 /* 302 * Fetch the SDRAM start/size from the PXA2X0 SDRAM configration 303 * registers. 304 */ 305 pxa_probe_sdram(obio_tag, PXA2X0_MEMCTL_BASE, memstart, memsize); 306 307 /* Fire up consoles. */ 308 cninit(); 309 310 undefined_init(); 311 312 init_proc0(kernelstack.pv_va); 313 314 /* Enable MMU, I-cache, D-cache, write buffer. */ 315 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 316 317 pmap_curmaxkvaddr = afterkern + PAGE_SIZE; 318 vm_max_kernel_address = 0xd0000000; 319 pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt); 320 msgbufp = (void*)msgbufpv.pv_va; 321 msgbufinit(msgbufp, msgbufsize); 322 mutex_init(); 323 324 /* 325 * Add the physical ram we have available. 326 * 327 * Exclude the kernel (and all the things we allocated which immediately 328 * follow the kernel) from the VM allocation pool but not from crash 329 * dumps. virtual_avail is a global variable which tracks the kva we've 330 * "allocated" while setting up pmaps. 331 * 332 * Prepare the list of physical memory available to the vm subsystem. 333 */ 334 for (j = 0; j < PXA2X0_SDRAM_BANKS; j++) { 335 if (memsize[j] > 0) 336 arm_physmem_hardware_region(memstart[j], memsize[j]); 337 } 338 arm_physmem_exclude_region(abp->abp_physaddr, 339 virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC); 340 arm_physmem_init_kernel_globals(); 341 342 init_param2(physmem); 343 kdb_init(); 344 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - 345 sizeof(struct pcb))); 346} 347 348static void 349pxa_probe_sdram(bus_space_tag_t bst, bus_space_handle_t bsh, 350 uint32_t *memstart, uint32_t *memsize) 351{ 352 uint32_t mdcnfg, dwid, dcac, drac, dnb; 353 int i; 354 355 mdcnfg = bus_space_read_4(bst, bsh, MEMCTL_MDCNFG); 356 357 /* 358 * Scan all 4 SDRAM banks 359 */ 360 for (i = 0; i < PXA2X0_SDRAM_BANKS; i++) { 361 memstart[i] = 0; 362 memsize[i] = 0; 363 364 switch (i) { 365 case 0: 366 case 1: 367 if ((i == 0 && (mdcnfg & MDCNFG_DE0) == 0) || 368 (i == 1 && (mdcnfg & MDCNFG_DE1) == 0)) 369 continue; 370 dwid = mdcnfg >> MDCNFD_DWID01_SHIFT; 371 dcac = mdcnfg >> MDCNFD_DCAC01_SHIFT; 372 drac = mdcnfg >> MDCNFD_DRAC01_SHIFT; 373 dnb = mdcnfg >> MDCNFD_DNB01_SHIFT; 374 break; 375 376 case 2: 377 case 3: 378 if ((i == 2 && (mdcnfg & MDCNFG_DE2) == 0) || 379 (i == 3 && (mdcnfg & MDCNFG_DE3) == 0)) 380 continue; 381 dwid = mdcnfg >> MDCNFD_DWID23_SHIFT; 382 dcac = mdcnfg >> MDCNFD_DCAC23_SHIFT; 383 drac = mdcnfg >> MDCNFD_DRAC23_SHIFT; 384 dnb = mdcnfg >> MDCNFD_DNB23_SHIFT; 385 break; 386 default: 387 panic("pxa_probe_sdram: impossible"); 388 } 389 390 dwid = 2 << (1 - (dwid & MDCNFD_DWID_MASK)); /* 16/32 width */ 391 dcac = 1 << ((dcac & MDCNFD_DCAC_MASK) + 8); /* 8-11 columns */ 392 drac = 1 << ((drac & MDCNFD_DRAC_MASK) + 11); /* 11-13 rows */ 393 dnb = 2 << (dnb & MDCNFD_DNB_MASK); /* # of banks */ 394 395 memsize[i] = dwid * dcac * drac * dnb; 396 memstart[i] = PXA2X0_SDRAM0_START + 397 (i * PXA2X0_SDRAM_BANK_SIZE); 398 } 399} 400 401#define TIMER_FREQUENCY 3686400 402#define UNIMPLEMENTED panic("%s: unimplemented", __func__) 403 404/* XXXBJR: Belongs with DELAY in a timer.c of some sort. */ 405void 406cpu_startprofclock(void) 407{ 408 UNIMPLEMENTED; 409} 410 411void 412cpu_stopprofclock(void) 413{ 414 UNIMPLEMENTED; 415} 416 417static struct arm32_dma_range pxa_range = { 418 .dr_sysbase = 0, 419 .dr_busbase = 0, 420 .dr_len = ~0u, 421}; 422 423struct arm32_dma_range * 424bus_dma_get_range(void) 425{ 426 427 return (&pxa_range); 428} 429 430int 431bus_dma_get_range_nb(void) 432{ 433 434 return (1); 435} 436