if_npe.c revision 213893
1/*- 2 * Copyright (c) 2006-2008 Sam Leffler. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25#include <sys/cdefs.h> 26__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/if_npe.c 213893 2010-10-15 14:52:11Z marius $"); 27 28/* 29 * Intel XScale NPE Ethernet driver. 30 * 31 * This driver handles the two ports present on the IXP425. 32 * Packet processing is done by the Network Processing Engines 33 * (NPE's) that work together with a MAC and PHY. The MAC 34 * is also mapped to the XScale cpu; the PHY is accessed via 35 * the MAC. NPE-XScale communication happens through h/w 36 * queues managed by the Q Manager block. 37 * 38 * The code here replaces the ethAcc, ethMii, and ethDB classes 39 * in the Intel Access Library (IAL) and the OS-specific driver. 40 * 41 * XXX add vlan support 42 */ 43#ifdef HAVE_KERNEL_OPTION_HEADERS 44#include "opt_device_polling.h" 45#endif 46 47#include <sys/param.h> 48#include <sys/systm.h> 49#include <sys/bus.h> 50#include <sys/kernel.h> 51#include <sys/mbuf.h> 52#include <sys/malloc.h> 53#include <sys/module.h> 54#include <sys/rman.h> 55#include <sys/socket.h> 56#include <sys/sockio.h> 57#include <sys/sysctl.h> 58#include <sys/endian.h> 59#include <machine/bus.h> 60 61#include <net/ethernet.h> 62#include <net/if.h> 63#include <net/if_arp.h> 64#include <net/if_dl.h> 65#include <net/if_media.h> 66#include <net/if_mib.h> 67#include <net/if_types.h> 68 69#ifdef INET 70#include <netinet/in.h> 71#include <netinet/in_systm.h> 72#include <netinet/in_var.h> 73#include <netinet/ip.h> 74#endif 75 76#include <net/bpf.h> 77#include <net/bpfdesc.h> 78 79#include <arm/xscale/ixp425/ixp425reg.h> 80#include <arm/xscale/ixp425/ixp425var.h> 81#include <arm/xscale/ixp425/ixp425_qmgr.h> 82#include <arm/xscale/ixp425/ixp425_npevar.h> 83 84#include <dev/mii/mii.h> 85#include <dev/mii/miivar.h> 86#include <arm/xscale/ixp425/if_npereg.h> 87 88#include <machine/armreg.h> 89 90#include "miibus_if.h" 91 92/* 93 * XXX: For the main bus dma tag. Can go away if the new method to get the 94 * dma tag from the parent got MFC'd into RELENG_6. 95 */ 96extern struct ixp425_softc *ixp425_softc; 97 98struct npebuf { 99 struct npebuf *ix_next; /* chain to next buffer */ 100 void *ix_m; /* backpointer to mbuf */ 101 bus_dmamap_t ix_map; /* bus dma map for associated data */ 102 struct npehwbuf *ix_hw; /* associated h/w block */ 103 uint32_t ix_neaddr; /* phys address of ix_hw */ 104}; 105 106struct npedma { 107 const char* name; 108 int nbuf; /* # npebuf's allocated */ 109 bus_dma_tag_t mtag; /* bus dma tag for mbuf data */ 110 struct npehwbuf *hwbuf; /* NPE h/w buffers */ 111 bus_dma_tag_t buf_tag; /* tag+map for NPE buffers */ 112 bus_dmamap_t buf_map; 113 bus_addr_t buf_phys; /* phys addr of buffers */ 114 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 115}; 116 117struct npe_softc { 118 /* XXX mii requires this be first; do not move! */ 119 struct ifnet *sc_ifp; /* ifnet pointer */ 120 struct mtx sc_mtx; /* basically a perimeter lock */ 121 device_t sc_dev; 122 bus_space_tag_t sc_iot; 123 bus_space_handle_t sc_ioh; /* MAC register window */ 124 device_t sc_mii; /* child miibus */ 125 bus_space_handle_t sc_miih; /* MII register window */ 126 int sc_npeid; 127 struct ixpnpe_softc *sc_npe; /* NPE support */ 128 int sc_debug; /* DPRINTF* control */ 129 int sc_tickinterval; 130 struct callout tick_ch; /* Tick callout */ 131 int npe_watchdog_timer; 132 struct npedma txdma; 133 struct npebuf *tx_free; /* list of free tx buffers */ 134 struct npedma rxdma; 135 bus_addr_t buf_phys; /* XXX for returning a value */ 136 int rx_qid; /* rx qid */ 137 int rx_freeqid; /* rx free buffers qid */ 138 int tx_qid; /* tx qid */ 139 int tx_doneqid; /* tx completed qid */ 140 struct ifmib_iso_8802_3 mibdata; 141 bus_dma_tag_t sc_stats_tag; /* bus dma tag for stats block */ 142 struct npestats *sc_stats; 143 bus_dmamap_t sc_stats_map; 144 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 145 struct npestats sc_totals; /* accumulated sc_stats */ 146}; 147 148/* 149 * Static configuration for IXP425. The tx and 150 * rx free Q id's are fixed by the NPE microcode. The 151 * rx Q id's are programmed to be separate to simplify 152 * multi-port processing. It may be better to handle 153 * all traffic through one Q (as done by the Intel drivers). 154 * 155 * Note that the PHY's are accessible only from MAC B on the 156 * IXP425 and from MAC C on other devices. This and other 157 * platform-specific assumptions are handled with hints. 158 */ 159static const struct { 160 uint32_t macbase; 161 uint32_t miibase; 162 int phy; /* phy id */ 163 uint8_t rx_qid; 164 uint8_t rx_freeqid; 165 uint8_t tx_qid; 166 uint8_t tx_doneqid; 167} npeconfig[NPE_MAX] = { 168 [NPE_A] = { 169 .macbase = IXP435_MAC_A_HWBASE, 170 .miibase = IXP425_MAC_C_HWBASE, 171 .phy = 2, 172 .rx_qid = 4, 173 .rx_freeqid = 26, 174 .tx_qid = 23, 175 .tx_doneqid = 31 176 }, 177 [NPE_B] = { 178 .macbase = IXP425_MAC_B_HWBASE, 179 .miibase = IXP425_MAC_B_HWBASE, 180 .phy = 0, 181 .rx_qid = 4, 182 .rx_freeqid = 27, 183 .tx_qid = 24, 184 .tx_doneqid = 31 185 }, 186 [NPE_C] = { 187 .macbase = IXP425_MAC_C_HWBASE, 188 .miibase = IXP425_MAC_B_HWBASE, 189 .phy = 1, 190 .rx_qid = 12, 191 .rx_freeqid = 28, 192 .tx_qid = 25, 193 .tx_doneqid = 31 194 }, 195}; 196static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 197 198static __inline uint32_t 199RD4(struct npe_softc *sc, bus_size_t off) 200{ 201 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 202} 203 204static __inline void 205WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 206{ 207 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 208} 209 210#define NPE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 211#define NPE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 212#define NPE_LOCK_INIT(_sc) \ 213 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 214 MTX_NETWORK_LOCK, MTX_DEF) 215#define NPE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 216#define NPE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 217#define NPE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 218 219static devclass_t npe_devclass; 220 221static int override_npeid(device_t, const char *resname, int *val); 222static int npe_activate(device_t dev); 223static void npe_deactivate(device_t dev); 224static int npe_ifmedia_update(struct ifnet *ifp); 225static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 226static void npe_setmac(struct npe_softc *sc, u_char *eaddr); 227static void npe_getmac(struct npe_softc *sc, u_char *eaddr); 228static void npe_txdone(int qid, void *arg); 229static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 230 struct mbuf *); 231static int npe_rxdone(int qid, void *arg); 232static void npeinit(void *); 233static void npestart_locked(struct ifnet *); 234static void npestart(struct ifnet *); 235static void npestop(struct npe_softc *); 236static void npewatchdog(struct npe_softc *); 237static int npeioctl(struct ifnet * ifp, u_long, caddr_t); 238 239static int npe_setrxqosentry(struct npe_softc *, int classix, 240 int trafclass, int qid); 241static int npe_setportaddress(struct npe_softc *, const uint8_t mac[]); 242static int npe_setfirewallmode(struct npe_softc *, int onoff); 243static int npe_updatestats(struct npe_softc *); 244#if 0 245static int npe_getstats(struct npe_softc *); 246static uint32_t npe_getimageid(struct npe_softc *); 247static int npe_setloopback(struct npe_softc *, int ena); 248#endif 249 250/* NB: all tx done processing goes through one queue */ 251static int tx_doneqid = -1; 252 253SYSCTL_NODE(_hw, OID_AUTO, npe, CTLFLAG_RD, 0, "IXP4XX NPE driver parameters"); 254 255static int npe_debug = 0; 256SYSCTL_INT(_hw_npe, OID_AUTO, debug, CTLFLAG_RW, &npe_debug, 257 0, "IXP4XX NPE network interface debug msgs"); 258TUNABLE_INT("hw.npe.debug", &npe_debug); 259#define DPRINTF(sc, fmt, ...) do { \ 260 if (sc->sc_debug) device_printf(sc->sc_dev, fmt, __VA_ARGS__); \ 261} while (0) 262#define DPRINTFn(n, sc, fmt, ...) do { \ 263 if (sc->sc_debug >= n) device_printf(sc->sc_dev, fmt, __VA_ARGS__);\ 264} while (0) 265static int npe_tickinterval = 3; /* npe_tick frequency (secs) */ 266SYSCTL_INT(_hw_npe, OID_AUTO, tickinterval, CTLFLAG_RD, &npe_tickinterval, 267 0, "periodic work interval (secs)"); 268TUNABLE_INT("hw.npe.tickinterval", &npe_tickinterval); 269 270static int npe_rxbuf = 64; /* # rx buffers to allocate */ 271SYSCTL_INT(_hw_npe, OID_AUTO, rxbuf, CTLFLAG_RD, &npe_rxbuf, 272 0, "rx buffers allocated"); 273TUNABLE_INT("hw.npe.rxbuf", &npe_rxbuf); 274static int npe_txbuf = 128; /* # tx buffers to allocate */ 275SYSCTL_INT(_hw_npe, OID_AUTO, txbuf, CTLFLAG_RD, &npe_txbuf, 276 0, "tx buffers allocated"); 277TUNABLE_INT("hw.npe.txbuf", &npe_txbuf); 278 279static int 280unit2npeid(int unit) 281{ 282 static const int npeidmap[2][3] = { 283 /* on 425 A is for HSS, B & C are for Ethernet */ 284 { NPE_B, NPE_C, -1 }, /* IXP425 */ 285 /* 435 only has A & C, order C then A */ 286 { NPE_C, NPE_A, -1 }, /* IXP435 */ 287 }; 288 /* XXX check feature register instead */ 289 return (unit < 3 ? npeidmap[ 290 (cpu_id() & CPU_ID_CPU_MASK) == CPU_ID_IXP435][unit] : -1); 291} 292 293static int 294npe_probe(device_t dev) 295{ 296 static const char *desc[NPE_MAX] = { 297 [NPE_A] = "IXP NPE-A", 298 [NPE_B] = "IXP NPE-B", 299 [NPE_C] = "IXP NPE-C" 300 }; 301 int unit = device_get_unit(dev); 302 int npeid; 303 304 if (unit > 2 || 305 (ixp4xx_read_feature_bits() & 306 (unit == 0 ? EXP_FCTRL_ETH0 : EXP_FCTRL_ETH1)) == 0) 307 return EINVAL; 308 309 npeid = -1; 310 if (!override_npeid(dev, "npeid", &npeid)) 311 npeid = unit2npeid(unit); 312 if (npeid == -1) { 313 device_printf(dev, "unit %d not supported\n", unit); 314 return EINVAL; 315 } 316 device_set_desc(dev, desc[npeid]); 317 return 0; 318} 319 320static int 321npe_attach(device_t dev) 322{ 323 struct npe_softc *sc = device_get_softc(dev); 324 struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); 325 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 326 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 327 struct ifnet *ifp; 328 int error; 329 u_char eaddr[6]; 330 331 sc->sc_dev = dev; 332 sc->sc_iot = sa->sc_iot; 333 NPE_LOCK_INIT(sc); 334 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 335 sc->sc_debug = npe_debug; 336 sc->sc_tickinterval = npe_tickinterval; 337 338 ifp = if_alloc(IFT_ETHER); 339 if (ifp == NULL) { 340 device_printf(dev, "cannot allocate ifnet\n"); 341 error = EIO; /* XXX */ 342 goto out; 343 } 344 /* NB: must be setup prior to invoking mii code */ 345 sc->sc_ifp = ifp; 346 347 error = npe_activate(dev); 348 if (error) { 349 device_printf(dev, "cannot activate npe\n"); 350 goto out; 351 } 352 353 npe_getmac(sc, eaddr); 354 355 ifp->if_softc = sc; 356 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 357 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 358 ifp->if_start = npestart; 359 ifp->if_ioctl = npeioctl; 360 ifp->if_init = npeinit; 361 IFQ_SET_MAXLEN(&ifp->if_snd, sc->txdma.nbuf - 1); 362 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 363 IFQ_SET_READY(&ifp->if_snd); 364 ifp->if_linkmib = &sc->mibdata; 365 ifp->if_linkmiblen = sizeof(sc->mibdata); 366 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_STATS; 367 /* device supports oversided vlan frames */ 368 ifp->if_capabilities |= IFCAP_VLAN_MTU; 369 ifp->if_capenable = ifp->if_capabilities; 370#ifdef DEVICE_POLLING 371 ifp->if_capabilities |= IFCAP_POLLING; 372#endif 373 374 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug", 375 CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 376 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tickinterval", 377 CTLFLAG_RW, &sc->sc_tickinterval, 0, "periodic work frequency"); 378 SYSCTL_ADD_STRUCT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "stats", 379 CTLFLAG_RD, &sc->sc_totals, npestats, "onboard stats"); 380 381 ether_ifattach(ifp, eaddr); 382 return 0; 383out: 384 if (ifp != NULL) 385 if_free(ifp); 386 NPE_LOCK_DESTROY(sc); 387 npe_deactivate(dev); 388 return error; 389} 390 391static int 392npe_detach(device_t dev) 393{ 394 struct npe_softc *sc = device_get_softc(dev); 395 struct ifnet *ifp = sc->sc_ifp; 396 397#ifdef DEVICE_POLLING 398 if (ifp->if_capenable & IFCAP_POLLING) 399 ether_poll_deregister(ifp); 400#endif 401 npestop(sc); 402 if (ifp != NULL) { 403 ether_ifdetach(ifp); 404 if_free(ifp); 405 } 406 NPE_LOCK_DESTROY(sc); 407 npe_deactivate(dev); 408 return 0; 409} 410 411/* 412 * Compute and install the multicast filter. 413 */ 414static void 415npe_setmcast(struct npe_softc *sc) 416{ 417 struct ifnet *ifp = sc->sc_ifp; 418 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 419 int i; 420 421 if (ifp->if_flags & IFF_PROMISC) { 422 memset(mask, 0, ETHER_ADDR_LEN); 423 memset(addr, 0, ETHER_ADDR_LEN); 424 } else if (ifp->if_flags & IFF_ALLMULTI) { 425 static const uint8_t allmulti[ETHER_ADDR_LEN] = 426 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 427 memcpy(mask, allmulti, ETHER_ADDR_LEN); 428 memcpy(addr, allmulti, ETHER_ADDR_LEN); 429 } else { 430 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 431 struct ifmultiaddr *ifma; 432 const uint8_t *mac; 433 434 memset(clr, 0, ETHER_ADDR_LEN); 435 memset(set, 0xff, ETHER_ADDR_LEN); 436 437 if_maddr_rlock(ifp); 438 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 439 if (ifma->ifma_addr->sa_family != AF_LINK) 440 continue; 441 mac = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 442 for (i = 0; i < ETHER_ADDR_LEN; i++) { 443 clr[i] |= mac[i]; 444 set[i] &= mac[i]; 445 } 446 } 447 if_maddr_runlock(ifp); 448 449 for (i = 0; i < ETHER_ADDR_LEN; i++) { 450 mask[i] = set[i] | ~clr[i]; 451 addr[i] = set[i]; 452 } 453 } 454 455 /* 456 * Write the mask and address registers. 457 */ 458 for (i = 0; i < ETHER_ADDR_LEN; i++) { 459 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 460 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 461 } 462} 463 464static void 465npe_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 466{ 467 struct npe_softc *sc; 468 469 if (error != 0) 470 return; 471 sc = (struct npe_softc *)arg; 472 sc->buf_phys = segs[0].ds_addr; 473} 474 475static int 476npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 477 const char *name, int nbuf, int maxseg) 478{ 479 int error, i; 480 481 memset(dma, 0, sizeof(*dma)); 482 483 dma->name = name; 484 dma->nbuf = nbuf; 485 486 /* DMA tag for mapped mbufs */ 487 error = bus_dma_tag_create(ixp425_softc->sc_dmat, 1, 0, 488 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 489 MCLBYTES, maxseg, MCLBYTES, 0, 490 busdma_lock_mutex, &sc->sc_mtx, &dma->mtag); 491 if (error != 0) { 492 device_printf(sc->sc_dev, "unable to create %s mbuf dma tag, " 493 "error %u\n", dma->name, error); 494 return error; 495 } 496 497 /* DMA tag and map for the NPE buffers */ 498 error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 499 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 500 nbuf * sizeof(struct npehwbuf), 1, 501 nbuf * sizeof(struct npehwbuf), 0, 502 busdma_lock_mutex, &sc->sc_mtx, &dma->buf_tag); 503 if (error != 0) { 504 device_printf(sc->sc_dev, 505 "unable to create %s npebuf dma tag, error %u\n", 506 dma->name, error); 507 return error; 508 } 509 /* XXX COHERENT for now */ 510 if (bus_dmamem_alloc(dma->buf_tag, (void **)&dma->hwbuf, 511 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 512 &dma->buf_map) != 0) { 513 device_printf(sc->sc_dev, 514 "unable to allocate memory for %s h/w buffers, error %u\n", 515 dma->name, error); 516 return error; 517 } 518 /* XXX M_TEMP */ 519 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 520 if (dma->buf == NULL) { 521 device_printf(sc->sc_dev, 522 "unable to allocate memory for %s s/w buffers\n", 523 dma->name); 524 return error; 525 } 526 if (bus_dmamap_load(dma->buf_tag, dma->buf_map, 527 dma->hwbuf, nbuf*sizeof(struct npehwbuf), npe_getaddr, sc, 0) != 0) { 528 device_printf(sc->sc_dev, 529 "unable to map memory for %s h/w buffers, error %u\n", 530 dma->name, error); 531 return error; 532 } 533 dma->buf_phys = sc->buf_phys; 534 for (i = 0; i < dma->nbuf; i++) { 535 struct npebuf *npe = &dma->buf[i]; 536 struct npehwbuf *hw = &dma->hwbuf[i]; 537 538 /* calculate offset to shared area */ 539 npe->ix_neaddr = dma->buf_phys + 540 ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 541 KASSERT((npe->ix_neaddr & 0x1f) == 0, 542 ("ixpbuf misaligned, PA 0x%x", npe->ix_neaddr)); 543 error = bus_dmamap_create(dma->mtag, BUS_DMA_NOWAIT, 544 &npe->ix_map); 545 if (error != 0) { 546 device_printf(sc->sc_dev, 547 "unable to create dmamap for %s buffer %u, " 548 "error %u\n", dma->name, i, error); 549 return error; 550 } 551 npe->ix_hw = hw; 552 } 553 bus_dmamap_sync(dma->buf_tag, dma->buf_map, BUS_DMASYNC_PREWRITE); 554 return 0; 555} 556 557static void 558npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 559{ 560 int i; 561 562 if (dma->hwbuf != NULL) { 563 for (i = 0; i < dma->nbuf; i++) { 564 struct npebuf *npe = &dma->buf[i]; 565 bus_dmamap_destroy(dma->mtag, npe->ix_map); 566 } 567 bus_dmamap_unload(dma->buf_tag, dma->buf_map); 568 bus_dmamem_free(dma->buf_tag, dma->hwbuf, dma->buf_map); 569 } 570 if (dma->buf != NULL) 571 free(dma->buf, M_TEMP); 572 if (dma->buf_tag) 573 bus_dma_tag_destroy(dma->buf_tag); 574 if (dma->mtag) 575 bus_dma_tag_destroy(dma->mtag); 576 memset(dma, 0, sizeof(*dma)); 577} 578 579static int 580override_addr(device_t dev, const char *resname, int *base) 581{ 582 int unit = device_get_unit(dev); 583 const char *resval; 584 585 /* XXX warn for wrong hint type */ 586 if (resource_string_value("npe", unit, resname, &resval) != 0) 587 return 0; 588 switch (resval[0]) { 589 case 'A': 590 *base = IXP435_MAC_A_HWBASE; 591 break; 592 case 'B': 593 *base = IXP425_MAC_B_HWBASE; 594 break; 595 case 'C': 596 *base = IXP425_MAC_C_HWBASE; 597 break; 598 default: 599 device_printf(dev, "Warning, bad value %s for " 600 "npe.%d.%s ignored\n", resval, unit, resname); 601 return 0; 602 } 603 if (bootverbose) 604 device_printf(dev, "using npe.%d.%s=%s override\n", 605 unit, resname, resval); 606 return 1; 607} 608 609static int 610override_npeid(device_t dev, const char *resname, int *npeid) 611{ 612 int unit = device_get_unit(dev); 613 const char *resval; 614 615 /* XXX warn for wrong hint type */ 616 if (resource_string_value("npe", unit, resname, &resval) != 0) 617 return 0; 618 switch (resval[0]) { 619 case 'A': *npeid = NPE_A; break; 620 case 'B': *npeid = NPE_B; break; 621 case 'C': *npeid = NPE_C; break; 622 default: 623 device_printf(dev, "Warning, bad value %s for " 624 "npe.%d.%s ignored\n", resval, unit, resname); 625 return 0; 626 } 627 if (bootverbose) 628 device_printf(dev, "using npe.%d.%s=%s override\n", 629 unit, resname, resval); 630 return 1; 631} 632 633static int 634override_unit(device_t dev, const char *resname, int *val, int min, int max) 635{ 636 int unit = device_get_unit(dev); 637 int resval; 638 639 if (resource_int_value("npe", unit, resname, &resval) != 0) 640 return 0; 641 if (!(min <= resval && resval <= max)) { 642 device_printf(dev, "Warning, bad value %d for npe.%d.%s " 643 "ignored (value must be [%d-%d])\n", resval, unit, 644 resname, min, max); 645 return 0; 646 } 647 if (bootverbose) 648 device_printf(dev, "using npe.%d.%s=%d override\n", 649 unit, resname, resval); 650 *val = resval; 651 return 1; 652} 653 654static void 655npe_mac_reset(struct npe_softc *sc) 656{ 657 /* 658 * Reset MAC core. 659 */ 660 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 661 DELAY(NPE_MAC_RESET_DELAY); 662 /* configure MAC to generate MDC clock */ 663 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 664} 665 666static int 667npe_activate(device_t dev) 668{ 669 struct npe_softc *sc = device_get_softc(dev); 670 int error, i, macbase, miibase, phy; 671 672 /* 673 * Setup NEP ID, MAC, and MII bindings. We allow override 674 * via hints to handle unexpected board configs. 675 */ 676 if (!override_npeid(dev, "npeid", &sc->sc_npeid)) 677 sc->sc_npeid = unit2npeid(device_get_unit(dev)); 678 sc->sc_npe = ixpnpe_attach(dev, sc->sc_npeid); 679 if (sc->sc_npe == NULL) { 680 device_printf(dev, "cannot attach ixpnpe\n"); 681 return EIO; /* XXX */ 682 } 683 684 /* MAC */ 685 if (!override_addr(dev, "mac", &macbase)) 686 macbase = npeconfig[sc->sc_npeid].macbase; 687 device_printf(sc->sc_dev, "MAC at 0x%x\n", macbase); 688 if (bus_space_map(sc->sc_iot, macbase, IXP425_REG_SIZE, 0, &sc->sc_ioh)) { 689 device_printf(dev, "cannot map mac registers 0x%x:0x%x\n", 690 macbase, IXP425_REG_SIZE); 691 return ENOMEM; 692 } 693 694 /* PHY */ 695 if (!override_unit(dev, "phy", &phy, 0, MII_NPHY - 1)) 696 phy = npeconfig[sc->sc_npeid].phy; 697 if (!override_addr(dev, "mii", &miibase)) 698 miibase = npeconfig[sc->sc_npeid].miibase; 699 device_printf(sc->sc_dev, "MII at 0x%x\n", miibase); 700 if (miibase != macbase) { 701 /* 702 * PHY is mapped through a different MAC, setup an 703 * additional mapping for frobbing the PHY registers. 704 */ 705 if (bus_space_map(sc->sc_iot, miibase, IXP425_REG_SIZE, 0, &sc->sc_miih)) { 706 device_printf(dev, 707 "cannot map MII registers 0x%x:0x%x\n", 708 miibase, IXP425_REG_SIZE); 709 return ENOMEM; 710 } 711 } else 712 sc->sc_miih = sc->sc_ioh; 713 714 /* 715 * Load NPE firmware and start it running. 716 */ 717 error = ixpnpe_init(sc->sc_npe); 718 if (error != 0) { 719 device_printf(dev, "cannot init NPE (error %d)\n", error); 720 return error; 721 } 722 723 /* attach PHY */ 724 error = mii_attach(dev, &sc->sc_mii, sc->sc_ifp, npe_ifmedia_update, 725 npe_ifmedia_status, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 726 if (error != 0) { 727 device_printf(dev, "attaching PHYs failed\n"); 728 return error; 729 } 730 731 error = npe_dma_setup(sc, &sc->txdma, "tx", npe_txbuf, NPE_MAXSEG); 732 if (error != 0) 733 return error; 734 error = npe_dma_setup(sc, &sc->rxdma, "rx", npe_rxbuf, 1); 735 if (error != 0) 736 return error; 737 738 /* setup statistics block */ 739 error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 740 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 741 sizeof(struct npestats), 1, sizeof(struct npestats), 0, 742 busdma_lock_mutex, &sc->sc_mtx, &sc->sc_stats_tag); 743 if (error != 0) { 744 device_printf(sc->sc_dev, "unable to create stats tag, " 745 "error %u\n", error); 746 return error; 747 } 748 if (bus_dmamem_alloc(sc->sc_stats_tag, (void **)&sc->sc_stats, 749 BUS_DMA_NOWAIT, &sc->sc_stats_map) != 0) { 750 device_printf(sc->sc_dev, 751 "unable to allocate memory for stats block, error %u\n", 752 error); 753 return error; 754 } 755 if (bus_dmamap_load(sc->sc_stats_tag, sc->sc_stats_map, 756 sc->sc_stats, sizeof(struct npestats), npe_getaddr, sc, 0) != 0) { 757 device_printf(sc->sc_dev, 758 "unable to load memory for stats block, error %u\n", 759 error); 760 return error; 761 } 762 sc->sc_stats_phys = sc->buf_phys; 763 764 /* 765 * Setup h/w rx/tx queues. There are four q's: 766 * rx inbound q of rx'd frames 767 * rx_free pool of ixpbuf's for receiving frames 768 * tx outbound q of frames to send 769 * tx_done q of tx frames that have been processed 770 * 771 * The NPE handles the actual tx/rx process and the q manager 772 * handles the queues. The driver just writes entries to the 773 * q manager mailbox's and gets callbacks when there are rx'd 774 * frames to process or tx'd frames to reap. These callbacks 775 * are controlled by the q configurations; e.g. we get a 776 * callback when tx_done has 2 or more frames to process and 777 * when the rx q has at least one frame. These setings can 778 * changed at the time the q is configured. 779 */ 780 sc->rx_qid = npeconfig[sc->sc_npeid].rx_qid; 781 ixpqmgr_qconfig(sc->rx_qid, npe_rxbuf, 0, 1, 782 IX_QMGR_Q_SOURCE_ID_NOT_E, (qconfig_hand_t *)npe_rxdone, sc); 783 sc->rx_freeqid = npeconfig[sc->sc_npeid].rx_freeqid; 784 ixpqmgr_qconfig(sc->rx_freeqid, npe_rxbuf, 0, npe_rxbuf/2, 0, NULL, sc); 785 /* 786 * Setup the NPE to direct all traffic to rx_qid. 787 * When QoS is enabled in the firmware there are 788 * 8 traffic classes; otherwise just 4. 789 */ 790 for (i = 0; i < 8; i++) 791 npe_setrxqosentry(sc, i, 0, sc->rx_qid); 792 793 /* disable firewall mode just in case (should be off) */ 794 npe_setfirewallmode(sc, 0); 795 796 sc->tx_qid = npeconfig[sc->sc_npeid].tx_qid; 797 sc->tx_doneqid = npeconfig[sc->sc_npeid].tx_doneqid; 798 ixpqmgr_qconfig(sc->tx_qid, npe_txbuf, 0, npe_txbuf, 0, NULL, sc); 799 if (tx_doneqid == -1) { 800 ixpqmgr_qconfig(sc->tx_doneqid, npe_txbuf, 0, 2, 801 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 802 tx_doneqid = sc->tx_doneqid; 803 } 804 805 KASSERT(npes[sc->sc_npeid] == NULL, 806 ("npe %u already setup", sc->sc_npeid)); 807 npes[sc->sc_npeid] = sc; 808 809 return 0; 810} 811 812static void 813npe_deactivate(device_t dev) 814{ 815 struct npe_softc *sc = device_get_softc(dev); 816 817 npes[sc->sc_npeid] = NULL; 818 819 /* XXX disable q's */ 820 if (sc->sc_npe != NULL) { 821 ixpnpe_stop(sc->sc_npe); 822 ixpnpe_detach(sc->sc_npe); 823 } 824 if (sc->sc_stats != NULL) { 825 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 826 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 827 sc->sc_stats_map); 828 } 829 if (sc->sc_stats_tag != NULL) 830 bus_dma_tag_destroy(sc->sc_stats_tag); 831 npe_dma_destroy(sc, &sc->txdma); 832 npe_dma_destroy(sc, &sc->rxdma); 833 bus_generic_detach(sc->sc_dev); 834 if (sc->sc_mii != NULL) 835 device_delete_child(sc->sc_dev, sc->sc_mii); 836} 837 838/* 839 * Change media according to request. 840 */ 841static int 842npe_ifmedia_update(struct ifnet *ifp) 843{ 844 struct npe_softc *sc = ifp->if_softc; 845 struct mii_data *mii; 846 847 mii = device_get_softc(sc->sc_mii); 848 NPE_LOCK(sc); 849 mii_mediachg(mii); 850 /* XXX push state ourself? */ 851 NPE_UNLOCK(sc); 852 return (0); 853} 854 855/* 856 * Notify the world which media we're using. 857 */ 858static void 859npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 860{ 861 struct npe_softc *sc = ifp->if_softc; 862 struct mii_data *mii; 863 864 mii = device_get_softc(sc->sc_mii); 865 NPE_LOCK(sc); 866 mii_pollstat(mii); 867 ifmr->ifm_active = mii->mii_media_active; 868 ifmr->ifm_status = mii->mii_media_status; 869 NPE_UNLOCK(sc); 870} 871 872static void 873npe_addstats(struct npe_softc *sc) 874{ 875#define NPEADD(x) sc->sc_totals.x += be32toh(ns->x) 876#define MIBADD(x) do { sc->mibdata.x += be32toh(ns->x); NPEADD(x); } while (0) 877 struct ifnet *ifp = sc->sc_ifp; 878 struct npestats *ns = sc->sc_stats; 879 880 MIBADD(dot3StatsAlignmentErrors); 881 MIBADD(dot3StatsFCSErrors); 882 MIBADD(dot3StatsInternalMacReceiveErrors); 883 NPEADD(RxOverrunDiscards); 884 NPEADD(RxLearnedEntryDiscards); 885 NPEADD(RxLargeFramesDiscards); 886 NPEADD(RxSTPBlockedDiscards); 887 NPEADD(RxVLANTypeFilterDiscards); 888 NPEADD(RxVLANIdFilterDiscards); 889 NPEADD(RxInvalidSourceDiscards); 890 NPEADD(RxBlackListDiscards); 891 NPEADD(RxWhiteListDiscards); 892 NPEADD(RxUnderflowEntryDiscards); 893 MIBADD(dot3StatsSingleCollisionFrames); 894 MIBADD(dot3StatsMultipleCollisionFrames); 895 MIBADD(dot3StatsDeferredTransmissions); 896 MIBADD(dot3StatsLateCollisions); 897 MIBADD(dot3StatsExcessiveCollisions); 898 MIBADD(dot3StatsInternalMacTransmitErrors); 899 MIBADD(dot3StatsCarrierSenseErrors); 900 NPEADD(TxLargeFrameDiscards); 901 NPEADD(TxVLANIdFilterDiscards); 902 903 sc->mibdata.dot3StatsFrameTooLongs += 904 be32toh(ns->RxLargeFramesDiscards) 905 + be32toh(ns->TxLargeFrameDiscards); 906 sc->mibdata.dot3StatsMissedFrames += 907 be32toh(ns->RxOverrunDiscards) 908 + be32toh(ns->RxUnderflowEntryDiscards); 909 910 ifp->if_oerrors += 911 be32toh(ns->dot3StatsInternalMacTransmitErrors) 912 + be32toh(ns->dot3StatsCarrierSenseErrors) 913 + be32toh(ns->TxVLANIdFilterDiscards) 914 ; 915 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 916 + be32toh(ns->dot3StatsInternalMacReceiveErrors) 917 + be32toh(ns->RxOverrunDiscards) 918 + be32toh(ns->RxUnderflowEntryDiscards) 919 ; 920 ifp->if_collisions += 921 be32toh(ns->dot3StatsSingleCollisionFrames) 922 + be32toh(ns->dot3StatsMultipleCollisionFrames) 923 ; 924#undef NPEADD 925#undef MIBADD 926} 927 928static void 929npe_tick(void *xsc) 930{ 931#define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 932 struct npe_softc *sc = xsc; 933 struct mii_data *mii = device_get_softc(sc->sc_mii); 934 uint32_t msg[2]; 935 936 NPE_ASSERT_LOCKED(sc); 937 938 /* 939 * NB: to avoid sleeping with the softc lock held we 940 * split the NPE msg processing into two parts. The 941 * request for statistics is sent w/o waiting for a 942 * reply and then on the next tick we retrieve the 943 * results. This works because npe_tick is the only 944 * code that talks via the mailbox's (except at setup). 945 * This likely can be handled better. 946 */ 947 if (ixpnpe_recvmsg_async(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 948 bus_dmamap_sync(sc->sc_stats_tag, sc->sc_stats_map, 949 BUS_DMASYNC_POSTREAD); 950 npe_addstats(sc); 951 } 952 npe_updatestats(sc); 953 mii_tick(mii); 954 955 npewatchdog(sc); 956 957 /* schedule next poll */ 958 callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 959#undef ACK 960} 961 962static void 963npe_setmac(struct npe_softc *sc, u_char *eaddr) 964{ 965 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 966 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 967 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 968 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 969 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 970 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 971} 972 973static void 974npe_getmac(struct npe_softc *sc, u_char *eaddr) 975{ 976 /* NB: the unicast address appears to be loaded from EEPROM on reset */ 977 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 978 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 979 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 980 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 981 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 982 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 983} 984 985struct txdone { 986 struct npebuf *head; 987 struct npebuf **tail; 988 int count; 989}; 990 991static __inline void 992npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 993{ 994 struct ifnet *ifp = sc->sc_ifp; 995 996 NPE_LOCK(sc); 997 *td->tail = sc->tx_free; 998 sc->tx_free = td->head; 999 /* 1000 * We're no longer busy, so clear the busy flag and call the 1001 * start routine to xmit more packets. 1002 */ 1003 ifp->if_opackets += td->count; 1004 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1005 sc->npe_watchdog_timer = 0; 1006 npestart_locked(ifp); 1007 NPE_UNLOCK(sc); 1008} 1009 1010/* 1011 * Q manager callback on tx done queue. Reap mbufs 1012 * and return tx buffers to the free list. Finally 1013 * restart output. Note the microcode has only one 1014 * txdone q wired into it so we must use the NPE ID 1015 * returned with each npehwbuf to decide where to 1016 * send buffers. 1017 */ 1018static void 1019npe_txdone(int qid, void *arg) 1020{ 1021#define P2V(a, dma) \ 1022 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1023 struct npe_softc *sc0 = arg; 1024 struct npe_softc *sc; 1025 struct npebuf *npe; 1026 struct txdone *td, q[NPE_MAX]; 1027 uint32_t entry; 1028 1029 q[NPE_A].tail = &q[NPE_A].head; q[NPE_A].count = 0; 1030 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 1031 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 1032 /* XXX max # at a time? */ 1033 while (ixpqmgr_qread(qid, &entry) == 0) { 1034 DPRINTF(sc0, "%s: entry 0x%x NPE %u port %u\n", 1035 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 1036 1037 sc = npes[NPE_QM_Q_NPE(entry)]; 1038 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 1039 m_freem(npe->ix_m); 1040 npe->ix_m = NULL; 1041 1042 td = &q[NPE_QM_Q_NPE(entry)]; 1043 *td->tail = npe; 1044 td->tail = &npe->ix_next; 1045 td->count++; 1046 } 1047 1048 if (q[NPE_A].count) 1049 npe_txdone_finish(npes[NPE_A], &q[NPE_A]); 1050 if (q[NPE_B].count) 1051 npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 1052 if (q[NPE_C].count) 1053 npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 1054#undef P2V 1055} 1056 1057static int 1058npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 1059{ 1060 bus_dma_segment_t segs[1]; 1061 struct npedma *dma = &sc->rxdma; 1062 struct npehwbuf *hw; 1063 int error, nseg; 1064 1065 if (m == NULL) { 1066 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1067 if (m == NULL) 1068 return ENOBUFS; 1069 } 1070 KASSERT(m->m_ext.ext_size >= 1536 + ETHER_ALIGN, 1071 ("ext_size %d", m->m_ext.ext_size)); 1072 m->m_pkthdr.len = m->m_len = 1536; 1073 /* backload payload and align ip hdr */ 1074 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN)); 1075 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, m, 1076 segs, &nseg, 0); 1077 if (error != 0) { 1078 m_freem(m); 1079 return error; 1080 } 1081 hw = npe->ix_hw; 1082 hw->ix_ne[0].data = htobe32(segs[0].ds_addr); 1083 /* NB: NPE requires length be a multiple of 64 */ 1084 /* NB: buffer length is shifted in word */ 1085 hw->ix_ne[0].len = htobe32(segs[0].ds_len << 16); 1086 hw->ix_ne[0].next = 0; 1087 npe->ix_m = m; 1088 /* Flush the memory in the mbuf */ 1089 bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREREAD); 1090 return 0; 1091} 1092 1093/* 1094 * RX q processing for a specific NPE. Claim entries 1095 * from the hardware queue and pass the frames up the 1096 * stack. Pass the rx buffers to the free list. 1097 */ 1098static int 1099npe_rxdone(int qid, void *arg) 1100{ 1101#define P2V(a, dma) \ 1102 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1103 struct npe_softc *sc = arg; 1104 struct npedma *dma = &sc->rxdma; 1105 uint32_t entry; 1106 int rx_npkts = 0; 1107 1108 while (ixpqmgr_qread(qid, &entry) == 0) { 1109 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 1110 struct mbuf *m; 1111 1112 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 1113 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 1114 /* 1115 * Allocate a new mbuf to replenish the rx buffer. 1116 * If doing so fails we drop the rx'd frame so we 1117 * can reuse the previous mbuf. When we're able to 1118 * allocate a new mbuf dispatch the mbuf w/ rx'd 1119 * data up the stack and replace it with the newly 1120 * allocated one. 1121 */ 1122 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1123 if (m != NULL) { 1124 struct mbuf *mrx = npe->ix_m; 1125 struct npehwbuf *hw = npe->ix_hw; 1126 struct ifnet *ifp = sc->sc_ifp; 1127 1128 /* Flush mbuf memory for rx'd data */ 1129 bus_dmamap_sync(dma->mtag, npe->ix_map, 1130 BUS_DMASYNC_POSTREAD); 1131 1132 /* XXX flush hw buffer; works now 'cuz coherent */ 1133 /* set m_len etc. per rx frame size */ 1134 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 1135 mrx->m_pkthdr.len = mrx->m_len; 1136 mrx->m_pkthdr.rcvif = ifp; 1137 1138 ifp->if_ipackets++; 1139 ifp->if_input(ifp, mrx); 1140 rx_npkts++; 1141 } else { 1142 /* discard frame and re-use mbuf */ 1143 m = npe->ix_m; 1144 } 1145 if (npe_rxbuf_init(sc, npe, m) == 0) { 1146 /* return npe buf to rx free list */ 1147 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1148 } else { 1149 /* XXX should not happen */ 1150 } 1151 } 1152 return rx_npkts; 1153#undef P2V 1154} 1155 1156#ifdef DEVICE_POLLING 1157static int 1158npe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1159{ 1160 struct npe_softc *sc = ifp->if_softc; 1161 int rx_npkts = 0; 1162 1163 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1164 rx_npkts = npe_rxdone(sc->rx_qid, sc); 1165 npe_txdone(sc->tx_doneqid, sc); /* XXX polls both NPE's */ 1166 } 1167 return rx_npkts; 1168} 1169#endif /* DEVICE_POLLING */ 1170 1171static void 1172npe_startxmit(struct npe_softc *sc) 1173{ 1174 struct npedma *dma = &sc->txdma; 1175 int i; 1176 1177 NPE_ASSERT_LOCKED(sc); 1178 sc->tx_free = NULL; 1179 for (i = 0; i < dma->nbuf; i++) { 1180 struct npebuf *npe = &dma->buf[i]; 1181 if (npe->ix_m != NULL) { 1182 /* NB: should not happen */ 1183 device_printf(sc->sc_dev, 1184 "%s: free mbuf at entry %u\n", __func__, i); 1185 m_freem(npe->ix_m); 1186 } 1187 npe->ix_m = NULL; 1188 npe->ix_next = sc->tx_free; 1189 sc->tx_free = npe; 1190 } 1191} 1192 1193static void 1194npe_startrecv(struct npe_softc *sc) 1195{ 1196 struct npedma *dma = &sc->rxdma; 1197 struct npebuf *npe; 1198 int i; 1199 1200 NPE_ASSERT_LOCKED(sc); 1201 for (i = 0; i < dma->nbuf; i++) { 1202 npe = &dma->buf[i]; 1203 npe_rxbuf_init(sc, npe, npe->ix_m); 1204 /* set npe buf on rx free list */ 1205 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1206 } 1207} 1208 1209/* 1210 * Reset and initialize the chip 1211 */ 1212static void 1213npeinit_locked(void *xsc) 1214{ 1215 struct npe_softc *sc = xsc; 1216 struct ifnet *ifp = sc->sc_ifp; 1217 1218 NPE_ASSERT_LOCKED(sc); 1219if (ifp->if_drv_flags & IFF_DRV_RUNNING) return;/*XXX*/ 1220 1221 /* 1222 * Reset MAC core. 1223 */ 1224 npe_mac_reset(sc); 1225 1226 /* disable transmitter and reciver in the MAC */ 1227 WR4(sc, NPE_MAC_RX_CNTRL1, 1228 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1229 WR4(sc, NPE_MAC_TX_CNTRL1, 1230 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1231 1232 /* 1233 * Set the MAC core registers. 1234 */ 1235 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1236 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1237 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1238 /* thresholds determined by NPE firmware FS */ 1239 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1240 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1241 WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */ 1242 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1243 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1244 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1245 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1246 WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */ 1247 1248 WR4(sc, NPE_MAC_TX_CNTRL1, 1249 NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1250 | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1251 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1252 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1253 /* XXX pad strip? */ 1254 /* ena pause frame handling */ 1255 WR4(sc, NPE_MAC_RX_CNTRL1, NPE_RX_CNTRL1_PAUSE_EN); 1256 WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1257 1258 npe_setmac(sc, IF_LLADDR(ifp)); 1259 npe_setportaddress(sc, IF_LLADDR(ifp)); 1260 npe_setmcast(sc); 1261 1262 npe_startxmit(sc); 1263 npe_startrecv(sc); 1264 1265 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1266 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1267 sc->npe_watchdog_timer = 0; /* just in case */ 1268 1269 /* enable transmitter and reciver in the MAC */ 1270 WR4(sc, NPE_MAC_RX_CNTRL1, 1271 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1272 WR4(sc, NPE_MAC_TX_CNTRL1, 1273 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1274 1275 callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 1276} 1277 1278static void 1279npeinit(void *xsc) 1280{ 1281 struct npe_softc *sc = xsc; 1282 NPE_LOCK(sc); 1283 npeinit_locked(sc); 1284 NPE_UNLOCK(sc); 1285} 1286 1287/* 1288 * Dequeue packets and place on the h/w transmit queue. 1289 */ 1290static void 1291npestart_locked(struct ifnet *ifp) 1292{ 1293 struct npe_softc *sc = ifp->if_softc; 1294 struct npebuf *npe; 1295 struct npehwbuf *hw; 1296 struct mbuf *m, *n; 1297 struct npedma *dma = &sc->txdma; 1298 bus_dma_segment_t segs[NPE_MAXSEG]; 1299 int nseg, len, error, i; 1300 uint32_t next; 1301 1302 NPE_ASSERT_LOCKED(sc); 1303 /* XXX can this happen? */ 1304 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1305 return; 1306 1307 while (sc->tx_free != NULL) { 1308 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1309 if (m == NULL) { 1310 /* XXX? */ 1311 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1312 return; 1313 } 1314 npe = sc->tx_free; 1315 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1316 m, segs, &nseg, 0); 1317 if (error == EFBIG) { 1318 n = m_collapse(m, M_DONTWAIT, NPE_MAXSEG); 1319 if (n == NULL) { 1320 if_printf(ifp, "%s: too many fragments %u\n", 1321 __func__, nseg); 1322 m_freem(m); 1323 return; /* XXX? */ 1324 } 1325 m = n; 1326 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1327 m, segs, &nseg, 0); 1328 } 1329 if (error != 0 || nseg == 0) { 1330 if_printf(ifp, "%s: error %u nseg %u\n", 1331 __func__, error, nseg); 1332 m_freem(m); 1333 return; /* XXX? */ 1334 } 1335 sc->tx_free = npe->ix_next; 1336 1337 bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREWRITE); 1338 1339 /* 1340 * Tap off here if there is a bpf listener. 1341 */ 1342 BPF_MTAP(ifp, m); 1343 1344 npe->ix_m = m; 1345 hw = npe->ix_hw; 1346 len = m->m_pkthdr.len; 1347 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1348 for (i = 0; i < nseg; i++) { 1349 hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1350 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1351 hw->ix_ne[i].next = htobe32(next); 1352 1353 len = 0; /* zero for segments > 1 */ 1354 next += sizeof(hw->ix_ne[0]); 1355 } 1356 hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1357 /* XXX flush descriptor instead of using uncached memory */ 1358 1359 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1360 __func__, sc->tx_qid, npe->ix_neaddr, 1361 hw->ix_ne[0].data, hw->ix_ne[0].len); 1362 /* stick it on the tx q */ 1363 /* XXX add vlan priority */ 1364 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1365 1366 sc->npe_watchdog_timer = 5; 1367 } 1368 if (sc->tx_free == NULL) 1369 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1370} 1371 1372void 1373npestart(struct ifnet *ifp) 1374{ 1375 struct npe_softc *sc = ifp->if_softc; 1376 NPE_LOCK(sc); 1377 npestart_locked(ifp); 1378 NPE_UNLOCK(sc); 1379} 1380 1381static void 1382npe_stopxmit(struct npe_softc *sc) 1383{ 1384 struct npedma *dma = &sc->txdma; 1385 int i; 1386 1387 NPE_ASSERT_LOCKED(sc); 1388 1389 /* XXX qmgr */ 1390 for (i = 0; i < dma->nbuf; i++) { 1391 struct npebuf *npe = &dma->buf[i]; 1392 1393 if (npe->ix_m != NULL) { 1394 bus_dmamap_unload(dma->mtag, npe->ix_map); 1395 m_freem(npe->ix_m); 1396 npe->ix_m = NULL; 1397 } 1398 } 1399} 1400 1401static void 1402npe_stoprecv(struct npe_softc *sc) 1403{ 1404 struct npedma *dma = &sc->rxdma; 1405 int i; 1406 1407 NPE_ASSERT_LOCKED(sc); 1408 1409 /* XXX qmgr */ 1410 for (i = 0; i < dma->nbuf; i++) { 1411 struct npebuf *npe = &dma->buf[i]; 1412 1413 if (npe->ix_m != NULL) { 1414 bus_dmamap_unload(dma->mtag, npe->ix_map); 1415 m_freem(npe->ix_m); 1416 npe->ix_m = NULL; 1417 } 1418 } 1419} 1420 1421/* 1422 * Turn off interrupts, and stop the nic. 1423 */ 1424void 1425npestop(struct npe_softc *sc) 1426{ 1427 struct ifnet *ifp = sc->sc_ifp; 1428 1429 /* disable transmitter and reciver in the MAC */ 1430 WR4(sc, NPE_MAC_RX_CNTRL1, 1431 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1432 WR4(sc, NPE_MAC_TX_CNTRL1, 1433 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1434 1435 sc->npe_watchdog_timer = 0; 1436 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1437 1438 callout_stop(&sc->tick_ch); 1439 1440 npe_stopxmit(sc); 1441 npe_stoprecv(sc); 1442 /* XXX go into loopback & drain q's? */ 1443 /* XXX but beware of disabling tx above */ 1444 1445 /* 1446 * The MAC core rx/tx disable may leave the MAC hardware in an 1447 * unpredictable state. A hw reset is executed before resetting 1448 * all the MAC parameters to a known value. 1449 */ 1450 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1451 DELAY(NPE_MAC_RESET_DELAY); 1452 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1453 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1454} 1455 1456void 1457npewatchdog(struct npe_softc *sc) 1458{ 1459 NPE_ASSERT_LOCKED(sc); 1460 1461 if (sc->npe_watchdog_timer == 0 || --sc->npe_watchdog_timer != 0) 1462 return; 1463 1464 device_printf(sc->sc_dev, "watchdog timeout\n"); 1465 sc->sc_ifp->if_oerrors++; 1466 1467 npeinit_locked(sc); 1468} 1469 1470static int 1471npeioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1472{ 1473 struct npe_softc *sc = ifp->if_softc; 1474 struct mii_data *mii; 1475 struct ifreq *ifr = (struct ifreq *)data; 1476 int error = 0; 1477#ifdef DEVICE_POLLING 1478 int mask; 1479#endif 1480 1481 switch (cmd) { 1482 case SIOCSIFFLAGS: 1483 NPE_LOCK(sc); 1484 if ((ifp->if_flags & IFF_UP) == 0 && 1485 ifp->if_drv_flags & IFF_DRV_RUNNING) { 1486 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1487 npestop(sc); 1488 } else { 1489 /* reinitialize card on any parameter change */ 1490 npeinit_locked(sc); 1491 } 1492 NPE_UNLOCK(sc); 1493 break; 1494 1495 case SIOCADDMULTI: 1496 case SIOCDELMULTI: 1497 /* update multicast filter list. */ 1498 NPE_LOCK(sc); 1499 npe_setmcast(sc); 1500 NPE_UNLOCK(sc); 1501 error = 0; 1502 break; 1503 1504 case SIOCSIFMEDIA: 1505 case SIOCGIFMEDIA: 1506 mii = device_get_softc(sc->sc_mii); 1507 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1508 break; 1509 1510#ifdef DEVICE_POLLING 1511 case SIOCSIFCAP: 1512 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1513 if (mask & IFCAP_POLLING) { 1514 if (ifr->ifr_reqcap & IFCAP_POLLING) { 1515 error = ether_poll_register(npe_poll, ifp); 1516 if (error) 1517 return error; 1518 NPE_LOCK(sc); 1519 /* disable callbacks XXX txdone is shared */ 1520 ixpqmgr_notify_disable(sc->rx_qid); 1521 ixpqmgr_notify_disable(sc->tx_doneqid); 1522 ifp->if_capenable |= IFCAP_POLLING; 1523 NPE_UNLOCK(sc); 1524 } else { 1525 error = ether_poll_deregister(ifp); 1526 /* NB: always enable qmgr callbacks */ 1527 NPE_LOCK(sc); 1528 /* enable qmgr callbacks */ 1529 ixpqmgr_notify_enable(sc->rx_qid, 1530 IX_QMGR_Q_SOURCE_ID_NOT_E); 1531 ixpqmgr_notify_enable(sc->tx_doneqid, 1532 IX_QMGR_Q_SOURCE_ID_NOT_E); 1533 ifp->if_capenable &= ~IFCAP_POLLING; 1534 NPE_UNLOCK(sc); 1535 } 1536 } 1537 break; 1538#endif 1539 default: 1540 error = ether_ioctl(ifp, cmd, data); 1541 break; 1542 } 1543 return error; 1544} 1545 1546/* 1547 * Setup a traffic class -> rx queue mapping. 1548 */ 1549static int 1550npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1551{ 1552 uint32_t msg[2]; 1553 1554 msg[0] = (NPE_SETRXQOSENTRY << 24) | (sc->sc_npeid << 20) | classix; 1555 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1556 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1557} 1558 1559static int 1560npe_setportaddress(struct npe_softc *sc, const uint8_t mac[ETHER_ADDR_LEN]) 1561{ 1562 uint32_t msg[2]; 1563 1564 msg[0] = (NPE_SETPORTADDRESS << 24) 1565 | (sc->sc_npeid << 20) 1566 | (mac[0] << 8) 1567 | (mac[1] << 0); 1568 msg[1] = (mac[2] << 24) 1569 | (mac[3] << 16) 1570 | (mac[4] << 8) 1571 | (mac[5] << 0); 1572 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1573} 1574 1575static int 1576npe_setfirewallmode(struct npe_softc *sc, int onoff) 1577{ 1578 uint32_t msg[2]; 1579 1580 /* XXX honor onoff */ 1581 msg[0] = (NPE_SETFIREWALLMODE << 24) | (sc->sc_npeid << 20); 1582 msg[1] = 0; 1583 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1584} 1585 1586/* 1587 * Update and reset the statistics in the NPE. 1588 */ 1589static int 1590npe_updatestats(struct npe_softc *sc) 1591{ 1592 uint32_t msg[2]; 1593 1594 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1595 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1596 return ixpnpe_sendmsg_async(sc->sc_npe, msg); 1597} 1598 1599#if 0 1600/* 1601 * Get the current statistics block. 1602 */ 1603static int 1604npe_getstats(struct npe_softc *sc) 1605{ 1606 uint32_t msg[2]; 1607 1608 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1609 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1610 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1611} 1612 1613/* 1614 * Query the image id of the loaded firmware. 1615 */ 1616static uint32_t 1617npe_getimageid(struct npe_softc *sc) 1618{ 1619 uint32_t msg[2]; 1620 1621 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1622 msg[1] = 0; 1623 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1624} 1625 1626/* 1627 * Enable/disable loopback. 1628 */ 1629static int 1630npe_setloopback(struct npe_softc *sc, int ena) 1631{ 1632 uint32_t msg[2]; 1633 1634 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1635 msg[1] = 0; 1636 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1637} 1638#endif 1639 1640static void 1641npe_child_detached(device_t dev, device_t child) 1642{ 1643 struct npe_softc *sc; 1644 1645 sc = device_get_softc(dev); 1646 if (child == sc->sc_mii) 1647 sc->sc_mii = NULL; 1648} 1649 1650/* 1651 * MII bus support routines. 1652 */ 1653#define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1654#define MII_WR4(sc, reg, v) \ 1655 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1656 1657static uint32_t 1658npe_mii_mdio_read(struct npe_softc *sc, int reg) 1659{ 1660 uint32_t v; 1661 1662 /* NB: registers are known to be sequential */ 1663 v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1664 v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1665 v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1666 v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1667 return v; 1668} 1669 1670static void 1671npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1672{ 1673 /* NB: registers are known to be sequential */ 1674 MII_WR4(sc, reg+0, cmd & 0xff); 1675 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1676 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1677 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1678} 1679 1680static int 1681npe_mii_mdio_wait(struct npe_softc *sc) 1682{ 1683 uint32_t v; 1684 int i; 1685 1686 /* NB: typically this takes 25-30 trips */ 1687 for (i = 0; i < 1000; i++) { 1688 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1689 if ((v & NPE_MII_GO) == 0) 1690 return 1; 1691 DELAY(1); 1692 } 1693 device_printf(sc->sc_dev, "%s: timeout after ~1ms, cmd 0x%x\n", 1694 __func__, v); 1695 return 0; /* NB: timeout */ 1696} 1697 1698static int 1699npe_miibus_readreg(device_t dev, int phy, int reg) 1700{ 1701 struct npe_softc *sc = device_get_softc(dev); 1702 uint32_t v; 1703 1704 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) | NPE_MII_GO; 1705 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1706 if (npe_mii_mdio_wait(sc)) 1707 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1708 else 1709 v = 0xffff | NPE_MII_READ_FAIL; 1710 return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1711} 1712 1713static int 1714npe_miibus_writereg(device_t dev, int phy, int reg, int data) 1715{ 1716 struct npe_softc *sc = device_get_softc(dev); 1717 uint32_t v; 1718 1719 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1720 | data | NPE_MII_WRITE 1721 | NPE_MII_GO; 1722 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1723 /* XXX complain about timeout */ 1724 (void) npe_mii_mdio_wait(sc); 1725 return (0); 1726} 1727 1728static void 1729npe_miibus_statchg(device_t dev) 1730{ 1731 struct npe_softc *sc = device_get_softc(dev); 1732 struct mii_data *mii = device_get_softc(sc->sc_mii); 1733 uint32_t tx1, rx1; 1734 1735 /* sync MAC duplex state */ 1736 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1737 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1738 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1739 tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1740 rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1741 } else { 1742 tx1 |= NPE_TX_CNTRL1_DUPLEX; 1743 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1744 } 1745 WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1746 WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1747} 1748 1749static device_method_t npe_methods[] = { 1750 /* Device interface */ 1751 DEVMETHOD(device_probe, npe_probe), 1752 DEVMETHOD(device_attach, npe_attach), 1753 DEVMETHOD(device_detach, npe_detach), 1754 1755 /* Bus interface */ 1756 DEVMETHOD(bus_child_detached, npe_child_detached), 1757 1758 /* MII interface */ 1759 DEVMETHOD(miibus_readreg, npe_miibus_readreg), 1760 DEVMETHOD(miibus_writereg, npe_miibus_writereg), 1761 DEVMETHOD(miibus_statchg, npe_miibus_statchg), 1762 1763 { 0, 0 } 1764}; 1765 1766static driver_t npe_driver = { 1767 "npe", 1768 npe_methods, 1769 sizeof(struct npe_softc), 1770}; 1771 1772DRIVER_MODULE(npe, ixp, npe_driver, npe_devclass, 0, 0); 1773DRIVER_MODULE(miibus, npe, miibus_driver, miibus_devclass, 0, 0); 1774MODULE_DEPEND(npe, ixpqmgr, 1, 1, 1); 1775MODULE_DEPEND(npe, miibus, 1, 1, 1); 1776MODULE_DEPEND(npe, ether, 1, 1, 1); 1777