if_npe.c revision 194321
1164426Ssam/*- 2177505Ssam * Copyright (c) 2006-2008 Sam Leffler. All rights reserved. 3164426Ssam * 4164426Ssam * Redistribution and use in source and binary forms, with or without 5164426Ssam * modification, are permitted provided that the following conditions 6164426Ssam * are met: 7164426Ssam * 1. Redistributions of source code must retain the above copyright 8164426Ssam * notice, this list of conditions and the following disclaimer. 9164426Ssam * 2. Redistributions in binary form must reproduce the above copyright 10164426Ssam * notice, this list of conditions and the following disclaimer in the 11164426Ssam * documentation and/or other materials provided with the distribution. 12164426Ssam * 13164426Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14164426Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15164426Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16164426Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17164426Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18164426Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19164426Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20164426Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21164426Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22164426Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23164426Ssam */ 24164426Ssam 25164426Ssam#include <sys/cdefs.h> 26164426Ssam__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/if_npe.c 194321 2009-06-17 02:53:05Z sam $"); 27164426Ssam 28164426Ssam/* 29164426Ssam * Intel XScale NPE Ethernet driver. 30164426Ssam * 31164426Ssam * This driver handles the two ports present on the IXP425. 32164426Ssam * Packet processing is done by the Network Processing Engines 33164426Ssam * (NPE's) that work together with a MAC and PHY. The MAC 34164426Ssam * is also mapped to the XScale cpu; the PHY is accessed via 35164426Ssam * the MAC. NPE-XScale communication happens through h/w 36164426Ssam * queues managed by the Q Manager block. 37164426Ssam * 38164426Ssam * The code here replaces the ethAcc, ethMii, and ethDB classes 39164426Ssam * in the Intel Access Library (IAL) and the OS-specific driver. 40164426Ssam * 41164426Ssam * XXX add vlan support 42164426Ssam */ 43164426Ssam#ifdef HAVE_KERNEL_OPTION_HEADERS 44164426Ssam#include "opt_device_polling.h" 45164426Ssam#endif 46164426Ssam 47164426Ssam#include <sys/param.h> 48164426Ssam#include <sys/systm.h> 49164426Ssam#include <sys/bus.h> 50164426Ssam#include <sys/kernel.h> 51164426Ssam#include <sys/mbuf.h> 52164426Ssam#include <sys/malloc.h> 53164426Ssam#include <sys/module.h> 54164426Ssam#include <sys/rman.h> 55164426Ssam#include <sys/socket.h> 56164426Ssam#include <sys/sockio.h> 57164426Ssam#include <sys/sysctl.h> 58164426Ssam#include <sys/endian.h> 59164426Ssam#include <machine/bus.h> 60164426Ssam 61164426Ssam#include <net/ethernet.h> 62164426Ssam#include <net/if.h> 63164426Ssam#include <net/if_arp.h> 64164426Ssam#include <net/if_dl.h> 65164426Ssam#include <net/if_media.h> 66164426Ssam#include <net/if_mib.h> 67164426Ssam#include <net/if_types.h> 68164426Ssam 69164426Ssam#ifdef INET 70164426Ssam#include <netinet/in.h> 71164426Ssam#include <netinet/in_systm.h> 72164426Ssam#include <netinet/in_var.h> 73164426Ssam#include <netinet/ip.h> 74164426Ssam#endif 75164426Ssam 76164426Ssam#include <net/bpf.h> 77164426Ssam#include <net/bpfdesc.h> 78164426Ssam 79164426Ssam#include <arm/xscale/ixp425/ixp425reg.h> 80164426Ssam#include <arm/xscale/ixp425/ixp425var.h> 81164426Ssam#include <arm/xscale/ixp425/ixp425_qmgr.h> 82164426Ssam#include <arm/xscale/ixp425/ixp425_npevar.h> 83164426Ssam 84164426Ssam#include <dev/mii/mii.h> 85164426Ssam#include <dev/mii/miivar.h> 86164426Ssam#include <arm/xscale/ixp425/if_npereg.h> 87164426Ssam 88186352Ssam#include <machine/armreg.h> 89186352Ssam 90164426Ssam#include "miibus_if.h" 91164426Ssam 92166064Scognet/* 93166064Scognet * XXX: For the main bus dma tag. Can go away if the new method to get the 94166064Scognet * dma tag from the parent got MFC'd into RELENG_6. 95166064Scognet */ 96166064Scognetextern struct ixp425_softc *ixp425_softc; 97166064Scognet 98164426Ssamstruct npebuf { 99164426Ssam struct npebuf *ix_next; /* chain to next buffer */ 100164426Ssam void *ix_m; /* backpointer to mbuf */ 101164426Ssam bus_dmamap_t ix_map; /* bus dma map for associated data */ 102164426Ssam struct npehwbuf *ix_hw; /* associated h/w block */ 103164426Ssam uint32_t ix_neaddr; /* phys address of ix_hw */ 104164426Ssam}; 105164426Ssam 106164426Ssamstruct npedma { 107164426Ssam const char* name; 108164426Ssam int nbuf; /* # npebuf's allocated */ 109164426Ssam bus_dma_tag_t mtag; /* bus dma tag for mbuf data */ 110164426Ssam struct npehwbuf *hwbuf; /* NPE h/w buffers */ 111164426Ssam bus_dma_tag_t buf_tag; /* tag+map for NPE buffers */ 112164426Ssam bus_dmamap_t buf_map; 113164426Ssam bus_addr_t buf_phys; /* phys addr of buffers */ 114164426Ssam struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 115164426Ssam}; 116164426Ssam 117164426Ssamstruct npe_softc { 118164426Ssam /* XXX mii requires this be first; do not move! */ 119164426Ssam struct ifnet *sc_ifp; /* ifnet pointer */ 120164426Ssam struct mtx sc_mtx; /* basically a perimeter lock */ 121164426Ssam device_t sc_dev; 122164426Ssam bus_space_tag_t sc_iot; 123164426Ssam bus_space_handle_t sc_ioh; /* MAC register window */ 124164426Ssam device_t sc_mii; /* child miibus */ 125164426Ssam bus_space_handle_t sc_miih; /* MII register window */ 126186352Ssam int sc_npeid; 127164426Ssam struct ixpnpe_softc *sc_npe; /* NPE support */ 128164426Ssam int sc_debug; /* DPRINTF* control */ 129164426Ssam int sc_tickinterval; 130164426Ssam struct callout tick_ch; /* Tick callout */ 131166339Skevlo int npe_watchdog_timer; 132164426Ssam struct npedma txdma; 133164426Ssam struct npebuf *tx_free; /* list of free tx buffers */ 134164426Ssam struct npedma rxdma; 135164426Ssam bus_addr_t buf_phys; /* XXX for returning a value */ 136164426Ssam int rx_qid; /* rx qid */ 137164426Ssam int rx_freeqid; /* rx free buffers qid */ 138164426Ssam int tx_qid; /* tx qid */ 139164426Ssam int tx_doneqid; /* tx completed qid */ 140177505Ssam int sc_phy; /* PHY id */ 141164426Ssam struct ifmib_iso_8802_3 mibdata; 142164426Ssam bus_dma_tag_t sc_stats_tag; /* bus dma tag for stats block */ 143164426Ssam struct npestats *sc_stats; 144164426Ssam bus_dmamap_t sc_stats_map; 145164426Ssam bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 146192660Ssam struct npestats sc_totals; /* accumulated sc_stats */ 147164426Ssam}; 148164426Ssam 149164426Ssam/* 150186352Ssam * Static configuration for IXP425. The tx and 151164426Ssam * rx free Q id's are fixed by the NPE microcode. The 152164426Ssam * rx Q id's are programmed to be separate to simplify 153164426Ssam * multi-port processing. It may be better to handle 154164426Ssam * all traffic through one Q (as done by the Intel drivers). 155164426Ssam * 156194321Ssam * Note that the PHY's are accessible only from MAC B on the 157194321Ssam * IXP425 and from MAC C on other devices. This and other 158194321Ssam * platform-specific assumptions are handled with hints. 159164426Ssam */ 160164426Ssamstatic const struct { 161186352Ssam uint32_t macbase; 162164426Ssam uint32_t miibase; 163177505Ssam int phy; /* phy id */ 164164426Ssam uint8_t rx_qid; 165164426Ssam uint8_t rx_freeqid; 166164426Ssam uint8_t tx_qid; 167164426Ssam uint8_t tx_doneqid; 168186352Ssam} npeconfig[NPE_MAX] = { 169186352Ssam [NPE_A] = { 170186352Ssam .macbase = IXP435_MAC_A_HWBASE, 171186352Ssam .miibase = IXP425_MAC_C_HWBASE, 172186352Ssam .phy = 2, 173186352Ssam .rx_qid = 4, 174186352Ssam .rx_freeqid = 26, 175186352Ssam .tx_qid = 23, 176186352Ssam .tx_doneqid = 31 177186352Ssam }, 178186352Ssam [NPE_B] = { 179186352Ssam .macbase = IXP425_MAC_B_HWBASE, 180194321Ssam .miibase = IXP425_MAC_B_HWBASE, 181177505Ssam .phy = 0, 182164426Ssam .rx_qid = 4, 183164426Ssam .rx_freeqid = 27, 184164426Ssam .tx_qid = 24, 185164426Ssam .tx_doneqid = 31 186164426Ssam }, 187186352Ssam [NPE_C] = { 188186352Ssam .macbase = IXP425_MAC_C_HWBASE, 189194321Ssam .miibase = IXP425_MAC_B_HWBASE, 190177505Ssam .phy = 1, 191164426Ssam .rx_qid = 12, 192164426Ssam .rx_freeqid = 28, 193164426Ssam .tx_qid = 25, 194164426Ssam .tx_doneqid = 31 195164426Ssam }, 196164426Ssam}; 197164426Ssamstatic struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 198164426Ssam 199164426Ssamstatic __inline uint32_t 200164426SsamRD4(struct npe_softc *sc, bus_size_t off) 201164426Ssam{ 202164426Ssam return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 203164426Ssam} 204164426Ssam 205164426Ssamstatic __inline void 206164426SsamWR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 207164426Ssam{ 208164426Ssam bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 209164426Ssam} 210164426Ssam 211164426Ssam#define NPE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 212164426Ssam#define NPE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 213164426Ssam#define NPE_LOCK_INIT(_sc) \ 214164426Ssam mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 215164426Ssam MTX_NETWORK_LOCK, MTX_DEF) 216164426Ssam#define NPE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 217164426Ssam#define NPE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 218164426Ssam#define NPE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 219164426Ssam 220164426Ssamstatic devclass_t npe_devclass; 221164426Ssam 222186352Ssamstatic int override_npeid(device_t, const char *resname, int *val); 223164426Ssamstatic int npe_activate(device_t dev); 224164426Ssamstatic void npe_deactivate(device_t dev); 225164426Ssamstatic int npe_ifmedia_update(struct ifnet *ifp); 226164426Ssamstatic void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 227164426Ssamstatic void npe_setmac(struct npe_softc *sc, u_char *eaddr); 228164426Ssamstatic void npe_getmac(struct npe_softc *sc, u_char *eaddr); 229164426Ssamstatic void npe_txdone(int qid, void *arg); 230164426Ssamstatic int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 231164426Ssam struct mbuf *); 232193096Sattiliostatic int npe_rxdone(int qid, void *arg); 233164426Ssamstatic void npeinit(void *); 234164426Ssamstatic void npestart_locked(struct ifnet *); 235164426Ssamstatic void npestart(struct ifnet *); 236164426Ssamstatic void npestop(struct npe_softc *); 237166339Skevlostatic void npewatchdog(struct npe_softc *); 238164426Ssamstatic int npeioctl(struct ifnet * ifp, u_long, caddr_t); 239164426Ssam 240164426Ssamstatic int npe_setrxqosentry(struct npe_softc *, int classix, 241164426Ssam int trafclass, int qid); 242194321Ssamstatic int npe_setportaddress(struct npe_softc *, const uint8_t mac[]); 243186352Ssamstatic int npe_setfirewallmode(struct npe_softc *, int onoff); 244164426Ssamstatic int npe_updatestats(struct npe_softc *); 245164426Ssam#if 0 246164426Ssamstatic int npe_getstats(struct npe_softc *); 247164426Ssamstatic uint32_t npe_getimageid(struct npe_softc *); 248164426Ssamstatic int npe_setloopback(struct npe_softc *, int ena); 249164426Ssam#endif 250164426Ssam 251164426Ssam/* NB: all tx done processing goes through one queue */ 252164426Ssamstatic int tx_doneqid = -1; 253164426Ssam 254186352SsamSYSCTL_NODE(_hw, OID_AUTO, npe, CTLFLAG_RD, 0, "IXP4XX NPE driver parameters"); 255164426Ssam 256164426Ssamstatic int npe_debug = 0; 257164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, debug, CTLFLAG_RW, &npe_debug, 258186352Ssam 0, "IXP4XX NPE network interface debug msgs"); 259186420SsamTUNABLE_INT("hw.npe.debug", &npe_debug); 260164426Ssam#define DPRINTF(sc, fmt, ...) do { \ 261164426Ssam if (sc->sc_debug) device_printf(sc->sc_dev, fmt, __VA_ARGS__); \ 262164426Ssam} while (0) 263164426Ssam#define DPRINTFn(n, sc, fmt, ...) do { \ 264164426Ssam if (sc->sc_debug >= n) device_printf(sc->sc_dev, fmt, __VA_ARGS__);\ 265164426Ssam} while (0) 266164426Ssamstatic int npe_tickinterval = 3; /* npe_tick frequency (secs) */ 267164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, tickinterval, CTLFLAG_RD, &npe_tickinterval, 268164426Ssam 0, "periodic work interval (secs)"); 269164426SsamTUNABLE_INT("hw.npe.tickinterval", &npe_tickinterval); 270164426Ssam 271164426Ssamstatic int npe_rxbuf = 64; /* # rx buffers to allocate */ 272164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, rxbuf, CTLFLAG_RD, &npe_rxbuf, 273164426Ssam 0, "rx buffers allocated"); 274164426SsamTUNABLE_INT("hw.npe.rxbuf", &npe_rxbuf); 275164426Ssamstatic int npe_txbuf = 128; /* # tx buffers to allocate */ 276164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, txbuf, CTLFLAG_RD, &npe_txbuf, 277164426Ssam 0, "tx buffers allocated"); 278164426SsamTUNABLE_INT("hw.npe.txbuf", &npe_txbuf); 279164426Ssam 280164426Ssamstatic int 281186352Ssamunit2npeid(int unit) 282186352Ssam{ 283186352Ssam static const int npeidmap[2][3] = { 284186352Ssam /* on 425 A is for HSS, B & C are for Ethernet */ 285186352Ssam { NPE_B, NPE_C, -1 }, /* IXP425 */ 286186352Ssam /* 435 only has A & C, order C then A */ 287186352Ssam { NPE_C, NPE_A, -1 }, /* IXP435 */ 288186352Ssam }; 289186352Ssam /* XXX check feature register instead */ 290186352Ssam return (unit < 3 ? npeidmap[ 291186352Ssam (cpu_id() & CPU_ID_CPU_MASK) == CPU_ID_IXP435][unit] : -1); 292186352Ssam} 293186352Ssam 294186352Ssamstatic int 295164426Ssamnpe_probe(device_t dev) 296164426Ssam{ 297186352Ssam static const char *desc[NPE_MAX] = { 298186352Ssam [NPE_A] = "IXP NPE-A", 299186352Ssam [NPE_B] = "IXP NPE-B", 300186352Ssam [NPE_C] = "IXP NPE-C" 301186352Ssam }; 302186420Ssam int unit = device_get_unit(dev); 303186352Ssam int npeid; 304164426Ssam 305186420Ssam if (unit > 2 || 306186420Ssam (ixp4xx_read_feature_bits() & 307186420Ssam (unit == 0 ? EXP_FCTRL_ETH0 : EXP_FCTRL_ETH1)) == 0) 308186420Ssam return EINVAL; 309186420Ssam 310186352Ssam npeid = -1; 311186352Ssam if (!override_npeid(dev, "npeid", &npeid)) 312186420Ssam npeid = unit2npeid(unit); 313186352Ssam if (npeid == -1) { 314186420Ssam device_printf(dev, "unit %d not supported\n", unit); 315164426Ssam return EINVAL; 316164426Ssam } 317186352Ssam device_set_desc(dev, desc[npeid]); 318164426Ssam return 0; 319164426Ssam} 320164426Ssam 321164426Ssamstatic int 322164426Ssamnpe_attach(device_t dev) 323164426Ssam{ 324164426Ssam struct npe_softc *sc = device_get_softc(dev); 325164426Ssam struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); 326164426Ssam struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 327164426Ssam struct sysctl_oid *tree = device_get_sysctl_tree(dev); 328186352Ssam struct ifnet *ifp; 329164426Ssam int error; 330164426Ssam u_char eaddr[6]; 331164426Ssam 332164426Ssam sc->sc_dev = dev; 333164426Ssam sc->sc_iot = sa->sc_iot; 334164426Ssam NPE_LOCK_INIT(sc); 335164426Ssam callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 336164426Ssam sc->sc_debug = npe_debug; 337164426Ssam sc->sc_tickinterval = npe_tickinterval; 338164426Ssam 339186352Ssam ifp = if_alloc(IFT_ETHER); 340186352Ssam if (ifp == NULL) { 341186352Ssam device_printf(dev, "cannot allocate ifnet\n"); 342164426Ssam error = EIO; /* XXX */ 343164426Ssam goto out; 344164426Ssam } 345186352Ssam /* NB: must be setup prior to invoking mii code */ 346186352Ssam sc->sc_ifp = ifp; 347164426Ssam 348164426Ssam error = npe_activate(dev); 349186352Ssam if (error) { 350186352Ssam device_printf(dev, "cannot activate npe\n"); 351164426Ssam goto out; 352186352Ssam } 353164426Ssam 354164426Ssam npe_getmac(sc, eaddr); 355164426Ssam 356164426Ssam ifp->if_softc = sc; 357164426Ssam if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 358164426Ssam ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 359164426Ssam ifp->if_start = npestart; 360164426Ssam ifp->if_ioctl = npeioctl; 361164426Ssam ifp->if_init = npeinit; 362164426Ssam IFQ_SET_MAXLEN(&ifp->if_snd, sc->txdma.nbuf - 1); 363166625Smlaier ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 364164426Ssam IFQ_SET_READY(&ifp->if_snd); 365164426Ssam ifp->if_linkmib = &sc->mibdata; 366164426Ssam ifp->if_linkmiblen = sizeof(sc->mibdata); 367164426Ssam sc->mibdata.dot3Compliance = DOT3COMPLIANCE_STATS; 368189645Ssam /* device supports oversided vlan frames */ 369189645Ssam ifp->if_capabilities |= IFCAP_VLAN_MTU; 370189645Ssam ifp->if_capenable = ifp->if_capabilities; 371164426Ssam#ifdef DEVICE_POLLING 372164426Ssam ifp->if_capabilities |= IFCAP_POLLING; 373164426Ssam#endif 374164426Ssam 375164426Ssam SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug", 376164426Ssam CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 377164426Ssam SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tickinterval", 378164426Ssam CTLFLAG_RW, &sc->sc_tickinterval, 0, "periodic work frequency"); 379192660Ssam SYSCTL_ADD_STRUCT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "stats", 380192660Ssam CTLFLAG_RD, &sc->sc_totals, npestats, "onboard stats"); 381164426Ssam 382164426Ssam ether_ifattach(ifp, eaddr); 383164426Ssam return 0; 384164426Ssamout: 385164426Ssam if (ifp != NULL) 386164426Ssam if_free(ifp); 387186352Ssam NPE_LOCK_DESTROY(sc); 388186352Ssam npe_deactivate(dev); 389164426Ssam return error; 390164426Ssam} 391164426Ssam 392164426Ssamstatic int 393164426Ssamnpe_detach(device_t dev) 394164426Ssam{ 395164426Ssam struct npe_softc *sc = device_get_softc(dev); 396164426Ssam struct ifnet *ifp = sc->sc_ifp; 397164426Ssam 398164426Ssam#ifdef DEVICE_POLLING 399164426Ssam if (ifp->if_capenable & IFCAP_POLLING) 400164426Ssam ether_poll_deregister(ifp); 401164426Ssam#endif 402164426Ssam npestop(sc); 403164426Ssam if (ifp != NULL) { 404164426Ssam ether_ifdetach(ifp); 405164426Ssam if_free(ifp); 406164426Ssam } 407164426Ssam NPE_LOCK_DESTROY(sc); 408164426Ssam npe_deactivate(dev); 409164426Ssam return 0; 410164426Ssam} 411164426Ssam 412164426Ssam/* 413164426Ssam * Compute and install the multicast filter. 414164426Ssam */ 415164426Ssamstatic void 416164426Ssamnpe_setmcast(struct npe_softc *sc) 417164426Ssam{ 418164426Ssam struct ifnet *ifp = sc->sc_ifp; 419164426Ssam uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 420164426Ssam int i; 421164426Ssam 422164426Ssam if (ifp->if_flags & IFF_PROMISC) { 423164426Ssam memset(mask, 0, ETHER_ADDR_LEN); 424164426Ssam memset(addr, 0, ETHER_ADDR_LEN); 425164426Ssam } else if (ifp->if_flags & IFF_ALLMULTI) { 426164426Ssam static const uint8_t allmulti[ETHER_ADDR_LEN] = 427164426Ssam { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 428164426Ssam memcpy(mask, allmulti, ETHER_ADDR_LEN); 429164426Ssam memcpy(addr, allmulti, ETHER_ADDR_LEN); 430164426Ssam } else { 431164426Ssam uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 432164426Ssam struct ifmultiaddr *ifma; 433164426Ssam const uint8_t *mac; 434164426Ssam 435164426Ssam memset(clr, 0, ETHER_ADDR_LEN); 436164426Ssam memset(set, 0xff, ETHER_ADDR_LEN); 437164426Ssam 438164426Ssam IF_ADDR_LOCK(ifp); 439164426Ssam TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 440164426Ssam if (ifma->ifma_addr->sa_family != AF_LINK) 441164426Ssam continue; 442164426Ssam mac = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 443164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 444164426Ssam clr[i] |= mac[i]; 445164426Ssam set[i] &= mac[i]; 446164426Ssam } 447164426Ssam } 448164426Ssam IF_ADDR_UNLOCK(ifp); 449164426Ssam 450164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 451164426Ssam mask[i] = set[i] | ~clr[i]; 452164426Ssam addr[i] = set[i]; 453164426Ssam } 454164426Ssam } 455164426Ssam 456164426Ssam /* 457164426Ssam * Write the mask and address registers. 458164426Ssam */ 459164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 460164426Ssam WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 461164426Ssam WR4(sc, NPE_MAC_ADDR(i), addr[i]); 462164426Ssam } 463164426Ssam} 464164426Ssam 465164426Ssamstatic void 466164426Ssamnpe_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 467164426Ssam{ 468164426Ssam struct npe_softc *sc; 469164426Ssam 470164426Ssam if (error != 0) 471164426Ssam return; 472164426Ssam sc = (struct npe_softc *)arg; 473164426Ssam sc->buf_phys = segs[0].ds_addr; 474164426Ssam} 475164426Ssam 476164426Ssamstatic int 477164426Ssamnpe_dma_setup(struct npe_softc *sc, struct npedma *dma, 478164426Ssam const char *name, int nbuf, int maxseg) 479164426Ssam{ 480164426Ssam int error, i; 481164426Ssam 482183886Ssam memset(dma, 0, sizeof(*dma)); 483164426Ssam 484164426Ssam dma->name = name; 485164426Ssam dma->nbuf = nbuf; 486164426Ssam 487164426Ssam /* DMA tag for mapped mbufs */ 488166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, 1, 0, 489164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 490164426Ssam MCLBYTES, maxseg, MCLBYTES, 0, 491164426Ssam busdma_lock_mutex, &sc->sc_mtx, &dma->mtag); 492164426Ssam if (error != 0) { 493164426Ssam device_printf(sc->sc_dev, "unable to create %s mbuf dma tag, " 494164426Ssam "error %u\n", dma->name, error); 495164426Ssam return error; 496164426Ssam } 497164426Ssam 498164426Ssam /* DMA tag and map for the NPE buffers */ 499166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 500164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 501164426Ssam nbuf * sizeof(struct npehwbuf), 1, 502164426Ssam nbuf * sizeof(struct npehwbuf), 0, 503164426Ssam busdma_lock_mutex, &sc->sc_mtx, &dma->buf_tag); 504164426Ssam if (error != 0) { 505164426Ssam device_printf(sc->sc_dev, 506164426Ssam "unable to create %s npebuf dma tag, error %u\n", 507164426Ssam dma->name, error); 508164426Ssam return error; 509164426Ssam } 510164426Ssam /* XXX COHERENT for now */ 511164426Ssam if (bus_dmamem_alloc(dma->buf_tag, (void **)&dma->hwbuf, 512164426Ssam BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 513164426Ssam &dma->buf_map) != 0) { 514164426Ssam device_printf(sc->sc_dev, 515164426Ssam "unable to allocate memory for %s h/w buffers, error %u\n", 516164426Ssam dma->name, error); 517164426Ssam return error; 518164426Ssam } 519164426Ssam /* XXX M_TEMP */ 520164426Ssam dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 521164426Ssam if (dma->buf == NULL) { 522164426Ssam device_printf(sc->sc_dev, 523164426Ssam "unable to allocate memory for %s s/w buffers\n", 524164426Ssam dma->name); 525164426Ssam return error; 526164426Ssam } 527164426Ssam if (bus_dmamap_load(dma->buf_tag, dma->buf_map, 528164426Ssam dma->hwbuf, nbuf*sizeof(struct npehwbuf), npe_getaddr, sc, 0) != 0) { 529164426Ssam device_printf(sc->sc_dev, 530164426Ssam "unable to map memory for %s h/w buffers, error %u\n", 531164426Ssam dma->name, error); 532164426Ssam return error; 533164426Ssam } 534164426Ssam dma->buf_phys = sc->buf_phys; 535164426Ssam for (i = 0; i < dma->nbuf; i++) { 536164426Ssam struct npebuf *npe = &dma->buf[i]; 537164426Ssam struct npehwbuf *hw = &dma->hwbuf[i]; 538164426Ssam 539164426Ssam /* calculate offset to shared area */ 540164426Ssam npe->ix_neaddr = dma->buf_phys + 541164426Ssam ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 542164426Ssam KASSERT((npe->ix_neaddr & 0x1f) == 0, 543164426Ssam ("ixpbuf misaligned, PA 0x%x", npe->ix_neaddr)); 544164426Ssam error = bus_dmamap_create(dma->mtag, BUS_DMA_NOWAIT, 545164426Ssam &npe->ix_map); 546164426Ssam if (error != 0) { 547164426Ssam device_printf(sc->sc_dev, 548164426Ssam "unable to create dmamap for %s buffer %u, " 549164426Ssam "error %u\n", dma->name, i, error); 550164426Ssam return error; 551164426Ssam } 552164426Ssam npe->ix_hw = hw; 553164426Ssam } 554164426Ssam bus_dmamap_sync(dma->buf_tag, dma->buf_map, BUS_DMASYNC_PREWRITE); 555164426Ssam return 0; 556164426Ssam} 557164426Ssam 558164426Ssamstatic void 559164426Ssamnpe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 560164426Ssam{ 561164426Ssam int i; 562164426Ssam 563164426Ssam if (dma->hwbuf != NULL) { 564164426Ssam for (i = 0; i < dma->nbuf; i++) { 565164426Ssam struct npebuf *npe = &dma->buf[i]; 566164426Ssam bus_dmamap_destroy(dma->mtag, npe->ix_map); 567164426Ssam } 568164426Ssam bus_dmamap_unload(dma->buf_tag, dma->buf_map); 569164426Ssam bus_dmamem_free(dma->buf_tag, dma->hwbuf, dma->buf_map); 570164426Ssam } 571164426Ssam if (dma->buf != NULL) 572164426Ssam free(dma->buf, M_TEMP); 573164426Ssam if (dma->buf_tag) 574164426Ssam bus_dma_tag_destroy(dma->buf_tag); 575164426Ssam if (dma->mtag) 576164426Ssam bus_dma_tag_destroy(dma->mtag); 577164426Ssam memset(dma, 0, sizeof(*dma)); 578164426Ssam} 579164426Ssam 580164426Ssamstatic int 581186352Ssamoverride_addr(device_t dev, const char *resname, int *base) 582177505Ssam{ 583177505Ssam int unit = device_get_unit(dev); 584177505Ssam const char *resval; 585177505Ssam 586177505Ssam /* XXX warn for wrong hint type */ 587177505Ssam if (resource_string_value("npe", unit, resname, &resval) != 0) 588177505Ssam return 0; 589177505Ssam switch (resval[0]) { 590177505Ssam case 'A': 591186352Ssam *base = IXP435_MAC_A_HWBASE; 592177505Ssam break; 593177505Ssam case 'B': 594177505Ssam *base = IXP425_MAC_B_HWBASE; 595177505Ssam break; 596186352Ssam case 'C': 597186352Ssam *base = IXP425_MAC_C_HWBASE; 598186352Ssam break; 599177505Ssam default: 600177505Ssam device_printf(dev, "Warning, bad value %s for " 601177505Ssam "npe.%d.%s ignored\n", resval, unit, resname); 602177505Ssam return 0; 603177505Ssam } 604177505Ssam if (bootverbose) 605177505Ssam device_printf(dev, "using npe.%d.%s=%s override\n", 606177505Ssam unit, resname, resval); 607177505Ssam return 1; 608177505Ssam} 609177505Ssam 610177505Ssamstatic int 611186352Ssamoverride_npeid(device_t dev, const char *resname, int *npeid) 612186352Ssam{ 613186352Ssam int unit = device_get_unit(dev); 614186352Ssam const char *resval; 615186352Ssam 616186352Ssam /* XXX warn for wrong hint type */ 617186352Ssam if (resource_string_value("npe", unit, resname, &resval) != 0) 618186352Ssam return 0; 619186352Ssam switch (resval[0]) { 620186352Ssam case 'A': *npeid = NPE_A; break; 621186352Ssam case 'B': *npeid = NPE_B; break; 622186352Ssam case 'C': *npeid = NPE_C; break; 623186352Ssam default: 624186352Ssam device_printf(dev, "Warning, bad value %s for " 625186352Ssam "npe.%d.%s ignored\n", resval, unit, resname); 626186352Ssam return 0; 627186352Ssam } 628186352Ssam if (bootverbose) 629186352Ssam device_printf(dev, "using npe.%d.%s=%s override\n", 630186352Ssam unit, resname, resval); 631186352Ssam return 1; 632186352Ssam} 633186352Ssam 634186352Ssamstatic int 635177505Ssamoverride_unit(device_t dev, const char *resname, int *val, int min, int max) 636177505Ssam{ 637177505Ssam int unit = device_get_unit(dev); 638177505Ssam int resval; 639177505Ssam 640177505Ssam if (resource_int_value("npe", unit, resname, &resval) != 0) 641177505Ssam return 0; 642177505Ssam if (!(min <= resval && resval <= max)) { 643177505Ssam device_printf(dev, "Warning, bad value %d for npe.%d.%s " 644177505Ssam "ignored (value must be [%d-%d])\n", resval, unit, 645177505Ssam resname, min, max); 646177505Ssam return 0; 647177505Ssam } 648177505Ssam if (bootverbose) 649177505Ssam device_printf(dev, "using npe.%d.%s=%d override\n", 650177505Ssam unit, resname, resval); 651177505Ssam *val = resval; 652177505Ssam return 1; 653177505Ssam} 654177505Ssam 655186352Ssamstatic void 656186352Ssamnpe_mac_reset(struct npe_softc *sc) 657186352Ssam{ 658186352Ssam /* 659186352Ssam * Reset MAC core. 660186352Ssam */ 661186352Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 662186352Ssam DELAY(NPE_MAC_RESET_DELAY); 663186352Ssam /* configure MAC to generate MDC clock */ 664186352Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 665186352Ssam} 666186352Ssam 667186352Ssamstatic int 668164426Ssamnpe_activate(device_t dev) 669164426Ssam{ 670194321Ssam struct npe_softc *sc = device_get_softc(dev); 671186352Ssam int error, i, macbase, miibase; 672164426Ssam 673169954Ssam /* 674186352Ssam * Setup NEP ID, MAC, and MII bindings. We allow override 675186352Ssam * via hints to handle unexpected board configs. 676186352Ssam */ 677186352Ssam if (!override_npeid(dev, "npeid", &sc->sc_npeid)) 678186352Ssam sc->sc_npeid = unit2npeid(device_get_unit(dev)); 679186352Ssam sc->sc_npe = ixpnpe_attach(dev, sc->sc_npeid); 680186352Ssam if (sc->sc_npe == NULL) { 681186352Ssam device_printf(dev, "cannot attach ixpnpe\n"); 682186352Ssam return EIO; /* XXX */ 683186352Ssam } 684186352Ssam 685186352Ssam /* MAC */ 686186352Ssam if (!override_addr(dev, "mac", &macbase)) 687186352Ssam macbase = npeconfig[sc->sc_npeid].macbase; 688186352Ssam device_printf(sc->sc_dev, "MAC at 0x%x\n", macbase); 689186352Ssam if (bus_space_map(sc->sc_iot, macbase, IXP425_REG_SIZE, 0, &sc->sc_ioh)) { 690186352Ssam device_printf(dev, "cannot map mac registers 0x%x:0x%x\n", 691186352Ssam macbase, IXP425_REG_SIZE); 692186352Ssam return ENOMEM; 693186352Ssam } 694186352Ssam 695186352Ssam /* PHY */ 696186352Ssam if (!override_unit(dev, "phy", &sc->sc_phy, 0, MII_NPHY-1)) 697186352Ssam sc->sc_phy = npeconfig[sc->sc_npeid].phy; 698186352Ssam if (!override_addr(dev, "mii", &miibase)) 699186352Ssam miibase = npeconfig[sc->sc_npeid].miibase; 700186352Ssam device_printf(sc->sc_dev, "MII at 0x%x\n", miibase); 701186352Ssam if (miibase != macbase) { 702186352Ssam /* 703186352Ssam * PHY is mapped through a different MAC, setup an 704186352Ssam * additional mapping for frobbing the PHY registers. 705186352Ssam */ 706186352Ssam if (bus_space_map(sc->sc_iot, miibase, IXP425_REG_SIZE, 0, &sc->sc_miih)) { 707186352Ssam device_printf(dev, 708186352Ssam "cannot map MII registers 0x%x:0x%x\n", 709186352Ssam miibase, IXP425_REG_SIZE); 710186352Ssam return ENOMEM; 711186352Ssam } 712186352Ssam } else 713186352Ssam sc->sc_miih = sc->sc_ioh; 714186352Ssam 715186352Ssam /* 716186420Ssam * Load NPE firmware and start it running. 717169954Ssam */ 718186420Ssam error = ixpnpe_init(sc->sc_npe); 719186420Ssam if (error != 0) { 720186420Ssam device_printf(dev, "cannot init NPE (error %d)\n", error); 721186420Ssam return error; 722169954Ssam } 723164426Ssam 724186352Ssam /* probe for PHY */ 725186352Ssam if (mii_phy_probe(dev, &sc->sc_mii, npe_ifmedia_update, npe_ifmedia_status)) { 726186352Ssam device_printf(dev, "cannot find PHY %d.\n", sc->sc_phy); 727186352Ssam return ENXIO; 728177505Ssam } 729164426Ssam 730164426Ssam error = npe_dma_setup(sc, &sc->txdma, "tx", npe_txbuf, NPE_MAXSEG); 731164426Ssam if (error != 0) 732164426Ssam return error; 733164426Ssam error = npe_dma_setup(sc, &sc->rxdma, "rx", npe_rxbuf, 1); 734164426Ssam if (error != 0) 735164426Ssam return error; 736164426Ssam 737164426Ssam /* setup statistics block */ 738166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 739164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 740164426Ssam sizeof(struct npestats), 1, sizeof(struct npestats), 0, 741164426Ssam busdma_lock_mutex, &sc->sc_mtx, &sc->sc_stats_tag); 742164426Ssam if (error != 0) { 743164426Ssam device_printf(sc->sc_dev, "unable to create stats tag, " 744164426Ssam "error %u\n", error); 745164426Ssam return error; 746164426Ssam } 747164426Ssam if (bus_dmamem_alloc(sc->sc_stats_tag, (void **)&sc->sc_stats, 748164426Ssam BUS_DMA_NOWAIT, &sc->sc_stats_map) != 0) { 749164426Ssam device_printf(sc->sc_dev, 750164426Ssam "unable to allocate memory for stats block, error %u\n", 751164426Ssam error); 752164426Ssam return error; 753164426Ssam } 754164426Ssam if (bus_dmamap_load(sc->sc_stats_tag, sc->sc_stats_map, 755164426Ssam sc->sc_stats, sizeof(struct npestats), npe_getaddr, sc, 0) != 0) { 756164426Ssam device_printf(sc->sc_dev, 757164426Ssam "unable to load memory for stats block, error %u\n", 758164426Ssam error); 759164426Ssam return error; 760164426Ssam } 761164426Ssam sc->sc_stats_phys = sc->buf_phys; 762164426Ssam 763164426Ssam /* 764164426Ssam * Setup h/w rx/tx queues. There are four q's: 765164426Ssam * rx inbound q of rx'd frames 766164426Ssam * rx_free pool of ixpbuf's for receiving frames 767164426Ssam * tx outbound q of frames to send 768164426Ssam * tx_done q of tx frames that have been processed 769164426Ssam * 770164426Ssam * The NPE handles the actual tx/rx process and the q manager 771164426Ssam * handles the queues. The driver just writes entries to the 772164426Ssam * q manager mailbox's and gets callbacks when there are rx'd 773164426Ssam * frames to process or tx'd frames to reap. These callbacks 774164426Ssam * are controlled by the q configurations; e.g. we get a 775164426Ssam * callback when tx_done has 2 or more frames to process and 776164426Ssam * when the rx q has at least one frame. These setings can 777164426Ssam * changed at the time the q is configured. 778164426Ssam */ 779186352Ssam sc->rx_qid = npeconfig[sc->sc_npeid].rx_qid; 780164426Ssam ixpqmgr_qconfig(sc->rx_qid, npe_rxbuf, 0, 1, 781193096Sattilio IX_QMGR_Q_SOURCE_ID_NOT_E, (qconfig_hand_t *)npe_rxdone, sc); 782186352Ssam sc->rx_freeqid = npeconfig[sc->sc_npeid].rx_freeqid; 783164426Ssam ixpqmgr_qconfig(sc->rx_freeqid, npe_rxbuf, 0, npe_rxbuf/2, 0, NULL, sc); 784186352Ssam /* 785186352Ssam * Setup the NPE to direct all traffic to rx_qid. 786186352Ssam * When QoS is enabled in the firmware there are 787186352Ssam * 8 traffic classes; otherwise just 4. 788186352Ssam */ 789164426Ssam for (i = 0; i < 8; i++) 790164426Ssam npe_setrxqosentry(sc, i, 0, sc->rx_qid); 791164426Ssam 792186352Ssam /* disable firewall mode just in case (should be off) */ 793186352Ssam npe_setfirewallmode(sc, 0); 794186352Ssam 795186352Ssam sc->tx_qid = npeconfig[sc->sc_npeid].tx_qid; 796186352Ssam sc->tx_doneqid = npeconfig[sc->sc_npeid].tx_doneqid; 797164426Ssam ixpqmgr_qconfig(sc->tx_qid, npe_txbuf, 0, npe_txbuf, 0, NULL, sc); 798164426Ssam if (tx_doneqid == -1) { 799164426Ssam ixpqmgr_qconfig(sc->tx_doneqid, npe_txbuf, 0, 2, 800164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 801164426Ssam tx_doneqid = sc->tx_doneqid; 802164426Ssam } 803164426Ssam 804186352Ssam KASSERT(npes[sc->sc_npeid] == NULL, 805186352Ssam ("npe %u already setup", sc->sc_npeid)); 806186352Ssam npes[sc->sc_npeid] = sc; 807177505Ssam 808164426Ssam return 0; 809164426Ssam} 810164426Ssam 811164426Ssamstatic void 812164426Ssamnpe_deactivate(device_t dev) 813164426Ssam{ 814164426Ssam struct npe_softc *sc = device_get_softc(dev); 815164426Ssam 816186352Ssam npes[sc->sc_npeid] = NULL; 817164426Ssam 818164426Ssam /* XXX disable q's */ 819186352Ssam if (sc->sc_npe != NULL) { 820164426Ssam ixpnpe_stop(sc->sc_npe); 821186352Ssam ixpnpe_detach(sc->sc_npe); 822186352Ssam } 823164426Ssam if (sc->sc_stats != NULL) { 824164426Ssam bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 825164426Ssam bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 826164426Ssam sc->sc_stats_map); 827164426Ssam } 828164426Ssam if (sc->sc_stats_tag != NULL) 829164426Ssam bus_dma_tag_destroy(sc->sc_stats_tag); 830164426Ssam npe_dma_destroy(sc, &sc->txdma); 831164426Ssam npe_dma_destroy(sc, &sc->rxdma); 832164426Ssam bus_generic_detach(sc->sc_dev); 833186352Ssam if (sc->sc_mii != NULL) 834164426Ssam device_delete_child(sc->sc_dev, sc->sc_mii); 835164426Ssam} 836164426Ssam 837164426Ssam/* 838164426Ssam * Change media according to request. 839164426Ssam */ 840164426Ssamstatic int 841164426Ssamnpe_ifmedia_update(struct ifnet *ifp) 842164426Ssam{ 843164426Ssam struct npe_softc *sc = ifp->if_softc; 844164426Ssam struct mii_data *mii; 845164426Ssam 846164426Ssam mii = device_get_softc(sc->sc_mii); 847164426Ssam NPE_LOCK(sc); 848164426Ssam mii_mediachg(mii); 849164426Ssam /* XXX push state ourself? */ 850164426Ssam NPE_UNLOCK(sc); 851164426Ssam return (0); 852164426Ssam} 853164426Ssam 854164426Ssam/* 855164426Ssam * Notify the world which media we're using. 856164426Ssam */ 857164426Ssamstatic void 858164426Ssamnpe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 859164426Ssam{ 860164426Ssam struct npe_softc *sc = ifp->if_softc; 861164426Ssam struct mii_data *mii; 862164426Ssam 863164426Ssam mii = device_get_softc(sc->sc_mii); 864164426Ssam NPE_LOCK(sc); 865164426Ssam mii_pollstat(mii); 866164426Ssam ifmr->ifm_active = mii->mii_media_active; 867164426Ssam ifmr->ifm_status = mii->mii_media_status; 868164426Ssam NPE_UNLOCK(sc); 869164426Ssam} 870164426Ssam 871164426Ssamstatic void 872164426Ssamnpe_addstats(struct npe_softc *sc) 873164426Ssam{ 874192660Ssam#define NPEADD(x) sc->sc_totals.x += be32toh(ns->x) 875192660Ssam#define MIBADD(x) do { sc->mibdata.x += be32toh(ns->x); NPEADD(x); } while (0) 876164426Ssam struct ifnet *ifp = sc->sc_ifp; 877164426Ssam struct npestats *ns = sc->sc_stats; 878164426Ssam 879164426Ssam MIBADD(dot3StatsAlignmentErrors); 880164426Ssam MIBADD(dot3StatsFCSErrors); 881192660Ssam MIBADD(dot3StatsInternalMacReceiveErrors); 882192660Ssam NPEADD(RxOverrunDiscards); 883192660Ssam NPEADD(RxLearnedEntryDiscards); 884192660Ssam NPEADD(RxLargeFramesDiscards); 885192660Ssam NPEADD(RxSTPBlockedDiscards); 886192660Ssam NPEADD(RxVLANTypeFilterDiscards); 887192660Ssam NPEADD(RxVLANIdFilterDiscards); 888192660Ssam NPEADD(RxInvalidSourceDiscards); 889192660Ssam NPEADD(RxBlackListDiscards); 890192660Ssam NPEADD(RxWhiteListDiscards); 891192660Ssam NPEADD(RxUnderflowEntryDiscards); 892164426Ssam MIBADD(dot3StatsSingleCollisionFrames); 893164426Ssam MIBADD(dot3StatsMultipleCollisionFrames); 894164426Ssam MIBADD(dot3StatsDeferredTransmissions); 895164426Ssam MIBADD(dot3StatsLateCollisions); 896164426Ssam MIBADD(dot3StatsExcessiveCollisions); 897164426Ssam MIBADD(dot3StatsInternalMacTransmitErrors); 898164426Ssam MIBADD(dot3StatsCarrierSenseErrors); 899192660Ssam NPEADD(TxLargeFrameDiscards); 900192660Ssam NPEADD(TxVLANIdFilterDiscards); 901192660Ssam 902164426Ssam sc->mibdata.dot3StatsFrameTooLongs += 903164426Ssam be32toh(ns->RxLargeFramesDiscards) 904164426Ssam + be32toh(ns->TxLargeFrameDiscards); 905164426Ssam sc->mibdata.dot3StatsMissedFrames += 906164426Ssam be32toh(ns->RxOverrunDiscards) 907164426Ssam + be32toh(ns->RxUnderflowEntryDiscards); 908164426Ssam 909164426Ssam ifp->if_oerrors += 910164426Ssam be32toh(ns->dot3StatsInternalMacTransmitErrors) 911164426Ssam + be32toh(ns->dot3StatsCarrierSenseErrors) 912164426Ssam + be32toh(ns->TxVLANIdFilterDiscards) 913164426Ssam ; 914164426Ssam ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 915164426Ssam + be32toh(ns->dot3StatsInternalMacReceiveErrors) 916164426Ssam + be32toh(ns->RxOverrunDiscards) 917164426Ssam + be32toh(ns->RxUnderflowEntryDiscards) 918164426Ssam ; 919164426Ssam ifp->if_collisions += 920164426Ssam be32toh(ns->dot3StatsSingleCollisionFrames) 921164426Ssam + be32toh(ns->dot3StatsMultipleCollisionFrames) 922164426Ssam ; 923192660Ssam#undef NPEADD 924164426Ssam#undef MIBADD 925164426Ssam} 926164426Ssam 927164426Ssamstatic void 928164426Ssamnpe_tick(void *xsc) 929164426Ssam{ 930164426Ssam#define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 931164426Ssam struct npe_softc *sc = xsc; 932164426Ssam struct mii_data *mii = device_get_softc(sc->sc_mii); 933164426Ssam uint32_t msg[2]; 934164426Ssam 935164426Ssam NPE_ASSERT_LOCKED(sc); 936164426Ssam 937164426Ssam /* 938164426Ssam * NB: to avoid sleeping with the softc lock held we 939164426Ssam * split the NPE msg processing into two parts. The 940164426Ssam * request for statistics is sent w/o waiting for a 941164426Ssam * reply and then on the next tick we retrieve the 942164426Ssam * results. This works because npe_tick is the only 943164426Ssam * code that talks via the mailbox's (except at setup). 944164426Ssam * This likely can be handled better. 945164426Ssam */ 946186352Ssam if (ixpnpe_recvmsg_async(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 947164426Ssam bus_dmamap_sync(sc->sc_stats_tag, sc->sc_stats_map, 948164426Ssam BUS_DMASYNC_POSTREAD); 949164426Ssam npe_addstats(sc); 950164426Ssam } 951164426Ssam npe_updatestats(sc); 952164426Ssam mii_tick(mii); 953164426Ssam 954166339Skevlo npewatchdog(sc); 955166339Skevlo 956164426Ssam /* schedule next poll */ 957164426Ssam callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 958164426Ssam#undef ACK 959164426Ssam} 960164426Ssam 961164426Ssamstatic void 962164426Ssamnpe_setmac(struct npe_softc *sc, u_char *eaddr) 963164426Ssam{ 964164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 965164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 966164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 967164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 968164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 969164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 970164426Ssam} 971164426Ssam 972164426Ssamstatic void 973164426Ssamnpe_getmac(struct npe_softc *sc, u_char *eaddr) 974164426Ssam{ 975164426Ssam /* NB: the unicast address appears to be loaded from EEPROM on reset */ 976164426Ssam eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 977164426Ssam eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 978164426Ssam eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 979164426Ssam eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 980164426Ssam eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 981164426Ssam eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 982164426Ssam} 983164426Ssam 984164426Ssamstruct txdone { 985164426Ssam struct npebuf *head; 986164426Ssam struct npebuf **tail; 987164426Ssam int count; 988164426Ssam}; 989164426Ssam 990164426Ssamstatic __inline void 991164426Ssamnpe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 992164426Ssam{ 993164426Ssam struct ifnet *ifp = sc->sc_ifp; 994164426Ssam 995164426Ssam NPE_LOCK(sc); 996164426Ssam *td->tail = sc->tx_free; 997164426Ssam sc->tx_free = td->head; 998164426Ssam /* 999164426Ssam * We're no longer busy, so clear the busy flag and call the 1000164426Ssam * start routine to xmit more packets. 1001164426Ssam */ 1002164426Ssam ifp->if_opackets += td->count; 1003164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1004166339Skevlo sc->npe_watchdog_timer = 0; 1005164426Ssam npestart_locked(ifp); 1006164426Ssam NPE_UNLOCK(sc); 1007164426Ssam} 1008164426Ssam 1009164426Ssam/* 1010164426Ssam * Q manager callback on tx done queue. Reap mbufs 1011164426Ssam * and return tx buffers to the free list. Finally 1012164426Ssam * restart output. Note the microcode has only one 1013164426Ssam * txdone q wired into it so we must use the NPE ID 1014164426Ssam * returned with each npehwbuf to decide where to 1015164426Ssam * send buffers. 1016164426Ssam */ 1017164426Ssamstatic void 1018164426Ssamnpe_txdone(int qid, void *arg) 1019164426Ssam{ 1020164426Ssam#define P2V(a, dma) \ 1021164426Ssam &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1022164426Ssam struct npe_softc *sc0 = arg; 1023164426Ssam struct npe_softc *sc; 1024164426Ssam struct npebuf *npe; 1025164426Ssam struct txdone *td, q[NPE_MAX]; 1026164426Ssam uint32_t entry; 1027164426Ssam 1028194321Ssam q[NPE_A].tail = &q[NPE_A].head; q[NPE_A].count = 0; 1029164426Ssam q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 1030164426Ssam q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 1031164426Ssam /* XXX max # at a time? */ 1032164426Ssam while (ixpqmgr_qread(qid, &entry) == 0) { 1033164426Ssam DPRINTF(sc0, "%s: entry 0x%x NPE %u port %u\n", 1034164426Ssam __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 1035164426Ssam 1036164426Ssam sc = npes[NPE_QM_Q_NPE(entry)]; 1037164426Ssam npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 1038164426Ssam m_freem(npe->ix_m); 1039164426Ssam npe->ix_m = NULL; 1040164426Ssam 1041164426Ssam td = &q[NPE_QM_Q_NPE(entry)]; 1042164426Ssam *td->tail = npe; 1043164426Ssam td->tail = &npe->ix_next; 1044164426Ssam td->count++; 1045164426Ssam } 1046164426Ssam 1047194321Ssam if (q[NPE_A].count) 1048194321Ssam npe_txdone_finish(npes[NPE_A], &q[NPE_A]); 1049164426Ssam if (q[NPE_B].count) 1050164426Ssam npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 1051164426Ssam if (q[NPE_C].count) 1052164426Ssam npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 1053164426Ssam#undef P2V 1054164426Ssam} 1055164426Ssam 1056164426Ssamstatic int 1057164426Ssamnpe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 1058164426Ssam{ 1059164426Ssam bus_dma_segment_t segs[1]; 1060164426Ssam struct npedma *dma = &sc->rxdma; 1061164426Ssam struct npehwbuf *hw; 1062164426Ssam int error, nseg; 1063164426Ssam 1064164426Ssam if (m == NULL) { 1065164426Ssam m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1066164426Ssam if (m == NULL) 1067164426Ssam return ENOBUFS; 1068164426Ssam } 1069164426Ssam KASSERT(m->m_ext.ext_size >= 1536 + ETHER_ALIGN, 1070164426Ssam ("ext_size %d", m->m_ext.ext_size)); 1071164426Ssam m->m_pkthdr.len = m->m_len = 1536; 1072164426Ssam /* backload payload and align ip hdr */ 1073164426Ssam m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN)); 1074164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, m, 1075164426Ssam segs, &nseg, 0); 1076164426Ssam if (error != 0) { 1077164426Ssam m_freem(m); 1078164426Ssam return error; 1079164426Ssam } 1080164426Ssam hw = npe->ix_hw; 1081164426Ssam hw->ix_ne[0].data = htobe32(segs[0].ds_addr); 1082164426Ssam /* NB: NPE requires length be a multiple of 64 */ 1083164426Ssam /* NB: buffer length is shifted in word */ 1084164426Ssam hw->ix_ne[0].len = htobe32(segs[0].ds_len << 16); 1085164426Ssam hw->ix_ne[0].next = 0; 1086164426Ssam npe->ix_m = m; 1087164426Ssam /* Flush the memory in the mbuf */ 1088164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREREAD); 1089164426Ssam return 0; 1090164426Ssam} 1091164426Ssam 1092164426Ssam/* 1093164426Ssam * RX q processing for a specific NPE. Claim entries 1094164426Ssam * from the hardware queue and pass the frames up the 1095164426Ssam * stack. Pass the rx buffers to the free list. 1096164426Ssam */ 1097193096Sattiliostatic int 1098164426Ssamnpe_rxdone(int qid, void *arg) 1099164426Ssam{ 1100164426Ssam#define P2V(a, dma) \ 1101164426Ssam &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1102164426Ssam struct npe_softc *sc = arg; 1103164426Ssam struct npedma *dma = &sc->rxdma; 1104164426Ssam uint32_t entry; 1105193096Sattilio int rx_npkts = 0; 1106164426Ssam 1107164426Ssam while (ixpqmgr_qread(qid, &entry) == 0) { 1108164426Ssam struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 1109164426Ssam struct mbuf *m; 1110164426Ssam 1111164426Ssam DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 1112164426Ssam __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 1113164426Ssam /* 1114164426Ssam * Allocate a new mbuf to replenish the rx buffer. 1115164426Ssam * If doing so fails we drop the rx'd frame so we 1116164426Ssam * can reuse the previous mbuf. When we're able to 1117164426Ssam * allocate a new mbuf dispatch the mbuf w/ rx'd 1118164426Ssam * data up the stack and replace it with the newly 1119164426Ssam * allocated one. 1120164426Ssam */ 1121164426Ssam m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1122164426Ssam if (m != NULL) { 1123164426Ssam struct mbuf *mrx = npe->ix_m; 1124164426Ssam struct npehwbuf *hw = npe->ix_hw; 1125164426Ssam struct ifnet *ifp = sc->sc_ifp; 1126164426Ssam 1127164426Ssam /* Flush mbuf memory for rx'd data */ 1128164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, 1129164426Ssam BUS_DMASYNC_POSTREAD); 1130164426Ssam 1131164426Ssam /* XXX flush hw buffer; works now 'cuz coherent */ 1132164426Ssam /* set m_len etc. per rx frame size */ 1133164426Ssam mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 1134164426Ssam mrx->m_pkthdr.len = mrx->m_len; 1135164426Ssam mrx->m_pkthdr.rcvif = ifp; 1136164426Ssam 1137164426Ssam ifp->if_ipackets++; 1138164426Ssam ifp->if_input(ifp, mrx); 1139193096Sattilio rx_npkts++; 1140164426Ssam } else { 1141164426Ssam /* discard frame and re-use mbuf */ 1142164426Ssam m = npe->ix_m; 1143164426Ssam } 1144164426Ssam if (npe_rxbuf_init(sc, npe, m) == 0) { 1145164426Ssam /* return npe buf to rx free list */ 1146164426Ssam ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1147164426Ssam } else { 1148164426Ssam /* XXX should not happen */ 1149164426Ssam } 1150164426Ssam } 1151193104Ssam return rx_npkts; 1152164426Ssam#undef P2V 1153164426Ssam} 1154164426Ssam 1155164426Ssam#ifdef DEVICE_POLLING 1156193096Sattiliostatic int 1157164426Ssamnpe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1158164426Ssam{ 1159164426Ssam struct npe_softc *sc = ifp->if_softc; 1160193096Sattilio int rx_npkts = 0; 1161164426Ssam 1162164426Ssam if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1163193096Sattilio rx_npkts = npe_rxdone(sc->rx_qid, sc); 1164164426Ssam npe_txdone(sc->tx_doneqid, sc); /* XXX polls both NPE's */ 1165164426Ssam } 1166193104Ssam return rx_npkts; 1167164426Ssam} 1168164426Ssam#endif /* DEVICE_POLLING */ 1169164426Ssam 1170164426Ssamstatic void 1171164426Ssamnpe_startxmit(struct npe_softc *sc) 1172164426Ssam{ 1173164426Ssam struct npedma *dma = &sc->txdma; 1174164426Ssam int i; 1175164426Ssam 1176164426Ssam NPE_ASSERT_LOCKED(sc); 1177164426Ssam sc->tx_free = NULL; 1178164426Ssam for (i = 0; i < dma->nbuf; i++) { 1179164426Ssam struct npebuf *npe = &dma->buf[i]; 1180164426Ssam if (npe->ix_m != NULL) { 1181164426Ssam /* NB: should not happen */ 1182164426Ssam device_printf(sc->sc_dev, 1183164426Ssam "%s: free mbuf at entry %u\n", __func__, i); 1184164426Ssam m_freem(npe->ix_m); 1185164426Ssam } 1186164426Ssam npe->ix_m = NULL; 1187164426Ssam npe->ix_next = sc->tx_free; 1188164426Ssam sc->tx_free = npe; 1189164426Ssam } 1190164426Ssam} 1191164426Ssam 1192164426Ssamstatic void 1193164426Ssamnpe_startrecv(struct npe_softc *sc) 1194164426Ssam{ 1195164426Ssam struct npedma *dma = &sc->rxdma; 1196164426Ssam struct npebuf *npe; 1197164426Ssam int i; 1198164426Ssam 1199164426Ssam NPE_ASSERT_LOCKED(sc); 1200164426Ssam for (i = 0; i < dma->nbuf; i++) { 1201164426Ssam npe = &dma->buf[i]; 1202164426Ssam npe_rxbuf_init(sc, npe, npe->ix_m); 1203164426Ssam /* set npe buf on rx free list */ 1204164426Ssam ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1205164426Ssam } 1206164426Ssam} 1207164426Ssam 1208164426Ssam/* 1209164426Ssam * Reset and initialize the chip 1210164426Ssam */ 1211164426Ssamstatic void 1212164426Ssamnpeinit_locked(void *xsc) 1213164426Ssam{ 1214164426Ssam struct npe_softc *sc = xsc; 1215164426Ssam struct ifnet *ifp = sc->sc_ifp; 1216164426Ssam 1217164426Ssam NPE_ASSERT_LOCKED(sc); 1218164426Ssamif (ifp->if_drv_flags & IFF_DRV_RUNNING) return;/*XXX*/ 1219164426Ssam 1220164426Ssam /* 1221164426Ssam * Reset MAC core. 1222164426Ssam */ 1223186352Ssam npe_mac_reset(sc); 1224164426Ssam 1225164426Ssam /* disable transmitter and reciver in the MAC */ 1226164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1227164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1228164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1229164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1230164426Ssam 1231164426Ssam /* 1232164426Ssam * Set the MAC core registers. 1233164426Ssam */ 1234164426Ssam WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1235164426Ssam WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1236164426Ssam WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1237164426Ssam /* thresholds determined by NPE firmware FS */ 1238164426Ssam WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1239164426Ssam WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1240164426Ssam WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */ 1241164426Ssam WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1242164426Ssam WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1243164426Ssam WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1244164426Ssam WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1245164426Ssam WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */ 1246164426Ssam 1247164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1248164426Ssam NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1249164426Ssam | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1250164426Ssam | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1251164426Ssam | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1252164426Ssam /* XXX pad strip? */ 1253189642Ssam /* ena pause frame handling */ 1254189642Ssam WR4(sc, NPE_MAC_RX_CNTRL1, NPE_RX_CNTRL1_PAUSE_EN); 1255164426Ssam WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1256164426Ssam 1257164426Ssam npe_setmac(sc, IF_LLADDR(ifp)); 1258194321Ssam npe_setportaddress(sc, IF_LLADDR(ifp)); 1259164426Ssam npe_setmcast(sc); 1260164426Ssam 1261164426Ssam npe_startxmit(sc); 1262164426Ssam npe_startrecv(sc); 1263164426Ssam 1264164426Ssam ifp->if_drv_flags |= IFF_DRV_RUNNING; 1265164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1266166339Skevlo sc->npe_watchdog_timer = 0; /* just in case */ 1267164426Ssam 1268164426Ssam /* enable transmitter and reciver in the MAC */ 1269164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1270164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1271164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1272164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1273164426Ssam 1274164426Ssam callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 1275164426Ssam} 1276164426Ssam 1277164426Ssamstatic void 1278164426Ssamnpeinit(void *xsc) 1279164426Ssam{ 1280164426Ssam struct npe_softc *sc = xsc; 1281164426Ssam NPE_LOCK(sc); 1282164426Ssam npeinit_locked(sc); 1283164426Ssam NPE_UNLOCK(sc); 1284164426Ssam} 1285164426Ssam 1286164426Ssam/* 1287164426Ssam * Dequeue packets and place on the h/w transmit queue. 1288164426Ssam */ 1289164426Ssamstatic void 1290164426Ssamnpestart_locked(struct ifnet *ifp) 1291164426Ssam{ 1292164426Ssam struct npe_softc *sc = ifp->if_softc; 1293164426Ssam struct npebuf *npe; 1294164426Ssam struct npehwbuf *hw; 1295164426Ssam struct mbuf *m, *n; 1296164426Ssam struct npedma *dma = &sc->txdma; 1297164426Ssam bus_dma_segment_t segs[NPE_MAXSEG]; 1298164426Ssam int nseg, len, error, i; 1299164426Ssam uint32_t next; 1300164426Ssam 1301164426Ssam NPE_ASSERT_LOCKED(sc); 1302164426Ssam /* XXX can this happen? */ 1303164426Ssam if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1304164426Ssam return; 1305164426Ssam 1306164426Ssam while (sc->tx_free != NULL) { 1307164426Ssam IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1308164426Ssam if (m == NULL) { 1309164426Ssam /* XXX? */ 1310164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1311164426Ssam return; 1312164426Ssam } 1313164426Ssam npe = sc->tx_free; 1314164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1315164426Ssam m, segs, &nseg, 0); 1316164426Ssam if (error == EFBIG) { 1317175418Sjhb n = m_collapse(m, M_DONTWAIT, NPE_MAXSEG); 1318164426Ssam if (n == NULL) { 1319164426Ssam if_printf(ifp, "%s: too many fragments %u\n", 1320164426Ssam __func__, nseg); 1321164426Ssam m_freem(m); 1322164426Ssam return; /* XXX? */ 1323164426Ssam } 1324164426Ssam m = n; 1325164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1326164426Ssam m, segs, &nseg, 0); 1327164426Ssam } 1328164426Ssam if (error != 0 || nseg == 0) { 1329164426Ssam if_printf(ifp, "%s: error %u nseg %u\n", 1330164426Ssam __func__, error, nseg); 1331164426Ssam m_freem(m); 1332164426Ssam return; /* XXX? */ 1333164426Ssam } 1334164426Ssam sc->tx_free = npe->ix_next; 1335164426Ssam 1336164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREWRITE); 1337164426Ssam 1338164426Ssam /* 1339164426Ssam * Tap off here if there is a bpf listener. 1340164426Ssam */ 1341164426Ssam BPF_MTAP(ifp, m); 1342164426Ssam 1343164426Ssam npe->ix_m = m; 1344164426Ssam hw = npe->ix_hw; 1345164426Ssam len = m->m_pkthdr.len; 1346164426Ssam next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1347164426Ssam for (i = 0; i < nseg; i++) { 1348164426Ssam hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1349164426Ssam hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1350164426Ssam hw->ix_ne[i].next = htobe32(next); 1351164426Ssam 1352164426Ssam len = 0; /* zero for segments > 1 */ 1353164426Ssam next += sizeof(hw->ix_ne[0]); 1354164426Ssam } 1355164426Ssam hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1356164426Ssam /* XXX flush descriptor instead of using uncached memory */ 1357164426Ssam 1358164426Ssam DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1359164426Ssam __func__, sc->tx_qid, npe->ix_neaddr, 1360164426Ssam hw->ix_ne[0].data, hw->ix_ne[0].len); 1361164426Ssam /* stick it on the tx q */ 1362164426Ssam /* XXX add vlan priority */ 1363164426Ssam ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1364164426Ssam 1365166339Skevlo sc->npe_watchdog_timer = 5; 1366164426Ssam } 1367164426Ssam if (sc->tx_free == NULL) 1368164426Ssam ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1369164426Ssam} 1370164426Ssam 1371164426Ssamvoid 1372164426Ssamnpestart(struct ifnet *ifp) 1373164426Ssam{ 1374164426Ssam struct npe_softc *sc = ifp->if_softc; 1375164426Ssam NPE_LOCK(sc); 1376164426Ssam npestart_locked(ifp); 1377164426Ssam NPE_UNLOCK(sc); 1378164426Ssam} 1379164426Ssam 1380164426Ssamstatic void 1381164426Ssamnpe_stopxmit(struct npe_softc *sc) 1382164426Ssam{ 1383164426Ssam struct npedma *dma = &sc->txdma; 1384164426Ssam int i; 1385164426Ssam 1386164426Ssam NPE_ASSERT_LOCKED(sc); 1387164426Ssam 1388164426Ssam /* XXX qmgr */ 1389164426Ssam for (i = 0; i < dma->nbuf; i++) { 1390164426Ssam struct npebuf *npe = &dma->buf[i]; 1391164426Ssam 1392164426Ssam if (npe->ix_m != NULL) { 1393164426Ssam bus_dmamap_unload(dma->mtag, npe->ix_map); 1394164426Ssam m_freem(npe->ix_m); 1395164426Ssam npe->ix_m = NULL; 1396164426Ssam } 1397164426Ssam } 1398164426Ssam} 1399164426Ssam 1400164426Ssamstatic void 1401164426Ssamnpe_stoprecv(struct npe_softc *sc) 1402164426Ssam{ 1403164426Ssam struct npedma *dma = &sc->rxdma; 1404164426Ssam int i; 1405164426Ssam 1406164426Ssam NPE_ASSERT_LOCKED(sc); 1407164426Ssam 1408164426Ssam /* XXX qmgr */ 1409164426Ssam for (i = 0; i < dma->nbuf; i++) { 1410164426Ssam struct npebuf *npe = &dma->buf[i]; 1411164426Ssam 1412164426Ssam if (npe->ix_m != NULL) { 1413164426Ssam bus_dmamap_unload(dma->mtag, npe->ix_map); 1414164426Ssam m_freem(npe->ix_m); 1415164426Ssam npe->ix_m = NULL; 1416164426Ssam } 1417164426Ssam } 1418164426Ssam} 1419164426Ssam 1420164426Ssam/* 1421164426Ssam * Turn off interrupts, and stop the nic. 1422164426Ssam */ 1423164426Ssamvoid 1424164426Ssamnpestop(struct npe_softc *sc) 1425164426Ssam{ 1426164426Ssam struct ifnet *ifp = sc->sc_ifp; 1427164426Ssam 1428164426Ssam /* disable transmitter and reciver in the MAC */ 1429164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1430164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1431164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1432164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1433164426Ssam 1434166339Skevlo sc->npe_watchdog_timer = 0; 1435164426Ssam ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1436164426Ssam 1437164426Ssam callout_stop(&sc->tick_ch); 1438164426Ssam 1439164426Ssam npe_stopxmit(sc); 1440164426Ssam npe_stoprecv(sc); 1441164426Ssam /* XXX go into loopback & drain q's? */ 1442164426Ssam /* XXX but beware of disabling tx above */ 1443164426Ssam 1444164426Ssam /* 1445164426Ssam * The MAC core rx/tx disable may leave the MAC hardware in an 1446164426Ssam * unpredictable state. A hw reset is executed before resetting 1447164426Ssam * all the MAC parameters to a known value. 1448164426Ssam */ 1449164426Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1450164426Ssam DELAY(NPE_MAC_RESET_DELAY); 1451164426Ssam WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1452164426Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1453164426Ssam} 1454164426Ssam 1455164426Ssamvoid 1456166339Skevlonpewatchdog(struct npe_softc *sc) 1457164426Ssam{ 1458166339Skevlo NPE_ASSERT_LOCKED(sc); 1459164426Ssam 1460166339Skevlo if (sc->npe_watchdog_timer == 0 || --sc->npe_watchdog_timer != 0) 1461166339Skevlo return; 1462166339Skevlo 1463166339Skevlo device_printf(sc->sc_dev, "watchdog timeout\n"); 1464166339Skevlo sc->sc_ifp->if_oerrors++; 1465166339Skevlo 1466164426Ssam npeinit_locked(sc); 1467164426Ssam} 1468164426Ssam 1469164426Ssamstatic int 1470164426Ssamnpeioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1471164426Ssam{ 1472164426Ssam struct npe_softc *sc = ifp->if_softc; 1473164426Ssam struct mii_data *mii; 1474164426Ssam struct ifreq *ifr = (struct ifreq *)data; 1475164426Ssam int error = 0; 1476164426Ssam#ifdef DEVICE_POLLING 1477164426Ssam int mask; 1478164426Ssam#endif 1479164426Ssam 1480164426Ssam switch (cmd) { 1481164426Ssam case SIOCSIFFLAGS: 1482164426Ssam NPE_LOCK(sc); 1483164426Ssam if ((ifp->if_flags & IFF_UP) == 0 && 1484164426Ssam ifp->if_drv_flags & IFF_DRV_RUNNING) { 1485164426Ssam ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1486164426Ssam npestop(sc); 1487164426Ssam } else { 1488164426Ssam /* reinitialize card on any parameter change */ 1489164426Ssam npeinit_locked(sc); 1490164426Ssam } 1491164426Ssam NPE_UNLOCK(sc); 1492164426Ssam break; 1493164426Ssam 1494164426Ssam case SIOCADDMULTI: 1495164426Ssam case SIOCDELMULTI: 1496164426Ssam /* update multicast filter list. */ 1497164426Ssam NPE_LOCK(sc); 1498164426Ssam npe_setmcast(sc); 1499164426Ssam NPE_UNLOCK(sc); 1500164426Ssam error = 0; 1501164426Ssam break; 1502164426Ssam 1503164426Ssam case SIOCSIFMEDIA: 1504164426Ssam case SIOCGIFMEDIA: 1505164426Ssam mii = device_get_softc(sc->sc_mii); 1506164426Ssam error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1507164426Ssam break; 1508164426Ssam 1509164426Ssam#ifdef DEVICE_POLLING 1510164426Ssam case SIOCSIFCAP: 1511164426Ssam mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1512164426Ssam if (mask & IFCAP_POLLING) { 1513164426Ssam if (ifr->ifr_reqcap & IFCAP_POLLING) { 1514164426Ssam error = ether_poll_register(npe_poll, ifp); 1515164426Ssam if (error) 1516164426Ssam return error; 1517164426Ssam NPE_LOCK(sc); 1518164426Ssam /* disable callbacks XXX txdone is shared */ 1519164426Ssam ixpqmgr_notify_disable(sc->rx_qid); 1520164426Ssam ixpqmgr_notify_disable(sc->tx_doneqid); 1521164426Ssam ifp->if_capenable |= IFCAP_POLLING; 1522164426Ssam NPE_UNLOCK(sc); 1523164426Ssam } else { 1524164426Ssam error = ether_poll_deregister(ifp); 1525164426Ssam /* NB: always enable qmgr callbacks */ 1526164426Ssam NPE_LOCK(sc); 1527164426Ssam /* enable qmgr callbacks */ 1528164426Ssam ixpqmgr_notify_enable(sc->rx_qid, 1529164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E); 1530164426Ssam ixpqmgr_notify_enable(sc->tx_doneqid, 1531164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E); 1532164426Ssam ifp->if_capenable &= ~IFCAP_POLLING; 1533164426Ssam NPE_UNLOCK(sc); 1534164426Ssam } 1535164426Ssam } 1536164426Ssam break; 1537164426Ssam#endif 1538164426Ssam default: 1539164426Ssam error = ether_ioctl(ifp, cmd, data); 1540164426Ssam break; 1541164426Ssam } 1542164426Ssam return error; 1543164426Ssam} 1544164426Ssam 1545164426Ssam/* 1546164426Ssam * Setup a traffic class -> rx queue mapping. 1547164426Ssam */ 1548164426Ssamstatic int 1549164426Ssamnpe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1550164426Ssam{ 1551164426Ssam uint32_t msg[2]; 1552164426Ssam 1553186352Ssam msg[0] = (NPE_SETRXQOSENTRY << 24) | (sc->sc_npeid << 20) | classix; 1554164426Ssam msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1555186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1556164426Ssam} 1557164426Ssam 1558186352Ssamstatic int 1559194321Ssamnpe_setportaddress(struct npe_softc *sc, const uint8_t mac[ETHER_ADDR_LEN]) 1560194321Ssam{ 1561194321Ssam uint32_t msg[2]; 1562194321Ssam 1563194321Ssam msg[0] = (NPE_SETPORTADDRESS << 24) 1564194321Ssam | (sc->sc_npeid << 20) 1565194321Ssam | (mac[0] << 8) 1566194321Ssam | (mac[1] << 0); 1567194321Ssam msg[1] = (mac[2] << 24) 1568194321Ssam | (mac[3] << 16) 1569194321Ssam | (mac[4] << 8) 1570194321Ssam | (mac[5] << 0); 1571194321Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1572194321Ssam} 1573194321Ssam 1574194321Ssamstatic int 1575186352Ssamnpe_setfirewallmode(struct npe_softc *sc, int onoff) 1576186352Ssam{ 1577186352Ssam uint32_t msg[2]; 1578186352Ssam 1579186352Ssam /* XXX honor onoff */ 1580186352Ssam msg[0] = (NPE_SETFIREWALLMODE << 24) | (sc->sc_npeid << 20); 1581186352Ssam msg[1] = 0; 1582186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1583186352Ssam} 1584186352Ssam 1585164426Ssam/* 1586164426Ssam * Update and reset the statistics in the NPE. 1587164426Ssam */ 1588164426Ssamstatic int 1589164426Ssamnpe_updatestats(struct npe_softc *sc) 1590164426Ssam{ 1591164426Ssam uint32_t msg[2]; 1592164426Ssam 1593164426Ssam msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1594164426Ssam msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1595186352Ssam return ixpnpe_sendmsg_async(sc->sc_npe, msg); 1596164426Ssam} 1597164426Ssam 1598164426Ssam#if 0 1599164426Ssam/* 1600164426Ssam * Get the current statistics block. 1601164426Ssam */ 1602164426Ssamstatic int 1603164426Ssamnpe_getstats(struct npe_softc *sc) 1604164426Ssam{ 1605164426Ssam uint32_t msg[2]; 1606164426Ssam 1607164426Ssam msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1608164426Ssam msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1609164426Ssam return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1610164426Ssam} 1611164426Ssam 1612164426Ssam/* 1613164426Ssam * Query the image id of the loaded firmware. 1614164426Ssam */ 1615164426Ssamstatic uint32_t 1616164426Ssamnpe_getimageid(struct npe_softc *sc) 1617164426Ssam{ 1618164426Ssam uint32_t msg[2]; 1619164426Ssam 1620164426Ssam msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1621164426Ssam msg[1] = 0; 1622186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1623164426Ssam} 1624164426Ssam 1625164426Ssam/* 1626164426Ssam * Enable/disable loopback. 1627164426Ssam */ 1628164426Ssamstatic int 1629164426Ssamnpe_setloopback(struct npe_softc *sc, int ena) 1630164426Ssam{ 1631164426Ssam uint32_t msg[2]; 1632164426Ssam 1633164426Ssam msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1634164426Ssam msg[1] = 0; 1635186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1636164426Ssam} 1637164426Ssam#endif 1638164426Ssam 1639164426Ssamstatic void 1640164426Ssamnpe_child_detached(device_t dev, device_t child) 1641164426Ssam{ 1642164426Ssam struct npe_softc *sc; 1643164426Ssam 1644164426Ssam sc = device_get_softc(dev); 1645164426Ssam if (child == sc->sc_mii) 1646164426Ssam sc->sc_mii = NULL; 1647164426Ssam} 1648164426Ssam 1649164426Ssam/* 1650164426Ssam * MII bus support routines. 1651164426Ssam */ 1652186352Ssam#define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1653186352Ssam#define MII_WR4(sc, reg, v) \ 1654186352Ssam bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1655186352Ssam 1656164426Ssamstatic uint32_t 1657164426Ssamnpe_mii_mdio_read(struct npe_softc *sc, int reg) 1658164426Ssam{ 1659164426Ssam uint32_t v; 1660164426Ssam 1661164426Ssam /* NB: registers are known to be sequential */ 1662164426Ssam v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1663164426Ssam v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1664164426Ssam v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1665164426Ssam v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1666164426Ssam return v; 1667164426Ssam} 1668164426Ssam 1669164426Ssamstatic void 1670164426Ssamnpe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1671164426Ssam{ 1672164426Ssam /* NB: registers are known to be sequential */ 1673164426Ssam MII_WR4(sc, reg+0, cmd & 0xff); 1674164426Ssam MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1675164426Ssam MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1676164426Ssam MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1677164426Ssam} 1678164426Ssam 1679164426Ssamstatic int 1680164426Ssamnpe_mii_mdio_wait(struct npe_softc *sc) 1681164426Ssam{ 1682164426Ssam uint32_t v; 1683164426Ssam int i; 1684164426Ssam 1685186352Ssam /* NB: typically this takes 25-30 trips */ 1686186352Ssam for (i = 0; i < 1000; i++) { 1687164426Ssam v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1688164426Ssam if ((v & NPE_MII_GO) == 0) 1689164426Ssam return 1; 1690186352Ssam DELAY(1); 1691164426Ssam } 1692186352Ssam device_printf(sc->sc_dev, "%s: timeout after ~1ms, cmd 0x%x\n", 1693186352Ssam __func__, v); 1694164426Ssam return 0; /* NB: timeout */ 1695164426Ssam} 1696164426Ssam 1697164426Ssamstatic int 1698164426Ssamnpe_miibus_readreg(device_t dev, int phy, int reg) 1699164426Ssam{ 1700164426Ssam struct npe_softc *sc = device_get_softc(dev); 1701164426Ssam uint32_t v; 1702164426Ssam 1703177505Ssam if (phy != sc->sc_phy) /* XXX no auto-detect */ 1704164426Ssam return 0xffff; 1705186352Ssam v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) | NPE_MII_GO; 1706164426Ssam npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1707164426Ssam if (npe_mii_mdio_wait(sc)) 1708164426Ssam v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1709164426Ssam else 1710164426Ssam v = 0xffff | NPE_MII_READ_FAIL; 1711164426Ssam return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1712164426Ssam} 1713164426Ssam 1714194015Savgstatic int 1715164426Ssamnpe_miibus_writereg(device_t dev, int phy, int reg, int data) 1716164426Ssam{ 1717164426Ssam struct npe_softc *sc = device_get_softc(dev); 1718164426Ssam uint32_t v; 1719164426Ssam 1720177505Ssam if (phy != sc->sc_phy) /* XXX */ 1721194015Savg return (0); 1722164426Ssam v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1723164426Ssam | data | NPE_MII_WRITE 1724164426Ssam | NPE_MII_GO; 1725164426Ssam npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1726164426Ssam /* XXX complain about timeout */ 1727164426Ssam (void) npe_mii_mdio_wait(sc); 1728194015Savg return (0); 1729164426Ssam} 1730164426Ssam 1731164426Ssamstatic void 1732164426Ssamnpe_miibus_statchg(device_t dev) 1733164426Ssam{ 1734164426Ssam struct npe_softc *sc = device_get_softc(dev); 1735164426Ssam struct mii_data *mii = device_get_softc(sc->sc_mii); 1736164426Ssam uint32_t tx1, rx1; 1737164426Ssam 1738164426Ssam /* sync MAC duplex state */ 1739164426Ssam tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1740164426Ssam rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1741164426Ssam if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1742164426Ssam tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1743164426Ssam rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1744164426Ssam } else { 1745164426Ssam tx1 |= NPE_TX_CNTRL1_DUPLEX; 1746164426Ssam rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1747164426Ssam } 1748164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1749164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1750164426Ssam} 1751164426Ssam 1752164426Ssamstatic device_method_t npe_methods[] = { 1753164426Ssam /* Device interface */ 1754164426Ssam DEVMETHOD(device_probe, npe_probe), 1755164426Ssam DEVMETHOD(device_attach, npe_attach), 1756164426Ssam DEVMETHOD(device_detach, npe_detach), 1757164426Ssam 1758164426Ssam /* Bus interface */ 1759164426Ssam DEVMETHOD(bus_child_detached, npe_child_detached), 1760164426Ssam 1761164426Ssam /* MII interface */ 1762164426Ssam DEVMETHOD(miibus_readreg, npe_miibus_readreg), 1763164426Ssam DEVMETHOD(miibus_writereg, npe_miibus_writereg), 1764164426Ssam DEVMETHOD(miibus_statchg, npe_miibus_statchg), 1765164426Ssam 1766164426Ssam { 0, 0 } 1767164426Ssam}; 1768164426Ssam 1769164426Ssamstatic driver_t npe_driver = { 1770164426Ssam "npe", 1771164426Ssam npe_methods, 1772164426Ssam sizeof(struct npe_softc), 1773164426Ssam}; 1774164426Ssam 1775164426SsamDRIVER_MODULE(npe, ixp, npe_driver, npe_devclass, 0, 0); 1776164426SsamDRIVER_MODULE(miibus, npe, miibus_driver, miibus_devclass, 0, 0); 1777164426SsamMODULE_DEPEND(npe, ixpqmgr, 1, 1, 1); 1778164426SsamMODULE_DEPEND(npe, miibus, 1, 1, 1); 1779164426SsamMODULE_DEPEND(npe, ether, 1, 1, 1); 1780