if_npe.c revision 193104
1164426Ssam/*- 2177505Ssam * Copyright (c) 2006-2008 Sam Leffler. All rights reserved. 3164426Ssam * 4164426Ssam * Redistribution and use in source and binary forms, with or without 5164426Ssam * modification, are permitted provided that the following conditions 6164426Ssam * are met: 7164426Ssam * 1. Redistributions of source code must retain the above copyright 8164426Ssam * notice, this list of conditions and the following disclaimer. 9164426Ssam * 2. Redistributions in binary form must reproduce the above copyright 10164426Ssam * notice, this list of conditions and the following disclaimer in the 11164426Ssam * documentation and/or other materials provided with the distribution. 12164426Ssam * 13164426Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14164426Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15164426Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16164426Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17164426Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18164426Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19164426Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20164426Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21164426Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22164426Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23164426Ssam */ 24164426Ssam 25164426Ssam#include <sys/cdefs.h> 26164426Ssam__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/if_npe.c 193104 2009-05-30 18:23:55Z sam $"); 27164426Ssam 28164426Ssam/* 29164426Ssam * Intel XScale NPE Ethernet driver. 30164426Ssam * 31164426Ssam * This driver handles the two ports present on the IXP425. 32164426Ssam * Packet processing is done by the Network Processing Engines 33164426Ssam * (NPE's) that work together with a MAC and PHY. The MAC 34164426Ssam * is also mapped to the XScale cpu; the PHY is accessed via 35164426Ssam * the MAC. NPE-XScale communication happens through h/w 36164426Ssam * queues managed by the Q Manager block. 37164426Ssam * 38164426Ssam * The code here replaces the ethAcc, ethMii, and ethDB classes 39164426Ssam * in the Intel Access Library (IAL) and the OS-specific driver. 40164426Ssam * 41164426Ssam * XXX add vlan support 42164426Ssam */ 43164426Ssam#ifdef HAVE_KERNEL_OPTION_HEADERS 44164426Ssam#include "opt_device_polling.h" 45164426Ssam#endif 46164426Ssam 47164426Ssam#include <sys/param.h> 48164426Ssam#include <sys/systm.h> 49164426Ssam#include <sys/bus.h> 50164426Ssam#include <sys/kernel.h> 51164426Ssam#include <sys/mbuf.h> 52164426Ssam#include <sys/malloc.h> 53164426Ssam#include <sys/module.h> 54164426Ssam#include <sys/rman.h> 55164426Ssam#include <sys/socket.h> 56164426Ssam#include <sys/sockio.h> 57164426Ssam#include <sys/sysctl.h> 58164426Ssam#include <sys/endian.h> 59164426Ssam#include <machine/bus.h> 60164426Ssam 61164426Ssam#include <net/ethernet.h> 62164426Ssam#include <net/if.h> 63164426Ssam#include <net/if_arp.h> 64164426Ssam#include <net/if_dl.h> 65164426Ssam#include <net/if_media.h> 66164426Ssam#include <net/if_mib.h> 67164426Ssam#include <net/if_types.h> 68164426Ssam 69164426Ssam#ifdef INET 70164426Ssam#include <netinet/in.h> 71164426Ssam#include <netinet/in_systm.h> 72164426Ssam#include <netinet/in_var.h> 73164426Ssam#include <netinet/ip.h> 74164426Ssam#endif 75164426Ssam 76164426Ssam#include <net/bpf.h> 77164426Ssam#include <net/bpfdesc.h> 78164426Ssam 79164426Ssam#include <arm/xscale/ixp425/ixp425reg.h> 80164426Ssam#include <arm/xscale/ixp425/ixp425var.h> 81164426Ssam#include <arm/xscale/ixp425/ixp425_qmgr.h> 82164426Ssam#include <arm/xscale/ixp425/ixp425_npevar.h> 83164426Ssam 84164426Ssam#include <dev/mii/mii.h> 85164426Ssam#include <dev/mii/miivar.h> 86164426Ssam#include <arm/xscale/ixp425/if_npereg.h> 87164426Ssam 88186352Ssam#include <machine/armreg.h> 89186352Ssam 90164426Ssam#include "miibus_if.h" 91164426Ssam 92166064Scognet/* 93166064Scognet * XXX: For the main bus dma tag. Can go away if the new method to get the 94166064Scognet * dma tag from the parent got MFC'd into RELENG_6. 95166064Scognet */ 96166064Scognetextern struct ixp425_softc *ixp425_softc; 97166064Scognet 98164426Ssamstruct npebuf { 99164426Ssam struct npebuf *ix_next; /* chain to next buffer */ 100164426Ssam void *ix_m; /* backpointer to mbuf */ 101164426Ssam bus_dmamap_t ix_map; /* bus dma map for associated data */ 102164426Ssam struct npehwbuf *ix_hw; /* associated h/w block */ 103164426Ssam uint32_t ix_neaddr; /* phys address of ix_hw */ 104164426Ssam}; 105164426Ssam 106164426Ssamstruct npedma { 107164426Ssam const char* name; 108164426Ssam int nbuf; /* # npebuf's allocated */ 109164426Ssam bus_dma_tag_t mtag; /* bus dma tag for mbuf data */ 110164426Ssam struct npehwbuf *hwbuf; /* NPE h/w buffers */ 111164426Ssam bus_dma_tag_t buf_tag; /* tag+map for NPE buffers */ 112164426Ssam bus_dmamap_t buf_map; 113164426Ssam bus_addr_t buf_phys; /* phys addr of buffers */ 114164426Ssam struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 115164426Ssam}; 116164426Ssam 117164426Ssamstruct npe_softc { 118164426Ssam /* XXX mii requires this be first; do not move! */ 119164426Ssam struct ifnet *sc_ifp; /* ifnet pointer */ 120164426Ssam struct mtx sc_mtx; /* basically a perimeter lock */ 121164426Ssam device_t sc_dev; 122164426Ssam bus_space_tag_t sc_iot; 123164426Ssam bus_space_handle_t sc_ioh; /* MAC register window */ 124164426Ssam device_t sc_mii; /* child miibus */ 125164426Ssam bus_space_handle_t sc_miih; /* MII register window */ 126186352Ssam int sc_npeid; 127164426Ssam struct ixpnpe_softc *sc_npe; /* NPE support */ 128164426Ssam int sc_debug; /* DPRINTF* control */ 129164426Ssam int sc_tickinterval; 130164426Ssam struct callout tick_ch; /* Tick callout */ 131166339Skevlo int npe_watchdog_timer; 132164426Ssam struct npedma txdma; 133164426Ssam struct npebuf *tx_free; /* list of free tx buffers */ 134164426Ssam struct npedma rxdma; 135164426Ssam bus_addr_t buf_phys; /* XXX for returning a value */ 136164426Ssam int rx_qid; /* rx qid */ 137164426Ssam int rx_freeqid; /* rx free buffers qid */ 138164426Ssam int tx_qid; /* tx qid */ 139164426Ssam int tx_doneqid; /* tx completed qid */ 140177505Ssam int sc_phy; /* PHY id */ 141164426Ssam struct ifmib_iso_8802_3 mibdata; 142164426Ssam bus_dma_tag_t sc_stats_tag; /* bus dma tag for stats block */ 143164426Ssam struct npestats *sc_stats; 144164426Ssam bus_dmamap_t sc_stats_map; 145164426Ssam bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 146192660Ssam struct npestats sc_totals; /* accumulated sc_stats */ 147164426Ssam}; 148164426Ssam 149164426Ssam/* 150186352Ssam * Static configuration for IXP425. The tx and 151164426Ssam * rx free Q id's are fixed by the NPE microcode. The 152164426Ssam * rx Q id's are programmed to be separate to simplify 153164426Ssam * multi-port processing. It may be better to handle 154164426Ssam * all traffic through one Q (as done by the Intel drivers). 155164426Ssam * 156164426Ssam * Note that the PHY's are accessible only from MAC A 157164426Ssam * on the IXP425. This and other platform-specific 158164426Ssam * assumptions probably need to be handled through hints. 159164426Ssam */ 160164426Ssamstatic const struct { 161186352Ssam uint32_t macbase; 162164426Ssam uint32_t miibase; 163177505Ssam int phy; /* phy id */ 164164426Ssam uint8_t rx_qid; 165164426Ssam uint8_t rx_freeqid; 166164426Ssam uint8_t tx_qid; 167164426Ssam uint8_t tx_doneqid; 168186352Ssam} npeconfig[NPE_MAX] = { 169186352Ssam [NPE_A] = { 170186352Ssam .macbase = IXP435_MAC_A_HWBASE, 171186352Ssam .miibase = IXP425_MAC_C_HWBASE, 172186352Ssam .phy = 2, 173186352Ssam .rx_qid = 4, 174186352Ssam .rx_freeqid = 26, 175186352Ssam .tx_qid = 23, 176186352Ssam .tx_doneqid = 31 177186352Ssam }, 178186352Ssam [NPE_B] = { 179186352Ssam .macbase = IXP425_MAC_B_HWBASE, 180186352Ssam .miibase = IXP425_MAC_C_HWBASE, 181177505Ssam .phy = 0, 182164426Ssam .rx_qid = 4, 183164426Ssam .rx_freeqid = 27, 184164426Ssam .tx_qid = 24, 185164426Ssam .tx_doneqid = 31 186164426Ssam }, 187186352Ssam [NPE_C] = { 188186352Ssam .macbase = IXP425_MAC_C_HWBASE, 189186352Ssam .miibase = IXP425_MAC_C_HWBASE, 190177505Ssam .phy = 1, 191164426Ssam .rx_qid = 12, 192164426Ssam .rx_freeqid = 28, 193164426Ssam .tx_qid = 25, 194164426Ssam .tx_doneqid = 31 195164426Ssam }, 196164426Ssam}; 197164426Ssamstatic struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 198164426Ssam 199164426Ssamstatic __inline uint32_t 200164426SsamRD4(struct npe_softc *sc, bus_size_t off) 201164426Ssam{ 202164426Ssam return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 203164426Ssam} 204164426Ssam 205164426Ssamstatic __inline void 206164426SsamWR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 207164426Ssam{ 208164426Ssam bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 209164426Ssam} 210164426Ssam 211164426Ssam#define NPE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 212164426Ssam#define NPE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 213164426Ssam#define NPE_LOCK_INIT(_sc) \ 214164426Ssam mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 215164426Ssam MTX_NETWORK_LOCK, MTX_DEF) 216164426Ssam#define NPE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 217164426Ssam#define NPE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 218164426Ssam#define NPE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 219164426Ssam 220164426Ssamstatic devclass_t npe_devclass; 221164426Ssam 222186352Ssamstatic int override_npeid(device_t, const char *resname, int *val); 223164426Ssamstatic int npe_activate(device_t dev); 224164426Ssamstatic void npe_deactivate(device_t dev); 225164426Ssamstatic int npe_ifmedia_update(struct ifnet *ifp); 226164426Ssamstatic void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 227164426Ssamstatic void npe_setmac(struct npe_softc *sc, u_char *eaddr); 228164426Ssamstatic void npe_getmac(struct npe_softc *sc, u_char *eaddr); 229164426Ssamstatic void npe_txdone(int qid, void *arg); 230164426Ssamstatic int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 231164426Ssam struct mbuf *); 232193096Sattiliostatic int npe_rxdone(int qid, void *arg); 233164426Ssamstatic void npeinit(void *); 234164426Ssamstatic void npestart_locked(struct ifnet *); 235164426Ssamstatic void npestart(struct ifnet *); 236164426Ssamstatic void npestop(struct npe_softc *); 237166339Skevlostatic void npewatchdog(struct npe_softc *); 238164426Ssamstatic int npeioctl(struct ifnet * ifp, u_long, caddr_t); 239164426Ssam 240164426Ssamstatic int npe_setrxqosentry(struct npe_softc *, int classix, 241164426Ssam int trafclass, int qid); 242186352Ssamstatic int npe_setfirewallmode(struct npe_softc *, int onoff); 243164426Ssamstatic int npe_updatestats(struct npe_softc *); 244164426Ssam#if 0 245164426Ssamstatic int npe_getstats(struct npe_softc *); 246164426Ssamstatic uint32_t npe_getimageid(struct npe_softc *); 247164426Ssamstatic int npe_setloopback(struct npe_softc *, int ena); 248164426Ssam#endif 249164426Ssam 250164426Ssam/* NB: all tx done processing goes through one queue */ 251164426Ssamstatic int tx_doneqid = -1; 252164426Ssam 253186352SsamSYSCTL_NODE(_hw, OID_AUTO, npe, CTLFLAG_RD, 0, "IXP4XX NPE driver parameters"); 254164426Ssam 255164426Ssamstatic int npe_debug = 0; 256164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, debug, CTLFLAG_RW, &npe_debug, 257186352Ssam 0, "IXP4XX NPE network interface debug msgs"); 258186420SsamTUNABLE_INT("hw.npe.debug", &npe_debug); 259164426Ssam#define DPRINTF(sc, fmt, ...) do { \ 260164426Ssam if (sc->sc_debug) device_printf(sc->sc_dev, fmt, __VA_ARGS__); \ 261164426Ssam} while (0) 262164426Ssam#define DPRINTFn(n, sc, fmt, ...) do { \ 263164426Ssam if (sc->sc_debug >= n) device_printf(sc->sc_dev, fmt, __VA_ARGS__);\ 264164426Ssam} while (0) 265164426Ssamstatic int npe_tickinterval = 3; /* npe_tick frequency (secs) */ 266164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, tickinterval, CTLFLAG_RD, &npe_tickinterval, 267164426Ssam 0, "periodic work interval (secs)"); 268164426SsamTUNABLE_INT("hw.npe.tickinterval", &npe_tickinterval); 269164426Ssam 270164426Ssamstatic int npe_rxbuf = 64; /* # rx buffers to allocate */ 271164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, rxbuf, CTLFLAG_RD, &npe_rxbuf, 272164426Ssam 0, "rx buffers allocated"); 273164426SsamTUNABLE_INT("hw.npe.rxbuf", &npe_rxbuf); 274164426Ssamstatic int npe_txbuf = 128; /* # tx buffers to allocate */ 275164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, txbuf, CTLFLAG_RD, &npe_txbuf, 276164426Ssam 0, "tx buffers allocated"); 277164426SsamTUNABLE_INT("hw.npe.txbuf", &npe_txbuf); 278164426Ssam 279164426Ssamstatic int 280186352Ssamunit2npeid(int unit) 281186352Ssam{ 282186352Ssam static const int npeidmap[2][3] = { 283186352Ssam /* on 425 A is for HSS, B & C are for Ethernet */ 284186352Ssam { NPE_B, NPE_C, -1 }, /* IXP425 */ 285186352Ssam /* 435 only has A & C, order C then A */ 286186352Ssam { NPE_C, NPE_A, -1 }, /* IXP435 */ 287186352Ssam }; 288186352Ssam /* XXX check feature register instead */ 289186352Ssam return (unit < 3 ? npeidmap[ 290186352Ssam (cpu_id() & CPU_ID_CPU_MASK) == CPU_ID_IXP435][unit] : -1); 291186352Ssam} 292186352Ssam 293186352Ssamstatic int 294164426Ssamnpe_probe(device_t dev) 295164426Ssam{ 296186352Ssam static const char *desc[NPE_MAX] = { 297186352Ssam [NPE_A] = "IXP NPE-A", 298186352Ssam [NPE_B] = "IXP NPE-B", 299186352Ssam [NPE_C] = "IXP NPE-C" 300186352Ssam }; 301186420Ssam int unit = device_get_unit(dev); 302186352Ssam int npeid; 303164426Ssam 304186420Ssam if (unit > 2 || 305186420Ssam (ixp4xx_read_feature_bits() & 306186420Ssam (unit == 0 ? EXP_FCTRL_ETH0 : EXP_FCTRL_ETH1)) == 0) 307186420Ssam return EINVAL; 308186420Ssam 309186352Ssam npeid = -1; 310186352Ssam if (!override_npeid(dev, "npeid", &npeid)) 311186420Ssam npeid = unit2npeid(unit); 312186352Ssam if (npeid == -1) { 313186420Ssam device_printf(dev, "unit %d not supported\n", unit); 314164426Ssam return EINVAL; 315164426Ssam } 316186352Ssam device_set_desc(dev, desc[npeid]); 317164426Ssam return 0; 318164426Ssam} 319164426Ssam 320164426Ssamstatic int 321164426Ssamnpe_attach(device_t dev) 322164426Ssam{ 323164426Ssam struct npe_softc *sc = device_get_softc(dev); 324164426Ssam struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); 325164426Ssam struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 326164426Ssam struct sysctl_oid *tree = device_get_sysctl_tree(dev); 327186352Ssam struct ifnet *ifp; 328164426Ssam int error; 329164426Ssam u_char eaddr[6]; 330164426Ssam 331164426Ssam sc->sc_dev = dev; 332164426Ssam sc->sc_iot = sa->sc_iot; 333164426Ssam NPE_LOCK_INIT(sc); 334164426Ssam callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 335164426Ssam sc->sc_debug = npe_debug; 336164426Ssam sc->sc_tickinterval = npe_tickinterval; 337164426Ssam 338186352Ssam ifp = if_alloc(IFT_ETHER); 339186352Ssam if (ifp == NULL) { 340186352Ssam device_printf(dev, "cannot allocate ifnet\n"); 341164426Ssam error = EIO; /* XXX */ 342164426Ssam goto out; 343164426Ssam } 344186352Ssam /* NB: must be setup prior to invoking mii code */ 345186352Ssam sc->sc_ifp = ifp; 346164426Ssam 347164426Ssam error = npe_activate(dev); 348186352Ssam if (error) { 349186352Ssam device_printf(dev, "cannot activate npe\n"); 350164426Ssam goto out; 351186352Ssam } 352164426Ssam 353164426Ssam npe_getmac(sc, eaddr); 354164426Ssam 355164426Ssam ifp->if_softc = sc; 356164426Ssam if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 357164426Ssam ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 358164426Ssam ifp->if_start = npestart; 359164426Ssam ifp->if_ioctl = npeioctl; 360164426Ssam ifp->if_init = npeinit; 361164426Ssam IFQ_SET_MAXLEN(&ifp->if_snd, sc->txdma.nbuf - 1); 362166625Smlaier ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 363164426Ssam IFQ_SET_READY(&ifp->if_snd); 364164426Ssam ifp->if_linkmib = &sc->mibdata; 365164426Ssam ifp->if_linkmiblen = sizeof(sc->mibdata); 366164426Ssam sc->mibdata.dot3Compliance = DOT3COMPLIANCE_STATS; 367189645Ssam /* device supports oversided vlan frames */ 368189645Ssam ifp->if_capabilities |= IFCAP_VLAN_MTU; 369189645Ssam ifp->if_capenable = ifp->if_capabilities; 370164426Ssam#ifdef DEVICE_POLLING 371164426Ssam ifp->if_capabilities |= IFCAP_POLLING; 372164426Ssam#endif 373164426Ssam 374164426Ssam SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug", 375164426Ssam CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 376164426Ssam SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tickinterval", 377164426Ssam CTLFLAG_RW, &sc->sc_tickinterval, 0, "periodic work frequency"); 378192660Ssam SYSCTL_ADD_STRUCT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "stats", 379192660Ssam CTLFLAG_RD, &sc->sc_totals, npestats, "onboard stats"); 380164426Ssam 381164426Ssam ether_ifattach(ifp, eaddr); 382164426Ssam return 0; 383164426Ssamout: 384164426Ssam if (ifp != NULL) 385164426Ssam if_free(ifp); 386186352Ssam NPE_LOCK_DESTROY(sc); 387186352Ssam npe_deactivate(dev); 388164426Ssam return error; 389164426Ssam} 390164426Ssam 391164426Ssamstatic int 392164426Ssamnpe_detach(device_t dev) 393164426Ssam{ 394164426Ssam struct npe_softc *sc = device_get_softc(dev); 395164426Ssam struct ifnet *ifp = sc->sc_ifp; 396164426Ssam 397164426Ssam#ifdef DEVICE_POLLING 398164426Ssam if (ifp->if_capenable & IFCAP_POLLING) 399164426Ssam ether_poll_deregister(ifp); 400164426Ssam#endif 401164426Ssam npestop(sc); 402164426Ssam if (ifp != NULL) { 403164426Ssam ether_ifdetach(ifp); 404164426Ssam if_free(ifp); 405164426Ssam } 406164426Ssam NPE_LOCK_DESTROY(sc); 407164426Ssam npe_deactivate(dev); 408164426Ssam return 0; 409164426Ssam} 410164426Ssam 411164426Ssam/* 412164426Ssam * Compute and install the multicast filter. 413164426Ssam */ 414164426Ssamstatic void 415164426Ssamnpe_setmcast(struct npe_softc *sc) 416164426Ssam{ 417164426Ssam struct ifnet *ifp = sc->sc_ifp; 418164426Ssam uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 419164426Ssam int i; 420164426Ssam 421164426Ssam if (ifp->if_flags & IFF_PROMISC) { 422164426Ssam memset(mask, 0, ETHER_ADDR_LEN); 423164426Ssam memset(addr, 0, ETHER_ADDR_LEN); 424164426Ssam } else if (ifp->if_flags & IFF_ALLMULTI) { 425164426Ssam static const uint8_t allmulti[ETHER_ADDR_LEN] = 426164426Ssam { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 427164426Ssam memcpy(mask, allmulti, ETHER_ADDR_LEN); 428164426Ssam memcpy(addr, allmulti, ETHER_ADDR_LEN); 429164426Ssam } else { 430164426Ssam uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 431164426Ssam struct ifmultiaddr *ifma; 432164426Ssam const uint8_t *mac; 433164426Ssam 434164426Ssam memset(clr, 0, ETHER_ADDR_LEN); 435164426Ssam memset(set, 0xff, ETHER_ADDR_LEN); 436164426Ssam 437164426Ssam IF_ADDR_LOCK(ifp); 438164426Ssam TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 439164426Ssam if (ifma->ifma_addr->sa_family != AF_LINK) 440164426Ssam continue; 441164426Ssam mac = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 442164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 443164426Ssam clr[i] |= mac[i]; 444164426Ssam set[i] &= mac[i]; 445164426Ssam } 446164426Ssam } 447164426Ssam IF_ADDR_UNLOCK(ifp); 448164426Ssam 449164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 450164426Ssam mask[i] = set[i] | ~clr[i]; 451164426Ssam addr[i] = set[i]; 452164426Ssam } 453164426Ssam } 454164426Ssam 455164426Ssam /* 456164426Ssam * Write the mask and address registers. 457164426Ssam */ 458164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 459164426Ssam WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 460164426Ssam WR4(sc, NPE_MAC_ADDR(i), addr[i]); 461164426Ssam } 462164426Ssam} 463164426Ssam 464164426Ssamstatic void 465164426Ssamnpe_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 466164426Ssam{ 467164426Ssam struct npe_softc *sc; 468164426Ssam 469164426Ssam if (error != 0) 470164426Ssam return; 471164426Ssam sc = (struct npe_softc *)arg; 472164426Ssam sc->buf_phys = segs[0].ds_addr; 473164426Ssam} 474164426Ssam 475164426Ssamstatic int 476164426Ssamnpe_dma_setup(struct npe_softc *sc, struct npedma *dma, 477164426Ssam const char *name, int nbuf, int maxseg) 478164426Ssam{ 479164426Ssam int error, i; 480164426Ssam 481183886Ssam memset(dma, 0, sizeof(*dma)); 482164426Ssam 483164426Ssam dma->name = name; 484164426Ssam dma->nbuf = nbuf; 485164426Ssam 486164426Ssam /* DMA tag for mapped mbufs */ 487166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, 1, 0, 488164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 489164426Ssam MCLBYTES, maxseg, MCLBYTES, 0, 490164426Ssam busdma_lock_mutex, &sc->sc_mtx, &dma->mtag); 491164426Ssam if (error != 0) { 492164426Ssam device_printf(sc->sc_dev, "unable to create %s mbuf dma tag, " 493164426Ssam "error %u\n", dma->name, error); 494164426Ssam return error; 495164426Ssam } 496164426Ssam 497164426Ssam /* DMA tag and map for the NPE buffers */ 498166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 499164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 500164426Ssam nbuf * sizeof(struct npehwbuf), 1, 501164426Ssam nbuf * sizeof(struct npehwbuf), 0, 502164426Ssam busdma_lock_mutex, &sc->sc_mtx, &dma->buf_tag); 503164426Ssam if (error != 0) { 504164426Ssam device_printf(sc->sc_dev, 505164426Ssam "unable to create %s npebuf dma tag, error %u\n", 506164426Ssam dma->name, error); 507164426Ssam return error; 508164426Ssam } 509164426Ssam /* XXX COHERENT for now */ 510164426Ssam if (bus_dmamem_alloc(dma->buf_tag, (void **)&dma->hwbuf, 511164426Ssam BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 512164426Ssam &dma->buf_map) != 0) { 513164426Ssam device_printf(sc->sc_dev, 514164426Ssam "unable to allocate memory for %s h/w buffers, error %u\n", 515164426Ssam dma->name, error); 516164426Ssam return error; 517164426Ssam } 518164426Ssam /* XXX M_TEMP */ 519164426Ssam dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 520164426Ssam if (dma->buf == NULL) { 521164426Ssam device_printf(sc->sc_dev, 522164426Ssam "unable to allocate memory for %s s/w buffers\n", 523164426Ssam dma->name); 524164426Ssam return error; 525164426Ssam } 526164426Ssam if (bus_dmamap_load(dma->buf_tag, dma->buf_map, 527164426Ssam dma->hwbuf, nbuf*sizeof(struct npehwbuf), npe_getaddr, sc, 0) != 0) { 528164426Ssam device_printf(sc->sc_dev, 529164426Ssam "unable to map memory for %s h/w buffers, error %u\n", 530164426Ssam dma->name, error); 531164426Ssam return error; 532164426Ssam } 533164426Ssam dma->buf_phys = sc->buf_phys; 534164426Ssam for (i = 0; i < dma->nbuf; i++) { 535164426Ssam struct npebuf *npe = &dma->buf[i]; 536164426Ssam struct npehwbuf *hw = &dma->hwbuf[i]; 537164426Ssam 538164426Ssam /* calculate offset to shared area */ 539164426Ssam npe->ix_neaddr = dma->buf_phys + 540164426Ssam ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 541164426Ssam KASSERT((npe->ix_neaddr & 0x1f) == 0, 542164426Ssam ("ixpbuf misaligned, PA 0x%x", npe->ix_neaddr)); 543164426Ssam error = bus_dmamap_create(dma->mtag, BUS_DMA_NOWAIT, 544164426Ssam &npe->ix_map); 545164426Ssam if (error != 0) { 546164426Ssam device_printf(sc->sc_dev, 547164426Ssam "unable to create dmamap for %s buffer %u, " 548164426Ssam "error %u\n", dma->name, i, error); 549164426Ssam return error; 550164426Ssam } 551164426Ssam npe->ix_hw = hw; 552164426Ssam } 553164426Ssam bus_dmamap_sync(dma->buf_tag, dma->buf_map, BUS_DMASYNC_PREWRITE); 554164426Ssam return 0; 555164426Ssam} 556164426Ssam 557164426Ssamstatic void 558164426Ssamnpe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 559164426Ssam{ 560164426Ssam int i; 561164426Ssam 562164426Ssam if (dma->hwbuf != NULL) { 563164426Ssam for (i = 0; i < dma->nbuf; i++) { 564164426Ssam struct npebuf *npe = &dma->buf[i]; 565164426Ssam bus_dmamap_destroy(dma->mtag, npe->ix_map); 566164426Ssam } 567164426Ssam bus_dmamap_unload(dma->buf_tag, dma->buf_map); 568164426Ssam bus_dmamem_free(dma->buf_tag, dma->hwbuf, dma->buf_map); 569164426Ssam } 570164426Ssam if (dma->buf != NULL) 571164426Ssam free(dma->buf, M_TEMP); 572164426Ssam if (dma->buf_tag) 573164426Ssam bus_dma_tag_destroy(dma->buf_tag); 574164426Ssam if (dma->mtag) 575164426Ssam bus_dma_tag_destroy(dma->mtag); 576164426Ssam memset(dma, 0, sizeof(*dma)); 577164426Ssam} 578164426Ssam 579164426Ssamstatic int 580186352Ssamoverride_addr(device_t dev, const char *resname, int *base) 581177505Ssam{ 582177505Ssam int unit = device_get_unit(dev); 583177505Ssam const char *resval; 584177505Ssam 585177505Ssam /* XXX warn for wrong hint type */ 586177505Ssam if (resource_string_value("npe", unit, resname, &resval) != 0) 587177505Ssam return 0; 588177505Ssam switch (resval[0]) { 589177505Ssam case 'A': 590186352Ssam *base = IXP435_MAC_A_HWBASE; 591177505Ssam break; 592177505Ssam case 'B': 593177505Ssam *base = IXP425_MAC_B_HWBASE; 594177505Ssam break; 595186352Ssam case 'C': 596186352Ssam *base = IXP425_MAC_C_HWBASE; 597186352Ssam break; 598177505Ssam default: 599177505Ssam device_printf(dev, "Warning, bad value %s for " 600177505Ssam "npe.%d.%s ignored\n", resval, unit, resname); 601177505Ssam return 0; 602177505Ssam } 603177505Ssam if (bootverbose) 604177505Ssam device_printf(dev, "using npe.%d.%s=%s override\n", 605177505Ssam unit, resname, resval); 606177505Ssam return 1; 607177505Ssam} 608177505Ssam 609177505Ssamstatic int 610186352Ssamoverride_npeid(device_t dev, const char *resname, int *npeid) 611186352Ssam{ 612186352Ssam int unit = device_get_unit(dev); 613186352Ssam const char *resval; 614186352Ssam 615186352Ssam /* XXX warn for wrong hint type */ 616186352Ssam if (resource_string_value("npe", unit, resname, &resval) != 0) 617186352Ssam return 0; 618186352Ssam switch (resval[0]) { 619186352Ssam case 'A': *npeid = NPE_A; break; 620186352Ssam case 'B': *npeid = NPE_B; break; 621186352Ssam case 'C': *npeid = NPE_C; break; 622186352Ssam default: 623186352Ssam device_printf(dev, "Warning, bad value %s for " 624186352Ssam "npe.%d.%s ignored\n", resval, unit, resname); 625186352Ssam return 0; 626186352Ssam } 627186352Ssam if (bootverbose) 628186352Ssam device_printf(dev, "using npe.%d.%s=%s override\n", 629186352Ssam unit, resname, resval); 630186352Ssam return 1; 631186352Ssam} 632186352Ssam 633186352Ssamstatic int 634177505Ssamoverride_unit(device_t dev, const char *resname, int *val, int min, int max) 635177505Ssam{ 636177505Ssam int unit = device_get_unit(dev); 637177505Ssam int resval; 638177505Ssam 639177505Ssam if (resource_int_value("npe", unit, resname, &resval) != 0) 640177505Ssam return 0; 641177505Ssam if (!(min <= resval && resval <= max)) { 642177505Ssam device_printf(dev, "Warning, bad value %d for npe.%d.%s " 643177505Ssam "ignored (value must be [%d-%d])\n", resval, unit, 644177505Ssam resname, min, max); 645177505Ssam return 0; 646177505Ssam } 647177505Ssam if (bootverbose) 648177505Ssam device_printf(dev, "using npe.%d.%s=%d override\n", 649177505Ssam unit, resname, resval); 650177505Ssam *val = resval; 651177505Ssam return 1; 652177505Ssam} 653177505Ssam 654186352Ssamstatic void 655186352Ssamnpe_mac_reset(struct npe_softc *sc) 656186352Ssam{ 657186352Ssam /* 658186352Ssam * Reset MAC core. 659186352Ssam */ 660186352Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 661186352Ssam DELAY(NPE_MAC_RESET_DELAY); 662186352Ssam /* configure MAC to generate MDC clock */ 663186352Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 664186352Ssam} 665186352Ssam 666186352Ssamstatic int 667164426Ssamnpe_activate(device_t dev) 668164426Ssam{ 669164426Ssam struct npe_softc * sc = device_get_softc(dev); 670186352Ssam int error, i, macbase, miibase; 671164426Ssam 672169954Ssam /* 673186352Ssam * Setup NEP ID, MAC, and MII bindings. We allow override 674186352Ssam * via hints to handle unexpected board configs. 675186352Ssam */ 676186352Ssam if (!override_npeid(dev, "npeid", &sc->sc_npeid)) 677186352Ssam sc->sc_npeid = unit2npeid(device_get_unit(dev)); 678186352Ssam sc->sc_npe = ixpnpe_attach(dev, sc->sc_npeid); 679186352Ssam if (sc->sc_npe == NULL) { 680186352Ssam device_printf(dev, "cannot attach ixpnpe\n"); 681186352Ssam return EIO; /* XXX */ 682186352Ssam } 683186352Ssam 684186352Ssam /* MAC */ 685186352Ssam if (!override_addr(dev, "mac", &macbase)) 686186352Ssam macbase = npeconfig[sc->sc_npeid].macbase; 687186352Ssam device_printf(sc->sc_dev, "MAC at 0x%x\n", macbase); 688186352Ssam if (bus_space_map(sc->sc_iot, macbase, IXP425_REG_SIZE, 0, &sc->sc_ioh)) { 689186352Ssam device_printf(dev, "cannot map mac registers 0x%x:0x%x\n", 690186352Ssam macbase, IXP425_REG_SIZE); 691186352Ssam return ENOMEM; 692186352Ssam } 693186352Ssam 694186352Ssam /* PHY */ 695186352Ssam if (!override_unit(dev, "phy", &sc->sc_phy, 0, MII_NPHY-1)) 696186352Ssam sc->sc_phy = npeconfig[sc->sc_npeid].phy; 697186352Ssam if (!override_addr(dev, "mii", &miibase)) 698186352Ssam miibase = npeconfig[sc->sc_npeid].miibase; 699186352Ssam device_printf(sc->sc_dev, "MII at 0x%x\n", miibase); 700186352Ssam if (miibase != macbase) { 701186352Ssam /* 702186352Ssam * PHY is mapped through a different MAC, setup an 703186352Ssam * additional mapping for frobbing the PHY registers. 704186352Ssam */ 705186352Ssam if (bus_space_map(sc->sc_iot, miibase, IXP425_REG_SIZE, 0, &sc->sc_miih)) { 706186352Ssam device_printf(dev, 707186352Ssam "cannot map MII registers 0x%x:0x%x\n", 708186352Ssam miibase, IXP425_REG_SIZE); 709186352Ssam return ENOMEM; 710186352Ssam } 711186352Ssam } else 712186352Ssam sc->sc_miih = sc->sc_ioh; 713186352Ssam 714186352Ssam /* 715186420Ssam * Load NPE firmware and start it running. 716169954Ssam */ 717186420Ssam error = ixpnpe_init(sc->sc_npe); 718186420Ssam if (error != 0) { 719186420Ssam device_printf(dev, "cannot init NPE (error %d)\n", error); 720186420Ssam return error; 721169954Ssam } 722164426Ssam 723186352Ssam /* probe for PHY */ 724186352Ssam if (mii_phy_probe(dev, &sc->sc_mii, npe_ifmedia_update, npe_ifmedia_status)) { 725186352Ssam device_printf(dev, "cannot find PHY %d.\n", sc->sc_phy); 726186352Ssam return ENXIO; 727177505Ssam } 728164426Ssam 729164426Ssam error = npe_dma_setup(sc, &sc->txdma, "tx", npe_txbuf, NPE_MAXSEG); 730164426Ssam if (error != 0) 731164426Ssam return error; 732164426Ssam error = npe_dma_setup(sc, &sc->rxdma, "rx", npe_rxbuf, 1); 733164426Ssam if (error != 0) 734164426Ssam return error; 735164426Ssam 736164426Ssam /* setup statistics block */ 737166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 738164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 739164426Ssam sizeof(struct npestats), 1, sizeof(struct npestats), 0, 740164426Ssam busdma_lock_mutex, &sc->sc_mtx, &sc->sc_stats_tag); 741164426Ssam if (error != 0) { 742164426Ssam device_printf(sc->sc_dev, "unable to create stats tag, " 743164426Ssam "error %u\n", error); 744164426Ssam return error; 745164426Ssam } 746164426Ssam if (bus_dmamem_alloc(sc->sc_stats_tag, (void **)&sc->sc_stats, 747164426Ssam BUS_DMA_NOWAIT, &sc->sc_stats_map) != 0) { 748164426Ssam device_printf(sc->sc_dev, 749164426Ssam "unable to allocate memory for stats block, error %u\n", 750164426Ssam error); 751164426Ssam return error; 752164426Ssam } 753164426Ssam if (bus_dmamap_load(sc->sc_stats_tag, sc->sc_stats_map, 754164426Ssam sc->sc_stats, sizeof(struct npestats), npe_getaddr, sc, 0) != 0) { 755164426Ssam device_printf(sc->sc_dev, 756164426Ssam "unable to load memory for stats block, error %u\n", 757164426Ssam error); 758164426Ssam return error; 759164426Ssam } 760164426Ssam sc->sc_stats_phys = sc->buf_phys; 761164426Ssam 762164426Ssam /* 763164426Ssam * Setup h/w rx/tx queues. There are four q's: 764164426Ssam * rx inbound q of rx'd frames 765164426Ssam * rx_free pool of ixpbuf's for receiving frames 766164426Ssam * tx outbound q of frames to send 767164426Ssam * tx_done q of tx frames that have been processed 768164426Ssam * 769164426Ssam * The NPE handles the actual tx/rx process and the q manager 770164426Ssam * handles the queues. The driver just writes entries to the 771164426Ssam * q manager mailbox's and gets callbacks when there are rx'd 772164426Ssam * frames to process or tx'd frames to reap. These callbacks 773164426Ssam * are controlled by the q configurations; e.g. we get a 774164426Ssam * callback when tx_done has 2 or more frames to process and 775164426Ssam * when the rx q has at least one frame. These setings can 776164426Ssam * changed at the time the q is configured. 777164426Ssam */ 778186352Ssam sc->rx_qid = npeconfig[sc->sc_npeid].rx_qid; 779164426Ssam ixpqmgr_qconfig(sc->rx_qid, npe_rxbuf, 0, 1, 780193096Sattilio IX_QMGR_Q_SOURCE_ID_NOT_E, (qconfig_hand_t *)npe_rxdone, sc); 781186352Ssam sc->rx_freeqid = npeconfig[sc->sc_npeid].rx_freeqid; 782164426Ssam ixpqmgr_qconfig(sc->rx_freeqid, npe_rxbuf, 0, npe_rxbuf/2, 0, NULL, sc); 783186352Ssam /* 784186352Ssam * Setup the NPE to direct all traffic to rx_qid. 785186352Ssam * When QoS is enabled in the firmware there are 786186352Ssam * 8 traffic classes; otherwise just 4. 787186352Ssam */ 788164426Ssam for (i = 0; i < 8; i++) 789164426Ssam npe_setrxqosentry(sc, i, 0, sc->rx_qid); 790164426Ssam 791186352Ssam /* disable firewall mode just in case (should be off) */ 792186352Ssam npe_setfirewallmode(sc, 0); 793186352Ssam 794186352Ssam sc->tx_qid = npeconfig[sc->sc_npeid].tx_qid; 795186352Ssam sc->tx_doneqid = npeconfig[sc->sc_npeid].tx_doneqid; 796164426Ssam ixpqmgr_qconfig(sc->tx_qid, npe_txbuf, 0, npe_txbuf, 0, NULL, sc); 797164426Ssam if (tx_doneqid == -1) { 798164426Ssam ixpqmgr_qconfig(sc->tx_doneqid, npe_txbuf, 0, 2, 799164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 800164426Ssam tx_doneqid = sc->tx_doneqid; 801164426Ssam } 802164426Ssam 803186352Ssam KASSERT(npes[sc->sc_npeid] == NULL, 804186352Ssam ("npe %u already setup", sc->sc_npeid)); 805186352Ssam npes[sc->sc_npeid] = sc; 806177505Ssam 807164426Ssam return 0; 808164426Ssam} 809164426Ssam 810164426Ssamstatic void 811164426Ssamnpe_deactivate(device_t dev) 812164426Ssam{ 813164426Ssam struct npe_softc *sc = device_get_softc(dev); 814164426Ssam 815186352Ssam npes[sc->sc_npeid] = NULL; 816164426Ssam 817164426Ssam /* XXX disable q's */ 818186352Ssam if (sc->sc_npe != NULL) { 819164426Ssam ixpnpe_stop(sc->sc_npe); 820186352Ssam ixpnpe_detach(sc->sc_npe); 821186352Ssam } 822164426Ssam if (sc->sc_stats != NULL) { 823164426Ssam bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 824164426Ssam bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 825164426Ssam sc->sc_stats_map); 826164426Ssam } 827164426Ssam if (sc->sc_stats_tag != NULL) 828164426Ssam bus_dma_tag_destroy(sc->sc_stats_tag); 829164426Ssam npe_dma_destroy(sc, &sc->txdma); 830164426Ssam npe_dma_destroy(sc, &sc->rxdma); 831164426Ssam bus_generic_detach(sc->sc_dev); 832186352Ssam if (sc->sc_mii != NULL) 833164426Ssam device_delete_child(sc->sc_dev, sc->sc_mii); 834164426Ssam} 835164426Ssam 836164426Ssam/* 837164426Ssam * Change media according to request. 838164426Ssam */ 839164426Ssamstatic int 840164426Ssamnpe_ifmedia_update(struct ifnet *ifp) 841164426Ssam{ 842164426Ssam struct npe_softc *sc = ifp->if_softc; 843164426Ssam struct mii_data *mii; 844164426Ssam 845164426Ssam mii = device_get_softc(sc->sc_mii); 846164426Ssam NPE_LOCK(sc); 847164426Ssam mii_mediachg(mii); 848164426Ssam /* XXX push state ourself? */ 849164426Ssam NPE_UNLOCK(sc); 850164426Ssam return (0); 851164426Ssam} 852164426Ssam 853164426Ssam/* 854164426Ssam * Notify the world which media we're using. 855164426Ssam */ 856164426Ssamstatic void 857164426Ssamnpe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 858164426Ssam{ 859164426Ssam struct npe_softc *sc = ifp->if_softc; 860164426Ssam struct mii_data *mii; 861164426Ssam 862164426Ssam mii = device_get_softc(sc->sc_mii); 863164426Ssam NPE_LOCK(sc); 864164426Ssam mii_pollstat(mii); 865164426Ssam ifmr->ifm_active = mii->mii_media_active; 866164426Ssam ifmr->ifm_status = mii->mii_media_status; 867164426Ssam NPE_UNLOCK(sc); 868164426Ssam} 869164426Ssam 870164426Ssamstatic void 871164426Ssamnpe_addstats(struct npe_softc *sc) 872164426Ssam{ 873192660Ssam#define NPEADD(x) sc->sc_totals.x += be32toh(ns->x) 874192660Ssam#define MIBADD(x) do { sc->mibdata.x += be32toh(ns->x); NPEADD(x); } while (0) 875164426Ssam struct ifnet *ifp = sc->sc_ifp; 876164426Ssam struct npestats *ns = sc->sc_stats; 877164426Ssam 878164426Ssam MIBADD(dot3StatsAlignmentErrors); 879164426Ssam MIBADD(dot3StatsFCSErrors); 880192660Ssam MIBADD(dot3StatsInternalMacReceiveErrors); 881192660Ssam NPEADD(RxOverrunDiscards); 882192660Ssam NPEADD(RxLearnedEntryDiscards); 883192660Ssam NPEADD(RxLargeFramesDiscards); 884192660Ssam NPEADD(RxSTPBlockedDiscards); 885192660Ssam NPEADD(RxVLANTypeFilterDiscards); 886192660Ssam NPEADD(RxVLANIdFilterDiscards); 887192660Ssam NPEADD(RxInvalidSourceDiscards); 888192660Ssam NPEADD(RxBlackListDiscards); 889192660Ssam NPEADD(RxWhiteListDiscards); 890192660Ssam NPEADD(RxUnderflowEntryDiscards); 891164426Ssam MIBADD(dot3StatsSingleCollisionFrames); 892164426Ssam MIBADD(dot3StatsMultipleCollisionFrames); 893164426Ssam MIBADD(dot3StatsDeferredTransmissions); 894164426Ssam MIBADD(dot3StatsLateCollisions); 895164426Ssam MIBADD(dot3StatsExcessiveCollisions); 896164426Ssam MIBADD(dot3StatsInternalMacTransmitErrors); 897164426Ssam MIBADD(dot3StatsCarrierSenseErrors); 898192660Ssam NPEADD(TxLargeFrameDiscards); 899192660Ssam NPEADD(TxVLANIdFilterDiscards); 900192660Ssam 901164426Ssam sc->mibdata.dot3StatsFrameTooLongs += 902164426Ssam be32toh(ns->RxLargeFramesDiscards) 903164426Ssam + be32toh(ns->TxLargeFrameDiscards); 904164426Ssam sc->mibdata.dot3StatsMissedFrames += 905164426Ssam be32toh(ns->RxOverrunDiscards) 906164426Ssam + be32toh(ns->RxUnderflowEntryDiscards); 907164426Ssam 908164426Ssam ifp->if_oerrors += 909164426Ssam be32toh(ns->dot3StatsInternalMacTransmitErrors) 910164426Ssam + be32toh(ns->dot3StatsCarrierSenseErrors) 911164426Ssam + be32toh(ns->TxVLANIdFilterDiscards) 912164426Ssam ; 913164426Ssam ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 914164426Ssam + be32toh(ns->dot3StatsInternalMacReceiveErrors) 915164426Ssam + be32toh(ns->RxOverrunDiscards) 916164426Ssam + be32toh(ns->RxUnderflowEntryDiscards) 917164426Ssam ; 918164426Ssam ifp->if_collisions += 919164426Ssam be32toh(ns->dot3StatsSingleCollisionFrames) 920164426Ssam + be32toh(ns->dot3StatsMultipleCollisionFrames) 921164426Ssam ; 922192660Ssam#undef NPEADD 923164426Ssam#undef MIBADD 924164426Ssam} 925164426Ssam 926164426Ssamstatic void 927164426Ssamnpe_tick(void *xsc) 928164426Ssam{ 929164426Ssam#define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 930164426Ssam struct npe_softc *sc = xsc; 931164426Ssam struct mii_data *mii = device_get_softc(sc->sc_mii); 932164426Ssam uint32_t msg[2]; 933164426Ssam 934164426Ssam NPE_ASSERT_LOCKED(sc); 935164426Ssam 936164426Ssam /* 937164426Ssam * NB: to avoid sleeping with the softc lock held we 938164426Ssam * split the NPE msg processing into two parts. The 939164426Ssam * request for statistics is sent w/o waiting for a 940164426Ssam * reply and then on the next tick we retrieve the 941164426Ssam * results. This works because npe_tick is the only 942164426Ssam * code that talks via the mailbox's (except at setup). 943164426Ssam * This likely can be handled better. 944164426Ssam */ 945186352Ssam if (ixpnpe_recvmsg_async(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 946164426Ssam bus_dmamap_sync(sc->sc_stats_tag, sc->sc_stats_map, 947164426Ssam BUS_DMASYNC_POSTREAD); 948164426Ssam npe_addstats(sc); 949164426Ssam } 950164426Ssam npe_updatestats(sc); 951164426Ssam mii_tick(mii); 952164426Ssam 953166339Skevlo npewatchdog(sc); 954166339Skevlo 955164426Ssam /* schedule next poll */ 956164426Ssam callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 957164426Ssam#undef ACK 958164426Ssam} 959164426Ssam 960164426Ssamstatic void 961164426Ssamnpe_setmac(struct npe_softc *sc, u_char *eaddr) 962164426Ssam{ 963164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 964164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 965164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 966164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 967164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 968164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 969164426Ssam} 970164426Ssam 971164426Ssamstatic void 972164426Ssamnpe_getmac(struct npe_softc *sc, u_char *eaddr) 973164426Ssam{ 974164426Ssam /* NB: the unicast address appears to be loaded from EEPROM on reset */ 975164426Ssam eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 976164426Ssam eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 977164426Ssam eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 978164426Ssam eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 979164426Ssam eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 980164426Ssam eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 981164426Ssam} 982164426Ssam 983164426Ssamstruct txdone { 984164426Ssam struct npebuf *head; 985164426Ssam struct npebuf **tail; 986164426Ssam int count; 987164426Ssam}; 988164426Ssam 989164426Ssamstatic __inline void 990164426Ssamnpe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 991164426Ssam{ 992164426Ssam struct ifnet *ifp = sc->sc_ifp; 993164426Ssam 994164426Ssam NPE_LOCK(sc); 995164426Ssam *td->tail = sc->tx_free; 996164426Ssam sc->tx_free = td->head; 997164426Ssam /* 998164426Ssam * We're no longer busy, so clear the busy flag and call the 999164426Ssam * start routine to xmit more packets. 1000164426Ssam */ 1001164426Ssam ifp->if_opackets += td->count; 1002164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1003166339Skevlo sc->npe_watchdog_timer = 0; 1004164426Ssam npestart_locked(ifp); 1005164426Ssam NPE_UNLOCK(sc); 1006164426Ssam} 1007164426Ssam 1008164426Ssam/* 1009164426Ssam * Q manager callback on tx done queue. Reap mbufs 1010164426Ssam * and return tx buffers to the free list. Finally 1011164426Ssam * restart output. Note the microcode has only one 1012164426Ssam * txdone q wired into it so we must use the NPE ID 1013164426Ssam * returned with each npehwbuf to decide where to 1014164426Ssam * send buffers. 1015164426Ssam */ 1016164426Ssamstatic void 1017164426Ssamnpe_txdone(int qid, void *arg) 1018164426Ssam{ 1019164426Ssam#define P2V(a, dma) \ 1020164426Ssam &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1021164426Ssam struct npe_softc *sc0 = arg; 1022164426Ssam struct npe_softc *sc; 1023164426Ssam struct npebuf *npe; 1024164426Ssam struct txdone *td, q[NPE_MAX]; 1025164426Ssam uint32_t entry; 1026164426Ssam 1027164426Ssam /* XXX no NPE-A support */ 1028164426Ssam q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 1029164426Ssam q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 1030164426Ssam /* XXX max # at a time? */ 1031164426Ssam while (ixpqmgr_qread(qid, &entry) == 0) { 1032164426Ssam DPRINTF(sc0, "%s: entry 0x%x NPE %u port %u\n", 1033164426Ssam __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 1034164426Ssam 1035164426Ssam sc = npes[NPE_QM_Q_NPE(entry)]; 1036164426Ssam npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 1037164426Ssam m_freem(npe->ix_m); 1038164426Ssam npe->ix_m = NULL; 1039164426Ssam 1040164426Ssam td = &q[NPE_QM_Q_NPE(entry)]; 1041164426Ssam *td->tail = npe; 1042164426Ssam td->tail = &npe->ix_next; 1043164426Ssam td->count++; 1044164426Ssam } 1045164426Ssam 1046164426Ssam if (q[NPE_B].count) 1047164426Ssam npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 1048164426Ssam if (q[NPE_C].count) 1049164426Ssam npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 1050164426Ssam#undef P2V 1051164426Ssam} 1052164426Ssam 1053164426Ssamstatic int 1054164426Ssamnpe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 1055164426Ssam{ 1056164426Ssam bus_dma_segment_t segs[1]; 1057164426Ssam struct npedma *dma = &sc->rxdma; 1058164426Ssam struct npehwbuf *hw; 1059164426Ssam int error, nseg; 1060164426Ssam 1061164426Ssam if (m == NULL) { 1062164426Ssam m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1063164426Ssam if (m == NULL) 1064164426Ssam return ENOBUFS; 1065164426Ssam } 1066164426Ssam KASSERT(m->m_ext.ext_size >= 1536 + ETHER_ALIGN, 1067164426Ssam ("ext_size %d", m->m_ext.ext_size)); 1068164426Ssam m->m_pkthdr.len = m->m_len = 1536; 1069164426Ssam /* backload payload and align ip hdr */ 1070164426Ssam m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN)); 1071164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, m, 1072164426Ssam segs, &nseg, 0); 1073164426Ssam if (error != 0) { 1074164426Ssam m_freem(m); 1075164426Ssam return error; 1076164426Ssam } 1077164426Ssam hw = npe->ix_hw; 1078164426Ssam hw->ix_ne[0].data = htobe32(segs[0].ds_addr); 1079164426Ssam /* NB: NPE requires length be a multiple of 64 */ 1080164426Ssam /* NB: buffer length is shifted in word */ 1081164426Ssam hw->ix_ne[0].len = htobe32(segs[0].ds_len << 16); 1082164426Ssam hw->ix_ne[0].next = 0; 1083164426Ssam npe->ix_m = m; 1084164426Ssam /* Flush the memory in the mbuf */ 1085164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREREAD); 1086164426Ssam return 0; 1087164426Ssam} 1088164426Ssam 1089164426Ssam/* 1090164426Ssam * RX q processing for a specific NPE. Claim entries 1091164426Ssam * from the hardware queue and pass the frames up the 1092164426Ssam * stack. Pass the rx buffers to the free list. 1093164426Ssam */ 1094193096Sattiliostatic int 1095164426Ssamnpe_rxdone(int qid, void *arg) 1096164426Ssam{ 1097164426Ssam#define P2V(a, dma) \ 1098164426Ssam &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1099164426Ssam struct npe_softc *sc = arg; 1100164426Ssam struct npedma *dma = &sc->rxdma; 1101164426Ssam uint32_t entry; 1102193096Sattilio int rx_npkts = 0; 1103164426Ssam 1104164426Ssam while (ixpqmgr_qread(qid, &entry) == 0) { 1105164426Ssam struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 1106164426Ssam struct mbuf *m; 1107164426Ssam 1108164426Ssam DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 1109164426Ssam __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 1110164426Ssam /* 1111164426Ssam * Allocate a new mbuf to replenish the rx buffer. 1112164426Ssam * If doing so fails we drop the rx'd frame so we 1113164426Ssam * can reuse the previous mbuf. When we're able to 1114164426Ssam * allocate a new mbuf dispatch the mbuf w/ rx'd 1115164426Ssam * data up the stack and replace it with the newly 1116164426Ssam * allocated one. 1117164426Ssam */ 1118164426Ssam m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1119164426Ssam if (m != NULL) { 1120164426Ssam struct mbuf *mrx = npe->ix_m; 1121164426Ssam struct npehwbuf *hw = npe->ix_hw; 1122164426Ssam struct ifnet *ifp = sc->sc_ifp; 1123164426Ssam 1124164426Ssam /* Flush mbuf memory for rx'd data */ 1125164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, 1126164426Ssam BUS_DMASYNC_POSTREAD); 1127164426Ssam 1128164426Ssam /* XXX flush hw buffer; works now 'cuz coherent */ 1129164426Ssam /* set m_len etc. per rx frame size */ 1130164426Ssam mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 1131164426Ssam mrx->m_pkthdr.len = mrx->m_len; 1132164426Ssam mrx->m_pkthdr.rcvif = ifp; 1133164426Ssam 1134164426Ssam ifp->if_ipackets++; 1135164426Ssam ifp->if_input(ifp, mrx); 1136193096Sattilio rx_npkts++; 1137164426Ssam } else { 1138164426Ssam /* discard frame and re-use mbuf */ 1139164426Ssam m = npe->ix_m; 1140164426Ssam } 1141164426Ssam if (npe_rxbuf_init(sc, npe, m) == 0) { 1142164426Ssam /* return npe buf to rx free list */ 1143164426Ssam ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1144164426Ssam } else { 1145164426Ssam /* XXX should not happen */ 1146164426Ssam } 1147164426Ssam } 1148193104Ssam return rx_npkts; 1149164426Ssam#undef P2V 1150164426Ssam} 1151164426Ssam 1152164426Ssam#ifdef DEVICE_POLLING 1153193096Sattiliostatic int 1154164426Ssamnpe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1155164426Ssam{ 1156164426Ssam struct npe_softc *sc = ifp->if_softc; 1157193096Sattilio int rx_npkts = 0; 1158164426Ssam 1159164426Ssam if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1160193096Sattilio rx_npkts = npe_rxdone(sc->rx_qid, sc); 1161164426Ssam npe_txdone(sc->tx_doneqid, sc); /* XXX polls both NPE's */ 1162164426Ssam } 1163193104Ssam return rx_npkts; 1164164426Ssam} 1165164426Ssam#endif /* DEVICE_POLLING */ 1166164426Ssam 1167164426Ssamstatic void 1168164426Ssamnpe_startxmit(struct npe_softc *sc) 1169164426Ssam{ 1170164426Ssam struct npedma *dma = &sc->txdma; 1171164426Ssam int i; 1172164426Ssam 1173164426Ssam NPE_ASSERT_LOCKED(sc); 1174164426Ssam sc->tx_free = NULL; 1175164426Ssam for (i = 0; i < dma->nbuf; i++) { 1176164426Ssam struct npebuf *npe = &dma->buf[i]; 1177164426Ssam if (npe->ix_m != NULL) { 1178164426Ssam /* NB: should not happen */ 1179164426Ssam device_printf(sc->sc_dev, 1180164426Ssam "%s: free mbuf at entry %u\n", __func__, i); 1181164426Ssam m_freem(npe->ix_m); 1182164426Ssam } 1183164426Ssam npe->ix_m = NULL; 1184164426Ssam npe->ix_next = sc->tx_free; 1185164426Ssam sc->tx_free = npe; 1186164426Ssam } 1187164426Ssam} 1188164426Ssam 1189164426Ssamstatic void 1190164426Ssamnpe_startrecv(struct npe_softc *sc) 1191164426Ssam{ 1192164426Ssam struct npedma *dma = &sc->rxdma; 1193164426Ssam struct npebuf *npe; 1194164426Ssam int i; 1195164426Ssam 1196164426Ssam NPE_ASSERT_LOCKED(sc); 1197164426Ssam for (i = 0; i < dma->nbuf; i++) { 1198164426Ssam npe = &dma->buf[i]; 1199164426Ssam npe_rxbuf_init(sc, npe, npe->ix_m); 1200164426Ssam /* set npe buf on rx free list */ 1201164426Ssam ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1202164426Ssam } 1203164426Ssam} 1204164426Ssam 1205164426Ssam/* 1206164426Ssam * Reset and initialize the chip 1207164426Ssam */ 1208164426Ssamstatic void 1209164426Ssamnpeinit_locked(void *xsc) 1210164426Ssam{ 1211164426Ssam struct npe_softc *sc = xsc; 1212164426Ssam struct ifnet *ifp = sc->sc_ifp; 1213164426Ssam 1214164426Ssam NPE_ASSERT_LOCKED(sc); 1215164426Ssamif (ifp->if_drv_flags & IFF_DRV_RUNNING) return;/*XXX*/ 1216164426Ssam 1217164426Ssam /* 1218164426Ssam * Reset MAC core. 1219164426Ssam */ 1220186352Ssam npe_mac_reset(sc); 1221164426Ssam 1222164426Ssam /* disable transmitter and reciver in the MAC */ 1223164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1224164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1225164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1226164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1227164426Ssam 1228164426Ssam /* 1229164426Ssam * Set the MAC core registers. 1230164426Ssam */ 1231164426Ssam WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1232164426Ssam WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1233164426Ssam WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1234164426Ssam /* thresholds determined by NPE firmware FS */ 1235164426Ssam WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1236164426Ssam WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1237164426Ssam WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */ 1238164426Ssam WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1239164426Ssam WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1240164426Ssam WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1241164426Ssam WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1242164426Ssam WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */ 1243164426Ssam 1244164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1245164426Ssam NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1246164426Ssam | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1247164426Ssam | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1248164426Ssam | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1249164426Ssam /* XXX pad strip? */ 1250189642Ssam /* ena pause frame handling */ 1251189642Ssam WR4(sc, NPE_MAC_RX_CNTRL1, NPE_RX_CNTRL1_PAUSE_EN); 1252164426Ssam WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1253164426Ssam 1254164426Ssam npe_setmac(sc, IF_LLADDR(ifp)); 1255164426Ssam npe_setmcast(sc); 1256164426Ssam 1257164426Ssam npe_startxmit(sc); 1258164426Ssam npe_startrecv(sc); 1259164426Ssam 1260164426Ssam ifp->if_drv_flags |= IFF_DRV_RUNNING; 1261164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1262166339Skevlo sc->npe_watchdog_timer = 0; /* just in case */ 1263164426Ssam 1264164426Ssam /* enable transmitter and reciver in the MAC */ 1265164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1266164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1267164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1268164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1269164426Ssam 1270164426Ssam callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 1271164426Ssam} 1272164426Ssam 1273164426Ssamstatic void 1274164426Ssamnpeinit(void *xsc) 1275164426Ssam{ 1276164426Ssam struct npe_softc *sc = xsc; 1277164426Ssam NPE_LOCK(sc); 1278164426Ssam npeinit_locked(sc); 1279164426Ssam NPE_UNLOCK(sc); 1280164426Ssam} 1281164426Ssam 1282164426Ssam/* 1283164426Ssam * Dequeue packets and place on the h/w transmit queue. 1284164426Ssam */ 1285164426Ssamstatic void 1286164426Ssamnpestart_locked(struct ifnet *ifp) 1287164426Ssam{ 1288164426Ssam struct npe_softc *sc = ifp->if_softc; 1289164426Ssam struct npebuf *npe; 1290164426Ssam struct npehwbuf *hw; 1291164426Ssam struct mbuf *m, *n; 1292164426Ssam struct npedma *dma = &sc->txdma; 1293164426Ssam bus_dma_segment_t segs[NPE_MAXSEG]; 1294164426Ssam int nseg, len, error, i; 1295164426Ssam uint32_t next; 1296164426Ssam 1297164426Ssam NPE_ASSERT_LOCKED(sc); 1298164426Ssam /* XXX can this happen? */ 1299164426Ssam if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1300164426Ssam return; 1301164426Ssam 1302164426Ssam while (sc->tx_free != NULL) { 1303164426Ssam IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1304164426Ssam if (m == NULL) { 1305164426Ssam /* XXX? */ 1306164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1307164426Ssam return; 1308164426Ssam } 1309164426Ssam npe = sc->tx_free; 1310164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1311164426Ssam m, segs, &nseg, 0); 1312164426Ssam if (error == EFBIG) { 1313175418Sjhb n = m_collapse(m, M_DONTWAIT, NPE_MAXSEG); 1314164426Ssam if (n == NULL) { 1315164426Ssam if_printf(ifp, "%s: too many fragments %u\n", 1316164426Ssam __func__, nseg); 1317164426Ssam m_freem(m); 1318164426Ssam return; /* XXX? */ 1319164426Ssam } 1320164426Ssam m = n; 1321164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1322164426Ssam m, segs, &nseg, 0); 1323164426Ssam } 1324164426Ssam if (error != 0 || nseg == 0) { 1325164426Ssam if_printf(ifp, "%s: error %u nseg %u\n", 1326164426Ssam __func__, error, nseg); 1327164426Ssam m_freem(m); 1328164426Ssam return; /* XXX? */ 1329164426Ssam } 1330164426Ssam sc->tx_free = npe->ix_next; 1331164426Ssam 1332164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREWRITE); 1333164426Ssam 1334164426Ssam /* 1335164426Ssam * Tap off here if there is a bpf listener. 1336164426Ssam */ 1337164426Ssam BPF_MTAP(ifp, m); 1338164426Ssam 1339164426Ssam npe->ix_m = m; 1340164426Ssam hw = npe->ix_hw; 1341164426Ssam len = m->m_pkthdr.len; 1342164426Ssam next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1343164426Ssam for (i = 0; i < nseg; i++) { 1344164426Ssam hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1345164426Ssam hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1346164426Ssam hw->ix_ne[i].next = htobe32(next); 1347164426Ssam 1348164426Ssam len = 0; /* zero for segments > 1 */ 1349164426Ssam next += sizeof(hw->ix_ne[0]); 1350164426Ssam } 1351164426Ssam hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1352164426Ssam /* XXX flush descriptor instead of using uncached memory */ 1353164426Ssam 1354164426Ssam DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1355164426Ssam __func__, sc->tx_qid, npe->ix_neaddr, 1356164426Ssam hw->ix_ne[0].data, hw->ix_ne[0].len); 1357164426Ssam /* stick it on the tx q */ 1358164426Ssam /* XXX add vlan priority */ 1359164426Ssam ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1360164426Ssam 1361166339Skevlo sc->npe_watchdog_timer = 5; 1362164426Ssam } 1363164426Ssam if (sc->tx_free == NULL) 1364164426Ssam ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1365164426Ssam} 1366164426Ssam 1367164426Ssamvoid 1368164426Ssamnpestart(struct ifnet *ifp) 1369164426Ssam{ 1370164426Ssam struct npe_softc *sc = ifp->if_softc; 1371164426Ssam NPE_LOCK(sc); 1372164426Ssam npestart_locked(ifp); 1373164426Ssam NPE_UNLOCK(sc); 1374164426Ssam} 1375164426Ssam 1376164426Ssamstatic void 1377164426Ssamnpe_stopxmit(struct npe_softc *sc) 1378164426Ssam{ 1379164426Ssam struct npedma *dma = &sc->txdma; 1380164426Ssam int i; 1381164426Ssam 1382164426Ssam NPE_ASSERT_LOCKED(sc); 1383164426Ssam 1384164426Ssam /* XXX qmgr */ 1385164426Ssam for (i = 0; i < dma->nbuf; i++) { 1386164426Ssam struct npebuf *npe = &dma->buf[i]; 1387164426Ssam 1388164426Ssam if (npe->ix_m != NULL) { 1389164426Ssam bus_dmamap_unload(dma->mtag, npe->ix_map); 1390164426Ssam m_freem(npe->ix_m); 1391164426Ssam npe->ix_m = NULL; 1392164426Ssam } 1393164426Ssam } 1394164426Ssam} 1395164426Ssam 1396164426Ssamstatic void 1397164426Ssamnpe_stoprecv(struct npe_softc *sc) 1398164426Ssam{ 1399164426Ssam struct npedma *dma = &sc->rxdma; 1400164426Ssam int i; 1401164426Ssam 1402164426Ssam NPE_ASSERT_LOCKED(sc); 1403164426Ssam 1404164426Ssam /* XXX qmgr */ 1405164426Ssam for (i = 0; i < dma->nbuf; i++) { 1406164426Ssam struct npebuf *npe = &dma->buf[i]; 1407164426Ssam 1408164426Ssam if (npe->ix_m != NULL) { 1409164426Ssam bus_dmamap_unload(dma->mtag, npe->ix_map); 1410164426Ssam m_freem(npe->ix_m); 1411164426Ssam npe->ix_m = NULL; 1412164426Ssam } 1413164426Ssam } 1414164426Ssam} 1415164426Ssam 1416164426Ssam/* 1417164426Ssam * Turn off interrupts, and stop the nic. 1418164426Ssam */ 1419164426Ssamvoid 1420164426Ssamnpestop(struct npe_softc *sc) 1421164426Ssam{ 1422164426Ssam struct ifnet *ifp = sc->sc_ifp; 1423164426Ssam 1424164426Ssam /* disable transmitter and reciver in the MAC */ 1425164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1426164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1427164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1428164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1429164426Ssam 1430166339Skevlo sc->npe_watchdog_timer = 0; 1431164426Ssam ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1432164426Ssam 1433164426Ssam callout_stop(&sc->tick_ch); 1434164426Ssam 1435164426Ssam npe_stopxmit(sc); 1436164426Ssam npe_stoprecv(sc); 1437164426Ssam /* XXX go into loopback & drain q's? */ 1438164426Ssam /* XXX but beware of disabling tx above */ 1439164426Ssam 1440164426Ssam /* 1441164426Ssam * The MAC core rx/tx disable may leave the MAC hardware in an 1442164426Ssam * unpredictable state. A hw reset is executed before resetting 1443164426Ssam * all the MAC parameters to a known value. 1444164426Ssam */ 1445164426Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1446164426Ssam DELAY(NPE_MAC_RESET_DELAY); 1447164426Ssam WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1448164426Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1449164426Ssam} 1450164426Ssam 1451164426Ssamvoid 1452166339Skevlonpewatchdog(struct npe_softc *sc) 1453164426Ssam{ 1454166339Skevlo NPE_ASSERT_LOCKED(sc); 1455164426Ssam 1456166339Skevlo if (sc->npe_watchdog_timer == 0 || --sc->npe_watchdog_timer != 0) 1457166339Skevlo return; 1458166339Skevlo 1459166339Skevlo device_printf(sc->sc_dev, "watchdog timeout\n"); 1460166339Skevlo sc->sc_ifp->if_oerrors++; 1461166339Skevlo 1462164426Ssam npeinit_locked(sc); 1463164426Ssam} 1464164426Ssam 1465164426Ssamstatic int 1466164426Ssamnpeioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1467164426Ssam{ 1468164426Ssam struct npe_softc *sc = ifp->if_softc; 1469164426Ssam struct mii_data *mii; 1470164426Ssam struct ifreq *ifr = (struct ifreq *)data; 1471164426Ssam int error = 0; 1472164426Ssam#ifdef DEVICE_POLLING 1473164426Ssam int mask; 1474164426Ssam#endif 1475164426Ssam 1476164426Ssam switch (cmd) { 1477164426Ssam case SIOCSIFFLAGS: 1478164426Ssam NPE_LOCK(sc); 1479164426Ssam if ((ifp->if_flags & IFF_UP) == 0 && 1480164426Ssam ifp->if_drv_flags & IFF_DRV_RUNNING) { 1481164426Ssam ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1482164426Ssam npestop(sc); 1483164426Ssam } else { 1484164426Ssam /* reinitialize card on any parameter change */ 1485164426Ssam npeinit_locked(sc); 1486164426Ssam } 1487164426Ssam NPE_UNLOCK(sc); 1488164426Ssam break; 1489164426Ssam 1490164426Ssam case SIOCADDMULTI: 1491164426Ssam case SIOCDELMULTI: 1492164426Ssam /* update multicast filter list. */ 1493164426Ssam NPE_LOCK(sc); 1494164426Ssam npe_setmcast(sc); 1495164426Ssam NPE_UNLOCK(sc); 1496164426Ssam error = 0; 1497164426Ssam break; 1498164426Ssam 1499164426Ssam case SIOCSIFMEDIA: 1500164426Ssam case SIOCGIFMEDIA: 1501164426Ssam mii = device_get_softc(sc->sc_mii); 1502164426Ssam error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1503164426Ssam break; 1504164426Ssam 1505164426Ssam#ifdef DEVICE_POLLING 1506164426Ssam case SIOCSIFCAP: 1507164426Ssam mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1508164426Ssam if (mask & IFCAP_POLLING) { 1509164426Ssam if (ifr->ifr_reqcap & IFCAP_POLLING) { 1510164426Ssam error = ether_poll_register(npe_poll, ifp); 1511164426Ssam if (error) 1512164426Ssam return error; 1513164426Ssam NPE_LOCK(sc); 1514164426Ssam /* disable callbacks XXX txdone is shared */ 1515164426Ssam ixpqmgr_notify_disable(sc->rx_qid); 1516164426Ssam ixpqmgr_notify_disable(sc->tx_doneqid); 1517164426Ssam ifp->if_capenable |= IFCAP_POLLING; 1518164426Ssam NPE_UNLOCK(sc); 1519164426Ssam } else { 1520164426Ssam error = ether_poll_deregister(ifp); 1521164426Ssam /* NB: always enable qmgr callbacks */ 1522164426Ssam NPE_LOCK(sc); 1523164426Ssam /* enable qmgr callbacks */ 1524164426Ssam ixpqmgr_notify_enable(sc->rx_qid, 1525164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E); 1526164426Ssam ixpqmgr_notify_enable(sc->tx_doneqid, 1527164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E); 1528164426Ssam ifp->if_capenable &= ~IFCAP_POLLING; 1529164426Ssam NPE_UNLOCK(sc); 1530164426Ssam } 1531164426Ssam } 1532164426Ssam break; 1533164426Ssam#endif 1534164426Ssam default: 1535164426Ssam error = ether_ioctl(ifp, cmd, data); 1536164426Ssam break; 1537164426Ssam } 1538164426Ssam return error; 1539164426Ssam} 1540164426Ssam 1541164426Ssam/* 1542164426Ssam * Setup a traffic class -> rx queue mapping. 1543164426Ssam */ 1544164426Ssamstatic int 1545164426Ssamnpe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1546164426Ssam{ 1547164426Ssam uint32_t msg[2]; 1548164426Ssam 1549186352Ssam msg[0] = (NPE_SETRXQOSENTRY << 24) | (sc->sc_npeid << 20) | classix; 1550164426Ssam msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1551186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1552164426Ssam} 1553164426Ssam 1554186352Ssamstatic int 1555186352Ssamnpe_setfirewallmode(struct npe_softc *sc, int onoff) 1556186352Ssam{ 1557186352Ssam uint32_t msg[2]; 1558186352Ssam 1559186352Ssam /* XXX honor onoff */ 1560186352Ssam msg[0] = (NPE_SETFIREWALLMODE << 24) | (sc->sc_npeid << 20); 1561186352Ssam msg[1] = 0; 1562186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1563186352Ssam} 1564186352Ssam 1565164426Ssam/* 1566164426Ssam * Update and reset the statistics in the NPE. 1567164426Ssam */ 1568164426Ssamstatic int 1569164426Ssamnpe_updatestats(struct npe_softc *sc) 1570164426Ssam{ 1571164426Ssam uint32_t msg[2]; 1572164426Ssam 1573164426Ssam msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1574164426Ssam msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1575186352Ssam return ixpnpe_sendmsg_async(sc->sc_npe, msg); 1576164426Ssam} 1577164426Ssam 1578164426Ssam#if 0 1579164426Ssam/* 1580164426Ssam * Get the current statistics block. 1581164426Ssam */ 1582164426Ssamstatic int 1583164426Ssamnpe_getstats(struct npe_softc *sc) 1584164426Ssam{ 1585164426Ssam uint32_t msg[2]; 1586164426Ssam 1587164426Ssam msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1588164426Ssam msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1589164426Ssam return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1590164426Ssam} 1591164426Ssam 1592164426Ssam/* 1593164426Ssam * Query the image id of the loaded firmware. 1594164426Ssam */ 1595164426Ssamstatic uint32_t 1596164426Ssamnpe_getimageid(struct npe_softc *sc) 1597164426Ssam{ 1598164426Ssam uint32_t msg[2]; 1599164426Ssam 1600164426Ssam msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1601164426Ssam msg[1] = 0; 1602186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1603164426Ssam} 1604164426Ssam 1605164426Ssam/* 1606164426Ssam * Enable/disable loopback. 1607164426Ssam */ 1608164426Ssamstatic int 1609164426Ssamnpe_setloopback(struct npe_softc *sc, int ena) 1610164426Ssam{ 1611164426Ssam uint32_t msg[2]; 1612164426Ssam 1613164426Ssam msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1614164426Ssam msg[1] = 0; 1615186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1616164426Ssam} 1617164426Ssam#endif 1618164426Ssam 1619164426Ssamstatic void 1620164426Ssamnpe_child_detached(device_t dev, device_t child) 1621164426Ssam{ 1622164426Ssam struct npe_softc *sc; 1623164426Ssam 1624164426Ssam sc = device_get_softc(dev); 1625164426Ssam if (child == sc->sc_mii) 1626164426Ssam sc->sc_mii = NULL; 1627164426Ssam} 1628164426Ssam 1629164426Ssam/* 1630164426Ssam * MII bus support routines. 1631164426Ssam */ 1632186352Ssam#define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1633186352Ssam#define MII_WR4(sc, reg, v) \ 1634186352Ssam bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1635186352Ssam 1636164426Ssamstatic uint32_t 1637164426Ssamnpe_mii_mdio_read(struct npe_softc *sc, int reg) 1638164426Ssam{ 1639164426Ssam uint32_t v; 1640164426Ssam 1641164426Ssam /* NB: registers are known to be sequential */ 1642164426Ssam v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1643164426Ssam v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1644164426Ssam v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1645164426Ssam v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1646164426Ssam return v; 1647164426Ssam} 1648164426Ssam 1649164426Ssamstatic void 1650164426Ssamnpe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1651164426Ssam{ 1652164426Ssam /* NB: registers are known to be sequential */ 1653164426Ssam MII_WR4(sc, reg+0, cmd & 0xff); 1654164426Ssam MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1655164426Ssam MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1656164426Ssam MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1657164426Ssam} 1658164426Ssam 1659164426Ssamstatic int 1660164426Ssamnpe_mii_mdio_wait(struct npe_softc *sc) 1661164426Ssam{ 1662164426Ssam uint32_t v; 1663164426Ssam int i; 1664164426Ssam 1665186352Ssam /* NB: typically this takes 25-30 trips */ 1666186352Ssam for (i = 0; i < 1000; i++) { 1667164426Ssam v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1668164426Ssam if ((v & NPE_MII_GO) == 0) 1669164426Ssam return 1; 1670186352Ssam DELAY(1); 1671164426Ssam } 1672186352Ssam device_printf(sc->sc_dev, "%s: timeout after ~1ms, cmd 0x%x\n", 1673186352Ssam __func__, v); 1674164426Ssam return 0; /* NB: timeout */ 1675164426Ssam} 1676164426Ssam 1677164426Ssamstatic int 1678164426Ssamnpe_miibus_readreg(device_t dev, int phy, int reg) 1679164426Ssam{ 1680164426Ssam struct npe_softc *sc = device_get_softc(dev); 1681164426Ssam uint32_t v; 1682164426Ssam 1683177505Ssam if (phy != sc->sc_phy) /* XXX no auto-detect */ 1684164426Ssam return 0xffff; 1685186352Ssam v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) | NPE_MII_GO; 1686164426Ssam npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1687164426Ssam if (npe_mii_mdio_wait(sc)) 1688164426Ssam v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1689164426Ssam else 1690164426Ssam v = 0xffff | NPE_MII_READ_FAIL; 1691164426Ssam return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1692164426Ssam} 1693164426Ssam 1694164426Ssamstatic void 1695164426Ssamnpe_miibus_writereg(device_t dev, int phy, int reg, int data) 1696164426Ssam{ 1697164426Ssam struct npe_softc *sc = device_get_softc(dev); 1698164426Ssam uint32_t v; 1699164426Ssam 1700177505Ssam if (phy != sc->sc_phy) /* XXX */ 1701164426Ssam return; 1702164426Ssam v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1703164426Ssam | data | NPE_MII_WRITE 1704164426Ssam | NPE_MII_GO; 1705164426Ssam npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1706164426Ssam /* XXX complain about timeout */ 1707164426Ssam (void) npe_mii_mdio_wait(sc); 1708164426Ssam} 1709164426Ssam 1710164426Ssamstatic void 1711164426Ssamnpe_miibus_statchg(device_t dev) 1712164426Ssam{ 1713164426Ssam struct npe_softc *sc = device_get_softc(dev); 1714164426Ssam struct mii_data *mii = device_get_softc(sc->sc_mii); 1715164426Ssam uint32_t tx1, rx1; 1716164426Ssam 1717164426Ssam /* sync MAC duplex state */ 1718164426Ssam tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1719164426Ssam rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1720164426Ssam if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1721164426Ssam tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1722164426Ssam rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1723164426Ssam } else { 1724164426Ssam tx1 |= NPE_TX_CNTRL1_DUPLEX; 1725164426Ssam rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1726164426Ssam } 1727164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1728164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1729164426Ssam} 1730164426Ssam 1731164426Ssamstatic device_method_t npe_methods[] = { 1732164426Ssam /* Device interface */ 1733164426Ssam DEVMETHOD(device_probe, npe_probe), 1734164426Ssam DEVMETHOD(device_attach, npe_attach), 1735164426Ssam DEVMETHOD(device_detach, npe_detach), 1736164426Ssam 1737164426Ssam /* Bus interface */ 1738164426Ssam DEVMETHOD(bus_child_detached, npe_child_detached), 1739164426Ssam 1740164426Ssam /* MII interface */ 1741164426Ssam DEVMETHOD(miibus_readreg, npe_miibus_readreg), 1742164426Ssam DEVMETHOD(miibus_writereg, npe_miibus_writereg), 1743164426Ssam DEVMETHOD(miibus_statchg, npe_miibus_statchg), 1744164426Ssam 1745164426Ssam { 0, 0 } 1746164426Ssam}; 1747164426Ssam 1748164426Ssamstatic driver_t npe_driver = { 1749164426Ssam "npe", 1750164426Ssam npe_methods, 1751164426Ssam sizeof(struct npe_softc), 1752164426Ssam}; 1753164426Ssam 1754164426SsamDRIVER_MODULE(npe, ixp, npe_driver, npe_devclass, 0, 0); 1755164426SsamDRIVER_MODULE(miibus, npe, miibus_driver, miibus_devclass, 0, 0); 1756164426SsamMODULE_DEPEND(npe, ixpqmgr, 1, 1, 1); 1757164426SsamMODULE_DEPEND(npe, miibus, 1, 1, 1); 1758164426SsamMODULE_DEPEND(npe, ether, 1, 1, 1); 1759