if_npe.c revision 189645
1164426Ssam/*- 2177505Ssam * Copyright (c) 2006-2008 Sam Leffler. All rights reserved. 3164426Ssam * 4164426Ssam * Redistribution and use in source and binary forms, with or without 5164426Ssam * modification, are permitted provided that the following conditions 6164426Ssam * are met: 7164426Ssam * 1. Redistributions of source code must retain the above copyright 8164426Ssam * notice, this list of conditions and the following disclaimer. 9164426Ssam * 2. Redistributions in binary form must reproduce the above copyright 10164426Ssam * notice, this list of conditions and the following disclaimer in the 11164426Ssam * documentation and/or other materials provided with the distribution. 12164426Ssam * 13164426Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14164426Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15164426Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16164426Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17164426Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18164426Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19164426Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20164426Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21164426Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22164426Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23164426Ssam */ 24164426Ssam 25164426Ssam#include <sys/cdefs.h> 26164426Ssam__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/if_npe.c 189645 2009-03-10 19:35:37Z sam $"); 27164426Ssam 28164426Ssam/* 29164426Ssam * Intel XScale NPE Ethernet driver. 30164426Ssam * 31164426Ssam * This driver handles the two ports present on the IXP425. 32164426Ssam * Packet processing is done by the Network Processing Engines 33164426Ssam * (NPE's) that work together with a MAC and PHY. The MAC 34164426Ssam * is also mapped to the XScale cpu; the PHY is accessed via 35164426Ssam * the MAC. NPE-XScale communication happens through h/w 36164426Ssam * queues managed by the Q Manager block. 37164426Ssam * 38164426Ssam * The code here replaces the ethAcc, ethMii, and ethDB classes 39164426Ssam * in the Intel Access Library (IAL) and the OS-specific driver. 40164426Ssam * 41164426Ssam * XXX add vlan support 42164426Ssam */ 43164426Ssam#ifdef HAVE_KERNEL_OPTION_HEADERS 44164426Ssam#include "opt_device_polling.h" 45164426Ssam#endif 46164426Ssam 47164426Ssam#include <sys/param.h> 48164426Ssam#include <sys/systm.h> 49164426Ssam#include <sys/bus.h> 50164426Ssam#include <sys/kernel.h> 51164426Ssam#include <sys/mbuf.h> 52164426Ssam#include <sys/malloc.h> 53164426Ssam#include <sys/module.h> 54164426Ssam#include <sys/rman.h> 55164426Ssam#include <sys/socket.h> 56164426Ssam#include <sys/sockio.h> 57164426Ssam#include <sys/sysctl.h> 58164426Ssam#include <sys/endian.h> 59164426Ssam#include <machine/bus.h> 60164426Ssam 61164426Ssam#include <net/ethernet.h> 62164426Ssam#include <net/if.h> 63164426Ssam#include <net/if_arp.h> 64164426Ssam#include <net/if_dl.h> 65164426Ssam#include <net/if_media.h> 66164426Ssam#include <net/if_mib.h> 67164426Ssam#include <net/if_types.h> 68164426Ssam 69164426Ssam#ifdef INET 70164426Ssam#include <netinet/in.h> 71164426Ssam#include <netinet/in_systm.h> 72164426Ssam#include <netinet/in_var.h> 73164426Ssam#include <netinet/ip.h> 74164426Ssam#endif 75164426Ssam 76164426Ssam#include <net/bpf.h> 77164426Ssam#include <net/bpfdesc.h> 78164426Ssam 79164426Ssam#include <arm/xscale/ixp425/ixp425reg.h> 80164426Ssam#include <arm/xscale/ixp425/ixp425var.h> 81164426Ssam#include <arm/xscale/ixp425/ixp425_qmgr.h> 82164426Ssam#include <arm/xscale/ixp425/ixp425_npevar.h> 83164426Ssam 84164426Ssam#include <dev/mii/mii.h> 85164426Ssam#include <dev/mii/miivar.h> 86164426Ssam#include <arm/xscale/ixp425/if_npereg.h> 87164426Ssam 88186352Ssam#include <machine/armreg.h> 89186352Ssam 90164426Ssam#include "miibus_if.h" 91164426Ssam 92166064Scognet/* 93166064Scognet * XXX: For the main bus dma tag. Can go away if the new method to get the 94166064Scognet * dma tag from the parent got MFC'd into RELENG_6. 95166064Scognet */ 96166064Scognetextern struct ixp425_softc *ixp425_softc; 97166064Scognet 98164426Ssamstruct npebuf { 99164426Ssam struct npebuf *ix_next; /* chain to next buffer */ 100164426Ssam void *ix_m; /* backpointer to mbuf */ 101164426Ssam bus_dmamap_t ix_map; /* bus dma map for associated data */ 102164426Ssam struct npehwbuf *ix_hw; /* associated h/w block */ 103164426Ssam uint32_t ix_neaddr; /* phys address of ix_hw */ 104164426Ssam}; 105164426Ssam 106164426Ssamstruct npedma { 107164426Ssam const char* name; 108164426Ssam int nbuf; /* # npebuf's allocated */ 109164426Ssam bus_dma_tag_t mtag; /* bus dma tag for mbuf data */ 110164426Ssam struct npehwbuf *hwbuf; /* NPE h/w buffers */ 111164426Ssam bus_dma_tag_t buf_tag; /* tag+map for NPE buffers */ 112164426Ssam bus_dmamap_t buf_map; 113164426Ssam bus_addr_t buf_phys; /* phys addr of buffers */ 114164426Ssam struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 115164426Ssam}; 116164426Ssam 117164426Ssamstruct npe_softc { 118164426Ssam /* XXX mii requires this be first; do not move! */ 119164426Ssam struct ifnet *sc_ifp; /* ifnet pointer */ 120164426Ssam struct mtx sc_mtx; /* basically a perimeter lock */ 121164426Ssam device_t sc_dev; 122164426Ssam bus_space_tag_t sc_iot; 123164426Ssam bus_space_handle_t sc_ioh; /* MAC register window */ 124164426Ssam device_t sc_mii; /* child miibus */ 125164426Ssam bus_space_handle_t sc_miih; /* MII register window */ 126186352Ssam int sc_npeid; 127164426Ssam struct ixpnpe_softc *sc_npe; /* NPE support */ 128164426Ssam int sc_debug; /* DPRINTF* control */ 129164426Ssam int sc_tickinterval; 130164426Ssam struct callout tick_ch; /* Tick callout */ 131166339Skevlo int npe_watchdog_timer; 132164426Ssam struct npedma txdma; 133164426Ssam struct npebuf *tx_free; /* list of free tx buffers */ 134164426Ssam struct npedma rxdma; 135164426Ssam bus_addr_t buf_phys; /* XXX for returning a value */ 136164426Ssam int rx_qid; /* rx qid */ 137164426Ssam int rx_freeqid; /* rx free buffers qid */ 138164426Ssam int tx_qid; /* tx qid */ 139164426Ssam int tx_doneqid; /* tx completed qid */ 140177505Ssam int sc_phy; /* PHY id */ 141164426Ssam struct ifmib_iso_8802_3 mibdata; 142164426Ssam bus_dma_tag_t sc_stats_tag; /* bus dma tag for stats block */ 143164426Ssam struct npestats *sc_stats; 144164426Ssam bus_dmamap_t sc_stats_map; 145164426Ssam bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 146164426Ssam}; 147164426Ssam 148164426Ssam/* 149186352Ssam * Static configuration for IXP425. The tx and 150164426Ssam * rx free Q id's are fixed by the NPE microcode. The 151164426Ssam * rx Q id's are programmed to be separate to simplify 152164426Ssam * multi-port processing. It may be better to handle 153164426Ssam * all traffic through one Q (as done by the Intel drivers). 154164426Ssam * 155164426Ssam * Note that the PHY's are accessible only from MAC A 156164426Ssam * on the IXP425. This and other platform-specific 157164426Ssam * assumptions probably need to be handled through hints. 158164426Ssam */ 159164426Ssamstatic const struct { 160186352Ssam uint32_t macbase; 161164426Ssam uint32_t miibase; 162177505Ssam int phy; /* phy id */ 163164426Ssam uint8_t rx_qid; 164164426Ssam uint8_t rx_freeqid; 165164426Ssam uint8_t tx_qid; 166164426Ssam uint8_t tx_doneqid; 167186352Ssam} npeconfig[NPE_MAX] = { 168186352Ssam [NPE_A] = { 169186352Ssam .macbase = IXP435_MAC_A_HWBASE, 170186352Ssam .miibase = IXP425_MAC_C_HWBASE, 171186352Ssam .phy = 2, 172186352Ssam .rx_qid = 4, 173186352Ssam .rx_freeqid = 26, 174186352Ssam .tx_qid = 23, 175186352Ssam .tx_doneqid = 31 176186352Ssam }, 177186352Ssam [NPE_B] = { 178186352Ssam .macbase = IXP425_MAC_B_HWBASE, 179186352Ssam .miibase = IXP425_MAC_C_HWBASE, 180177505Ssam .phy = 0, 181164426Ssam .rx_qid = 4, 182164426Ssam .rx_freeqid = 27, 183164426Ssam .tx_qid = 24, 184164426Ssam .tx_doneqid = 31 185164426Ssam }, 186186352Ssam [NPE_C] = { 187186352Ssam .macbase = IXP425_MAC_C_HWBASE, 188186352Ssam .miibase = IXP425_MAC_C_HWBASE, 189177505Ssam .phy = 1, 190164426Ssam .rx_qid = 12, 191164426Ssam .rx_freeqid = 28, 192164426Ssam .tx_qid = 25, 193164426Ssam .tx_doneqid = 31 194164426Ssam }, 195164426Ssam}; 196164426Ssamstatic struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 197164426Ssam 198164426Ssamstatic __inline uint32_t 199164426SsamRD4(struct npe_softc *sc, bus_size_t off) 200164426Ssam{ 201164426Ssam return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 202164426Ssam} 203164426Ssam 204164426Ssamstatic __inline void 205164426SsamWR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 206164426Ssam{ 207164426Ssam bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 208164426Ssam} 209164426Ssam 210164426Ssam#define NPE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 211164426Ssam#define NPE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 212164426Ssam#define NPE_LOCK_INIT(_sc) \ 213164426Ssam mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 214164426Ssam MTX_NETWORK_LOCK, MTX_DEF) 215164426Ssam#define NPE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 216164426Ssam#define NPE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 217164426Ssam#define NPE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 218164426Ssam 219164426Ssamstatic devclass_t npe_devclass; 220164426Ssam 221186352Ssamstatic int override_npeid(device_t, const char *resname, int *val); 222164426Ssamstatic int npe_activate(device_t dev); 223164426Ssamstatic void npe_deactivate(device_t dev); 224164426Ssamstatic int npe_ifmedia_update(struct ifnet *ifp); 225164426Ssamstatic void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 226164426Ssamstatic void npe_setmac(struct npe_softc *sc, u_char *eaddr); 227164426Ssamstatic void npe_getmac(struct npe_softc *sc, u_char *eaddr); 228164426Ssamstatic void npe_txdone(int qid, void *arg); 229164426Ssamstatic int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 230164426Ssam struct mbuf *); 231164426Ssamstatic void npe_rxdone(int qid, void *arg); 232164426Ssamstatic void npeinit(void *); 233164426Ssamstatic void npestart_locked(struct ifnet *); 234164426Ssamstatic void npestart(struct ifnet *); 235164426Ssamstatic void npestop(struct npe_softc *); 236166339Skevlostatic void npewatchdog(struct npe_softc *); 237164426Ssamstatic int npeioctl(struct ifnet * ifp, u_long, caddr_t); 238164426Ssam 239164426Ssamstatic int npe_setrxqosentry(struct npe_softc *, int classix, 240164426Ssam int trafclass, int qid); 241186352Ssamstatic int npe_setfirewallmode(struct npe_softc *, int onoff); 242164426Ssamstatic int npe_updatestats(struct npe_softc *); 243164426Ssam#if 0 244164426Ssamstatic int npe_getstats(struct npe_softc *); 245164426Ssamstatic uint32_t npe_getimageid(struct npe_softc *); 246164426Ssamstatic int npe_setloopback(struct npe_softc *, int ena); 247164426Ssam#endif 248164426Ssam 249164426Ssam/* NB: all tx done processing goes through one queue */ 250164426Ssamstatic int tx_doneqid = -1; 251164426Ssam 252186352SsamSYSCTL_NODE(_hw, OID_AUTO, npe, CTLFLAG_RD, 0, "IXP4XX NPE driver parameters"); 253164426Ssam 254164426Ssamstatic int npe_debug = 0; 255164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, debug, CTLFLAG_RW, &npe_debug, 256186352Ssam 0, "IXP4XX NPE network interface debug msgs"); 257186420SsamTUNABLE_INT("hw.npe.debug", &npe_debug); 258164426Ssam#define DPRINTF(sc, fmt, ...) do { \ 259164426Ssam if (sc->sc_debug) device_printf(sc->sc_dev, fmt, __VA_ARGS__); \ 260164426Ssam} while (0) 261164426Ssam#define DPRINTFn(n, sc, fmt, ...) do { \ 262164426Ssam if (sc->sc_debug >= n) device_printf(sc->sc_dev, fmt, __VA_ARGS__);\ 263164426Ssam} while (0) 264164426Ssamstatic int npe_tickinterval = 3; /* npe_tick frequency (secs) */ 265164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, tickinterval, CTLFLAG_RD, &npe_tickinterval, 266164426Ssam 0, "periodic work interval (secs)"); 267164426SsamTUNABLE_INT("hw.npe.tickinterval", &npe_tickinterval); 268164426Ssam 269164426Ssamstatic int npe_rxbuf = 64; /* # rx buffers to allocate */ 270164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, rxbuf, CTLFLAG_RD, &npe_rxbuf, 271164426Ssam 0, "rx buffers allocated"); 272164426SsamTUNABLE_INT("hw.npe.rxbuf", &npe_rxbuf); 273164426Ssamstatic int npe_txbuf = 128; /* # tx buffers to allocate */ 274164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, txbuf, CTLFLAG_RD, &npe_txbuf, 275164426Ssam 0, "tx buffers allocated"); 276164426SsamTUNABLE_INT("hw.npe.txbuf", &npe_txbuf); 277164426Ssam 278164426Ssamstatic int 279186352Ssamunit2npeid(int unit) 280186352Ssam{ 281186352Ssam static const int npeidmap[2][3] = { 282186352Ssam /* on 425 A is for HSS, B & C are for Ethernet */ 283186352Ssam { NPE_B, NPE_C, -1 }, /* IXP425 */ 284186352Ssam /* 435 only has A & C, order C then A */ 285186352Ssam { NPE_C, NPE_A, -1 }, /* IXP435 */ 286186352Ssam }; 287186352Ssam /* XXX check feature register instead */ 288186352Ssam return (unit < 3 ? npeidmap[ 289186352Ssam (cpu_id() & CPU_ID_CPU_MASK) == CPU_ID_IXP435][unit] : -1); 290186352Ssam} 291186352Ssam 292186352Ssamstatic int 293164426Ssamnpe_probe(device_t dev) 294164426Ssam{ 295186352Ssam static const char *desc[NPE_MAX] = { 296186352Ssam [NPE_A] = "IXP NPE-A", 297186352Ssam [NPE_B] = "IXP NPE-B", 298186352Ssam [NPE_C] = "IXP NPE-C" 299186352Ssam }; 300186420Ssam int unit = device_get_unit(dev); 301186352Ssam int npeid; 302164426Ssam 303186420Ssam if (unit > 2 || 304186420Ssam (ixp4xx_read_feature_bits() & 305186420Ssam (unit == 0 ? EXP_FCTRL_ETH0 : EXP_FCTRL_ETH1)) == 0) 306186420Ssam return EINVAL; 307186420Ssam 308186352Ssam npeid = -1; 309186352Ssam if (!override_npeid(dev, "npeid", &npeid)) 310186420Ssam npeid = unit2npeid(unit); 311186352Ssam if (npeid == -1) { 312186420Ssam device_printf(dev, "unit %d not supported\n", unit); 313164426Ssam return EINVAL; 314164426Ssam } 315186352Ssam device_set_desc(dev, desc[npeid]); 316164426Ssam return 0; 317164426Ssam} 318164426Ssam 319164426Ssamstatic int 320164426Ssamnpe_attach(device_t dev) 321164426Ssam{ 322164426Ssam struct npe_softc *sc = device_get_softc(dev); 323164426Ssam struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); 324164426Ssam struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 325164426Ssam struct sysctl_oid *tree = device_get_sysctl_tree(dev); 326186352Ssam struct ifnet *ifp; 327164426Ssam int error; 328164426Ssam u_char eaddr[6]; 329164426Ssam 330164426Ssam sc->sc_dev = dev; 331164426Ssam sc->sc_iot = sa->sc_iot; 332164426Ssam NPE_LOCK_INIT(sc); 333164426Ssam callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 334164426Ssam sc->sc_debug = npe_debug; 335164426Ssam sc->sc_tickinterval = npe_tickinterval; 336164426Ssam 337186352Ssam ifp = if_alloc(IFT_ETHER); 338186352Ssam if (ifp == NULL) { 339186352Ssam device_printf(dev, "cannot allocate ifnet\n"); 340164426Ssam error = EIO; /* XXX */ 341164426Ssam goto out; 342164426Ssam } 343186352Ssam /* NB: must be setup prior to invoking mii code */ 344186352Ssam sc->sc_ifp = ifp; 345164426Ssam 346164426Ssam error = npe_activate(dev); 347186352Ssam if (error) { 348186352Ssam device_printf(dev, "cannot activate npe\n"); 349164426Ssam goto out; 350186352Ssam } 351164426Ssam 352164426Ssam npe_getmac(sc, eaddr); 353164426Ssam 354164426Ssam ifp->if_softc = sc; 355164426Ssam if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 356164426Ssam ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 357164426Ssam ifp->if_start = npestart; 358164426Ssam ifp->if_ioctl = npeioctl; 359164426Ssam ifp->if_init = npeinit; 360164426Ssam IFQ_SET_MAXLEN(&ifp->if_snd, sc->txdma.nbuf - 1); 361166625Smlaier ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 362164426Ssam IFQ_SET_READY(&ifp->if_snd); 363164426Ssam ifp->if_linkmib = &sc->mibdata; 364164426Ssam ifp->if_linkmiblen = sizeof(sc->mibdata); 365164426Ssam sc->mibdata.dot3Compliance = DOT3COMPLIANCE_STATS; 366189645Ssam /* device supports oversided vlan frames */ 367189645Ssam ifp->if_capabilities |= IFCAP_VLAN_MTU; 368189645Ssam ifp->if_capenable = ifp->if_capabilities; 369164426Ssam#ifdef DEVICE_POLLING 370164426Ssam ifp->if_capabilities |= IFCAP_POLLING; 371164426Ssam#endif 372164426Ssam 373164426Ssam SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug", 374164426Ssam CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 375164426Ssam SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tickinterval", 376164426Ssam CTLFLAG_RW, &sc->sc_tickinterval, 0, "periodic work frequency"); 377164426Ssam 378164426Ssam ether_ifattach(ifp, eaddr); 379164426Ssam return 0; 380164426Ssamout: 381164426Ssam if (ifp != NULL) 382164426Ssam if_free(ifp); 383186352Ssam NPE_LOCK_DESTROY(sc); 384186352Ssam npe_deactivate(dev); 385164426Ssam return error; 386164426Ssam} 387164426Ssam 388164426Ssamstatic int 389164426Ssamnpe_detach(device_t dev) 390164426Ssam{ 391164426Ssam struct npe_softc *sc = device_get_softc(dev); 392164426Ssam struct ifnet *ifp = sc->sc_ifp; 393164426Ssam 394164426Ssam#ifdef DEVICE_POLLING 395164426Ssam if (ifp->if_capenable & IFCAP_POLLING) 396164426Ssam ether_poll_deregister(ifp); 397164426Ssam#endif 398164426Ssam npestop(sc); 399164426Ssam if (ifp != NULL) { 400164426Ssam ether_ifdetach(ifp); 401164426Ssam if_free(ifp); 402164426Ssam } 403164426Ssam NPE_LOCK_DESTROY(sc); 404164426Ssam npe_deactivate(dev); 405164426Ssam return 0; 406164426Ssam} 407164426Ssam 408164426Ssam/* 409164426Ssam * Compute and install the multicast filter. 410164426Ssam */ 411164426Ssamstatic void 412164426Ssamnpe_setmcast(struct npe_softc *sc) 413164426Ssam{ 414164426Ssam struct ifnet *ifp = sc->sc_ifp; 415164426Ssam uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 416164426Ssam int i; 417164426Ssam 418164426Ssam if (ifp->if_flags & IFF_PROMISC) { 419164426Ssam memset(mask, 0, ETHER_ADDR_LEN); 420164426Ssam memset(addr, 0, ETHER_ADDR_LEN); 421164426Ssam } else if (ifp->if_flags & IFF_ALLMULTI) { 422164426Ssam static const uint8_t allmulti[ETHER_ADDR_LEN] = 423164426Ssam { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 424164426Ssam memcpy(mask, allmulti, ETHER_ADDR_LEN); 425164426Ssam memcpy(addr, allmulti, ETHER_ADDR_LEN); 426164426Ssam } else { 427164426Ssam uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 428164426Ssam struct ifmultiaddr *ifma; 429164426Ssam const uint8_t *mac; 430164426Ssam 431164426Ssam memset(clr, 0, ETHER_ADDR_LEN); 432164426Ssam memset(set, 0xff, ETHER_ADDR_LEN); 433164426Ssam 434164426Ssam IF_ADDR_LOCK(ifp); 435164426Ssam TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 436164426Ssam if (ifma->ifma_addr->sa_family != AF_LINK) 437164426Ssam continue; 438164426Ssam mac = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 439164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 440164426Ssam clr[i] |= mac[i]; 441164426Ssam set[i] &= mac[i]; 442164426Ssam } 443164426Ssam } 444164426Ssam IF_ADDR_UNLOCK(ifp); 445164426Ssam 446164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 447164426Ssam mask[i] = set[i] | ~clr[i]; 448164426Ssam addr[i] = set[i]; 449164426Ssam } 450164426Ssam } 451164426Ssam 452164426Ssam /* 453164426Ssam * Write the mask and address registers. 454164426Ssam */ 455164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 456164426Ssam WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 457164426Ssam WR4(sc, NPE_MAC_ADDR(i), addr[i]); 458164426Ssam } 459164426Ssam} 460164426Ssam 461164426Ssamstatic void 462164426Ssamnpe_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 463164426Ssam{ 464164426Ssam struct npe_softc *sc; 465164426Ssam 466164426Ssam if (error != 0) 467164426Ssam return; 468164426Ssam sc = (struct npe_softc *)arg; 469164426Ssam sc->buf_phys = segs[0].ds_addr; 470164426Ssam} 471164426Ssam 472164426Ssamstatic int 473164426Ssamnpe_dma_setup(struct npe_softc *sc, struct npedma *dma, 474164426Ssam const char *name, int nbuf, int maxseg) 475164426Ssam{ 476164426Ssam int error, i; 477164426Ssam 478183886Ssam memset(dma, 0, sizeof(*dma)); 479164426Ssam 480164426Ssam dma->name = name; 481164426Ssam dma->nbuf = nbuf; 482164426Ssam 483164426Ssam /* DMA tag for mapped mbufs */ 484166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, 1, 0, 485164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 486164426Ssam MCLBYTES, maxseg, MCLBYTES, 0, 487164426Ssam busdma_lock_mutex, &sc->sc_mtx, &dma->mtag); 488164426Ssam if (error != 0) { 489164426Ssam device_printf(sc->sc_dev, "unable to create %s mbuf dma tag, " 490164426Ssam "error %u\n", dma->name, error); 491164426Ssam return error; 492164426Ssam } 493164426Ssam 494164426Ssam /* DMA tag and map for the NPE buffers */ 495166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 496164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 497164426Ssam nbuf * sizeof(struct npehwbuf), 1, 498164426Ssam nbuf * sizeof(struct npehwbuf), 0, 499164426Ssam busdma_lock_mutex, &sc->sc_mtx, &dma->buf_tag); 500164426Ssam if (error != 0) { 501164426Ssam device_printf(sc->sc_dev, 502164426Ssam "unable to create %s npebuf dma tag, error %u\n", 503164426Ssam dma->name, error); 504164426Ssam return error; 505164426Ssam } 506164426Ssam /* XXX COHERENT for now */ 507164426Ssam if (bus_dmamem_alloc(dma->buf_tag, (void **)&dma->hwbuf, 508164426Ssam BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 509164426Ssam &dma->buf_map) != 0) { 510164426Ssam device_printf(sc->sc_dev, 511164426Ssam "unable to allocate memory for %s h/w buffers, error %u\n", 512164426Ssam dma->name, error); 513164426Ssam return error; 514164426Ssam } 515164426Ssam /* XXX M_TEMP */ 516164426Ssam dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 517164426Ssam if (dma->buf == NULL) { 518164426Ssam device_printf(sc->sc_dev, 519164426Ssam "unable to allocate memory for %s s/w buffers\n", 520164426Ssam dma->name); 521164426Ssam return error; 522164426Ssam } 523164426Ssam if (bus_dmamap_load(dma->buf_tag, dma->buf_map, 524164426Ssam dma->hwbuf, nbuf*sizeof(struct npehwbuf), npe_getaddr, sc, 0) != 0) { 525164426Ssam device_printf(sc->sc_dev, 526164426Ssam "unable to map memory for %s h/w buffers, error %u\n", 527164426Ssam dma->name, error); 528164426Ssam return error; 529164426Ssam } 530164426Ssam dma->buf_phys = sc->buf_phys; 531164426Ssam for (i = 0; i < dma->nbuf; i++) { 532164426Ssam struct npebuf *npe = &dma->buf[i]; 533164426Ssam struct npehwbuf *hw = &dma->hwbuf[i]; 534164426Ssam 535164426Ssam /* calculate offset to shared area */ 536164426Ssam npe->ix_neaddr = dma->buf_phys + 537164426Ssam ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 538164426Ssam KASSERT((npe->ix_neaddr & 0x1f) == 0, 539164426Ssam ("ixpbuf misaligned, PA 0x%x", npe->ix_neaddr)); 540164426Ssam error = bus_dmamap_create(dma->mtag, BUS_DMA_NOWAIT, 541164426Ssam &npe->ix_map); 542164426Ssam if (error != 0) { 543164426Ssam device_printf(sc->sc_dev, 544164426Ssam "unable to create dmamap for %s buffer %u, " 545164426Ssam "error %u\n", dma->name, i, error); 546164426Ssam return error; 547164426Ssam } 548164426Ssam npe->ix_hw = hw; 549164426Ssam } 550164426Ssam bus_dmamap_sync(dma->buf_tag, dma->buf_map, BUS_DMASYNC_PREWRITE); 551164426Ssam return 0; 552164426Ssam} 553164426Ssam 554164426Ssamstatic void 555164426Ssamnpe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 556164426Ssam{ 557164426Ssam int i; 558164426Ssam 559164426Ssam if (dma->hwbuf != NULL) { 560164426Ssam for (i = 0; i < dma->nbuf; i++) { 561164426Ssam struct npebuf *npe = &dma->buf[i]; 562164426Ssam bus_dmamap_destroy(dma->mtag, npe->ix_map); 563164426Ssam } 564164426Ssam bus_dmamap_unload(dma->buf_tag, dma->buf_map); 565164426Ssam bus_dmamem_free(dma->buf_tag, dma->hwbuf, dma->buf_map); 566164426Ssam } 567164426Ssam if (dma->buf != NULL) 568164426Ssam free(dma->buf, M_TEMP); 569164426Ssam if (dma->buf_tag) 570164426Ssam bus_dma_tag_destroy(dma->buf_tag); 571164426Ssam if (dma->mtag) 572164426Ssam bus_dma_tag_destroy(dma->mtag); 573164426Ssam memset(dma, 0, sizeof(*dma)); 574164426Ssam} 575164426Ssam 576164426Ssamstatic int 577186352Ssamoverride_addr(device_t dev, const char *resname, int *base) 578177505Ssam{ 579177505Ssam int unit = device_get_unit(dev); 580177505Ssam const char *resval; 581177505Ssam 582177505Ssam /* XXX warn for wrong hint type */ 583177505Ssam if (resource_string_value("npe", unit, resname, &resval) != 0) 584177505Ssam return 0; 585177505Ssam switch (resval[0]) { 586177505Ssam case 'A': 587186352Ssam *base = IXP435_MAC_A_HWBASE; 588177505Ssam break; 589177505Ssam case 'B': 590177505Ssam *base = IXP425_MAC_B_HWBASE; 591177505Ssam break; 592186352Ssam case 'C': 593186352Ssam *base = IXP425_MAC_C_HWBASE; 594186352Ssam break; 595177505Ssam default: 596177505Ssam device_printf(dev, "Warning, bad value %s for " 597177505Ssam "npe.%d.%s ignored\n", resval, unit, resname); 598177505Ssam return 0; 599177505Ssam } 600177505Ssam if (bootverbose) 601177505Ssam device_printf(dev, "using npe.%d.%s=%s override\n", 602177505Ssam unit, resname, resval); 603177505Ssam return 1; 604177505Ssam} 605177505Ssam 606177505Ssamstatic int 607186352Ssamoverride_npeid(device_t dev, const char *resname, int *npeid) 608186352Ssam{ 609186352Ssam int unit = device_get_unit(dev); 610186352Ssam const char *resval; 611186352Ssam 612186352Ssam /* XXX warn for wrong hint type */ 613186352Ssam if (resource_string_value("npe", unit, resname, &resval) != 0) 614186352Ssam return 0; 615186352Ssam switch (resval[0]) { 616186352Ssam case 'A': *npeid = NPE_A; break; 617186352Ssam case 'B': *npeid = NPE_B; break; 618186352Ssam case 'C': *npeid = NPE_C; break; 619186352Ssam default: 620186352Ssam device_printf(dev, "Warning, bad value %s for " 621186352Ssam "npe.%d.%s ignored\n", resval, unit, resname); 622186352Ssam return 0; 623186352Ssam } 624186352Ssam if (bootverbose) 625186352Ssam device_printf(dev, "using npe.%d.%s=%s override\n", 626186352Ssam unit, resname, resval); 627186352Ssam return 1; 628186352Ssam} 629186352Ssam 630186352Ssamstatic int 631177505Ssamoverride_unit(device_t dev, const char *resname, int *val, int min, int max) 632177505Ssam{ 633177505Ssam int unit = device_get_unit(dev); 634177505Ssam int resval; 635177505Ssam 636177505Ssam if (resource_int_value("npe", unit, resname, &resval) != 0) 637177505Ssam return 0; 638177505Ssam if (!(min <= resval && resval <= max)) { 639177505Ssam device_printf(dev, "Warning, bad value %d for npe.%d.%s " 640177505Ssam "ignored (value must be [%d-%d])\n", resval, unit, 641177505Ssam resname, min, max); 642177505Ssam return 0; 643177505Ssam } 644177505Ssam if (bootverbose) 645177505Ssam device_printf(dev, "using npe.%d.%s=%d override\n", 646177505Ssam unit, resname, resval); 647177505Ssam *val = resval; 648177505Ssam return 1; 649177505Ssam} 650177505Ssam 651186352Ssamstatic void 652186352Ssamnpe_mac_reset(struct npe_softc *sc) 653186352Ssam{ 654186352Ssam /* 655186352Ssam * Reset MAC core. 656186352Ssam */ 657186352Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 658186352Ssam DELAY(NPE_MAC_RESET_DELAY); 659186352Ssam /* configure MAC to generate MDC clock */ 660186352Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 661186352Ssam} 662186352Ssam 663186352Ssamstatic int 664164426Ssamnpe_activate(device_t dev) 665164426Ssam{ 666164426Ssam struct npe_softc * sc = device_get_softc(dev); 667186352Ssam int error, i, macbase, miibase; 668164426Ssam 669169954Ssam /* 670186352Ssam * Setup NEP ID, MAC, and MII bindings. We allow override 671186352Ssam * via hints to handle unexpected board configs. 672186352Ssam */ 673186352Ssam if (!override_npeid(dev, "npeid", &sc->sc_npeid)) 674186352Ssam sc->sc_npeid = unit2npeid(device_get_unit(dev)); 675186352Ssam sc->sc_npe = ixpnpe_attach(dev, sc->sc_npeid); 676186352Ssam if (sc->sc_npe == NULL) { 677186352Ssam device_printf(dev, "cannot attach ixpnpe\n"); 678186352Ssam return EIO; /* XXX */ 679186352Ssam } 680186352Ssam 681186352Ssam /* MAC */ 682186352Ssam if (!override_addr(dev, "mac", &macbase)) 683186352Ssam macbase = npeconfig[sc->sc_npeid].macbase; 684186352Ssam device_printf(sc->sc_dev, "MAC at 0x%x\n", macbase); 685186352Ssam if (bus_space_map(sc->sc_iot, macbase, IXP425_REG_SIZE, 0, &sc->sc_ioh)) { 686186352Ssam device_printf(dev, "cannot map mac registers 0x%x:0x%x\n", 687186352Ssam macbase, IXP425_REG_SIZE); 688186352Ssam return ENOMEM; 689186352Ssam } 690186352Ssam 691186352Ssam /* PHY */ 692186352Ssam if (!override_unit(dev, "phy", &sc->sc_phy, 0, MII_NPHY-1)) 693186352Ssam sc->sc_phy = npeconfig[sc->sc_npeid].phy; 694186352Ssam if (!override_addr(dev, "mii", &miibase)) 695186352Ssam miibase = npeconfig[sc->sc_npeid].miibase; 696186352Ssam device_printf(sc->sc_dev, "MII at 0x%x\n", miibase); 697186352Ssam if (miibase != macbase) { 698186352Ssam /* 699186352Ssam * PHY is mapped through a different MAC, setup an 700186352Ssam * additional mapping for frobbing the PHY registers. 701186352Ssam */ 702186352Ssam if (bus_space_map(sc->sc_iot, miibase, IXP425_REG_SIZE, 0, &sc->sc_miih)) { 703186352Ssam device_printf(dev, 704186352Ssam "cannot map MII registers 0x%x:0x%x\n", 705186352Ssam miibase, IXP425_REG_SIZE); 706186352Ssam return ENOMEM; 707186352Ssam } 708186352Ssam } else 709186352Ssam sc->sc_miih = sc->sc_ioh; 710186352Ssam 711186352Ssam /* 712186420Ssam * Load NPE firmware and start it running. 713169954Ssam */ 714186420Ssam error = ixpnpe_init(sc->sc_npe); 715186420Ssam if (error != 0) { 716186420Ssam device_printf(dev, "cannot init NPE (error %d)\n", error); 717186420Ssam return error; 718169954Ssam } 719164426Ssam 720186352Ssam /* probe for PHY */ 721186352Ssam if (mii_phy_probe(dev, &sc->sc_mii, npe_ifmedia_update, npe_ifmedia_status)) { 722186352Ssam device_printf(dev, "cannot find PHY %d.\n", sc->sc_phy); 723186352Ssam return ENXIO; 724177505Ssam } 725164426Ssam 726164426Ssam error = npe_dma_setup(sc, &sc->txdma, "tx", npe_txbuf, NPE_MAXSEG); 727164426Ssam if (error != 0) 728164426Ssam return error; 729164426Ssam error = npe_dma_setup(sc, &sc->rxdma, "rx", npe_rxbuf, 1); 730164426Ssam if (error != 0) 731164426Ssam return error; 732164426Ssam 733164426Ssam /* setup statistics block */ 734166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 735164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 736164426Ssam sizeof(struct npestats), 1, sizeof(struct npestats), 0, 737164426Ssam busdma_lock_mutex, &sc->sc_mtx, &sc->sc_stats_tag); 738164426Ssam if (error != 0) { 739164426Ssam device_printf(sc->sc_dev, "unable to create stats tag, " 740164426Ssam "error %u\n", error); 741164426Ssam return error; 742164426Ssam } 743164426Ssam if (bus_dmamem_alloc(sc->sc_stats_tag, (void **)&sc->sc_stats, 744164426Ssam BUS_DMA_NOWAIT, &sc->sc_stats_map) != 0) { 745164426Ssam device_printf(sc->sc_dev, 746164426Ssam "unable to allocate memory for stats block, error %u\n", 747164426Ssam error); 748164426Ssam return error; 749164426Ssam } 750164426Ssam if (bus_dmamap_load(sc->sc_stats_tag, sc->sc_stats_map, 751164426Ssam sc->sc_stats, sizeof(struct npestats), npe_getaddr, sc, 0) != 0) { 752164426Ssam device_printf(sc->sc_dev, 753164426Ssam "unable to load memory for stats block, error %u\n", 754164426Ssam error); 755164426Ssam return error; 756164426Ssam } 757164426Ssam sc->sc_stats_phys = sc->buf_phys; 758164426Ssam 759164426Ssam /* 760164426Ssam * Setup h/w rx/tx queues. There are four q's: 761164426Ssam * rx inbound q of rx'd frames 762164426Ssam * rx_free pool of ixpbuf's for receiving frames 763164426Ssam * tx outbound q of frames to send 764164426Ssam * tx_done q of tx frames that have been processed 765164426Ssam * 766164426Ssam * The NPE handles the actual tx/rx process and the q manager 767164426Ssam * handles the queues. The driver just writes entries to the 768164426Ssam * q manager mailbox's and gets callbacks when there are rx'd 769164426Ssam * frames to process or tx'd frames to reap. These callbacks 770164426Ssam * are controlled by the q configurations; e.g. we get a 771164426Ssam * callback when tx_done has 2 or more frames to process and 772164426Ssam * when the rx q has at least one frame. These setings can 773164426Ssam * changed at the time the q is configured. 774164426Ssam */ 775186352Ssam sc->rx_qid = npeconfig[sc->sc_npeid].rx_qid; 776164426Ssam ixpqmgr_qconfig(sc->rx_qid, npe_rxbuf, 0, 1, 777164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 778186352Ssam sc->rx_freeqid = npeconfig[sc->sc_npeid].rx_freeqid; 779164426Ssam ixpqmgr_qconfig(sc->rx_freeqid, npe_rxbuf, 0, npe_rxbuf/2, 0, NULL, sc); 780186352Ssam /* 781186352Ssam * Setup the NPE to direct all traffic to rx_qid. 782186352Ssam * When QoS is enabled in the firmware there are 783186352Ssam * 8 traffic classes; otherwise just 4. 784186352Ssam */ 785164426Ssam for (i = 0; i < 8; i++) 786164426Ssam npe_setrxqosentry(sc, i, 0, sc->rx_qid); 787164426Ssam 788186352Ssam /* disable firewall mode just in case (should be off) */ 789186352Ssam npe_setfirewallmode(sc, 0); 790186352Ssam 791186352Ssam sc->tx_qid = npeconfig[sc->sc_npeid].tx_qid; 792186352Ssam sc->tx_doneqid = npeconfig[sc->sc_npeid].tx_doneqid; 793164426Ssam ixpqmgr_qconfig(sc->tx_qid, npe_txbuf, 0, npe_txbuf, 0, NULL, sc); 794164426Ssam if (tx_doneqid == -1) { 795164426Ssam ixpqmgr_qconfig(sc->tx_doneqid, npe_txbuf, 0, 2, 796164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 797164426Ssam tx_doneqid = sc->tx_doneqid; 798164426Ssam } 799164426Ssam 800186352Ssam KASSERT(npes[sc->sc_npeid] == NULL, 801186352Ssam ("npe %u already setup", sc->sc_npeid)); 802186352Ssam npes[sc->sc_npeid] = sc; 803177505Ssam 804164426Ssam return 0; 805164426Ssam} 806164426Ssam 807164426Ssamstatic void 808164426Ssamnpe_deactivate(device_t dev) 809164426Ssam{ 810164426Ssam struct npe_softc *sc = device_get_softc(dev); 811164426Ssam 812186352Ssam npes[sc->sc_npeid] = NULL; 813164426Ssam 814164426Ssam /* XXX disable q's */ 815186352Ssam if (sc->sc_npe != NULL) { 816164426Ssam ixpnpe_stop(sc->sc_npe); 817186352Ssam ixpnpe_detach(sc->sc_npe); 818186352Ssam } 819164426Ssam if (sc->sc_stats != NULL) { 820164426Ssam bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 821164426Ssam bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 822164426Ssam sc->sc_stats_map); 823164426Ssam } 824164426Ssam if (sc->sc_stats_tag != NULL) 825164426Ssam bus_dma_tag_destroy(sc->sc_stats_tag); 826164426Ssam npe_dma_destroy(sc, &sc->txdma); 827164426Ssam npe_dma_destroy(sc, &sc->rxdma); 828164426Ssam bus_generic_detach(sc->sc_dev); 829186352Ssam if (sc->sc_mii != NULL) 830164426Ssam device_delete_child(sc->sc_dev, sc->sc_mii); 831164426Ssam} 832164426Ssam 833164426Ssam/* 834164426Ssam * Change media according to request. 835164426Ssam */ 836164426Ssamstatic int 837164426Ssamnpe_ifmedia_update(struct ifnet *ifp) 838164426Ssam{ 839164426Ssam struct npe_softc *sc = ifp->if_softc; 840164426Ssam struct mii_data *mii; 841164426Ssam 842164426Ssam mii = device_get_softc(sc->sc_mii); 843164426Ssam NPE_LOCK(sc); 844164426Ssam mii_mediachg(mii); 845164426Ssam /* XXX push state ourself? */ 846164426Ssam NPE_UNLOCK(sc); 847164426Ssam return (0); 848164426Ssam} 849164426Ssam 850164426Ssam/* 851164426Ssam * Notify the world which media we're using. 852164426Ssam */ 853164426Ssamstatic void 854164426Ssamnpe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 855164426Ssam{ 856164426Ssam struct npe_softc *sc = ifp->if_softc; 857164426Ssam struct mii_data *mii; 858164426Ssam 859164426Ssam mii = device_get_softc(sc->sc_mii); 860164426Ssam NPE_LOCK(sc); 861164426Ssam mii_pollstat(mii); 862164426Ssam ifmr->ifm_active = mii->mii_media_active; 863164426Ssam ifmr->ifm_status = mii->mii_media_status; 864164426Ssam NPE_UNLOCK(sc); 865164426Ssam} 866164426Ssam 867164426Ssamstatic void 868164426Ssamnpe_addstats(struct npe_softc *sc) 869164426Ssam{ 870164426Ssam#define MIBADD(x) sc->mibdata.x += be32toh(ns->x) 871164426Ssam struct ifnet *ifp = sc->sc_ifp; 872164426Ssam struct npestats *ns = sc->sc_stats; 873164426Ssam 874164426Ssam MIBADD(dot3StatsAlignmentErrors); 875164426Ssam MIBADD(dot3StatsFCSErrors); 876164426Ssam MIBADD(dot3StatsSingleCollisionFrames); 877164426Ssam MIBADD(dot3StatsMultipleCollisionFrames); 878164426Ssam MIBADD(dot3StatsDeferredTransmissions); 879164426Ssam MIBADD(dot3StatsLateCollisions); 880164426Ssam MIBADD(dot3StatsExcessiveCollisions); 881164426Ssam MIBADD(dot3StatsInternalMacTransmitErrors); 882164426Ssam MIBADD(dot3StatsCarrierSenseErrors); 883164426Ssam sc->mibdata.dot3StatsFrameTooLongs += 884164426Ssam be32toh(ns->RxLargeFramesDiscards) 885164426Ssam + be32toh(ns->TxLargeFrameDiscards); 886164426Ssam MIBADD(dot3StatsInternalMacReceiveErrors); 887164426Ssam sc->mibdata.dot3StatsMissedFrames += 888164426Ssam be32toh(ns->RxOverrunDiscards) 889164426Ssam + be32toh(ns->RxUnderflowEntryDiscards); 890164426Ssam 891164426Ssam ifp->if_oerrors += 892164426Ssam be32toh(ns->dot3StatsInternalMacTransmitErrors) 893164426Ssam + be32toh(ns->dot3StatsCarrierSenseErrors) 894164426Ssam + be32toh(ns->TxVLANIdFilterDiscards) 895164426Ssam ; 896164426Ssam ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 897164426Ssam + be32toh(ns->dot3StatsInternalMacReceiveErrors) 898164426Ssam + be32toh(ns->RxOverrunDiscards) 899164426Ssam + be32toh(ns->RxUnderflowEntryDiscards) 900164426Ssam ; 901164426Ssam ifp->if_collisions += 902164426Ssam be32toh(ns->dot3StatsSingleCollisionFrames) 903164426Ssam + be32toh(ns->dot3StatsMultipleCollisionFrames) 904164426Ssam ; 905164426Ssam#undef MIBADD 906164426Ssam} 907164426Ssam 908164426Ssamstatic void 909164426Ssamnpe_tick(void *xsc) 910164426Ssam{ 911164426Ssam#define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 912164426Ssam struct npe_softc *sc = xsc; 913164426Ssam struct mii_data *mii = device_get_softc(sc->sc_mii); 914164426Ssam uint32_t msg[2]; 915164426Ssam 916164426Ssam NPE_ASSERT_LOCKED(sc); 917164426Ssam 918164426Ssam /* 919164426Ssam * NB: to avoid sleeping with the softc lock held we 920164426Ssam * split the NPE msg processing into two parts. The 921164426Ssam * request for statistics is sent w/o waiting for a 922164426Ssam * reply and then on the next tick we retrieve the 923164426Ssam * results. This works because npe_tick is the only 924164426Ssam * code that talks via the mailbox's (except at setup). 925164426Ssam * This likely can be handled better. 926164426Ssam */ 927186352Ssam if (ixpnpe_recvmsg_async(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 928164426Ssam bus_dmamap_sync(sc->sc_stats_tag, sc->sc_stats_map, 929164426Ssam BUS_DMASYNC_POSTREAD); 930164426Ssam npe_addstats(sc); 931164426Ssam } 932164426Ssam npe_updatestats(sc); 933164426Ssam mii_tick(mii); 934164426Ssam 935166339Skevlo npewatchdog(sc); 936166339Skevlo 937164426Ssam /* schedule next poll */ 938164426Ssam callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 939164426Ssam#undef ACK 940164426Ssam} 941164426Ssam 942164426Ssamstatic void 943164426Ssamnpe_setmac(struct npe_softc *sc, u_char *eaddr) 944164426Ssam{ 945164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 946164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 947164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 948164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 949164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 950164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 951164426Ssam} 952164426Ssam 953164426Ssamstatic void 954164426Ssamnpe_getmac(struct npe_softc *sc, u_char *eaddr) 955164426Ssam{ 956164426Ssam /* NB: the unicast address appears to be loaded from EEPROM on reset */ 957164426Ssam eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 958164426Ssam eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 959164426Ssam eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 960164426Ssam eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 961164426Ssam eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 962164426Ssam eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 963164426Ssam} 964164426Ssam 965164426Ssamstruct txdone { 966164426Ssam struct npebuf *head; 967164426Ssam struct npebuf **tail; 968164426Ssam int count; 969164426Ssam}; 970164426Ssam 971164426Ssamstatic __inline void 972164426Ssamnpe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 973164426Ssam{ 974164426Ssam struct ifnet *ifp = sc->sc_ifp; 975164426Ssam 976164426Ssam NPE_LOCK(sc); 977164426Ssam *td->tail = sc->tx_free; 978164426Ssam sc->tx_free = td->head; 979164426Ssam /* 980164426Ssam * We're no longer busy, so clear the busy flag and call the 981164426Ssam * start routine to xmit more packets. 982164426Ssam */ 983164426Ssam ifp->if_opackets += td->count; 984164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 985166339Skevlo sc->npe_watchdog_timer = 0; 986164426Ssam npestart_locked(ifp); 987164426Ssam NPE_UNLOCK(sc); 988164426Ssam} 989164426Ssam 990164426Ssam/* 991164426Ssam * Q manager callback on tx done queue. Reap mbufs 992164426Ssam * and return tx buffers to the free list. Finally 993164426Ssam * restart output. Note the microcode has only one 994164426Ssam * txdone q wired into it so we must use the NPE ID 995164426Ssam * returned with each npehwbuf to decide where to 996164426Ssam * send buffers. 997164426Ssam */ 998164426Ssamstatic void 999164426Ssamnpe_txdone(int qid, void *arg) 1000164426Ssam{ 1001164426Ssam#define P2V(a, dma) \ 1002164426Ssam &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1003164426Ssam struct npe_softc *sc0 = arg; 1004164426Ssam struct npe_softc *sc; 1005164426Ssam struct npebuf *npe; 1006164426Ssam struct txdone *td, q[NPE_MAX]; 1007164426Ssam uint32_t entry; 1008164426Ssam 1009164426Ssam /* XXX no NPE-A support */ 1010164426Ssam q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 1011164426Ssam q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 1012164426Ssam /* XXX max # at a time? */ 1013164426Ssam while (ixpqmgr_qread(qid, &entry) == 0) { 1014164426Ssam DPRINTF(sc0, "%s: entry 0x%x NPE %u port %u\n", 1015164426Ssam __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 1016164426Ssam 1017164426Ssam sc = npes[NPE_QM_Q_NPE(entry)]; 1018164426Ssam npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 1019164426Ssam m_freem(npe->ix_m); 1020164426Ssam npe->ix_m = NULL; 1021164426Ssam 1022164426Ssam td = &q[NPE_QM_Q_NPE(entry)]; 1023164426Ssam *td->tail = npe; 1024164426Ssam td->tail = &npe->ix_next; 1025164426Ssam td->count++; 1026164426Ssam } 1027164426Ssam 1028164426Ssam if (q[NPE_B].count) 1029164426Ssam npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 1030164426Ssam if (q[NPE_C].count) 1031164426Ssam npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 1032164426Ssam#undef P2V 1033164426Ssam} 1034164426Ssam 1035164426Ssamstatic int 1036164426Ssamnpe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 1037164426Ssam{ 1038164426Ssam bus_dma_segment_t segs[1]; 1039164426Ssam struct npedma *dma = &sc->rxdma; 1040164426Ssam struct npehwbuf *hw; 1041164426Ssam int error, nseg; 1042164426Ssam 1043164426Ssam if (m == NULL) { 1044164426Ssam m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1045164426Ssam if (m == NULL) 1046164426Ssam return ENOBUFS; 1047164426Ssam } 1048164426Ssam KASSERT(m->m_ext.ext_size >= 1536 + ETHER_ALIGN, 1049164426Ssam ("ext_size %d", m->m_ext.ext_size)); 1050164426Ssam m->m_pkthdr.len = m->m_len = 1536; 1051164426Ssam /* backload payload and align ip hdr */ 1052164426Ssam m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN)); 1053164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, m, 1054164426Ssam segs, &nseg, 0); 1055164426Ssam if (error != 0) { 1056164426Ssam m_freem(m); 1057164426Ssam return error; 1058164426Ssam } 1059164426Ssam hw = npe->ix_hw; 1060164426Ssam hw->ix_ne[0].data = htobe32(segs[0].ds_addr); 1061164426Ssam /* NB: NPE requires length be a multiple of 64 */ 1062164426Ssam /* NB: buffer length is shifted in word */ 1063164426Ssam hw->ix_ne[0].len = htobe32(segs[0].ds_len << 16); 1064164426Ssam hw->ix_ne[0].next = 0; 1065164426Ssam npe->ix_m = m; 1066164426Ssam /* Flush the memory in the mbuf */ 1067164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREREAD); 1068164426Ssam return 0; 1069164426Ssam} 1070164426Ssam 1071164426Ssam/* 1072164426Ssam * RX q processing for a specific NPE. Claim entries 1073164426Ssam * from the hardware queue and pass the frames up the 1074164426Ssam * stack. Pass the rx buffers to the free list. 1075164426Ssam */ 1076164426Ssamstatic void 1077164426Ssamnpe_rxdone(int qid, void *arg) 1078164426Ssam{ 1079164426Ssam#define P2V(a, dma) \ 1080164426Ssam &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1081164426Ssam struct npe_softc *sc = arg; 1082164426Ssam struct npedma *dma = &sc->rxdma; 1083164426Ssam uint32_t entry; 1084164426Ssam 1085164426Ssam while (ixpqmgr_qread(qid, &entry) == 0) { 1086164426Ssam struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 1087164426Ssam struct mbuf *m; 1088164426Ssam 1089164426Ssam DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 1090164426Ssam __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 1091164426Ssam /* 1092164426Ssam * Allocate a new mbuf to replenish the rx buffer. 1093164426Ssam * If doing so fails we drop the rx'd frame so we 1094164426Ssam * can reuse the previous mbuf. When we're able to 1095164426Ssam * allocate a new mbuf dispatch the mbuf w/ rx'd 1096164426Ssam * data up the stack and replace it with the newly 1097164426Ssam * allocated one. 1098164426Ssam */ 1099164426Ssam m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1100164426Ssam if (m != NULL) { 1101164426Ssam struct mbuf *mrx = npe->ix_m; 1102164426Ssam struct npehwbuf *hw = npe->ix_hw; 1103164426Ssam struct ifnet *ifp = sc->sc_ifp; 1104164426Ssam 1105164426Ssam /* Flush mbuf memory for rx'd data */ 1106164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, 1107164426Ssam BUS_DMASYNC_POSTREAD); 1108164426Ssam 1109164426Ssam /* XXX flush hw buffer; works now 'cuz coherent */ 1110164426Ssam /* set m_len etc. per rx frame size */ 1111164426Ssam mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 1112164426Ssam mrx->m_pkthdr.len = mrx->m_len; 1113164426Ssam mrx->m_pkthdr.rcvif = ifp; 1114164426Ssam 1115164426Ssam ifp->if_ipackets++; 1116164426Ssam ifp->if_input(ifp, mrx); 1117164426Ssam } else { 1118164426Ssam /* discard frame and re-use mbuf */ 1119164426Ssam m = npe->ix_m; 1120164426Ssam } 1121164426Ssam if (npe_rxbuf_init(sc, npe, m) == 0) { 1122164426Ssam /* return npe buf to rx free list */ 1123164426Ssam ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1124164426Ssam } else { 1125164426Ssam /* XXX should not happen */ 1126164426Ssam } 1127164426Ssam } 1128164426Ssam#undef P2V 1129164426Ssam} 1130164426Ssam 1131164426Ssam#ifdef DEVICE_POLLING 1132164426Ssamstatic void 1133164426Ssamnpe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1134164426Ssam{ 1135164426Ssam struct npe_softc *sc = ifp->if_softc; 1136164426Ssam 1137164426Ssam if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1138164426Ssam npe_rxdone(sc->rx_qid, sc); 1139164426Ssam npe_txdone(sc->tx_doneqid, sc); /* XXX polls both NPE's */ 1140164426Ssam } 1141164426Ssam} 1142164426Ssam#endif /* DEVICE_POLLING */ 1143164426Ssam 1144164426Ssamstatic void 1145164426Ssamnpe_startxmit(struct npe_softc *sc) 1146164426Ssam{ 1147164426Ssam struct npedma *dma = &sc->txdma; 1148164426Ssam int i; 1149164426Ssam 1150164426Ssam NPE_ASSERT_LOCKED(sc); 1151164426Ssam sc->tx_free = NULL; 1152164426Ssam for (i = 0; i < dma->nbuf; i++) { 1153164426Ssam struct npebuf *npe = &dma->buf[i]; 1154164426Ssam if (npe->ix_m != NULL) { 1155164426Ssam /* NB: should not happen */ 1156164426Ssam device_printf(sc->sc_dev, 1157164426Ssam "%s: free mbuf at entry %u\n", __func__, i); 1158164426Ssam m_freem(npe->ix_m); 1159164426Ssam } 1160164426Ssam npe->ix_m = NULL; 1161164426Ssam npe->ix_next = sc->tx_free; 1162164426Ssam sc->tx_free = npe; 1163164426Ssam } 1164164426Ssam} 1165164426Ssam 1166164426Ssamstatic void 1167164426Ssamnpe_startrecv(struct npe_softc *sc) 1168164426Ssam{ 1169164426Ssam struct npedma *dma = &sc->rxdma; 1170164426Ssam struct npebuf *npe; 1171164426Ssam int i; 1172164426Ssam 1173164426Ssam NPE_ASSERT_LOCKED(sc); 1174164426Ssam for (i = 0; i < dma->nbuf; i++) { 1175164426Ssam npe = &dma->buf[i]; 1176164426Ssam npe_rxbuf_init(sc, npe, npe->ix_m); 1177164426Ssam /* set npe buf on rx free list */ 1178164426Ssam ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1179164426Ssam } 1180164426Ssam} 1181164426Ssam 1182164426Ssam/* 1183164426Ssam * Reset and initialize the chip 1184164426Ssam */ 1185164426Ssamstatic void 1186164426Ssamnpeinit_locked(void *xsc) 1187164426Ssam{ 1188164426Ssam struct npe_softc *sc = xsc; 1189164426Ssam struct ifnet *ifp = sc->sc_ifp; 1190164426Ssam 1191164426Ssam NPE_ASSERT_LOCKED(sc); 1192164426Ssamif (ifp->if_drv_flags & IFF_DRV_RUNNING) return;/*XXX*/ 1193164426Ssam 1194164426Ssam /* 1195164426Ssam * Reset MAC core. 1196164426Ssam */ 1197186352Ssam npe_mac_reset(sc); 1198164426Ssam 1199164426Ssam /* disable transmitter and reciver in the MAC */ 1200164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1201164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1202164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1203164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1204164426Ssam 1205164426Ssam /* 1206164426Ssam * Set the MAC core registers. 1207164426Ssam */ 1208164426Ssam WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1209164426Ssam WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1210164426Ssam WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1211164426Ssam /* thresholds determined by NPE firmware FS */ 1212164426Ssam WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1213164426Ssam WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1214164426Ssam WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */ 1215164426Ssam WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1216164426Ssam WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1217164426Ssam WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1218164426Ssam WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1219164426Ssam WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */ 1220164426Ssam 1221164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1222164426Ssam NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1223164426Ssam | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1224164426Ssam | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1225164426Ssam | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1226164426Ssam /* XXX pad strip? */ 1227189642Ssam /* ena pause frame handling */ 1228189642Ssam WR4(sc, NPE_MAC_RX_CNTRL1, NPE_RX_CNTRL1_PAUSE_EN); 1229164426Ssam WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1230164426Ssam 1231164426Ssam npe_setmac(sc, IF_LLADDR(ifp)); 1232164426Ssam npe_setmcast(sc); 1233164426Ssam 1234164426Ssam npe_startxmit(sc); 1235164426Ssam npe_startrecv(sc); 1236164426Ssam 1237164426Ssam ifp->if_drv_flags |= IFF_DRV_RUNNING; 1238164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1239166339Skevlo sc->npe_watchdog_timer = 0; /* just in case */ 1240164426Ssam 1241164426Ssam /* enable transmitter and reciver in the MAC */ 1242164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1243164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1244164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1245164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1246164426Ssam 1247164426Ssam callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 1248164426Ssam} 1249164426Ssam 1250164426Ssamstatic void 1251164426Ssamnpeinit(void *xsc) 1252164426Ssam{ 1253164426Ssam struct npe_softc *sc = xsc; 1254164426Ssam NPE_LOCK(sc); 1255164426Ssam npeinit_locked(sc); 1256164426Ssam NPE_UNLOCK(sc); 1257164426Ssam} 1258164426Ssam 1259164426Ssam/* 1260164426Ssam * Dequeue packets and place on the h/w transmit queue. 1261164426Ssam */ 1262164426Ssamstatic void 1263164426Ssamnpestart_locked(struct ifnet *ifp) 1264164426Ssam{ 1265164426Ssam struct npe_softc *sc = ifp->if_softc; 1266164426Ssam struct npebuf *npe; 1267164426Ssam struct npehwbuf *hw; 1268164426Ssam struct mbuf *m, *n; 1269164426Ssam struct npedma *dma = &sc->txdma; 1270164426Ssam bus_dma_segment_t segs[NPE_MAXSEG]; 1271164426Ssam int nseg, len, error, i; 1272164426Ssam uint32_t next; 1273164426Ssam 1274164426Ssam NPE_ASSERT_LOCKED(sc); 1275164426Ssam /* XXX can this happen? */ 1276164426Ssam if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1277164426Ssam return; 1278164426Ssam 1279164426Ssam while (sc->tx_free != NULL) { 1280164426Ssam IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1281164426Ssam if (m == NULL) { 1282164426Ssam /* XXX? */ 1283164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1284164426Ssam return; 1285164426Ssam } 1286164426Ssam npe = sc->tx_free; 1287164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1288164426Ssam m, segs, &nseg, 0); 1289164426Ssam if (error == EFBIG) { 1290175418Sjhb n = m_collapse(m, M_DONTWAIT, NPE_MAXSEG); 1291164426Ssam if (n == NULL) { 1292164426Ssam if_printf(ifp, "%s: too many fragments %u\n", 1293164426Ssam __func__, nseg); 1294164426Ssam m_freem(m); 1295164426Ssam return; /* XXX? */ 1296164426Ssam } 1297164426Ssam m = n; 1298164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1299164426Ssam m, segs, &nseg, 0); 1300164426Ssam } 1301164426Ssam if (error != 0 || nseg == 0) { 1302164426Ssam if_printf(ifp, "%s: error %u nseg %u\n", 1303164426Ssam __func__, error, nseg); 1304164426Ssam m_freem(m); 1305164426Ssam return; /* XXX? */ 1306164426Ssam } 1307164426Ssam sc->tx_free = npe->ix_next; 1308164426Ssam 1309164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREWRITE); 1310164426Ssam 1311164426Ssam /* 1312164426Ssam * Tap off here if there is a bpf listener. 1313164426Ssam */ 1314164426Ssam BPF_MTAP(ifp, m); 1315164426Ssam 1316164426Ssam npe->ix_m = m; 1317164426Ssam hw = npe->ix_hw; 1318164426Ssam len = m->m_pkthdr.len; 1319164426Ssam next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1320164426Ssam for (i = 0; i < nseg; i++) { 1321164426Ssam hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1322164426Ssam hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1323164426Ssam hw->ix_ne[i].next = htobe32(next); 1324164426Ssam 1325164426Ssam len = 0; /* zero for segments > 1 */ 1326164426Ssam next += sizeof(hw->ix_ne[0]); 1327164426Ssam } 1328164426Ssam hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1329164426Ssam /* XXX flush descriptor instead of using uncached memory */ 1330164426Ssam 1331164426Ssam DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1332164426Ssam __func__, sc->tx_qid, npe->ix_neaddr, 1333164426Ssam hw->ix_ne[0].data, hw->ix_ne[0].len); 1334164426Ssam /* stick it on the tx q */ 1335164426Ssam /* XXX add vlan priority */ 1336164426Ssam ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1337164426Ssam 1338166339Skevlo sc->npe_watchdog_timer = 5; 1339164426Ssam } 1340164426Ssam if (sc->tx_free == NULL) 1341164426Ssam ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1342164426Ssam} 1343164426Ssam 1344164426Ssamvoid 1345164426Ssamnpestart(struct ifnet *ifp) 1346164426Ssam{ 1347164426Ssam struct npe_softc *sc = ifp->if_softc; 1348164426Ssam NPE_LOCK(sc); 1349164426Ssam npestart_locked(ifp); 1350164426Ssam NPE_UNLOCK(sc); 1351164426Ssam} 1352164426Ssam 1353164426Ssamstatic void 1354164426Ssamnpe_stopxmit(struct npe_softc *sc) 1355164426Ssam{ 1356164426Ssam struct npedma *dma = &sc->txdma; 1357164426Ssam int i; 1358164426Ssam 1359164426Ssam NPE_ASSERT_LOCKED(sc); 1360164426Ssam 1361164426Ssam /* XXX qmgr */ 1362164426Ssam for (i = 0; i < dma->nbuf; i++) { 1363164426Ssam struct npebuf *npe = &dma->buf[i]; 1364164426Ssam 1365164426Ssam if (npe->ix_m != NULL) { 1366164426Ssam bus_dmamap_unload(dma->mtag, npe->ix_map); 1367164426Ssam m_freem(npe->ix_m); 1368164426Ssam npe->ix_m = NULL; 1369164426Ssam } 1370164426Ssam } 1371164426Ssam} 1372164426Ssam 1373164426Ssamstatic void 1374164426Ssamnpe_stoprecv(struct npe_softc *sc) 1375164426Ssam{ 1376164426Ssam struct npedma *dma = &sc->rxdma; 1377164426Ssam int i; 1378164426Ssam 1379164426Ssam NPE_ASSERT_LOCKED(sc); 1380164426Ssam 1381164426Ssam /* XXX qmgr */ 1382164426Ssam for (i = 0; i < dma->nbuf; i++) { 1383164426Ssam struct npebuf *npe = &dma->buf[i]; 1384164426Ssam 1385164426Ssam if (npe->ix_m != NULL) { 1386164426Ssam bus_dmamap_unload(dma->mtag, npe->ix_map); 1387164426Ssam m_freem(npe->ix_m); 1388164426Ssam npe->ix_m = NULL; 1389164426Ssam } 1390164426Ssam } 1391164426Ssam} 1392164426Ssam 1393164426Ssam/* 1394164426Ssam * Turn off interrupts, and stop the nic. 1395164426Ssam */ 1396164426Ssamvoid 1397164426Ssamnpestop(struct npe_softc *sc) 1398164426Ssam{ 1399164426Ssam struct ifnet *ifp = sc->sc_ifp; 1400164426Ssam 1401164426Ssam /* disable transmitter and reciver in the MAC */ 1402164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1403164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1404164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1405164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1406164426Ssam 1407166339Skevlo sc->npe_watchdog_timer = 0; 1408164426Ssam ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1409164426Ssam 1410164426Ssam callout_stop(&sc->tick_ch); 1411164426Ssam 1412164426Ssam npe_stopxmit(sc); 1413164426Ssam npe_stoprecv(sc); 1414164426Ssam /* XXX go into loopback & drain q's? */ 1415164426Ssam /* XXX but beware of disabling tx above */ 1416164426Ssam 1417164426Ssam /* 1418164426Ssam * The MAC core rx/tx disable may leave the MAC hardware in an 1419164426Ssam * unpredictable state. A hw reset is executed before resetting 1420164426Ssam * all the MAC parameters to a known value. 1421164426Ssam */ 1422164426Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1423164426Ssam DELAY(NPE_MAC_RESET_DELAY); 1424164426Ssam WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1425164426Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1426164426Ssam} 1427164426Ssam 1428164426Ssamvoid 1429166339Skevlonpewatchdog(struct npe_softc *sc) 1430164426Ssam{ 1431166339Skevlo NPE_ASSERT_LOCKED(sc); 1432164426Ssam 1433166339Skevlo if (sc->npe_watchdog_timer == 0 || --sc->npe_watchdog_timer != 0) 1434166339Skevlo return; 1435166339Skevlo 1436166339Skevlo device_printf(sc->sc_dev, "watchdog timeout\n"); 1437166339Skevlo sc->sc_ifp->if_oerrors++; 1438166339Skevlo 1439164426Ssam npeinit_locked(sc); 1440164426Ssam} 1441164426Ssam 1442164426Ssamstatic int 1443164426Ssamnpeioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1444164426Ssam{ 1445164426Ssam struct npe_softc *sc = ifp->if_softc; 1446164426Ssam struct mii_data *mii; 1447164426Ssam struct ifreq *ifr = (struct ifreq *)data; 1448164426Ssam int error = 0; 1449164426Ssam#ifdef DEVICE_POLLING 1450164426Ssam int mask; 1451164426Ssam#endif 1452164426Ssam 1453164426Ssam switch (cmd) { 1454164426Ssam case SIOCSIFFLAGS: 1455164426Ssam NPE_LOCK(sc); 1456164426Ssam if ((ifp->if_flags & IFF_UP) == 0 && 1457164426Ssam ifp->if_drv_flags & IFF_DRV_RUNNING) { 1458164426Ssam ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1459164426Ssam npestop(sc); 1460164426Ssam } else { 1461164426Ssam /* reinitialize card on any parameter change */ 1462164426Ssam npeinit_locked(sc); 1463164426Ssam } 1464164426Ssam NPE_UNLOCK(sc); 1465164426Ssam break; 1466164426Ssam 1467164426Ssam case SIOCADDMULTI: 1468164426Ssam case SIOCDELMULTI: 1469164426Ssam /* update multicast filter list. */ 1470164426Ssam NPE_LOCK(sc); 1471164426Ssam npe_setmcast(sc); 1472164426Ssam NPE_UNLOCK(sc); 1473164426Ssam error = 0; 1474164426Ssam break; 1475164426Ssam 1476164426Ssam case SIOCSIFMEDIA: 1477164426Ssam case SIOCGIFMEDIA: 1478164426Ssam mii = device_get_softc(sc->sc_mii); 1479164426Ssam error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1480164426Ssam break; 1481164426Ssam 1482164426Ssam#ifdef DEVICE_POLLING 1483164426Ssam case SIOCSIFCAP: 1484164426Ssam mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1485164426Ssam if (mask & IFCAP_POLLING) { 1486164426Ssam if (ifr->ifr_reqcap & IFCAP_POLLING) { 1487164426Ssam error = ether_poll_register(npe_poll, ifp); 1488164426Ssam if (error) 1489164426Ssam return error; 1490164426Ssam NPE_LOCK(sc); 1491164426Ssam /* disable callbacks XXX txdone is shared */ 1492164426Ssam ixpqmgr_notify_disable(sc->rx_qid); 1493164426Ssam ixpqmgr_notify_disable(sc->tx_doneqid); 1494164426Ssam ifp->if_capenable |= IFCAP_POLLING; 1495164426Ssam NPE_UNLOCK(sc); 1496164426Ssam } else { 1497164426Ssam error = ether_poll_deregister(ifp); 1498164426Ssam /* NB: always enable qmgr callbacks */ 1499164426Ssam NPE_LOCK(sc); 1500164426Ssam /* enable qmgr callbacks */ 1501164426Ssam ixpqmgr_notify_enable(sc->rx_qid, 1502164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E); 1503164426Ssam ixpqmgr_notify_enable(sc->tx_doneqid, 1504164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E); 1505164426Ssam ifp->if_capenable &= ~IFCAP_POLLING; 1506164426Ssam NPE_UNLOCK(sc); 1507164426Ssam } 1508164426Ssam } 1509164426Ssam break; 1510164426Ssam#endif 1511164426Ssam default: 1512164426Ssam error = ether_ioctl(ifp, cmd, data); 1513164426Ssam break; 1514164426Ssam } 1515164426Ssam return error; 1516164426Ssam} 1517164426Ssam 1518164426Ssam/* 1519164426Ssam * Setup a traffic class -> rx queue mapping. 1520164426Ssam */ 1521164426Ssamstatic int 1522164426Ssamnpe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1523164426Ssam{ 1524164426Ssam uint32_t msg[2]; 1525164426Ssam 1526186352Ssam msg[0] = (NPE_SETRXQOSENTRY << 24) | (sc->sc_npeid << 20) | classix; 1527164426Ssam msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1528186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1529164426Ssam} 1530164426Ssam 1531186352Ssamstatic int 1532186352Ssamnpe_setfirewallmode(struct npe_softc *sc, int onoff) 1533186352Ssam{ 1534186352Ssam uint32_t msg[2]; 1535186352Ssam 1536186352Ssam /* XXX honor onoff */ 1537186352Ssam msg[0] = (NPE_SETFIREWALLMODE << 24) | (sc->sc_npeid << 20); 1538186352Ssam msg[1] = 0; 1539186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1540186352Ssam} 1541186352Ssam 1542164426Ssam/* 1543164426Ssam * Update and reset the statistics in the NPE. 1544164426Ssam */ 1545164426Ssamstatic int 1546164426Ssamnpe_updatestats(struct npe_softc *sc) 1547164426Ssam{ 1548164426Ssam uint32_t msg[2]; 1549164426Ssam 1550164426Ssam msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1551164426Ssam msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1552186352Ssam return ixpnpe_sendmsg_async(sc->sc_npe, msg); 1553164426Ssam} 1554164426Ssam 1555164426Ssam#if 0 1556164426Ssam/* 1557164426Ssam * Get the current statistics block. 1558164426Ssam */ 1559164426Ssamstatic int 1560164426Ssamnpe_getstats(struct npe_softc *sc) 1561164426Ssam{ 1562164426Ssam uint32_t msg[2]; 1563164426Ssam 1564164426Ssam msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1565164426Ssam msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1566164426Ssam return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1567164426Ssam} 1568164426Ssam 1569164426Ssam/* 1570164426Ssam * Query the image id of the loaded firmware. 1571164426Ssam */ 1572164426Ssamstatic uint32_t 1573164426Ssamnpe_getimageid(struct npe_softc *sc) 1574164426Ssam{ 1575164426Ssam uint32_t msg[2]; 1576164426Ssam 1577164426Ssam msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1578164426Ssam msg[1] = 0; 1579186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1580164426Ssam} 1581164426Ssam 1582164426Ssam/* 1583164426Ssam * Enable/disable loopback. 1584164426Ssam */ 1585164426Ssamstatic int 1586164426Ssamnpe_setloopback(struct npe_softc *sc, int ena) 1587164426Ssam{ 1588164426Ssam uint32_t msg[2]; 1589164426Ssam 1590164426Ssam msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1591164426Ssam msg[1] = 0; 1592186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1593164426Ssam} 1594164426Ssam#endif 1595164426Ssam 1596164426Ssamstatic void 1597164426Ssamnpe_child_detached(device_t dev, device_t child) 1598164426Ssam{ 1599164426Ssam struct npe_softc *sc; 1600164426Ssam 1601164426Ssam sc = device_get_softc(dev); 1602164426Ssam if (child == sc->sc_mii) 1603164426Ssam sc->sc_mii = NULL; 1604164426Ssam} 1605164426Ssam 1606164426Ssam/* 1607164426Ssam * MII bus support routines. 1608164426Ssam */ 1609186352Ssam#define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1610186352Ssam#define MII_WR4(sc, reg, v) \ 1611186352Ssam bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1612186352Ssam 1613164426Ssamstatic uint32_t 1614164426Ssamnpe_mii_mdio_read(struct npe_softc *sc, int reg) 1615164426Ssam{ 1616164426Ssam uint32_t v; 1617164426Ssam 1618164426Ssam /* NB: registers are known to be sequential */ 1619164426Ssam v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1620164426Ssam v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1621164426Ssam v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1622164426Ssam v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1623164426Ssam return v; 1624164426Ssam} 1625164426Ssam 1626164426Ssamstatic void 1627164426Ssamnpe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1628164426Ssam{ 1629164426Ssam /* NB: registers are known to be sequential */ 1630164426Ssam MII_WR4(sc, reg+0, cmd & 0xff); 1631164426Ssam MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1632164426Ssam MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1633164426Ssam MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1634164426Ssam} 1635164426Ssam 1636164426Ssamstatic int 1637164426Ssamnpe_mii_mdio_wait(struct npe_softc *sc) 1638164426Ssam{ 1639164426Ssam uint32_t v; 1640164426Ssam int i; 1641164426Ssam 1642186352Ssam /* NB: typically this takes 25-30 trips */ 1643186352Ssam for (i = 0; i < 1000; i++) { 1644164426Ssam v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1645164426Ssam if ((v & NPE_MII_GO) == 0) 1646164426Ssam return 1; 1647186352Ssam DELAY(1); 1648164426Ssam } 1649186352Ssam device_printf(sc->sc_dev, "%s: timeout after ~1ms, cmd 0x%x\n", 1650186352Ssam __func__, v); 1651164426Ssam return 0; /* NB: timeout */ 1652164426Ssam} 1653164426Ssam 1654164426Ssamstatic int 1655164426Ssamnpe_miibus_readreg(device_t dev, int phy, int reg) 1656164426Ssam{ 1657164426Ssam struct npe_softc *sc = device_get_softc(dev); 1658164426Ssam uint32_t v; 1659164426Ssam 1660177505Ssam if (phy != sc->sc_phy) /* XXX no auto-detect */ 1661164426Ssam return 0xffff; 1662186352Ssam v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) | NPE_MII_GO; 1663164426Ssam npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1664164426Ssam if (npe_mii_mdio_wait(sc)) 1665164426Ssam v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1666164426Ssam else 1667164426Ssam v = 0xffff | NPE_MII_READ_FAIL; 1668164426Ssam return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1669164426Ssam} 1670164426Ssam 1671164426Ssamstatic void 1672164426Ssamnpe_miibus_writereg(device_t dev, int phy, int reg, int data) 1673164426Ssam{ 1674164426Ssam struct npe_softc *sc = device_get_softc(dev); 1675164426Ssam uint32_t v; 1676164426Ssam 1677177505Ssam if (phy != sc->sc_phy) /* XXX */ 1678164426Ssam return; 1679164426Ssam v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1680164426Ssam | data | NPE_MII_WRITE 1681164426Ssam | NPE_MII_GO; 1682164426Ssam npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1683164426Ssam /* XXX complain about timeout */ 1684164426Ssam (void) npe_mii_mdio_wait(sc); 1685164426Ssam} 1686164426Ssam 1687164426Ssamstatic void 1688164426Ssamnpe_miibus_statchg(device_t dev) 1689164426Ssam{ 1690164426Ssam struct npe_softc *sc = device_get_softc(dev); 1691164426Ssam struct mii_data *mii = device_get_softc(sc->sc_mii); 1692164426Ssam uint32_t tx1, rx1; 1693164426Ssam 1694164426Ssam /* sync MAC duplex state */ 1695164426Ssam tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1696164426Ssam rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1697164426Ssam if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1698164426Ssam tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1699164426Ssam rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1700164426Ssam } else { 1701164426Ssam tx1 |= NPE_TX_CNTRL1_DUPLEX; 1702164426Ssam rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1703164426Ssam } 1704164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1705164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1706164426Ssam} 1707164426Ssam 1708164426Ssamstatic device_method_t npe_methods[] = { 1709164426Ssam /* Device interface */ 1710164426Ssam DEVMETHOD(device_probe, npe_probe), 1711164426Ssam DEVMETHOD(device_attach, npe_attach), 1712164426Ssam DEVMETHOD(device_detach, npe_detach), 1713164426Ssam 1714164426Ssam /* Bus interface */ 1715164426Ssam DEVMETHOD(bus_child_detached, npe_child_detached), 1716164426Ssam 1717164426Ssam /* MII interface */ 1718164426Ssam DEVMETHOD(miibus_readreg, npe_miibus_readreg), 1719164426Ssam DEVMETHOD(miibus_writereg, npe_miibus_writereg), 1720164426Ssam DEVMETHOD(miibus_statchg, npe_miibus_statchg), 1721164426Ssam 1722164426Ssam { 0, 0 } 1723164426Ssam}; 1724164426Ssam 1725164426Ssamstatic driver_t npe_driver = { 1726164426Ssam "npe", 1727164426Ssam npe_methods, 1728164426Ssam sizeof(struct npe_softc), 1729164426Ssam}; 1730164426Ssam 1731164426SsamDRIVER_MODULE(npe, ixp, npe_driver, npe_devclass, 0, 0); 1732164426SsamDRIVER_MODULE(miibus, npe, miibus_driver, miibus_devclass, 0, 0); 1733164426SsamMODULE_DEPEND(npe, ixpqmgr, 1, 1, 1); 1734164426SsamMODULE_DEPEND(npe, miibus, 1, 1, 1); 1735164426SsamMODULE_DEPEND(npe, ether, 1, 1, 1); 1736