if_npe.c revision 186420
1164426Ssam/*- 2177505Ssam * Copyright (c) 2006-2008 Sam Leffler. All rights reserved. 3164426Ssam * 4164426Ssam * Redistribution and use in source and binary forms, with or without 5164426Ssam * modification, are permitted provided that the following conditions 6164426Ssam * are met: 7164426Ssam * 1. Redistributions of source code must retain the above copyright 8164426Ssam * notice, this list of conditions and the following disclaimer. 9164426Ssam * 2. Redistributions in binary form must reproduce the above copyright 10164426Ssam * notice, this list of conditions and the following disclaimer in the 11164426Ssam * documentation and/or other materials provided with the distribution. 12164426Ssam * 13164426Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14164426Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15164426Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16164426Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17164426Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18164426Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19164426Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20164426Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21164426Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22164426Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23164426Ssam */ 24164426Ssam 25164426Ssam#include <sys/cdefs.h> 26164426Ssam__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/if_npe.c 186420 2008-12-23 04:51:46Z sam $"); 27164426Ssam 28164426Ssam/* 29164426Ssam * Intel XScale NPE Ethernet driver. 30164426Ssam * 31164426Ssam * This driver handles the two ports present on the IXP425. 32164426Ssam * Packet processing is done by the Network Processing Engines 33164426Ssam * (NPE's) that work together with a MAC and PHY. The MAC 34164426Ssam * is also mapped to the XScale cpu; the PHY is accessed via 35164426Ssam * the MAC. NPE-XScale communication happens through h/w 36164426Ssam * queues managed by the Q Manager block. 37164426Ssam * 38164426Ssam * The code here replaces the ethAcc, ethMii, and ethDB classes 39164426Ssam * in the Intel Access Library (IAL) and the OS-specific driver. 40164426Ssam * 41164426Ssam * XXX add vlan support 42164426Ssam */ 43164426Ssam#ifdef HAVE_KERNEL_OPTION_HEADERS 44164426Ssam#include "opt_device_polling.h" 45164426Ssam#endif 46164426Ssam 47164426Ssam#include <sys/param.h> 48164426Ssam#include <sys/systm.h> 49164426Ssam#include <sys/bus.h> 50164426Ssam#include <sys/kernel.h> 51164426Ssam#include <sys/mbuf.h> 52164426Ssam#include <sys/malloc.h> 53164426Ssam#include <sys/module.h> 54164426Ssam#include <sys/rman.h> 55164426Ssam#include <sys/socket.h> 56164426Ssam#include <sys/sockio.h> 57164426Ssam#include <sys/sysctl.h> 58164426Ssam#include <sys/endian.h> 59164426Ssam#include <machine/bus.h> 60164426Ssam 61164426Ssam#include <net/ethernet.h> 62164426Ssam#include <net/if.h> 63164426Ssam#include <net/if_arp.h> 64164426Ssam#include <net/if_dl.h> 65164426Ssam#include <net/if_media.h> 66164426Ssam#include <net/if_mib.h> 67164426Ssam#include <net/if_types.h> 68164426Ssam 69164426Ssam#ifdef INET 70164426Ssam#include <netinet/in.h> 71164426Ssam#include <netinet/in_systm.h> 72164426Ssam#include <netinet/in_var.h> 73164426Ssam#include <netinet/ip.h> 74164426Ssam#endif 75164426Ssam 76164426Ssam#include <net/bpf.h> 77164426Ssam#include <net/bpfdesc.h> 78164426Ssam 79164426Ssam#include <arm/xscale/ixp425/ixp425reg.h> 80164426Ssam#include <arm/xscale/ixp425/ixp425var.h> 81164426Ssam#include <arm/xscale/ixp425/ixp425_qmgr.h> 82164426Ssam#include <arm/xscale/ixp425/ixp425_npevar.h> 83164426Ssam 84164426Ssam#include <dev/mii/mii.h> 85164426Ssam#include <dev/mii/miivar.h> 86164426Ssam#include <arm/xscale/ixp425/if_npereg.h> 87164426Ssam 88186352Ssam#include <machine/armreg.h> 89186352Ssam 90164426Ssam#include "miibus_if.h" 91164426Ssam 92166064Scognet/* 93166064Scognet * XXX: For the main bus dma tag. Can go away if the new method to get the 94166064Scognet * dma tag from the parent got MFC'd into RELENG_6. 95166064Scognet */ 96166064Scognetextern struct ixp425_softc *ixp425_softc; 97166064Scognet 98164426Ssamstruct npebuf { 99164426Ssam struct npebuf *ix_next; /* chain to next buffer */ 100164426Ssam void *ix_m; /* backpointer to mbuf */ 101164426Ssam bus_dmamap_t ix_map; /* bus dma map for associated data */ 102164426Ssam struct npehwbuf *ix_hw; /* associated h/w block */ 103164426Ssam uint32_t ix_neaddr; /* phys address of ix_hw */ 104164426Ssam}; 105164426Ssam 106164426Ssamstruct npedma { 107164426Ssam const char* name; 108164426Ssam int nbuf; /* # npebuf's allocated */ 109164426Ssam bus_dma_tag_t mtag; /* bus dma tag for mbuf data */ 110164426Ssam struct npehwbuf *hwbuf; /* NPE h/w buffers */ 111164426Ssam bus_dma_tag_t buf_tag; /* tag+map for NPE buffers */ 112164426Ssam bus_dmamap_t buf_map; 113164426Ssam bus_addr_t buf_phys; /* phys addr of buffers */ 114164426Ssam struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 115164426Ssam}; 116164426Ssam 117164426Ssamstruct npe_softc { 118164426Ssam /* XXX mii requires this be first; do not move! */ 119164426Ssam struct ifnet *sc_ifp; /* ifnet pointer */ 120164426Ssam struct mtx sc_mtx; /* basically a perimeter lock */ 121164426Ssam device_t sc_dev; 122164426Ssam bus_space_tag_t sc_iot; 123164426Ssam bus_space_handle_t sc_ioh; /* MAC register window */ 124164426Ssam device_t sc_mii; /* child miibus */ 125164426Ssam bus_space_handle_t sc_miih; /* MII register window */ 126186352Ssam int sc_npeid; 127164426Ssam struct ixpnpe_softc *sc_npe; /* NPE support */ 128164426Ssam int sc_debug; /* DPRINTF* control */ 129164426Ssam int sc_tickinterval; 130164426Ssam struct callout tick_ch; /* Tick callout */ 131166339Skevlo int npe_watchdog_timer; 132164426Ssam struct npedma txdma; 133164426Ssam struct npebuf *tx_free; /* list of free tx buffers */ 134164426Ssam struct npedma rxdma; 135164426Ssam bus_addr_t buf_phys; /* XXX for returning a value */ 136164426Ssam int rx_qid; /* rx qid */ 137164426Ssam int rx_freeqid; /* rx free buffers qid */ 138164426Ssam int tx_qid; /* tx qid */ 139164426Ssam int tx_doneqid; /* tx completed qid */ 140177505Ssam int sc_phy; /* PHY id */ 141164426Ssam struct ifmib_iso_8802_3 mibdata; 142164426Ssam bus_dma_tag_t sc_stats_tag; /* bus dma tag for stats block */ 143164426Ssam struct npestats *sc_stats; 144164426Ssam bus_dmamap_t sc_stats_map; 145164426Ssam bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 146164426Ssam}; 147164426Ssam 148164426Ssam/* 149186352Ssam * Static configuration for IXP425. The tx and 150164426Ssam * rx free Q id's are fixed by the NPE microcode. The 151164426Ssam * rx Q id's are programmed to be separate to simplify 152164426Ssam * multi-port processing. It may be better to handle 153164426Ssam * all traffic through one Q (as done by the Intel drivers). 154164426Ssam * 155164426Ssam * Note that the PHY's are accessible only from MAC A 156164426Ssam * on the IXP425. This and other platform-specific 157164426Ssam * assumptions probably need to be handled through hints. 158164426Ssam */ 159164426Ssamstatic const struct { 160186352Ssam uint32_t macbase; 161164426Ssam uint32_t miibase; 162177505Ssam int phy; /* phy id */ 163164426Ssam uint8_t rx_qid; 164164426Ssam uint8_t rx_freeqid; 165164426Ssam uint8_t tx_qid; 166164426Ssam uint8_t tx_doneqid; 167186352Ssam} npeconfig[NPE_MAX] = { 168186352Ssam [NPE_A] = { 169186352Ssam .macbase = IXP435_MAC_A_HWBASE, 170186352Ssam .miibase = IXP425_MAC_C_HWBASE, 171186352Ssam .phy = 2, 172186352Ssam .rx_qid = 4, 173186352Ssam .rx_freeqid = 26, 174186352Ssam .tx_qid = 23, 175186352Ssam .tx_doneqid = 31 176186352Ssam }, 177186352Ssam [NPE_B] = { 178186352Ssam .macbase = IXP425_MAC_B_HWBASE, 179186352Ssam .miibase = IXP425_MAC_C_HWBASE, 180177505Ssam .phy = 0, 181164426Ssam .rx_qid = 4, 182164426Ssam .rx_freeqid = 27, 183164426Ssam .tx_qid = 24, 184164426Ssam .tx_doneqid = 31 185164426Ssam }, 186186352Ssam [NPE_C] = { 187186352Ssam .macbase = IXP425_MAC_C_HWBASE, 188186352Ssam .miibase = IXP425_MAC_C_HWBASE, 189177505Ssam .phy = 1, 190164426Ssam .rx_qid = 12, 191164426Ssam .rx_freeqid = 28, 192164426Ssam .tx_qid = 25, 193164426Ssam .tx_doneqid = 31 194164426Ssam }, 195164426Ssam}; 196164426Ssamstatic struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 197164426Ssam 198164426Ssamstatic __inline uint32_t 199164426SsamRD4(struct npe_softc *sc, bus_size_t off) 200164426Ssam{ 201164426Ssam return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 202164426Ssam} 203164426Ssam 204164426Ssamstatic __inline void 205164426SsamWR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 206164426Ssam{ 207164426Ssam bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 208164426Ssam} 209164426Ssam 210164426Ssam#define NPE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 211164426Ssam#define NPE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 212164426Ssam#define NPE_LOCK_INIT(_sc) \ 213164426Ssam mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 214164426Ssam MTX_NETWORK_LOCK, MTX_DEF) 215164426Ssam#define NPE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 216164426Ssam#define NPE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 217164426Ssam#define NPE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 218164426Ssam 219164426Ssamstatic devclass_t npe_devclass; 220164426Ssam 221186352Ssamstatic int override_npeid(device_t, const char *resname, int *val); 222164426Ssamstatic int npe_activate(device_t dev); 223164426Ssamstatic void npe_deactivate(device_t dev); 224164426Ssamstatic int npe_ifmedia_update(struct ifnet *ifp); 225164426Ssamstatic void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 226164426Ssamstatic void npe_setmac(struct npe_softc *sc, u_char *eaddr); 227164426Ssamstatic void npe_getmac(struct npe_softc *sc, u_char *eaddr); 228164426Ssamstatic void npe_txdone(int qid, void *arg); 229164426Ssamstatic int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 230164426Ssam struct mbuf *); 231164426Ssamstatic void npe_rxdone(int qid, void *arg); 232164426Ssamstatic void npeinit(void *); 233164426Ssamstatic void npestart_locked(struct ifnet *); 234164426Ssamstatic void npestart(struct ifnet *); 235164426Ssamstatic void npestop(struct npe_softc *); 236166339Skevlostatic void npewatchdog(struct npe_softc *); 237164426Ssamstatic int npeioctl(struct ifnet * ifp, u_long, caddr_t); 238164426Ssam 239164426Ssamstatic int npe_setrxqosentry(struct npe_softc *, int classix, 240164426Ssam int trafclass, int qid); 241186352Ssamstatic int npe_setfirewallmode(struct npe_softc *, int onoff); 242164426Ssamstatic int npe_updatestats(struct npe_softc *); 243164426Ssam#if 0 244164426Ssamstatic int npe_getstats(struct npe_softc *); 245164426Ssamstatic uint32_t npe_getimageid(struct npe_softc *); 246164426Ssamstatic int npe_setloopback(struct npe_softc *, int ena); 247164426Ssam#endif 248164426Ssam 249164426Ssam/* NB: all tx done processing goes through one queue */ 250164426Ssamstatic int tx_doneqid = -1; 251164426Ssam 252186352SsamSYSCTL_NODE(_hw, OID_AUTO, npe, CTLFLAG_RD, 0, "IXP4XX NPE driver parameters"); 253164426Ssam 254164426Ssamstatic int npe_debug = 0; 255164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, debug, CTLFLAG_RW, &npe_debug, 256186352Ssam 0, "IXP4XX NPE network interface debug msgs"); 257186420SsamTUNABLE_INT("hw.npe.debug", &npe_debug); 258164426Ssam#define DPRINTF(sc, fmt, ...) do { \ 259164426Ssam if (sc->sc_debug) device_printf(sc->sc_dev, fmt, __VA_ARGS__); \ 260164426Ssam} while (0) 261164426Ssam#define DPRINTFn(n, sc, fmt, ...) do { \ 262164426Ssam if (sc->sc_debug >= n) device_printf(sc->sc_dev, fmt, __VA_ARGS__);\ 263164426Ssam} while (0) 264164426Ssamstatic int npe_tickinterval = 3; /* npe_tick frequency (secs) */ 265164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, tickinterval, CTLFLAG_RD, &npe_tickinterval, 266164426Ssam 0, "periodic work interval (secs)"); 267164426SsamTUNABLE_INT("hw.npe.tickinterval", &npe_tickinterval); 268164426Ssam 269164426Ssamstatic int npe_rxbuf = 64; /* # rx buffers to allocate */ 270164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, rxbuf, CTLFLAG_RD, &npe_rxbuf, 271164426Ssam 0, "rx buffers allocated"); 272164426SsamTUNABLE_INT("hw.npe.rxbuf", &npe_rxbuf); 273164426Ssamstatic int npe_txbuf = 128; /* # tx buffers to allocate */ 274164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, txbuf, CTLFLAG_RD, &npe_txbuf, 275164426Ssam 0, "tx buffers allocated"); 276164426SsamTUNABLE_INT("hw.npe.txbuf", &npe_txbuf); 277164426Ssam 278164426Ssamstatic int 279186352Ssamunit2npeid(int unit) 280186352Ssam{ 281186352Ssam static const int npeidmap[2][3] = { 282186352Ssam /* on 425 A is for HSS, B & C are for Ethernet */ 283186352Ssam { NPE_B, NPE_C, -1 }, /* IXP425 */ 284186352Ssam /* 435 only has A & C, order C then A */ 285186352Ssam { NPE_C, NPE_A, -1 }, /* IXP435 */ 286186352Ssam }; 287186352Ssam /* XXX check feature register instead */ 288186352Ssam return (unit < 3 ? npeidmap[ 289186352Ssam (cpu_id() & CPU_ID_CPU_MASK) == CPU_ID_IXP435][unit] : -1); 290186352Ssam} 291186352Ssam 292186352Ssamstatic int 293164426Ssamnpe_probe(device_t dev) 294164426Ssam{ 295186352Ssam static const char *desc[NPE_MAX] = { 296186352Ssam [NPE_A] = "IXP NPE-A", 297186352Ssam [NPE_B] = "IXP NPE-B", 298186352Ssam [NPE_C] = "IXP NPE-C" 299186352Ssam }; 300186420Ssam int unit = device_get_unit(dev); 301186352Ssam int npeid; 302164426Ssam 303186420Ssam if (unit > 2 || 304186420Ssam (ixp4xx_read_feature_bits() & 305186420Ssam (unit == 0 ? EXP_FCTRL_ETH0 : EXP_FCTRL_ETH1)) == 0) 306186420Ssam return EINVAL; 307186420Ssam 308186352Ssam npeid = -1; 309186352Ssam if (!override_npeid(dev, "npeid", &npeid)) 310186420Ssam npeid = unit2npeid(unit); 311186352Ssam if (npeid == -1) { 312186420Ssam device_printf(dev, "unit %d not supported\n", unit); 313164426Ssam return EINVAL; 314164426Ssam } 315186352Ssam device_set_desc(dev, desc[npeid]); 316164426Ssam return 0; 317164426Ssam} 318164426Ssam 319164426Ssamstatic int 320164426Ssamnpe_attach(device_t dev) 321164426Ssam{ 322164426Ssam struct npe_softc *sc = device_get_softc(dev); 323164426Ssam struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); 324164426Ssam struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 325164426Ssam struct sysctl_oid *tree = device_get_sysctl_tree(dev); 326186352Ssam struct ifnet *ifp; 327164426Ssam int error; 328164426Ssam u_char eaddr[6]; 329164426Ssam 330164426Ssam sc->sc_dev = dev; 331164426Ssam sc->sc_iot = sa->sc_iot; 332164426Ssam NPE_LOCK_INIT(sc); 333164426Ssam callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 334164426Ssam sc->sc_debug = npe_debug; 335164426Ssam sc->sc_tickinterval = npe_tickinterval; 336164426Ssam 337186352Ssam ifp = if_alloc(IFT_ETHER); 338186352Ssam if (ifp == NULL) { 339186352Ssam device_printf(dev, "cannot allocate ifnet\n"); 340164426Ssam error = EIO; /* XXX */ 341164426Ssam goto out; 342164426Ssam } 343186352Ssam /* NB: must be setup prior to invoking mii code */ 344186352Ssam sc->sc_ifp = ifp; 345164426Ssam 346164426Ssam error = npe_activate(dev); 347186352Ssam if (error) { 348186352Ssam device_printf(dev, "cannot activate npe\n"); 349164426Ssam goto out; 350186352Ssam } 351164426Ssam 352164426Ssam npe_getmac(sc, eaddr); 353164426Ssam 354164426Ssam ifp->if_softc = sc; 355164426Ssam if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 356164426Ssam ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 357164426Ssam ifp->if_start = npestart; 358164426Ssam ifp->if_ioctl = npeioctl; 359164426Ssam ifp->if_init = npeinit; 360164426Ssam IFQ_SET_MAXLEN(&ifp->if_snd, sc->txdma.nbuf - 1); 361166625Smlaier ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 362164426Ssam IFQ_SET_READY(&ifp->if_snd); 363164426Ssam ifp->if_linkmib = &sc->mibdata; 364164426Ssam ifp->if_linkmiblen = sizeof(sc->mibdata); 365164426Ssam sc->mibdata.dot3Compliance = DOT3COMPLIANCE_STATS; 366164426Ssam#ifdef DEVICE_POLLING 367164426Ssam ifp->if_capabilities |= IFCAP_POLLING; 368164426Ssam#endif 369164426Ssam 370164426Ssam SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug", 371164426Ssam CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 372164426Ssam SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tickinterval", 373164426Ssam CTLFLAG_RW, &sc->sc_tickinterval, 0, "periodic work frequency"); 374164426Ssam 375164426Ssam ether_ifattach(ifp, eaddr); 376164426Ssam return 0; 377164426Ssamout: 378164426Ssam if (ifp != NULL) 379164426Ssam if_free(ifp); 380186352Ssam NPE_LOCK_DESTROY(sc); 381186352Ssam npe_deactivate(dev); 382164426Ssam return error; 383164426Ssam} 384164426Ssam 385164426Ssamstatic int 386164426Ssamnpe_detach(device_t dev) 387164426Ssam{ 388164426Ssam struct npe_softc *sc = device_get_softc(dev); 389164426Ssam struct ifnet *ifp = sc->sc_ifp; 390164426Ssam 391164426Ssam#ifdef DEVICE_POLLING 392164426Ssam if (ifp->if_capenable & IFCAP_POLLING) 393164426Ssam ether_poll_deregister(ifp); 394164426Ssam#endif 395164426Ssam npestop(sc); 396164426Ssam if (ifp != NULL) { 397164426Ssam ether_ifdetach(ifp); 398164426Ssam if_free(ifp); 399164426Ssam } 400164426Ssam NPE_LOCK_DESTROY(sc); 401164426Ssam npe_deactivate(dev); 402164426Ssam return 0; 403164426Ssam} 404164426Ssam 405164426Ssam/* 406164426Ssam * Compute and install the multicast filter. 407164426Ssam */ 408164426Ssamstatic void 409164426Ssamnpe_setmcast(struct npe_softc *sc) 410164426Ssam{ 411164426Ssam struct ifnet *ifp = sc->sc_ifp; 412164426Ssam uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 413164426Ssam int i; 414164426Ssam 415164426Ssam if (ifp->if_flags & IFF_PROMISC) { 416164426Ssam memset(mask, 0, ETHER_ADDR_LEN); 417164426Ssam memset(addr, 0, ETHER_ADDR_LEN); 418164426Ssam } else if (ifp->if_flags & IFF_ALLMULTI) { 419164426Ssam static const uint8_t allmulti[ETHER_ADDR_LEN] = 420164426Ssam { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 421164426Ssam memcpy(mask, allmulti, ETHER_ADDR_LEN); 422164426Ssam memcpy(addr, allmulti, ETHER_ADDR_LEN); 423164426Ssam } else { 424164426Ssam uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 425164426Ssam struct ifmultiaddr *ifma; 426164426Ssam const uint8_t *mac; 427164426Ssam 428164426Ssam memset(clr, 0, ETHER_ADDR_LEN); 429164426Ssam memset(set, 0xff, ETHER_ADDR_LEN); 430164426Ssam 431164426Ssam IF_ADDR_LOCK(ifp); 432164426Ssam TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 433164426Ssam if (ifma->ifma_addr->sa_family != AF_LINK) 434164426Ssam continue; 435164426Ssam mac = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 436164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 437164426Ssam clr[i] |= mac[i]; 438164426Ssam set[i] &= mac[i]; 439164426Ssam } 440164426Ssam } 441164426Ssam IF_ADDR_UNLOCK(ifp); 442164426Ssam 443164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 444164426Ssam mask[i] = set[i] | ~clr[i]; 445164426Ssam addr[i] = set[i]; 446164426Ssam } 447164426Ssam } 448164426Ssam 449164426Ssam /* 450164426Ssam * Write the mask and address registers. 451164426Ssam */ 452164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 453164426Ssam WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 454164426Ssam WR4(sc, NPE_MAC_ADDR(i), addr[i]); 455164426Ssam } 456164426Ssam} 457164426Ssam 458164426Ssamstatic void 459164426Ssamnpe_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 460164426Ssam{ 461164426Ssam struct npe_softc *sc; 462164426Ssam 463164426Ssam if (error != 0) 464164426Ssam return; 465164426Ssam sc = (struct npe_softc *)arg; 466164426Ssam sc->buf_phys = segs[0].ds_addr; 467164426Ssam} 468164426Ssam 469164426Ssamstatic int 470164426Ssamnpe_dma_setup(struct npe_softc *sc, struct npedma *dma, 471164426Ssam const char *name, int nbuf, int maxseg) 472164426Ssam{ 473164426Ssam int error, i; 474164426Ssam 475183886Ssam memset(dma, 0, sizeof(*dma)); 476164426Ssam 477164426Ssam dma->name = name; 478164426Ssam dma->nbuf = nbuf; 479164426Ssam 480164426Ssam /* DMA tag for mapped mbufs */ 481166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, 1, 0, 482164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 483164426Ssam MCLBYTES, maxseg, MCLBYTES, 0, 484164426Ssam busdma_lock_mutex, &sc->sc_mtx, &dma->mtag); 485164426Ssam if (error != 0) { 486164426Ssam device_printf(sc->sc_dev, "unable to create %s mbuf dma tag, " 487164426Ssam "error %u\n", dma->name, error); 488164426Ssam return error; 489164426Ssam } 490164426Ssam 491164426Ssam /* DMA tag and map for the NPE buffers */ 492166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 493164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 494164426Ssam nbuf * sizeof(struct npehwbuf), 1, 495164426Ssam nbuf * sizeof(struct npehwbuf), 0, 496164426Ssam busdma_lock_mutex, &sc->sc_mtx, &dma->buf_tag); 497164426Ssam if (error != 0) { 498164426Ssam device_printf(sc->sc_dev, 499164426Ssam "unable to create %s npebuf dma tag, error %u\n", 500164426Ssam dma->name, error); 501164426Ssam return error; 502164426Ssam } 503164426Ssam /* XXX COHERENT for now */ 504164426Ssam if (bus_dmamem_alloc(dma->buf_tag, (void **)&dma->hwbuf, 505164426Ssam BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 506164426Ssam &dma->buf_map) != 0) { 507164426Ssam device_printf(sc->sc_dev, 508164426Ssam "unable to allocate memory for %s h/w buffers, error %u\n", 509164426Ssam dma->name, error); 510164426Ssam return error; 511164426Ssam } 512164426Ssam /* XXX M_TEMP */ 513164426Ssam dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 514164426Ssam if (dma->buf == NULL) { 515164426Ssam device_printf(sc->sc_dev, 516164426Ssam "unable to allocate memory for %s s/w buffers\n", 517164426Ssam dma->name); 518164426Ssam return error; 519164426Ssam } 520164426Ssam if (bus_dmamap_load(dma->buf_tag, dma->buf_map, 521164426Ssam dma->hwbuf, nbuf*sizeof(struct npehwbuf), npe_getaddr, sc, 0) != 0) { 522164426Ssam device_printf(sc->sc_dev, 523164426Ssam "unable to map memory for %s h/w buffers, error %u\n", 524164426Ssam dma->name, error); 525164426Ssam return error; 526164426Ssam } 527164426Ssam dma->buf_phys = sc->buf_phys; 528164426Ssam for (i = 0; i < dma->nbuf; i++) { 529164426Ssam struct npebuf *npe = &dma->buf[i]; 530164426Ssam struct npehwbuf *hw = &dma->hwbuf[i]; 531164426Ssam 532164426Ssam /* calculate offset to shared area */ 533164426Ssam npe->ix_neaddr = dma->buf_phys + 534164426Ssam ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 535164426Ssam KASSERT((npe->ix_neaddr & 0x1f) == 0, 536164426Ssam ("ixpbuf misaligned, PA 0x%x", npe->ix_neaddr)); 537164426Ssam error = bus_dmamap_create(dma->mtag, BUS_DMA_NOWAIT, 538164426Ssam &npe->ix_map); 539164426Ssam if (error != 0) { 540164426Ssam device_printf(sc->sc_dev, 541164426Ssam "unable to create dmamap for %s buffer %u, " 542164426Ssam "error %u\n", dma->name, i, error); 543164426Ssam return error; 544164426Ssam } 545164426Ssam npe->ix_hw = hw; 546164426Ssam } 547164426Ssam bus_dmamap_sync(dma->buf_tag, dma->buf_map, BUS_DMASYNC_PREWRITE); 548164426Ssam return 0; 549164426Ssam} 550164426Ssam 551164426Ssamstatic void 552164426Ssamnpe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 553164426Ssam{ 554164426Ssam int i; 555164426Ssam 556164426Ssam if (dma->hwbuf != NULL) { 557164426Ssam for (i = 0; i < dma->nbuf; i++) { 558164426Ssam struct npebuf *npe = &dma->buf[i]; 559164426Ssam bus_dmamap_destroy(dma->mtag, npe->ix_map); 560164426Ssam } 561164426Ssam bus_dmamap_unload(dma->buf_tag, dma->buf_map); 562164426Ssam bus_dmamem_free(dma->buf_tag, dma->hwbuf, dma->buf_map); 563164426Ssam } 564164426Ssam if (dma->buf != NULL) 565164426Ssam free(dma->buf, M_TEMP); 566164426Ssam if (dma->buf_tag) 567164426Ssam bus_dma_tag_destroy(dma->buf_tag); 568164426Ssam if (dma->mtag) 569164426Ssam bus_dma_tag_destroy(dma->mtag); 570164426Ssam memset(dma, 0, sizeof(*dma)); 571164426Ssam} 572164426Ssam 573164426Ssamstatic int 574186352Ssamoverride_addr(device_t dev, const char *resname, int *base) 575177505Ssam{ 576177505Ssam int unit = device_get_unit(dev); 577177505Ssam const char *resval; 578177505Ssam 579177505Ssam /* XXX warn for wrong hint type */ 580177505Ssam if (resource_string_value("npe", unit, resname, &resval) != 0) 581177505Ssam return 0; 582177505Ssam switch (resval[0]) { 583177505Ssam case 'A': 584186352Ssam *base = IXP435_MAC_A_HWBASE; 585177505Ssam break; 586177505Ssam case 'B': 587177505Ssam *base = IXP425_MAC_B_HWBASE; 588177505Ssam break; 589186352Ssam case 'C': 590186352Ssam *base = IXP425_MAC_C_HWBASE; 591186352Ssam break; 592177505Ssam default: 593177505Ssam device_printf(dev, "Warning, bad value %s for " 594177505Ssam "npe.%d.%s ignored\n", resval, unit, resname); 595177505Ssam return 0; 596177505Ssam } 597177505Ssam if (bootverbose) 598177505Ssam device_printf(dev, "using npe.%d.%s=%s override\n", 599177505Ssam unit, resname, resval); 600177505Ssam return 1; 601177505Ssam} 602177505Ssam 603177505Ssamstatic int 604186352Ssamoverride_npeid(device_t dev, const char *resname, int *npeid) 605186352Ssam{ 606186352Ssam int unit = device_get_unit(dev); 607186352Ssam const char *resval; 608186352Ssam 609186352Ssam /* XXX warn for wrong hint type */ 610186352Ssam if (resource_string_value("npe", unit, resname, &resval) != 0) 611186352Ssam return 0; 612186352Ssam switch (resval[0]) { 613186352Ssam case 'A': *npeid = NPE_A; break; 614186352Ssam case 'B': *npeid = NPE_B; break; 615186352Ssam case 'C': *npeid = NPE_C; break; 616186352Ssam default: 617186352Ssam device_printf(dev, "Warning, bad value %s for " 618186352Ssam "npe.%d.%s ignored\n", resval, unit, resname); 619186352Ssam return 0; 620186352Ssam } 621186352Ssam if (bootverbose) 622186352Ssam device_printf(dev, "using npe.%d.%s=%s override\n", 623186352Ssam unit, resname, resval); 624186352Ssam return 1; 625186352Ssam} 626186352Ssam 627186352Ssamstatic int 628177505Ssamoverride_unit(device_t dev, const char *resname, int *val, int min, int max) 629177505Ssam{ 630177505Ssam int unit = device_get_unit(dev); 631177505Ssam int resval; 632177505Ssam 633177505Ssam if (resource_int_value("npe", unit, resname, &resval) != 0) 634177505Ssam return 0; 635177505Ssam if (!(min <= resval && resval <= max)) { 636177505Ssam device_printf(dev, "Warning, bad value %d for npe.%d.%s " 637177505Ssam "ignored (value must be [%d-%d])\n", resval, unit, 638177505Ssam resname, min, max); 639177505Ssam return 0; 640177505Ssam } 641177505Ssam if (bootverbose) 642177505Ssam device_printf(dev, "using npe.%d.%s=%d override\n", 643177505Ssam unit, resname, resval); 644177505Ssam *val = resval; 645177505Ssam return 1; 646177505Ssam} 647177505Ssam 648186352Ssamstatic void 649186352Ssamnpe_mac_reset(struct npe_softc *sc) 650186352Ssam{ 651186352Ssam /* 652186352Ssam * Reset MAC core. 653186352Ssam */ 654186352Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 655186352Ssam DELAY(NPE_MAC_RESET_DELAY); 656186352Ssam /* configure MAC to generate MDC clock */ 657186352Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 658186352Ssam} 659186352Ssam 660186352Ssamstatic int 661164426Ssamnpe_activate(device_t dev) 662164426Ssam{ 663164426Ssam struct npe_softc * sc = device_get_softc(dev); 664186352Ssam int error, i, macbase, miibase; 665164426Ssam 666169954Ssam /* 667186352Ssam * Setup NEP ID, MAC, and MII bindings. We allow override 668186352Ssam * via hints to handle unexpected board configs. 669186352Ssam */ 670186352Ssam if (!override_npeid(dev, "npeid", &sc->sc_npeid)) 671186352Ssam sc->sc_npeid = unit2npeid(device_get_unit(dev)); 672186352Ssam sc->sc_npe = ixpnpe_attach(dev, sc->sc_npeid); 673186352Ssam if (sc->sc_npe == NULL) { 674186352Ssam device_printf(dev, "cannot attach ixpnpe\n"); 675186352Ssam return EIO; /* XXX */ 676186352Ssam } 677186352Ssam 678186352Ssam /* MAC */ 679186352Ssam if (!override_addr(dev, "mac", &macbase)) 680186352Ssam macbase = npeconfig[sc->sc_npeid].macbase; 681186352Ssam device_printf(sc->sc_dev, "MAC at 0x%x\n", macbase); 682186352Ssam if (bus_space_map(sc->sc_iot, macbase, IXP425_REG_SIZE, 0, &sc->sc_ioh)) { 683186352Ssam device_printf(dev, "cannot map mac registers 0x%x:0x%x\n", 684186352Ssam macbase, IXP425_REG_SIZE); 685186352Ssam return ENOMEM; 686186352Ssam } 687186352Ssam 688186352Ssam /* PHY */ 689186352Ssam if (!override_unit(dev, "phy", &sc->sc_phy, 0, MII_NPHY-1)) 690186352Ssam sc->sc_phy = npeconfig[sc->sc_npeid].phy; 691186352Ssam if (!override_addr(dev, "mii", &miibase)) 692186352Ssam miibase = npeconfig[sc->sc_npeid].miibase; 693186352Ssam device_printf(sc->sc_dev, "MII at 0x%x\n", miibase); 694186352Ssam if (miibase != macbase) { 695186352Ssam /* 696186352Ssam * PHY is mapped through a different MAC, setup an 697186352Ssam * additional mapping for frobbing the PHY registers. 698186352Ssam */ 699186352Ssam if (bus_space_map(sc->sc_iot, miibase, IXP425_REG_SIZE, 0, &sc->sc_miih)) { 700186352Ssam device_printf(dev, 701186352Ssam "cannot map MII registers 0x%x:0x%x\n", 702186352Ssam miibase, IXP425_REG_SIZE); 703186352Ssam return ENOMEM; 704186352Ssam } 705186352Ssam } else 706186352Ssam sc->sc_miih = sc->sc_ioh; 707186352Ssam 708186352Ssam /* 709186420Ssam * Load NPE firmware and start it running. 710169954Ssam */ 711186420Ssam error = ixpnpe_init(sc->sc_npe); 712186420Ssam if (error != 0) { 713186420Ssam device_printf(dev, "cannot init NPE (error %d)\n", error); 714186420Ssam return error; 715169954Ssam } 716164426Ssam 717186352Ssam /* probe for PHY */ 718186352Ssam if (mii_phy_probe(dev, &sc->sc_mii, npe_ifmedia_update, npe_ifmedia_status)) { 719186352Ssam device_printf(dev, "cannot find PHY %d.\n", sc->sc_phy); 720186352Ssam return ENXIO; 721177505Ssam } 722164426Ssam 723164426Ssam error = npe_dma_setup(sc, &sc->txdma, "tx", npe_txbuf, NPE_MAXSEG); 724164426Ssam if (error != 0) 725164426Ssam return error; 726164426Ssam error = npe_dma_setup(sc, &sc->rxdma, "rx", npe_rxbuf, 1); 727164426Ssam if (error != 0) 728164426Ssam return error; 729164426Ssam 730164426Ssam /* setup statistics block */ 731166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 732164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 733164426Ssam sizeof(struct npestats), 1, sizeof(struct npestats), 0, 734164426Ssam busdma_lock_mutex, &sc->sc_mtx, &sc->sc_stats_tag); 735164426Ssam if (error != 0) { 736164426Ssam device_printf(sc->sc_dev, "unable to create stats tag, " 737164426Ssam "error %u\n", error); 738164426Ssam return error; 739164426Ssam } 740164426Ssam if (bus_dmamem_alloc(sc->sc_stats_tag, (void **)&sc->sc_stats, 741164426Ssam BUS_DMA_NOWAIT, &sc->sc_stats_map) != 0) { 742164426Ssam device_printf(sc->sc_dev, 743164426Ssam "unable to allocate memory for stats block, error %u\n", 744164426Ssam error); 745164426Ssam return error; 746164426Ssam } 747164426Ssam if (bus_dmamap_load(sc->sc_stats_tag, sc->sc_stats_map, 748164426Ssam sc->sc_stats, sizeof(struct npestats), npe_getaddr, sc, 0) != 0) { 749164426Ssam device_printf(sc->sc_dev, 750164426Ssam "unable to load memory for stats block, error %u\n", 751164426Ssam error); 752164426Ssam return error; 753164426Ssam } 754164426Ssam sc->sc_stats_phys = sc->buf_phys; 755164426Ssam 756164426Ssam /* 757164426Ssam * Setup h/w rx/tx queues. There are four q's: 758164426Ssam * rx inbound q of rx'd frames 759164426Ssam * rx_free pool of ixpbuf's for receiving frames 760164426Ssam * tx outbound q of frames to send 761164426Ssam * tx_done q of tx frames that have been processed 762164426Ssam * 763164426Ssam * The NPE handles the actual tx/rx process and the q manager 764164426Ssam * handles the queues. The driver just writes entries to the 765164426Ssam * q manager mailbox's and gets callbacks when there are rx'd 766164426Ssam * frames to process or tx'd frames to reap. These callbacks 767164426Ssam * are controlled by the q configurations; e.g. we get a 768164426Ssam * callback when tx_done has 2 or more frames to process and 769164426Ssam * when the rx q has at least one frame. These setings can 770164426Ssam * changed at the time the q is configured. 771164426Ssam */ 772186352Ssam sc->rx_qid = npeconfig[sc->sc_npeid].rx_qid; 773164426Ssam ixpqmgr_qconfig(sc->rx_qid, npe_rxbuf, 0, 1, 774164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 775186352Ssam sc->rx_freeqid = npeconfig[sc->sc_npeid].rx_freeqid; 776164426Ssam ixpqmgr_qconfig(sc->rx_freeqid, npe_rxbuf, 0, npe_rxbuf/2, 0, NULL, sc); 777186352Ssam /* 778186352Ssam * Setup the NPE to direct all traffic to rx_qid. 779186352Ssam * When QoS is enabled in the firmware there are 780186352Ssam * 8 traffic classes; otherwise just 4. 781186352Ssam */ 782164426Ssam for (i = 0; i < 8; i++) 783164426Ssam npe_setrxqosentry(sc, i, 0, sc->rx_qid); 784164426Ssam 785186352Ssam /* disable firewall mode just in case (should be off) */ 786186352Ssam npe_setfirewallmode(sc, 0); 787186352Ssam 788186352Ssam sc->tx_qid = npeconfig[sc->sc_npeid].tx_qid; 789186352Ssam sc->tx_doneqid = npeconfig[sc->sc_npeid].tx_doneqid; 790164426Ssam ixpqmgr_qconfig(sc->tx_qid, npe_txbuf, 0, npe_txbuf, 0, NULL, sc); 791164426Ssam if (tx_doneqid == -1) { 792164426Ssam ixpqmgr_qconfig(sc->tx_doneqid, npe_txbuf, 0, 2, 793164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 794164426Ssam tx_doneqid = sc->tx_doneqid; 795164426Ssam } 796164426Ssam 797186352Ssam KASSERT(npes[sc->sc_npeid] == NULL, 798186352Ssam ("npe %u already setup", sc->sc_npeid)); 799186352Ssam npes[sc->sc_npeid] = sc; 800177505Ssam 801164426Ssam return 0; 802164426Ssam} 803164426Ssam 804164426Ssamstatic void 805164426Ssamnpe_deactivate(device_t dev) 806164426Ssam{ 807164426Ssam struct npe_softc *sc = device_get_softc(dev); 808164426Ssam 809186352Ssam npes[sc->sc_npeid] = NULL; 810164426Ssam 811164426Ssam /* XXX disable q's */ 812186352Ssam if (sc->sc_npe != NULL) { 813164426Ssam ixpnpe_stop(sc->sc_npe); 814186352Ssam ixpnpe_detach(sc->sc_npe); 815186352Ssam } 816164426Ssam if (sc->sc_stats != NULL) { 817164426Ssam bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 818164426Ssam bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 819164426Ssam sc->sc_stats_map); 820164426Ssam } 821164426Ssam if (sc->sc_stats_tag != NULL) 822164426Ssam bus_dma_tag_destroy(sc->sc_stats_tag); 823164426Ssam npe_dma_destroy(sc, &sc->txdma); 824164426Ssam npe_dma_destroy(sc, &sc->rxdma); 825164426Ssam bus_generic_detach(sc->sc_dev); 826186352Ssam if (sc->sc_mii != NULL) 827164426Ssam device_delete_child(sc->sc_dev, sc->sc_mii); 828164426Ssam} 829164426Ssam 830164426Ssam/* 831164426Ssam * Change media according to request. 832164426Ssam */ 833164426Ssamstatic int 834164426Ssamnpe_ifmedia_update(struct ifnet *ifp) 835164426Ssam{ 836164426Ssam struct npe_softc *sc = ifp->if_softc; 837164426Ssam struct mii_data *mii; 838164426Ssam 839164426Ssam mii = device_get_softc(sc->sc_mii); 840164426Ssam NPE_LOCK(sc); 841164426Ssam mii_mediachg(mii); 842164426Ssam /* XXX push state ourself? */ 843164426Ssam NPE_UNLOCK(sc); 844164426Ssam return (0); 845164426Ssam} 846164426Ssam 847164426Ssam/* 848164426Ssam * Notify the world which media we're using. 849164426Ssam */ 850164426Ssamstatic void 851164426Ssamnpe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 852164426Ssam{ 853164426Ssam struct npe_softc *sc = ifp->if_softc; 854164426Ssam struct mii_data *mii; 855164426Ssam 856164426Ssam mii = device_get_softc(sc->sc_mii); 857164426Ssam NPE_LOCK(sc); 858164426Ssam mii_pollstat(mii); 859164426Ssam ifmr->ifm_active = mii->mii_media_active; 860164426Ssam ifmr->ifm_status = mii->mii_media_status; 861164426Ssam NPE_UNLOCK(sc); 862164426Ssam} 863164426Ssam 864164426Ssamstatic void 865164426Ssamnpe_addstats(struct npe_softc *sc) 866164426Ssam{ 867164426Ssam#define MIBADD(x) sc->mibdata.x += be32toh(ns->x) 868164426Ssam struct ifnet *ifp = sc->sc_ifp; 869164426Ssam struct npestats *ns = sc->sc_stats; 870164426Ssam 871164426Ssam MIBADD(dot3StatsAlignmentErrors); 872164426Ssam MIBADD(dot3StatsFCSErrors); 873164426Ssam MIBADD(dot3StatsSingleCollisionFrames); 874164426Ssam MIBADD(dot3StatsMultipleCollisionFrames); 875164426Ssam MIBADD(dot3StatsDeferredTransmissions); 876164426Ssam MIBADD(dot3StatsLateCollisions); 877164426Ssam MIBADD(dot3StatsExcessiveCollisions); 878164426Ssam MIBADD(dot3StatsInternalMacTransmitErrors); 879164426Ssam MIBADD(dot3StatsCarrierSenseErrors); 880164426Ssam sc->mibdata.dot3StatsFrameTooLongs += 881164426Ssam be32toh(ns->RxLargeFramesDiscards) 882164426Ssam + be32toh(ns->TxLargeFrameDiscards); 883164426Ssam MIBADD(dot3StatsInternalMacReceiveErrors); 884164426Ssam sc->mibdata.dot3StatsMissedFrames += 885164426Ssam be32toh(ns->RxOverrunDiscards) 886164426Ssam + be32toh(ns->RxUnderflowEntryDiscards); 887164426Ssam 888164426Ssam ifp->if_oerrors += 889164426Ssam be32toh(ns->dot3StatsInternalMacTransmitErrors) 890164426Ssam + be32toh(ns->dot3StatsCarrierSenseErrors) 891164426Ssam + be32toh(ns->TxVLANIdFilterDiscards) 892164426Ssam ; 893164426Ssam ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 894164426Ssam + be32toh(ns->dot3StatsInternalMacReceiveErrors) 895164426Ssam + be32toh(ns->RxOverrunDiscards) 896164426Ssam + be32toh(ns->RxUnderflowEntryDiscards) 897164426Ssam ; 898164426Ssam ifp->if_collisions += 899164426Ssam be32toh(ns->dot3StatsSingleCollisionFrames) 900164426Ssam + be32toh(ns->dot3StatsMultipleCollisionFrames) 901164426Ssam ; 902164426Ssam#undef MIBADD 903164426Ssam} 904164426Ssam 905164426Ssamstatic void 906164426Ssamnpe_tick(void *xsc) 907164426Ssam{ 908164426Ssam#define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 909164426Ssam struct npe_softc *sc = xsc; 910164426Ssam struct mii_data *mii = device_get_softc(sc->sc_mii); 911164426Ssam uint32_t msg[2]; 912164426Ssam 913164426Ssam NPE_ASSERT_LOCKED(sc); 914164426Ssam 915164426Ssam /* 916164426Ssam * NB: to avoid sleeping with the softc lock held we 917164426Ssam * split the NPE msg processing into two parts. The 918164426Ssam * request for statistics is sent w/o waiting for a 919164426Ssam * reply and then on the next tick we retrieve the 920164426Ssam * results. This works because npe_tick is the only 921164426Ssam * code that talks via the mailbox's (except at setup). 922164426Ssam * This likely can be handled better. 923164426Ssam */ 924186352Ssam if (ixpnpe_recvmsg_async(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 925164426Ssam bus_dmamap_sync(sc->sc_stats_tag, sc->sc_stats_map, 926164426Ssam BUS_DMASYNC_POSTREAD); 927164426Ssam npe_addstats(sc); 928164426Ssam } 929164426Ssam npe_updatestats(sc); 930164426Ssam mii_tick(mii); 931164426Ssam 932166339Skevlo npewatchdog(sc); 933166339Skevlo 934164426Ssam /* schedule next poll */ 935164426Ssam callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 936164426Ssam#undef ACK 937164426Ssam} 938164426Ssam 939164426Ssamstatic void 940164426Ssamnpe_setmac(struct npe_softc *sc, u_char *eaddr) 941164426Ssam{ 942164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 943164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 944164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 945164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 946164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 947164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 948164426Ssam} 949164426Ssam 950164426Ssamstatic void 951164426Ssamnpe_getmac(struct npe_softc *sc, u_char *eaddr) 952164426Ssam{ 953164426Ssam /* NB: the unicast address appears to be loaded from EEPROM on reset */ 954164426Ssam eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 955164426Ssam eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 956164426Ssam eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 957164426Ssam eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 958164426Ssam eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 959164426Ssam eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 960164426Ssam} 961164426Ssam 962164426Ssamstruct txdone { 963164426Ssam struct npebuf *head; 964164426Ssam struct npebuf **tail; 965164426Ssam int count; 966164426Ssam}; 967164426Ssam 968164426Ssamstatic __inline void 969164426Ssamnpe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 970164426Ssam{ 971164426Ssam struct ifnet *ifp = sc->sc_ifp; 972164426Ssam 973164426Ssam NPE_LOCK(sc); 974164426Ssam *td->tail = sc->tx_free; 975164426Ssam sc->tx_free = td->head; 976164426Ssam /* 977164426Ssam * We're no longer busy, so clear the busy flag and call the 978164426Ssam * start routine to xmit more packets. 979164426Ssam */ 980164426Ssam ifp->if_opackets += td->count; 981164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 982166339Skevlo sc->npe_watchdog_timer = 0; 983164426Ssam npestart_locked(ifp); 984164426Ssam NPE_UNLOCK(sc); 985164426Ssam} 986164426Ssam 987164426Ssam/* 988164426Ssam * Q manager callback on tx done queue. Reap mbufs 989164426Ssam * and return tx buffers to the free list. Finally 990164426Ssam * restart output. Note the microcode has only one 991164426Ssam * txdone q wired into it so we must use the NPE ID 992164426Ssam * returned with each npehwbuf to decide where to 993164426Ssam * send buffers. 994164426Ssam */ 995164426Ssamstatic void 996164426Ssamnpe_txdone(int qid, void *arg) 997164426Ssam{ 998164426Ssam#define P2V(a, dma) \ 999164426Ssam &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1000164426Ssam struct npe_softc *sc0 = arg; 1001164426Ssam struct npe_softc *sc; 1002164426Ssam struct npebuf *npe; 1003164426Ssam struct txdone *td, q[NPE_MAX]; 1004164426Ssam uint32_t entry; 1005164426Ssam 1006164426Ssam /* XXX no NPE-A support */ 1007164426Ssam q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 1008164426Ssam q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 1009164426Ssam /* XXX max # at a time? */ 1010164426Ssam while (ixpqmgr_qread(qid, &entry) == 0) { 1011164426Ssam DPRINTF(sc0, "%s: entry 0x%x NPE %u port %u\n", 1012164426Ssam __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 1013164426Ssam 1014164426Ssam sc = npes[NPE_QM_Q_NPE(entry)]; 1015164426Ssam npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 1016164426Ssam m_freem(npe->ix_m); 1017164426Ssam npe->ix_m = NULL; 1018164426Ssam 1019164426Ssam td = &q[NPE_QM_Q_NPE(entry)]; 1020164426Ssam *td->tail = npe; 1021164426Ssam td->tail = &npe->ix_next; 1022164426Ssam td->count++; 1023164426Ssam } 1024164426Ssam 1025164426Ssam if (q[NPE_B].count) 1026164426Ssam npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 1027164426Ssam if (q[NPE_C].count) 1028164426Ssam npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 1029164426Ssam#undef P2V 1030164426Ssam} 1031164426Ssam 1032164426Ssamstatic int 1033164426Ssamnpe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 1034164426Ssam{ 1035164426Ssam bus_dma_segment_t segs[1]; 1036164426Ssam struct npedma *dma = &sc->rxdma; 1037164426Ssam struct npehwbuf *hw; 1038164426Ssam int error, nseg; 1039164426Ssam 1040164426Ssam if (m == NULL) { 1041164426Ssam m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1042164426Ssam if (m == NULL) 1043164426Ssam return ENOBUFS; 1044164426Ssam } 1045164426Ssam KASSERT(m->m_ext.ext_size >= 1536 + ETHER_ALIGN, 1046164426Ssam ("ext_size %d", m->m_ext.ext_size)); 1047164426Ssam m->m_pkthdr.len = m->m_len = 1536; 1048164426Ssam /* backload payload and align ip hdr */ 1049164426Ssam m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN)); 1050164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, m, 1051164426Ssam segs, &nseg, 0); 1052164426Ssam if (error != 0) { 1053164426Ssam m_freem(m); 1054164426Ssam return error; 1055164426Ssam } 1056164426Ssam hw = npe->ix_hw; 1057164426Ssam hw->ix_ne[0].data = htobe32(segs[0].ds_addr); 1058164426Ssam /* NB: NPE requires length be a multiple of 64 */ 1059164426Ssam /* NB: buffer length is shifted in word */ 1060164426Ssam hw->ix_ne[0].len = htobe32(segs[0].ds_len << 16); 1061164426Ssam hw->ix_ne[0].next = 0; 1062164426Ssam npe->ix_m = m; 1063164426Ssam /* Flush the memory in the mbuf */ 1064164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREREAD); 1065164426Ssam return 0; 1066164426Ssam} 1067164426Ssam 1068164426Ssam/* 1069164426Ssam * RX q processing for a specific NPE. Claim entries 1070164426Ssam * from the hardware queue and pass the frames up the 1071164426Ssam * stack. Pass the rx buffers to the free list. 1072164426Ssam */ 1073164426Ssamstatic void 1074164426Ssamnpe_rxdone(int qid, void *arg) 1075164426Ssam{ 1076164426Ssam#define P2V(a, dma) \ 1077164426Ssam &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1078164426Ssam struct npe_softc *sc = arg; 1079164426Ssam struct npedma *dma = &sc->rxdma; 1080164426Ssam uint32_t entry; 1081164426Ssam 1082164426Ssam while (ixpqmgr_qread(qid, &entry) == 0) { 1083164426Ssam struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 1084164426Ssam struct mbuf *m; 1085164426Ssam 1086164426Ssam DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 1087164426Ssam __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 1088164426Ssam /* 1089164426Ssam * Allocate a new mbuf to replenish the rx buffer. 1090164426Ssam * If doing so fails we drop the rx'd frame so we 1091164426Ssam * can reuse the previous mbuf. When we're able to 1092164426Ssam * allocate a new mbuf dispatch the mbuf w/ rx'd 1093164426Ssam * data up the stack and replace it with the newly 1094164426Ssam * allocated one. 1095164426Ssam */ 1096164426Ssam m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1097164426Ssam if (m != NULL) { 1098164426Ssam struct mbuf *mrx = npe->ix_m; 1099164426Ssam struct npehwbuf *hw = npe->ix_hw; 1100164426Ssam struct ifnet *ifp = sc->sc_ifp; 1101164426Ssam 1102164426Ssam /* Flush mbuf memory for rx'd data */ 1103164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, 1104164426Ssam BUS_DMASYNC_POSTREAD); 1105164426Ssam 1106164426Ssam /* XXX flush hw buffer; works now 'cuz coherent */ 1107164426Ssam /* set m_len etc. per rx frame size */ 1108164426Ssam mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 1109164426Ssam mrx->m_pkthdr.len = mrx->m_len; 1110164426Ssam mrx->m_pkthdr.rcvif = ifp; 1111164426Ssam mrx->m_flags |= M_HASFCS; 1112164426Ssam 1113164426Ssam ifp->if_ipackets++; 1114164426Ssam ifp->if_input(ifp, mrx); 1115164426Ssam } else { 1116164426Ssam /* discard frame and re-use mbuf */ 1117164426Ssam m = npe->ix_m; 1118164426Ssam } 1119164426Ssam if (npe_rxbuf_init(sc, npe, m) == 0) { 1120164426Ssam /* return npe buf to rx free list */ 1121164426Ssam ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1122164426Ssam } else { 1123164426Ssam /* XXX should not happen */ 1124164426Ssam } 1125164426Ssam } 1126164426Ssam#undef P2V 1127164426Ssam} 1128164426Ssam 1129164426Ssam#ifdef DEVICE_POLLING 1130164426Ssamstatic void 1131164426Ssamnpe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1132164426Ssam{ 1133164426Ssam struct npe_softc *sc = ifp->if_softc; 1134164426Ssam 1135164426Ssam if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1136164426Ssam npe_rxdone(sc->rx_qid, sc); 1137164426Ssam npe_txdone(sc->tx_doneqid, sc); /* XXX polls both NPE's */ 1138164426Ssam } 1139164426Ssam} 1140164426Ssam#endif /* DEVICE_POLLING */ 1141164426Ssam 1142164426Ssamstatic void 1143164426Ssamnpe_startxmit(struct npe_softc *sc) 1144164426Ssam{ 1145164426Ssam struct npedma *dma = &sc->txdma; 1146164426Ssam int i; 1147164426Ssam 1148164426Ssam NPE_ASSERT_LOCKED(sc); 1149164426Ssam sc->tx_free = NULL; 1150164426Ssam for (i = 0; i < dma->nbuf; i++) { 1151164426Ssam struct npebuf *npe = &dma->buf[i]; 1152164426Ssam if (npe->ix_m != NULL) { 1153164426Ssam /* NB: should not happen */ 1154164426Ssam device_printf(sc->sc_dev, 1155164426Ssam "%s: free mbuf at entry %u\n", __func__, i); 1156164426Ssam m_freem(npe->ix_m); 1157164426Ssam } 1158164426Ssam npe->ix_m = NULL; 1159164426Ssam npe->ix_next = sc->tx_free; 1160164426Ssam sc->tx_free = npe; 1161164426Ssam } 1162164426Ssam} 1163164426Ssam 1164164426Ssamstatic void 1165164426Ssamnpe_startrecv(struct npe_softc *sc) 1166164426Ssam{ 1167164426Ssam struct npedma *dma = &sc->rxdma; 1168164426Ssam struct npebuf *npe; 1169164426Ssam int i; 1170164426Ssam 1171164426Ssam NPE_ASSERT_LOCKED(sc); 1172164426Ssam for (i = 0; i < dma->nbuf; i++) { 1173164426Ssam npe = &dma->buf[i]; 1174164426Ssam npe_rxbuf_init(sc, npe, npe->ix_m); 1175164426Ssam /* set npe buf on rx free list */ 1176164426Ssam ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1177164426Ssam } 1178164426Ssam} 1179164426Ssam 1180164426Ssam/* 1181164426Ssam * Reset and initialize the chip 1182164426Ssam */ 1183164426Ssamstatic void 1184164426Ssamnpeinit_locked(void *xsc) 1185164426Ssam{ 1186164426Ssam struct npe_softc *sc = xsc; 1187164426Ssam struct ifnet *ifp = sc->sc_ifp; 1188164426Ssam 1189164426Ssam NPE_ASSERT_LOCKED(sc); 1190164426Ssamif (ifp->if_drv_flags & IFF_DRV_RUNNING) return;/*XXX*/ 1191164426Ssam 1192164426Ssam /* 1193164426Ssam * Reset MAC core. 1194164426Ssam */ 1195186352Ssam npe_mac_reset(sc); 1196164426Ssam 1197164426Ssam /* disable transmitter and reciver in the MAC */ 1198164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1199164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1200164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1201164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1202164426Ssam 1203164426Ssam /* 1204164426Ssam * Set the MAC core registers. 1205164426Ssam */ 1206164426Ssam WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1207164426Ssam WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1208164426Ssam WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1209164426Ssam /* thresholds determined by NPE firmware FS */ 1210164426Ssam WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1211164426Ssam WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1212164426Ssam WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */ 1213164426Ssam WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1214164426Ssam WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1215164426Ssam WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1216164426Ssam WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1217164426Ssam WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */ 1218164426Ssam 1219164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1220164426Ssam NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1221164426Ssam | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1222164426Ssam | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1223164426Ssam | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1224164426Ssam /* XXX pad strip? */ 1225164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1226164426Ssam NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1227164426Ssam | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1228164426Ssam WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1229164426Ssam 1230164426Ssam npe_setmac(sc, IF_LLADDR(ifp)); 1231164426Ssam npe_setmcast(sc); 1232164426Ssam 1233164426Ssam npe_startxmit(sc); 1234164426Ssam npe_startrecv(sc); 1235164426Ssam 1236164426Ssam ifp->if_drv_flags |= IFF_DRV_RUNNING; 1237164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1238166339Skevlo sc->npe_watchdog_timer = 0; /* just in case */ 1239164426Ssam 1240164426Ssam /* enable transmitter and reciver in the MAC */ 1241164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1242164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1243164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1244164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1245164426Ssam 1246164426Ssam callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 1247164426Ssam} 1248164426Ssam 1249164426Ssamstatic void 1250164426Ssamnpeinit(void *xsc) 1251164426Ssam{ 1252164426Ssam struct npe_softc *sc = xsc; 1253164426Ssam NPE_LOCK(sc); 1254164426Ssam npeinit_locked(sc); 1255164426Ssam NPE_UNLOCK(sc); 1256164426Ssam} 1257164426Ssam 1258164426Ssam/* 1259164426Ssam * Dequeue packets and place on the h/w transmit queue. 1260164426Ssam */ 1261164426Ssamstatic void 1262164426Ssamnpestart_locked(struct ifnet *ifp) 1263164426Ssam{ 1264164426Ssam struct npe_softc *sc = ifp->if_softc; 1265164426Ssam struct npebuf *npe; 1266164426Ssam struct npehwbuf *hw; 1267164426Ssam struct mbuf *m, *n; 1268164426Ssam struct npedma *dma = &sc->txdma; 1269164426Ssam bus_dma_segment_t segs[NPE_MAXSEG]; 1270164426Ssam int nseg, len, error, i; 1271164426Ssam uint32_t next; 1272164426Ssam 1273164426Ssam NPE_ASSERT_LOCKED(sc); 1274164426Ssam /* XXX can this happen? */ 1275164426Ssam if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1276164426Ssam return; 1277164426Ssam 1278164426Ssam while (sc->tx_free != NULL) { 1279164426Ssam IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1280164426Ssam if (m == NULL) { 1281164426Ssam /* XXX? */ 1282164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1283164426Ssam return; 1284164426Ssam } 1285164426Ssam npe = sc->tx_free; 1286164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1287164426Ssam m, segs, &nseg, 0); 1288164426Ssam if (error == EFBIG) { 1289175418Sjhb n = m_collapse(m, M_DONTWAIT, NPE_MAXSEG); 1290164426Ssam if (n == NULL) { 1291164426Ssam if_printf(ifp, "%s: too many fragments %u\n", 1292164426Ssam __func__, nseg); 1293164426Ssam m_freem(m); 1294164426Ssam return; /* XXX? */ 1295164426Ssam } 1296164426Ssam m = n; 1297164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1298164426Ssam m, segs, &nseg, 0); 1299164426Ssam } 1300164426Ssam if (error != 0 || nseg == 0) { 1301164426Ssam if_printf(ifp, "%s: error %u nseg %u\n", 1302164426Ssam __func__, error, nseg); 1303164426Ssam m_freem(m); 1304164426Ssam return; /* XXX? */ 1305164426Ssam } 1306164426Ssam sc->tx_free = npe->ix_next; 1307164426Ssam 1308164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREWRITE); 1309164426Ssam 1310164426Ssam /* 1311164426Ssam * Tap off here if there is a bpf listener. 1312164426Ssam */ 1313164426Ssam BPF_MTAP(ifp, m); 1314164426Ssam 1315164426Ssam npe->ix_m = m; 1316164426Ssam hw = npe->ix_hw; 1317164426Ssam len = m->m_pkthdr.len; 1318164426Ssam next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1319164426Ssam for (i = 0; i < nseg; i++) { 1320164426Ssam hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1321164426Ssam hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1322164426Ssam hw->ix_ne[i].next = htobe32(next); 1323164426Ssam 1324164426Ssam len = 0; /* zero for segments > 1 */ 1325164426Ssam next += sizeof(hw->ix_ne[0]); 1326164426Ssam } 1327164426Ssam hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1328164426Ssam /* XXX flush descriptor instead of using uncached memory */ 1329164426Ssam 1330164426Ssam DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1331164426Ssam __func__, sc->tx_qid, npe->ix_neaddr, 1332164426Ssam hw->ix_ne[0].data, hw->ix_ne[0].len); 1333164426Ssam /* stick it on the tx q */ 1334164426Ssam /* XXX add vlan priority */ 1335164426Ssam ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1336164426Ssam 1337166339Skevlo sc->npe_watchdog_timer = 5; 1338164426Ssam } 1339164426Ssam if (sc->tx_free == NULL) 1340164426Ssam ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1341164426Ssam} 1342164426Ssam 1343164426Ssamvoid 1344164426Ssamnpestart(struct ifnet *ifp) 1345164426Ssam{ 1346164426Ssam struct npe_softc *sc = ifp->if_softc; 1347164426Ssam NPE_LOCK(sc); 1348164426Ssam npestart_locked(ifp); 1349164426Ssam NPE_UNLOCK(sc); 1350164426Ssam} 1351164426Ssam 1352164426Ssamstatic void 1353164426Ssamnpe_stopxmit(struct npe_softc *sc) 1354164426Ssam{ 1355164426Ssam struct npedma *dma = &sc->txdma; 1356164426Ssam int i; 1357164426Ssam 1358164426Ssam NPE_ASSERT_LOCKED(sc); 1359164426Ssam 1360164426Ssam /* XXX qmgr */ 1361164426Ssam for (i = 0; i < dma->nbuf; i++) { 1362164426Ssam struct npebuf *npe = &dma->buf[i]; 1363164426Ssam 1364164426Ssam if (npe->ix_m != NULL) { 1365164426Ssam bus_dmamap_unload(dma->mtag, npe->ix_map); 1366164426Ssam m_freem(npe->ix_m); 1367164426Ssam npe->ix_m = NULL; 1368164426Ssam } 1369164426Ssam } 1370164426Ssam} 1371164426Ssam 1372164426Ssamstatic void 1373164426Ssamnpe_stoprecv(struct npe_softc *sc) 1374164426Ssam{ 1375164426Ssam struct npedma *dma = &sc->rxdma; 1376164426Ssam int i; 1377164426Ssam 1378164426Ssam NPE_ASSERT_LOCKED(sc); 1379164426Ssam 1380164426Ssam /* XXX qmgr */ 1381164426Ssam for (i = 0; i < dma->nbuf; i++) { 1382164426Ssam struct npebuf *npe = &dma->buf[i]; 1383164426Ssam 1384164426Ssam if (npe->ix_m != NULL) { 1385164426Ssam bus_dmamap_unload(dma->mtag, npe->ix_map); 1386164426Ssam m_freem(npe->ix_m); 1387164426Ssam npe->ix_m = NULL; 1388164426Ssam } 1389164426Ssam } 1390164426Ssam} 1391164426Ssam 1392164426Ssam/* 1393164426Ssam * Turn off interrupts, and stop the nic. 1394164426Ssam */ 1395164426Ssamvoid 1396164426Ssamnpestop(struct npe_softc *sc) 1397164426Ssam{ 1398164426Ssam struct ifnet *ifp = sc->sc_ifp; 1399164426Ssam 1400164426Ssam /* disable transmitter and reciver in the MAC */ 1401164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1402164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1403164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1404164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1405164426Ssam 1406166339Skevlo sc->npe_watchdog_timer = 0; 1407164426Ssam ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1408164426Ssam 1409164426Ssam callout_stop(&sc->tick_ch); 1410164426Ssam 1411164426Ssam npe_stopxmit(sc); 1412164426Ssam npe_stoprecv(sc); 1413164426Ssam /* XXX go into loopback & drain q's? */ 1414164426Ssam /* XXX but beware of disabling tx above */ 1415164426Ssam 1416164426Ssam /* 1417164426Ssam * The MAC core rx/tx disable may leave the MAC hardware in an 1418164426Ssam * unpredictable state. A hw reset is executed before resetting 1419164426Ssam * all the MAC parameters to a known value. 1420164426Ssam */ 1421164426Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1422164426Ssam DELAY(NPE_MAC_RESET_DELAY); 1423164426Ssam WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1424164426Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1425164426Ssam} 1426164426Ssam 1427164426Ssamvoid 1428166339Skevlonpewatchdog(struct npe_softc *sc) 1429164426Ssam{ 1430166339Skevlo NPE_ASSERT_LOCKED(sc); 1431164426Ssam 1432166339Skevlo if (sc->npe_watchdog_timer == 0 || --sc->npe_watchdog_timer != 0) 1433166339Skevlo return; 1434166339Skevlo 1435166339Skevlo device_printf(sc->sc_dev, "watchdog timeout\n"); 1436166339Skevlo sc->sc_ifp->if_oerrors++; 1437166339Skevlo 1438164426Ssam npeinit_locked(sc); 1439164426Ssam} 1440164426Ssam 1441164426Ssamstatic int 1442164426Ssamnpeioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1443164426Ssam{ 1444164426Ssam struct npe_softc *sc = ifp->if_softc; 1445164426Ssam struct mii_data *mii; 1446164426Ssam struct ifreq *ifr = (struct ifreq *)data; 1447164426Ssam int error = 0; 1448164426Ssam#ifdef DEVICE_POLLING 1449164426Ssam int mask; 1450164426Ssam#endif 1451164426Ssam 1452164426Ssam switch (cmd) { 1453164426Ssam case SIOCSIFFLAGS: 1454164426Ssam NPE_LOCK(sc); 1455164426Ssam if ((ifp->if_flags & IFF_UP) == 0 && 1456164426Ssam ifp->if_drv_flags & IFF_DRV_RUNNING) { 1457164426Ssam ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1458164426Ssam npestop(sc); 1459164426Ssam } else { 1460164426Ssam /* reinitialize card on any parameter change */ 1461164426Ssam npeinit_locked(sc); 1462164426Ssam } 1463164426Ssam NPE_UNLOCK(sc); 1464164426Ssam break; 1465164426Ssam 1466164426Ssam case SIOCADDMULTI: 1467164426Ssam case SIOCDELMULTI: 1468164426Ssam /* update multicast filter list. */ 1469164426Ssam NPE_LOCK(sc); 1470164426Ssam npe_setmcast(sc); 1471164426Ssam NPE_UNLOCK(sc); 1472164426Ssam error = 0; 1473164426Ssam break; 1474164426Ssam 1475164426Ssam case SIOCSIFMEDIA: 1476164426Ssam case SIOCGIFMEDIA: 1477164426Ssam mii = device_get_softc(sc->sc_mii); 1478164426Ssam error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1479164426Ssam break; 1480164426Ssam 1481164426Ssam#ifdef DEVICE_POLLING 1482164426Ssam case SIOCSIFCAP: 1483164426Ssam mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1484164426Ssam if (mask & IFCAP_POLLING) { 1485164426Ssam if (ifr->ifr_reqcap & IFCAP_POLLING) { 1486164426Ssam error = ether_poll_register(npe_poll, ifp); 1487164426Ssam if (error) 1488164426Ssam return error; 1489164426Ssam NPE_LOCK(sc); 1490164426Ssam /* disable callbacks XXX txdone is shared */ 1491164426Ssam ixpqmgr_notify_disable(sc->rx_qid); 1492164426Ssam ixpqmgr_notify_disable(sc->tx_doneqid); 1493164426Ssam ifp->if_capenable |= IFCAP_POLLING; 1494164426Ssam NPE_UNLOCK(sc); 1495164426Ssam } else { 1496164426Ssam error = ether_poll_deregister(ifp); 1497164426Ssam /* NB: always enable qmgr callbacks */ 1498164426Ssam NPE_LOCK(sc); 1499164426Ssam /* enable qmgr callbacks */ 1500164426Ssam ixpqmgr_notify_enable(sc->rx_qid, 1501164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E); 1502164426Ssam ixpqmgr_notify_enable(sc->tx_doneqid, 1503164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E); 1504164426Ssam ifp->if_capenable &= ~IFCAP_POLLING; 1505164426Ssam NPE_UNLOCK(sc); 1506164426Ssam } 1507164426Ssam } 1508164426Ssam break; 1509164426Ssam#endif 1510164426Ssam default: 1511164426Ssam error = ether_ioctl(ifp, cmd, data); 1512164426Ssam break; 1513164426Ssam } 1514164426Ssam return error; 1515164426Ssam} 1516164426Ssam 1517164426Ssam/* 1518164426Ssam * Setup a traffic class -> rx queue mapping. 1519164426Ssam */ 1520164426Ssamstatic int 1521164426Ssamnpe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1522164426Ssam{ 1523164426Ssam uint32_t msg[2]; 1524164426Ssam 1525186352Ssam msg[0] = (NPE_SETRXQOSENTRY << 24) | (sc->sc_npeid << 20) | classix; 1526164426Ssam msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1527186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1528164426Ssam} 1529164426Ssam 1530186352Ssamstatic int 1531186352Ssamnpe_setfirewallmode(struct npe_softc *sc, int onoff) 1532186352Ssam{ 1533186352Ssam uint32_t msg[2]; 1534186352Ssam 1535186352Ssam /* XXX honor onoff */ 1536186352Ssam msg[0] = (NPE_SETFIREWALLMODE << 24) | (sc->sc_npeid << 20); 1537186352Ssam msg[1] = 0; 1538186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1539186352Ssam} 1540186352Ssam 1541164426Ssam/* 1542164426Ssam * Update and reset the statistics in the NPE. 1543164426Ssam */ 1544164426Ssamstatic int 1545164426Ssamnpe_updatestats(struct npe_softc *sc) 1546164426Ssam{ 1547164426Ssam uint32_t msg[2]; 1548164426Ssam 1549164426Ssam msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1550164426Ssam msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1551186352Ssam return ixpnpe_sendmsg_async(sc->sc_npe, msg); 1552164426Ssam} 1553164426Ssam 1554164426Ssam#if 0 1555164426Ssam/* 1556164426Ssam * Get the current statistics block. 1557164426Ssam */ 1558164426Ssamstatic int 1559164426Ssamnpe_getstats(struct npe_softc *sc) 1560164426Ssam{ 1561164426Ssam uint32_t msg[2]; 1562164426Ssam 1563164426Ssam msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1564164426Ssam msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1565164426Ssam return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1566164426Ssam} 1567164426Ssam 1568164426Ssam/* 1569164426Ssam * Query the image id of the loaded firmware. 1570164426Ssam */ 1571164426Ssamstatic uint32_t 1572164426Ssamnpe_getimageid(struct npe_softc *sc) 1573164426Ssam{ 1574164426Ssam uint32_t msg[2]; 1575164426Ssam 1576164426Ssam msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1577164426Ssam msg[1] = 0; 1578186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1579164426Ssam} 1580164426Ssam 1581164426Ssam/* 1582164426Ssam * Enable/disable loopback. 1583164426Ssam */ 1584164426Ssamstatic int 1585164426Ssamnpe_setloopback(struct npe_softc *sc, int ena) 1586164426Ssam{ 1587164426Ssam uint32_t msg[2]; 1588164426Ssam 1589164426Ssam msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1590164426Ssam msg[1] = 0; 1591186352Ssam return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1592164426Ssam} 1593164426Ssam#endif 1594164426Ssam 1595164426Ssamstatic void 1596164426Ssamnpe_child_detached(device_t dev, device_t child) 1597164426Ssam{ 1598164426Ssam struct npe_softc *sc; 1599164426Ssam 1600164426Ssam sc = device_get_softc(dev); 1601164426Ssam if (child == sc->sc_mii) 1602164426Ssam sc->sc_mii = NULL; 1603164426Ssam} 1604164426Ssam 1605164426Ssam/* 1606164426Ssam * MII bus support routines. 1607164426Ssam */ 1608186352Ssam#define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1609186352Ssam#define MII_WR4(sc, reg, v) \ 1610186352Ssam bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1611186352Ssam 1612164426Ssamstatic uint32_t 1613164426Ssamnpe_mii_mdio_read(struct npe_softc *sc, int reg) 1614164426Ssam{ 1615164426Ssam uint32_t v; 1616164426Ssam 1617164426Ssam /* NB: registers are known to be sequential */ 1618164426Ssam v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1619164426Ssam v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1620164426Ssam v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1621164426Ssam v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1622164426Ssam return v; 1623164426Ssam} 1624164426Ssam 1625164426Ssamstatic void 1626164426Ssamnpe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1627164426Ssam{ 1628164426Ssam /* NB: registers are known to be sequential */ 1629164426Ssam MII_WR4(sc, reg+0, cmd & 0xff); 1630164426Ssam MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1631164426Ssam MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1632164426Ssam MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1633164426Ssam} 1634164426Ssam 1635164426Ssamstatic int 1636164426Ssamnpe_mii_mdio_wait(struct npe_softc *sc) 1637164426Ssam{ 1638164426Ssam uint32_t v; 1639164426Ssam int i; 1640164426Ssam 1641186352Ssam /* NB: typically this takes 25-30 trips */ 1642186352Ssam for (i = 0; i < 1000; i++) { 1643164426Ssam v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1644164426Ssam if ((v & NPE_MII_GO) == 0) 1645164426Ssam return 1; 1646186352Ssam DELAY(1); 1647164426Ssam } 1648186352Ssam device_printf(sc->sc_dev, "%s: timeout after ~1ms, cmd 0x%x\n", 1649186352Ssam __func__, v); 1650164426Ssam return 0; /* NB: timeout */ 1651164426Ssam} 1652164426Ssam 1653164426Ssamstatic int 1654164426Ssamnpe_miibus_readreg(device_t dev, int phy, int reg) 1655164426Ssam{ 1656164426Ssam struct npe_softc *sc = device_get_softc(dev); 1657164426Ssam uint32_t v; 1658164426Ssam 1659177505Ssam if (phy != sc->sc_phy) /* XXX no auto-detect */ 1660164426Ssam return 0xffff; 1661186352Ssam v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) | NPE_MII_GO; 1662164426Ssam npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1663164426Ssam if (npe_mii_mdio_wait(sc)) 1664164426Ssam v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1665164426Ssam else 1666164426Ssam v = 0xffff | NPE_MII_READ_FAIL; 1667164426Ssam return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1668164426Ssam} 1669164426Ssam 1670164426Ssamstatic void 1671164426Ssamnpe_miibus_writereg(device_t dev, int phy, int reg, int data) 1672164426Ssam{ 1673164426Ssam struct npe_softc *sc = device_get_softc(dev); 1674164426Ssam uint32_t v; 1675164426Ssam 1676177505Ssam if (phy != sc->sc_phy) /* XXX */ 1677164426Ssam return; 1678164426Ssam v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1679164426Ssam | data | NPE_MII_WRITE 1680164426Ssam | NPE_MII_GO; 1681164426Ssam npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1682164426Ssam /* XXX complain about timeout */ 1683164426Ssam (void) npe_mii_mdio_wait(sc); 1684164426Ssam} 1685164426Ssam 1686164426Ssamstatic void 1687164426Ssamnpe_miibus_statchg(device_t dev) 1688164426Ssam{ 1689164426Ssam struct npe_softc *sc = device_get_softc(dev); 1690164426Ssam struct mii_data *mii = device_get_softc(sc->sc_mii); 1691164426Ssam uint32_t tx1, rx1; 1692164426Ssam 1693164426Ssam /* sync MAC duplex state */ 1694164426Ssam tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1695164426Ssam rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1696164426Ssam if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1697164426Ssam tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1698164426Ssam rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1699164426Ssam } else { 1700164426Ssam tx1 |= NPE_TX_CNTRL1_DUPLEX; 1701164426Ssam rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1702164426Ssam } 1703164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1704164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1705164426Ssam} 1706164426Ssam 1707164426Ssamstatic device_method_t npe_methods[] = { 1708164426Ssam /* Device interface */ 1709164426Ssam DEVMETHOD(device_probe, npe_probe), 1710164426Ssam DEVMETHOD(device_attach, npe_attach), 1711164426Ssam DEVMETHOD(device_detach, npe_detach), 1712164426Ssam 1713164426Ssam /* Bus interface */ 1714164426Ssam DEVMETHOD(bus_child_detached, npe_child_detached), 1715164426Ssam 1716164426Ssam /* MII interface */ 1717164426Ssam DEVMETHOD(miibus_readreg, npe_miibus_readreg), 1718164426Ssam DEVMETHOD(miibus_writereg, npe_miibus_writereg), 1719164426Ssam DEVMETHOD(miibus_statchg, npe_miibus_statchg), 1720164426Ssam 1721164426Ssam { 0, 0 } 1722164426Ssam}; 1723164426Ssam 1724164426Ssamstatic driver_t npe_driver = { 1725164426Ssam "npe", 1726164426Ssam npe_methods, 1727164426Ssam sizeof(struct npe_softc), 1728164426Ssam}; 1729164426Ssam 1730164426SsamDRIVER_MODULE(npe, ixp, npe_driver, npe_devclass, 0, 0); 1731164426SsamDRIVER_MODULE(miibus, npe, miibus_driver, miibus_devclass, 0, 0); 1732164426SsamMODULE_DEPEND(npe, ixpqmgr, 1, 1, 1); 1733164426SsamMODULE_DEPEND(npe, miibus, 1, 1, 1); 1734164426SsamMODULE_DEPEND(npe, ether, 1, 1, 1); 1735