if_npe.c revision 183886
1164426Ssam/*- 2177505Ssam * Copyright (c) 2006-2008 Sam Leffler. All rights reserved. 3164426Ssam * 4164426Ssam * Redistribution and use in source and binary forms, with or without 5164426Ssam * modification, are permitted provided that the following conditions 6164426Ssam * are met: 7164426Ssam * 1. Redistributions of source code must retain the above copyright 8164426Ssam * notice, this list of conditions and the following disclaimer. 9164426Ssam * 2. Redistributions in binary form must reproduce the above copyright 10164426Ssam * notice, this list of conditions and the following disclaimer in the 11164426Ssam * documentation and/or other materials provided with the distribution. 12164426Ssam * 13164426Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14164426Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15164426Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16164426Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17164426Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18164426Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19164426Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20164426Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21164426Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22164426Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23164426Ssam */ 24164426Ssam 25164426Ssam#include <sys/cdefs.h> 26164426Ssam__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/if_npe.c 183886 2008-10-14 16:27:52Z sam $"); 27164426Ssam 28164426Ssam/* 29164426Ssam * Intel XScale NPE Ethernet driver. 30164426Ssam * 31164426Ssam * This driver handles the two ports present on the IXP425. 32164426Ssam * Packet processing is done by the Network Processing Engines 33164426Ssam * (NPE's) that work together with a MAC and PHY. The MAC 34164426Ssam * is also mapped to the XScale cpu; the PHY is accessed via 35164426Ssam * the MAC. NPE-XScale communication happens through h/w 36164426Ssam * queues managed by the Q Manager block. 37164426Ssam * 38164426Ssam * The code here replaces the ethAcc, ethMii, and ethDB classes 39164426Ssam * in the Intel Access Library (IAL) and the OS-specific driver. 40164426Ssam * 41164426Ssam * XXX add vlan support 42164426Ssam */ 43164426Ssam#ifdef HAVE_KERNEL_OPTION_HEADERS 44164426Ssam#include "opt_device_polling.h" 45164426Ssam#endif 46164426Ssam 47164426Ssam#include <sys/param.h> 48164426Ssam#include <sys/systm.h> 49164426Ssam#include <sys/bus.h> 50164426Ssam#include <sys/kernel.h> 51164426Ssam#include <sys/mbuf.h> 52164426Ssam#include <sys/malloc.h> 53164426Ssam#include <sys/module.h> 54164426Ssam#include <sys/rman.h> 55164426Ssam#include <sys/socket.h> 56164426Ssam#include <sys/sockio.h> 57164426Ssam#include <sys/sysctl.h> 58164426Ssam#include <sys/endian.h> 59164426Ssam#include <machine/bus.h> 60164426Ssam 61164426Ssam#include <net/ethernet.h> 62164426Ssam#include <net/if.h> 63164426Ssam#include <net/if_arp.h> 64164426Ssam#include <net/if_dl.h> 65164426Ssam#include <net/if_media.h> 66164426Ssam#include <net/if_mib.h> 67164426Ssam#include <net/if_types.h> 68164426Ssam 69164426Ssam#ifdef INET 70164426Ssam#include <netinet/in.h> 71164426Ssam#include <netinet/in_systm.h> 72164426Ssam#include <netinet/in_var.h> 73164426Ssam#include <netinet/ip.h> 74164426Ssam#endif 75164426Ssam 76164426Ssam#include <net/bpf.h> 77164426Ssam#include <net/bpfdesc.h> 78164426Ssam 79164426Ssam#include <arm/xscale/ixp425/ixp425reg.h> 80164426Ssam#include <arm/xscale/ixp425/ixp425var.h> 81164426Ssam#include <arm/xscale/ixp425/ixp425_qmgr.h> 82164426Ssam#include <arm/xscale/ixp425/ixp425_npevar.h> 83164426Ssam 84164426Ssam#include <dev/mii/mii.h> 85164426Ssam#include <dev/mii/miivar.h> 86164426Ssam#include <arm/xscale/ixp425/if_npereg.h> 87164426Ssam 88164426Ssam#include "miibus_if.h" 89164426Ssam 90166064Scognet/* 91166064Scognet * XXX: For the main bus dma tag. Can go away if the new method to get the 92166064Scognet * dma tag from the parent got MFC'd into RELENG_6. 93166064Scognet */ 94166064Scognetextern struct ixp425_softc *ixp425_softc; 95166064Scognet 96164426Ssamstruct npebuf { 97164426Ssam struct npebuf *ix_next; /* chain to next buffer */ 98164426Ssam void *ix_m; /* backpointer to mbuf */ 99164426Ssam bus_dmamap_t ix_map; /* bus dma map for associated data */ 100164426Ssam struct npehwbuf *ix_hw; /* associated h/w block */ 101164426Ssam uint32_t ix_neaddr; /* phys address of ix_hw */ 102164426Ssam}; 103164426Ssam 104164426Ssamstruct npedma { 105164426Ssam const char* name; 106164426Ssam int nbuf; /* # npebuf's allocated */ 107164426Ssam bus_dma_tag_t mtag; /* bus dma tag for mbuf data */ 108164426Ssam struct npehwbuf *hwbuf; /* NPE h/w buffers */ 109164426Ssam bus_dma_tag_t buf_tag; /* tag+map for NPE buffers */ 110164426Ssam bus_dmamap_t buf_map; 111164426Ssam bus_addr_t buf_phys; /* phys addr of buffers */ 112164426Ssam struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 113164426Ssam}; 114164426Ssam 115164426Ssamstruct npe_softc { 116164426Ssam /* XXX mii requires this be first; do not move! */ 117164426Ssam struct ifnet *sc_ifp; /* ifnet pointer */ 118164426Ssam struct mtx sc_mtx; /* basically a perimeter lock */ 119164426Ssam device_t sc_dev; 120164426Ssam bus_space_tag_t sc_iot; 121164426Ssam bus_space_handle_t sc_ioh; /* MAC register window */ 122164426Ssam device_t sc_mii; /* child miibus */ 123164426Ssam bus_space_handle_t sc_miih; /* MII register window */ 124164426Ssam struct ixpnpe_softc *sc_npe; /* NPE support */ 125164426Ssam int sc_debug; /* DPRINTF* control */ 126164426Ssam int sc_tickinterval; 127164426Ssam struct callout tick_ch; /* Tick callout */ 128166339Skevlo int npe_watchdog_timer; 129164426Ssam struct npedma txdma; 130164426Ssam struct npebuf *tx_free; /* list of free tx buffers */ 131164426Ssam struct npedma rxdma; 132164426Ssam bus_addr_t buf_phys; /* XXX for returning a value */ 133164426Ssam int rx_qid; /* rx qid */ 134164426Ssam int rx_freeqid; /* rx free buffers qid */ 135164426Ssam int tx_qid; /* tx qid */ 136164426Ssam int tx_doneqid; /* tx completed qid */ 137177505Ssam int sc_phy; /* PHY id */ 138164426Ssam struct ifmib_iso_8802_3 mibdata; 139164426Ssam bus_dma_tag_t sc_stats_tag; /* bus dma tag for stats block */ 140164426Ssam struct npestats *sc_stats; 141164426Ssam bus_dmamap_t sc_stats_map; 142164426Ssam bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 143164426Ssam}; 144164426Ssam 145164426Ssam/* 146164426Ssam * Per-unit static configuration for IXP425. The tx and 147164426Ssam * rx free Q id's are fixed by the NPE microcode. The 148164426Ssam * rx Q id's are programmed to be separate to simplify 149164426Ssam * multi-port processing. It may be better to handle 150164426Ssam * all traffic through one Q (as done by the Intel drivers). 151164426Ssam * 152164426Ssam * Note that the PHY's are accessible only from MAC A 153164426Ssam * on the IXP425. This and other platform-specific 154164426Ssam * assumptions probably need to be handled through hints. 155164426Ssam */ 156164426Ssamstatic const struct { 157164426Ssam const char *desc; /* device description */ 158164426Ssam int npeid; /* NPE assignment */ 159164426Ssam uint32_t imageid; /* NPE firmware image id */ 160164426Ssam uint32_t regbase; 161164426Ssam int regsize; 162164426Ssam uint32_t miibase; 163164426Ssam int miisize; 164177505Ssam int phy; /* phy id */ 165164426Ssam uint8_t rx_qid; 166164426Ssam uint8_t rx_freeqid; 167164426Ssam uint8_t tx_qid; 168164426Ssam uint8_t tx_doneqid; 169164426Ssam} npeconfig[NPE_PORTS_MAX] = { 170164426Ssam { .desc = "IXP NPE-B", 171164426Ssam .npeid = NPE_B, 172164426Ssam .imageid = IXP425_NPE_B_IMAGEID, 173164426Ssam .regbase = IXP425_MAC_A_HWBASE, 174164426Ssam .regsize = IXP425_MAC_A_SIZE, 175164426Ssam .miibase = IXP425_MAC_A_HWBASE, 176164426Ssam .miisize = IXP425_MAC_A_SIZE, 177177505Ssam .phy = 0, 178164426Ssam .rx_qid = 4, 179164426Ssam .rx_freeqid = 27, 180164426Ssam .tx_qid = 24, 181164426Ssam .tx_doneqid = 31 182164426Ssam }, 183164426Ssam { .desc = "IXP NPE-C", 184164426Ssam .npeid = NPE_C, 185164426Ssam .imageid = IXP425_NPE_C_IMAGEID, 186164426Ssam .regbase = IXP425_MAC_B_HWBASE, 187164426Ssam .regsize = IXP425_MAC_B_SIZE, 188164426Ssam .miibase = IXP425_MAC_A_HWBASE, 189164426Ssam .miisize = IXP425_MAC_A_SIZE, 190177505Ssam .phy = 1, 191164426Ssam .rx_qid = 12, 192164426Ssam .rx_freeqid = 28, 193164426Ssam .tx_qid = 25, 194164426Ssam .tx_doneqid = 31 195164426Ssam }, 196164426Ssam}; 197164426Ssamstatic struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 198164426Ssam 199164426Ssamstatic __inline uint32_t 200164426SsamRD4(struct npe_softc *sc, bus_size_t off) 201164426Ssam{ 202164426Ssam return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 203164426Ssam} 204164426Ssam 205164426Ssamstatic __inline void 206164426SsamWR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 207164426Ssam{ 208164426Ssam bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 209164426Ssam} 210164426Ssam 211164426Ssam#define NPE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 212164426Ssam#define NPE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 213164426Ssam#define NPE_LOCK_INIT(_sc) \ 214164426Ssam mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 215164426Ssam MTX_NETWORK_LOCK, MTX_DEF) 216164426Ssam#define NPE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 217164426Ssam#define NPE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 218164426Ssam#define NPE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 219164426Ssam 220164426Ssamstatic devclass_t npe_devclass; 221164426Ssam 222164426Ssamstatic int npe_activate(device_t dev); 223164426Ssamstatic void npe_deactivate(device_t dev); 224164426Ssamstatic int npe_ifmedia_update(struct ifnet *ifp); 225164426Ssamstatic void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 226164426Ssamstatic void npe_setmac(struct npe_softc *sc, u_char *eaddr); 227164426Ssamstatic void npe_getmac(struct npe_softc *sc, u_char *eaddr); 228164426Ssamstatic void npe_txdone(int qid, void *arg); 229164426Ssamstatic int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 230164426Ssam struct mbuf *); 231164426Ssamstatic void npe_rxdone(int qid, void *arg); 232164426Ssamstatic void npeinit(void *); 233164426Ssamstatic void npestart_locked(struct ifnet *); 234164426Ssamstatic void npestart(struct ifnet *); 235164426Ssamstatic void npestop(struct npe_softc *); 236166339Skevlostatic void npewatchdog(struct npe_softc *); 237164426Ssamstatic int npeioctl(struct ifnet * ifp, u_long, caddr_t); 238164426Ssam 239164426Ssamstatic int npe_setrxqosentry(struct npe_softc *, int classix, 240164426Ssam int trafclass, int qid); 241164426Ssamstatic int npe_updatestats(struct npe_softc *); 242164426Ssam#if 0 243164426Ssamstatic int npe_getstats(struct npe_softc *); 244164426Ssamstatic uint32_t npe_getimageid(struct npe_softc *); 245164426Ssamstatic int npe_setloopback(struct npe_softc *, int ena); 246164426Ssam#endif 247164426Ssam 248164426Ssam/* NB: all tx done processing goes through one queue */ 249164426Ssamstatic int tx_doneqid = -1; 250164426Ssam 251164426SsamSYSCTL_NODE(_hw, OID_AUTO, npe, CTLFLAG_RD, 0, "IXP425 NPE driver parameters"); 252164426Ssam 253164426Ssamstatic int npe_debug = 0; 254164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, debug, CTLFLAG_RW, &npe_debug, 255164426Ssam 0, "IXP425 NPE network interface debug msgs"); 256164426SsamTUNABLE_INT("hw.npe.npe", &npe_debug); 257164426Ssam#define DPRINTF(sc, fmt, ...) do { \ 258164426Ssam if (sc->sc_debug) device_printf(sc->sc_dev, fmt, __VA_ARGS__); \ 259164426Ssam} while (0) 260164426Ssam#define DPRINTFn(n, sc, fmt, ...) do { \ 261164426Ssam if (sc->sc_debug >= n) device_printf(sc->sc_dev, fmt, __VA_ARGS__);\ 262164426Ssam} while (0) 263164426Ssamstatic int npe_tickinterval = 3; /* npe_tick frequency (secs) */ 264164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, tickinterval, CTLFLAG_RD, &npe_tickinterval, 265164426Ssam 0, "periodic work interval (secs)"); 266164426SsamTUNABLE_INT("hw.npe.tickinterval", &npe_tickinterval); 267164426Ssam 268164426Ssamstatic int npe_rxbuf = 64; /* # rx buffers to allocate */ 269164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, rxbuf, CTLFLAG_RD, &npe_rxbuf, 270164426Ssam 0, "rx buffers allocated"); 271164426SsamTUNABLE_INT("hw.npe.rxbuf", &npe_rxbuf); 272164426Ssamstatic int npe_txbuf = 128; /* # tx buffers to allocate */ 273164426SsamSYSCTL_INT(_hw_npe, OID_AUTO, txbuf, CTLFLAG_RD, &npe_txbuf, 274164426Ssam 0, "tx buffers allocated"); 275164426SsamTUNABLE_INT("hw.npe.txbuf", &npe_txbuf); 276164426Ssam 277164426Ssamstatic int 278164426Ssamnpe_probe(device_t dev) 279164426Ssam{ 280164426Ssam int unit = device_get_unit(dev); 281164426Ssam 282164426Ssam if (unit >= NPE_PORTS_MAX) { 283164426Ssam device_printf(dev, "unit %d not supported\n", unit); 284164426Ssam return EINVAL; 285164426Ssam } 286164426Ssam /* XXX check feature register to see if enabled */ 287164426Ssam device_set_desc(dev, npeconfig[unit].desc); 288164426Ssam return 0; 289164426Ssam} 290164426Ssam 291164426Ssamstatic int 292164426Ssamnpe_attach(device_t dev) 293164426Ssam{ 294164426Ssam struct npe_softc *sc = device_get_softc(dev); 295164426Ssam struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); 296164426Ssam struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 297164426Ssam struct sysctl_oid *tree = device_get_sysctl_tree(dev); 298164426Ssam struct ifnet *ifp = NULL; 299164426Ssam int error; 300164426Ssam u_char eaddr[6]; 301164426Ssam 302164426Ssam sc->sc_dev = dev; 303164426Ssam sc->sc_iot = sa->sc_iot; 304164426Ssam NPE_LOCK_INIT(sc); 305164426Ssam callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 306164426Ssam sc->sc_debug = npe_debug; 307164426Ssam sc->sc_tickinterval = npe_tickinterval; 308164426Ssam 309164426Ssam sc->sc_npe = ixpnpe_attach(dev); 310164426Ssam if (sc->sc_npe == NULL) { 311164426Ssam error = EIO; /* XXX */ 312164426Ssam goto out; 313164426Ssam } 314164426Ssam 315164426Ssam error = npe_activate(dev); 316164426Ssam if (error) 317164426Ssam goto out; 318164426Ssam 319164426Ssam npe_getmac(sc, eaddr); 320164426Ssam 321164426Ssam /* NB: must be setup prior to invoking mii code */ 322164426Ssam sc->sc_ifp = ifp = if_alloc(IFT_ETHER); 323164426Ssam if (mii_phy_probe(dev, &sc->sc_mii, npe_ifmedia_update, npe_ifmedia_status)) { 324164426Ssam device_printf(dev, "Cannot find my PHY.\n"); 325164426Ssam error = ENXIO; 326164426Ssam goto out; 327164426Ssam } 328164426Ssam 329164426Ssam ifp->if_softc = sc; 330164426Ssam if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 331164426Ssam ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 332164426Ssam ifp->if_start = npestart; 333164426Ssam ifp->if_ioctl = npeioctl; 334164426Ssam ifp->if_init = npeinit; 335164426Ssam IFQ_SET_MAXLEN(&ifp->if_snd, sc->txdma.nbuf - 1); 336166625Smlaier ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 337164426Ssam IFQ_SET_READY(&ifp->if_snd); 338164426Ssam ifp->if_linkmib = &sc->mibdata; 339164426Ssam ifp->if_linkmiblen = sizeof(sc->mibdata); 340164426Ssam sc->mibdata.dot3Compliance = DOT3COMPLIANCE_STATS; 341164426Ssam#ifdef DEVICE_POLLING 342164426Ssam ifp->if_capabilities |= IFCAP_POLLING; 343164426Ssam#endif 344164426Ssam 345164426Ssam SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug", 346164426Ssam CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 347164426Ssam SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tickinterval", 348164426Ssam CTLFLAG_RW, &sc->sc_tickinterval, 0, "periodic work frequency"); 349164426Ssam 350164426Ssam ether_ifattach(ifp, eaddr); 351164426Ssam return 0; 352164426Ssamout: 353164426Ssam npe_deactivate(dev); 354164426Ssam if (ifp != NULL) 355164426Ssam if_free(ifp); 356164426Ssam return error; 357164426Ssam} 358164426Ssam 359164426Ssamstatic int 360164426Ssamnpe_detach(device_t dev) 361164426Ssam{ 362164426Ssam struct npe_softc *sc = device_get_softc(dev); 363164426Ssam struct ifnet *ifp = sc->sc_ifp; 364164426Ssam 365164426Ssam#ifdef DEVICE_POLLING 366164426Ssam if (ifp->if_capenable & IFCAP_POLLING) 367164426Ssam ether_poll_deregister(ifp); 368164426Ssam#endif 369164426Ssam npestop(sc); 370164426Ssam if (ifp != NULL) { 371164426Ssam ether_ifdetach(ifp); 372164426Ssam if_free(ifp); 373164426Ssam } 374164426Ssam NPE_LOCK_DESTROY(sc); 375164426Ssam npe_deactivate(dev); 376164426Ssam if (sc->sc_npe != NULL) 377164426Ssam ixpnpe_detach(sc->sc_npe); 378164426Ssam return 0; 379164426Ssam} 380164426Ssam 381164426Ssam/* 382164426Ssam * Compute and install the multicast filter. 383164426Ssam */ 384164426Ssamstatic void 385164426Ssamnpe_setmcast(struct npe_softc *sc) 386164426Ssam{ 387164426Ssam struct ifnet *ifp = sc->sc_ifp; 388164426Ssam uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 389164426Ssam int i; 390164426Ssam 391164426Ssam if (ifp->if_flags & IFF_PROMISC) { 392164426Ssam memset(mask, 0, ETHER_ADDR_LEN); 393164426Ssam memset(addr, 0, ETHER_ADDR_LEN); 394164426Ssam } else if (ifp->if_flags & IFF_ALLMULTI) { 395164426Ssam static const uint8_t allmulti[ETHER_ADDR_LEN] = 396164426Ssam { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 397164426Ssam memcpy(mask, allmulti, ETHER_ADDR_LEN); 398164426Ssam memcpy(addr, allmulti, ETHER_ADDR_LEN); 399164426Ssam } else { 400164426Ssam uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 401164426Ssam struct ifmultiaddr *ifma; 402164426Ssam const uint8_t *mac; 403164426Ssam 404164426Ssam memset(clr, 0, ETHER_ADDR_LEN); 405164426Ssam memset(set, 0xff, ETHER_ADDR_LEN); 406164426Ssam 407164426Ssam IF_ADDR_LOCK(ifp); 408164426Ssam TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 409164426Ssam if (ifma->ifma_addr->sa_family != AF_LINK) 410164426Ssam continue; 411164426Ssam mac = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 412164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 413164426Ssam clr[i] |= mac[i]; 414164426Ssam set[i] &= mac[i]; 415164426Ssam } 416164426Ssam } 417164426Ssam IF_ADDR_UNLOCK(ifp); 418164426Ssam 419164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 420164426Ssam mask[i] = set[i] | ~clr[i]; 421164426Ssam addr[i] = set[i]; 422164426Ssam } 423164426Ssam } 424164426Ssam 425164426Ssam /* 426164426Ssam * Write the mask and address registers. 427164426Ssam */ 428164426Ssam for (i = 0; i < ETHER_ADDR_LEN; i++) { 429164426Ssam WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 430164426Ssam WR4(sc, NPE_MAC_ADDR(i), addr[i]); 431164426Ssam } 432164426Ssam} 433164426Ssam 434164426Ssamstatic void 435164426Ssamnpe_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 436164426Ssam{ 437164426Ssam struct npe_softc *sc; 438164426Ssam 439164426Ssam if (error != 0) 440164426Ssam return; 441164426Ssam sc = (struct npe_softc *)arg; 442164426Ssam sc->buf_phys = segs[0].ds_addr; 443164426Ssam} 444164426Ssam 445164426Ssamstatic int 446164426Ssamnpe_dma_setup(struct npe_softc *sc, struct npedma *dma, 447164426Ssam const char *name, int nbuf, int maxseg) 448164426Ssam{ 449164426Ssam int error, i; 450164426Ssam 451183886Ssam memset(dma, 0, sizeof(*dma)); 452164426Ssam 453164426Ssam dma->name = name; 454164426Ssam dma->nbuf = nbuf; 455164426Ssam 456164426Ssam /* DMA tag for mapped mbufs */ 457166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, 1, 0, 458164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 459164426Ssam MCLBYTES, maxseg, MCLBYTES, 0, 460164426Ssam busdma_lock_mutex, &sc->sc_mtx, &dma->mtag); 461164426Ssam if (error != 0) { 462164426Ssam device_printf(sc->sc_dev, "unable to create %s mbuf dma tag, " 463164426Ssam "error %u\n", dma->name, error); 464164426Ssam return error; 465164426Ssam } 466164426Ssam 467164426Ssam /* DMA tag and map for the NPE buffers */ 468166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 469164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 470164426Ssam nbuf * sizeof(struct npehwbuf), 1, 471164426Ssam nbuf * sizeof(struct npehwbuf), 0, 472164426Ssam busdma_lock_mutex, &sc->sc_mtx, &dma->buf_tag); 473164426Ssam if (error != 0) { 474164426Ssam device_printf(sc->sc_dev, 475164426Ssam "unable to create %s npebuf dma tag, error %u\n", 476164426Ssam dma->name, error); 477164426Ssam return error; 478164426Ssam } 479164426Ssam /* XXX COHERENT for now */ 480164426Ssam if (bus_dmamem_alloc(dma->buf_tag, (void **)&dma->hwbuf, 481164426Ssam BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 482164426Ssam &dma->buf_map) != 0) { 483164426Ssam device_printf(sc->sc_dev, 484164426Ssam "unable to allocate memory for %s h/w buffers, error %u\n", 485164426Ssam dma->name, error); 486164426Ssam return error; 487164426Ssam } 488164426Ssam /* XXX M_TEMP */ 489164426Ssam dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 490164426Ssam if (dma->buf == NULL) { 491164426Ssam device_printf(sc->sc_dev, 492164426Ssam "unable to allocate memory for %s s/w buffers\n", 493164426Ssam dma->name); 494164426Ssam return error; 495164426Ssam } 496164426Ssam if (bus_dmamap_load(dma->buf_tag, dma->buf_map, 497164426Ssam dma->hwbuf, nbuf*sizeof(struct npehwbuf), npe_getaddr, sc, 0) != 0) { 498164426Ssam device_printf(sc->sc_dev, 499164426Ssam "unable to map memory for %s h/w buffers, error %u\n", 500164426Ssam dma->name, error); 501164426Ssam return error; 502164426Ssam } 503164426Ssam dma->buf_phys = sc->buf_phys; 504164426Ssam for (i = 0; i < dma->nbuf; i++) { 505164426Ssam struct npebuf *npe = &dma->buf[i]; 506164426Ssam struct npehwbuf *hw = &dma->hwbuf[i]; 507164426Ssam 508164426Ssam /* calculate offset to shared area */ 509164426Ssam npe->ix_neaddr = dma->buf_phys + 510164426Ssam ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 511164426Ssam KASSERT((npe->ix_neaddr & 0x1f) == 0, 512164426Ssam ("ixpbuf misaligned, PA 0x%x", npe->ix_neaddr)); 513164426Ssam error = bus_dmamap_create(dma->mtag, BUS_DMA_NOWAIT, 514164426Ssam &npe->ix_map); 515164426Ssam if (error != 0) { 516164426Ssam device_printf(sc->sc_dev, 517164426Ssam "unable to create dmamap for %s buffer %u, " 518164426Ssam "error %u\n", dma->name, i, error); 519164426Ssam return error; 520164426Ssam } 521164426Ssam npe->ix_hw = hw; 522164426Ssam } 523164426Ssam bus_dmamap_sync(dma->buf_tag, dma->buf_map, BUS_DMASYNC_PREWRITE); 524164426Ssam return 0; 525164426Ssam} 526164426Ssam 527164426Ssamstatic void 528164426Ssamnpe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 529164426Ssam{ 530164426Ssam int i; 531164426Ssam 532164426Ssam if (dma->hwbuf != NULL) { 533164426Ssam for (i = 0; i < dma->nbuf; i++) { 534164426Ssam struct npebuf *npe = &dma->buf[i]; 535164426Ssam bus_dmamap_destroy(dma->mtag, npe->ix_map); 536164426Ssam } 537164426Ssam bus_dmamap_unload(dma->buf_tag, dma->buf_map); 538164426Ssam bus_dmamem_free(dma->buf_tag, dma->hwbuf, dma->buf_map); 539164426Ssam bus_dmamap_destroy(dma->buf_tag, dma->buf_map); 540164426Ssam } 541164426Ssam if (dma->buf != NULL) 542164426Ssam free(dma->buf, M_TEMP); 543164426Ssam if (dma->buf_tag) 544164426Ssam bus_dma_tag_destroy(dma->buf_tag); 545164426Ssam if (dma->mtag) 546164426Ssam bus_dma_tag_destroy(dma->mtag); 547164426Ssam memset(dma, 0, sizeof(*dma)); 548164426Ssam} 549164426Ssam 550164426Ssamstatic int 551177505Ssamoverride_addr(device_t dev, const char *resname, int *base, int *size) 552177505Ssam{ 553177505Ssam int unit = device_get_unit(dev); 554177505Ssam const char *resval; 555177505Ssam 556177505Ssam /* XXX warn for wrong hint type */ 557177505Ssam if (resource_string_value("npe", unit, resname, &resval) != 0) 558177505Ssam return 0; 559177505Ssam switch (resval[0]) { 560177505Ssam case 'A': 561177505Ssam *base = IXP425_MAC_A_HWBASE; 562177505Ssam *size = IXP425_MAC_A_SIZE; 563177505Ssam break; 564177505Ssam case 'B': 565177505Ssam *base = IXP425_MAC_B_HWBASE; 566177505Ssam *size = IXP425_MAC_B_SIZE; 567177505Ssam break; 568177505Ssam default: 569177505Ssam device_printf(dev, "Warning, bad value %s for " 570177505Ssam "npe.%d.%s ignored\n", resval, unit, resname); 571177505Ssam return 0; 572177505Ssam } 573177505Ssam if (bootverbose) 574177505Ssam device_printf(dev, "using npe.%d.%s=%s override\n", 575177505Ssam unit, resname, resval); 576177505Ssam return 1; 577177505Ssam} 578177505Ssam 579177505Ssamstatic int 580177505Ssamoverride_unit(device_t dev, const char *resname, int *val, int min, int max) 581177505Ssam{ 582177505Ssam int unit = device_get_unit(dev); 583177505Ssam int resval; 584177505Ssam 585177505Ssam if (resource_int_value("npe", unit, resname, &resval) != 0) 586177505Ssam return 0; 587177505Ssam if (!(min <= resval && resval <= max)) { 588177505Ssam device_printf(dev, "Warning, bad value %d for npe.%d.%s " 589177505Ssam "ignored (value must be [%d-%d])\n", resval, unit, 590177505Ssam resname, min, max); 591177505Ssam return 0; 592177505Ssam } 593177505Ssam if (bootverbose) 594177505Ssam device_printf(dev, "using npe.%d.%s=%d override\n", 595177505Ssam unit, resname, resval); 596177505Ssam *val = resval; 597177505Ssam return 1; 598177505Ssam} 599177505Ssam 600177505Ssamstatic int 601164426Ssamnpe_activate(device_t dev) 602164426Ssam{ 603164426Ssam struct npe_softc * sc = device_get_softc(dev); 604164426Ssam int unit = device_get_unit(dev); 605177505Ssam int error, i, regbase, regsize, miibase, miisize; 606169954Ssam uint32_t imageid; 607164426Ssam 608169954Ssam /* 609169954Ssam * Load NPE firmware and start it running. We assume 610169954Ssam * that minor version bumps remain compatible so probe 611169954Ssam * the firmware image starting with the expected version 612169954Ssam * and then bump the minor version up to the max. 613169954Ssam */ 614169954Ssam imageid = npeconfig[unit].imageid; 615169954Ssam for (;;) { 616169954Ssam error = ixpnpe_init(sc->sc_npe, "npe_fw", imageid); 617169954Ssam if (error == 0) 618169954Ssam break; 619169954Ssam /* ESRCH is returned when the requested image is not present */ 620169954Ssam if (error != ESRCH) 621169954Ssam return error; 622169954Ssam /* bump the minor version up to the max possible */ 623169954Ssam if (NPEIMAGE_MINOR(imageid) == 0xff) 624169954Ssam return error; 625169954Ssam imageid++; 626169954Ssam } 627164426Ssam 628177505Ssam if (!override_addr(dev, "mac", ®base, ®size)) { 629177505Ssam regbase = npeconfig[unit].regbase; 630177505Ssam regbase = npeconfig[unit].regsize; 631177505Ssam } 632177505Ssam if (bus_space_map(sc->sc_iot, regbase, regsize, 0, &sc->sc_ioh)) { 633164426Ssam device_printf(dev, "Cannot map registers 0x%x:0x%x\n", 634177505Ssam regbase, regsize); 635164426Ssam return ENOMEM; 636164426Ssam } 637164426Ssam 638177505Ssam if (!override_addr(dev, "mii", &miibase, &miisize)) { 639177505Ssam miibase = npeconfig[unit].miibase; 640177505Ssam miisize = npeconfig[unit].miisize; 641177505Ssam } 642177505Ssam if (miibase != regbase) { 643164426Ssam /* 644177505Ssam * PHY is mapped through a different MAC, setup an 645177505Ssam * additional mapping for frobbing the PHY registers. 646164426Ssam */ 647177505Ssam if (bus_space_map(sc->sc_iot, miibase, miisize, 0, &sc->sc_miih)) { 648164426Ssam device_printf(dev, 649164426Ssam "Cannot map MII registers 0x%x:0x%x\n", 650177505Ssam miibase, miisize); 651164426Ssam return ENOMEM; 652164426Ssam } 653164426Ssam } else 654164426Ssam sc->sc_miih = sc->sc_ioh; 655164426Ssam error = npe_dma_setup(sc, &sc->txdma, "tx", npe_txbuf, NPE_MAXSEG); 656164426Ssam if (error != 0) 657164426Ssam return error; 658164426Ssam error = npe_dma_setup(sc, &sc->rxdma, "rx", npe_rxbuf, 1); 659164426Ssam if (error != 0) 660164426Ssam return error; 661164426Ssam 662164426Ssam /* setup statistics block */ 663166064Scognet error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 664164426Ssam BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 665164426Ssam sizeof(struct npestats), 1, sizeof(struct npestats), 0, 666164426Ssam busdma_lock_mutex, &sc->sc_mtx, &sc->sc_stats_tag); 667164426Ssam if (error != 0) { 668164426Ssam device_printf(sc->sc_dev, "unable to create stats tag, " 669164426Ssam "error %u\n", error); 670164426Ssam return error; 671164426Ssam } 672164426Ssam if (bus_dmamem_alloc(sc->sc_stats_tag, (void **)&sc->sc_stats, 673164426Ssam BUS_DMA_NOWAIT, &sc->sc_stats_map) != 0) { 674164426Ssam device_printf(sc->sc_dev, 675164426Ssam "unable to allocate memory for stats block, error %u\n", 676164426Ssam error); 677164426Ssam return error; 678164426Ssam } 679164426Ssam if (bus_dmamap_load(sc->sc_stats_tag, sc->sc_stats_map, 680164426Ssam sc->sc_stats, sizeof(struct npestats), npe_getaddr, sc, 0) != 0) { 681164426Ssam device_printf(sc->sc_dev, 682164426Ssam "unable to load memory for stats block, error %u\n", 683164426Ssam error); 684164426Ssam return error; 685164426Ssam } 686164426Ssam sc->sc_stats_phys = sc->buf_phys; 687164426Ssam 688164426Ssam /* XXX disable half-bridge LEARNING+FILTERING feature */ 689164426Ssam 690164426Ssam /* 691164426Ssam * Setup h/w rx/tx queues. There are four q's: 692164426Ssam * rx inbound q of rx'd frames 693164426Ssam * rx_free pool of ixpbuf's for receiving frames 694164426Ssam * tx outbound q of frames to send 695164426Ssam * tx_done q of tx frames that have been processed 696164426Ssam * 697164426Ssam * The NPE handles the actual tx/rx process and the q manager 698164426Ssam * handles the queues. The driver just writes entries to the 699164426Ssam * q manager mailbox's and gets callbacks when there are rx'd 700164426Ssam * frames to process or tx'd frames to reap. These callbacks 701164426Ssam * are controlled by the q configurations; e.g. we get a 702164426Ssam * callback when tx_done has 2 or more frames to process and 703164426Ssam * when the rx q has at least one frame. These setings can 704164426Ssam * changed at the time the q is configured. 705164426Ssam */ 706164426Ssam sc->rx_qid = npeconfig[unit].rx_qid; 707164426Ssam ixpqmgr_qconfig(sc->rx_qid, npe_rxbuf, 0, 1, 708164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 709164426Ssam sc->rx_freeqid = npeconfig[unit].rx_freeqid; 710164426Ssam ixpqmgr_qconfig(sc->rx_freeqid, npe_rxbuf, 0, npe_rxbuf/2, 0, NULL, sc); 711164426Ssam /* tell the NPE to direct all traffic to rx_qid */ 712164426Ssam#if 0 713164426Ssam for (i = 0; i < 8; i++) 714164426Ssam#else 715164426Ssamdevice_printf(sc->sc_dev, "remember to fix rx q setup\n"); 716164426Ssam for (i = 0; i < 4; i++) 717164426Ssam#endif 718164426Ssam npe_setrxqosentry(sc, i, 0, sc->rx_qid); 719164426Ssam 720164426Ssam sc->tx_qid = npeconfig[unit].tx_qid; 721164426Ssam sc->tx_doneqid = npeconfig[unit].tx_doneqid; 722164426Ssam ixpqmgr_qconfig(sc->tx_qid, npe_txbuf, 0, npe_txbuf, 0, NULL, sc); 723164426Ssam if (tx_doneqid == -1) { 724164426Ssam ixpqmgr_qconfig(sc->tx_doneqid, npe_txbuf, 0, 2, 725164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 726164426Ssam tx_doneqid = sc->tx_doneqid; 727164426Ssam } 728164426Ssam 729177505Ssam /* 730177505Ssam * Setup phy port number. We allow override via hints 731177505Ssam * to handle different board configs. 732177505Ssam */ 733177505Ssam if (!override_unit(dev, "phy", &sc->sc_phy, 0, MII_NPHY-1)) 734177505Ssam sc->sc_phy = npeconfig[unit].phy; 735177505Ssam 736164426Ssam KASSERT(npes[npeconfig[unit].npeid] == NULL, 737164426Ssam ("npe %u already setup", npeconfig[unit].npeid)); 738164426Ssam npes[npeconfig[unit].npeid] = sc; 739164426Ssam 740164426Ssam return 0; 741164426Ssam} 742164426Ssam 743164426Ssamstatic void 744164426Ssamnpe_deactivate(device_t dev) 745164426Ssam{ 746164426Ssam struct npe_softc *sc = device_get_softc(dev); 747164426Ssam int unit = device_get_unit(dev); 748164426Ssam 749164426Ssam npes[npeconfig[unit].npeid] = NULL; 750164426Ssam 751164426Ssam /* XXX disable q's */ 752164426Ssam if (sc->sc_npe != NULL) 753164426Ssam ixpnpe_stop(sc->sc_npe); 754164426Ssam if (sc->sc_stats != NULL) { 755164426Ssam bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 756164426Ssam bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 757164426Ssam sc->sc_stats_map); 758164426Ssam bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map); 759164426Ssam } 760164426Ssam if (sc->sc_stats_tag != NULL) 761164426Ssam bus_dma_tag_destroy(sc->sc_stats_tag); 762164426Ssam npe_dma_destroy(sc, &sc->txdma); 763164426Ssam npe_dma_destroy(sc, &sc->rxdma); 764164426Ssam bus_generic_detach(sc->sc_dev); 765164426Ssam if (sc->sc_mii) 766164426Ssam device_delete_child(sc->sc_dev, sc->sc_mii); 767164426Ssam#if 0 768164426Ssam /* XXX sc_ioh and sc_miih */ 769164426Ssam if (sc->mem_res) 770164426Ssam bus_release_resource(dev, SYS_RES_IOPORT, 771164426Ssam rman_get_rid(sc->mem_res), sc->mem_res); 772164426Ssam sc->mem_res = 0; 773164426Ssam#endif 774164426Ssam} 775164426Ssam 776164426Ssam/* 777164426Ssam * Change media according to request. 778164426Ssam */ 779164426Ssamstatic int 780164426Ssamnpe_ifmedia_update(struct ifnet *ifp) 781164426Ssam{ 782164426Ssam struct npe_softc *sc = ifp->if_softc; 783164426Ssam struct mii_data *mii; 784164426Ssam 785164426Ssam mii = device_get_softc(sc->sc_mii); 786164426Ssam NPE_LOCK(sc); 787164426Ssam mii_mediachg(mii); 788164426Ssam /* XXX push state ourself? */ 789164426Ssam NPE_UNLOCK(sc); 790164426Ssam return (0); 791164426Ssam} 792164426Ssam 793164426Ssam/* 794164426Ssam * Notify the world which media we're using. 795164426Ssam */ 796164426Ssamstatic void 797164426Ssamnpe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 798164426Ssam{ 799164426Ssam struct npe_softc *sc = ifp->if_softc; 800164426Ssam struct mii_data *mii; 801164426Ssam 802164426Ssam mii = device_get_softc(sc->sc_mii); 803164426Ssam NPE_LOCK(sc); 804164426Ssam mii_pollstat(mii); 805164426Ssam ifmr->ifm_active = mii->mii_media_active; 806164426Ssam ifmr->ifm_status = mii->mii_media_status; 807164426Ssam NPE_UNLOCK(sc); 808164426Ssam} 809164426Ssam 810164426Ssamstatic void 811164426Ssamnpe_addstats(struct npe_softc *sc) 812164426Ssam{ 813164426Ssam#define MIBADD(x) sc->mibdata.x += be32toh(ns->x) 814164426Ssam struct ifnet *ifp = sc->sc_ifp; 815164426Ssam struct npestats *ns = sc->sc_stats; 816164426Ssam 817164426Ssam MIBADD(dot3StatsAlignmentErrors); 818164426Ssam MIBADD(dot3StatsFCSErrors); 819164426Ssam MIBADD(dot3StatsSingleCollisionFrames); 820164426Ssam MIBADD(dot3StatsMultipleCollisionFrames); 821164426Ssam MIBADD(dot3StatsDeferredTransmissions); 822164426Ssam MIBADD(dot3StatsLateCollisions); 823164426Ssam MIBADD(dot3StatsExcessiveCollisions); 824164426Ssam MIBADD(dot3StatsInternalMacTransmitErrors); 825164426Ssam MIBADD(dot3StatsCarrierSenseErrors); 826164426Ssam sc->mibdata.dot3StatsFrameTooLongs += 827164426Ssam be32toh(ns->RxLargeFramesDiscards) 828164426Ssam + be32toh(ns->TxLargeFrameDiscards); 829164426Ssam MIBADD(dot3StatsInternalMacReceiveErrors); 830164426Ssam sc->mibdata.dot3StatsMissedFrames += 831164426Ssam be32toh(ns->RxOverrunDiscards) 832164426Ssam + be32toh(ns->RxUnderflowEntryDiscards); 833164426Ssam 834164426Ssam ifp->if_oerrors += 835164426Ssam be32toh(ns->dot3StatsInternalMacTransmitErrors) 836164426Ssam + be32toh(ns->dot3StatsCarrierSenseErrors) 837164426Ssam + be32toh(ns->TxVLANIdFilterDiscards) 838164426Ssam ; 839164426Ssam ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 840164426Ssam + be32toh(ns->dot3StatsInternalMacReceiveErrors) 841164426Ssam + be32toh(ns->RxOverrunDiscards) 842164426Ssam + be32toh(ns->RxUnderflowEntryDiscards) 843164426Ssam ; 844164426Ssam ifp->if_collisions += 845164426Ssam be32toh(ns->dot3StatsSingleCollisionFrames) 846164426Ssam + be32toh(ns->dot3StatsMultipleCollisionFrames) 847164426Ssam ; 848164426Ssam#undef MIBADD 849164426Ssam} 850164426Ssam 851164426Ssamstatic void 852164426Ssamnpe_tick(void *xsc) 853164426Ssam{ 854164426Ssam#define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 855164426Ssam struct npe_softc *sc = xsc; 856164426Ssam struct mii_data *mii = device_get_softc(sc->sc_mii); 857164426Ssam uint32_t msg[2]; 858164426Ssam 859164426Ssam NPE_ASSERT_LOCKED(sc); 860164426Ssam 861164426Ssam /* 862164426Ssam * NB: to avoid sleeping with the softc lock held we 863164426Ssam * split the NPE msg processing into two parts. The 864164426Ssam * request for statistics is sent w/o waiting for a 865164426Ssam * reply and then on the next tick we retrieve the 866164426Ssam * results. This works because npe_tick is the only 867164426Ssam * code that talks via the mailbox's (except at setup). 868164426Ssam * This likely can be handled better. 869164426Ssam */ 870164426Ssam if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 871164426Ssam bus_dmamap_sync(sc->sc_stats_tag, sc->sc_stats_map, 872164426Ssam BUS_DMASYNC_POSTREAD); 873164426Ssam npe_addstats(sc); 874164426Ssam } 875164426Ssam npe_updatestats(sc); 876164426Ssam mii_tick(mii); 877164426Ssam 878166339Skevlo npewatchdog(sc); 879166339Skevlo 880164426Ssam /* schedule next poll */ 881164426Ssam callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 882164426Ssam#undef ACK 883164426Ssam} 884164426Ssam 885164426Ssamstatic void 886164426Ssamnpe_setmac(struct npe_softc *sc, u_char *eaddr) 887164426Ssam{ 888164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 889164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 890164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 891164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 892164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 893164426Ssam WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 894164426Ssam 895164426Ssam} 896164426Ssam 897164426Ssamstatic void 898164426Ssamnpe_getmac(struct npe_softc *sc, u_char *eaddr) 899164426Ssam{ 900164426Ssam /* NB: the unicast address appears to be loaded from EEPROM on reset */ 901164426Ssam eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 902164426Ssam eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 903164426Ssam eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 904164426Ssam eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 905164426Ssam eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 906164426Ssam eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 907164426Ssam} 908164426Ssam 909164426Ssamstruct txdone { 910164426Ssam struct npebuf *head; 911164426Ssam struct npebuf **tail; 912164426Ssam int count; 913164426Ssam}; 914164426Ssam 915164426Ssamstatic __inline void 916164426Ssamnpe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 917164426Ssam{ 918164426Ssam struct ifnet *ifp = sc->sc_ifp; 919164426Ssam 920164426Ssam NPE_LOCK(sc); 921164426Ssam *td->tail = sc->tx_free; 922164426Ssam sc->tx_free = td->head; 923164426Ssam /* 924164426Ssam * We're no longer busy, so clear the busy flag and call the 925164426Ssam * start routine to xmit more packets. 926164426Ssam */ 927164426Ssam ifp->if_opackets += td->count; 928164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 929166339Skevlo sc->npe_watchdog_timer = 0; 930164426Ssam npestart_locked(ifp); 931164426Ssam NPE_UNLOCK(sc); 932164426Ssam} 933164426Ssam 934164426Ssam/* 935164426Ssam * Q manager callback on tx done queue. Reap mbufs 936164426Ssam * and return tx buffers to the free list. Finally 937164426Ssam * restart output. Note the microcode has only one 938164426Ssam * txdone q wired into it so we must use the NPE ID 939164426Ssam * returned with each npehwbuf to decide where to 940164426Ssam * send buffers. 941164426Ssam */ 942164426Ssamstatic void 943164426Ssamnpe_txdone(int qid, void *arg) 944164426Ssam{ 945164426Ssam#define P2V(a, dma) \ 946164426Ssam &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 947164426Ssam struct npe_softc *sc0 = arg; 948164426Ssam struct npe_softc *sc; 949164426Ssam struct npebuf *npe; 950164426Ssam struct txdone *td, q[NPE_MAX]; 951164426Ssam uint32_t entry; 952164426Ssam 953164426Ssam /* XXX no NPE-A support */ 954164426Ssam q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 955164426Ssam q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 956164426Ssam /* XXX max # at a time? */ 957164426Ssam while (ixpqmgr_qread(qid, &entry) == 0) { 958164426Ssam DPRINTF(sc0, "%s: entry 0x%x NPE %u port %u\n", 959164426Ssam __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 960164426Ssam 961164426Ssam sc = npes[NPE_QM_Q_NPE(entry)]; 962164426Ssam npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 963164426Ssam m_freem(npe->ix_m); 964164426Ssam npe->ix_m = NULL; 965164426Ssam 966164426Ssam td = &q[NPE_QM_Q_NPE(entry)]; 967164426Ssam *td->tail = npe; 968164426Ssam td->tail = &npe->ix_next; 969164426Ssam td->count++; 970164426Ssam } 971164426Ssam 972164426Ssam if (q[NPE_B].count) 973164426Ssam npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 974164426Ssam if (q[NPE_C].count) 975164426Ssam npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 976164426Ssam#undef P2V 977164426Ssam} 978164426Ssam 979164426Ssamstatic int 980164426Ssamnpe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 981164426Ssam{ 982164426Ssam bus_dma_segment_t segs[1]; 983164426Ssam struct npedma *dma = &sc->rxdma; 984164426Ssam struct npehwbuf *hw; 985164426Ssam int error, nseg; 986164426Ssam 987164426Ssam if (m == NULL) { 988164426Ssam m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 989164426Ssam if (m == NULL) 990164426Ssam return ENOBUFS; 991164426Ssam } 992164426Ssam KASSERT(m->m_ext.ext_size >= 1536 + ETHER_ALIGN, 993164426Ssam ("ext_size %d", m->m_ext.ext_size)); 994164426Ssam m->m_pkthdr.len = m->m_len = 1536; 995164426Ssam /* backload payload and align ip hdr */ 996164426Ssam m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN)); 997164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, m, 998164426Ssam segs, &nseg, 0); 999164426Ssam if (error != 0) { 1000164426Ssam m_freem(m); 1001164426Ssam return error; 1002164426Ssam } 1003164426Ssam hw = npe->ix_hw; 1004164426Ssam hw->ix_ne[0].data = htobe32(segs[0].ds_addr); 1005164426Ssam /* NB: NPE requires length be a multiple of 64 */ 1006164426Ssam /* NB: buffer length is shifted in word */ 1007164426Ssam hw->ix_ne[0].len = htobe32(segs[0].ds_len << 16); 1008164426Ssam hw->ix_ne[0].next = 0; 1009164426Ssam npe->ix_m = m; 1010164426Ssam /* Flush the memory in the mbuf */ 1011164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREREAD); 1012164426Ssam return 0; 1013164426Ssam} 1014164426Ssam 1015164426Ssam/* 1016164426Ssam * RX q processing for a specific NPE. Claim entries 1017164426Ssam * from the hardware queue and pass the frames up the 1018164426Ssam * stack. Pass the rx buffers to the free list. 1019164426Ssam */ 1020164426Ssamstatic void 1021164426Ssamnpe_rxdone(int qid, void *arg) 1022164426Ssam{ 1023164426Ssam#define P2V(a, dma) \ 1024164426Ssam &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1025164426Ssam struct npe_softc *sc = arg; 1026164426Ssam struct npedma *dma = &sc->rxdma; 1027164426Ssam uint32_t entry; 1028164426Ssam 1029164426Ssam while (ixpqmgr_qread(qid, &entry) == 0) { 1030164426Ssam struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 1031164426Ssam struct mbuf *m; 1032164426Ssam 1033164426Ssam DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 1034164426Ssam __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 1035164426Ssam /* 1036164426Ssam * Allocate a new mbuf to replenish the rx buffer. 1037164426Ssam * If doing so fails we drop the rx'd frame so we 1038164426Ssam * can reuse the previous mbuf. When we're able to 1039164426Ssam * allocate a new mbuf dispatch the mbuf w/ rx'd 1040164426Ssam * data up the stack and replace it with the newly 1041164426Ssam * allocated one. 1042164426Ssam */ 1043164426Ssam m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1044164426Ssam if (m != NULL) { 1045164426Ssam struct mbuf *mrx = npe->ix_m; 1046164426Ssam struct npehwbuf *hw = npe->ix_hw; 1047164426Ssam struct ifnet *ifp = sc->sc_ifp; 1048164426Ssam 1049164426Ssam /* Flush mbuf memory for rx'd data */ 1050164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, 1051164426Ssam BUS_DMASYNC_POSTREAD); 1052164426Ssam 1053164426Ssam /* XXX flush hw buffer; works now 'cuz coherent */ 1054164426Ssam /* set m_len etc. per rx frame size */ 1055164426Ssam mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 1056164426Ssam mrx->m_pkthdr.len = mrx->m_len; 1057164426Ssam mrx->m_pkthdr.rcvif = ifp; 1058164426Ssam mrx->m_flags |= M_HASFCS; 1059164426Ssam 1060164426Ssam ifp->if_ipackets++; 1061164426Ssam ifp->if_input(ifp, mrx); 1062164426Ssam } else { 1063164426Ssam /* discard frame and re-use mbuf */ 1064164426Ssam m = npe->ix_m; 1065164426Ssam } 1066164426Ssam if (npe_rxbuf_init(sc, npe, m) == 0) { 1067164426Ssam /* return npe buf to rx free list */ 1068164426Ssam ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1069164426Ssam } else { 1070164426Ssam /* XXX should not happen */ 1071164426Ssam } 1072164426Ssam } 1073164426Ssam#undef P2V 1074164426Ssam} 1075164426Ssam 1076164426Ssam#ifdef DEVICE_POLLING 1077164426Ssamstatic void 1078164426Ssamnpe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1079164426Ssam{ 1080164426Ssam struct npe_softc *sc = ifp->if_softc; 1081164426Ssam 1082164426Ssam if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1083164426Ssam npe_rxdone(sc->rx_qid, sc); 1084164426Ssam npe_txdone(sc->tx_doneqid, sc); /* XXX polls both NPE's */ 1085164426Ssam } 1086164426Ssam} 1087164426Ssam#endif /* DEVICE_POLLING */ 1088164426Ssam 1089164426Ssamstatic void 1090164426Ssamnpe_startxmit(struct npe_softc *sc) 1091164426Ssam{ 1092164426Ssam struct npedma *dma = &sc->txdma; 1093164426Ssam int i; 1094164426Ssam 1095164426Ssam NPE_ASSERT_LOCKED(sc); 1096164426Ssam sc->tx_free = NULL; 1097164426Ssam for (i = 0; i < dma->nbuf; i++) { 1098164426Ssam struct npebuf *npe = &dma->buf[i]; 1099164426Ssam if (npe->ix_m != NULL) { 1100164426Ssam /* NB: should not happen */ 1101164426Ssam device_printf(sc->sc_dev, 1102164426Ssam "%s: free mbuf at entry %u\n", __func__, i); 1103164426Ssam m_freem(npe->ix_m); 1104164426Ssam } 1105164426Ssam npe->ix_m = NULL; 1106164426Ssam npe->ix_next = sc->tx_free; 1107164426Ssam sc->tx_free = npe; 1108164426Ssam } 1109164426Ssam} 1110164426Ssam 1111164426Ssamstatic void 1112164426Ssamnpe_startrecv(struct npe_softc *sc) 1113164426Ssam{ 1114164426Ssam struct npedma *dma = &sc->rxdma; 1115164426Ssam struct npebuf *npe; 1116164426Ssam int i; 1117164426Ssam 1118164426Ssam NPE_ASSERT_LOCKED(sc); 1119164426Ssam for (i = 0; i < dma->nbuf; i++) { 1120164426Ssam npe = &dma->buf[i]; 1121164426Ssam npe_rxbuf_init(sc, npe, npe->ix_m); 1122164426Ssam /* set npe buf on rx free list */ 1123164426Ssam ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1124164426Ssam } 1125164426Ssam} 1126164426Ssam 1127164426Ssam/* 1128164426Ssam * Reset and initialize the chip 1129164426Ssam */ 1130164426Ssamstatic void 1131164426Ssamnpeinit_locked(void *xsc) 1132164426Ssam{ 1133164426Ssam struct npe_softc *sc = xsc; 1134164426Ssam struct ifnet *ifp = sc->sc_ifp; 1135164426Ssam 1136164426Ssam NPE_ASSERT_LOCKED(sc); 1137164426Ssamif (ifp->if_drv_flags & IFF_DRV_RUNNING) return;/*XXX*/ 1138164426Ssam 1139164426Ssam /* 1140164426Ssam * Reset MAC core. 1141164426Ssam */ 1142164426Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1143164426Ssam DELAY(NPE_MAC_RESET_DELAY); 1144164426Ssam /* configure MAC to generate MDC clock */ 1145164426Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1146164426Ssam 1147164426Ssam /* disable transmitter and reciver in the MAC */ 1148164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1149164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1150164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1151164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1152164426Ssam 1153164426Ssam /* 1154164426Ssam * Set the MAC core registers. 1155164426Ssam */ 1156164426Ssam WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1157164426Ssam WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1158164426Ssam WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1159164426Ssam /* thresholds determined by NPE firmware FS */ 1160164426Ssam WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1161164426Ssam WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1162164426Ssam WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */ 1163164426Ssam WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1164164426Ssam WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1165164426Ssam WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1166164426Ssam WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1167164426Ssam WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */ 1168164426Ssam 1169164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1170164426Ssam NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1171164426Ssam | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1172164426Ssam | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1173164426Ssam | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1174164426Ssam /* XXX pad strip? */ 1175164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1176164426Ssam NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1177164426Ssam | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1178164426Ssam WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1179164426Ssam 1180164426Ssam npe_setmac(sc, IF_LLADDR(ifp)); 1181164426Ssam npe_setmcast(sc); 1182164426Ssam 1183164426Ssam npe_startxmit(sc); 1184164426Ssam npe_startrecv(sc); 1185164426Ssam 1186164426Ssam ifp->if_drv_flags |= IFF_DRV_RUNNING; 1187164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1188166339Skevlo sc->npe_watchdog_timer = 0; /* just in case */ 1189164426Ssam 1190164426Ssam /* enable transmitter and reciver in the MAC */ 1191164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1192164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1193164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1194164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1195164426Ssam 1196164426Ssam callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 1197164426Ssam} 1198164426Ssam 1199164426Ssamstatic void 1200164426Ssamnpeinit(void *xsc) 1201164426Ssam{ 1202164426Ssam struct npe_softc *sc = xsc; 1203164426Ssam NPE_LOCK(sc); 1204164426Ssam npeinit_locked(sc); 1205164426Ssam NPE_UNLOCK(sc); 1206164426Ssam} 1207164426Ssam 1208164426Ssam/* 1209164426Ssam * Dequeue packets and place on the h/w transmit queue. 1210164426Ssam */ 1211164426Ssamstatic void 1212164426Ssamnpestart_locked(struct ifnet *ifp) 1213164426Ssam{ 1214164426Ssam struct npe_softc *sc = ifp->if_softc; 1215164426Ssam struct npebuf *npe; 1216164426Ssam struct npehwbuf *hw; 1217164426Ssam struct mbuf *m, *n; 1218164426Ssam struct npedma *dma = &sc->txdma; 1219164426Ssam bus_dma_segment_t segs[NPE_MAXSEG]; 1220164426Ssam int nseg, len, error, i; 1221164426Ssam uint32_t next; 1222164426Ssam 1223164426Ssam NPE_ASSERT_LOCKED(sc); 1224164426Ssam /* XXX can this happen? */ 1225164426Ssam if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1226164426Ssam return; 1227164426Ssam 1228164426Ssam while (sc->tx_free != NULL) { 1229164426Ssam IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1230164426Ssam if (m == NULL) { 1231164426Ssam /* XXX? */ 1232164426Ssam ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1233164426Ssam return; 1234164426Ssam } 1235164426Ssam npe = sc->tx_free; 1236164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1237164426Ssam m, segs, &nseg, 0); 1238164426Ssam if (error == EFBIG) { 1239175418Sjhb n = m_collapse(m, M_DONTWAIT, NPE_MAXSEG); 1240164426Ssam if (n == NULL) { 1241164426Ssam if_printf(ifp, "%s: too many fragments %u\n", 1242164426Ssam __func__, nseg); 1243164426Ssam m_freem(m); 1244164426Ssam return; /* XXX? */ 1245164426Ssam } 1246164426Ssam m = n; 1247164426Ssam error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1248164426Ssam m, segs, &nseg, 0); 1249164426Ssam } 1250164426Ssam if (error != 0 || nseg == 0) { 1251164426Ssam if_printf(ifp, "%s: error %u nseg %u\n", 1252164426Ssam __func__, error, nseg); 1253164426Ssam m_freem(m); 1254164426Ssam return; /* XXX? */ 1255164426Ssam } 1256164426Ssam sc->tx_free = npe->ix_next; 1257164426Ssam 1258164426Ssam bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREWRITE); 1259164426Ssam 1260164426Ssam /* 1261164426Ssam * Tap off here if there is a bpf listener. 1262164426Ssam */ 1263164426Ssam BPF_MTAP(ifp, m); 1264164426Ssam 1265164426Ssam npe->ix_m = m; 1266164426Ssam hw = npe->ix_hw; 1267164426Ssam len = m->m_pkthdr.len; 1268164426Ssam next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1269164426Ssam for (i = 0; i < nseg; i++) { 1270164426Ssam hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1271164426Ssam hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1272164426Ssam hw->ix_ne[i].next = htobe32(next); 1273164426Ssam 1274164426Ssam len = 0; /* zero for segments > 1 */ 1275164426Ssam next += sizeof(hw->ix_ne[0]); 1276164426Ssam } 1277164426Ssam hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1278164426Ssam /* XXX flush descriptor instead of using uncached memory */ 1279164426Ssam 1280164426Ssam DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1281164426Ssam __func__, sc->tx_qid, npe->ix_neaddr, 1282164426Ssam hw->ix_ne[0].data, hw->ix_ne[0].len); 1283164426Ssam /* stick it on the tx q */ 1284164426Ssam /* XXX add vlan priority */ 1285164426Ssam ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1286164426Ssam 1287166339Skevlo sc->npe_watchdog_timer = 5; 1288164426Ssam } 1289164426Ssam if (sc->tx_free == NULL) 1290164426Ssam ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1291164426Ssam} 1292164426Ssam 1293164426Ssamvoid 1294164426Ssamnpestart(struct ifnet *ifp) 1295164426Ssam{ 1296164426Ssam struct npe_softc *sc = ifp->if_softc; 1297164426Ssam NPE_LOCK(sc); 1298164426Ssam npestart_locked(ifp); 1299164426Ssam NPE_UNLOCK(sc); 1300164426Ssam} 1301164426Ssam 1302164426Ssamstatic void 1303164426Ssamnpe_stopxmit(struct npe_softc *sc) 1304164426Ssam{ 1305164426Ssam struct npedma *dma = &sc->txdma; 1306164426Ssam int i; 1307164426Ssam 1308164426Ssam NPE_ASSERT_LOCKED(sc); 1309164426Ssam 1310164426Ssam /* XXX qmgr */ 1311164426Ssam for (i = 0; i < dma->nbuf; i++) { 1312164426Ssam struct npebuf *npe = &dma->buf[i]; 1313164426Ssam 1314164426Ssam if (npe->ix_m != NULL) { 1315164426Ssam bus_dmamap_unload(dma->mtag, npe->ix_map); 1316164426Ssam m_freem(npe->ix_m); 1317164426Ssam npe->ix_m = NULL; 1318164426Ssam } 1319164426Ssam } 1320164426Ssam} 1321164426Ssam 1322164426Ssamstatic void 1323164426Ssamnpe_stoprecv(struct npe_softc *sc) 1324164426Ssam{ 1325164426Ssam struct npedma *dma = &sc->rxdma; 1326164426Ssam int i; 1327164426Ssam 1328164426Ssam NPE_ASSERT_LOCKED(sc); 1329164426Ssam 1330164426Ssam /* XXX qmgr */ 1331164426Ssam for (i = 0; i < dma->nbuf; i++) { 1332164426Ssam struct npebuf *npe = &dma->buf[i]; 1333164426Ssam 1334164426Ssam if (npe->ix_m != NULL) { 1335164426Ssam bus_dmamap_unload(dma->mtag, npe->ix_map); 1336164426Ssam m_freem(npe->ix_m); 1337164426Ssam npe->ix_m = NULL; 1338164426Ssam } 1339164426Ssam } 1340164426Ssam} 1341164426Ssam 1342164426Ssam/* 1343164426Ssam * Turn off interrupts, and stop the nic. 1344164426Ssam */ 1345164426Ssamvoid 1346164426Ssamnpestop(struct npe_softc *sc) 1347164426Ssam{ 1348164426Ssam struct ifnet *ifp = sc->sc_ifp; 1349164426Ssam 1350164426Ssam /* disable transmitter and reciver in the MAC */ 1351164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, 1352164426Ssam RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1353164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, 1354164426Ssam RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1355164426Ssam 1356166339Skevlo sc->npe_watchdog_timer = 0; 1357164426Ssam ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1358164426Ssam 1359164426Ssam callout_stop(&sc->tick_ch); 1360164426Ssam 1361164426Ssam npe_stopxmit(sc); 1362164426Ssam npe_stoprecv(sc); 1363164426Ssam /* XXX go into loopback & drain q's? */ 1364164426Ssam /* XXX but beware of disabling tx above */ 1365164426Ssam 1366164426Ssam /* 1367164426Ssam * The MAC core rx/tx disable may leave the MAC hardware in an 1368164426Ssam * unpredictable state. A hw reset is executed before resetting 1369164426Ssam * all the MAC parameters to a known value. 1370164426Ssam */ 1371164426Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1372164426Ssam DELAY(NPE_MAC_RESET_DELAY); 1373164426Ssam WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1374164426Ssam WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1375164426Ssam} 1376164426Ssam 1377164426Ssamvoid 1378166339Skevlonpewatchdog(struct npe_softc *sc) 1379164426Ssam{ 1380166339Skevlo NPE_ASSERT_LOCKED(sc); 1381164426Ssam 1382166339Skevlo if (sc->npe_watchdog_timer == 0 || --sc->npe_watchdog_timer != 0) 1383166339Skevlo return; 1384166339Skevlo 1385166339Skevlo device_printf(sc->sc_dev, "watchdog timeout\n"); 1386166339Skevlo sc->sc_ifp->if_oerrors++; 1387166339Skevlo 1388164426Ssam npeinit_locked(sc); 1389164426Ssam} 1390164426Ssam 1391164426Ssamstatic int 1392164426Ssamnpeioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1393164426Ssam{ 1394164426Ssam struct npe_softc *sc = ifp->if_softc; 1395164426Ssam struct mii_data *mii; 1396164426Ssam struct ifreq *ifr = (struct ifreq *)data; 1397164426Ssam int error = 0; 1398164426Ssam#ifdef DEVICE_POLLING 1399164426Ssam int mask; 1400164426Ssam#endif 1401164426Ssam 1402164426Ssam switch (cmd) { 1403164426Ssam case SIOCSIFFLAGS: 1404164426Ssam NPE_LOCK(sc); 1405164426Ssam if ((ifp->if_flags & IFF_UP) == 0 && 1406164426Ssam ifp->if_drv_flags & IFF_DRV_RUNNING) { 1407164426Ssam ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1408164426Ssam npestop(sc); 1409164426Ssam } else { 1410164426Ssam /* reinitialize card on any parameter change */ 1411164426Ssam npeinit_locked(sc); 1412164426Ssam } 1413164426Ssam NPE_UNLOCK(sc); 1414164426Ssam break; 1415164426Ssam 1416164426Ssam case SIOCADDMULTI: 1417164426Ssam case SIOCDELMULTI: 1418164426Ssam /* update multicast filter list. */ 1419164426Ssam NPE_LOCK(sc); 1420164426Ssam npe_setmcast(sc); 1421164426Ssam NPE_UNLOCK(sc); 1422164426Ssam error = 0; 1423164426Ssam break; 1424164426Ssam 1425164426Ssam case SIOCSIFMEDIA: 1426164426Ssam case SIOCGIFMEDIA: 1427164426Ssam mii = device_get_softc(sc->sc_mii); 1428164426Ssam error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1429164426Ssam break; 1430164426Ssam 1431164426Ssam#ifdef DEVICE_POLLING 1432164426Ssam case SIOCSIFCAP: 1433164426Ssam mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1434164426Ssam if (mask & IFCAP_POLLING) { 1435164426Ssam if (ifr->ifr_reqcap & IFCAP_POLLING) { 1436164426Ssam error = ether_poll_register(npe_poll, ifp); 1437164426Ssam if (error) 1438164426Ssam return error; 1439164426Ssam NPE_LOCK(sc); 1440164426Ssam /* disable callbacks XXX txdone is shared */ 1441164426Ssam ixpqmgr_notify_disable(sc->rx_qid); 1442164426Ssam ixpqmgr_notify_disable(sc->tx_doneqid); 1443164426Ssam ifp->if_capenable |= IFCAP_POLLING; 1444164426Ssam NPE_UNLOCK(sc); 1445164426Ssam } else { 1446164426Ssam error = ether_poll_deregister(ifp); 1447164426Ssam /* NB: always enable qmgr callbacks */ 1448164426Ssam NPE_LOCK(sc); 1449164426Ssam /* enable qmgr callbacks */ 1450164426Ssam ixpqmgr_notify_enable(sc->rx_qid, 1451164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E); 1452164426Ssam ixpqmgr_notify_enable(sc->tx_doneqid, 1453164426Ssam IX_QMGR_Q_SOURCE_ID_NOT_E); 1454164426Ssam ifp->if_capenable &= ~IFCAP_POLLING; 1455164426Ssam NPE_UNLOCK(sc); 1456164426Ssam } 1457164426Ssam } 1458164426Ssam break; 1459164426Ssam#endif 1460164426Ssam default: 1461164426Ssam error = ether_ioctl(ifp, cmd, data); 1462164426Ssam break; 1463164426Ssam } 1464164426Ssam return error; 1465164426Ssam} 1466164426Ssam 1467164426Ssam/* 1468164426Ssam * Setup a traffic class -> rx queue mapping. 1469164426Ssam */ 1470164426Ssamstatic int 1471164426Ssamnpe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1472164426Ssam{ 1473164426Ssam int npeid = npeconfig[device_get_unit(sc->sc_dev)].npeid; 1474164426Ssam uint32_t msg[2]; 1475164426Ssam 1476164426Ssam msg[0] = (NPE_SETRXQOSENTRY << 24) | (npeid << 20) | classix; 1477164426Ssam msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1478164426Ssam return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1479164426Ssam} 1480164426Ssam 1481164426Ssam/* 1482164426Ssam * Update and reset the statistics in the NPE. 1483164426Ssam */ 1484164426Ssamstatic int 1485164426Ssamnpe_updatestats(struct npe_softc *sc) 1486164426Ssam{ 1487164426Ssam uint32_t msg[2]; 1488164426Ssam 1489164426Ssam msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1490164426Ssam msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1491164426Ssam return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */ 1492164426Ssam} 1493164426Ssam 1494164426Ssam#if 0 1495164426Ssam/* 1496164426Ssam * Get the current statistics block. 1497164426Ssam */ 1498164426Ssamstatic int 1499164426Ssamnpe_getstats(struct npe_softc *sc) 1500164426Ssam{ 1501164426Ssam uint32_t msg[2]; 1502164426Ssam 1503164426Ssam msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1504164426Ssam msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1505164426Ssam return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1506164426Ssam} 1507164426Ssam 1508164426Ssam/* 1509164426Ssam * Query the image id of the loaded firmware. 1510164426Ssam */ 1511164426Ssamstatic uint32_t 1512164426Ssamnpe_getimageid(struct npe_softc *sc) 1513164426Ssam{ 1514164426Ssam uint32_t msg[2]; 1515164426Ssam 1516164426Ssam msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1517164426Ssam msg[1] = 0; 1518164426Ssam return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1519164426Ssam} 1520164426Ssam 1521164426Ssam/* 1522164426Ssam * Enable/disable loopback. 1523164426Ssam */ 1524164426Ssamstatic int 1525164426Ssamnpe_setloopback(struct npe_softc *sc, int ena) 1526164426Ssam{ 1527164426Ssam uint32_t msg[2]; 1528164426Ssam 1529164426Ssam msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1530164426Ssam msg[1] = 0; 1531164426Ssam return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1532164426Ssam} 1533164426Ssam#endif 1534164426Ssam 1535164426Ssamstatic void 1536164426Ssamnpe_child_detached(device_t dev, device_t child) 1537164426Ssam{ 1538164426Ssam struct npe_softc *sc; 1539164426Ssam 1540164426Ssam sc = device_get_softc(dev); 1541164426Ssam if (child == sc->sc_mii) 1542164426Ssam sc->sc_mii = NULL; 1543164426Ssam} 1544164426Ssam 1545164426Ssam/* 1546164426Ssam * MII bus support routines. 1547164426Ssam */ 1548164426Ssamstatic uint32_t 1549164426Ssamnpe_mii_mdio_read(struct npe_softc *sc, int reg) 1550164426Ssam{ 1551164426Ssam#define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1552164426Ssam uint32_t v; 1553164426Ssam 1554164426Ssam /* NB: registers are known to be sequential */ 1555164426Ssam v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1556164426Ssam v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1557164426Ssam v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1558164426Ssam v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1559164426Ssam return v; 1560164426Ssam#undef MII_RD4 1561164426Ssam} 1562164426Ssam 1563164426Ssamstatic void 1564164426Ssamnpe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1565164426Ssam{ 1566164426Ssam#define MII_WR4(sc, reg, v) \ 1567164426Ssam bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1568164426Ssam 1569164426Ssam /* NB: registers are known to be sequential */ 1570164426Ssam MII_WR4(sc, reg+0, cmd & 0xff); 1571164426Ssam MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1572164426Ssam MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1573164426Ssam MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1574164426Ssam#undef MII_WR4 1575164426Ssam} 1576164426Ssam 1577164426Ssamstatic int 1578164426Ssamnpe_mii_mdio_wait(struct npe_softc *sc) 1579164426Ssam{ 1580164426Ssam#define MAXTRIES 100 /* XXX */ 1581164426Ssam uint32_t v; 1582164426Ssam int i; 1583164426Ssam 1584164426Ssam for (i = 0; i < MAXTRIES; i++) { 1585164426Ssam v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1586164426Ssam if ((v & NPE_MII_GO) == 0) 1587164426Ssam return 1; 1588164426Ssam } 1589164426Ssam return 0; /* NB: timeout */ 1590164426Ssam#undef MAXTRIES 1591164426Ssam} 1592164426Ssam 1593164426Ssamstatic int 1594164426Ssamnpe_miibus_readreg(device_t dev, int phy, int reg) 1595164426Ssam{ 1596164426Ssam struct npe_softc *sc = device_get_softc(dev); 1597164426Ssam uint32_t v; 1598164426Ssam 1599177505Ssam if (phy != sc->sc_phy) /* XXX no auto-detect */ 1600164426Ssam return 0xffff; 1601164426Ssam v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1602164426Ssam | NPE_MII_GO; 1603164426Ssam npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1604164426Ssam if (npe_mii_mdio_wait(sc)) 1605164426Ssam v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1606164426Ssam else 1607164426Ssam v = 0xffff | NPE_MII_READ_FAIL; 1608164426Ssam return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1609164426Ssam#undef MAXTRIES 1610164426Ssam} 1611164426Ssam 1612164426Ssamstatic void 1613164426Ssamnpe_miibus_writereg(device_t dev, int phy, int reg, int data) 1614164426Ssam{ 1615164426Ssam struct npe_softc *sc = device_get_softc(dev); 1616164426Ssam uint32_t v; 1617164426Ssam 1618177505Ssam if (phy != sc->sc_phy) /* XXX */ 1619164426Ssam return; 1620164426Ssam v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1621164426Ssam | data | NPE_MII_WRITE 1622164426Ssam | NPE_MII_GO; 1623164426Ssam npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1624164426Ssam /* XXX complain about timeout */ 1625164426Ssam (void) npe_mii_mdio_wait(sc); 1626164426Ssam} 1627164426Ssam 1628164426Ssamstatic void 1629164426Ssamnpe_miibus_statchg(device_t dev) 1630164426Ssam{ 1631164426Ssam struct npe_softc *sc = device_get_softc(dev); 1632164426Ssam struct mii_data *mii = device_get_softc(sc->sc_mii); 1633164426Ssam uint32_t tx1, rx1; 1634164426Ssam 1635164426Ssam /* sync MAC duplex state */ 1636164426Ssam tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1637164426Ssam rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1638164426Ssam if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1639164426Ssam tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1640164426Ssam rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1641164426Ssam } else { 1642164426Ssam tx1 |= NPE_TX_CNTRL1_DUPLEX; 1643164426Ssam rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1644164426Ssam } 1645164426Ssam WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1646164426Ssam WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1647164426Ssam} 1648164426Ssam 1649164426Ssamstatic device_method_t npe_methods[] = { 1650164426Ssam /* Device interface */ 1651164426Ssam DEVMETHOD(device_probe, npe_probe), 1652164426Ssam DEVMETHOD(device_attach, npe_attach), 1653164426Ssam DEVMETHOD(device_detach, npe_detach), 1654164426Ssam 1655164426Ssam /* Bus interface */ 1656164426Ssam DEVMETHOD(bus_child_detached, npe_child_detached), 1657164426Ssam 1658164426Ssam /* MII interface */ 1659164426Ssam DEVMETHOD(miibus_readreg, npe_miibus_readreg), 1660164426Ssam DEVMETHOD(miibus_writereg, npe_miibus_writereg), 1661164426Ssam DEVMETHOD(miibus_statchg, npe_miibus_statchg), 1662164426Ssam 1663164426Ssam { 0, 0 } 1664164426Ssam}; 1665164426Ssam 1666164426Ssamstatic driver_t npe_driver = { 1667164426Ssam "npe", 1668164426Ssam npe_methods, 1669164426Ssam sizeof(struct npe_softc), 1670164426Ssam}; 1671164426Ssam 1672164426SsamDRIVER_MODULE(npe, ixp, npe_driver, npe_devclass, 0, 0); 1673164426SsamDRIVER_MODULE(miibus, npe, miibus_driver, miibus_devclass, 0, 0); 1674164426SsamMODULE_DEPEND(npe, ixpqmgr, 1, 1, 1); 1675164426SsamMODULE_DEPEND(npe, miibus, 1, 1, 1); 1676164426SsamMODULE_DEPEND(npe, ether, 1, 1, 1); 1677