zy7_slcr.h revision 249997
1249997Swkoszek/*- 2249997Swkoszek * Copyright (C) 2013, Thomas Skibo. 3249997Swkoszek * All rights reserved. 4249997Swkoszek * 5249997Swkoszek * Redistribution and use in source and binary forms, with or without 6249997Swkoszek * modification, are permitted provided that the following conditions are met: 7249997Swkoszek * * Redistributions of source code must retain the above copyright 8249997Swkoszek * notice, this list of conditions and the following disclaimer. 9249997Swkoszek * * Redistributions in binary form must reproduce the above copyright 10249997Swkoszek * notice, this list of conditions and the following disclaimer in the 11249997Swkoszek * documentation and/or other materials provided with the distribution. 12249997Swkoszek * * The names of contributors may not be used to endorse or promote products 13249997Swkoszek * derived from this software without specific prior written permission. 14249997Swkoszek * 15249997Swkoszek * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16249997Swkoszek * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17249997Swkoszek * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18249997Swkoszek * ARE DISCLAIMED. IN NO EVENT SHALL AUTHORS OR CONTRIBUTORS BE LIABLE FOR 19249997Swkoszek * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20249997Swkoszek * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21249997Swkoszek * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 22249997Swkoszek * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23249997Swkoszek * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24249997Swkoszek * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 25249997Swkoszek * DAMAGE. 26249997Swkoszek * 27249997Swkoszek */ 28249997Swkoszek 29249997Swkoszek/* $FreeBSD: head/sys/arm/xilinx/zy7_slcr.h 249997 2013-04-27 22:38:29Z wkoszek $ */ 30249997Swkoszek 31249997Swkoszek/* Defines for Zynq-7000 SLCR registers. 32249997Swkoszek * 33249997Swkoszek * Most of these registers are initialized by the First Stage Boot 34249997Swkoszek * Loader and are not modified by the kernel. 35249997Swkoszek * 36249997Swkoszek * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 37249997Swkoszek * (v1.4) November 16, 2012. Xilinx doc UG585. SLCR register definitions 38249997Swkoszek * are in appendix B.28. 39249997Swkoszek */ 40249997Swkoszek 41249997Swkoszek 42249997Swkoszek#ifndef _ZY7_SLCR_H_ 43249997Swkoszek#define _ZY7_SLCR_H_ 44249997Swkoszek 45249997Swkoszek#define ZY7_SCLR_SCL 0x0000 46249997Swkoszek#define ZY7_SLCR_LOCK 0x0004 47249997Swkoszek#define ZY7_SLCR_LOCK_MAGIC 0x767b 48249997Swkoszek#define ZY7_SLCR_UNLOCK 0x0008 49249997Swkoszek#define ZY7_SLCR_UNLOCK_MAGIC 0xdf0d 50249997Swkoszek#define ZY7_SLCR_LOCKSTA 0x000c 51249997Swkoszek 52249997Swkoszek/* PLL controls. */ 53249997Swkoszek#define ZY7_SLCR_ARM_PLL_CTRL 0x0100 54249997Swkoszek#define ZY7_SLCR_DDR_PLL_CTRL 0x0104 55249997Swkoszek#define ZY7_SLCR_IO_PLL_CTRL 0x0108 56249997Swkoszek#define ZY7_SLCR_PLL_CTRL_RESET (1<<0) 57249997Swkoszek#define ZY7_SLCR_PLL_CTRL_PWRDWN (1<<1) 58249997Swkoszek#define ZY7_SLCR_PLL_CTRL_BYPASS_QUAL (1<<3) 59249997Swkoszek#define ZY7_SLCR_PLL_CTRL_BYPASS_FORCE (1<<4) 60249997Swkoszek#define ZY7_SLCR_PLL_CTRL_FDIV_SHIFT 12 61249997Swkoszek#define ZY7_SLCR_PLL_CTRL_FDIV_MASK (0x7f<<12) 62249997Swkoszek#define ZY7_SLCR_PLL_STATUS 0x010c 63249997Swkoszek#define ZY7_SLCR_PLL_STAT_ARM_PLL_LOCK (1<<0) 64249997Swkoszek#define ZY7_SLCR_PLL_STAT_DDR_PLL_LOCK (1<<1) 65249997Swkoszek#define ZY7_SLCR_PLL_STAT_IO_PLL_LOCK (1<<2) 66249997Swkoszek#define ZY7_SLCR_PLL_STAT_ARM_PLL_STABLE (1<<3) 67249997Swkoszek#define ZY7_SLCR_PLL_STAT_DDR_PLL_STABLE (1<<4) 68249997Swkoszek#define ZY7_SLCR_PLL_STAT_IO_PLL_STABLE (1<<5) 69249997Swkoszek#define ZY7_SLCR_ARM_PLL_CFG 0x0110 70249997Swkoszek#define ZY7_SLCR_DDR_PLL_CFG 0x0114 71249997Swkoszek#define ZY7_SLCR_IO_PLL_CFG 0x0118 72249997Swkoszek#define ZY7_SLCR_PLL_CFG_RES_SHIFT 4 73249997Swkoszek#define ZY7_SLCR_PLL_CFG_RES_MASK (0xf<<4) 74249997Swkoszek#define ZY7_SLCR_PLL_CFG_PLL_CP_SHIFT 8 75249997Swkoszek#define ZY7_SLCR_PLL_CFG_PLL_CP_MASK (0xf<<8) 76249997Swkoszek#define ZY7_SLCR_PLL_CFG_LOCK_CNT_SHIFT 12 77249997Swkoszek#define ZY7_SLCR_PLL_CFG_LOCK_CNT_MASK (0x3ff<<12) 78249997Swkoszek 79249997Swkoszek/* Clock controls. */ 80249997Swkoszek#define ZY7_SLCR_ARM_CLK_CTRL 0x0120 81249997Swkoszek#define ZY7_SLCR_ARM_CLK_CTRL_CPU_PERI_CLKACT (1<<28) 82249997Swkoszek#define ZY7_SLCR_ARM_CLK_CTRL_CPU_1XCLKACT (1<<27) 83249997Swkoszek#define ZY7_SLCR_ARM_CLK_CTRL_CPU_2XCLKACT (1<<26) 84249997Swkoszek#define ZY7_SLCR_ARM_CLK_CTRL_CPU_3OR2XCLKACT (1<<25) 85249997Swkoszek#define ZY7_SLCR_ARM_CLK_CTRL_CPU_6OR4XCLKACT (1<<24) 86249997Swkoszek#define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_MASK (3<<4) 87249997Swkoszek#define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_ARM_PLL (0<<4) 88249997Swkoszek#define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_DDR_PLL (2<<4) 89249997Swkoszek#define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_IO_PLL (3<<4) 90249997Swkoszek#define ZY7_SLCR_ARM_CLK_CTRL_DIVISOR_SHIFT 8 91249997Swkoszek#define ZY7_SLCR_ARM_CLK_CTRL_DIVISOR_MASK (0x3f<<8) 92249997Swkoszek#define ZY7_SLCR_DDR_CLK_CTRL 0x0124 93249997Swkoszek#define ZY7_SLCR_DDR_CLK_CTRL_2XCLK_DIV_SHIFT 26 94249997Swkoszek#define ZY7_SLCR_DDR_CLK_CTRL_2XCLK_DIV_MASK (0x3f<<26) 95249997Swkoszek#define ZY7_SLCR_DDR_CLK_CTRL_3XCLK_DIV_SHIFT 20 96249997Swkoszek#define ZY7_SLCR_DDR_CLK_CTRL_3XCLK_DIV_MASK (0x3f<<20) 97249997Swkoszek#define ZY7_SLCR_DDR_CLK_CTRL_2XCLKACT (1<<1) 98249997Swkoszek#define ZY7_SLCR_DDR_CLK_CTRL_3XCLKACT (1<<0) 99249997Swkoszek#define ZY7_SLCR_DCI_CLK_CTRL 0x0128 100249997Swkoszek#define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR1_SHIFT 20 101249997Swkoszek#define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR1_MASK (0x3f<<20) 102249997Swkoszek#define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR0_SHIFT 8 103249997Swkoszek#define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR0_MASK (0x3f<<8) 104249997Swkoszek#define ZY7_SLCR_DCI_CLK_CTRL_CLKACT (1<<0) 105249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL 0x012c /* amba periph clk ctrl */ 106249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_SMC_CPU_1XCLKACT (1<<24) 107249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_LQSPI_CPU_1XCLKACT (1<<23) 108249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_GPIO_CPU_1XCLKACT (1<<22) 109249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_UART1_CPU_1XCLKACT (1<<21) 110249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_UART0_CPU_1XCLKACT (1<<20) 111249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_I2C1_CPU_1XCLKACT (1<<19) 112249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_I2C0_CPU_1XCLKACT (1<<18) 113249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_CAN1_CPU_1XCLKACT (1<<17) 114249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_CAN0_CPU_1XCLKACT (1<<16) 115249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_SPI1_CPU_1XCLKACT (1<<15) 116249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_SPI0_CPU_1XCLKACT (1<<14) 117249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_SDI1_CPU_1XCLKACT (1<<11) 118249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_SDI0_CPU_1XCLKACT (1<<10) 119249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_GEM1_CPU_1XCLKACT (1<<7) 120249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_GEM0_CPU_1XCLKACT (1<<6) 121249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_USB1_CPU_1XCLKACT (1<<3) 122249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_USB0_CPU_1XCLKACT (1<<2) 123249997Swkoszek#define ZY7_SLCR_APER_CLK_CTRL_DMA_CPU_1XCLKACT (1<<0) 124249997Swkoszek#define ZY7_SLCR_USB0_CLK_CTRL 0x0130 125249997Swkoszek#define ZY7_SLCR_USB1_CLK_CTRL 0x0134 126249997Swkoszek#define ZY7_SLCR_GEM0_RCLK_CTRL 0x0138 127249997Swkoszek#define ZY7_SLCR_GEM1_RCLK_CTRL 0x013c 128249997Swkoszek#define ZY7_SLCR_GEM0_CLK_CTRL 0x0140 129249997Swkoszek#define ZY7_SLCR_GEM1_CLK_CTRL 0x0144 130249997Swkoszek#define ZY7_SLCR_SMC_CLK_CTRL 0x0148 131249997Swkoszek#define ZY7_SLCR_LQSPI_CLK_CTRL 0x014c 132249997Swkoszek#define ZY7_SLCR_SDIO_CLK_CTRL 0x0150 133249997Swkoszek#define ZY7_SLCR_UART_CLK_CTRL 0x0154 134249997Swkoszek#define ZY7_SLCR_SPI_CLK_CTRL 0x0158 135249997Swkoszek#define ZY7_SLCR_CAN_CLK_CTRL 0x015c 136249997Swkoszek#define ZY7_SLCR_CAN_MIOCLK_CTRL 0x0160 137249997Swkoszek#define ZY7_SLCR_DBG_CLK_CTRL 0x0164 138249997Swkoszek#define ZY7_SLCR_PCAP_CLK_CTRL 0x0168 139249997Swkoszek#define ZY7_SLCR_TOPSW_CLK_CTRL 0x016c /* central intercnn clk ctrl */ 140249997Swkoszek#define ZY7_SLCR_FPGA0_CLK_CTRL 0x0170 141249997Swkoszek#define ZY7_SLCR_FPGA1_CLK_CTRL 0x0180 142249997Swkoszek#define ZY7_SLCR_FPGA2_CLK_CTRL 0x0190 143249997Swkoszek#define ZY7_SLCR_FPGA3_CLK_CTRL 0x01a0 144249997Swkoszek#define ZY7_SLCR_CLK_621_TRUE 0x01c4 /* cpu clock ratio mode */ 145249997Swkoszek 146249997Swkoszek/* Reset controls. */ 147249997Swkoszek#define ZY7_SLCR_PSS_RST_CTRL 0x0200 148249997Swkoszek#define ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET (1<<0) 149249997Swkoszek#define ZY7_SLCR_DDR_RST_CTRL 0x0204 150249997Swkoszek#define ZY7_SLCR_TOPSW_RST_CTRL 0x0208 151249997Swkoszek#define ZY7_SLCR_DMAC_RST_CTRL 0x020c 152249997Swkoszek#define ZY7_SLCR_USB_RST_CTRL 0x0210 153249997Swkoszek#define ZY7_SLCR_GEM_RST_CTRL 0x0214 154249997Swkoszek#define ZY7_SLCR_SDIO_RST_CTRL 0x0218 155249997Swkoszek#define ZY7_SLCR_SPI_RST_CTRL 0x021c 156249997Swkoszek#define ZY7_SLCR_CAN_RST_CTRL 0x0220 157249997Swkoszek#define ZY7_SLCR_I2C_RST_CTRL 0x0224 158249997Swkoszek#define ZY7_SLCR_UART_RST_CTRL 0x0228 159249997Swkoszek#define ZY7_SLCR_GPIO_RST_CTRL 0x022c 160249997Swkoszek#define ZY7_SLCR_LQSPI_RST_CTRL 0x0230 161249997Swkoszek#define ZY7_SLCR_SMC_RST_CTRL 0x0234 162249997Swkoszek#define ZY7_SLCR_OCM_RST_CTRL 0x0238 163249997Swkoszek#define ZY7_SLCR_DEVCI_RST_CTRL 0x023c 164249997Swkoszek#define ZY7_SLCR_FPGA_RST_CTRL 0x0240 165249997Swkoszek#define ZY7_SLCR_FPGA_RST_CTRL_FPGA3_OUT_RST (1<<3) 166249997Swkoszek#define ZY7_SLCR_FPGA_RST_CTRL_FPGA2_OUT_RST (1<<2) 167249997Swkoszek#define ZY7_SLCR_FPGA_RST_CTRL_FPGA1_OUT_RST (1<<1) 168249997Swkoszek#define ZY7_SLCR_FPGA_RST_CTRL_FPGA0_OUT_RST (1<<0) 169249997Swkoszek#define ZY7_SLCR_FPGA_RST_CTRL_RST_ALL 0xf 170249997Swkoszek#define ZY7_SLCR_A9_CPU_RST_CTRL 0x0244 171249997Swkoszek#define ZY7_SLCR_RS_AWDT_CTRL 0x024c 172249997Swkoszek 173249997Swkoszek#define ZY7_SLCR_REBOOT_STAT 0x0258 174249997Swkoszek#define ZY7_SLCR_REBOOT_STAT_STATE_MASK (0xff<<24) 175249997Swkoszek#define ZY7_SLCR_REBOOT_STAT_POR (1<<22) 176249997Swkoszek#define ZY7_SLCR_REBOOT_STAT_SRST_B (1<<21) 177249997Swkoszek#define ZY7_SLCR_REBOOT_STAT_DBG_RST (1<<20) 178249997Swkoszek#define ZY7_SLCR_REBOOT_STAT_SLC_RST (1<<19) 179249997Swkoszek#define ZY7_SLCR_REBOOT_STAT_AWDT1_RST (1<<18) 180249997Swkoszek#define ZY7_SLCR_REBOOT_STAT_AWDT0_RST (1<<17) 181249997Swkoszek#define ZY7_SLCR_REBOOT_STAT_SWDT_RST (1<<16) 182249997Swkoszek#define ZY7_SLCR_REBOOT_STAT_BOOTROM_ERR_CODE_MASK (0xffff) 183249997Swkoszek#define ZY7_SLCR_BOOT_MODE 0x025c 184249997Swkoszek#define ZY7_SLCR_BOOT_MODE_PLL_BYPASS (1<<4) 185249997Swkoszek#define ZY7_SLCR_BOOT_MODE_JTAG_INDEP (1<<3) 186249997Swkoszek#define ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK 7 187249997Swkoszek#define ZY7_SLCR_BOOT_MODE_BOOTDEV_JTAG 0 188249997Swkoszek#define ZY7_SLCR_BOOT_MODE_BOOTDEV_QUAD_SPI 1 189249997Swkoszek#define ZY7_SLCR_BOOT_MODE_BOOTDEV_NOR 2 190249997Swkoszek#define ZY7_SLCR_BOOT_MODE_BOOTDEV_NAND 4 191249997Swkoszek#define ZY7_SLCR_BOOT_MODE_BOOTDEV_SD_CARD 5 192249997Swkoszek#define ZY7_SLCR_APU_CTRL 0x0300 193249997Swkoszek#define ZY7_SLCR_WDT_CLK_SEL 0x0304 194249997Swkoszek 195249997Swkoszek#define ZY7_SLCR_PSS_IDCODE 0x0530 196249997Swkoszek#define ZY7_SLCR_PSS_IDCODE_REVISION_MASK (0xf<<28) 197249997Swkoszek#define ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT 28 198249997Swkoszek#define ZY7_SLCR_PSS_IDCODE_FAMILY_MASK (0x7f<<21) 199249997Swkoszek#define ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT 21 200249997Swkoszek#define ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK (0xf<<17) 201249997Swkoszek#define ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT 17 202249997Swkoszek#define ZY7_SLCR_PSS_IDCODE_DEVICE_MASK (0x1f<<12) 203249997Swkoszek#define ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT 12 204249997Swkoszek#define ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK (0x7ff<<1) 205249997Swkoszek#define ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT 1 206249997Swkoszek 207249997Swkoszek#define ZY7_SLCR_DDR_URGENT 0x0600 208249997Swkoszek#define ZY7_SLCR_DDR_CAL_START 0x060c 209249997Swkoszek#define ZY7_SLCR_DDR_REF_START 0x0614 210249997Swkoszek#define ZY7_SLCR_DDR_CMD_STA 0x0618 211249997Swkoszek#define ZY7_SLCR_DDR_URGENT_SEL 0x061c 212249997Swkoszek#define ZY7_SLCR_DDR_DFI_STATUS 0x0620 213249997Swkoszek 214249997Swkoszek/* MIO Pin controls */ 215249997Swkoszek#define ZY7_SLCR_MIO_PIN(n) (0x0700+(n)*4) /* 0-53 */ 216249997Swkoszek#define ZY7_SLCR_MIO_PIN_RCVR_DIS (1<<13) 217249997Swkoszek#define ZY7_SLCR_MIO_PIN_PULLUP_EN (1<<12) 218249997Swkoszek#define ZY7_SLCR_MIO_PIN_IO_TYPE_MASK (7<<9) 219249997Swkoszek#define ZY7_SLCR_MIO_PIN_IO_TYPE_LVTTL (0<<9) 220249997Swkoszek#define ZY7_SLCR_MIO_PIN_IO_TYPE_LVCMOS18 (1<<9) 221249997Swkoszek#define ZY7_SLCR_MIO_PIN_IO_TYPE_LVCMOS25 (2<<9) 222249997Swkoszek#define ZY7_SLCR_MIO_PIN_IO_TYPE_LVCMOS33 (3<<9) 223249997Swkoszek#define ZY7_SLCR_MIO_PIN_IO_TYPE_HSTL (4<<9) 224249997Swkoszek#define ZY7_SLCR_MIO_PIN_L2_SEL_MASK (3<<3) 225249997Swkoszek#define ZY7_SLCR_MIO_PIN_L2_SEL_L3_MUX (0<<3) 226249997Swkoszek#define ZY7_SLCR_MIO_PIN_L2_SEL_SRAM_NOR_CS0 (1<<3) 227249997Swkoszek#define ZY7_SLCR_MIO_PIN_L2_SEL_NAND_CS (2<<3) 228249997Swkoszek#define ZY7_SLCR_MIO_PIN_L2_SEL_SDIO0_PC (3<<3) 229249997Swkoszek#define ZY7_SLCR_MIO_PIN_L1_SEL (1<<2) 230249997Swkoszek#define ZY7_SLCR_MIO_PIN_L0_SEL (1<<1) 231249997Swkoszek#define ZY7_SLCR_MIO_PIN_TRI_EN (1<<0) 232249997Swkoszek 233249997Swkoszek#define ZY7_SLCR_MIO_LOOPBACK 0x0804 234249997Swkoszek#define ZY7_SLCR_MIO_LOOPBACK_I2C0_I2C1 (1<<3) 235249997Swkoszek#define ZY7_SLCR_MIO_LOOPBACK_CAN0_CAN1 (1<<2) 236249997Swkoszek#define ZY7_SLCR_MIO_LOOPBACK_UA0_UA1 (1<<1) 237249997Swkoszek#define ZY7_SLCR_MIO_LOOPBACK_SPI0_SPI1 (1<<0) 238249997Swkoszek#define ZY7_SLCR_MIO_MST_TRI0 0x080c 239249997Swkoszek#define ZY7_SLCR_MIO_MST_TRI1 0x0810 240249997Swkoszek#define ZY7_SLCR_SD0_WP_CD_SEL 0x0830 241249997Swkoszek#define ZY7_SLCR_SD1_WP_CD_SEL 0x0834 242249997Swkoszek 243249997Swkoszek/* PS-PL level shifter control. */ 244249997Swkoszek#define ZY7_SLCR_LVL_SHFTR_EN 0x900 245249997Swkoszek#define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_IN_EN_0 (1<<3) /* PL to PS */ 246249997Swkoszek#define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_OUT_EN_0 (1<<2) /* PS to PL */ 247249997Swkoszek#define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_IN_EN_1 (1<<1) /* PL to PS */ 248249997Swkoszek#define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_OUT_EN_1 (1<<0) /* PS to PL */ 249249997Swkoszek#define ZY7_SLCR_LVL_SHFTR_EN_ALL 0xf 250249997Swkoszek 251249997Swkoszek#define ZY7_SLCR_OCM_CFG 0x0910 252249997Swkoszek 253249997Swkoszek#define ZY7_SLCR_GPIOB_CTRL 0x0b00 254249997Swkoszek#define ZY7_SLCR_GPIOB_CFG_CMOS18 0x0b04 255249997Swkoszek#define ZY7_SLCR_GPIOB_CFG_CMOS25 0x0b08 256249997Swkoszek#define ZY7_SLCR_GPIOB_CFG_CMOS33 0x0b0c 257249997Swkoszek#define ZY7_SLCR_GPIOB_CFG_LVTTL 0x0b10 258249997Swkoszek#define ZY7_SLCR_GPIOB_CFG_HSTL 0x0b14 259249997Swkoszek#define ZY7_SLCR_GPIOB_DRVR_BIAS_CTRL 0x0b18 260249997Swkoszek 261249997Swkoszek#define ZY7_SLCR_DDRIOB_ADDR0 0x0b40 262249997Swkoszek#define ZY7_SLCR_DDRIOB_ADDR1 0x0b44 263249997Swkoszek#define ZY7_SLCR_DDRIOB_DATA0 0x0b48 264249997Swkoszek#define ZY7_SLCR_DDRIOB_DATA1 0x0b4c 265249997Swkoszek#define ZY7_SLCR_DDRIOB_DIFF0 0x0b50 266249997Swkoszek#define ZY7_SLCR_DDRIOB_DIFF1 0x0b54 267249997Swkoszek#define ZY7_SLCR_DDRIOB_CLK 0x0b58 268249997Swkoszek#define ZY7_SLCR_DDRIOB_DRIVE_SLEW_ADDR 0x0b5c 269249997Swkoszek#define ZY7_SLCR_DDRIOB_DRIVE_SLEW_DATA 0x0b60 270249997Swkoszek#define ZY7_SLCR_DDRIOB_DRIVE_SLEW_DIFF 0x0b64 271249997Swkoszek#define ZY7_SLCR_DDRIOB_DRIVE_SLEW_CLK 0x0b68 272249997Swkoszek#define ZY7_SLCR_DDRIOB_DDR_CTRL 0x0b6c 273249997Swkoszek#define ZY7_SLCR_DDRIOB_DCI_CTRL 0x0b70 274249997Swkoszek#define ZY7_SLCR_DDRIOB_DCI_STATUS 0x0b74 275249997Swkoszek 276249997Swkoszek#ifdef _KERNEL 277249997Swkoszekextern void zy7_slcr_preload_pl(void); 278249997Swkoszekextern void zy7_slcr_postload_pl(int); 279249997Swkoszek#endif 280249997Swkoszek#endif /* _ZY7_SLCR_H_ */ 281