ti_sdhci.c revision 271051
1254559Sian/*- 2254559Sian * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3254559Sian * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 4254559Sian * All rights reserved. 5254559Sian * 6254559Sian * Redistribution and use in source and binary forms, with or without 7254559Sian * modification, are permitted provided that the following conditions 8254559Sian * are met: 9254559Sian * 1. Redistributions of source code must retain the above copyright 10254559Sian * notice, this list of conditions and the following disclaimer. 11254559Sian * 2. Redistributions in binary form must reproduce the above copyright 12254559Sian * notice, this list of conditions and the following disclaimer in the 13254559Sian * documentation and/or other materials provided with the distribution. 14254559Sian * 15254559Sian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16254559Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17254559Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18254559Sian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19254559Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20254559Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21254559Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22254559Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23254559Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24254559Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25254559Sian * SUCH DAMAGE. 26254559Sian * 27254559Sian */ 28254559Sian#include <sys/cdefs.h> 29254559Sian__FBSDID("$FreeBSD: stable/10/sys/arm/ti/ti_sdhci.c 271051 2014-09-03 20:07:26Z marius $"); 30254559Sian 31254559Sian#include <sys/param.h> 32254559Sian#include <sys/systm.h> 33254559Sian#include <sys/bus.h> 34254559Sian#include <sys/gpio.h> 35254559Sian#include <sys/kernel.h> 36254559Sian#include <sys/malloc.h> 37254559Sian#include <sys/module.h> 38254559Sian#include <sys/resource.h> 39254559Sian#include <sys/rman.h> 40271051Smarius#include <sys/sysctl.h> 41254559Sian#include <sys/taskqueue.h> 42254559Sian 43254559Sian#include <machine/bus.h> 44254559Sian#include <machine/resource.h> 45254559Sian#include <machine/intr.h> 46254559Sian 47254559Sian#include <dev/fdt/fdt_common.h> 48254559Sian#include <dev/ofw/ofw_bus.h> 49254559Sian#include <dev/ofw/ofw_bus_subr.h> 50254559Sian 51254559Sian#include <dev/mmc/bridge.h> 52254559Sian#include <dev/mmc/mmcreg.h> 53254559Sian#include <dev/mmc/mmcbrvar.h> 54254559Sian 55254559Sian#include <dev/sdhci/sdhci.h> 56254559Sian#include "sdhci_if.h" 57254559Sian 58254559Sian#include <arm/ti/ti_cpuid.h> 59254559Sian#include <arm/ti/ti_prcm.h> 60254559Sian#include "gpio_if.h" 61254559Sian 62254559Sianstruct ti_sdhci_softc { 63254559Sian device_t dev; 64254559Sian device_t gpio_dev; 65254559Sian struct resource * mem_res; 66254559Sian struct resource * irq_res; 67254559Sian void * intr_cookie; 68254559Sian struct sdhci_slot slot; 69254559Sian uint32_t mmchs_device_id; 70254559Sian uint32_t mmchs_reg_off; 71254559Sian uint32_t sdhci_reg_off; 72254559Sian uint32_t baseclk_hz; 73254559Sian uint32_t wp_gpio_pin; 74254559Sian uint32_t cmd_and_mode; 75254559Sian uint32_t sdhci_clkdiv; 76266751Sian boolean_t disable_highspeed; 77266751Sian boolean_t force_card_present; 78254559Sian}; 79254559Sian 80254559Sian/* 81259356Sian * Table of supported FDT compat strings. 82259356Sian * 83259356Sian * Note that "ti,mmchs" is our own invention, and should be phased out in favor 84259356Sian * of the documented names. 85259356Sian * 86259356Sian * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x. 87259356Sian */ 88259356Sianstatic struct ofw_compat_data compat_data[] = { 89259356Sian {"ti,omap3-hsmmc", 1}, 90259356Sian {"ti,omap4-hsmmc", 1}, 91259356Sian {"ti,mmchs", 1}, 92259356Sian {NULL, 0}, 93259356Sian}; 94259356Sian 95259356Sian/* 96254559Sian * The MMCHS hardware has a few control and status registers at the beginning of 97254559Sian * the device's memory map, followed by the standard sdhci register block. 98254559Sian * Different SoCs have the register blocks at different offsets from the 99254559Sian * beginning of the device. Define some constants to map out the registers we 100254559Sian * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far 101254559Sian * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs. 102254559Sian */ 103254559Sian#define OMAP3_MMCHS_REG_OFFSET 0x000 104254559Sian#define OMAP4_MMCHS_REG_OFFSET 0x100 105254559Sian#define AM335X_MMCHS_REG_OFFSET 0x100 106254559Sian#define SDHCI_REG_OFFSET 0x100 107254559Sian 108254559Sian#define MMCHS_SYSCONFIG 0x010 109254559Sian#define MMCHS_SYSCONFIG_RESET (1 << 1) 110254559Sian#define MMCHS_SYSSTATUS 0x014 111266751Sian#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) 112254559Sian#define MMCHS_CON 0x02C 113254559Sian#define MMCHS_CON_DW8 (1 << 5) 114254559Sian#define MMCHS_CON_DVAL_8_4MS (3 << 9) 115266751Sian#define MMCHS_SYSCTL 0x12C 116266751Sian#define MMCHS_SYSCTL_CLKD_MASK 0x3FF 117266751Sian#define MMCHS_SYSCTL_CLKD_SHIFT 6 118259374Sian#define MMCHS_SD_CAPA 0x140 119259356Sian#define MMCHS_SD_CAPA_VS18 (1 << 26) 120259356Sian#define MMCHS_SD_CAPA_VS30 (1 << 25) 121259356Sian#define MMCHS_SD_CAPA_VS33 (1 << 24) 122254559Sian 123254559Sianstatic inline uint32_t 124254559Sianti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off) 125254559Sian{ 126254559Sian 127254559Sian return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); 128254559Sian} 129254559Sian 130254559Sianstatic inline void 131254559Sianti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 132254559Sian{ 133254559Sian 134254559Sian bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); 135254559Sian} 136254559Sian 137254559Sianstatic inline uint32_t 138254559SianRD4(struct ti_sdhci_softc *sc, bus_size_t off) 139254559Sian{ 140254559Sian 141254559Sian return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off)); 142254559Sian} 143254559Sian 144254559Sianstatic inline void 145254559SianWR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 146254559Sian{ 147254559Sian 148254559Sian bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val); 149254559Sian} 150254559Sian 151254559Sianstatic uint8_t 152254559Sianti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 153254559Sian{ 154254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 155254559Sian 156254559Sian return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 157254559Sian} 158254559Sian 159254559Sianstatic uint16_t 160254559Sianti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 161254559Sian{ 162254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 163254559Sian uint32_t clkdiv, val32; 164254559Sian 165254559Sian /* 166254559Sian * The MMCHS hardware has a non-standard interpretation of the sdclock 167254559Sian * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6) 168254559Sian * but doesn't split them into low:high fields. Instead they're a 169254559Sian * single number in the range 0..1023 and the number is exactly the 170254559Sian * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI 171266751Sian * driver code expects a v2.0 or v3.0 divisor. The shifting and masking 172254559Sian * here extracts the MMCHS representation from the hardware word, cleans 173266751Sian * those bits out, applies the 2N adjustment, and plugs the result into 174266751Sian * the bit positions for the 2.0 or 3.0 divisor in the returned register 175266751Sian * value. The ti_sdhci_write_2() routine performs the opposite 176266751Sian * transformation when the SDHCI driver writes to the register. 177254559Sian */ 178254559Sian if (off == SDHCI_CLOCK_CONTROL) { 179254559Sian val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 180266751Sian clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) & 181266751Sian MMCHS_SYSCTL_CLKD_MASK) / 2; 182266751Sian val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT); 183266751Sian val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 184266751Sian if (slot->version >= SDHCI_SPEC_300) 185266751Sian val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) & 186266751Sian SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT; 187254559Sian return (val32 & 0xffff); 188254559Sian } 189254559Sian 190254559Sian /* 191254559Sian * Standard 32-bit handling of command and transfer mode. 192254559Sian */ 193254559Sian if (off == SDHCI_TRANSFER_MODE) { 194254559Sian return (sc->cmd_and_mode >> 16); 195254559Sian } else if (off == SDHCI_COMMAND_FLAGS) { 196254559Sian return (sc->cmd_and_mode & 0x0000ffff); 197254559Sian } 198254559Sian 199254559Sian return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 200254559Sian} 201254559Sian 202254559Sianstatic uint32_t 203254559Sianti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 204254559Sian{ 205254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 206266751Sian uint32_t val32; 207254559Sian 208266751Sian val32 = RD4(sc, off); 209266751Sian 210266751Sian /* 211266751Sian * If we need to disallow highspeed mode due to the OMAP4 erratum, strip 212266751Sian * that flag from the returned capabilities. 213266751Sian */ 214266751Sian if (off == SDHCI_CAPABILITIES && sc->disable_highspeed) 215266751Sian val32 &= ~SDHCI_CAN_DO_HISPD; 216266751Sian 217266751Sian /* 218266751Sian * Force the card-present state if necessary. 219266751Sian */ 220266751Sian if (off == SDHCI_PRESENT_STATE && sc->force_card_present) 221266751Sian val32 |= SDHCI_CARD_PRESENT; 222266751Sian 223266751Sian return (val32); 224254559Sian} 225254559Sian 226254559Sianstatic void 227254559Sianti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 228254559Sian uint32_t *data, bus_size_t count) 229254559Sian{ 230254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 231254559Sian 232254559Sian bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 233254559Sian} 234254559Sian 235254559Sianstatic void 236254559Sianti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 237254559Sian uint8_t val) 238254559Sian{ 239254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 240254559Sian uint32_t val32; 241254559Sian 242254559Sian val32 = RD4(sc, off & ~3); 243254559Sian val32 &= ~(0xff << (off & 3) * 8); 244254559Sian val32 |= (val << (off & 3) * 8); 245254559Sian 246254559Sian WR4(sc, off & ~3, val32); 247254559Sian} 248254559Sian 249254559Sianstatic void 250254559Sianti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 251254559Sian uint16_t val) 252254559Sian{ 253254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 254254559Sian uint32_t clkdiv, val32; 255254559Sian 256254559Sian /* 257266751Sian * Translate between the hardware and SDHCI 2.0 or 3.0 representations 258266751Sian * of the clock divisor. See the comments in ti_sdhci_read_2() for 259266751Sian * details. 260254559Sian */ 261254559Sian if (off == SDHCI_CLOCK_CONTROL) { 262254559Sian clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 263266751Sian if (slot->version >= SDHCI_SPEC_300) 264266751Sian clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & 265266751Sian SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; 266266751Sian clkdiv *= 2; 267266751Sian if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) 268266751Sian clkdiv = MMCHS_SYSCTL_CLKD_MASK; 269254559Sian val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 270254559Sian val32 &= 0xffff0000; 271266751Sian val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK << 272266751Sian MMCHS_SYSCTL_CLKD_SHIFT); 273266751Sian val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT; 274254559Sian WR4(sc, SDHCI_CLOCK_CONTROL, val32); 275254559Sian return; 276254559Sian } 277254559Sian 278254559Sian /* 279254559Sian * Standard 32-bit handling of command and transfer mode. 280254559Sian */ 281254559Sian if (off == SDHCI_TRANSFER_MODE) { 282254559Sian sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | 283254559Sian ((uint32_t)val & 0x0000ffff); 284254559Sian return; 285254559Sian } else if (off == SDHCI_COMMAND_FLAGS) { 286254559Sian sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) | 287254559Sian ((uint32_t)val << 16); 288254559Sian WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 289254559Sian return; 290254559Sian } 291254559Sian 292254559Sian val32 = RD4(sc, off & ~3); 293254559Sian val32 &= ~(0xffff << (off & 3) * 8); 294254559Sian val32 |= ((val & 0xffff) << (off & 3) * 8); 295254559Sian WR4(sc, off & ~3, val32); 296254559Sian} 297254559Sian 298254559Sianstatic void 299254559Sianti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 300254559Sian uint32_t val) 301254559Sian{ 302254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 303254559Sian 304254559Sian WR4(sc, off, val); 305254559Sian} 306254559Sian 307254559Sianstatic void 308254559Sianti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 309254559Sian uint32_t *data, bus_size_t count) 310254559Sian{ 311254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 312254559Sian 313254559Sian bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 314254559Sian} 315254559Sian 316254559Sianstatic void 317254559Sianti_sdhci_intr(void *arg) 318254559Sian{ 319254559Sian struct ti_sdhci_softc *sc = arg; 320254559Sian 321254559Sian sdhci_generic_intr(&sc->slot); 322254559Sian} 323254559Sian 324254559Sianstatic int 325254559Sianti_sdhci_update_ios(device_t brdev, device_t reqdev) 326254559Sian{ 327254559Sian struct ti_sdhci_softc *sc = device_get_softc(brdev); 328254559Sian struct sdhci_slot *slot; 329254559Sian struct mmc_ios *ios; 330254559Sian uint32_t val32; 331254559Sian 332254559Sian slot = device_get_ivars(reqdev); 333254559Sian ios = &slot->host.ios; 334254559Sian 335254559Sian /* 336254559Sian * There is an 8-bit-bus bit in the MMCHS control register which, when 337254559Sian * set, overrides the 1 vs 4 bit setting in the standard SDHCI 338254559Sian * registers. Set that bit first according to whether an 8-bit bus is 339254559Sian * requested, then let the standard driver handle everything else. 340254559Sian */ 341254559Sian val32 = ti_mmchs_read_4(sc, MMCHS_CON); 342254559Sian if (ios->bus_width == bus_width_8) 343254559Sian ti_mmchs_write_4(sc, MMCHS_CON, val32 | MMCHS_CON_DW8); 344254559Sian else 345254559Sian ti_mmchs_write_4(sc, MMCHS_CON, val32 & ~MMCHS_CON_DW8); 346254559Sian 347254559Sian return (sdhci_generic_update_ios(brdev, reqdev)); 348254559Sian} 349254559Sian 350254559Sianstatic int 351254559Sianti_sdhci_get_ro(device_t brdev, device_t reqdev) 352254559Sian{ 353254559Sian struct ti_sdhci_softc *sc = device_get_softc(brdev); 354254559Sian unsigned int readonly = 0; 355254559Sian 356254559Sian /* If a gpio pin is configured, read it. */ 357254559Sian if (sc->gpio_dev != NULL) { 358254559Sian GPIO_PIN_GET(sc->gpio_dev, sc->wp_gpio_pin, &readonly); 359254559Sian } 360254559Sian 361254559Sian return (readonly); 362254559Sian} 363254559Sian 364254559Sianstatic int 365254559Sianti_sdhci_detach(device_t dev) 366254559Sian{ 367254559Sian 368254559Sian return (EBUSY); 369254559Sian} 370254559Sian 371254559Sianstatic void 372254559Sianti_sdhci_hw_init(device_t dev) 373254559Sian{ 374254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 375254559Sian clk_ident_t clk; 376259356Sian uint32_t regval; 377254559Sian unsigned long timeout; 378254559Sian 379254559Sian /* Enable the controller and interface/functional clocks */ 380254559Sian clk = MMC0_CLK + sc->mmchs_device_id; 381254559Sian if (ti_prcm_clk_enable(clk) != 0) { 382254559Sian device_printf(dev, "Error: failed to enable MMC clock\n"); 383254559Sian return; 384254559Sian } 385254559Sian 386254559Sian /* Get the frequency of the source clock */ 387254559Sian if (ti_prcm_clk_get_source_freq(clk, &sc->baseclk_hz) != 0) { 388254559Sian device_printf(dev, "Error: failed to get source clock freq\n"); 389254559Sian return; 390254559Sian } 391254559Sian 392254559Sian /* Issue a softreset to the controller */ 393254559Sian ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET); 394254559Sian timeout = 1000; 395266751Sian while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & MMCHS_SYSSTATUS_RESETDONE)) { 396254559Sian if (--timeout == 0) { 397254559Sian device_printf(dev, "Error: Controller reset operation timed out\n"); 398254559Sian break; 399254559Sian } 400254559Sian DELAY(100); 401254559Sian } 402254559Sian 403254559Sian /* Reset both the command and data state machines */ 404254559Sian ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); 405254559Sian timeout = 1000; 406254559Sian while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL)) { 407254559Sian if (--timeout == 0) { 408254559Sian device_printf(dev, "Error: Software reset operation timed out\n"); 409254559Sian break; 410254559Sian } 411254559Sian DELAY(100); 412254559Sian } 413254559Sian 414259356Sian /* 415259356Sian * The attach() routine has examined fdt data and set flags in 416259356Sian * slot.host.caps to reflect what voltages we can handle. Set those 417259356Sian * values in the CAPA register. The manual says that these values can 418259356Sian * only be set once, "before initialization" whatever that means, and 419259356Sian * that they survive a reset. So maybe doing this will be a no-op if 420259356Sian * u-boot has already initialized the hardware. 421259356Sian */ 422259356Sian regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA); 423259356Sian if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE) 424259356Sian regval |= MMCHS_SD_CAPA_VS18; 425259356Sian if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310)) 426259356Sian regval |= MMCHS_SD_CAPA_VS30; 427259356Sian ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval); 428259356Sian 429254559Sian /* Set initial host configuration (1-bit, std speed, pwr off). */ 430254559Sian ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0); 431254559Sian ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0); 432254559Sian 433254559Sian /* Set the initial controller configuration. */ 434254559Sian ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS); 435254559Sian} 436254559Sian 437254559Sianstatic int 438254559Sianti_sdhci_attach(device_t dev) 439254559Sian{ 440254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 441254559Sian int rid, err; 442254559Sian pcell_t prop; 443254559Sian phandle_t node; 444254559Sian 445254559Sian sc->dev = dev; 446254559Sian 447254559Sian /* 448254559Sian * Get the MMCHS device id from FDT. If it's not there use the newbus 449254559Sian * unit number (which will work as long as the devices are in order and 450259356Sian * none are skipped in the fdt). Note that this is a property we made 451259356Sian * up and added in freebsd, it doesn't exist in the published bindings. 452254559Sian */ 453254559Sian node = ofw_bus_get_node(dev); 454254559Sian if ((OF_getprop(node, "mmchs-device-id", &prop, sizeof(prop))) <= 0) { 455254559Sian sc->mmchs_device_id = device_get_unit(dev); 456254559Sian device_printf(dev, "missing mmchs-device-id attribute in FDT, " 457254559Sian "using unit number (%d)", sc->mmchs_device_id); 458254559Sian } else 459254559Sian sc->mmchs_device_id = fdt32_to_cpu(prop); 460254559Sian 461259356Sian /* 462259356Sian * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first 463259356Sian * device, and only 1p8v on other devices unless an external transceiver 464259356Sian * is used. The only way we could know about a transceiver is fdt data. 465259356Sian * Note that we have to do this before calling ti_sdhci_hw_init() so 466259356Sian * that it can set the right values in the CAPA register, which can only 467259356Sian * be done once and never reset. 468259356Sian */ 469259374Sian sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE; 470259356Sian if (sc->mmchs_device_id == 0 || OF_hasprop(node, "ti,dual-volt")) { 471259374Sian sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310; 472259356Sian } 473259356Sian 474259356Sian /* 475259356Sian * See if we've got a GPIO-based write detect pin. This is not the 476259356Sian * standard documented property for this, we added it in freebsd. 477259356Sian */ 478254559Sian if ((OF_getprop(node, "mmchs-wp-gpio-pin", &prop, sizeof(prop))) <= 0) 479254559Sian sc->wp_gpio_pin = 0xffffffff; 480254559Sian else 481254559Sian sc->wp_gpio_pin = fdt32_to_cpu(prop); 482254559Sian 483254559Sian if (sc->wp_gpio_pin != 0xffffffff) { 484254559Sian sc->gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 485254559Sian if (sc->gpio_dev == NULL) 486254559Sian device_printf(dev, "Error: No GPIO device, " 487254559Sian "Write Protect pin will not function\n"); 488254559Sian else 489254559Sian GPIO_PIN_SETFLAGS(sc->gpio_dev, sc->wp_gpio_pin, 490254559Sian GPIO_PIN_INPUT); 491254559Sian } 492254559Sian 493254559Sian /* 494254559Sian * Set the offset from the device's memory start to the MMCHS registers. 495266751Sian * Also for OMAP4 disable high speed mode due to erratum ID i626. 496254559Sian */ 497254559Sian if (ti_chip() == CHIP_OMAP_3) 498254559Sian sc->mmchs_reg_off = OMAP3_MMCHS_REG_OFFSET; 499266751Sian else if (ti_chip() == CHIP_OMAP_4) { 500254559Sian sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET; 501266751Sian sc->disable_highspeed = true; 502266751Sian } else if (ti_chip() == CHIP_AM335X) 503254559Sian sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET; 504254559Sian else 505254559Sian panic("Unknown OMAP device\n"); 506254559Sian 507254559Sian /* 508254559Sian * The standard SDHCI registers are at a fixed offset (the same on all 509254559Sian * SoCs) beyond the MMCHS registers. 510254559Sian */ 511254559Sian sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET; 512254559Sian 513254559Sian /* Resource setup. */ 514254559Sian rid = 0; 515254559Sian sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 516254559Sian RF_ACTIVE); 517254559Sian if (!sc->mem_res) { 518254559Sian device_printf(dev, "cannot allocate memory window\n"); 519254559Sian err = ENXIO; 520254559Sian goto fail; 521254559Sian } 522254559Sian 523254559Sian rid = 0; 524254559Sian sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 525254559Sian RF_ACTIVE); 526254559Sian if (!sc->irq_res) { 527254559Sian device_printf(dev, "cannot allocate interrupt\n"); 528254559Sian err = ENXIO; 529254559Sian goto fail; 530254559Sian } 531254559Sian 532254559Sian if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 533254559Sian NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) { 534254559Sian device_printf(dev, "cannot setup interrupt handler\n"); 535254559Sian err = ENXIO; 536254559Sian goto fail; 537254559Sian } 538254559Sian 539254559Sian /* Initialise the MMCHS hardware. */ 540254559Sian ti_sdhci_hw_init(dev); 541254559Sian 542254559Sian /* 543254559Sian * The capabilities register can only express base clock frequencies in 544254559Sian * the range of 0-63MHz for a v2.0 controller. Since our clock runs 545254559Sian * faster than that, the hardware sets the frequency to zero in the 546254559Sian * register. When the register contains zero, the sdhci driver expects 547254559Sian * slot.max_clk to already have the right value in it. 548254559Sian */ 549254559Sian sc->slot.max_clk = sc->baseclk_hz; 550254559Sian 551254559Sian /* 552254559Sian * The MMCHS timeout counter is based on the output sdclock. Tell the 553254559Sian * sdhci driver to recalculate the timeout clock whenever the output 554254559Sian * sdclock frequency changes. 555254559Sian */ 556254559Sian sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 557254559Sian 558254559Sian /* 559254559Sian * The MMCHS hardware shifts the 136-bit response data (in violation of 560254559Sian * the spec), so tell the sdhci driver not to do the same in software. 561254559Sian */ 562254559Sian sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE; 563254559Sian 564254559Sian /* 565254559Sian * DMA is not really broken, I just haven't implemented it yet. 566254559Sian */ 567254559Sian sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 568254559Sian 569259356Sian /* 570259356Sian * Set up the hardware and go. Note that this sets many of the 571259356Sian * slot.host.* fields, so we have to do this before overriding any of 572259356Sian * those values based on fdt data, below. 573259356Sian */ 574254559Sian sdhci_init_slot(dev, &sc->slot, 0); 575254559Sian 576254559Sian /* 577259356Sian * The SDHCI controller doesn't realize it, but we can support 8-bit 578259356Sian * even though we're not a v3.0 controller. If there's an fdt bus-width 579259356Sian * property, honor it. 580254559Sian */ 581259356Sian if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { 582259356Sian sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | 583259356Sian MMC_CAP_8_BIT_DATA); 584259356Sian switch (prop) { 585259356Sian case 8: 586259356Sian sc->slot.host.caps |= MMC_CAP_8_BIT_DATA; 587259356Sian /* FALLTHROUGH */ 588259356Sian case 4: 589259356Sian sc->slot.host.caps |= MMC_CAP_4_BIT_DATA; 590259356Sian break; 591259356Sian case 1: 592259356Sian break; 593259356Sian default: 594259356Sian device_printf(dev, "Bad bus-width value %u\n", prop); 595259356Sian break; 596259356Sian } 597259356Sian } 598254559Sian 599266751Sian /* 600266751Sian * If the slot is flagged with the non-removable property, set our flag 601266751Sian * to always force the SDHCI_CARD_PRESENT bit on. 602266751Sian */ 603266751Sian node = ofw_bus_get_node(dev); 604266751Sian if (OF_hasprop(node, "non-removable")) 605266751Sian sc->force_card_present = true; 606266751Sian 607254559Sian bus_generic_probe(dev); 608254559Sian bus_generic_attach(dev); 609254559Sian 610254559Sian sdhci_start_slot(&sc->slot); 611254559Sian 612254559Sian return (0); 613254559Sian 614254559Sianfail: 615254559Sian if (sc->intr_cookie) 616254559Sian bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 617254559Sian if (sc->irq_res) 618254559Sian bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 619254559Sian if (sc->mem_res) 620254559Sian bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 621254559Sian 622254559Sian return (err); 623254559Sian} 624254559Sian 625254559Sianstatic int 626254559Sianti_sdhci_probe(device_t dev) 627254559Sian{ 628254559Sian 629266152Sian if (!ofw_bus_status_okay(dev)) 630266152Sian return (ENXIO); 631266152Sian 632259356Sian if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 633259356Sian device_set_desc(dev, "TI MMCHS (SDHCI 2.0)"); 634259356Sian return (BUS_PROBE_DEFAULT); 635254559Sian } 636254559Sian 637259356Sian return (ENXIO); 638254559Sian} 639254559Sian 640254559Sianstatic device_method_t ti_sdhci_methods[] = { 641254559Sian /* Device interface */ 642254559Sian DEVMETHOD(device_probe, ti_sdhci_probe), 643254559Sian DEVMETHOD(device_attach, ti_sdhci_attach), 644254559Sian DEVMETHOD(device_detach, ti_sdhci_detach), 645254559Sian 646254559Sian /* Bus interface */ 647254559Sian DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 648254559Sian DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 649254559Sian DEVMETHOD(bus_print_child, bus_generic_print_child), 650254559Sian 651254559Sian /* MMC bridge interface */ 652254559Sian DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios), 653254559Sian DEVMETHOD(mmcbr_request, sdhci_generic_request), 654254559Sian DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro), 655254559Sian DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 656254559Sian DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 657254559Sian 658254559Sian /* SDHCI registers accessors */ 659254559Sian DEVMETHOD(sdhci_read_1, ti_sdhci_read_1), 660254559Sian DEVMETHOD(sdhci_read_2, ti_sdhci_read_2), 661254559Sian DEVMETHOD(sdhci_read_4, ti_sdhci_read_4), 662254559Sian DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4), 663254559Sian DEVMETHOD(sdhci_write_1, ti_sdhci_write_1), 664254559Sian DEVMETHOD(sdhci_write_2, ti_sdhci_write_2), 665254559Sian DEVMETHOD(sdhci_write_4, ti_sdhci_write_4), 666254559Sian DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4), 667254559Sian 668254559Sian DEVMETHOD_END 669254559Sian}; 670254559Sian 671254559Sianstatic devclass_t ti_sdhci_devclass; 672254559Sian 673254559Sianstatic driver_t ti_sdhci_driver = { 674254559Sian "sdhci_ti", 675254559Sian ti_sdhci_methods, 676254559Sian sizeof(struct ti_sdhci_softc), 677254559Sian}; 678254559Sian 679254559SianDRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, 0, 0); 680254559SianMODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1); 681