ti_sdhci.c revision 259374
1254559Sian/*- 2254559Sian * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3254559Sian * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 4254559Sian * All rights reserved. 5254559Sian * 6254559Sian * Redistribution and use in source and binary forms, with or without 7254559Sian * modification, are permitted provided that the following conditions 8254559Sian * are met: 9254559Sian * 1. Redistributions of source code must retain the above copyright 10254559Sian * notice, this list of conditions and the following disclaimer. 11254559Sian * 2. Redistributions in binary form must reproduce the above copyright 12254559Sian * notice, this list of conditions and the following disclaimer in the 13254559Sian * documentation and/or other materials provided with the distribution. 14254559Sian * 15254559Sian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16254559Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17254559Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18254559Sian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19254559Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20254559Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21254559Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22254559Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23254559Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24254559Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25254559Sian * SUCH DAMAGE. 26254559Sian * 27254559Sian */ 28254559Sian#include <sys/cdefs.h> 29254559Sian__FBSDID("$FreeBSD: stable/10/sys/arm/ti/ti_sdhci.c 259374 2013-12-14 00:58:13Z ian $"); 30254559Sian 31254559Sian#include <sys/param.h> 32254559Sian#include <sys/systm.h> 33254559Sian#include <sys/bus.h> 34254559Sian#include <sys/gpio.h> 35254559Sian#include <sys/kernel.h> 36254559Sian#include <sys/malloc.h> 37254559Sian#include <sys/module.h> 38254559Sian#include <sys/resource.h> 39254559Sian#include <sys/rman.h> 40254559Sian#include <sys/taskqueue.h> 41254559Sian 42254559Sian#include <machine/bus.h> 43254559Sian#include <machine/resource.h> 44254559Sian#include <machine/intr.h> 45254559Sian 46254559Sian#include <dev/fdt/fdt_common.h> 47254559Sian#include <dev/ofw/ofw_bus.h> 48254559Sian#include <dev/ofw/ofw_bus_subr.h> 49254559Sian 50254559Sian#include <dev/mmc/bridge.h> 51254559Sian#include <dev/mmc/mmcreg.h> 52254559Sian#include <dev/mmc/mmcbrvar.h> 53254559Sian 54254559Sian#include <dev/sdhci/sdhci.h> 55254559Sian#include "sdhci_if.h" 56254559Sian 57254559Sian#include <arm/ti/ti_cpuid.h> 58254559Sian#include <arm/ti/ti_prcm.h> 59254559Sian#include "gpio_if.h" 60254559Sian 61254559Sianstruct ti_sdhci_softc { 62254559Sian device_t dev; 63254559Sian device_t gpio_dev; 64254559Sian struct resource * mem_res; 65254559Sian struct resource * irq_res; 66254559Sian void * intr_cookie; 67254559Sian struct sdhci_slot slot; 68254559Sian uint32_t mmchs_device_id; 69254559Sian uint32_t mmchs_reg_off; 70254559Sian uint32_t sdhci_reg_off; 71254559Sian uint32_t baseclk_hz; 72254559Sian uint32_t wp_gpio_pin; 73254559Sian uint32_t cmd_and_mode; 74254559Sian uint32_t sdhci_clkdiv; 75254559Sian}; 76254559Sian 77254559Sian/* 78259356Sian * Table of supported FDT compat strings. 79259356Sian * 80259356Sian * Note that "ti,mmchs" is our own invention, and should be phased out in favor 81259356Sian * of the documented names. 82259356Sian * 83259356Sian * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x. 84259356Sian */ 85259356Sianstatic struct ofw_compat_data compat_data[] = { 86259356Sian {"ti,omap3-hsmmc", 1}, 87259356Sian {"ti,omap4-hsmmc", 1}, 88259356Sian {"ti,mmchs", 1}, 89259356Sian {NULL, 0}, 90259356Sian}; 91259356Sian 92259356Sian/* 93254559Sian * The MMCHS hardware has a few control and status registers at the beginning of 94254559Sian * the device's memory map, followed by the standard sdhci register block. 95254559Sian * Different SoCs have the register blocks at different offsets from the 96254559Sian * beginning of the device. Define some constants to map out the registers we 97254559Sian * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far 98254559Sian * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs. 99254559Sian */ 100254559Sian#define OMAP3_MMCHS_REG_OFFSET 0x000 101254559Sian#define OMAP4_MMCHS_REG_OFFSET 0x100 102254559Sian#define AM335X_MMCHS_REG_OFFSET 0x100 103254559Sian#define SDHCI_REG_OFFSET 0x100 104254559Sian 105254559Sian#define MMCHS_SYSCONFIG 0x010 106254559Sian#define MMCHS_SYSCONFIG_RESET (1 << 1) 107254559Sian#define MMCHS_SYSSTATUS 0x014 108254559Sian#define MMCHS_CON 0x02C 109254559Sian#define MMCHS_CON_DW8 (1 << 5) 110254559Sian#define MMCHS_CON_DVAL_8_4MS (3 << 9) 111259374Sian#define MMCHS_SD_CAPA 0x140 112259356Sian#define MMCHS_SD_CAPA_VS18 (1 << 26) 113259356Sian#define MMCHS_SD_CAPA_VS30 (1 << 25) 114259356Sian#define MMCHS_SD_CAPA_VS33 (1 << 24) 115254559Sian 116254559Sianstatic inline uint32_t 117254559Sianti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off) 118254559Sian{ 119254559Sian 120254559Sian return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); 121254559Sian} 122254559Sian 123254559Sianstatic inline void 124254559Sianti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 125254559Sian{ 126254559Sian 127254559Sian bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); 128254559Sian} 129254559Sian 130254559Sianstatic inline uint32_t 131254559SianRD4(struct ti_sdhci_softc *sc, bus_size_t off) 132254559Sian{ 133254559Sian 134254559Sian return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off)); 135254559Sian} 136254559Sian 137254559Sianstatic inline void 138254559SianWR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 139254559Sian{ 140254559Sian 141254559Sian bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val); 142254559Sian} 143254559Sian 144254559Sianstatic uint8_t 145254559Sianti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 146254559Sian{ 147254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 148254559Sian 149254559Sian return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 150254559Sian} 151254559Sian 152254559Sianstatic uint16_t 153254559Sianti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 154254559Sian{ 155254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 156254559Sian uint32_t clkdiv, val32; 157254559Sian 158254559Sian /* 159254559Sian * The MMCHS hardware has a non-standard interpretation of the sdclock 160254559Sian * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6) 161254559Sian * but doesn't split them into low:high fields. Instead they're a 162254559Sian * single number in the range 0..1023 and the number is exactly the 163254559Sian * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI 164254559Sian * driver code expects a v2.0 divisor (value N is power of two in the 165254559Sian * range 0..128 and clock is divided by 2N). The shifting and masking 166254559Sian * here extracts the MMCHS representation from the hardware word, cleans 167254559Sian * those bits out, applies the 2N adjustment, and plugs that into the 168254559Sian * bit positions for the 2.0 divisor in the returned register value. The 169254559Sian * ti_sdhci_write_2() routine performs the opposite transformation when 170254559Sian * the SDHCI driver writes to the register. 171254559Sian */ 172254559Sian if (off == SDHCI_CLOCK_CONTROL) { 173254559Sian val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 174254559Sian clkdiv = (val32 >> SDHCI_DIVIDER_HI_SHIFT) & 0xff; 175254559Sian val32 &= ~(0xff << SDHCI_DIVIDER_HI_SHIFT); 176254559Sian val32 |= (clkdiv / 2) << SDHCI_DIVIDER_SHIFT; 177254559Sian return (val32 & 0xffff); 178254559Sian } 179254559Sian 180254559Sian /* 181254559Sian * Standard 32-bit handling of command and transfer mode. 182254559Sian */ 183254559Sian if (off == SDHCI_TRANSFER_MODE) { 184254559Sian return (sc->cmd_and_mode >> 16); 185254559Sian } else if (off == SDHCI_COMMAND_FLAGS) { 186254559Sian return (sc->cmd_and_mode & 0x0000ffff); 187254559Sian } 188254559Sian 189254559Sian return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 190254559Sian} 191254559Sian 192254559Sianstatic uint32_t 193254559Sianti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 194254559Sian{ 195254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 196254559Sian 197254559Sian return (RD4(sc, off)); 198254559Sian} 199254559Sian 200254559Sianstatic void 201254559Sianti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 202254559Sian uint32_t *data, bus_size_t count) 203254559Sian{ 204254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 205254559Sian 206254559Sian bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 207254559Sian} 208254559Sian 209254559Sianstatic void 210254559Sianti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 211254559Sian uint8_t val) 212254559Sian{ 213254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 214254559Sian uint32_t val32; 215254559Sian 216254559Sian val32 = RD4(sc, off & ~3); 217254559Sian val32 &= ~(0xff << (off & 3) * 8); 218254559Sian val32 |= (val << (off & 3) * 8); 219254559Sian 220254559Sian WR4(sc, off & ~3, val32); 221254559Sian} 222254559Sian 223254559Sianstatic void 224254559Sianti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 225254559Sian uint16_t val) 226254559Sian{ 227254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 228254559Sian uint32_t clkdiv, val32; 229254559Sian 230254559Sian /* 231254559Sian * Translate between the hardware and SDHCI 2.0 representations of the 232254559Sian * clock divisor. See the comments in ti_sdhci_read_2() for details. 233254559Sian */ 234254559Sian if (off == SDHCI_CLOCK_CONTROL) { 235254559Sian clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 236254559Sian val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 237254559Sian val32 &= 0xffff0000; 238254559Sian val32 |= val & ~(SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT); 239254559Sian val32 |= (clkdiv * 2) << SDHCI_DIVIDER_HI_SHIFT; 240254559Sian WR4(sc, SDHCI_CLOCK_CONTROL, val32); 241254559Sian return; 242254559Sian } 243254559Sian 244254559Sian /* 245254559Sian * Standard 32-bit handling of command and transfer mode. 246254559Sian */ 247254559Sian if (off == SDHCI_TRANSFER_MODE) { 248254559Sian sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | 249254559Sian ((uint32_t)val & 0x0000ffff); 250254559Sian return; 251254559Sian } else if (off == SDHCI_COMMAND_FLAGS) { 252254559Sian sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) | 253254559Sian ((uint32_t)val << 16); 254254559Sian WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 255254559Sian return; 256254559Sian } 257254559Sian 258254559Sian val32 = RD4(sc, off & ~3); 259254559Sian val32 &= ~(0xffff << (off & 3) * 8); 260254559Sian val32 |= ((val & 0xffff) << (off & 3) * 8); 261254559Sian WR4(sc, off & ~3, val32); 262254559Sian} 263254559Sian 264254559Sianstatic void 265254559Sianti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 266254559Sian uint32_t val) 267254559Sian{ 268254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 269254559Sian 270254559Sian WR4(sc, off, val); 271254559Sian} 272254559Sian 273254559Sianstatic void 274254559Sianti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 275254559Sian uint32_t *data, bus_size_t count) 276254559Sian{ 277254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 278254559Sian 279254559Sian bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 280254559Sian} 281254559Sian 282254559Sianstatic void 283254559Sianti_sdhci_intr(void *arg) 284254559Sian{ 285254559Sian struct ti_sdhci_softc *sc = arg; 286254559Sian 287254559Sian sdhci_generic_intr(&sc->slot); 288254559Sian} 289254559Sian 290254559Sianstatic int 291254559Sianti_sdhci_update_ios(device_t brdev, device_t reqdev) 292254559Sian{ 293254559Sian struct ti_sdhci_softc *sc = device_get_softc(brdev); 294254559Sian struct sdhci_slot *slot; 295254559Sian struct mmc_ios *ios; 296254559Sian uint32_t val32; 297254559Sian 298254559Sian slot = device_get_ivars(reqdev); 299254559Sian ios = &slot->host.ios; 300254559Sian 301254559Sian /* 302254559Sian * There is an 8-bit-bus bit in the MMCHS control register which, when 303254559Sian * set, overrides the 1 vs 4 bit setting in the standard SDHCI 304254559Sian * registers. Set that bit first according to whether an 8-bit bus is 305254559Sian * requested, then let the standard driver handle everything else. 306254559Sian */ 307254559Sian val32 = ti_mmchs_read_4(sc, MMCHS_CON); 308254559Sian if (ios->bus_width == bus_width_8) 309254559Sian ti_mmchs_write_4(sc, MMCHS_CON, val32 | MMCHS_CON_DW8); 310254559Sian else 311254559Sian ti_mmchs_write_4(sc, MMCHS_CON, val32 & ~MMCHS_CON_DW8); 312254559Sian 313254559Sian return (sdhci_generic_update_ios(brdev, reqdev)); 314254559Sian} 315254559Sian 316254559Sianstatic int 317254559Sianti_sdhci_get_ro(device_t brdev, device_t reqdev) 318254559Sian{ 319254559Sian struct ti_sdhci_softc *sc = device_get_softc(brdev); 320254559Sian unsigned int readonly = 0; 321254559Sian 322254559Sian /* If a gpio pin is configured, read it. */ 323254559Sian if (sc->gpio_dev != NULL) { 324254559Sian GPIO_PIN_GET(sc->gpio_dev, sc->wp_gpio_pin, &readonly); 325254559Sian } 326254559Sian 327254559Sian return (readonly); 328254559Sian} 329254559Sian 330254559Sianstatic int 331254559Sianti_sdhci_detach(device_t dev) 332254559Sian{ 333254559Sian 334254559Sian return (EBUSY); 335254559Sian} 336254559Sian 337254559Sianstatic void 338254559Sianti_sdhci_hw_init(device_t dev) 339254559Sian{ 340254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 341254559Sian clk_ident_t clk; 342259356Sian uint32_t regval; 343254559Sian unsigned long timeout; 344254559Sian 345254559Sian /* Enable the controller and interface/functional clocks */ 346254559Sian clk = MMC0_CLK + sc->mmchs_device_id; 347254559Sian if (ti_prcm_clk_enable(clk) != 0) { 348254559Sian device_printf(dev, "Error: failed to enable MMC clock\n"); 349254559Sian return; 350254559Sian } 351254559Sian 352254559Sian /* Get the frequency of the source clock */ 353254559Sian if (ti_prcm_clk_get_source_freq(clk, &sc->baseclk_hz) != 0) { 354254559Sian device_printf(dev, "Error: failed to get source clock freq\n"); 355254559Sian return; 356254559Sian } 357254559Sian 358254559Sian /* Issue a softreset to the controller */ 359254559Sian ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET); 360254559Sian timeout = 1000; 361254559Sian while ((ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & MMCHS_SYSCONFIG_RESET)) { 362254559Sian if (--timeout == 0) { 363254559Sian device_printf(dev, "Error: Controller reset operation timed out\n"); 364254559Sian break; 365254559Sian } 366254559Sian DELAY(100); 367254559Sian } 368254559Sian 369254559Sian /* Reset both the command and data state machines */ 370254559Sian ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); 371254559Sian timeout = 1000; 372254559Sian while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL)) { 373254559Sian if (--timeout == 0) { 374254559Sian device_printf(dev, "Error: Software reset operation timed out\n"); 375254559Sian break; 376254559Sian } 377254559Sian DELAY(100); 378254559Sian } 379254559Sian 380259356Sian /* 381259356Sian * The attach() routine has examined fdt data and set flags in 382259356Sian * slot.host.caps to reflect what voltages we can handle. Set those 383259356Sian * values in the CAPA register. The manual says that these values can 384259356Sian * only be set once, "before initialization" whatever that means, and 385259356Sian * that they survive a reset. So maybe doing this will be a no-op if 386259356Sian * u-boot has already initialized the hardware. 387259356Sian */ 388259356Sian regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA); 389259356Sian if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE) 390259356Sian regval |= MMCHS_SD_CAPA_VS18; 391259356Sian if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310)) 392259356Sian regval |= MMCHS_SD_CAPA_VS30; 393259356Sian ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval); 394259356Sian 395254559Sian /* Set initial host configuration (1-bit, std speed, pwr off). */ 396254559Sian ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0); 397254559Sian ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0); 398254559Sian 399254559Sian /* Set the initial controller configuration. */ 400254559Sian ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS); 401254559Sian} 402254559Sian 403254559Sianstatic int 404254559Sianti_sdhci_attach(device_t dev) 405254559Sian{ 406254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 407254559Sian int rid, err; 408254559Sian pcell_t prop; 409254559Sian phandle_t node; 410254559Sian 411254559Sian sc->dev = dev; 412254559Sian 413254559Sian /* 414254559Sian * Get the MMCHS device id from FDT. If it's not there use the newbus 415254559Sian * unit number (which will work as long as the devices are in order and 416259356Sian * none are skipped in the fdt). Note that this is a property we made 417259356Sian * up and added in freebsd, it doesn't exist in the published bindings. 418254559Sian */ 419254559Sian node = ofw_bus_get_node(dev); 420254559Sian if ((OF_getprop(node, "mmchs-device-id", &prop, sizeof(prop))) <= 0) { 421254559Sian sc->mmchs_device_id = device_get_unit(dev); 422254559Sian device_printf(dev, "missing mmchs-device-id attribute in FDT, " 423254559Sian "using unit number (%d)", sc->mmchs_device_id); 424254559Sian } else 425254559Sian sc->mmchs_device_id = fdt32_to_cpu(prop); 426254559Sian 427259356Sian /* 428259356Sian * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first 429259356Sian * device, and only 1p8v on other devices unless an external transceiver 430259356Sian * is used. The only way we could know about a transceiver is fdt data. 431259356Sian * Note that we have to do this before calling ti_sdhci_hw_init() so 432259356Sian * that it can set the right values in the CAPA register, which can only 433259356Sian * be done once and never reset. 434259356Sian */ 435259374Sian sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE; 436259356Sian if (sc->mmchs_device_id == 0 || OF_hasprop(node, "ti,dual-volt")) { 437259374Sian sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310; 438259356Sian } 439259356Sian 440259356Sian /* 441259356Sian * See if we've got a GPIO-based write detect pin. This is not the 442259356Sian * standard documented property for this, we added it in freebsd. 443259356Sian */ 444254559Sian if ((OF_getprop(node, "mmchs-wp-gpio-pin", &prop, sizeof(prop))) <= 0) 445254559Sian sc->wp_gpio_pin = 0xffffffff; 446254559Sian else 447254559Sian sc->wp_gpio_pin = fdt32_to_cpu(prop); 448254559Sian 449254559Sian if (sc->wp_gpio_pin != 0xffffffff) { 450254559Sian sc->gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 451254559Sian if (sc->gpio_dev == NULL) 452254559Sian device_printf(dev, "Error: No GPIO device, " 453254559Sian "Write Protect pin will not function\n"); 454254559Sian else 455254559Sian GPIO_PIN_SETFLAGS(sc->gpio_dev, sc->wp_gpio_pin, 456254559Sian GPIO_PIN_INPUT); 457254559Sian } 458254559Sian 459254559Sian /* 460254559Sian * Set the offset from the device's memory start to the MMCHS registers. 461254559Sian */ 462254559Sian if (ti_chip() == CHIP_OMAP_3) 463254559Sian sc->mmchs_reg_off = OMAP3_MMCHS_REG_OFFSET; 464254559Sian else if (ti_chip() == CHIP_OMAP_4) 465254559Sian sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET; 466254559Sian else if (ti_chip() == CHIP_AM335X) 467254559Sian sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET; 468254559Sian else 469254559Sian panic("Unknown OMAP device\n"); 470254559Sian 471254559Sian /* 472254559Sian * The standard SDHCI registers are at a fixed offset (the same on all 473254559Sian * SoCs) beyond the MMCHS registers. 474254559Sian */ 475254559Sian sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET; 476254559Sian 477254559Sian /* Resource setup. */ 478254559Sian rid = 0; 479254559Sian sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 480254559Sian RF_ACTIVE); 481254559Sian if (!sc->mem_res) { 482254559Sian device_printf(dev, "cannot allocate memory window\n"); 483254559Sian err = ENXIO; 484254559Sian goto fail; 485254559Sian } 486254559Sian 487254559Sian rid = 0; 488254559Sian sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 489254559Sian RF_ACTIVE); 490254559Sian if (!sc->irq_res) { 491254559Sian device_printf(dev, "cannot allocate interrupt\n"); 492254559Sian err = ENXIO; 493254559Sian goto fail; 494254559Sian } 495254559Sian 496254559Sian if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 497254559Sian NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) { 498254559Sian device_printf(dev, "cannot setup interrupt handler\n"); 499254559Sian err = ENXIO; 500254559Sian goto fail; 501254559Sian } 502254559Sian 503254559Sian /* Initialise the MMCHS hardware. */ 504254559Sian ti_sdhci_hw_init(dev); 505254559Sian 506254559Sian /* 507254559Sian * The capabilities register can only express base clock frequencies in 508254559Sian * the range of 0-63MHz for a v2.0 controller. Since our clock runs 509254559Sian * faster than that, the hardware sets the frequency to zero in the 510254559Sian * register. When the register contains zero, the sdhci driver expects 511254559Sian * slot.max_clk to already have the right value in it. 512254559Sian */ 513254559Sian sc->slot.max_clk = sc->baseclk_hz; 514254559Sian 515254559Sian /* 516254559Sian * The MMCHS timeout counter is based on the output sdclock. Tell the 517254559Sian * sdhci driver to recalculate the timeout clock whenever the output 518254559Sian * sdclock frequency changes. 519254559Sian */ 520254559Sian sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 521254559Sian 522254559Sian /* 523254559Sian * The MMCHS hardware shifts the 136-bit response data (in violation of 524254559Sian * the spec), so tell the sdhci driver not to do the same in software. 525254559Sian */ 526254559Sian sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE; 527254559Sian 528254559Sian /* 529254559Sian * DMA is not really broken, I just haven't implemented it yet. 530254559Sian */ 531254559Sian sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 532254559Sian 533259356Sian /* 534259356Sian * Set up the hardware and go. Note that this sets many of the 535259356Sian * slot.host.* fields, so we have to do this before overriding any of 536259356Sian * those values based on fdt data, below. 537259356Sian */ 538254559Sian sdhci_init_slot(dev, &sc->slot, 0); 539254559Sian 540254559Sian /* 541259356Sian * The SDHCI controller doesn't realize it, but we can support 8-bit 542259356Sian * even though we're not a v3.0 controller. If there's an fdt bus-width 543259356Sian * property, honor it. 544254559Sian */ 545259356Sian if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { 546259356Sian sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | 547259356Sian MMC_CAP_8_BIT_DATA); 548259356Sian switch (prop) { 549259356Sian case 8: 550259356Sian sc->slot.host.caps |= MMC_CAP_8_BIT_DATA; 551259356Sian /* FALLTHROUGH */ 552259356Sian case 4: 553259356Sian sc->slot.host.caps |= MMC_CAP_4_BIT_DATA; 554259356Sian break; 555259356Sian case 1: 556259356Sian break; 557259356Sian default: 558259356Sian device_printf(dev, "Bad bus-width value %u\n", prop); 559259356Sian break; 560259356Sian } 561259356Sian } 562254559Sian 563254559Sian bus_generic_probe(dev); 564254559Sian bus_generic_attach(dev); 565254559Sian 566254559Sian sdhci_start_slot(&sc->slot); 567254559Sian 568254559Sian return (0); 569254559Sian 570254559Sianfail: 571254559Sian if (sc->intr_cookie) 572254559Sian bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 573254559Sian if (sc->irq_res) 574254559Sian bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 575254559Sian if (sc->mem_res) 576254559Sian bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 577254559Sian 578254559Sian return (err); 579254559Sian} 580254559Sian 581254559Sianstatic int 582254559Sianti_sdhci_probe(device_t dev) 583254559Sian{ 584254559Sian 585259356Sian if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 586259356Sian device_set_desc(dev, "TI MMCHS (SDHCI 2.0)"); 587259356Sian return (BUS_PROBE_DEFAULT); 588254559Sian } 589254559Sian 590259356Sian return (ENXIO); 591254559Sian} 592254559Sian 593254559Sianstatic device_method_t ti_sdhci_methods[] = { 594254559Sian /* Device interface */ 595254559Sian DEVMETHOD(device_probe, ti_sdhci_probe), 596254559Sian DEVMETHOD(device_attach, ti_sdhci_attach), 597254559Sian DEVMETHOD(device_detach, ti_sdhci_detach), 598254559Sian 599254559Sian /* Bus interface */ 600254559Sian DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 601254559Sian DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 602254559Sian DEVMETHOD(bus_print_child, bus_generic_print_child), 603254559Sian 604254559Sian /* MMC bridge interface */ 605254559Sian DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios), 606254559Sian DEVMETHOD(mmcbr_request, sdhci_generic_request), 607254559Sian DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro), 608254559Sian DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 609254559Sian DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 610254559Sian 611254559Sian /* SDHCI registers accessors */ 612254559Sian DEVMETHOD(sdhci_read_1, ti_sdhci_read_1), 613254559Sian DEVMETHOD(sdhci_read_2, ti_sdhci_read_2), 614254559Sian DEVMETHOD(sdhci_read_4, ti_sdhci_read_4), 615254559Sian DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4), 616254559Sian DEVMETHOD(sdhci_write_1, ti_sdhci_write_1), 617254559Sian DEVMETHOD(sdhci_write_2, ti_sdhci_write_2), 618254559Sian DEVMETHOD(sdhci_write_4, ti_sdhci_write_4), 619254559Sian DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4), 620254559Sian 621254559Sian DEVMETHOD_END 622254559Sian}; 623254559Sian 624254559Sianstatic devclass_t ti_sdhci_devclass; 625254559Sian 626254559Sianstatic driver_t ti_sdhci_driver = { 627254559Sian "sdhci_ti", 628254559Sian ti_sdhci_methods, 629254559Sian sizeof(struct ti_sdhci_softc), 630254559Sian}; 631254559Sian 632254559SianDRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, 0, 0); 633254559SianMODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1); 634