1205354Simp/*- 2205354Simp * Copyright (C) 2009 Andrew Turner 3205354Simp * All rights reserved. 4205354Simp * 5205354Simp * Redistribution and use in source and binary forms, with or without 6205354Simp * modification, are permitted provided that the following conditions 7205354Simp * are met: 8205354Simp * 1. Redistributions of source code must retain the above copyright 9205354Simp * notice, this list of conditions and the following disclaimer. 10205354Simp * 2. Redistributions in binary form must reproduce the above copyright 11205354Simp * notice, this list of conditions and the following disclaimer in the 12205354Simp * documentation and/or other materials provided with the distribution. 13205354Simp * 14205354Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15205354Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16205354Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17205354Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18205354Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19205354Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20205354Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21205354Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22205354Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23205354Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24205354Simp * SUCH DAMAGE. 25205354Simp * 26205354Simp * $FreeBSD$ 27205354Simp */ 28205354Simp 29205354Simp/* 30205354Simp * Samsung S3C2440X processor is ARM920T based integrated CPU 31205354Simp * 32205354Simp * Reference: 33236990Simp * S3C2440A/S3C2442B User's Manual 34205354Simp */ 35205354Simp#ifndef _ARM_S3C2XX0_S3C2440REG_H_ 36205354Simp#define _ARM_S3C2XX0_S3C2440REG_H_ 37205354Simp 38205354Simp/* common definitions for S3C2410 and S3C2440 */ 39272103Sgavin#include <arm/samsung/s3c2xx0/s3c24x0reg.h> 40205354Simp 41205354Simp/* 42205354Simp * Memory Map 43205354Simp */ 44205354Simp#define S3C2440_BANK_SIZE 0x08000000 45205354Simp#define S3C2440_BANK_START(n) (S3C2410_BANK_SIZE*(n)) 46205354Simp#define S3C2440_SDRAM_START S3C2410_BANK_START(6) 47205354Simp 48205354Simp 49205354Simp/* interrupt control */ 50205354Simp#define S3C2440_SUBIRQ_MAX (S3C24X0_SUBIRQ_MIN+10) 51205354Simp 52205354Simp/* Clock control */ 53205354Simp/* CLKMAN_CLKCON */ 54205354Simp#define S3C2440_CLKCON_STOP (1<<0) /* 1=transition to STOP mode */ 55205354Simp/* CLKMAN_CLKDIVN */ 56205354Simp#define S3C2440_CLKDIVN_HDIVN (3<<1) /* hclk */ 57205354Simp#define S3C2440_CLKMAN_CAMDIVN 0x18 58205354Simp#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) 59205354Simp#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8) 60205354Simp 61205354Simp/* NAND Flash controller */ 62205354Simp#define S3C2440_NANDFC_SIZE 0x40 63205354Simp 64205354Simp#define S3C2440_NANDFC_NFCONT 0x04 65205354Simp#define S3C2440_NFCONT_LOCK_TIGHT (1<<13) /* Lock part of the NAND */ 66205354Simp#define S3C2440_NFCONT_SOFT_LOCK (1<<12) /* Soft lock part of the NAND */ 67205354Simp#define S3C2440_NFCONT_ILLEGAL_ACC_INT (1<<10) /* Illegal access interrupt */ 68205354Simp#define S3C2440_NFCONT_RNB_INT (1<<9) /* RnB transition interrupt */ 69205354Simp#define S3C2440_NFCONT_RNB_TRANS_MODE (1<<8) /* RnB transition mode */ 70205354Simp#define S3C2440_NFCONT_SPARE_ECC_LOCK (1<<6) /* Lock spare ECC generation */ 71205354Simp#define S3C2440_NFCONT_MAIN_ECC_LOCK (1<<5) /* Lock main ECC generation */ 72205354Simp#define S3C2440_NFCONT_INIT_ECC (1<<4) /* Init ECC encoder/decoder */ 73205354Simp#define S3C2440_NFCONT_NCE (1<<1) /* NAND Chip select */ 74205354Simp#define S3C2440_NFCONT_ENABLE (1<<0) /* Enable the controller */ 75205354Simp#define S3C2440_NANDFC_NFCMMD 0x08 76205354Simp#define S3C2440_NANDFC_NFADDR 0x0c 77205354Simp#define S3C2440_NANDFC_NFDATA 0x10 78205354Simp#define S3C2440_NANDFC_NFSTAT 0x20 79205354Simp 80205354Simp/* MMC/SD */ 81205354Simp/* SDI_CON */ 82205354Simp#define S3C2440_CON_RESET (1<<8) 83205354Simp#define S3C2440_CON_CLOCK_TYPE (1<<5) 84205354Simp/* SDI_FSTA */ 85205354Simp#define S3c2440_FSTA_RESET (1<<16) 86205354Simp#define S3C2440_FSTA_FAIL_ERROR_MSK (3<<14) 87205354Simp#define S3C2440_FSTA_FAIL_NONE (0<<14) 88205354Simp#define S3C2440_FSTA_FAIL_FIFO (1<<14) 89205354Simp#define S3C2440_FSTA_FAIL_LAST_TRANS (2<<14) 90205354Simp 91205354Simp/* GPIO */ 92205354Simp#define S3C2440_GPIO_SIZE 0xd0 93205354Simp 94205354Simp/* SD interface */ 95205354Simp#define S3C2410_SDI_SIZE 0x44 96205354Simp#define DCON_START (1<<14) /* Start the data transfer */ 97205354Simp#define S3C2440_SDI_IMSK 0x3c /* Interrupt mask */ 98205354Simp#define S3C2440_SDI_IMASK_ALL 0x3C7C0 99205354Simp#define S3C2440_SDI_DAT 0x40 100205354Simp 101205354Simp/* ADC */ 102205354Simp#define ADCTSC_UD_SEN (1<<8) 103205354Simp#define S3C2440_ADC_SIZE 0x18 104205354Simp 105205354Simp/* UART */ 106205354Simp#define S3C2440_UFSTAT_TXCOUNT (0x3f << 8) 107205354Simp#define S3C2440_UFSTAT_RXCOUNT (0x3f << 0) 108205354Simp 109205354Simp#endif /* _ARM_S3C2XX0_S3C2440REG_H_ */ 110