mv_machdep.c revision 259364
1/*- 2 * Copyright (c) 1994-1998 Mark Brinicombe. 3 * Copyright (c) 1994 Brini. 4 * All rights reserved. 5 * 6 * This code is derived from software written for Brini by Mark Brinicombe 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 36 */ 37 38#include "opt_ddb.h" 39#include "opt_platform.h" 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: stable/10/sys/arm/mv/mv_machdep.c 259364 2013-12-13 23:56:53Z ian $"); 43 44#define _ARM32_BUS_DMA_PRIVATE 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48 49#include <vm/vm.h> 50#include <vm/pmap.h> 51 52#include <machine/bus.h> 53#include <machine/devmap.h> 54#include <machine/machdep.h> 55 56#include <arm/mv/mvreg.h> /* XXX */ 57#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */ 58#include <arm/mv/mvwin.h> 59 60#include <dev/fdt/fdt_common.h> 61 62static int platform_mpp_init(void); 63#if defined(SOC_MV_ARMADAXP) 64void armadaxp_init_coher_fabric(void); 65void armadaxp_l2_init(void); 66#endif 67 68#define MPP_PIN_MAX 68 69#define MPP_PIN_CELLS 2 70#define MPP_PINS_PER_REG 8 71#define MPP_SEL(pin,func) (((func) & 0xf) << \ 72 (((pin) % MPP_PINS_PER_REG) * 4)) 73 74static int 75platform_mpp_init(void) 76{ 77 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 78 int mpp[MPP_PIN_MAX]; 79 uint32_t ctrl_val, ctrl_offset; 80 pcell_t reg[4]; 81 u_long start, size; 82 phandle_t node; 83 pcell_t pin_cells, *pinmap_ptr, pin_count; 84 ssize_t len; 85 int par_addr_cells, par_size_cells; 86 int tuple_size, tuples, rv, pins, i, j; 87 int mpp_pin, mpp_function; 88 89 /* 90 * Try to access the MPP node directly i.e. through /aliases/mpp. 91 */ 92 if ((node = OF_finddevice("mpp")) != -1) 93 if (fdt_is_compatible(node, "mrvl,mpp")) 94 goto moveon; 95 /* 96 * Find the node the long way. 97 */ 98 if ((node = OF_finddevice("/")) == -1) 99 return (ENXIO); 100 101 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 102 return (ENXIO); 103 104 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 105 /* 106 * No MPP node. Fall back to how MPP got set by the 107 * first-stage loader and try to continue booting. 108 */ 109 return (0); 110moveon: 111 /* 112 * Process 'reg' prop. 113 */ 114 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 115 &par_size_cells)) != 0) 116 return(ENXIO); 117 118 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 119 len = OF_getprop(node, "reg", reg, sizeof(reg)); 120 tuples = len / tuple_size; 121 if (tuple_size <= 0) 122 return (EINVAL); 123 124 /* 125 * Get address/size. XXX we assume only the first 'reg' tuple is used. 126 */ 127 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 128 &start, &size); 129 if (rv != 0) 130 return (rv); 131 start += fdt_immr_va; 132 133 /* 134 * Process 'pin-count' and 'pin-map' props. 135 */ 136 if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 137 return (ENXIO); 138 pin_count = fdt32_to_cpu(pin_count); 139 if (pin_count > MPP_PIN_MAX) 140 return (ERANGE); 141 142 if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 143 pin_cells = MPP_PIN_CELLS; 144 pin_cells = fdt32_to_cpu(pin_cells); 145 if (pin_cells > MPP_PIN_CELLS) 146 return (ERANGE); 147 tuple_size = sizeof(pcell_t) * pin_cells; 148 149 bzero(pinmap, sizeof(pinmap)); 150 len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap)); 151 if (len <= 0) 152 return (ERANGE); 153 if (len % tuple_size) 154 return (ERANGE); 155 pins = len / tuple_size; 156 if (pins > pin_count) 157 return (ERANGE); 158 /* 159 * Fill out a "mpp[pin] => function" table. All pins unspecified in 160 * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 161 */ 162 bzero(mpp, sizeof(mpp)); 163 pinmap_ptr = pinmap; 164 for (i = 0; i < pins; i++) { 165 mpp_pin = fdt32_to_cpu(*pinmap_ptr); 166 mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1)); 167 mpp[mpp_pin] = mpp_function; 168 pinmap_ptr += pin_cells; 169 } 170 171 /* 172 * Prepare and program MPP control register values. 173 */ 174 ctrl_offset = 0; 175 for (i = 0; i < pin_count;) { 176 ctrl_val = 0; 177 178 for (j = 0; j < MPP_PINS_PER_REG; j++) { 179 if (i + j == pin_count - 1) 180 break; 181 ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 182 } 183 i += MPP_PINS_PER_REG; 184 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 185 ctrl_val); 186 187#if defined(SOC_MV_ORION) 188 /* 189 * Third MPP reg on Orion SoC is placed 190 * non-linearly (with different offset). 191 */ 192 if (i == (2 * MPP_PINS_PER_REG)) 193 ctrl_offset = 0x50; 194 else 195#endif 196 ctrl_offset += 4; 197 } 198 199 return (0); 200} 201 202vm_offset_t 203initarm_lastaddr(void) 204{ 205 206 if (fdt_immr_addr(MV_BASE) != 0) 207 while (1); 208 209 /* Platform-specific initialisation */ 210 return (fdt_immr_va); 211} 212 213void 214initarm_gpio_init(void) 215{ 216 217 /* 218 * Re-initialise MPP. It is important to call this prior to using 219 * console as the physical connection can be routed via MPP. 220 */ 221 if (platform_mpp_init() != 0) 222 while (1); 223} 224 225void 226initarm_late_init(void) 227{ 228 /* 229 * Re-initialise decode windows 230 */ 231#if !defined(SOC_MV_FREY) 232 if (soc_decode_win() != 0) 233 printf("WARNING: could not re-initialise decode windows! " 234 "Running with existing settings...\n"); 235#else 236 /* Disable watchdog and timers */ 237 write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0); 238#endif 239#if defined(SOC_MV_ARMADAXP) 240#if !defined(SMP) 241 /* For SMP case it should be initialized after APs are booted */ 242 armadaxp_init_coher_fabric(); 243#endif 244 armadaxp_l2_init(); 245#endif 246} 247 248#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2) 249static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = { 250 { 0, 0, 0, 0, 0, } 251}; 252 253static int 254platform_sram_devmap(struct arm_devmap_entry *map) 255{ 256#if !defined(SOC_MV_ARMADAXP) 257 phandle_t child, root; 258 u_long base, size; 259 /* 260 * SRAM range. 261 */ 262 if ((child = OF_finddevice("/sram")) != 0) 263 if (fdt_is_compatible(child, "mrvl,cesa-sram") || 264 fdt_is_compatible(child, "mrvl,scratchpad")) 265 goto moveon; 266 267 if ((root = OF_finddevice("/")) == 0) 268 return (ENXIO); 269 270 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 && 271 (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0) 272 goto out; 273 274moveon: 275 if (fdt_regsize(child, &base, &size) != 0) 276 return (EINVAL); 277 278 map->pd_va = MV_CESA_SRAM_BASE; /* XXX */ 279 map->pd_pa = base; 280 map->pd_size = size; 281 map->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 282 map->pd_cache = PTE_NOCACHE; 283 284 return (0); 285out: 286#endif 287 return (ENOENT); 288 289} 290 291/* 292 * Supply a default do-nothing implementation of fdt_pci_devmap() via a weak 293 * alias. Many Marvell platforms don't support a PCI interface, but to support 294 * those that do, we end up with a reference to this function below, in 295 * platform_devmap_init(). If "device pci" appears in the kernel config, the 296 * real implementation of this function in dev/fdt/fdt_pci.c overrides the weak 297 * alias defined here. 298 */ 299int mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, 300 vm_offset_t io_va, vm_offset_t mem_va); 301int 302mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, 303 vm_offset_t io_va, vm_offset_t mem_va) 304{ 305 306 return (0); 307} 308__weak_reference(mv_default_fdt_pci_devmap, fdt_pci_devmap); 309 310/* 311 * XXX: When device entry in devmap has pd_size smaller than section size, 312 * system will freeze during initialization 313 */ 314 315/* 316 * Construct pmap_devmap[] with DT-derived config data. 317 */ 318int 319platform_devmap_init(void) 320{ 321 phandle_t root, child; 322 pcell_t bank_count; 323 int i, num_mapped; 324 325 i = 0; 326 arm_devmap_register_table(&fdt_devmap[0]); 327 328 /* 329 * IMMR range. 330 */ 331 fdt_devmap[i].pd_va = fdt_immr_va; 332 fdt_devmap[i].pd_pa = fdt_immr_pa; 333 fdt_devmap[i].pd_size = fdt_immr_size; 334 fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; 335 fdt_devmap[i].pd_cache = PTE_NOCACHE; 336 i++; 337 338 /* 339 * SRAM range. 340 */ 341 if (i < FDT_DEVMAP_MAX) 342 if (platform_sram_devmap(&fdt_devmap[i]) == 0) 343 i++; 344 345 /* 346 * PCI range(s). 347 * PCI range(s) and localbus. 348 */ 349 if ((root = OF_finddevice("/")) == -1) 350 return (ENXIO); 351 for (child = OF_child(root); child != 0; child = OF_peer(child)) { 352 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) { 353 /* 354 * Check space: each PCI node will consume 2 devmap 355 * entries. 356 */ 357 if (i + 1 >= FDT_DEVMAP_MAX) 358 return (ENOMEM); 359 360 /* 361 * XXX this should account for PCI and multiple ranges 362 * of a given kind. 363 */ 364 if (fdt_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, 365 MV_PCI_VA_MEM_BASE) != 0) 366 return (ENXIO); 367 i += 2; 368 } 369 370 if (fdt_is_compatible(child, "mrvl,lbc")) { 371 /* Check available space */ 372 if (OF_getprop(child, "bank-count", (void *)&bank_count, 373 sizeof(bank_count)) <= 0) 374 /* If no property, use default value */ 375 bank_count = 1; 376 else 377 bank_count = fdt32_to_cpu(bank_count); 378 379 if ((i + bank_count) >= FDT_DEVMAP_MAX) 380 return (ENOMEM); 381 382 /* Add all localbus ranges to device map */ 383 num_mapped = 0; 384 385 if (fdt_localbus_devmap(child, &fdt_devmap[i], 386 (int)bank_count, &num_mapped) != 0) 387 return (ENXIO); 388 389 i += num_mapped; 390 } 391 } 392 393 return (0); 394} 395 396struct arm32_dma_range * 397bus_dma_get_range(void) 398{ 399 400 return (NULL); 401} 402 403int 404bus_dma_get_range_nb(void) 405{ 406 407 return (0); 408} 409 410#if defined(CPU_MV_PJ4B) 411#ifdef DDB 412#include <ddb/ddb.h> 413 414DB_SHOW_COMMAND(cp15, db_show_cp15) 415{ 416 u_int reg; 417 418 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg)); 419 db_printf("Cpu ID: 0x%08x\n", reg); 420 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg)); 421 db_printf("Current Cache Lvl ID: 0x%08x\n",reg); 422 423 __asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg)); 424 db_printf("Ctrl: 0x%08x\n",reg); 425 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg)); 426 db_printf("Aux Ctrl: 0x%08x\n",reg); 427 428 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg)); 429 db_printf("Processor Feat 0: 0x%08x\n", reg); 430 __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg)); 431 db_printf("Processor Feat 1: 0x%08x\n", reg); 432 __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg)); 433 db_printf("Debug Feat 0: 0x%08x\n", reg); 434 __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg)); 435 db_printf("Auxiliary Feat 0: 0x%08x\n", reg); 436 __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg)); 437 db_printf("Memory Model Feat 0: 0x%08x\n", reg); 438 __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg)); 439 db_printf("Memory Model Feat 1: 0x%08x\n", reg); 440 __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg)); 441 db_printf("Memory Model Feat 2: 0x%08x\n", reg); 442 __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg)); 443 db_printf("Memory Model Feat 3: 0x%08x\n", reg); 444 445 __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg)); 446 db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg); 447 __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg)); 448 db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg); 449 450 __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg)); 451 db_printf("CPU ID code extension: 0x%08x\n",reg); 452} 453 454DB_SHOW_COMMAND(vtop, db_show_vtop) 455{ 456 u_int reg; 457 458 if (have_addr) { 459 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr)); 460 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg)); 461 db_printf("Physical address reg: 0x%08x\n",reg); 462 } else 463 db_printf("show vtop <virt_addr>\n"); 464} 465#endif /* DDB */ 466#endif /* CPU_MV_PJ4B */ 467 468