armreg.h revision 266311
1/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * $FreeBSD: stable/10/sys/arm/include/armreg.h 266311 2014-05-17 13:53:38Z ian $ 39 */ 40 41#ifndef MACHINE_ARMREG_H 42#define MACHINE_ARMREG_H 43 44#define INSN_SIZE 4 45#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 46#define PSR_MODE 0x0000001f /* mode mask */ 47#define PSR_USR26_MODE 0x00000000 48#define PSR_FIQ26_MODE 0x00000001 49#define PSR_IRQ26_MODE 0x00000002 50#define PSR_SVC26_MODE 0x00000003 51#define PSR_USR32_MODE 0x00000010 52#define PSR_FIQ32_MODE 0x00000011 53#define PSR_IRQ32_MODE 0x00000012 54#define PSR_SVC32_MODE 0x00000013 55#define PSR_ABT32_MODE 0x00000017 56#define PSR_UND32_MODE 0x0000001b 57#define PSR_SYS32_MODE 0x0000001f 58#define PSR_32_MODE 0x00000010 59#define PSR_FLAGS 0xf0000000 /* flags */ 60 61#define PSR_C_bit (1 << 29) /* carry */ 62 63/* The high-order byte is always the implementor */ 64#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 65#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 66#define CPU_ID_DEC 0x44000000 /* 'D' */ 67#define CPU_ID_INTEL 0x69000000 /* 'i' */ 68#define CPU_ID_TI 0x54000000 /* 'T' */ 69#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 70 71/* How to decide what format the CPUID is in. */ 72#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 73#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 74#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 75 76/* On recent ARMs this byte holds the architecture and variant (sub-model) */ 77#define CPU_ID_ARCH_MASK 0x000f0000 78#define CPU_ID_ARCH_V3 0x00000000 79#define CPU_ID_ARCH_V4 0x00010000 80#define CPU_ID_ARCH_V4T 0x00020000 81#define CPU_ID_ARCH_V5 0x00030000 82#define CPU_ID_ARCH_V5T 0x00040000 83#define CPU_ID_ARCH_V5TE 0x00050000 84#define CPU_ID_ARCH_V5TEJ 0x00060000 85#define CPU_ID_ARCH_V6 0x00070000 86#define CPU_ID_CPUID_SCHEME 0x000f0000 87#define CPU_ID_VARIANT_MASK 0x00f00000 88 89/* Next three nybbles are part number */ 90#define CPU_ID_PARTNO_MASK 0x0000fff0 91 92/* Intel XScale has sub fields in part number */ 93#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 94#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 95#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 96 97/* And finally, the revision number. */ 98#define CPU_ID_REVISION_MASK 0x0000000f 99 100/* Individual CPUs are probably best IDed by everything but the revision. */ 101#define CPU_ID_CPU_MASK 0xfffffff0 102 103/* ARM9 and later CPUs */ 104#define CPU_ID_ARM920T 0x41129200 105#define CPU_ID_ARM920T_ALT 0x41009200 106#define CPU_ID_ARM922T 0x41029220 107#define CPU_ID_ARM926EJS 0x41069260 108#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 109#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 110#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 111#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 112#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 113#define CPU_ID_ARM1022ES 0x4105a220 114#define CPU_ID_ARM1026EJS 0x4106a260 115#define CPU_ID_ARM1136JS 0x4107b360 116#define CPU_ID_ARM1136JSR1 0x4117b360 117#define CPU_ID_ARM1176JZS 0x410fb760 118#define CPU_ID_CORTEXA7 0x410fc070 119#define CPU_ID_CORTEXA8R1 0x411fc080 120#define CPU_ID_CORTEXA8R2 0x412fc080 121#define CPU_ID_CORTEXA8R3 0x413fc080 122#define CPU_ID_CORTEXA9R1 0x411fc090 123#define CPU_ID_CORTEXA9R2 0x412fc090 124#define CPU_ID_CORTEXA9R3 0x413fc090 125#define CPU_ID_CORTEXA15 0x410fc0f0 126#define CPU_ID_KRAIT 0x510f06f0 /* Snapdragon S4 Pro/APQ8064 */ 127#define CPU_ID_TI925T 0x54029250 128#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 129#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ 130#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 131 132/* 133 * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported 134 * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID. 135 */ 136#ifdef SOC_MV_LOKIPLUS 137#define CPU_ID_MV88FR571_41 0x00000000 138#else 139#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ 140#endif 141 142#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ 143#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ 144/* Marvell's CPUIDs with ARM ID in implementor field */ 145#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ 146 147#define CPU_ID_FA526 0x66015260 148#define CPU_ID_FA626TE 0x66056260 149#define CPU_ID_80200 0x69052000 150#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 151#define CPU_ID_PXA210 0x69052120 152#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 153#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 154#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 155#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 156#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 157#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 158#define CPU_ID_PXA27X 0x69054110 159#define CPU_ID_80321_400 0x69052420 160#define CPU_ID_80321_600 0x69052430 161#define CPU_ID_80321_400_B0 0x69052c20 162#define CPU_ID_80321_600_B0 0x69052c30 163#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 164#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 165#define CPU_ID_81342 0x69056810 166#define CPU_ID_IXP425 0x690541c0 167#define CPU_ID_IXP425_533 0x690541c0 168#define CPU_ID_IXP425_400 0x690541d0 169#define CPU_ID_IXP425_266 0x690541f0 170#define CPU_ID_IXP435 0x69054040 171#define CPU_ID_IXP465 0x69054200 172 173/* CPUID registers */ 174#define ARM_PFR0_ARM_ISA_MASK 0x0000000f 175 176#define ARM_PFR0_THUMB_MASK 0x000000f0 177#define ARM_PFR0_THUMB 0x10 178#define ARM_PFR0_THUMB2 0x30 179 180#define ARM_PFR0_JAZELLE_MASK 0x00000f00 181#define ARM_PFR0_THUMBEE_MASK 0x0000f000 182 183#define ARM_PFR1_ARMV4_MASK 0x0000000f 184#define ARM_PFR1_SEC_EXT_MASK 0x000000f0 185#define ARM_PFR1_MICROCTRL_MASK 0x00000f00 186 187/* 188 * Post-ARM3 CP15 registers: 189 * 190 * 1 Control register 191 * 192 * 2 Translation Table Base 193 * 194 * 3 Domain Access Control 195 * 196 * 4 Reserved 197 * 198 * 5 Fault Status 199 * 200 * 6 Fault Address 201 * 202 * 7 Cache/write-buffer Control 203 * 204 * 8 TLB Control 205 * 206 * 9 Cache Lockdown 207 * 208 * 10 TLB Lockdown 209 * 210 * 11 Reserved 211 * 212 * 12 Reserved 213 * 214 * 13 Process ID (for FCSE) 215 * 216 * 14 Reserved 217 * 218 * 15 Implementation Dependent 219 */ 220 221/* Some of the definitions below need cleaning up for V3/V4 architectures */ 222 223/* CPU control register (CP15 register 1) */ 224#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 225#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 226#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 227#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 228#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 229#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 230#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 231#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 232#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 233#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 234#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 235#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 236#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 237#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 238#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 239#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 240#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 241#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 242#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ 243#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ 244#define CPU_CONTROL_AF_ENABLE 0x20000000 /* Access Flag enable */ 245 246#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 247 248/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 249#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 250#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 251#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 252#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 253#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 254#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 255#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 256#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 257 258/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 259#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 260 /* This is an undocumented flag 261 * used to work around a cache bug 262 * in r0 steppings. See errata 263 * 364296. 264 */ 265/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 266#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 267#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 268#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 269#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 270 271/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 272#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 273#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 274/* Note: XSCale core 3 uses those for LLR DCcahce attributes */ 275#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 276#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 277#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 278#define XSCALE_AUXCTL_MD_MASK 0x00000030 279 280/* Xscale Core 3 only */ 281#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ 282 283/* Marvell Extra Features Register (CP15 register 1, opcode2 0) */ 284#define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */ 285#define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */ 286#define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */ 287#define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */ 288#define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 289#define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */ 290#define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */ 291#define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */ 292#define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */ 293#define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */ 294 295/* Cache type register definitions */ 296#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 297#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 298#define CPU_CT_S (1U << 24) /* split cache */ 299#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 300#define CPU_CT_FORMAT(x) ((x) >> 29) 301 302#define CPU_CT_CTYPE_WT 0 /* write-through */ 303#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 304#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 305#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 306#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 307 308#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 309#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 310#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 311#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 312 313#define CPU_CT_ARMV7 0x4 314/* ARM v7 Cache type definitions */ 315#define CPUV7_CT_CTYPE_WT (1U << 31) 316#define CPUV7_CT_CTYPE_WB (1 << 30) 317#define CPUV7_CT_CTYPE_RA (1 << 29) 318#define CPUV7_CT_CTYPE_WA (1 << 28) 319 320#define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */ 321#define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */ 322#define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */ 323 324#define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7) 325#define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7) 326#define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7) 327#define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7) 328 329#define CACHE_ICACHE 1 330#define CACHE_DCACHE 2 331#define CACHE_SEP_CACHE 3 332#define CACHE_UNI_CACHE 4 333 334/* Fault status register definitions */ 335 336#define FAULT_TYPE_MASK 0x0f 337#define FAULT_USER 0x10 338 339#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 340#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 341#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 342#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 343#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 344#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 345#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 346#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 347#define FAULT_ALIGN_0 0x01 /* Alignment */ 348#define FAULT_ALIGN_1 0x03 /* Alignment */ 349#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 350#define FAULT_TRANS_F 0x06 /* Translation -- Flag */ 351#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 352#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 353#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 354#define FAULT_PERM_S 0x0d /* Permission -- Section */ 355#define FAULT_PERM_P 0x0f /* Permission -- Page */ 356 357#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 358#define FAULT_EXTERNAL 0x400 /* External abort (armv6+) */ 359#define FAULT_WNR 0x800 /* Write-not-Read access (armv6+) */ 360 361/* 362 * Address of the vector page, low and high versions. 363 */ 364#ifndef __ASSEMBLER__ 365#define ARM_VECTORS_LOW 0x00000000U 366#define ARM_VECTORS_HIGH 0xffff0000U 367#else 368#define ARM_VECTORS_LOW 0 369#define ARM_VECTORS_HIGH 0xffff0000 370#endif 371 372/* 373 * ARM Instructions 374 * 375 * 3 3 2 2 2 376 * 1 0 9 8 7 0 377 * +-------+-------------------------------------------------------+ 378 * | cond | instruction dependant | 379 * |c c c c| | 380 * +-------+-------------------------------------------------------+ 381 */ 382 383#define INSN_SIZE 4 /* Always 4 bytes */ 384#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 385#define INSN_COND_AL 0xe0000000 /* Always condition */ 386 387#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 388 389#endif /* !MACHINE_ARMREG_H */ 390