1248557Sray/*- 2250357Sray * Copyright (c) 2012, 2013 The FreeBSD Foundation 3248557Sray * All rights reserved. 4248557Sray * 5248557Sray * This software was developed by Oleksandr Rybalko under sponsorship 6248557Sray * from the FreeBSD Foundation. 7248557Sray * 8248557Sray * Redistribution and use in source and binary forms, with or without 9248557Sray * modification, are permitted provided that the following conditions 10248557Sray * are met: 11248557Sray * 1. Redistributions of source code must retain the above copyright 12248557Sray * notice, this list of conditions and the following disclaimer. 13248557Sray * 2. Redistributions in binary form must reproduce the above copyright 14248557Sray * notice, this list of conditions and the following disclaimer in the 15248557Sray * documentation and/or other materials provided with the distribution. 16248557Sray * 17248557Sray * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18248557Sray * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19248557Sray * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20248557Sray * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21248557Sray * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22248557Sray * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23248557Sray * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24248557Sray * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25248557Sray * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26248557Sray * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27248557Sray * SUCH DAMAGE. 28248557Sray */ 29248557Sray 30248557Sray#include <sys/cdefs.h> 31248557Sray__FBSDID("$FreeBSD$"); 32248557Sray 33248557Sray#include <sys/param.h> 34248557Sray#include <sys/systm.h> 35248557Sray#include <sys/bus.h> 36248557Sray#include <sys/kernel.h> 37248557Sray#include <sys/module.h> 38248557Sray#include <sys/malloc.h> 39248557Sray#include <sys/rman.h> 40248557Sray#include <sys/timeet.h> 41248557Sray#include <sys/timetc.h> 42248557Sray#include <sys/watchdog.h> 43248557Sray#include <machine/bus.h> 44248557Sray#include <machine/cpu.h> 45248557Sray#include <machine/intr.h> 46248557Sray 47248557Sray#include <machine/fdt.h> 48248557Sray#include <dev/fdt/fdt_common.h> 49248557Sray#include <dev/ofw/openfirm.h> 50248557Sray#include <dev/ofw/ofw_bus.h> 51248557Sray#include <dev/ofw/ofw_bus_subr.h> 52248557Sray 53248557Sray#include <arm/freescale/imx/imx_gptvar.h> 54248557Sray#include <arm/freescale/imx/imx_gptreg.h> 55248557Sray 56248557Sray#include <sys/kdb.h> 57266371Sian#include <arm/freescale/imx/imx_ccmvar.h> 58248557Sray 59248557Sray#define WRITE4(_sc, _r, _v) \ 60248557Sray bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 61248557Sray#define READ4(_sc, _r) \ 62248557Sray bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 63248557Sray#define SET4(_sc, _r, _m) \ 64248557Sray WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 65248557Sray#define CLEAR4(_sc, _r, _m) \ 66248557Sray WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 67248557Sray 68248557Sraystatic u_int imx_gpt_get_timecount(struct timecounter *); 69248557Sraystatic int imx_gpt_timer_start(struct eventtimer *, sbintime_t, 70248557Sray sbintime_t); 71248557Sraystatic int imx_gpt_timer_stop(struct eventtimer *); 72248557Sray 73248557Sraystatic int imx_gpt_intr(void *); 74248557Sraystatic int imx_gpt_probe(device_t); 75248557Sraystatic int imx_gpt_attach(device_t); 76248557Sray 77248557Sraystatic struct timecounter imx_gpt_timecounter = { 78266203Sian .tc_name = "iMXGPT", 79248557Sray .tc_get_timecount = imx_gpt_get_timecount, 80248557Sray .tc_counter_mask = ~0u, 81248557Sray .tc_frequency = 0, 82254281Sian .tc_quality = 1000, 83248557Sray}; 84248557Sray 85254281Sian/* Global softc pointer for use in DELAY(). */ 86248557Sraystruct imx_gpt_softc *imx_gpt_sc = NULL; 87248557Sray 88254281Sian/* 89254281Sian * Hand-calibrated delay-loop counter. This was calibrated on an i.MX6 running 90254281Sian * at 792mhz. It will delay a bit too long on slower processors -- that's 91254281Sian * better than not delaying long enough. In practice this is unlikely to get 92254281Sian * used much since the clock driver is one of the first to start up, and once 93254281Sian * we're attached the delay loop switches to using the timer hardware. 94254281Sian */ 95254281Sianstatic const int imx_gpt_delay_count = 78; 96254281Sian 97254281Sian/* Try to divide down an available fast clock to this frequency. */ 98273681Sian#define TARGET_FREQUENCY 1000000000 99254281Sian 100254281Sian/* Don't try to set an event timer period smaller than this. */ 101254281Sian#define MIN_ET_PERIOD 10LLU 102254281Sian 103254281Sian 104248557Sraystatic struct resource_spec imx_gpt_spec[] = { 105248557Sray { SYS_RES_MEMORY, 0, RF_ACTIVE }, 106248557Sray { SYS_RES_IRQ, 0, RF_ACTIVE }, 107248557Sray { -1, 0 } 108248557Sray}; 109248557Sray 110259346Sianstatic struct ofw_compat_data compat_data[] = { 111259346Sian {"fsl,imx6q-gpt", 1}, 112259346Sian {"fsl,imx53-gpt", 1}, 113259346Sian {"fsl,imx51-gpt", 1}, 114259346Sian {"fsl,imx31-gpt", 1}, 115259346Sian {"fsl,imx27-gpt", 1}, 116259346Sian {"fsl,imx25-gpt", 1}, 117259346Sian {NULL, 0} 118259346Sian}; 119259346Sian 120248557Sraystatic int 121248557Srayimx_gpt_probe(device_t dev) 122248557Sray{ 123248557Sray 124266152Sian if (!ofw_bus_status_okay(dev)) 125266152Sian return (ENXIO); 126266152Sian 127259346Sian if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 128259346Sian device_set_desc(dev, "Freescale i.MX GPT timer"); 129259346Sian return (BUS_PROBE_DEFAULT); 130259346Sian } 131248557Sray 132259346Sian return (ENXIO); 133248557Sray} 134248557Sray 135248557Sraystatic int 136248557Srayimx_gpt_attach(device_t dev) 137248557Sray{ 138248557Sray struct imx_gpt_softc *sc; 139254281Sian int ctlreg, err; 140254281Sian uint32_t basefreq, prescale; 141248557Sray 142248557Sray sc = device_get_softc(dev); 143248557Sray 144248557Sray if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) { 145248557Sray device_printf(dev, "could not allocate resources\n"); 146248557Sray return (ENXIO); 147248557Sray } 148248557Sray 149248557Sray sc->sc_dev = dev; 150248557Sray sc->sc_iot = rman_get_bustag(sc->res[0]); 151248557Sray sc->sc_ioh = rman_get_bushandle(sc->res[0]); 152248557Sray 153254281Sian /* 154254281Sian * For now, just automatically choose a good clock for the hardware 155254281Sian * we're running on. Eventually we could allow selection from the fdt; 156254281Sian * the code in this driver will cope with any clock frequency. 157254281Sian */ 158259346Sian sc->sc_clksrc = GPT_CR_CLKSRC_IPG; 159254281Sian 160254281Sian ctlreg = 0; 161254281Sian 162248557Sray switch (sc->sc_clksrc) { 163248557Sray case GPT_CR_CLKSRC_32K: 164254281Sian basefreq = 32768; 165248557Sray break; 166254281Sian case GPT_CR_CLKSRC_IPG: 167266371Sian basefreq = imx_ccm_ipg_hz(); 168254281Sian break; 169248557Sray case GPT_CR_CLKSRC_IPG_HIGH: 170266371Sian basefreq = imx_ccm_ipg_hz() * 2; 171248557Sray break; 172254281Sian case GPT_CR_CLKSRC_24M: 173254281Sian ctlreg |= GPT_CR_24MEN; 174254281Sian basefreq = 24000000; 175254281Sian break; 176254281Sian case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */ 177254281Sian case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */ 178248557Sray default: 179254281Sian device_printf(dev, "Unsupported clock source '%d'\n", 180254281Sian sc->sc_clksrc); 181254281Sian return (EINVAL); 182248557Sray } 183248557Sray 184254281Sian /* 185254281Sian * The following setup sequence is from the I.MX6 reference manual, 186254281Sian * "Selecting the clock source". First, disable the clock and 187254281Sian * interrupts. This also clears input and output mode bits and in 188254281Sian * general completes several of the early steps in the procedure. 189254281Sian */ 190254281Sian WRITE4(sc, IMX_GPT_CR, 0); 191254281Sian WRITE4(sc, IMX_GPT_IR, 0); 192254281Sian 193254281Sian /* Choose the clock and the power-saving behaviors. */ 194254281Sian ctlreg |= 195254281Sian sc->sc_clksrc | /* Use selected clock */ 196248557Sray GPT_CR_FRR | /* Just count (FreeRunner mode) */ 197248557Sray GPT_CR_STOPEN | /* Run in STOP mode */ 198254281Sian GPT_CR_DOZEEN | /* Run in DOZE mode */ 199248557Sray GPT_CR_WAITEN | /* Run in WAIT mode */ 200254281Sian GPT_CR_DBGEN; /* Run in DEBUG mode */ 201254281Sian WRITE4(sc, IMX_GPT_CR, ctlreg); 202248557Sray 203254281Sian /* 204254281Sian * The datasheet says to do the software reset after choosing the clock 205254281Sian * source. It says nothing about needing to wait for the reset to 206254281Sian * complete, but the register description does document the fact that 207254281Sian * the reset isn't complete until the SWR bit reads 0, so let's be safe. 208254281Sian * The reset also clears all registers except for a few of the bits in 209254281Sian * CR, but we'll rewrite all the CR bits when we start the counter. 210254281Sian */ 211254281Sian WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); 212254281Sian while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR) 213254281Sian continue; 214248557Sray 215254281Sian /* Set a prescaler value that gets us near the target frequency. */ 216254281Sian if (basefreq < TARGET_FREQUENCY) { 217254281Sian prescale = 0; 218254281Sian sc->clkfreq = basefreq; 219254281Sian } else { 220254281Sian prescale = basefreq / TARGET_FREQUENCY; 221254281Sian sc->clkfreq = basefreq / prescale; 222254281Sian prescale -= 1; /* 1..n range is 0..n-1 in hardware. */ 223254281Sian } 224254281Sian WRITE4(sc, IMX_GPT_PR, prescale); 225248557Sray 226254281Sian /* Clear the status register. */ 227254281Sian WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); 228254281Sian 229254281Sian /* Start the counter. */ 230254281Sian WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN); 231254281Sian 232254281Sian if (bootverbose) 233254281Sian device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n", 234254281Sian sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR)); 235254281Sian 236254281Sian /* Setup the timer interrupt. */ 237248557Sray err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr, 238248557Sray NULL, sc, &sc->sc_ih); 239248557Sray if (err != 0) { 240248557Sray bus_release_resources(dev, imx_gpt_spec, sc->res); 241248557Sray device_printf(dev, "Unable to setup the clock irq handler, " 242248557Sray "err = %d\n", err); 243248557Sray return (ENXIO); 244248557Sray } 245248557Sray 246254281Sian /* Register as an eventtimer. */ 247266203Sian sc->et.et_name = "iMXGPT"; 248248557Sray sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 249266203Sian sc->et.et_quality = 800; 250248557Sray sc->et.et_frequency = sc->clkfreq; 251254281Sian sc->et.et_min_period = (MIN_ET_PERIOD << 32) / sc->et.et_frequency; 252248557Sray sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 253248557Sray sc->et.et_start = imx_gpt_timer_start; 254248557Sray sc->et.et_stop = imx_gpt_timer_stop; 255248557Sray sc->et.et_priv = sc; 256248557Sray et_register(&sc->et); 257248557Sray 258254281Sian /* Register as a timecounter. */ 259254281Sian imx_gpt_timecounter.tc_frequency = sc->clkfreq; 260254281Sian tc_init(&imx_gpt_timecounter); 261248557Sray 262254281Sian /* If this is the first unit, store the softc for use in DELAY. */ 263248557Sray if (device_get_unit(dev) == 0) 264248557Sray imx_gpt_sc = sc; 265248557Sray 266248557Sray return (0); 267248557Sray} 268248557Sray 269248557Sraystatic int 270248557Srayimx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 271248557Sray{ 272248557Sray struct imx_gpt_softc *sc; 273248557Sray uint32_t ticks; 274248557Sray 275248557Sray sc = (struct imx_gpt_softc *)et->et_priv; 276248557Sray 277248557Sray if (period != 0) { 278248557Sray sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32; 279248557Sray /* Set expected value */ 280248557Sray WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period); 281248557Sray /* Enable compare register 2 Interrupt */ 282248557Sray SET4(sc, IMX_GPT_IR, GPT_IR_OF2); 283259347Sian return (0); 284248557Sray } else if (first != 0) { 285248557Sray ticks = ((uint32_t)et->et_frequency * first) >> 32; 286248557Sray /* Do not disturb, otherwise event will be lost */ 287248557Sray spinlock_enter(); 288248557Sray /* Set expected value */ 289266203Sian WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks); 290248557Sray /* Enable compare register 1 Interrupt */ 291266203Sian SET4(sc, IMX_GPT_IR, GPT_IR_OF3); 292248557Sray /* Now everybody can relax */ 293248557Sray spinlock_exit(); 294248557Sray return (0); 295248557Sray } 296248557Sray 297248557Sray return (EINVAL); 298248557Sray} 299248557Sray 300248557Sraystatic int 301248557Srayimx_gpt_timer_stop(struct eventtimer *et) 302248557Sray{ 303248557Sray struct imx_gpt_softc *sc; 304248557Sray 305248557Sray sc = (struct imx_gpt_softc *)et->et_priv; 306248557Sray 307248557Sray /* Disable OF2 Interrupt */ 308248557Sray CLEAR4(sc, IMX_GPT_IR, GPT_IR_OF2); 309248557Sray WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2); 310248557Sray sc->sc_period = 0; 311248557Sray 312248557Sray return (0); 313248557Sray} 314248557Sray 315248557Srayint 316248557Srayimx_gpt_get_timerfreq(struct imx_gpt_softc *sc) 317248557Sray{ 318248557Sray 319248557Sray return (sc->clkfreq); 320248557Sray} 321248557Sray 322248557Sraystatic int 323248557Srayimx_gpt_intr(void *arg) 324248557Sray{ 325248557Sray struct imx_gpt_softc *sc; 326248557Sray uint32_t status; 327248557Sray 328248557Sray sc = (struct imx_gpt_softc *)arg; 329248557Sray 330259347Sian status = READ4(sc, IMX_GPT_SR); 331248557Sray 332259347Sian /* 333259347Sian * Clear interrupt status before invoking event callbacks. The callback 334259347Sian * often sets up a new one-shot timer event and if the interval is short 335259347Sian * enough it can fire before we get out of this function. If we cleared 336259347Sian * at the bottom we'd miss the interrupt and hang until the clock wraps. 337259347Sian */ 338259347Sian WRITE4(sc, IMX_GPT_SR, status); 339259347Sian 340259347Sian /* Handle one-shot timer events. */ 341266203Sian if (status & GPT_IR_OF3) { 342248557Sray if (sc->et.et_active) { 343248557Sray sc->et.et_event_cb(&sc->et, sc->et.et_arg); 344248557Sray } 345248557Sray } 346259347Sian 347259347Sian /* Handle periodic timer events. */ 348248557Sray if (status & GPT_IR_OF2) { 349259347Sian if (sc->et.et_active) 350248557Sray sc->et.et_event_cb(&sc->et, sc->et.et_arg); 351259347Sian if (sc->sc_period != 0) 352248557Sray WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + 353248557Sray sc->sc_period); 354248557Sray } 355248557Sray 356248557Sray return (FILTER_HANDLED); 357248557Sray} 358248557Sray 359248557Srayu_int 360248557Srayimx_gpt_get_timecount(struct timecounter *tc) 361248557Sray{ 362248557Sray 363248557Sray if (imx_gpt_sc == NULL) 364248557Sray return (0); 365248557Sray 366248557Sray return (READ4(imx_gpt_sc, IMX_GPT_CNT)); 367248557Sray} 368248557Sray 369248557Sraystatic device_method_t imx_gpt_methods[] = { 370248557Sray DEVMETHOD(device_probe, imx_gpt_probe), 371248557Sray DEVMETHOD(device_attach, imx_gpt_attach), 372248557Sray 373248557Sray DEVMETHOD_END 374248557Sray}; 375248557Sray 376248557Sraystatic driver_t imx_gpt_driver = { 377248557Sray "imx_gpt", 378248557Sray imx_gpt_methods, 379248557Sray sizeof(struct imx_gpt_softc), 380248557Sray}; 381248557Sray 382248557Sraystatic devclass_t imx_gpt_devclass; 383248557Sray 384248557SrayEARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, imx_gpt_devclass, 0, 385248557Sray 0, BUS_PASS_TIMER); 386248557Sray 387248557Srayvoid 388248557SrayDELAY(int usec) 389248557Sray{ 390254281Sian uint64_t curcnt, endcnt, startcnt, ticks; 391248557Sray 392254281Sian /* If the timer hardware is not accessible, just use a loop. */ 393254281Sian if (imx_gpt_sc == NULL) { 394254281Sian while (usec-- > 0) 395254281Sian for (ticks = 0; ticks < imx_gpt_delay_count; ++ticks) 396248557Sray cpufunc_nullop(); 397248557Sray return; 398248557Sray } 399248557Sray 400254281Sian /* 401254281Sian * Calculate the tick count with 64-bit values so that it works for any 402254281Sian * clock frequency. Loop until the hardware count reaches start+ticks. 403254281Sian * If the 32-bit hardware count rolls over while we're looping, just 404254281Sian * manually do a carry into the high bits after each read; don't worry 405254281Sian * that doing this on each loop iteration is inefficient -- we're trying 406254281Sian * to waste time here. 407254281Sian */ 408254281Sian ticks = 1 + ((uint64_t)usec * imx_gpt_sc->clkfreq) / 1000000; 409254281Sian curcnt = startcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 410254281Sian endcnt = startcnt + ticks; 411254281Sian while (curcnt < endcnt) { 412254281Sian curcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 413254281Sian if (curcnt < startcnt) 414254281Sian curcnt += 1ULL << 32; 415248557Sray } 416248557Sray} 417