bcm2835_spi.c revision 259325 
1/*-
2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: stable/10/sys/arm/broadcom/bcm2835/bcm2835_spi.c 259325 2013-12-13 19:27:23Z ian $");
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/rman.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <sys/sysctl.h>
41
42#include <machine/bus.h>
43#include <machine/cpu.h>
44#include <machine/cpufunc.h>
45#include <machine/resource.h>
46#include <machine/fdt.h>
47#include <machine/frame.h>
48#include <machine/intr.h>
49
50#include <dev/fdt/fdt_common.h>
51#include <dev/ofw/ofw_bus.h>
52#include <dev/ofw/ofw_bus_subr.h>
53
54#include <dev/spibus/spi.h>
55#include <dev/spibus/spibusvar.h>
56
57#include <arm/broadcom/bcm2835/bcm2835_gpio.h>
58#include <arm/broadcom/bcm2835/bcm2835_spireg.h>
59#include <arm/broadcom/bcm2835/bcm2835_spivar.h>
60
61#include "spibus_if.h"
62
63static void bcm_spi_intr(void *);
64
65#ifdef	BCM_SPI_DEBUG
66static void
67bcm_spi_printr(device_t dev)
68{
69	struct bcm_spi_softc *sc;
70	uint32_t reg;
71
72	sc = device_get_softc(dev);
73	reg = BCM_SPI_READ(sc, SPI_CS);
74	device_printf(dev, "CS=%b\n", reg,
75	    "\20\1CS0\2CS1\3CPHA\4CPOL\7CSPOL"
76	    "\10TA\11DMAEN\12INTD\13INTR\14ADCS\15REN\16LEN"
77	    "\21DONE\22RXD\23TXD\24RXR\25RXF\26CSPOL0\27CSPOL1"
78	    "\30CSPOL2\31DMA_LEN\32LEN_LONG");
79	reg = BCM_SPI_READ(sc, SPI_CLK) & SPI_CLK_MASK;
80	if (reg % 2)
81		reg--;
82	if (reg == 0)
83		reg = 65536;
84	device_printf(dev, "CLK=%uMhz/%d=%luhz\n",
85	    SPI_CORE_CLK / 1000000, reg, SPI_CORE_CLK / reg);
86	reg = BCM_SPI_READ(sc, SPI_DLEN) & SPI_DLEN_MASK;
87	device_printf(dev, "DLEN=%d\n", reg);
88	reg = BCM_SPI_READ(sc, SPI_LTOH) & SPI_LTOH_MASK;
89	device_printf(dev, "LTOH=%d\n", reg);
90	reg = BCM_SPI_READ(sc, SPI_DC);
91	device_printf(dev, "DC=RPANIC=%#x RDREQ=%#x TPANIC=%#x TDREQ=%#x\n",
92	    (reg & SPI_DC_RPANIC_MASK) >> SPI_DC_RPANIC_SHIFT,
93	    (reg & SPI_DC_RDREQ_MASK) >> SPI_DC_RDREQ_SHIFT,
94	    (reg & SPI_DC_TPANIC_MASK) >> SPI_DC_TPANIC_SHIFT,
95	    (reg & SPI_DC_TDREQ_MASK) >> SPI_DC_TDREQ_SHIFT);
96}
97#endif
98
99static void
100bcm_spi_modifyreg(struct bcm_spi_softc *sc, uint32_t off, uint32_t mask,
101	uint32_t value)
102{
103	uint32_t reg;
104
105	mtx_assert(&sc->sc_mtx, MA_OWNED);
106	reg = BCM_SPI_READ(sc, off);
107	reg &= ~mask;
108	reg |= value;
109	BCM_SPI_WRITE(sc, off, reg);
110}
111
112static int
113bcm_spi_clock_proc(SYSCTL_HANDLER_ARGS)
114{
115	struct bcm_spi_softc *sc;
116	uint32_t clk;
117	int error;
118
119	sc = (struct bcm_spi_softc *)arg1;
120
121	BCM_SPI_LOCK(sc);
122	clk = BCM_SPI_READ(sc, SPI_CLK);
123	BCM_SPI_UNLOCK(sc);
124	clk &= 0xffff;
125	if (clk == 0)
126		clk = 65536;
127	clk = SPI_CORE_CLK / clk;
128
129	error = sysctl_handle_int(oidp, &clk, sizeof(clk), req);
130	if (error != 0 || req->newptr == NULL)
131		return (error);
132
133	clk = SPI_CORE_CLK / clk;
134	if (clk <= 1)
135		clk = 2;
136	else if (clk % 2)
137		clk--;
138	if (clk > 0xffff)
139		clk = 0;
140	BCM_SPI_LOCK(sc);
141	BCM_SPI_WRITE(sc, SPI_CLK, clk);
142	BCM_SPI_UNLOCK(sc);
143
144	return (0);
145}
146
147static int
148bcm_spi_cs_bit_proc(SYSCTL_HANDLER_ARGS, uint32_t bit)
149{
150	struct bcm_spi_softc *sc;
151	uint32_t reg;
152	int error;
153
154	sc = (struct bcm_spi_softc *)arg1;
155	BCM_SPI_LOCK(sc);
156	reg = BCM_SPI_READ(sc, SPI_CS);
157	BCM_SPI_UNLOCK(sc);
158	reg = (reg & bit) ? 1 : 0;
159
160	error = sysctl_handle_int(oidp, &reg, sizeof(reg), req);
161	if (error != 0 || req->newptr == NULL)
162		return (error);
163
164	if (reg)
165		reg = bit;
166	BCM_SPI_LOCK(sc);
167	bcm_spi_modifyreg(sc, SPI_CS, bit, reg);
168	BCM_SPI_UNLOCK(sc);
169
170	return (0);
171}
172
173static int
174bcm_spi_cpol_proc(SYSCTL_HANDLER_ARGS)
175{
176
177	return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPOL));
178}
179
180static int
181bcm_spi_cpha_proc(SYSCTL_HANDLER_ARGS)
182{
183
184	return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPHA));
185}
186
187static int
188bcm_spi_cspol0_proc(SYSCTL_HANDLER_ARGS)
189{
190
191	return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL0));
192}
193
194static int
195bcm_spi_cspol1_proc(SYSCTL_HANDLER_ARGS)
196{
197
198	return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL1));
199}
200
201static void
202bcm_spi_sysctl_init(struct bcm_spi_softc *sc)
203{
204	struct sysctl_ctx_list *ctx;
205	struct sysctl_oid *tree_node;
206	struct sysctl_oid_list *tree;
207
208	/*
209	 * Add system sysctl tree/handlers.
210	 */
211	ctx = device_get_sysctl_ctx(sc->sc_dev);
212	tree_node = device_get_sysctl_tree(sc->sc_dev);
213	tree = SYSCTL_CHILDREN(tree_node);
214	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock",
215	    CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
216	    bcm_spi_clock_proc, "IU", "SPI BUS clock frequency");
217	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpol",
218	    CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
219	    bcm_spi_cpol_proc, "IU", "SPI BUS clock polarity");
220	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpha",
221	    CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
222	    bcm_spi_cpha_proc, "IU", "SPI BUS clock phase");
223	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol0",
224	    CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
225	    bcm_spi_cspol0_proc, "IU", "SPI BUS chip select 0 polarity");
226	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol1",
227	    CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
228	    bcm_spi_cspol1_proc, "IU", "SPI BUS chip select 1 polarity");
229}
230
231static int
232bcm_spi_probe(device_t dev)
233{
234
235	if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-spi"))
236		return (ENXIO);
237
238	device_set_desc(dev, "BCM2708/2835 SPI controller");
239
240	return (BUS_PROBE_DEFAULT);
241}
242
243static int
244bcm_spi_attach(device_t dev)
245{
246	struct bcm_spi_softc *sc;
247	device_t gpio;
248	int i, rid;
249
250	if (device_get_unit(dev) != 0) {
251		device_printf(dev, "only one SPI controller supported\n");
252		return (ENXIO);
253	}
254
255	sc = device_get_softc(dev);
256	sc->sc_dev = dev;
257
258	/* Configure the GPIO pins to ALT0 function to enable SPI the pins. */
259	gpio = devclass_get_device(devclass_find("gpio"), 0);
260	if (!gpio) {
261		device_printf(dev, "cannot find gpio0\n");
262		return (ENXIO);
263	}
264	for (i = 0; i < nitems(bcm_spi_pins); i++)
265		bcm_gpio_set_alternate(gpio, bcm_spi_pins[i], BCM_GPIO_ALT0);
266
267	rid = 0;
268	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
269	    RF_ACTIVE);
270	if (!sc->sc_mem_res) {
271		device_printf(dev, "cannot allocate memory window\n");
272		return (ENXIO);
273	}
274
275	sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
276	sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
277
278	rid = 0;
279	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
280	    RF_ACTIVE);
281	if (!sc->sc_irq_res) {
282		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
283		device_printf(dev, "cannot allocate interrupt\n");
284		return (ENXIO);
285	}
286
287	/* Hook up our interrupt handler. */
288	if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
289	    NULL, bcm_spi_intr, sc, &sc->sc_intrhand)) {
290		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
291		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
292		device_printf(dev, "cannot setup the interrupt handler\n");
293		return (ENXIO);
294	}
295
296	mtx_init(&sc->sc_mtx, "bcm_spi", NULL, MTX_DEF);
297
298	/* Add sysctl nodes. */
299	bcm_spi_sysctl_init(sc);
300
301#ifdef	BCM_SPI_DEBUG
302	bcm_spi_printr(dev);
303#endif
304
305	/*
306	 * Enable the SPI controller.  Clear the rx and tx FIFO.
307	 * Defaults to SPI mode 0.
308	 */
309	BCM_SPI_WRITE(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO);
310
311	/* Set the SPI clock to 500Khz. */
312	BCM_SPI_WRITE(sc, SPI_CLK, SPI_CORE_CLK / 500000);
313
314#ifdef	BCM_SPI_DEBUG
315	bcm_spi_printr(dev);
316#endif
317
318	device_add_child(dev, "spibus", -1);
319
320	return (bus_generic_attach(dev));
321}
322
323static int
324bcm_spi_detach(device_t dev)
325{
326	struct bcm_spi_softc *sc;
327
328	bus_generic_detach(dev);
329
330	sc = device_get_softc(dev);
331	mtx_destroy(&sc->sc_mtx);
332	if (sc->sc_intrhand)
333		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
334	if (sc->sc_irq_res)
335		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
336	if (sc->sc_mem_res)
337		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
338
339	return (0);
340}
341
342static void
343bcm_spi_fill_fifo(struct bcm_spi_softc *sc)
344{
345	struct spi_command *cmd;
346	uint32_t cs, written;
347	uint8_t *data;
348
349	cmd = sc->sc_cmd;
350	cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD);
351	while (sc->sc_written < sc->sc_len &&
352	    cs == (SPI_CS_TA | SPI_CS_TXD)) {
353		data = (uint8_t *)cmd->tx_cmd;
354		written = sc->sc_written++;
355		if (written >= cmd->tx_cmd_sz) {
356			data = (uint8_t *)cmd->tx_data;
357			written -= cmd->tx_cmd_sz;
358		}
359		BCM_SPI_WRITE(sc, SPI_FIFO, data[written]);
360		cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD);
361	}
362}
363
364static void
365bcm_spi_drain_fifo(struct bcm_spi_softc *sc)
366{
367	struct spi_command *cmd;
368	uint32_t cs, read;
369	uint8_t *data;
370
371	cmd = sc->sc_cmd;
372	cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD;
373	while (sc->sc_read < sc->sc_len && cs == SPI_CS_RXD) {
374		data = (uint8_t *)cmd->rx_cmd;
375		read = sc->sc_read++;
376		if (read >= cmd->rx_cmd_sz) {
377			data = (uint8_t *)cmd->rx_data;
378			read -= cmd->rx_cmd_sz;
379		}
380		data[read] = BCM_SPI_READ(sc, SPI_FIFO) & 0xff;
381		cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD;
382	}
383}
384
385static void
386bcm_spi_intr(void *arg)
387{
388	struct bcm_spi_softc *sc;
389
390	sc = (struct bcm_spi_softc *)arg;
391	BCM_SPI_LOCK(sc);
392
393	/* Filter stray interrupts. */
394	if ((sc->sc_flags & BCM_SPI_BUSY) == 0) {
395		BCM_SPI_UNLOCK(sc);
396		return;
397	}
398
399	/* TX - Fill up the FIFO. */
400	bcm_spi_fill_fifo(sc);
401
402	/* RX - Drain the FIFO. */
403	bcm_spi_drain_fifo(sc);
404
405	/* Check for end of transfer. */
406	if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) {
407		/* Disable interrupts and the SPI engine. */
408		bcm_spi_modifyreg(sc, SPI_CS,
409		    SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0);
410		wakeup(sc->sc_dev);
411	}
412
413	BCM_SPI_UNLOCK(sc);
414}
415
416static int
417bcm_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
418{
419	struct bcm_spi_softc *sc;
420	int cs, err;
421
422	sc = device_get_softc(dev);
423
424	KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
425	    ("TX/RX command sizes should be equal"));
426	KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
427	    ("TX/RX data sizes should be equal"));
428
429	BCM_SPI_LOCK(sc);
430
431	/* If the controller is in use wait until it is available. */
432	while (sc->sc_flags & BCM_SPI_BUSY)
433		mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", 0);
434
435	/* Now we have control over SPI controller. */
436	sc->sc_flags = BCM_SPI_BUSY;
437
438	/* Clear the FIFO. */
439	bcm_spi_modifyreg(sc, SPI_CS,
440	    SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO,
441	    SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO);
442
443	/* Get the proper chip select for this child. */
444	spibus_get_cs(child, &cs);
445	if (cs < 0 || cs > 2) {
446		device_printf(dev,
447		    "Invalid chip select %d requested by %s\n", cs,
448		    device_get_nameunit(child));
449		BCM_SPI_UNLOCK(sc);
450		return (EINVAL);
451	}
452
453	/* Save a pointer to the SPI command. */
454	sc->sc_cmd = cmd;
455	sc->sc_read = 0;
456	sc->sc_written = 0;
457	sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
458
459	/*
460	 * Set the CS for this transaction, enable interrupts and announce
461	 * we're ready to tx.  This will kick off the first interrupt.
462	 */
463	bcm_spi_modifyreg(sc, SPI_CS,
464	    SPI_CS_MASK | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD,
465	    cs | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD);
466
467	/* Wait for the transaction to complete. */
468	err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", hz * 2);
469
470	/* Make sure the SPI engine and interrupts are disabled. */
471	bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0);
472
473	/* Clear the controller flags. */
474	sc->sc_flags = 0;
475
476	/*
477	 * Check for transfer timeout.  The SPI controller doesn't
478	 * return errors.
479	 */
480	if (err == EWOULDBLOCK) {
481		device_printf(sc->sc_dev, "SPI error\n");
482		err = EIO;
483	}
484
485	BCM_SPI_UNLOCK(sc);
486
487	return (err);
488}
489
490static phandle_t
491bcm_spi_get_node(device_t bus, device_t dev)
492{
493
494	/* We only have one child, the SPI bus, which needs our own node. */
495	return (ofw_bus_get_node(bus));
496}
497
498static device_method_t bcm_spi_methods[] = {
499	/* Device interface */
500	DEVMETHOD(device_probe,		bcm_spi_probe),
501	DEVMETHOD(device_attach,	bcm_spi_attach),
502	DEVMETHOD(device_detach,	bcm_spi_detach),
503
504	/* SPI interface */
505	DEVMETHOD(spibus_transfer,	bcm_spi_transfer),
506
507	/* ofw_bus interface */
508	DEVMETHOD(ofw_bus_get_node,	bcm_spi_get_node),
509
510	DEVMETHOD_END
511};
512
513static devclass_t bcm_spi_devclass;
514
515static driver_t bcm_spi_driver = {
516	"spi",
517	bcm_spi_methods,
518	sizeof(struct bcm_spi_softc),
519};
520
521DRIVER_MODULE(bcm2835_spi, simplebus, bcm_spi_driver, bcm_spi_devclass, 0, 0);
522