if_ate.c revision 185267
1155324Simp/*- 2155324Simp * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3155324Simp * 4155324Simp * Redistribution and use in source and binary forms, with or without 5155324Simp * modification, are permitted provided that the following conditions 6155324Simp * are met: 7155324Simp * 1. Redistributions of source code must retain the above copyright 8155324Simp * notice, this list of conditions and the following disclaimer. 9155324Simp * 2. Redistributions in binary form must reproduce the above copyright 10155324Simp * notice, this list of conditions and the following disclaimer in the 11155324Simp * documentation and/or other materials provided with the distribution. 12155324Simp * 13185267Simp * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14185267Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15185267Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16185267Simp * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17185267Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18185267Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19185267Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20185267Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21185267Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22185267Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23185267Simp * SUCH DAMAGE. 24155324Simp */ 25155324Simp 26155324Simp/* TODO: (in no order) 27155324Simp * 28155324Simp * 8) Need to sync busdma goo in atestop 29155324Simp * 9) atestop should maybe free the mbufs? 30155324Simp * 31155324Simp * 1) detach 32155324Simp * 2) Free dma setup 33163522Simp * 3) Turn on the clock in pmc? Turn off? 34155324Simp */ 35155324Simp 36155324Simp#include <sys/cdefs.h> 37155324Simp__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 185267 2008-11-25 00:14:49Z imp $"); 38155324Simp 39155324Simp#include <sys/param.h> 40155324Simp#include <sys/systm.h> 41155324Simp#include <sys/bus.h> 42155324Simp#include <sys/kernel.h> 43155324Simp#include <sys/mbuf.h> 44155324Simp#include <sys/malloc.h> 45155324Simp#include <sys/module.h> 46155324Simp#include <sys/rman.h> 47155324Simp#include <sys/socket.h> 48155324Simp#include <sys/sockio.h> 49163522Simp#include <sys/sysctl.h> 50155324Simp#include <machine/bus.h> 51155324Simp 52155324Simp#include <net/ethernet.h> 53155324Simp#include <net/if.h> 54155324Simp#include <net/if_arp.h> 55155324Simp#include <net/if_dl.h> 56155324Simp#include <net/if_media.h> 57155324Simp#include <net/if_mib.h> 58155324Simp#include <net/if_types.h> 59155324Simp 60155324Simp#ifdef INET 61155324Simp#include <netinet/in.h> 62155324Simp#include <netinet/in_systm.h> 63155324Simp#include <netinet/in_var.h> 64155324Simp#include <netinet/ip.h> 65155324Simp#endif 66155324Simp 67155324Simp#include <net/bpf.h> 68155324Simp#include <net/bpfdesc.h> 69155324Simp 70155324Simp#include <dev/mii/mii.h> 71155324Simp#include <dev/mii/miivar.h> 72155324Simp#include <arm/at91/if_atereg.h> 73155324Simp 74155324Simp#include "miibus_if.h" 75155324Simp 76165778Sticso#define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 77156831Simp#define ATE_MAX_RX_BUFFERS 64 78155324Simp 79155324Simpstruct ate_softc 80155324Simp{ 81155324Simp struct ifnet *ifp; /* ifnet pointer */ 82155324Simp struct mtx sc_mtx; /* basically a perimeter lock */ 83155324Simp device_t dev; /* Myself */ 84155324Simp device_t miibus; /* My child miibus */ 85155324Simp void *intrhand; /* Interrupt handle */ 86155324Simp struct resource *irq_res; /* IRQ resource */ 87155324Simp struct resource *mem_res; /* Memory resource */ 88155324Simp struct callout tick_ch; /* Tick callout */ 89155324Simp bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 90155324Simp bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 91157562Simp struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 92155324Simp bus_dma_tag_t rxtag; 93155324Simp bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 94157562Simp void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 95157562Simp int rx_buf_ptr; 96155324Simp bus_dma_tag_t rx_desc_tag; 97155324Simp bus_dmamap_t rx_desc_map; 98155324Simp int txcur; /* current tx map pointer */ 99155324Simp bus_addr_t rx_desc_phys; 100155324Simp eth_rx_desc_t *rx_descs; 101159708Simp int use_rmii; 102155324Simp struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 103155324Simp}; 104155324Simp 105155324Simpstatic inline uint32_t 106155324SimpRD4(struct ate_softc *sc, bus_size_t off) 107155324Simp{ 108155324Simp return bus_read_4(sc->mem_res, off); 109155324Simp} 110155324Simp 111155324Simpstatic inline void 112155324SimpWR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 113155324Simp{ 114155324Simp bus_write_4(sc->mem_res, off, val); 115155324Simp} 116155324Simp 117155324Simp#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 118155324Simp#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 119155324Simp#define ATE_LOCK_INIT(_sc) \ 120155324Simp mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 121155324Simp MTX_NETWORK_LOCK, MTX_DEF) 122155324Simp#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 123155324Simp#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 124155324Simp#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 125155324Simp 126155324Simpstatic devclass_t ate_devclass; 127155324Simp 128155324Simp/* ifnet entry points */ 129155324Simp 130155324Simpstatic void ateinit_locked(void *); 131155324Simpstatic void atestart_locked(struct ifnet *); 132155324Simp 133155324Simpstatic void ateinit(void *); 134155324Simpstatic void atestart(struct ifnet *); 135155324Simpstatic void atestop(struct ate_softc *); 136155324Simpstatic int ateioctl(struct ifnet * ifp, u_long, caddr_t); 137155324Simp 138155324Simp/* bus entry points */ 139155324Simp 140155324Simpstatic int ate_probe(device_t dev); 141155324Simpstatic int ate_attach(device_t dev); 142155324Simpstatic int ate_detach(device_t dev); 143155324Simpstatic void ate_intr(void *); 144155324Simp 145155324Simp/* helper routines */ 146155324Simpstatic int ate_activate(device_t dev); 147155324Simpstatic void ate_deactivate(device_t dev); 148155324Simpstatic int ate_ifmedia_upd(struct ifnet *ifp); 149155324Simpstatic void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 150166573Simpstatic int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 151155445Scognetstatic void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 152155324Simp 153155324Simp/* 154155324Simp * The AT91 family of products has the ethernet called EMAC. However, 155155324Simp * it isn't self identifying. It is anticipated that the parent bus 156155324Simp * code will take care to only add ate devices where they really are. As 157155324Simp * such, we do nothing here to identify the device and just set its name. 158155324Simp */ 159155324Simpstatic int 160155324Simpate_probe(device_t dev) 161155324Simp{ 162155324Simp device_set_desc(dev, "EMAC"); 163155324Simp return (0); 164155324Simp} 165155324Simp 166155324Simpstatic int 167155324Simpate_attach(device_t dev) 168155324Simp{ 169155324Simp struct ate_softc *sc = device_get_softc(dev); 170155324Simp struct ifnet *ifp = NULL; 171163522Simp struct sysctl_ctx_list *sctx; 172163522Simp struct sysctl_oid *soid; 173155324Simp int err; 174182477Sstas u_char eaddr[ETHER_ADDR_LEN]; 175182477Sstas uint32_t rnd; 176155324Simp 177155324Simp sc->dev = dev; 178155324Simp err = ate_activate(dev); 179155324Simp if (err) 180155324Simp goto out; 181155324Simp 182159708Simp sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 183159708Simp 184182476Sstas /* Sysctls */ 185163522Simp sctx = device_get_sysctl_ctx(dev); 186163522Simp soid = device_get_sysctl_tree(dev); 187163522Simp SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 188163522Simp CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 189163522Simp 190155324Simp /* calling atestop before ifp is set is OK */ 191155324Simp atestop(sc); 192155324Simp ATE_LOCK_INIT(sc); 193155324Simp callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 194155324Simp 195166573Simp if ((err = ate_get_mac(sc, eaddr)) != 0) { 196182477Sstas /* 197182524Sstas * No MAC address configured. Generate the random one. 198182477Sstas */ 199182477Sstas if (bootverbose) 200182477Sstas device_printf(dev, 201182524Sstas "Generating random ethernet address.\n"); 202182477Sstas rnd = arc4random(); 203182477Sstas 204182477Sstas /* 205182555Simp * Set OUI to convenient locally assigned address. 'b' 206182555Simp * is 0x62, which has the locally assigned bit set, and 207182555Simp * the broadcast/multicast bit clear. 208182477Sstas */ 209182555Simp eaddr[0] = 'b'; 210182555Simp eaddr[1] = 's'; 211182555Simp eaddr[2] = 'd'; 212182477Sstas eaddr[3] = (rnd >> 16) & 0xff; 213182477Sstas eaddr[4] = (rnd >> 8) & 0xff; 214182477Sstas eaddr[5] = rnd & 0xff; 215166573Simp } 216155445Scognet ate_set_mac(sc, eaddr); 217155324Simp 218155405Scognet sc->ifp = ifp = if_alloc(IFT_ETHER); 219155324Simp if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 220155324Simp device_printf(dev, "Cannot find my PHY.\n"); 221155324Simp err = ENXIO; 222155324Simp goto out; 223155324Simp } 224155324Simp 225155324Simp ifp->if_softc = sc; 226155324Simp if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 227155324Simp ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 228165779Sticso ifp->if_capabilities |= IFCAP_VLAN_MTU; 229165779Sticso ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 230155324Simp ifp->if_start = atestart; 231155324Simp ifp->if_ioctl = ateioctl; 232155324Simp ifp->if_init = ateinit; 233155324Simp ifp->if_baudrate = 10000000; 234155324Simp IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 235166625Smlaier ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 236155324Simp IFQ_SET_READY(&ifp->if_snd); 237155324Simp ifp->if_timer = 0; 238155324Simp ifp->if_linkmib = &sc->mibdata; 239155324Simp ifp->if_linkmiblen = sizeof(sc->mibdata); 240155324Simp sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 241155324Simp 242155324Simp ether_ifattach(ifp, eaddr); 243155324Simp 244155324Simp /* 245155324Simp * Activate the interrupt 246155324Simp */ 247155324Simp err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 248166901Spiso NULL, ate_intr, sc, &sc->intrhand); 249155324Simp if (err) { 250155324Simp ether_ifdetach(ifp); 251155324Simp ATE_LOCK_DESTROY(sc); 252155324Simp } 253155324Simpout:; 254155324Simp if (err) 255155324Simp ate_deactivate(dev); 256155324Simp if (err && ifp) 257155324Simp if_free(ifp); 258155324Simp return (err); 259155324Simp} 260155324Simp 261155324Simpstatic int 262155324Simpate_detach(device_t dev) 263155324Simp{ 264155324Simp return EBUSY; /* XXX TODO(1) */ 265155324Simp} 266155324Simp 267155324Simpstatic void 268155324Simpate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 269155324Simp{ 270155324Simp struct ate_softc *sc; 271155324Simp 272155324Simp if (error != 0) 273155324Simp return; 274155324Simp sc = (struct ate_softc *)arg; 275155324Simp sc->rx_desc_phys = segs[0].ds_addr; 276155324Simp} 277155324Simp 278157562Simpstatic void 279157562Simpate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 280157562Simp{ 281157562Simp struct ate_softc *sc; 282157562Simp int i; 283157562Simp 284157562Simp if (error != 0) 285157562Simp return; 286157562Simp sc = (struct ate_softc *)arg; 287157562Simp i = sc->rx_buf_ptr; 288157562Simp 289157562Simp /* 290157562Simp * For the last buffer, set the wrap bit so the controller 291157562Simp * restarts from the first descriptor. 292157562Simp */ 293163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 294157562Simp if (i == ATE_MAX_RX_BUFFERS - 1) 295157562Simp sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 296157562Simp else 297157562Simp sc->rx_descs[i].addr = segs[0].ds_addr; 298163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 299157562Simp sc->rx_descs[i].status = 0; 300157562Simp /* Flush the memory in the mbuf */ 301157562Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 302157562Simp} 303157562Simp 304155324Simp/* 305155324Simp * Compute the multicast filter for this device using the standard 306155324Simp * algorithm. I wonder why this isn't in ether somewhere as a lot 307155324Simp * of different MAC chips use this method (or the reverse the bits) 308155324Simp * method. 309155324Simp */ 310155324Simpstatic void 311155324Simpate_setmcast(struct ate_softc *sc) 312155324Simp{ 313155324Simp uint32_t index; 314155324Simp uint32_t mcaf[2]; 315155324Simp u_char *af = (u_char *) mcaf; 316155324Simp struct ifmultiaddr *ifma; 317155324Simp 318155324Simp mcaf[0] = 0; 319155324Simp mcaf[1] = 0; 320155324Simp 321155324Simp IF_ADDR_LOCK(sc->ifp); 322155324Simp TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 323155324Simp if (ifma->ifma_addr->sa_family != AF_LINK) 324155324Simp continue; 325155324Simp index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 326155324Simp ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 327155324Simp af[index >> 3] |= 1 << (index & 7); 328155324Simp } 329155324Simp IF_ADDR_UNLOCK(sc->ifp); 330155324Simp 331155324Simp /* 332155324Simp * Write the hash to the hash register. This card can also 333155324Simp * accept unicast packets as well as multicast packets using this 334155324Simp * register for easier bridging operations, but we don't take 335155324Simp * advantage of that. Locks here are to avoid LOR with the 336155324Simp * IF_ADDR_LOCK, but might not be strictly necessary. 337155324Simp */ 338155324Simp WR4(sc, ETH_HSL, mcaf[0]); 339155324Simp WR4(sc, ETH_HSH, mcaf[1]); 340155324Simp} 341155324Simp 342155324Simpstatic int 343155324Simpate_activate(device_t dev) 344155324Simp{ 345155324Simp struct ate_softc *sc; 346155324Simp int rid, err, i; 347155324Simp 348155324Simp sc = device_get_softc(dev); 349155324Simp rid = 0; 350155324Simp sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 351155324Simp RF_ACTIVE); 352155324Simp if (sc->mem_res == NULL) 353155324Simp goto errout; 354155324Simp rid = 0; 355155324Simp sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 356155324Simp RF_ACTIVE); 357163522Simp if (sc->irq_res == NULL) 358155324Simp goto errout; 359155324Simp 360155324Simp /* 361155324Simp * Allocate DMA tags and maps 362155324Simp */ 363183670Simp err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 364183670Simp BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 365183670Simp 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 366155324Simp if (err != 0) 367155324Simp goto errout; 368155324Simp for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 369155324Simp err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 370155324Simp if (err != 0) 371155324Simp goto errout; 372155324Simp } 373155324Simp /* 374155324Simp * Allocate our Rx buffers. This chip has a rx structure that's filled 375155324Simp * in 376155324Simp */ 377155324Simp 378155324Simp /* 379155324Simp * Allocate DMA tags and maps for RX. 380155324Simp */ 381183670Simp err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 382183670Simp BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 383183670Simp 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 384155324Simp if (err != 0) 385155324Simp goto errout; 386155324Simp 387155324Simp /* Dma TAG and MAP for the rx descriptors. */ 388183670Simp err = bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t), 389183670Simp 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 390155324Simp ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 391155324Simp ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 392155324Simp &sc->sc_mtx, &sc->rx_desc_tag); 393155324Simp if (err != 0) 394155324Simp goto errout; 395156831Simp if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 396156831Simp BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 397155324Simp goto errout; 398157562Simp if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 399155324Simp sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 400155324Simp ate_getaddr, sc, 0) != 0) 401155324Simp goto errout; 402155324Simp /* XXX TODO(5) Put this in ateinit_locked? */ 403155324Simp for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 404157562Simp sc->rx_buf_ptr = i; 405157562Simp if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 406157562Simp BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 407155324Simp goto errout; 408157562Simp if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 409157562Simp MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 410157562Simp goto errout; 411155324Simp } 412157562Simp sc->rx_buf_ptr = 0; 413156831Simp /* Flush the memory for the EMAC rx descriptor */ 414155324Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 415155324Simp /* Write the descriptor queue address. */ 416155324Simp WR4(sc, ETH_RBQP, sc->rx_desc_phys); 417155324Simp return (0); 418155324Simperrout: 419155324Simp ate_deactivate(dev); 420155324Simp return (ENOMEM); 421155324Simp} 422155324Simp 423155324Simpstatic void 424155324Simpate_deactivate(device_t dev) 425155324Simp{ 426155324Simp struct ate_softc *sc; 427155324Simp 428155324Simp sc = device_get_softc(dev); 429155324Simp /* XXX TODO(2) teardown busdma junk, below from fxp -- customize */ 430155324Simp#if 0 431155324Simp if (sc->fxp_mtag) { 432155324Simp for (i = 0; i < FXP_NRFABUFS; i++) { 433155324Simp rxp = &sc->fxp_desc.rx_list[i]; 434155324Simp if (rxp->rx_mbuf != NULL) { 435155324Simp bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 436155324Simp BUS_DMASYNC_POSTREAD); 437155324Simp bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 438155324Simp m_freem(rxp->rx_mbuf); 439155324Simp } 440155324Simp bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 441155324Simp } 442155324Simp bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 443155324Simp for (i = 0; i < FXP_NTXCB; i++) { 444155324Simp txp = &sc->fxp_desc.tx_list[i]; 445155324Simp if (txp->tx_mbuf != NULL) { 446155324Simp bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 447155324Simp BUS_DMASYNC_POSTWRITE); 448155324Simp bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 449155324Simp m_freem(txp->tx_mbuf); 450155324Simp } 451155324Simp bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 452155324Simp } 453155324Simp bus_dma_tag_destroy(sc->fxp_mtag); 454155324Simp } 455155324Simp if (sc->fxp_stag) 456155324Simp bus_dma_tag_destroy(sc->fxp_stag); 457155324Simp if (sc->cbl_tag) 458155324Simp bus_dma_tag_destroy(sc->cbl_tag); 459155324Simp if (sc->mcs_tag) 460155324Simp bus_dma_tag_destroy(sc->mcs_tag); 461155324Simp#endif 462155324Simp if (sc->intrhand) 463155324Simp bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 464155324Simp sc->intrhand = 0; 465155324Simp bus_generic_detach(sc->dev); 466155324Simp if (sc->miibus) 467155324Simp device_delete_child(sc->dev, sc->miibus); 468155324Simp if (sc->mem_res) 469155324Simp bus_release_resource(dev, SYS_RES_IOPORT, 470155324Simp rman_get_rid(sc->mem_res), sc->mem_res); 471155324Simp sc->mem_res = 0; 472155324Simp if (sc->irq_res) 473155324Simp bus_release_resource(dev, SYS_RES_IRQ, 474155324Simp rman_get_rid(sc->irq_res), sc->irq_res); 475155324Simp sc->irq_res = 0; 476155324Simp return; 477155324Simp} 478155324Simp 479155324Simp/* 480155324Simp * Change media according to request. 481155324Simp */ 482155324Simpstatic int 483155324Simpate_ifmedia_upd(struct ifnet *ifp) 484155324Simp{ 485155324Simp struct ate_softc *sc = ifp->if_softc; 486155324Simp struct mii_data *mii; 487155324Simp 488155324Simp mii = device_get_softc(sc->miibus); 489155324Simp ATE_LOCK(sc); 490155324Simp mii_mediachg(mii); 491155324Simp ATE_UNLOCK(sc); 492155324Simp return (0); 493155324Simp} 494155324Simp 495155324Simp/* 496155324Simp * Notify the world which media we're using. 497155324Simp */ 498155324Simpstatic void 499155324Simpate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 500155324Simp{ 501155324Simp struct ate_softc *sc = ifp->if_softc; 502155324Simp struct mii_data *mii; 503155324Simp 504155324Simp mii = device_get_softc(sc->miibus); 505155324Simp ATE_LOCK(sc); 506155324Simp mii_pollstat(mii); 507155324Simp ifmr->ifm_active = mii->mii_media_active; 508155324Simp ifmr->ifm_status = mii->mii_media_status; 509155324Simp ATE_UNLOCK(sc); 510155324Simp} 511155324Simp 512155324Simpstatic void 513163937Simpate_stat_update(struct ate_softc *sc, int active) 514163937Simp{ 515163937Simp /* 516163937Simp * The speed and full/half-duplex state needs to be reflected 517163937Simp * in the ETH_CFG register. 518163937Simp */ 519163937Simp if (IFM_SUBTYPE(active) == IFM_10_T) 520163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_SPD); 521163937Simp else 522163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_SPD); 523163937Simp if (active & IFM_FDX) 524163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_FD); 525163937Simp else 526163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_FD); 527163937Simp} 528163937Simp 529163937Simpstatic void 530155324Simpate_tick(void *xsc) 531155324Simp{ 532155324Simp struct ate_softc *sc = xsc; 533163937Simp struct ifnet *ifp = sc->ifp; 534155324Simp struct mii_data *mii; 535155324Simp int active; 536163937Simp uint32_t c; 537155324Simp 538155324Simp /* 539155324Simp * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 540155324Simp * the MII if there's a link if this bit is clear. Not sure if we 541155324Simp * should do the same thing here or not. 542155324Simp */ 543155324Simp ATE_ASSERT_LOCKED(sc); 544155324Simp if (sc->miibus != NULL) { 545155324Simp mii = device_get_softc(sc->miibus); 546155324Simp active = mii->mii_media_active; 547155324Simp mii_tick(mii); 548155324Simp if (mii->mii_media_status & IFM_ACTIVE && 549163937Simp active != mii->mii_media_active) 550163937Simp ate_stat_update(sc, mii->mii_media_active); 551155324Simp } 552155324Simp 553155324Simp /* 554155324Simp * Update the stats as best we can. When we're done, clear 555155324Simp * the status counters and start over. We're supposed to read these 556155324Simp * registers often enough that they won't overflow. Hopefully 557155324Simp * once a second is often enough. Some don't map well to 558155324Simp * the dot3Stats mib, so for those we just count them as general 559155324Simp * errors. Stats for iframes, ibutes, oframes and obytes are 560155324Simp * collected elsewhere. These registers zero on a read to prevent 561163937Simp * races. For all the collision stats, also update the collision 562163937Simp * stats for the interface. 563155324Simp */ 564155324Simp sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 565155324Simp sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 566163937Simp c = RD4(sc, ETH_SCOL); 567163937Simp ifp->if_collisions += c; 568163937Simp sc->mibdata.dot3StatsSingleCollisionFrames += c; 569163937Simp c = RD4(sc, ETH_MCOL); 570163937Simp sc->mibdata.dot3StatsMultipleCollisionFrames += c; 571163937Simp ifp->if_collisions += c; 572155324Simp sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 573155324Simp sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 574163937Simp c = RD4(sc, ETH_LCOL); 575163937Simp sc->mibdata.dot3StatsLateCollisions += c; 576163937Simp ifp->if_collisions += c; 577163937Simp c = RD4(sc, ETH_ECOL); 578163937Simp sc->mibdata.dot3StatsExcessiveCollisions += c; 579163937Simp ifp->if_collisions += c; 580155324Simp sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 581155324Simp sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 582155324Simp sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 583155324Simp /* 584155324Simp * not sure where to lump these, so count them against the errors 585155324Simp * for the interface. 586155324Simp */ 587163937Simp sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 588155324Simp sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 589155324Simp RD4(sc, ETH_USF); 590155324Simp 591155324Simp /* 592155324Simp * Schedule another timeout one second from now. 593155324Simp */ 594155324Simp callout_reset(&sc->tick_ch, hz, ate_tick, sc); 595155324Simp} 596155324Simp 597155324Simpstatic void 598155445Scognetate_set_mac(struct ate_softc *sc, u_char *eaddr) 599155445Scognet{ 600155445Scognet WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 601155445Scognet (eaddr[1] << 8) | eaddr[0]); 602155445Scognet WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 603155445Scognet} 604155445Scognet 605166573Simpstatic int 606155324Simpate_get_mac(struct ate_softc *sc, u_char *eaddr) 607155324Simp{ 608182477Sstas bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 609182477Sstas bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 610166573Simp uint32_t low, high; 611182477Sstas int i; 612155324Simp 613166573Simp /* 614166573Simp * The boot loader setup the MAC with an address, if one is set in 615182477Sstas * the loader. Grab one MAC address from the SA[1-4][HL] registers. 616166573Simp */ 617182477Sstas for (i = 0; i < 4; i++) { 618182477Sstas low = RD4(sc, sa_low_reg[i]); 619182477Sstas high = RD4(sc, sa_high_reg[i]); 620182477Sstas if ((low | (high & 0xffff)) != 0) { 621182477Sstas eaddr[0] = low & 0xff; 622182477Sstas eaddr[1] = (low >> 8) & 0xff; 623182477Sstas eaddr[2] = (low >> 16) & 0xff; 624182477Sstas eaddr[3] = (low >> 24) & 0xff; 625182477Sstas eaddr[4] = high & 0xff; 626182477Sstas eaddr[5] = (high >> 8) & 0xff; 627182477Sstas return (0); 628182477Sstas } 629182477Sstas } 630182477Sstas return (ENXIO); 631155324Simp} 632155324Simp 633155324Simpstatic void 634155324Simpate_intr(void *xsc) 635155324Simp{ 636155324Simp struct ate_softc *sc = xsc; 637163937Simp struct ifnet *ifp = sc->ifp; 638155324Simp int status; 639155324Simp int i; 640157562Simp void *bp; 641157562Simp struct mbuf *mb; 642157562Simp uint32_t rx_stat; 643156831Simp 644155324Simp status = RD4(sc, ETH_ISR); 645155324Simp if (status == 0) 646155324Simp return; 647155324Simp if (status & ETH_ISR_RCOM) { 648155324Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 649155324Simp BUS_DMASYNC_POSTREAD); 650157562Simp while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 651157562Simp i = sc->rx_buf_ptr; 652157562Simp sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 653157562Simp bp = sc->rx_buf[i]; 654156831Simp rx_stat = sc->rx_descs[i].status; 655156831Simp if ((rx_stat & ETH_LEN_MASK) == 0) { 656156831Simp printf("ignoring bogus 0 len packet\n"); 657163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 658163937Simp BUS_DMASYNC_PREWRITE); 659157562Simp sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 660156831Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 661163937Simp BUS_DMASYNC_POSTWRITE); 662156831Simp continue; 663155324Simp } 664156831Simp /* Flush memory for mbuf so we don't get stale bytes */ 665156831Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 666156831Simp BUS_DMASYNC_POSTREAD); 667163937Simp WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 668163937Simp 669156831Simp /* 670156831Simp * The length returned by the device includes the 671156831Simp * ethernet CRC calculation for the packet, but 672156831Simp * ifnet drivers are supposed to discard it. 673156831Simp */ 674157562Simp mb = m_devget(sc->rx_buf[i], 675157562Simp (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 676163937Simp ETHER_ALIGN, ifp, NULL); 677163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 678163937Simp BUS_DMASYNC_PREWRITE); 679157562Simp sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 680157562Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 681163937Simp BUS_DMASYNC_POSTWRITE); 682156831Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 683156831Simp BUS_DMASYNC_PREREAD); 684163937Simp if (mb != NULL) { 685163937Simp ifp->if_ipackets++; 686163937Simp (*ifp->if_input)(ifp, mb); 687163937Simp } 688163937Simp 689155324Simp } 690155324Simp } 691155324Simp if (status & ETH_ISR_TCOM) { 692156831Simp ATE_LOCK(sc); 693163937Simp /* XXX TSR register should be cleared */ 694156831Simp if (sc->sent_mbuf[0]) { 695179693Swkoszek bus_dmamap_sync(sc->mtag, sc->tx_map[0], 696163937Simp BUS_DMASYNC_POSTWRITE); 697155324Simp m_freem(sc->sent_mbuf[0]); 698163937Simp ifp->if_opackets++; 699156831Simp sc->sent_mbuf[0] = NULL; 700156831Simp } 701155324Simp if (sc->sent_mbuf[1]) { 702155324Simp if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 703179693Swkoszek bus_dmamap_sync(sc->mtag, sc->tx_map[1], 704163937Simp BUS_DMASYNC_POSTWRITE); 705155324Simp m_freem(sc->sent_mbuf[1]); 706163937Simp ifp->if_opackets++; 707155324Simp sc->txcur = 0; 708155324Simp sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 709155324Simp } else { 710155324Simp sc->sent_mbuf[0] = sc->sent_mbuf[1]; 711155324Simp sc->sent_mbuf[1] = NULL; 712155324Simp sc->txcur = 1; 713155324Simp } 714155324Simp } else { 715155324Simp sc->sent_mbuf[0] = NULL; 716155324Simp sc->txcur = 0; 717155324Simp } 718156831Simp /* 719156831Simp * We're no longer busy, so clear the busy flag and call the 720156831Simp * start routine to xmit more packets. 721156831Simp */ 722156831Simp sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 723156831Simp atestart_locked(sc->ifp); 724156831Simp ATE_UNLOCK(sc); 725155324Simp } 726155324Simp if (status & ETH_ISR_RBNA) { 727156831Simp printf("RBNA workaround\n"); 728155324Simp /* Workaround Errata #11 */ 729155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) &~ ETH_CTL_RE); 730155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_RE); 731155324Simp } 732155324Simp} 733155324Simp 734155324Simp/* 735155324Simp * Reset and initialize the chip 736155324Simp */ 737155324Simpstatic void 738155324Simpateinit_locked(void *xsc) 739155324Simp{ 740155324Simp struct ate_softc *sc = xsc; 741155324Simp struct ifnet *ifp = sc->ifp; 742163937Simp struct mii_data *mii; 743155324Simp 744155324Simp ATE_ASSERT_LOCKED(sc); 745155324Simp 746155324Simp /* 747155324Simp * XXX TODO(3) 748155324Simp * we need to turn on the EMAC clock in the pmc. With the 749155324Simp * default boot loader, this is already turned on. However, we 750155324Simp * need to think about how best to turn it on/off as the interface 751155324Simp * is brought up/down, as well as dealing with the mii bus... 752155324Simp * 753155324Simp * We also need to multiplex the pins correctly. 754155324Simp */ 755155324Simp 756155324Simp /* 757155324Simp * There are two different ways that the mii bus is connected 758155324Simp * to this chip. Select the right one based on a compile-time 759155324Simp * option. 760155324Simp */ 761159708Simp if (sc->use_rmii) 762159708Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_RMII); 763159708Simp else 764159708Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_RMII); 765159708Simp 766155324Simp /* 767155324Simp * Turn on the multicast hash, and write 0's to it. 768155324Simp */ 769155324Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_MTI); 770155324Simp WR4(sc, ETH_HSH, 0); 771155324Simp WR4(sc, ETH_HSL, 0); 772155324Simp 773155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 774156831Simp WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 775155324Simp 776155324Simp /* 777155324Simp * Boot loader fills in MAC address. If that's not the case, then 778155324Simp * we should set SA1L and SA1H here to the appropriate value. Note: 779155324Simp * the byte order is big endian, not little endian, so we have some 780155324Simp * swapping to do. Again, if we need it (which I don't think we do). 781155324Simp */ 782155324Simp ate_setmcast(sc); 783155324Simp 784165779Sticso /* enable big packets */ 785165779Sticso WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 786165779Sticso 787155324Simp /* 788155324Simp * Set 'running' flag, and clear output active flag 789155324Simp * and attempt to start the output 790155324Simp */ 791155324Simp ifp->if_drv_flags |= IFF_DRV_RUNNING; 792155324Simp ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 793163937Simp 794163937Simp mii = device_get_softc(sc->miibus); 795163937Simp mii_pollstat(mii); 796163937Simp ate_stat_update(sc, mii->mii_media_active); 797155324Simp atestart_locked(ifp); 798155324Simp 799155324Simp callout_reset(&sc->tick_ch, hz, ate_tick, sc); 800155324Simp} 801155324Simp 802155324Simp/* 803155324Simp * dequeu packets and transmit 804155324Simp */ 805155324Simpstatic void 806155324Simpatestart_locked(struct ifnet *ifp) 807155324Simp{ 808155324Simp struct ate_softc *sc = ifp->if_softc; 809155324Simp struct mbuf *m, *mdefrag; 810155324Simp bus_dma_segment_t segs[1]; 811163937Simp int nseg, e; 812155324Simp 813155324Simp ATE_ASSERT_LOCKED(sc); 814155324Simp if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 815155324Simp return; 816155324Simp 817156831Simp while (sc->txcur < ATE_MAX_TX_BUFFERS) { 818156831Simp /* 819156831Simp * check to see if there's room to put another packet into the 820156831Simp * xmit queue. The EMAC chip has a ping-pong buffer for xmit 821156831Simp * packets. We use OACTIVE to indicate "we can stuff more into 822156831Simp * our buffers (clear) or not (set)." 823156831Simp */ 824156831Simp if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 825156831Simp ifp->if_drv_flags |= IFF_DRV_OACTIVE; 826156831Simp return; 827156831Simp } 828156831Simp IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 829156831Simp if (m == 0) { 830156831Simp ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 831156831Simp return; 832156831Simp } 833163937Simp e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 834163937Simp segs, &nseg, 0); 835163937Simp if (e == EFBIG) { 836163937Simp mdefrag = m_defrag(m, M_DONTWAIT); 837163937Simp if (mdefrag == NULL) { 838163937Simp IFQ_DRV_PREPEND(&ifp->if_snd, m); 839163937Simp return; 840163937Simp } 841163937Simp m = mdefrag; 842163937Simp e = bus_dmamap_load_mbuf_sg(sc->mtag, 843163937Simp sc->tx_map[sc->txcur], m, segs, &nseg, 0); 844156831Simp } 845163937Simp if (e != 0) { 846156831Simp m_freem(m); 847156831Simp continue; 848156831Simp } 849156831Simp bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 850156831Simp BUS_DMASYNC_PREWRITE); 851155324Simp 852156831Simp /* 853156831Simp * tell the hardware to xmit the packet. 854156831Simp */ 855156831Simp WR4(sc, ETH_TAR, segs[0].ds_addr); 856156831Simp WR4(sc, ETH_TCR, segs[0].ds_len); 857155324Simp 858156831Simp /* 859156831Simp * Tap off here if there is a bpf listener. 860156831Simp */ 861156831Simp BPF_MTAP(ifp, m); 862155324Simp 863156831Simp sc->sent_mbuf[sc->txcur] = m; 864156831Simp sc->txcur++; 865156831Simp } 866155324Simp} 867155324Simp 868155324Simpstatic void 869155324Simpateinit(void *xsc) 870155324Simp{ 871155324Simp struct ate_softc *sc = xsc; 872155324Simp ATE_LOCK(sc); 873155324Simp ateinit_locked(sc); 874155324Simp ATE_UNLOCK(sc); 875155324Simp} 876155324Simp 877155324Simpstatic void 878155324Simpatestart(struct ifnet *ifp) 879155324Simp{ 880155324Simp struct ate_softc *sc = ifp->if_softc; 881155324Simp ATE_LOCK(sc); 882155324Simp atestart_locked(ifp); 883155324Simp ATE_UNLOCK(sc); 884155324Simp} 885155324Simp 886155324Simp/* 887155324Simp * Turn off interrupts, and stop the nic. Can be called with sc->ifp NULL 888155324Simp * so be careful. 889155324Simp */ 890155324Simpstatic void 891155324Simpatestop(struct ate_softc *sc) 892155324Simp{ 893155324Simp struct ifnet *ifp = sc->ifp; 894155324Simp 895155324Simp if (ifp) { 896155324Simp ifp->if_timer = 0; 897155324Simp ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 898155324Simp } 899155324Simp 900155324Simp callout_stop(&sc->tick_ch); 901155324Simp 902155324Simp /* 903155324Simp * Enable some parts of the MAC that are needed always (like the 904155324Simp * MII bus. This turns off the RE and TE bits, which will remain 905155405Scognet * off until ateinit() is called to turn them on. With RE and TE 906155324Simp * turned off, there's no DMA to worry about after this write. 907155324Simp */ 908155324Simp WR4(sc, ETH_CTL, ETH_CTL_MPE); 909155324Simp 910155324Simp /* 911155324Simp * Turn off all the configured options and revert to defaults. 912155324Simp */ 913155324Simp WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 914155324Simp 915155324Simp /* 916155324Simp * Turn off all the interrupts, and ack any pending ones by reading 917155324Simp * the ISR. 918155324Simp */ 919155324Simp WR4(sc, ETH_IDR, 0xffffffff); 920155324Simp RD4(sc, ETH_ISR); 921155324Simp 922155324Simp /* 923155324Simp * Clear out the Transmit and Receiver Status registers of any 924155324Simp * errors they may be reporting 925155324Simp */ 926155324Simp WR4(sc, ETH_TSR, 0xffffffff); 927155324Simp WR4(sc, ETH_RSR, 0xffffffff); 928155324Simp 929155324Simp /* 930155324Simp * XXX TODO(8) 931155324Simp * need to worry about the busdma resources? Yes, I think we need 932155324Simp * to sync and unload them. We may also need to release the mbufs 933155324Simp * that are assocaited with RX and TX operations. 934155324Simp */ 935155324Simp 936155324Simp /* 937155324Simp * XXX we should power down the EMAC if it isn't in use, after 938155324Simp * putting it into loopback mode. This saves about 400uA according 939155324Simp * to the datasheet. 940155324Simp */ 941155324Simp} 942155324Simp 943155324Simpstatic int 944155324Simpateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 945155324Simp{ 946155324Simp struct ate_softc *sc = ifp->if_softc; 947157562Simp struct mii_data *mii; 948157562Simp struct ifreq *ifr = (struct ifreq *)data; 949165779Sticso int mask, error = 0; 950155324Simp 951155324Simp switch (cmd) { 952155324Simp case SIOCSIFFLAGS: 953155324Simp ATE_LOCK(sc); 954155324Simp if ((ifp->if_flags & IFF_UP) == 0 && 955155324Simp ifp->if_drv_flags & IFF_DRV_RUNNING) { 956155324Simp ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 957155324Simp atestop(sc); 958155324Simp } else { 959155324Simp /* reinitialize card on any parameter change */ 960155324Simp ateinit_locked(sc); 961155324Simp } 962155324Simp ATE_UNLOCK(sc); 963155324Simp break; 964155324Simp 965155324Simp case SIOCADDMULTI: 966155324Simp case SIOCDELMULTI: 967155324Simp /* update multicast filter list. */ 968157562Simp ATE_LOCK(sc); 969155324Simp ate_setmcast(sc); 970157562Simp ATE_UNLOCK(sc); 971155324Simp error = 0; 972155324Simp break; 973155324Simp 974157562Simp case SIOCSIFMEDIA: 975157562Simp case SIOCGIFMEDIA: 976157562Simp mii = device_get_softc(sc->miibus); 977157562Simp error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 978157562Simp break; 979165779Sticso case SIOCSIFCAP: 980165779Sticso mask = ifp->if_capenable ^ ifr->ifr_reqcap; 981165779Sticso if (mask & IFCAP_VLAN_MTU) { 982165779Sticso ATE_LOCK(sc); 983165779Sticso if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 984165779Sticso WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 985165779Sticso ifp->if_capenable |= IFCAP_VLAN_MTU; 986165779Sticso } else { 987165779Sticso WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 988165779Sticso ifp->if_capenable &= ~IFCAP_VLAN_MTU; 989165779Sticso } 990165779Sticso ATE_UNLOCK(sc); 991165779Sticso } 992155324Simp default: 993155324Simp error = ether_ioctl(ifp, cmd, data); 994155324Simp break; 995155324Simp } 996155324Simp return (error); 997155324Simp} 998155324Simp 999155324Simpstatic void 1000155324Simpate_child_detached(device_t dev, device_t child) 1001155324Simp{ 1002155324Simp struct ate_softc *sc; 1003155324Simp 1004155324Simp sc = device_get_softc(dev); 1005155324Simp if (child == sc->miibus) 1006155324Simp sc->miibus = NULL; 1007155324Simp} 1008155324Simp 1009155324Simp/* 1010155324Simp * MII bus support routines. 1011155324Simp */ 1012155324Simpstatic int 1013155324Simpate_miibus_readreg(device_t dev, int phy, int reg) 1014155324Simp{ 1015155324Simp struct ate_softc *sc; 1016155324Simp int val; 1017155324Simp 1018155324Simp /* 1019155324Simp * XXX if we implement agressive power savings, then we need 1020155324Simp * XXX to make sure that the clock to the emac is on here 1021155324Simp */ 1022155324Simp 1023155324Simp sc = device_get_softc(dev); 1024155324Simp DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1025155324Simp WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1026155324Simp while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1027155324Simp continue; 1028155324Simp val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1029155324Simp 1030155324Simp return (val); 1031155324Simp} 1032155324Simp 1033155324Simpstatic void 1034155324Simpate_miibus_writereg(device_t dev, int phy, int reg, int data) 1035155324Simp{ 1036155324Simp struct ate_softc *sc; 1037155324Simp 1038155324Simp /* 1039155324Simp * XXX if we implement agressive power savings, then we need 1040155324Simp * XXX to make sure that the clock to the emac is on here 1041155324Simp */ 1042155324Simp 1043155324Simp sc = device_get_softc(dev); 1044155324Simp WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1045155324Simp while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1046155324Simp continue; 1047155324Simp return; 1048155324Simp} 1049155324Simp 1050155324Simpstatic device_method_t ate_methods[] = { 1051155324Simp /* Device interface */ 1052155324Simp DEVMETHOD(device_probe, ate_probe), 1053155324Simp DEVMETHOD(device_attach, ate_attach), 1054155324Simp DEVMETHOD(device_detach, ate_detach), 1055155324Simp 1056155324Simp /* Bus interface */ 1057155324Simp DEVMETHOD(bus_child_detached, ate_child_detached), 1058155324Simp 1059155324Simp /* MII interface */ 1060155324Simp DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1061155324Simp DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1062155324Simp 1063155324Simp { 0, 0 } 1064155324Simp}; 1065155324Simp 1066155324Simpstatic driver_t ate_driver = { 1067155324Simp "ate", 1068155324Simp ate_methods, 1069155324Simp sizeof(struct ate_softc), 1070155324Simp}; 1071155324Simp 1072155324SimpDRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1073155324SimpDRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1074155324SimpMODULE_DEPEND(ate, miibus, 1, 1, 1); 1075155324SimpMODULE_DEPEND(ate, ether, 1, 1, 1); 1076