if_ate.c revision 183670
1221420Sdes/*- 2224638Sbrooks * Copyright (c) 2006 M. Warner Losh. All rights reserved. 360573Skris * 492555Sdes * Redistribution and use in source and binary forms, with or without 560573Skris * modification, are permitted provided that the following conditions 660573Skris * are met: 760573Skris * 1. Redistributions of source code must retain the above copyright 860573Skris * notice, this list of conditions and the following disclaimer. 960573Skris * 2. Redistributions in binary form must reproduce the above copyright 1060573Skris * notice, this list of conditions and the following disclaimer in the 1160573Skris * documentation and/or other materials provided with the distribution. 1260573Skris * 1360573Skris * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1460573Skris * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1560573Skris * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1660573Skris * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1760573Skris * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 1860573Skris * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 1960573Skris * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2060573Skris * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2160573Skris * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2260573Skris * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2360573Skris */ 2460573Skris 2560573Skris/* TODO: (in no order) 2660573Skris * 2760573Skris * 8) Need to sync busdma goo in atestop 2860573Skris * 9) atestop should maybe free the mbufs? 29162852Sdes * 30162852Sdes * 1) detach 31162852Sdes * 2) Free dma setup 32162852Sdes * 3) Turn on the clock in pmc? Turn off? 33162852Sdes */ 34162852Sdes 35162852Sdes#include <sys/cdefs.h> 36162852Sdes__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 183670 2008-10-07 17:23:16Z imp $"); 3776259Sgreen 3876259Sgreen#include <sys/param.h> 39162852Sdes#include <sys/systm.h> 4060573Skris#include <sys/bus.h> 4160573Skris#include <sys/kernel.h> 4261209Skris#include <sys/mbuf.h> 4360573Skris#include <sys/malloc.h> 4476259Sgreen#include <sys/module.h> 45162852Sdes#include <sys/rman.h> 4660573Skris#include <sys/socket.h> 4776259Sgreen#include <sys/sockio.h> 4876259Sgreen#include <sys/sysctl.h> 4976259Sgreen#include <machine/bus.h> 5076259Sgreen 5198675Sdes#include <net/ethernet.h> 52204917Sdes#include <net/if.h> 5360573Skris#include <net/if_arp.h> 54162852Sdes#include <net/if_dl.h> 55162852Sdes#include <net/if_media.h> 56162852Sdes#include <net/if_mib.h> 57162852Sdes#include <net/if_types.h> 58162852Sdes 59162852Sdes#ifdef INET 60162852Sdes#include <netinet/in.h> 61162852Sdes#include <netinet/in_systm.h> 6292555Sdes#include <netinet/in_var.h> 6392555Sdes#include <netinet/ip.h> 6492555Sdes#endif 6576259Sgreen 66221420Sdes#include <net/bpf.h> 67221420Sdes#include <net/bpfdesc.h> 68221420Sdes 69221420Sdes#include <dev/mii/mii.h> 70221420Sdes#include <dev/mii/miivar.h> 71221420Sdes#include <arm/at91/if_atereg.h> 72221420Sdes 73221420Sdes#include "miibus_if.h" 74221420Sdes 75221420Sdes#define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 76221420Sdes#define ATE_MAX_RX_BUFFERS 64 77221420Sdes 78221420Sdesstruct ate_softc 79221420Sdes{ 80221420Sdes struct ifnet *ifp; /* ifnet pointer */ 81221420Sdes struct mtx sc_mtx; /* basically a perimeter lock */ 82221420Sdes device_t dev; /* Myself */ 83221420Sdes device_t miibus; /* My child miibus */ 84221420Sdes void *intrhand; /* Interrupt handle */ 85221420Sdes struct resource *irq_res; /* IRQ resource */ 86221420Sdes struct resource *mem_res; /* Memory resource */ 87221420Sdes struct callout tick_ch; /* Tick callout */ 88221420Sdes bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 89221420Sdes bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 90221420Sdes struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 91221420Sdes bus_dma_tag_t rxtag; 92221420Sdes bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 93221420Sdes void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 94240075Sdes int rx_buf_ptr; 95224638Sbrooks bus_dma_tag_t rx_desc_tag; 9692555Sdes bus_dmamap_t rx_desc_map; 97224638Sbrooks int txcur; /* current tx map pointer */ 98224638Sbrooks bus_addr_t rx_desc_phys; 99224638Sbrooks eth_rx_desc_t *rx_descs; 100224638Sbrooks int use_rmii; 10176259Sgreen struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 10260573Skris}; 103149749Sdes 10476259Sgreenstatic inline uint32_t 10576259SgreenRD4(struct ate_softc *sc, bus_size_t off) 10698675Sdes{ 10798675Sdes return bus_read_4(sc->mem_res, off); 10898675Sdes} 10998675Sdes 11098675Sdesstatic inline void 11198675SdesWR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 11260573Skris{ 11376259Sgreen bus_write_4(sc->mem_res, off, val); 11476259Sgreen} 11576259Sgreen 11660573Skris#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 11760573Skris#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 11876259Sgreen#define ATE_LOCK_INIT(_sc) \ 11992555Sdes mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 120113908Sdes MTX_NETWORK_LOCK, MTX_DEF) 12161209Skris#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 12276259Sgreen#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 123181111Sdes#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 12476259Sgreen 12561209Skrisstatic devclass_t ate_devclass; 126162852Sdes 12761209Skris/* ifnet entry points */ 12876259Sgreen 12976259Sgreenstatic void ateinit_locked(void *); 13061209Skrisstatic void atestart_locked(struct ifnet *); 13161209Skris 13276259Sgreenstatic void ateinit(void *); 13361209Skrisstatic void atestart(struct ifnet *); 13461209Skrisstatic void atestop(struct ate_softc *); 135221420Sdesstatic int ateioctl(struct ifnet * ifp, u_long, caddr_t); 13676259Sgreen 13761209Skris/* bus entry points */ 13876259Sgreen 13976259Sgreenstatic int ate_probe(device_t dev); 140113908Sdesstatic int ate_attach(device_t dev); 141113908Sdesstatic int ate_detach(device_t dev); 14276259Sgreenstatic void ate_intr(void *); 14376259Sgreen 144181111Sdes/* helper routines */ 14576259Sgreenstatic int ate_activate(device_t dev); 14676259Sgreenstatic void ate_deactivate(device_t dev); 14761209Skrisstatic int ate_ifmedia_upd(struct ifnet *ifp); 14861209Skrisstatic void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 14992555Sdesstatic int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 15076259Sgreenstatic void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 15160573Skris 152149749Sdes/* 15360573Skris * The AT91 family of products has the ethernet called EMAC. However, 15476259Sgreen * it isn't self identifying. It is anticipated that the parent bus 15576259Sgreen * code will take care to only add ate devices where they really are. As 15676259Sgreen * such, we do nothing here to identify the device and just set its name. 15760573Skris */ 15860573Skrisstatic int 159181111Sdesate_probe(device_t dev) 16092555Sdes{ 16192555Sdes device_set_desc(dev, "EMAC"); 16260573Skris return (0); 16392555Sdes} 16460573Skris 16560573Skrisstatic int 16692555Sdesate_attach(device_t dev) 16792555Sdes{ 16869587Sgreen struct ate_softc *sc = device_get_softc(dev); 16992555Sdes struct ifnet *ifp = NULL; 17092555Sdes struct sysctl_ctx_list *sctx; 17192555Sdes struct sysctl_oid *soid; 17269587Sgreen int err; 17369587Sgreen u_char eaddr[ETHER_ADDR_LEN]; 17476259Sgreen uint32_t rnd; 17576259Sgreen 17669587Sgreen sc->dev = dev; 17792555Sdes err = ate_activate(dev); 17869587Sgreen if (err) 17976259Sgreen goto out; 18076259Sgreen 18176259Sgreen sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 18276259Sgreen 18369587Sgreen /* Sysctls */ 184113908Sdes sctx = device_get_sysctl_ctx(dev); 18592555Sdes soid = device_get_sysctl_tree(dev); 18692555Sdes SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 18776259Sgreen CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 18869587Sgreen 18976259Sgreen /* calling atestop before ifp is set is OK */ 19076259Sgreen atestop(sc); 19176259Sgreen ATE_LOCK_INIT(sc); 19276259Sgreen callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 19376259Sgreen 19476259Sgreen if ((err = ate_get_mac(sc, eaddr)) != 0) { 19569587Sgreen /* 19669587Sgreen * No MAC address configured. Generate the random one. 19760573Skris */ 19876259Sgreen if (bootverbose) 19960573Skris device_printf(dev, 200137015Sdes "Generating random ethernet address.\n"); 20198675Sdes rnd = arc4random(); 202149749Sdes 20398675Sdes /* 20476259Sgreen * Set OUI to convenient locally assigned address. 'b' 20576259Sgreen * is 0x62, which has the locally assigned bit set, and 20676259Sgreen * the broadcast/multicast bit clear. 20760573Skris */ 20876259Sgreen eaddr[0] = 'b'; 20976259Sgreen eaddr[1] = 's'; 21076259Sgreen eaddr[2] = 'd'; 21176259Sgreen eaddr[3] = (rnd >> 16) & 0xff; 21276259Sgreen eaddr[4] = (rnd >> 8) & 0xff; 21398675Sdes eaddr[5] = rnd & 0xff; 21498675Sdes } 21598675Sdes ate_set_mac(sc, eaddr); 21698675Sdes 21798675Sdes sc->ifp = ifp = if_alloc(IFT_ETHER); 21898675Sdes if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 21998675Sdes device_printf(dev, "Cannot find my PHY.\n"); 220137015Sdes err = ENXIO; 221137015Sdes goto out; 222137015Sdes } 22398675Sdes 22476259Sgreen ifp->if_softc = sc; 22576259Sgreen if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 22676259Sgreen ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 22776259Sgreen ifp->if_capabilities |= IFCAP_VLAN_MTU; 22876259Sgreen ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 22960573Skris ifp->if_start = atestart; 23060573Skris ifp->if_ioctl = ateioctl; 231181111Sdes ifp->if_init = ateinit; 23276259Sgreen ifp->if_baudrate = 10000000; 23392555Sdes IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 23460573Skris ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 23576259Sgreen IFQ_SET_READY(&ifp->if_snd); 236149749Sdes ifp->if_timer = 0; 23776259Sgreen ifp->if_linkmib = &sc->mibdata; 23860573Skris ifp->if_linkmiblen = sizeof(sc->mibdata); 23976259Sgreen sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 24076259Sgreen 24176259Sgreen ether_ifattach(ifp, eaddr); 24260573Skris 24376259Sgreen /* 24476259Sgreen * Activate the interrupt 24560573Skris */ 24676259Sgreen err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 24776259Sgreen NULL, ate_intr, sc, &sc->intrhand); 24876259Sgreen if (err) { 24976259Sgreen ether_ifdetach(ifp); 25076259Sgreen ATE_LOCK_DESTROY(sc); 25199060Sdes } 25299060Sdesout:; 25392555Sdes if (err) 25460573Skris ate_deactivate(dev); 25576259Sgreen if (err && ifp) 25660573Skris if_free(ifp); 25760573Skris return (err); 25876259Sgreen} 25976259Sgreen 26069587Sgreenstatic int 26176259Sgreenate_detach(device_t dev) 26269587Sgreen{ 263162852Sdes return EBUSY; /* XXX TODO(1) */ 26476259Sgreen} 26576259Sgreen 26676259Sgreenstatic void 26776259Sgreenate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 26869587Sgreen{ 26976259Sgreen struct ate_softc *sc; 27092555Sdes 27169587Sgreen if (error != 0) 27276259Sgreen return; 27369587Sgreen sc = (struct ate_softc *)arg; 27469587Sgreen sc->rx_desc_phys = segs[0].ds_addr; 27592555Sdes} 27676259Sgreen 27760573Skrisstatic void 27876259Sgreenate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 27976259Sgreen{ 28060573Skris struct ate_softc *sc; 28176259Sgreen int i; 28260573Skris 283113908Sdes if (error != 0) 284113908Sdes return; 285113908Sdes sc = (struct ate_softc *)arg; 286113908Sdes i = sc->rx_buf_ptr; 28776259Sgreen 28860573Skris /* 28960573Skris * For the last buffer, set the wrap bit so the controller 29060573Skris * restarts from the first descriptor. 29192555Sdes */ 29260573Skris bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 29360573Skris if (i == ATE_MAX_RX_BUFFERS - 1) 29476259Sgreen sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 29560573Skris else 296181111Sdes sc->rx_descs[i].addr = segs[0].ds_addr; 297181111Sdes bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 29892555Sdes sc->rx_descs[i].status = 0; 29969587Sgreen /* Flush the memory in the mbuf */ 30060573Skris bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 30160573Skris} 30260573Skris 30360573Skris/* 30492555Sdes * Compute the multicast filter for this device using the standard 30592555Sdes * algorithm. I wonder why this isn't in ether somewhere as a lot 30660573Skris * of different MAC chips use this method (or the reverse the bits) 307162852Sdes * method. 30892555Sdes */ 30960573Skrisstatic void 31060573Skrisate_setmcast(struct ate_softc *sc) 31176259Sgreen{ 31260573Skris uint32_t index; 313181111Sdes uint32_t mcaf[2]; 314181111Sdes u_char *af = (u_char *) mcaf; 315181111Sdes struct ifmultiaddr *ifma; 31660573Skris 31776259Sgreen mcaf[0] = 0; 31876259Sgreen mcaf[1] = 0; 31976259Sgreen 32060573Skris IF_ADDR_LOCK(sc->ifp); 32160573Skris TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 32260573Skris if (ifma->ifma_addr->sa_family != AF_LINK) 32360573Skris continue; 324162852Sdes index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 32592555Sdes ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 32660573Skris af[index >> 3] |= 1 << (index & 7); 32760573Skris } 32876259Sgreen IF_ADDR_UNLOCK(sc->ifp); 32960573Skris 33060573Skris /* 331149749Sdes * Write the hash to the hash register. This card can also 332149749Sdes * accept unicast packets as well as multicast packets using this 333149749Sdes * register for easier bridging operations, but we don't take 334149749Sdes * advantage of that. Locks here are to avoid LOR with the 33560573Skris * IF_ADDR_LOCK, but might not be strictly necessary. 336149749Sdes */ 33760573Skris WR4(sc, ETH_HSL, mcaf[0]); 33860573Skris WR4(sc, ETH_HSH, mcaf[1]); 33960573Skris} 34060573Skris 34160573Skrisstatic int 342162852Sdesate_activate(device_t dev) 34392555Sdes{ 34460573Skris struct ate_softc *sc; 34560573Skris int rid, err, i; 34676259Sgreen 34760573Skris sc = device_get_softc(dev); 348181111Sdes rid = 0; 34969587Sgreen sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 350113908Sdes RF_ACTIVE); 351157016Sdes if (sc->mem_res == NULL) 352137015Sdes goto errout; 353137015Sdes rid = 0; 354157016Sdes sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 355157016Sdes RF_ACTIVE); 356113908Sdes if (sc->irq_res == NULL) 357157016Sdes goto errout; 358162852Sdes 359162852Sdes /* 360162852Sdes * Allocate DMA tags and maps 361162852Sdes */ 362221420Sdes err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 363221420Sdes BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 364221420Sdes 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 365221420Sdes if (err != 0) 366162852Sdes goto errout; 36769587Sgreen for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 36860573Skris err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 36960573Skris if (err != 0) 370157016Sdes goto errout; 37192555Sdes } 37260573Skris /* 37360573Skris * Allocate our Rx buffers. This chip has a rx structure that's filled 37476259Sgreen * in 37576259Sgreen */ 37660573Skris 37776259Sgreen /* 37876259Sgreen * Allocate DMA tags and maps for RX. 37976259Sgreen */ 38076259Sgreen err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 38160573Skris BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 38260573Skris 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 383126274Sdes if (err != 0) 384113908Sdes goto errout; 385113908Sdes 386113908Sdes /* Dma TAG and MAP for the rx descriptors. */ 387113908Sdes err = bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t), 388113908Sdes 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 389113908Sdes ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 390113908Sdes ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 391113908Sdes &sc->sc_mtx, &sc->rx_desc_tag); 392113908Sdes if (err != 0) 393113908Sdes goto errout; 394113908Sdes if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 395113908Sdes BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 396113908Sdes goto errout; 397113908Sdes if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 398113908Sdes sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 399113908Sdes ate_getaddr, sc, 0) != 0) 400113908Sdes goto errout; 401113908Sdes /* XXX TODO(5) Put this in ateinit_locked? */ 402113908Sdes for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 403113908Sdes sc->rx_buf_ptr = i; 404113908Sdes if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 405113908Sdes BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 406113908Sdes goto errout; 40792555Sdes if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 40876259Sgreen MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 40960573Skris goto errout; 41076259Sgreen } 41176259Sgreen sc->rx_buf_ptr = 0; 41276259Sgreen /* Flush the memory for the EMAC rx descriptor */ 41376259Sgreen bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 414149749Sdes /* Write the descriptor queue address. */ 415113908Sdes WR4(sc, ETH_RBQP, sc->rx_desc_phys); 416224638Sbrooks return (0); 417224638Sbrookserrout: 418224638Sbrooks ate_deactivate(dev); 41960573Skris return (ENOMEM); 420113908Sdes} 421113908Sdes 42260573Skrisstatic void 42376259Sgreenate_deactivate(device_t dev) 42476259Sgreen{ 42576259Sgreen struct ate_softc *sc; 42676259Sgreen 42776259Sgreen sc = device_get_softc(dev); 42876259Sgreen /* XXX TODO(2) teardown busdma junk, below from fxp -- customize */ 42976259Sgreen#if 0 43076259Sgreen if (sc->fxp_mtag) { 431204917Sdes for (i = 0; i < FXP_NRFABUFS; i++) { 432204917Sdes rxp = &sc->fxp_desc.rx_list[i]; 433204917Sdes if (rxp->rx_mbuf != NULL) { 434204917Sdes bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 435204917Sdes BUS_DMASYNC_POSTREAD); 436204917Sdes bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 437204917Sdes m_freem(rxp->rx_mbuf); 438204917Sdes } 439204917Sdes bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 440204917Sdes } 44176259Sgreen bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 442224638Sbrooks for (i = 0; i < FXP_NTXCB; i++) { 443224638Sbrooks txp = &sc->fxp_desc.tx_list[i]; 444224638Sbrooks if (txp->tx_mbuf != NULL) { 445224638Sbrooks bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 44660573Skris BUS_DMASYNC_POSTWRITE); 447162852Sdes bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 44876259Sgreen m_freem(txp->tx_mbuf); 449181111Sdes } 450181111Sdes bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 45160573Skris } 45260573Skris bus_dma_tag_destroy(sc->fxp_mtag); 45360573Skris } 45476259Sgreen if (sc->fxp_stag) 45576259Sgreen bus_dma_tag_destroy(sc->fxp_stag); 45676259Sgreen if (sc->cbl_tag) 457224638Sbrooks bus_dma_tag_destroy(sc->cbl_tag); 458224638Sbrooks if (sc->mcs_tag) 459224638Sbrooks bus_dma_tag_destroy(sc->mcs_tag); 460231584Sed#endif 461224638Sbrooks if (sc->intrhand) 462224638Sbrooks bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 463224638Sbrooks sc->intrhand = 0; 464224638Sbrooks bus_generic_detach(sc->dev); 465224638Sbrooks if (sc->miibus) 466231584Sed device_delete_child(sc->dev, sc->miibus); 467224638Sbrooks if (sc->mem_res) 46860573Skris bus_release_resource(dev, SYS_RES_IOPORT, 46960573Skris rman_get_rid(sc->mem_res), sc->mem_res); 47076259Sgreen sc->mem_res = 0; 47176259Sgreen if (sc->irq_res) 47276259Sgreen bus_release_resource(dev, SYS_RES_IRQ, 47360573Skris rman_get_rid(sc->irq_res), sc->irq_res); 47476259Sgreen sc->irq_res = 0; 47576259Sgreen return; 47660573Skris} 47760573Skris 47860573Skris/* 47976259Sgreen * Change media according to request. 48092555Sdes */ 48192555Sdesstatic int 48292555Sdesate_ifmedia_upd(struct ifnet *ifp) 48392555Sdes{ 48476259Sgreen struct ate_softc *sc = ifp->if_softc; 48576259Sgreen struct mii_data *mii; 48660573Skris 48761209Skris mii = device_get_softc(sc->miibus); 48876259Sgreen ATE_LOCK(sc); 48976259Sgreen mii_mediachg(mii); 490113908Sdes ATE_UNLOCK(sc); 491126274Sdes return (0); 492149749Sdes} 493113908Sdes 494113908Sdes/* 495113908Sdes * Notify the world which media we're using. 496113908Sdes */ 49776259Sgreenstatic void 49876259Sgreenate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 49960573Skris{ 50060573Skris struct ate_softc *sc = ifp->if_softc; 50192555Sdes struct mii_data *mii; 502157016Sdes 503157016Sdes mii = device_get_softc(sc->miibus); 50460573Skris ATE_LOCK(sc); 50576259Sgreen mii_pollstat(mii); 50676259Sgreen ifmr->ifm_active = mii->mii_media_active; 50776259Sgreen ifmr->ifm_status = mii->mii_media_status; 508149749Sdes ATE_UNLOCK(sc); 509157016Sdes} 510149749Sdes 51160573Skrisstatic void 512157016Sdesate_stat_update(struct ate_softc *sc, int active) 513157016Sdes{ 514162852Sdes /* 515149749Sdes * The speed and full/half-duplex state needs to be reflected 51676259Sgreen * in the ETH_CFG register. 51776259Sgreen */ 51876259Sgreen if (IFM_SUBTYPE(active) == IFM_10_T) 51976259Sgreen WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_SPD); 520157016Sdes else 52192555Sdes WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_SPD); 52292555Sdes if (active & IFM_FDX) 523157016Sdes WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_FD); 52476259Sgreen else 52576259Sgreen WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_FD); 52676259Sgreen} 52776259Sgreen 52876259Sgreenstatic void 52976259Sgreenate_tick(void *xsc) 53076259Sgreen{ 53176259Sgreen struct ate_softc *sc = xsc; 53276259Sgreen struct ifnet *ifp = sc->ifp; 53376259Sgreen struct mii_data *mii; 534157016Sdes int active; 53592555Sdes uint32_t c; 53692555Sdes 537157016Sdes /* 53876259Sgreen * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 53976259Sgreen * the MII if there's a link if this bit is clear. Not sure if we 54076259Sgreen * should do the same thing here or not. 54176259Sgreen */ 54276259Sgreen ATE_ASSERT_LOCKED(sc); 54376259Sgreen if (sc->miibus != NULL) { 54476259Sgreen mii = device_get_softc(sc->miibus); 54576259Sgreen active = mii->mii_media_active; 54676259Sgreen mii_tick(mii); 54776259Sgreen if (mii->mii_media_status & IFM_ACTIVE && 54876259Sgreen active != mii->mii_media_active) 54976259Sgreen ate_stat_update(sc, mii->mii_media_active); 55076259Sgreen } 55176259Sgreen 55276259Sgreen /* 553157016Sdes * Update the stats as best we can. When we're done, clear 55476259Sgreen * the status counters and start over. We're supposed to read these 55576259Sgreen * registers often enough that they won't overflow. Hopefully 556149749Sdes * once a second is often enough. Some don't map well to 55776259Sgreen * the dot3Stats mib, so for those we just count them as general 558157016Sdes * errors. Stats for iframes, ibutes, oframes and obytes are 559157016Sdes * collected elsewhere. These registers zero on a read to prevent 560157016Sdes * races. For all the collision stats, also update the collision 561157016Sdes * stats for the interface. 56260573Skris */ 563113908Sdes sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 56460573Skris sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 56576259Sgreen c = RD4(sc, ETH_SCOL); 56676259Sgreen ifp->if_collisions += c; 567162852Sdes sc->mibdata.dot3StatsSingleCollisionFrames += c; 568162852Sdes c = RD4(sc, ETH_MCOL); 56976259Sgreen sc->mibdata.dot3StatsMultipleCollisionFrames += c; 57076259Sgreen ifp->if_collisions += c; 57176259Sgreen sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 57260573Skris sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 57360573Skris c = RD4(sc, ETH_LCOL); 57476259Sgreen sc->mibdata.dot3StatsLateCollisions += c; 57576259Sgreen ifp->if_collisions += c; 57676259Sgreen c = RD4(sc, ETH_ECOL); 57776259Sgreen sc->mibdata.dot3StatsExcessiveCollisions += c; 57876259Sgreen ifp->if_collisions += c; 57976259Sgreen sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 58076259Sgreen sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 58176259Sgreen sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 58276259Sgreen /* 58376259Sgreen * not sure where to lump these, so count them against the errors 58476259Sgreen * for the interface. 585137015Sdes */ 586137015Sdes sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 587137015Sdes sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 588137015Sdes RD4(sc, ETH_USF); 589137015Sdes 590137015Sdes /* 591137015Sdes * Schedule another timeout one second from now. 592137015Sdes */ 593137015Sdes callout_reset(&sc->tick_ch, hz, ate_tick, sc); 594137015Sdes} 595137015Sdes 596137015Sdesstatic void 597149749Sdesate_set_mac(struct ate_softc *sc, u_char *eaddr) 598137015Sdes{ 599137015Sdes WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 600137015Sdes (eaddr[1] << 8) | eaddr[0]); 601137015Sdes WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 602137015Sdes} 603149749Sdes 604137015Sdesstatic int 605137015Sdesate_get_mac(struct ate_softc *sc, u_char *eaddr) 606137015Sdes{ 607137015Sdes bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 608137015Sdes bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 609137015Sdes uint32_t low, high; 610137015Sdes int i; 611137015Sdes 612137015Sdes /* 613137015Sdes * The boot loader setup the MAC with an address, if one is set in 614137015Sdes * the loader. Grab one MAC address from the SA[1-4][HL] registers. 615137015Sdes */ 616137015Sdes for (i = 0; i < 4; i++) { 617137015Sdes low = RD4(sc, sa_low_reg[i]); 618221420Sdes high = RD4(sc, sa_high_reg[i]); 61976259Sgreen if ((low | (high & 0xffff)) != 0) { 62076259Sgreen eaddr[0] = low & 0xff; 62176259Sgreen eaddr[1] = (low >> 8) & 0xff; 622221420Sdes eaddr[2] = (low >> 16) & 0xff; 62376259Sgreen eaddr[3] = (low >> 24) & 0xff; 62476259Sgreen eaddr[4] = high & 0xff; 625181111Sdes eaddr[5] = (high >> 8) & 0xff; 62676259Sgreen return (0); 62776259Sgreen } 62876259Sgreen } 62976259Sgreen return (ENXIO); 63076259Sgreen} 63176259Sgreen 63276259Sgreenstatic void 63376259Sgreenate_intr(void *xsc) 63476259Sgreen{ 635 struct ate_softc *sc = xsc; 636 struct ifnet *ifp = sc->ifp; 637 int status; 638 int i; 639 void *bp; 640 struct mbuf *mb; 641 uint32_t rx_stat; 642 643 status = RD4(sc, ETH_ISR); 644 if (status == 0) 645 return; 646 if (status & ETH_ISR_RCOM) { 647 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 648 BUS_DMASYNC_POSTREAD); 649 while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 650 i = sc->rx_buf_ptr; 651 sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 652 bp = sc->rx_buf[i]; 653 rx_stat = sc->rx_descs[i].status; 654 if ((rx_stat & ETH_LEN_MASK) == 0) { 655 printf("ignoring bogus 0 len packet\n"); 656 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 657 BUS_DMASYNC_PREWRITE); 658 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 659 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 660 BUS_DMASYNC_POSTWRITE); 661 continue; 662 } 663 /* Flush memory for mbuf so we don't get stale bytes */ 664 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 665 BUS_DMASYNC_POSTREAD); 666 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 667 668 /* 669 * The length returned by the device includes the 670 * ethernet CRC calculation for the packet, but 671 * ifnet drivers are supposed to discard it. 672 */ 673 mb = m_devget(sc->rx_buf[i], 674 (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 675 ETHER_ALIGN, ifp, NULL); 676 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 677 BUS_DMASYNC_PREWRITE); 678 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 679 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 680 BUS_DMASYNC_POSTWRITE); 681 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 682 BUS_DMASYNC_PREREAD); 683 if (mb != NULL) { 684 ifp->if_ipackets++; 685 (*ifp->if_input)(ifp, mb); 686 } 687 688 } 689 } 690 if (status & ETH_ISR_TCOM) { 691 ATE_LOCK(sc); 692 /* XXX TSR register should be cleared */ 693 if (sc->sent_mbuf[0]) { 694 bus_dmamap_sync(sc->mtag, sc->tx_map[0], 695 BUS_DMASYNC_POSTWRITE); 696 m_freem(sc->sent_mbuf[0]); 697 ifp->if_opackets++; 698 sc->sent_mbuf[0] = NULL; 699 } 700 if (sc->sent_mbuf[1]) { 701 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 702 bus_dmamap_sync(sc->mtag, sc->tx_map[1], 703 BUS_DMASYNC_POSTWRITE); 704 m_freem(sc->sent_mbuf[1]); 705 ifp->if_opackets++; 706 sc->txcur = 0; 707 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 708 } else { 709 sc->sent_mbuf[0] = sc->sent_mbuf[1]; 710 sc->sent_mbuf[1] = NULL; 711 sc->txcur = 1; 712 } 713 } else { 714 sc->sent_mbuf[0] = NULL; 715 sc->txcur = 0; 716 } 717 /* 718 * We're no longer busy, so clear the busy flag and call the 719 * start routine to xmit more packets. 720 */ 721 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 722 atestart_locked(sc->ifp); 723 ATE_UNLOCK(sc); 724 } 725 if (status & ETH_ISR_RBNA) { 726 printf("RBNA workaround\n"); 727 /* Workaround Errata #11 */ 728 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) &~ ETH_CTL_RE); 729 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_RE); 730 } 731} 732 733/* 734 * Reset and initialize the chip 735 */ 736static void 737ateinit_locked(void *xsc) 738{ 739 struct ate_softc *sc = xsc; 740 struct ifnet *ifp = sc->ifp; 741 struct mii_data *mii; 742 743 ATE_ASSERT_LOCKED(sc); 744 745 /* 746 * XXX TODO(3) 747 * we need to turn on the EMAC clock in the pmc. With the 748 * default boot loader, this is already turned on. However, we 749 * need to think about how best to turn it on/off as the interface 750 * is brought up/down, as well as dealing with the mii bus... 751 * 752 * We also need to multiplex the pins correctly. 753 */ 754 755 /* 756 * There are two different ways that the mii bus is connected 757 * to this chip. Select the right one based on a compile-time 758 * option. 759 */ 760 if (sc->use_rmii) 761 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_RMII); 762 else 763 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_RMII); 764 765 /* 766 * Turn on the multicast hash, and write 0's to it. 767 */ 768 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_MTI); 769 WR4(sc, ETH_HSH, 0); 770 WR4(sc, ETH_HSL, 0); 771 772 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 773 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 774 775 /* 776 * Boot loader fills in MAC address. If that's not the case, then 777 * we should set SA1L and SA1H here to the appropriate value. Note: 778 * the byte order is big endian, not little endian, so we have some 779 * swapping to do. Again, if we need it (which I don't think we do). 780 */ 781 ate_setmcast(sc); 782 783 /* enable big packets */ 784 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 785 786 /* 787 * Set 'running' flag, and clear output active flag 788 * and attempt to start the output 789 */ 790 ifp->if_drv_flags |= IFF_DRV_RUNNING; 791 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 792 793 mii = device_get_softc(sc->miibus); 794 mii_pollstat(mii); 795 ate_stat_update(sc, mii->mii_media_active); 796 atestart_locked(ifp); 797 798 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 799} 800 801/* 802 * dequeu packets and transmit 803 */ 804static void 805atestart_locked(struct ifnet *ifp) 806{ 807 struct ate_softc *sc = ifp->if_softc; 808 struct mbuf *m, *mdefrag; 809 bus_dma_segment_t segs[1]; 810 int nseg, e; 811 812 ATE_ASSERT_LOCKED(sc); 813 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 814 return; 815 816 while (sc->txcur < ATE_MAX_TX_BUFFERS) { 817 /* 818 * check to see if there's room to put another packet into the 819 * xmit queue. The EMAC chip has a ping-pong buffer for xmit 820 * packets. We use OACTIVE to indicate "we can stuff more into 821 * our buffers (clear) or not (set)." 822 */ 823 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 824 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 825 return; 826 } 827 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 828 if (m == 0) { 829 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 830 return; 831 } 832 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 833 segs, &nseg, 0); 834 if (e == EFBIG) { 835 mdefrag = m_defrag(m, M_DONTWAIT); 836 if (mdefrag == NULL) { 837 IFQ_DRV_PREPEND(&ifp->if_snd, m); 838 return; 839 } 840 m = mdefrag; 841 e = bus_dmamap_load_mbuf_sg(sc->mtag, 842 sc->tx_map[sc->txcur], m, segs, &nseg, 0); 843 } 844 if (e != 0) { 845 m_freem(m); 846 continue; 847 } 848 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 849 BUS_DMASYNC_PREWRITE); 850 851 /* 852 * tell the hardware to xmit the packet. 853 */ 854 WR4(sc, ETH_TAR, segs[0].ds_addr); 855 WR4(sc, ETH_TCR, segs[0].ds_len); 856 857 /* 858 * Tap off here if there is a bpf listener. 859 */ 860 BPF_MTAP(ifp, m); 861 862 sc->sent_mbuf[sc->txcur] = m; 863 sc->txcur++; 864 } 865} 866 867static void 868ateinit(void *xsc) 869{ 870 struct ate_softc *sc = xsc; 871 ATE_LOCK(sc); 872 ateinit_locked(sc); 873 ATE_UNLOCK(sc); 874} 875 876static void 877atestart(struct ifnet *ifp) 878{ 879 struct ate_softc *sc = ifp->if_softc; 880 ATE_LOCK(sc); 881 atestart_locked(ifp); 882 ATE_UNLOCK(sc); 883} 884 885/* 886 * Turn off interrupts, and stop the nic. Can be called with sc->ifp NULL 887 * so be careful. 888 */ 889static void 890atestop(struct ate_softc *sc) 891{ 892 struct ifnet *ifp = sc->ifp; 893 894 if (ifp) { 895 ifp->if_timer = 0; 896 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 897 } 898 899 callout_stop(&sc->tick_ch); 900 901 /* 902 * Enable some parts of the MAC that are needed always (like the 903 * MII bus. This turns off the RE and TE bits, which will remain 904 * off until ateinit() is called to turn them on. With RE and TE 905 * turned off, there's no DMA to worry about after this write. 906 */ 907 WR4(sc, ETH_CTL, ETH_CTL_MPE); 908 909 /* 910 * Turn off all the configured options and revert to defaults. 911 */ 912 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 913 914 /* 915 * Turn off all the interrupts, and ack any pending ones by reading 916 * the ISR. 917 */ 918 WR4(sc, ETH_IDR, 0xffffffff); 919 RD4(sc, ETH_ISR); 920 921 /* 922 * Clear out the Transmit and Receiver Status registers of any 923 * errors they may be reporting 924 */ 925 WR4(sc, ETH_TSR, 0xffffffff); 926 WR4(sc, ETH_RSR, 0xffffffff); 927 928 /* 929 * XXX TODO(8) 930 * need to worry about the busdma resources? Yes, I think we need 931 * to sync and unload them. We may also need to release the mbufs 932 * that are assocaited with RX and TX operations. 933 */ 934 935 /* 936 * XXX we should power down the EMAC if it isn't in use, after 937 * putting it into loopback mode. This saves about 400uA according 938 * to the datasheet. 939 */ 940} 941 942static int 943ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 944{ 945 struct ate_softc *sc = ifp->if_softc; 946 struct mii_data *mii; 947 struct ifreq *ifr = (struct ifreq *)data; 948 int mask, error = 0; 949 950 switch (cmd) { 951 case SIOCSIFFLAGS: 952 ATE_LOCK(sc); 953 if ((ifp->if_flags & IFF_UP) == 0 && 954 ifp->if_drv_flags & IFF_DRV_RUNNING) { 955 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 956 atestop(sc); 957 } else { 958 /* reinitialize card on any parameter change */ 959 ateinit_locked(sc); 960 } 961 ATE_UNLOCK(sc); 962 break; 963 964 case SIOCADDMULTI: 965 case SIOCDELMULTI: 966 /* update multicast filter list. */ 967 ATE_LOCK(sc); 968 ate_setmcast(sc); 969 ATE_UNLOCK(sc); 970 error = 0; 971 break; 972 973 case SIOCSIFMEDIA: 974 case SIOCGIFMEDIA: 975 mii = device_get_softc(sc->miibus); 976 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 977 break; 978 case SIOCSIFCAP: 979 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 980 if (mask & IFCAP_VLAN_MTU) { 981 ATE_LOCK(sc); 982 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 983 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 984 ifp->if_capenable |= IFCAP_VLAN_MTU; 985 } else { 986 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 987 ifp->if_capenable &= ~IFCAP_VLAN_MTU; 988 } 989 ATE_UNLOCK(sc); 990 } 991 default: 992 error = ether_ioctl(ifp, cmd, data); 993 break; 994 } 995 return (error); 996} 997 998static void 999ate_child_detached(device_t dev, device_t child) 1000{ 1001 struct ate_softc *sc; 1002 1003 sc = device_get_softc(dev); 1004 if (child == sc->miibus) 1005 sc->miibus = NULL; 1006} 1007 1008/* 1009 * MII bus support routines. 1010 */ 1011static int 1012ate_miibus_readreg(device_t dev, int phy, int reg) 1013{ 1014 struct ate_softc *sc; 1015 int val; 1016 1017 /* 1018 * XXX if we implement agressive power savings, then we need 1019 * XXX to make sure that the clock to the emac is on here 1020 */ 1021 1022 sc = device_get_softc(dev); 1023 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1024 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1025 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1026 continue; 1027 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1028 1029 return (val); 1030} 1031 1032static void 1033ate_miibus_writereg(device_t dev, int phy, int reg, int data) 1034{ 1035 struct ate_softc *sc; 1036 1037 /* 1038 * XXX if we implement agressive power savings, then we need 1039 * XXX to make sure that the clock to the emac is on here 1040 */ 1041 1042 sc = device_get_softc(dev); 1043 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1044 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1045 continue; 1046 return; 1047} 1048 1049static device_method_t ate_methods[] = { 1050 /* Device interface */ 1051 DEVMETHOD(device_probe, ate_probe), 1052 DEVMETHOD(device_attach, ate_attach), 1053 DEVMETHOD(device_detach, ate_detach), 1054 1055 /* Bus interface */ 1056 DEVMETHOD(bus_child_detached, ate_child_detached), 1057 1058 /* MII interface */ 1059 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1060 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1061 1062 { 0, 0 } 1063}; 1064 1065static driver_t ate_driver = { 1066 "ate", 1067 ate_methods, 1068 sizeof(struct ate_softc), 1069}; 1070 1071DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1072DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1073MODULE_DEPEND(ate, miibus, 1, 1, 1); 1074MODULE_DEPEND(ate, ether, 1, 1, 1); 1075