if_ate.c revision 182524
1155324Simp/*- 2155324Simp * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3155324Simp * 4155324Simp * Redistribution and use in source and binary forms, with or without 5155324Simp * modification, are permitted provided that the following conditions 6155324Simp * are met: 7155324Simp * 1. Redistributions of source code must retain the above copyright 8155324Simp * notice, this list of conditions and the following disclaimer. 9155324Simp * 2. Redistributions in binary form must reproduce the above copyright 10155324Simp * notice, this list of conditions and the following disclaimer in the 11155324Simp * documentation and/or other materials provided with the distribution. 12155324Simp * 13155324Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14155324Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15155324Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16155324Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17155324Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18155324Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19155324Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20155324Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21155324Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22155324Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23155324Simp */ 24155324Simp 25155324Simp/* TODO: (in no order) 26155324Simp * 27155324Simp * 8) Need to sync busdma goo in atestop 28155324Simp * 9) atestop should maybe free the mbufs? 29155324Simp * 30155324Simp * 1) detach 31155324Simp * 2) Free dma setup 32163522Simp * 3) Turn on the clock in pmc? Turn off? 33155324Simp */ 34155324Simp 35155324Simp#include <sys/cdefs.h> 36155324Simp__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 182524 2008-08-31 09:28:49Z stas $"); 37155324Simp 38155324Simp#include <sys/param.h> 39155324Simp#include <sys/systm.h> 40155324Simp#include <sys/bus.h> 41155324Simp#include <sys/kernel.h> 42155324Simp#include <sys/mbuf.h> 43155324Simp#include <sys/malloc.h> 44155324Simp#include <sys/module.h> 45155324Simp#include <sys/rman.h> 46155324Simp#include <sys/socket.h> 47155324Simp#include <sys/sockio.h> 48163522Simp#include <sys/sysctl.h> 49155324Simp#include <machine/bus.h> 50155324Simp 51155324Simp#include <net/ethernet.h> 52155324Simp#include <net/if.h> 53155324Simp#include <net/if_arp.h> 54155324Simp#include <net/if_dl.h> 55155324Simp#include <net/if_media.h> 56155324Simp#include <net/if_mib.h> 57155324Simp#include <net/if_types.h> 58155324Simp 59155324Simp#ifdef INET 60155324Simp#include <netinet/in.h> 61155324Simp#include <netinet/in_systm.h> 62155324Simp#include <netinet/in_var.h> 63155324Simp#include <netinet/ip.h> 64155324Simp#endif 65155324Simp 66155324Simp#include <net/bpf.h> 67155324Simp#include <net/bpfdesc.h> 68155324Simp 69155324Simp#include <dev/mii/mii.h> 70155324Simp#include <dev/mii/miivar.h> 71155324Simp#include <arm/at91/if_atereg.h> 72155324Simp 73155324Simp#include "miibus_if.h" 74155324Simp 75165778Sticso#define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 76156831Simp#define ATE_MAX_RX_BUFFERS 64 77155324Simp 78155324Simpstruct ate_softc 79155324Simp{ 80155324Simp struct ifnet *ifp; /* ifnet pointer */ 81155324Simp struct mtx sc_mtx; /* basically a perimeter lock */ 82155324Simp device_t dev; /* Myself */ 83155324Simp device_t miibus; /* My child miibus */ 84155324Simp void *intrhand; /* Interrupt handle */ 85155324Simp struct resource *irq_res; /* IRQ resource */ 86155324Simp struct resource *mem_res; /* Memory resource */ 87155324Simp struct callout tick_ch; /* Tick callout */ 88155324Simp bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 89155324Simp bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 90157562Simp struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 91155324Simp bus_dma_tag_t rxtag; 92155324Simp bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 93157562Simp void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 94157562Simp int rx_buf_ptr; 95155324Simp bus_dma_tag_t rx_desc_tag; 96155324Simp bus_dmamap_t rx_desc_map; 97155324Simp int txcur; /* current tx map pointer */ 98155324Simp bus_addr_t rx_desc_phys; 99155324Simp eth_rx_desc_t *rx_descs; 100159708Simp int use_rmii; 101155324Simp struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 102155324Simp}; 103155324Simp 104155324Simpstatic inline uint32_t 105155324SimpRD4(struct ate_softc *sc, bus_size_t off) 106155324Simp{ 107155324Simp return bus_read_4(sc->mem_res, off); 108155324Simp} 109155324Simp 110155324Simpstatic inline void 111155324SimpWR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 112155324Simp{ 113155324Simp bus_write_4(sc->mem_res, off, val); 114155324Simp} 115155324Simp 116155324Simp#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 117155324Simp#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 118155324Simp#define ATE_LOCK_INIT(_sc) \ 119155324Simp mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 120155324Simp MTX_NETWORK_LOCK, MTX_DEF) 121155324Simp#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 122155324Simp#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 123155324Simp#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 124155324Simp 125155324Simpstatic devclass_t ate_devclass; 126155324Simp 127155324Simp/* ifnet entry points */ 128155324Simp 129155324Simpstatic void ateinit_locked(void *); 130155324Simpstatic void atestart_locked(struct ifnet *); 131155324Simp 132155324Simpstatic void ateinit(void *); 133155324Simpstatic void atestart(struct ifnet *); 134155324Simpstatic void atestop(struct ate_softc *); 135155324Simpstatic int ateioctl(struct ifnet * ifp, u_long, caddr_t); 136155324Simp 137155324Simp/* bus entry points */ 138155324Simp 139155324Simpstatic int ate_probe(device_t dev); 140155324Simpstatic int ate_attach(device_t dev); 141155324Simpstatic int ate_detach(device_t dev); 142155324Simpstatic void ate_intr(void *); 143155324Simp 144155324Simp/* helper routines */ 145155324Simpstatic int ate_activate(device_t dev); 146155324Simpstatic void ate_deactivate(device_t dev); 147155324Simpstatic int ate_ifmedia_upd(struct ifnet *ifp); 148155324Simpstatic void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 149166573Simpstatic int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 150155445Scognetstatic void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 151155324Simp 152155324Simp/* 153155324Simp * The AT91 family of products has the ethernet called EMAC. However, 154155324Simp * it isn't self identifying. It is anticipated that the parent bus 155155324Simp * code will take care to only add ate devices where they really are. As 156155324Simp * such, we do nothing here to identify the device and just set its name. 157155324Simp */ 158155324Simpstatic int 159155324Simpate_probe(device_t dev) 160155324Simp{ 161155324Simp device_set_desc(dev, "EMAC"); 162155324Simp return (0); 163155324Simp} 164155324Simp 165155324Simpstatic int 166155324Simpate_attach(device_t dev) 167155324Simp{ 168155324Simp struct ate_softc *sc = device_get_softc(dev); 169155324Simp struct ifnet *ifp = NULL; 170163522Simp struct sysctl_ctx_list *sctx; 171163522Simp struct sysctl_oid *soid; 172155324Simp int err; 173182477Sstas u_char eaddr[ETHER_ADDR_LEN]; 174182477Sstas uint32_t rnd; 175155324Simp 176155324Simp sc->dev = dev; 177155324Simp err = ate_activate(dev); 178155324Simp if (err) 179155324Simp goto out; 180155324Simp 181159708Simp sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 182159708Simp 183182476Sstas /* Sysctls */ 184163522Simp sctx = device_get_sysctl_ctx(dev); 185163522Simp soid = device_get_sysctl_tree(dev); 186163522Simp SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 187163522Simp CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 188163522Simp 189155324Simp /* calling atestop before ifp is set is OK */ 190155324Simp atestop(sc); 191155324Simp ATE_LOCK_INIT(sc); 192155324Simp callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 193155324Simp 194166573Simp if ((err = ate_get_mac(sc, eaddr)) != 0) { 195182477Sstas /* 196182524Sstas * No MAC address configured. Generate the random one. 197182477Sstas */ 198182477Sstas if (bootverbose) 199182477Sstas device_printf(dev, 200182524Sstas "Generating random ethernet address.\n"); 201182477Sstas rnd = arc4random(); 202182477Sstas 203182477Sstas /* 204182477Sstas * Set OUI to Atmel. 205182477Sstas */ 206182524Sstas eaddr[0] = 0x02; 207182477Sstas eaddr[1] = 0x04; 208182477Sstas eaddr[2] = 0x25; 209182477Sstas eaddr[3] = (rnd >> 16) & 0xff; 210182477Sstas eaddr[4] = (rnd >> 8) & 0xff; 211182477Sstas eaddr[5] = rnd & 0xff; 212166573Simp } 213155445Scognet ate_set_mac(sc, eaddr); 214155324Simp 215155405Scognet sc->ifp = ifp = if_alloc(IFT_ETHER); 216155324Simp if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 217155324Simp device_printf(dev, "Cannot find my PHY.\n"); 218155324Simp err = ENXIO; 219155324Simp goto out; 220155324Simp } 221155324Simp 222155324Simp ifp->if_softc = sc; 223155324Simp if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 224155324Simp ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 225165779Sticso ifp->if_capabilities |= IFCAP_VLAN_MTU; 226165779Sticso ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 227155324Simp ifp->if_start = atestart; 228155324Simp ifp->if_ioctl = ateioctl; 229155324Simp ifp->if_init = ateinit; 230155324Simp ifp->if_baudrate = 10000000; 231155324Simp IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 232166625Smlaier ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 233155324Simp IFQ_SET_READY(&ifp->if_snd); 234155324Simp ifp->if_timer = 0; 235155324Simp ifp->if_linkmib = &sc->mibdata; 236155324Simp ifp->if_linkmiblen = sizeof(sc->mibdata); 237155324Simp sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 238155324Simp 239155324Simp ether_ifattach(ifp, eaddr); 240155324Simp 241155324Simp /* 242155324Simp * Activate the interrupt 243155324Simp */ 244155324Simp err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 245166901Spiso NULL, ate_intr, sc, &sc->intrhand); 246155324Simp if (err) { 247155324Simp ether_ifdetach(ifp); 248155324Simp ATE_LOCK_DESTROY(sc); 249155324Simp } 250155324Simpout:; 251155324Simp if (err) 252155324Simp ate_deactivate(dev); 253155324Simp if (err && ifp) 254155324Simp if_free(ifp); 255155324Simp return (err); 256155324Simp} 257155324Simp 258155324Simpstatic int 259155324Simpate_detach(device_t dev) 260155324Simp{ 261155324Simp return EBUSY; /* XXX TODO(1) */ 262155324Simp} 263155324Simp 264155324Simpstatic void 265155324Simpate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 266155324Simp{ 267155324Simp struct ate_softc *sc; 268155324Simp 269155324Simp if (error != 0) 270155324Simp return; 271155324Simp sc = (struct ate_softc *)arg; 272155324Simp sc->rx_desc_phys = segs[0].ds_addr; 273155324Simp} 274155324Simp 275157562Simpstatic void 276157562Simpate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 277157562Simp{ 278157562Simp struct ate_softc *sc; 279157562Simp int i; 280157562Simp 281157562Simp if (error != 0) 282157562Simp return; 283157562Simp sc = (struct ate_softc *)arg; 284157562Simp i = sc->rx_buf_ptr; 285157562Simp 286157562Simp /* 287157562Simp * For the last buffer, set the wrap bit so the controller 288157562Simp * restarts from the first descriptor. 289157562Simp */ 290163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 291157562Simp if (i == ATE_MAX_RX_BUFFERS - 1) 292157562Simp sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 293157562Simp else 294157562Simp sc->rx_descs[i].addr = segs[0].ds_addr; 295163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 296157562Simp sc->rx_descs[i].status = 0; 297157562Simp /* Flush the memory in the mbuf */ 298157562Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 299157562Simp} 300157562Simp 301155324Simp/* 302155324Simp * Compute the multicast filter for this device using the standard 303155324Simp * algorithm. I wonder why this isn't in ether somewhere as a lot 304155324Simp * of different MAC chips use this method (or the reverse the bits) 305155324Simp * method. 306155324Simp */ 307155324Simpstatic void 308155324Simpate_setmcast(struct ate_softc *sc) 309155324Simp{ 310155324Simp uint32_t index; 311155324Simp uint32_t mcaf[2]; 312155324Simp u_char *af = (u_char *) mcaf; 313155324Simp struct ifmultiaddr *ifma; 314155324Simp 315155324Simp mcaf[0] = 0; 316155324Simp mcaf[1] = 0; 317155324Simp 318155324Simp IF_ADDR_LOCK(sc->ifp); 319155324Simp TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 320155324Simp if (ifma->ifma_addr->sa_family != AF_LINK) 321155324Simp continue; 322155324Simp index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 323155324Simp ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 324155324Simp af[index >> 3] |= 1 << (index & 7); 325155324Simp } 326155324Simp IF_ADDR_UNLOCK(sc->ifp); 327155324Simp 328155324Simp /* 329155324Simp * Write the hash to the hash register. This card can also 330155324Simp * accept unicast packets as well as multicast packets using this 331155324Simp * register for easier bridging operations, but we don't take 332155324Simp * advantage of that. Locks here are to avoid LOR with the 333155324Simp * IF_ADDR_LOCK, but might not be strictly necessary. 334155324Simp */ 335155324Simp WR4(sc, ETH_HSL, mcaf[0]); 336155324Simp WR4(sc, ETH_HSH, mcaf[1]); 337155324Simp} 338155324Simp 339155324Simpstatic int 340155324Simpate_activate(device_t dev) 341155324Simp{ 342155324Simp struct ate_softc *sc; 343155324Simp int rid, err, i; 344155324Simp 345155324Simp sc = device_get_softc(dev); 346155324Simp rid = 0; 347155324Simp sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 348155324Simp RF_ACTIVE); 349155324Simp if (sc->mem_res == NULL) 350155324Simp goto errout; 351155324Simp rid = 0; 352155324Simp sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 353155324Simp RF_ACTIVE); 354163522Simp if (sc->irq_res == NULL) 355155324Simp goto errout; 356155324Simp 357155324Simp /* 358155324Simp * Allocate DMA tags and maps 359155324Simp */ 360155324Simp err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 361155324Simp BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 362155324Simp busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 363155324Simp if (err != 0) 364155324Simp goto errout; 365155324Simp for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 366155324Simp err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 367155324Simp if (err != 0) 368155324Simp goto errout; 369155324Simp } 370155324Simp /* 371155324Simp * Allocate our Rx buffers. This chip has a rx structure that's filled 372155324Simp * in 373155324Simp */ 374155324Simp 375155324Simp /* 376155324Simp * Allocate DMA tags and maps for RX. 377155324Simp */ 378155324Simp err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 379155324Simp BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 380155324Simp busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 381155324Simp if (err != 0) 382155324Simp goto errout; 383155324Simp 384155324Simp /* Dma TAG and MAP for the rx descriptors. */ 385155324Simp err = bus_dma_tag_create(NULL, sizeof(eth_rx_desc_t), 0, 386155324Simp BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 387155324Simp ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 388155324Simp ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 389155324Simp &sc->sc_mtx, &sc->rx_desc_tag); 390155324Simp if (err != 0) 391155324Simp goto errout; 392156831Simp if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 393156831Simp BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 394155324Simp goto errout; 395157562Simp if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 396155324Simp sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 397155324Simp ate_getaddr, sc, 0) != 0) 398155324Simp goto errout; 399155324Simp /* XXX TODO(5) Put this in ateinit_locked? */ 400155324Simp for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 401157562Simp sc->rx_buf_ptr = i; 402157562Simp if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 403157562Simp BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 404155324Simp goto errout; 405157562Simp if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 406157562Simp MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 407157562Simp goto errout; 408155324Simp } 409157562Simp sc->rx_buf_ptr = 0; 410156831Simp /* Flush the memory for the EMAC rx descriptor */ 411155324Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 412155324Simp /* Write the descriptor queue address. */ 413155324Simp WR4(sc, ETH_RBQP, sc->rx_desc_phys); 414155324Simp return (0); 415155324Simperrout: 416155324Simp ate_deactivate(dev); 417155324Simp return (ENOMEM); 418155324Simp} 419155324Simp 420155324Simpstatic void 421155324Simpate_deactivate(device_t dev) 422155324Simp{ 423155324Simp struct ate_softc *sc; 424155324Simp 425155324Simp sc = device_get_softc(dev); 426155324Simp /* XXX TODO(2) teardown busdma junk, below from fxp -- customize */ 427155324Simp#if 0 428155324Simp if (sc->fxp_mtag) { 429155324Simp for (i = 0; i < FXP_NRFABUFS; i++) { 430155324Simp rxp = &sc->fxp_desc.rx_list[i]; 431155324Simp if (rxp->rx_mbuf != NULL) { 432155324Simp bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 433155324Simp BUS_DMASYNC_POSTREAD); 434155324Simp bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 435155324Simp m_freem(rxp->rx_mbuf); 436155324Simp } 437155324Simp bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 438155324Simp } 439155324Simp bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 440155324Simp for (i = 0; i < FXP_NTXCB; i++) { 441155324Simp txp = &sc->fxp_desc.tx_list[i]; 442155324Simp if (txp->tx_mbuf != NULL) { 443155324Simp bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 444155324Simp BUS_DMASYNC_POSTWRITE); 445155324Simp bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 446155324Simp m_freem(txp->tx_mbuf); 447155324Simp } 448155324Simp bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 449155324Simp } 450155324Simp bus_dma_tag_destroy(sc->fxp_mtag); 451155324Simp } 452155324Simp if (sc->fxp_stag) 453155324Simp bus_dma_tag_destroy(sc->fxp_stag); 454155324Simp if (sc->cbl_tag) 455155324Simp bus_dma_tag_destroy(sc->cbl_tag); 456155324Simp if (sc->mcs_tag) 457155324Simp bus_dma_tag_destroy(sc->mcs_tag); 458155324Simp#endif 459155324Simp if (sc->intrhand) 460155324Simp bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 461155324Simp sc->intrhand = 0; 462155324Simp bus_generic_detach(sc->dev); 463155324Simp if (sc->miibus) 464155324Simp device_delete_child(sc->dev, sc->miibus); 465155324Simp if (sc->mem_res) 466155324Simp bus_release_resource(dev, SYS_RES_IOPORT, 467155324Simp rman_get_rid(sc->mem_res), sc->mem_res); 468155324Simp sc->mem_res = 0; 469155324Simp if (sc->irq_res) 470155324Simp bus_release_resource(dev, SYS_RES_IRQ, 471155324Simp rman_get_rid(sc->irq_res), sc->irq_res); 472155324Simp sc->irq_res = 0; 473155324Simp return; 474155324Simp} 475155324Simp 476155324Simp/* 477155324Simp * Change media according to request. 478155324Simp */ 479155324Simpstatic int 480155324Simpate_ifmedia_upd(struct ifnet *ifp) 481155324Simp{ 482155324Simp struct ate_softc *sc = ifp->if_softc; 483155324Simp struct mii_data *mii; 484155324Simp 485155324Simp mii = device_get_softc(sc->miibus); 486155324Simp ATE_LOCK(sc); 487155324Simp mii_mediachg(mii); 488155324Simp ATE_UNLOCK(sc); 489155324Simp return (0); 490155324Simp} 491155324Simp 492155324Simp/* 493155324Simp * Notify the world which media we're using. 494155324Simp */ 495155324Simpstatic void 496155324Simpate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 497155324Simp{ 498155324Simp struct ate_softc *sc = ifp->if_softc; 499155324Simp struct mii_data *mii; 500155324Simp 501155324Simp mii = device_get_softc(sc->miibus); 502155324Simp ATE_LOCK(sc); 503155324Simp mii_pollstat(mii); 504155324Simp ifmr->ifm_active = mii->mii_media_active; 505155324Simp ifmr->ifm_status = mii->mii_media_status; 506155324Simp ATE_UNLOCK(sc); 507155324Simp} 508155324Simp 509155324Simpstatic void 510163937Simpate_stat_update(struct ate_softc *sc, int active) 511163937Simp{ 512163937Simp /* 513163937Simp * The speed and full/half-duplex state needs to be reflected 514163937Simp * in the ETH_CFG register. 515163937Simp */ 516163937Simp if (IFM_SUBTYPE(active) == IFM_10_T) 517163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_SPD); 518163937Simp else 519163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_SPD); 520163937Simp if (active & IFM_FDX) 521163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_FD); 522163937Simp else 523163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_FD); 524163937Simp} 525163937Simp 526163937Simpstatic void 527155324Simpate_tick(void *xsc) 528155324Simp{ 529155324Simp struct ate_softc *sc = xsc; 530163937Simp struct ifnet *ifp = sc->ifp; 531155324Simp struct mii_data *mii; 532155324Simp int active; 533163937Simp uint32_t c; 534155324Simp 535155324Simp /* 536155324Simp * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 537155324Simp * the MII if there's a link if this bit is clear. Not sure if we 538155324Simp * should do the same thing here or not. 539155324Simp */ 540155324Simp ATE_ASSERT_LOCKED(sc); 541155324Simp if (sc->miibus != NULL) { 542155324Simp mii = device_get_softc(sc->miibus); 543155324Simp active = mii->mii_media_active; 544155324Simp mii_tick(mii); 545155324Simp if (mii->mii_media_status & IFM_ACTIVE && 546163937Simp active != mii->mii_media_active) 547163937Simp ate_stat_update(sc, mii->mii_media_active); 548155324Simp } 549155324Simp 550155324Simp /* 551155324Simp * Update the stats as best we can. When we're done, clear 552155324Simp * the status counters and start over. We're supposed to read these 553155324Simp * registers often enough that they won't overflow. Hopefully 554155324Simp * once a second is often enough. Some don't map well to 555155324Simp * the dot3Stats mib, so for those we just count them as general 556155324Simp * errors. Stats for iframes, ibutes, oframes and obytes are 557155324Simp * collected elsewhere. These registers zero on a read to prevent 558163937Simp * races. For all the collision stats, also update the collision 559163937Simp * stats for the interface. 560155324Simp */ 561155324Simp sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 562155324Simp sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 563163937Simp c = RD4(sc, ETH_SCOL); 564163937Simp ifp->if_collisions += c; 565163937Simp sc->mibdata.dot3StatsSingleCollisionFrames += c; 566163937Simp c = RD4(sc, ETH_MCOL); 567163937Simp sc->mibdata.dot3StatsMultipleCollisionFrames += c; 568163937Simp ifp->if_collisions += c; 569155324Simp sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 570155324Simp sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 571163937Simp c = RD4(sc, ETH_LCOL); 572163937Simp sc->mibdata.dot3StatsLateCollisions += c; 573163937Simp ifp->if_collisions += c; 574163937Simp c = RD4(sc, ETH_ECOL); 575163937Simp sc->mibdata.dot3StatsExcessiveCollisions += c; 576163937Simp ifp->if_collisions += c; 577155324Simp sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 578155324Simp sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 579155324Simp sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 580155324Simp /* 581155324Simp * not sure where to lump these, so count them against the errors 582155324Simp * for the interface. 583155324Simp */ 584163937Simp sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 585155324Simp sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 586155324Simp RD4(sc, ETH_USF); 587155324Simp 588155324Simp /* 589155324Simp * Schedule another timeout one second from now. 590155324Simp */ 591155324Simp callout_reset(&sc->tick_ch, hz, ate_tick, sc); 592155324Simp} 593155324Simp 594155324Simpstatic void 595155445Scognetate_set_mac(struct ate_softc *sc, u_char *eaddr) 596155445Scognet{ 597155445Scognet WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 598155445Scognet (eaddr[1] << 8) | eaddr[0]); 599155445Scognet WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 600155445Scognet} 601155445Scognet 602166573Simpstatic int 603155324Simpate_get_mac(struct ate_softc *sc, u_char *eaddr) 604155324Simp{ 605182477Sstas bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 606182477Sstas bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 607166573Simp uint32_t low, high; 608182477Sstas int i; 609155324Simp 610166573Simp /* 611166573Simp * The boot loader setup the MAC with an address, if one is set in 612182477Sstas * the loader. Grab one MAC address from the SA[1-4][HL] registers. 613166573Simp */ 614182477Sstas for (i = 0; i < 4; i++) { 615182477Sstas low = RD4(sc, sa_low_reg[i]); 616182477Sstas high = RD4(sc, sa_high_reg[i]); 617182477Sstas if ((low | (high & 0xffff)) != 0) { 618182477Sstas eaddr[0] = low & 0xff; 619182477Sstas eaddr[1] = (low >> 8) & 0xff; 620182477Sstas eaddr[2] = (low >> 16) & 0xff; 621182477Sstas eaddr[3] = (low >> 24) & 0xff; 622182477Sstas eaddr[4] = high & 0xff; 623182477Sstas eaddr[5] = (high >> 8) & 0xff; 624182477Sstas return (0); 625182477Sstas } 626182477Sstas } 627182477Sstas return (ENXIO); 628155324Simp} 629155324Simp 630155324Simpstatic void 631155324Simpate_intr(void *xsc) 632155324Simp{ 633155324Simp struct ate_softc *sc = xsc; 634163937Simp struct ifnet *ifp = sc->ifp; 635155324Simp int status; 636155324Simp int i; 637157562Simp void *bp; 638157562Simp struct mbuf *mb; 639157562Simp uint32_t rx_stat; 640156831Simp 641155324Simp status = RD4(sc, ETH_ISR); 642155324Simp if (status == 0) 643155324Simp return; 644155324Simp if (status & ETH_ISR_RCOM) { 645155324Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 646155324Simp BUS_DMASYNC_POSTREAD); 647157562Simp while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 648157562Simp i = sc->rx_buf_ptr; 649157562Simp sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 650157562Simp bp = sc->rx_buf[i]; 651156831Simp rx_stat = sc->rx_descs[i].status; 652156831Simp if ((rx_stat & ETH_LEN_MASK) == 0) { 653156831Simp printf("ignoring bogus 0 len packet\n"); 654163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 655163937Simp BUS_DMASYNC_PREWRITE); 656157562Simp sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 657156831Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 658163937Simp BUS_DMASYNC_POSTWRITE); 659156831Simp continue; 660155324Simp } 661156831Simp /* Flush memory for mbuf so we don't get stale bytes */ 662156831Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 663156831Simp BUS_DMASYNC_POSTREAD); 664163937Simp WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 665163937Simp 666156831Simp /* 667156831Simp * The length returned by the device includes the 668156831Simp * ethernet CRC calculation for the packet, but 669156831Simp * ifnet drivers are supposed to discard it. 670156831Simp */ 671157562Simp mb = m_devget(sc->rx_buf[i], 672157562Simp (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 673163937Simp ETHER_ALIGN, ifp, NULL); 674163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 675163937Simp BUS_DMASYNC_PREWRITE); 676157562Simp sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 677157562Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 678163937Simp BUS_DMASYNC_POSTWRITE); 679156831Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 680156831Simp BUS_DMASYNC_PREREAD); 681163937Simp if (mb != NULL) { 682163937Simp ifp->if_ipackets++; 683163937Simp (*ifp->if_input)(ifp, mb); 684163937Simp } 685163937Simp 686155324Simp } 687155324Simp } 688155324Simp if (status & ETH_ISR_TCOM) { 689156831Simp ATE_LOCK(sc); 690163937Simp /* XXX TSR register should be cleared */ 691156831Simp if (sc->sent_mbuf[0]) { 692179693Swkoszek bus_dmamap_sync(sc->mtag, sc->tx_map[0], 693163937Simp BUS_DMASYNC_POSTWRITE); 694155324Simp m_freem(sc->sent_mbuf[0]); 695163937Simp ifp->if_opackets++; 696156831Simp sc->sent_mbuf[0] = NULL; 697156831Simp } 698155324Simp if (sc->sent_mbuf[1]) { 699155324Simp if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 700179693Swkoszek bus_dmamap_sync(sc->mtag, sc->tx_map[1], 701163937Simp BUS_DMASYNC_POSTWRITE); 702155324Simp m_freem(sc->sent_mbuf[1]); 703163937Simp ifp->if_opackets++; 704155324Simp sc->txcur = 0; 705155324Simp sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 706155324Simp } else { 707155324Simp sc->sent_mbuf[0] = sc->sent_mbuf[1]; 708155324Simp sc->sent_mbuf[1] = NULL; 709155324Simp sc->txcur = 1; 710155324Simp } 711155324Simp } else { 712155324Simp sc->sent_mbuf[0] = NULL; 713155324Simp sc->txcur = 0; 714155324Simp } 715156831Simp /* 716156831Simp * We're no longer busy, so clear the busy flag and call the 717156831Simp * start routine to xmit more packets. 718156831Simp */ 719156831Simp sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 720156831Simp atestart_locked(sc->ifp); 721156831Simp ATE_UNLOCK(sc); 722155324Simp } 723155324Simp if (status & ETH_ISR_RBNA) { 724156831Simp printf("RBNA workaround\n"); 725155324Simp /* Workaround Errata #11 */ 726155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) &~ ETH_CTL_RE); 727155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_RE); 728155324Simp } 729155324Simp} 730155324Simp 731155324Simp/* 732155324Simp * Reset and initialize the chip 733155324Simp */ 734155324Simpstatic void 735155324Simpateinit_locked(void *xsc) 736155324Simp{ 737155324Simp struct ate_softc *sc = xsc; 738155324Simp struct ifnet *ifp = sc->ifp; 739163937Simp struct mii_data *mii; 740155324Simp 741155324Simp ATE_ASSERT_LOCKED(sc); 742155324Simp 743155324Simp /* 744155324Simp * XXX TODO(3) 745155324Simp * we need to turn on the EMAC clock in the pmc. With the 746155324Simp * default boot loader, this is already turned on. However, we 747155324Simp * need to think about how best to turn it on/off as the interface 748155324Simp * is brought up/down, as well as dealing with the mii bus... 749155324Simp * 750155324Simp * We also need to multiplex the pins correctly. 751155324Simp */ 752155324Simp 753155324Simp /* 754155324Simp * There are two different ways that the mii bus is connected 755155324Simp * to this chip. Select the right one based on a compile-time 756155324Simp * option. 757155324Simp */ 758159708Simp if (sc->use_rmii) 759159708Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_RMII); 760159708Simp else 761159708Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_RMII); 762159708Simp 763155324Simp /* 764155324Simp * Turn on the multicast hash, and write 0's to it. 765155324Simp */ 766155324Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_MTI); 767155324Simp WR4(sc, ETH_HSH, 0); 768155324Simp WR4(sc, ETH_HSL, 0); 769155324Simp 770155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 771156831Simp WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 772155324Simp 773155324Simp /* 774155324Simp * Boot loader fills in MAC address. If that's not the case, then 775155324Simp * we should set SA1L and SA1H here to the appropriate value. Note: 776155324Simp * the byte order is big endian, not little endian, so we have some 777155324Simp * swapping to do. Again, if we need it (which I don't think we do). 778155324Simp */ 779155324Simp ate_setmcast(sc); 780155324Simp 781165779Sticso /* enable big packets */ 782165779Sticso WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 783165779Sticso 784155324Simp /* 785155324Simp * Set 'running' flag, and clear output active flag 786155324Simp * and attempt to start the output 787155324Simp */ 788155324Simp ifp->if_drv_flags |= IFF_DRV_RUNNING; 789155324Simp ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 790163937Simp 791163937Simp mii = device_get_softc(sc->miibus); 792163937Simp mii_pollstat(mii); 793163937Simp ate_stat_update(sc, mii->mii_media_active); 794155324Simp atestart_locked(ifp); 795155324Simp 796155324Simp callout_reset(&sc->tick_ch, hz, ate_tick, sc); 797155324Simp} 798155324Simp 799155324Simp/* 800155324Simp * dequeu packets and transmit 801155324Simp */ 802155324Simpstatic void 803155324Simpatestart_locked(struct ifnet *ifp) 804155324Simp{ 805155324Simp struct ate_softc *sc = ifp->if_softc; 806155324Simp struct mbuf *m, *mdefrag; 807155324Simp bus_dma_segment_t segs[1]; 808163937Simp int nseg, e; 809155324Simp 810155324Simp ATE_ASSERT_LOCKED(sc); 811155324Simp if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 812155324Simp return; 813155324Simp 814156831Simp while (sc->txcur < ATE_MAX_TX_BUFFERS) { 815156831Simp /* 816156831Simp * check to see if there's room to put another packet into the 817156831Simp * xmit queue. The EMAC chip has a ping-pong buffer for xmit 818156831Simp * packets. We use OACTIVE to indicate "we can stuff more into 819156831Simp * our buffers (clear) or not (set)." 820156831Simp */ 821156831Simp if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 822156831Simp ifp->if_drv_flags |= IFF_DRV_OACTIVE; 823156831Simp return; 824156831Simp } 825156831Simp IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 826156831Simp if (m == 0) { 827156831Simp ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 828156831Simp return; 829156831Simp } 830163937Simp e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 831163937Simp segs, &nseg, 0); 832163937Simp if (e == EFBIG) { 833163937Simp mdefrag = m_defrag(m, M_DONTWAIT); 834163937Simp if (mdefrag == NULL) { 835163937Simp IFQ_DRV_PREPEND(&ifp->if_snd, m); 836163937Simp return; 837163937Simp } 838163937Simp m = mdefrag; 839163937Simp e = bus_dmamap_load_mbuf_sg(sc->mtag, 840163937Simp sc->tx_map[sc->txcur], m, segs, &nseg, 0); 841156831Simp } 842163937Simp if (e != 0) { 843156831Simp m_freem(m); 844156831Simp continue; 845156831Simp } 846156831Simp bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 847156831Simp BUS_DMASYNC_PREWRITE); 848155324Simp 849156831Simp /* 850156831Simp * tell the hardware to xmit the packet. 851156831Simp */ 852156831Simp WR4(sc, ETH_TAR, segs[0].ds_addr); 853156831Simp WR4(sc, ETH_TCR, segs[0].ds_len); 854155324Simp 855156831Simp /* 856156831Simp * Tap off here if there is a bpf listener. 857156831Simp */ 858156831Simp BPF_MTAP(ifp, m); 859155324Simp 860156831Simp sc->sent_mbuf[sc->txcur] = m; 861156831Simp sc->txcur++; 862156831Simp } 863155324Simp} 864155324Simp 865155324Simpstatic void 866155324Simpateinit(void *xsc) 867155324Simp{ 868155324Simp struct ate_softc *sc = xsc; 869155324Simp ATE_LOCK(sc); 870155324Simp ateinit_locked(sc); 871155324Simp ATE_UNLOCK(sc); 872155324Simp} 873155324Simp 874155324Simpstatic void 875155324Simpatestart(struct ifnet *ifp) 876155324Simp{ 877155324Simp struct ate_softc *sc = ifp->if_softc; 878155324Simp ATE_LOCK(sc); 879155324Simp atestart_locked(ifp); 880155324Simp ATE_UNLOCK(sc); 881155324Simp} 882155324Simp 883155324Simp/* 884155324Simp * Turn off interrupts, and stop the nic. Can be called with sc->ifp NULL 885155324Simp * so be careful. 886155324Simp */ 887155324Simpstatic void 888155324Simpatestop(struct ate_softc *sc) 889155324Simp{ 890155324Simp struct ifnet *ifp = sc->ifp; 891155324Simp 892155324Simp if (ifp) { 893155324Simp ifp->if_timer = 0; 894155324Simp ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 895155324Simp } 896155324Simp 897155324Simp callout_stop(&sc->tick_ch); 898155324Simp 899155324Simp /* 900155324Simp * Enable some parts of the MAC that are needed always (like the 901155324Simp * MII bus. This turns off the RE and TE bits, which will remain 902155405Scognet * off until ateinit() is called to turn them on. With RE and TE 903155324Simp * turned off, there's no DMA to worry about after this write. 904155324Simp */ 905155324Simp WR4(sc, ETH_CTL, ETH_CTL_MPE); 906155324Simp 907155324Simp /* 908155324Simp * Turn off all the configured options and revert to defaults. 909155324Simp */ 910155324Simp WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 911155324Simp 912155324Simp /* 913155324Simp * Turn off all the interrupts, and ack any pending ones by reading 914155324Simp * the ISR. 915155324Simp */ 916155324Simp WR4(sc, ETH_IDR, 0xffffffff); 917155324Simp RD4(sc, ETH_ISR); 918155324Simp 919155324Simp /* 920155324Simp * Clear out the Transmit and Receiver Status registers of any 921155324Simp * errors they may be reporting 922155324Simp */ 923155324Simp WR4(sc, ETH_TSR, 0xffffffff); 924155324Simp WR4(sc, ETH_RSR, 0xffffffff); 925155324Simp 926155324Simp /* 927155324Simp * XXX TODO(8) 928155324Simp * need to worry about the busdma resources? Yes, I think we need 929155324Simp * to sync and unload them. We may also need to release the mbufs 930155324Simp * that are assocaited with RX and TX operations. 931155324Simp */ 932155324Simp 933155324Simp /* 934155324Simp * XXX we should power down the EMAC if it isn't in use, after 935155324Simp * putting it into loopback mode. This saves about 400uA according 936155324Simp * to the datasheet. 937155324Simp */ 938155324Simp} 939155324Simp 940155324Simpstatic int 941155324Simpateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 942155324Simp{ 943155324Simp struct ate_softc *sc = ifp->if_softc; 944157562Simp struct mii_data *mii; 945157562Simp struct ifreq *ifr = (struct ifreq *)data; 946165779Sticso int mask, error = 0; 947155324Simp 948155324Simp switch (cmd) { 949155324Simp case SIOCSIFFLAGS: 950155324Simp ATE_LOCK(sc); 951155324Simp if ((ifp->if_flags & IFF_UP) == 0 && 952155324Simp ifp->if_drv_flags & IFF_DRV_RUNNING) { 953155324Simp ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 954155324Simp atestop(sc); 955155324Simp } else { 956155324Simp /* reinitialize card on any parameter change */ 957155324Simp ateinit_locked(sc); 958155324Simp } 959155324Simp ATE_UNLOCK(sc); 960155324Simp break; 961155324Simp 962155324Simp case SIOCADDMULTI: 963155324Simp case SIOCDELMULTI: 964155324Simp /* update multicast filter list. */ 965157562Simp ATE_LOCK(sc); 966155324Simp ate_setmcast(sc); 967157562Simp ATE_UNLOCK(sc); 968155324Simp error = 0; 969155324Simp break; 970155324Simp 971157562Simp case SIOCSIFMEDIA: 972157562Simp case SIOCGIFMEDIA: 973157562Simp mii = device_get_softc(sc->miibus); 974157562Simp error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 975157562Simp break; 976165779Sticso case SIOCSIFCAP: 977165779Sticso mask = ifp->if_capenable ^ ifr->ifr_reqcap; 978165779Sticso if (mask & IFCAP_VLAN_MTU) { 979165779Sticso ATE_LOCK(sc); 980165779Sticso if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 981165779Sticso WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 982165779Sticso ifp->if_capenable |= IFCAP_VLAN_MTU; 983165779Sticso } else { 984165779Sticso WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 985165779Sticso ifp->if_capenable &= ~IFCAP_VLAN_MTU; 986165779Sticso } 987165779Sticso ATE_UNLOCK(sc); 988165779Sticso } 989155324Simp default: 990155324Simp error = ether_ioctl(ifp, cmd, data); 991155324Simp break; 992155324Simp } 993155324Simp return (error); 994155324Simp} 995155324Simp 996155324Simpstatic void 997155324Simpate_child_detached(device_t dev, device_t child) 998155324Simp{ 999155324Simp struct ate_softc *sc; 1000155324Simp 1001155324Simp sc = device_get_softc(dev); 1002155324Simp if (child == sc->miibus) 1003155324Simp sc->miibus = NULL; 1004155324Simp} 1005155324Simp 1006155324Simp/* 1007155324Simp * MII bus support routines. 1008155324Simp */ 1009155324Simpstatic int 1010155324Simpate_miibus_readreg(device_t dev, int phy, int reg) 1011155324Simp{ 1012155324Simp struct ate_softc *sc; 1013155324Simp int val; 1014155324Simp 1015155324Simp /* 1016155324Simp * XXX if we implement agressive power savings, then we need 1017155324Simp * XXX to make sure that the clock to the emac is on here 1018155324Simp */ 1019155324Simp 1020155324Simp sc = device_get_softc(dev); 1021155324Simp DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1022155324Simp WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1023155324Simp while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1024155324Simp continue; 1025155324Simp val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1026155324Simp 1027155324Simp return (val); 1028155324Simp} 1029155324Simp 1030155324Simpstatic void 1031155324Simpate_miibus_writereg(device_t dev, int phy, int reg, int data) 1032155324Simp{ 1033155324Simp struct ate_softc *sc; 1034155324Simp 1035155324Simp /* 1036155324Simp * XXX if we implement agressive power savings, then we need 1037155324Simp * XXX to make sure that the clock to the emac is on here 1038155324Simp */ 1039155324Simp 1040155324Simp sc = device_get_softc(dev); 1041155324Simp WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1042155324Simp while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1043155324Simp continue; 1044155324Simp return; 1045155324Simp} 1046155324Simp 1047155324Simpstatic device_method_t ate_methods[] = { 1048155324Simp /* Device interface */ 1049155324Simp DEVMETHOD(device_probe, ate_probe), 1050155324Simp DEVMETHOD(device_attach, ate_attach), 1051155324Simp DEVMETHOD(device_detach, ate_detach), 1052155324Simp 1053155324Simp /* Bus interface */ 1054155324Simp DEVMETHOD(bus_child_detached, ate_child_detached), 1055155324Simp 1056155324Simp /* MII interface */ 1057155324Simp DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1058155324Simp DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1059155324Simp 1060155324Simp { 0, 0 } 1061155324Simp}; 1062155324Simp 1063155324Simpstatic driver_t ate_driver = { 1064155324Simp "ate", 1065155324Simp ate_methods, 1066155324Simp sizeof(struct ate_softc), 1067155324Simp}; 1068155324Simp 1069155324SimpDRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1070155324SimpDRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1071155324SimpMODULE_DEPEND(ate, miibus, 1, 1, 1); 1072155324SimpMODULE_DEPEND(ate, ether, 1, 1, 1); 1073