if_ate.c revision 166901
1155324Simp/*- 2155324Simp * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3155324Simp * 4155324Simp * Redistribution and use in source and binary forms, with or without 5155324Simp * modification, are permitted provided that the following conditions 6155324Simp * are met: 7155324Simp * 1. Redistributions of source code must retain the above copyright 8155324Simp * notice, this list of conditions and the following disclaimer. 9155324Simp * 2. Redistributions in binary form must reproduce the above copyright 10155324Simp * notice, this list of conditions and the following disclaimer in the 11155324Simp * documentation and/or other materials provided with the distribution. 12155324Simp * 13155324Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14155324Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15155324Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16155324Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17155324Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18155324Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19155324Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20155324Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21155324Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22155324Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23155324Simp */ 24155324Simp 25155324Simp/* TODO: (in no order) 26155324Simp * 27155324Simp * 8) Need to sync busdma goo in atestop 28155324Simp * 9) atestop should maybe free the mbufs? 29155324Simp * 30155324Simp * 1) detach 31155324Simp * 2) Free dma setup 32163522Simp * 3) Turn on the clock in pmc? Turn off? 33155324Simp */ 34155324Simp 35155324Simp#include <sys/cdefs.h> 36155324Simp__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 166901 2007-02-23 12:19:07Z piso $"); 37155324Simp 38155324Simp#include <sys/param.h> 39155324Simp#include <sys/systm.h> 40155324Simp#include <sys/bus.h> 41155324Simp#include <sys/kernel.h> 42155324Simp#include <sys/mbuf.h> 43155324Simp#include <sys/malloc.h> 44155324Simp#include <sys/module.h> 45155324Simp#include <sys/rman.h> 46155324Simp#include <sys/socket.h> 47155324Simp#include <sys/sockio.h> 48163522Simp#include <sys/sysctl.h> 49155324Simp#include <machine/bus.h> 50155324Simp 51155324Simp#include <net/ethernet.h> 52155324Simp#include <net/if.h> 53155324Simp#include <net/if_arp.h> 54155324Simp#include <net/if_dl.h> 55155324Simp#include <net/if_media.h> 56155324Simp#include <net/if_mib.h> 57155324Simp#include <net/if_types.h> 58155324Simp 59155324Simp#ifdef INET 60155324Simp#include <netinet/in.h> 61155324Simp#include <netinet/in_systm.h> 62155324Simp#include <netinet/in_var.h> 63155324Simp#include <netinet/ip.h> 64155324Simp#endif 65155324Simp 66155324Simp#include <net/bpf.h> 67155324Simp#include <net/bpfdesc.h> 68155324Simp 69155324Simp#include <dev/mii/mii.h> 70155324Simp#include <dev/mii/miivar.h> 71155324Simp#include <arm/at91/if_atereg.h> 72155324Simp 73155324Simp#include "miibus_if.h" 74155324Simp 75165778Sticso#define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 76156831Simp#define ATE_MAX_RX_BUFFERS 64 77155324Simp 78155324Simpstruct ate_softc 79155324Simp{ 80155324Simp struct ifnet *ifp; /* ifnet pointer */ 81155324Simp struct mtx sc_mtx; /* basically a perimeter lock */ 82155324Simp device_t dev; /* Myself */ 83155324Simp device_t miibus; /* My child miibus */ 84155324Simp void *intrhand; /* Interrupt handle */ 85155324Simp struct resource *irq_res; /* IRQ resource */ 86155324Simp struct resource *mem_res; /* Memory resource */ 87155324Simp struct callout tick_ch; /* Tick callout */ 88155324Simp bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 89155324Simp bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 90157562Simp struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 91155324Simp bus_dma_tag_t rxtag; 92155324Simp bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 93157562Simp void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 94157562Simp int rx_buf_ptr; 95155324Simp bus_dma_tag_t rx_desc_tag; 96155324Simp bus_dmamap_t rx_desc_map; 97155324Simp int txcur; /* current tx map pointer */ 98155324Simp bus_addr_t rx_desc_phys; 99155324Simp eth_rx_desc_t *rx_descs; 100159708Simp int use_rmii; 101155324Simp struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 102155324Simp}; 103155324Simp 104155324Simpstatic inline uint32_t 105155324SimpRD4(struct ate_softc *sc, bus_size_t off) 106155324Simp{ 107155324Simp return bus_read_4(sc->mem_res, off); 108155324Simp} 109155324Simp 110155324Simpstatic inline void 111155324SimpWR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 112155324Simp{ 113155324Simp bus_write_4(sc->mem_res, off, val); 114155324Simp} 115155324Simp 116155324Simp#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 117155324Simp#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 118155324Simp#define ATE_LOCK_INIT(_sc) \ 119155324Simp mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 120155324Simp MTX_NETWORK_LOCK, MTX_DEF) 121155324Simp#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 122155324Simp#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 123155324Simp#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 124155324Simp 125155324Simpstatic devclass_t ate_devclass; 126155324Simp 127155324Simp/* ifnet entry points */ 128155324Simp 129155324Simpstatic void ateinit_locked(void *); 130155324Simpstatic void atestart_locked(struct ifnet *); 131155324Simp 132155324Simpstatic void ateinit(void *); 133155324Simpstatic void atestart(struct ifnet *); 134155324Simpstatic void atestop(struct ate_softc *); 135155324Simpstatic int ateioctl(struct ifnet * ifp, u_long, caddr_t); 136155324Simp 137155324Simp/* bus entry points */ 138155324Simp 139155324Simpstatic int ate_probe(device_t dev); 140155324Simpstatic int ate_attach(device_t dev); 141155324Simpstatic int ate_detach(device_t dev); 142155324Simpstatic void ate_intr(void *); 143155324Simp 144155324Simp/* helper routines */ 145155324Simpstatic int ate_activate(device_t dev); 146155324Simpstatic void ate_deactivate(device_t dev); 147155324Simpstatic int ate_ifmedia_upd(struct ifnet *ifp); 148155324Simpstatic void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 149166573Simpstatic int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 150155445Scognetstatic void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 151155324Simp 152155324Simp/* 153155324Simp * The AT91 family of products has the ethernet called EMAC. However, 154155324Simp * it isn't self identifying. It is anticipated that the parent bus 155155324Simp * code will take care to only add ate devices where they really are. As 156155324Simp * such, we do nothing here to identify the device and just set its name. 157155324Simp */ 158155324Simpstatic int 159155324Simpate_probe(device_t dev) 160155324Simp{ 161155324Simp device_set_desc(dev, "EMAC"); 162155324Simp return (0); 163155324Simp} 164155324Simp 165155324Simpstatic int 166155324Simpate_attach(device_t dev) 167155324Simp{ 168155324Simp struct ate_softc *sc = device_get_softc(dev); 169155324Simp struct ifnet *ifp = NULL; 170163522Simp struct sysctl_ctx_list *sctx; 171163522Simp struct sysctl_oid *soid; 172155324Simp int err; 173155324Simp u_char eaddr[6]; 174155324Simp 175155324Simp sc->dev = dev; 176155324Simp err = ate_activate(dev); 177155324Simp if (err) 178155324Simp goto out; 179155324Simp 180159708Simp sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 181159708Simp 182163522Simp /*Sysctls*/ 183163522Simp sctx = device_get_sysctl_ctx(dev); 184163522Simp soid = device_get_sysctl_tree(dev); 185163522Simp SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 186163522Simp CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 187163522Simp 188155324Simp /* calling atestop before ifp is set is OK */ 189155324Simp atestop(sc); 190155324Simp ATE_LOCK_INIT(sc); 191155324Simp callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 192155324Simp 193166573Simp if ((err = ate_get_mac(sc, eaddr)) != 0) { 194166573Simp device_printf(dev, "No MAC address set"); 195166573Simp goto out; 196166573Simp } 197155445Scognet ate_set_mac(sc, eaddr); 198155324Simp 199155405Scognet sc->ifp = ifp = if_alloc(IFT_ETHER); 200155324Simp if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 201155324Simp device_printf(dev, "Cannot find my PHY.\n"); 202155324Simp err = ENXIO; 203155324Simp goto out; 204155324Simp } 205155324Simp 206155324Simp ifp->if_softc = sc; 207155324Simp if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 208155324Simp ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 209165779Sticso ifp->if_capabilities |= IFCAP_VLAN_MTU; 210165779Sticso ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 211155324Simp ifp->if_start = atestart; 212155324Simp ifp->if_ioctl = ateioctl; 213155324Simp ifp->if_init = ateinit; 214155324Simp ifp->if_baudrate = 10000000; 215155324Simp IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 216166625Smlaier ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 217155324Simp IFQ_SET_READY(&ifp->if_snd); 218155324Simp ifp->if_timer = 0; 219155324Simp ifp->if_linkmib = &sc->mibdata; 220155324Simp ifp->if_linkmiblen = sizeof(sc->mibdata); 221155324Simp sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 222155324Simp 223155324Simp ether_ifattach(ifp, eaddr); 224155324Simp 225155324Simp /* 226155324Simp * Activate the interrupt 227155324Simp */ 228155324Simp err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 229166901Spiso NULL, ate_intr, sc, &sc->intrhand); 230155324Simp if (err) { 231155324Simp ether_ifdetach(ifp); 232155324Simp ATE_LOCK_DESTROY(sc); 233155324Simp } 234155324Simpout:; 235155324Simp if (err) 236155324Simp ate_deactivate(dev); 237155324Simp if (err && ifp) 238155324Simp if_free(ifp); 239155324Simp return (err); 240155324Simp} 241155324Simp 242155324Simpstatic int 243155324Simpate_detach(device_t dev) 244155324Simp{ 245155324Simp return EBUSY; /* XXX TODO(1) */ 246155324Simp} 247155324Simp 248155324Simpstatic void 249155324Simpate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 250155324Simp{ 251155324Simp struct ate_softc *sc; 252155324Simp 253155324Simp if (error != 0) 254155324Simp return; 255155324Simp sc = (struct ate_softc *)arg; 256155324Simp sc->rx_desc_phys = segs[0].ds_addr; 257155324Simp} 258155324Simp 259157562Simpstatic void 260157562Simpate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 261157562Simp{ 262157562Simp struct ate_softc *sc; 263157562Simp int i; 264157562Simp 265157562Simp if (error != 0) 266157562Simp return; 267157562Simp sc = (struct ate_softc *)arg; 268157562Simp i = sc->rx_buf_ptr; 269157562Simp 270157562Simp /* 271157562Simp * For the last buffer, set the wrap bit so the controller 272157562Simp * restarts from the first descriptor. 273157562Simp */ 274163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 275157562Simp if (i == ATE_MAX_RX_BUFFERS - 1) 276157562Simp sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 277157562Simp else 278157562Simp sc->rx_descs[i].addr = segs[0].ds_addr; 279163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 280157562Simp sc->rx_descs[i].status = 0; 281157562Simp /* Flush the memory in the mbuf */ 282157562Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 283157562Simp} 284157562Simp 285155324Simp/* 286155324Simp * Compute the multicast filter for this device using the standard 287155324Simp * algorithm. I wonder why this isn't in ether somewhere as a lot 288155324Simp * of different MAC chips use this method (or the reverse the bits) 289155324Simp * method. 290155324Simp */ 291155324Simpstatic void 292155324Simpate_setmcast(struct ate_softc *sc) 293155324Simp{ 294155324Simp uint32_t index; 295155324Simp uint32_t mcaf[2]; 296155324Simp u_char *af = (u_char *) mcaf; 297155324Simp struct ifmultiaddr *ifma; 298155324Simp 299155324Simp mcaf[0] = 0; 300155324Simp mcaf[1] = 0; 301155324Simp 302155324Simp IF_ADDR_LOCK(sc->ifp); 303155324Simp TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 304155324Simp if (ifma->ifma_addr->sa_family != AF_LINK) 305155324Simp continue; 306155324Simp index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 307155324Simp ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 308155324Simp af[index >> 3] |= 1 << (index & 7); 309155324Simp } 310155324Simp IF_ADDR_UNLOCK(sc->ifp); 311155324Simp 312155324Simp /* 313155324Simp * Write the hash to the hash register. This card can also 314155324Simp * accept unicast packets as well as multicast packets using this 315155324Simp * register for easier bridging operations, but we don't take 316155324Simp * advantage of that. Locks here are to avoid LOR with the 317155324Simp * IF_ADDR_LOCK, but might not be strictly necessary. 318155324Simp */ 319155324Simp WR4(sc, ETH_HSL, mcaf[0]); 320155324Simp WR4(sc, ETH_HSH, mcaf[1]); 321155324Simp} 322155324Simp 323155324Simpstatic int 324155324Simpate_activate(device_t dev) 325155324Simp{ 326155324Simp struct ate_softc *sc; 327155324Simp int rid, err, i; 328155324Simp 329155324Simp sc = device_get_softc(dev); 330155324Simp rid = 0; 331155324Simp sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 332155324Simp RF_ACTIVE); 333155324Simp if (sc->mem_res == NULL) 334155324Simp goto errout; 335155324Simp rid = 0; 336155324Simp sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 337155324Simp RF_ACTIVE); 338163522Simp if (sc->irq_res == NULL) 339155324Simp goto errout; 340155324Simp 341155324Simp /* 342155324Simp * Allocate DMA tags and maps 343155324Simp */ 344155324Simp err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 345155324Simp BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 346155324Simp busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 347155324Simp if (err != 0) 348155324Simp goto errout; 349155324Simp for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 350155324Simp err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 351155324Simp if (err != 0) 352155324Simp goto errout; 353155324Simp } 354155324Simp /* 355155324Simp * Allocate our Rx buffers. This chip has a rx structure that's filled 356155324Simp * in 357155324Simp */ 358155324Simp 359155324Simp /* 360155324Simp * Allocate DMA tags and maps for RX. 361155324Simp */ 362155324Simp err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 363155324Simp BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 364155324Simp busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 365155324Simp if (err != 0) 366155324Simp goto errout; 367155324Simp 368155324Simp /* Dma TAG and MAP for the rx descriptors. */ 369155324Simp err = bus_dma_tag_create(NULL, sizeof(eth_rx_desc_t), 0, 370155324Simp BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 371155324Simp ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 372155324Simp ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 373155324Simp &sc->sc_mtx, &sc->rx_desc_tag); 374155324Simp if (err != 0) 375155324Simp goto errout; 376156831Simp if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 377156831Simp BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 378155324Simp goto errout; 379157562Simp if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 380155324Simp sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 381155324Simp ate_getaddr, sc, 0) != 0) 382155324Simp goto errout; 383155324Simp /* XXX TODO(5) Put this in ateinit_locked? */ 384155324Simp for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 385157562Simp sc->rx_buf_ptr = i; 386157562Simp if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 387157562Simp BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 388155324Simp goto errout; 389157562Simp if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 390157562Simp MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 391157562Simp goto errout; 392155324Simp } 393157562Simp sc->rx_buf_ptr = 0; 394156831Simp /* Flush the memory for the EMAC rx descriptor */ 395155324Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 396155324Simp /* Write the descriptor queue address. */ 397155324Simp WR4(sc, ETH_RBQP, sc->rx_desc_phys); 398155324Simp return (0); 399155324Simperrout: 400155324Simp ate_deactivate(dev); 401155324Simp return (ENOMEM); 402155324Simp} 403155324Simp 404155324Simpstatic void 405155324Simpate_deactivate(device_t dev) 406155324Simp{ 407155324Simp struct ate_softc *sc; 408155324Simp 409155324Simp sc = device_get_softc(dev); 410155324Simp /* XXX TODO(2) teardown busdma junk, below from fxp -- customize */ 411155324Simp#if 0 412155324Simp if (sc->fxp_mtag) { 413155324Simp for (i = 0; i < FXP_NRFABUFS; i++) { 414155324Simp rxp = &sc->fxp_desc.rx_list[i]; 415155324Simp if (rxp->rx_mbuf != NULL) { 416155324Simp bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 417155324Simp BUS_DMASYNC_POSTREAD); 418155324Simp bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 419155324Simp m_freem(rxp->rx_mbuf); 420155324Simp } 421155324Simp bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 422155324Simp } 423155324Simp bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 424155324Simp for (i = 0; i < FXP_NTXCB; i++) { 425155324Simp txp = &sc->fxp_desc.tx_list[i]; 426155324Simp if (txp->tx_mbuf != NULL) { 427155324Simp bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 428155324Simp BUS_DMASYNC_POSTWRITE); 429155324Simp bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 430155324Simp m_freem(txp->tx_mbuf); 431155324Simp } 432155324Simp bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 433155324Simp } 434155324Simp bus_dma_tag_destroy(sc->fxp_mtag); 435155324Simp } 436155324Simp if (sc->fxp_stag) 437155324Simp bus_dma_tag_destroy(sc->fxp_stag); 438155324Simp if (sc->cbl_tag) 439155324Simp bus_dma_tag_destroy(sc->cbl_tag); 440155324Simp if (sc->mcs_tag) 441155324Simp bus_dma_tag_destroy(sc->mcs_tag); 442155324Simp#endif 443155324Simp if (sc->intrhand) 444155324Simp bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 445155324Simp sc->intrhand = 0; 446155324Simp bus_generic_detach(sc->dev); 447155324Simp if (sc->miibus) 448155324Simp device_delete_child(sc->dev, sc->miibus); 449155324Simp if (sc->mem_res) 450155324Simp bus_release_resource(dev, SYS_RES_IOPORT, 451155324Simp rman_get_rid(sc->mem_res), sc->mem_res); 452155324Simp sc->mem_res = 0; 453155324Simp if (sc->irq_res) 454155324Simp bus_release_resource(dev, SYS_RES_IRQ, 455155324Simp rman_get_rid(sc->irq_res), sc->irq_res); 456155324Simp sc->irq_res = 0; 457155324Simp return; 458155324Simp} 459155324Simp 460155324Simp/* 461155324Simp * Change media according to request. 462155324Simp */ 463155324Simpstatic int 464155324Simpate_ifmedia_upd(struct ifnet *ifp) 465155324Simp{ 466155324Simp struct ate_softc *sc = ifp->if_softc; 467155324Simp struct mii_data *mii; 468155324Simp 469155324Simp mii = device_get_softc(sc->miibus); 470155324Simp ATE_LOCK(sc); 471155324Simp mii_mediachg(mii); 472155324Simp ATE_UNLOCK(sc); 473155324Simp return (0); 474155324Simp} 475155324Simp 476155324Simp/* 477155324Simp * Notify the world which media we're using. 478155324Simp */ 479155324Simpstatic void 480155324Simpate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 481155324Simp{ 482155324Simp struct ate_softc *sc = ifp->if_softc; 483155324Simp struct mii_data *mii; 484155324Simp 485155324Simp mii = device_get_softc(sc->miibus); 486155324Simp ATE_LOCK(sc); 487155324Simp mii_pollstat(mii); 488155324Simp ifmr->ifm_active = mii->mii_media_active; 489155324Simp ifmr->ifm_status = mii->mii_media_status; 490155324Simp ATE_UNLOCK(sc); 491155324Simp} 492155324Simp 493155324Simpstatic void 494163937Simpate_stat_update(struct ate_softc *sc, int active) 495163937Simp{ 496163937Simp /* 497163937Simp * The speed and full/half-duplex state needs to be reflected 498163937Simp * in the ETH_CFG register. 499163937Simp */ 500163937Simp if (IFM_SUBTYPE(active) == IFM_10_T) 501163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_SPD); 502163937Simp else 503163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_SPD); 504163937Simp if (active & IFM_FDX) 505163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_FD); 506163937Simp else 507163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_FD); 508163937Simp} 509163937Simp 510163937Simpstatic void 511155324Simpate_tick(void *xsc) 512155324Simp{ 513155324Simp struct ate_softc *sc = xsc; 514163937Simp struct ifnet *ifp = sc->ifp; 515155324Simp struct mii_data *mii; 516155324Simp int active; 517163937Simp uint32_t c; 518155324Simp 519155324Simp /* 520155324Simp * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 521155324Simp * the MII if there's a link if this bit is clear. Not sure if we 522155324Simp * should do the same thing here or not. 523155324Simp */ 524155324Simp ATE_ASSERT_LOCKED(sc); 525155324Simp if (sc->miibus != NULL) { 526155324Simp mii = device_get_softc(sc->miibus); 527155324Simp active = mii->mii_media_active; 528155324Simp mii_tick(mii); 529155324Simp if (mii->mii_media_status & IFM_ACTIVE && 530163937Simp active != mii->mii_media_active) 531163937Simp ate_stat_update(sc, mii->mii_media_active); 532155324Simp } 533155324Simp 534155324Simp /* 535155324Simp * Update the stats as best we can. When we're done, clear 536155324Simp * the status counters and start over. We're supposed to read these 537155324Simp * registers often enough that they won't overflow. Hopefully 538155324Simp * once a second is often enough. Some don't map well to 539155324Simp * the dot3Stats mib, so for those we just count them as general 540155324Simp * errors. Stats for iframes, ibutes, oframes and obytes are 541155324Simp * collected elsewhere. These registers zero on a read to prevent 542163937Simp * races. For all the collision stats, also update the collision 543163937Simp * stats for the interface. 544155324Simp */ 545155324Simp sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 546155324Simp sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 547163937Simp c = RD4(sc, ETH_SCOL); 548163937Simp ifp->if_collisions += c; 549163937Simp sc->mibdata.dot3StatsSingleCollisionFrames += c; 550163937Simp c = RD4(sc, ETH_MCOL); 551163937Simp sc->mibdata.dot3StatsMultipleCollisionFrames += c; 552163937Simp ifp->if_collisions += c; 553155324Simp sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 554155324Simp sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 555163937Simp c = RD4(sc, ETH_LCOL); 556163937Simp sc->mibdata.dot3StatsLateCollisions += c; 557163937Simp ifp->if_collisions += c; 558163937Simp c = RD4(sc, ETH_ECOL); 559163937Simp sc->mibdata.dot3StatsExcessiveCollisions += c; 560163937Simp ifp->if_collisions += c; 561155324Simp sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 562155324Simp sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 563155324Simp sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 564155324Simp /* 565155324Simp * not sure where to lump these, so count them against the errors 566155324Simp * for the interface. 567155324Simp */ 568163937Simp sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 569155324Simp sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 570155324Simp RD4(sc, ETH_USF); 571155324Simp 572155324Simp /* 573155324Simp * Schedule another timeout one second from now. 574155324Simp */ 575155324Simp callout_reset(&sc->tick_ch, hz, ate_tick, sc); 576155324Simp} 577155324Simp 578155324Simpstatic void 579155445Scognetate_set_mac(struct ate_softc *sc, u_char *eaddr) 580155445Scognet{ 581155445Scognet WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 582155445Scognet (eaddr[1] << 8) | eaddr[0]); 583155445Scognet WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 584155445Scognet 585155445Scognet} 586155445Scognet 587166573Simpstatic int 588155324Simpate_get_mac(struct ate_softc *sc, u_char *eaddr) 589155324Simp{ 590166573Simp uint32_t low, high; 591155324Simp 592166573Simp /* 593166573Simp * The boot loader setup the MAC with an address, if one is set in 594166573Simp * the loader. The TSC loader will also set the MAC address in a 595166573Simp * similar way. Grab the MAC address from the SA1[HL] registers. 596166573Simp */ 597166573Simp low = RD4(sc, ETH_SA1L); 598166573Simp high = RD4(sc, ETH_SA1H); 599166573Simp if ((low | (high & 0xffff)) == 0) 600166573Simp return (ENXIO); 601166573Simp eaddr[0] = (high >> 8) & 0xff; 602166573Simp eaddr[1] = high & 0xff; 603166573Simp eaddr[2] = (low >> 24) & 0xff; 604166573Simp eaddr[3] = (low >> 16) & 0xff; 605166573Simp eaddr[4] = (low >> 8) & 0xff; 606166573Simp eaddr[5] = low & 0xff; 607166573Simp return (0); 608155324Simp} 609155324Simp 610155324Simpstatic void 611155324Simpate_intr(void *xsc) 612155324Simp{ 613155324Simp struct ate_softc *sc = xsc; 614163937Simp struct ifnet *ifp = sc->ifp; 615155324Simp int status; 616155324Simp int i; 617157562Simp void *bp; 618157562Simp struct mbuf *mb; 619157562Simp uint32_t rx_stat; 620156831Simp 621155324Simp status = RD4(sc, ETH_ISR); 622155324Simp if (status == 0) 623155324Simp return; 624155324Simp if (status & ETH_ISR_RCOM) { 625155324Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 626155324Simp BUS_DMASYNC_POSTREAD); 627157562Simp while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 628157562Simp i = sc->rx_buf_ptr; 629157562Simp sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 630157562Simp bp = sc->rx_buf[i]; 631156831Simp rx_stat = sc->rx_descs[i].status; 632156831Simp if ((rx_stat & ETH_LEN_MASK) == 0) { 633156831Simp printf("ignoring bogus 0 len packet\n"); 634163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 635163937Simp BUS_DMASYNC_PREWRITE); 636157562Simp sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 637156831Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 638163937Simp BUS_DMASYNC_POSTWRITE); 639156831Simp continue; 640155324Simp } 641156831Simp /* Flush memory for mbuf so we don't get stale bytes */ 642156831Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 643156831Simp BUS_DMASYNC_POSTREAD); 644163937Simp WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 645163937Simp 646156831Simp /* 647156831Simp * The length returned by the device includes the 648156831Simp * ethernet CRC calculation for the packet, but 649156831Simp * ifnet drivers are supposed to discard it. 650156831Simp */ 651157562Simp mb = m_devget(sc->rx_buf[i], 652157562Simp (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 653163937Simp ETHER_ALIGN, ifp, NULL); 654163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 655163937Simp BUS_DMASYNC_PREWRITE); 656157562Simp sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 657157562Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 658163937Simp BUS_DMASYNC_POSTWRITE); 659156831Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 660156831Simp BUS_DMASYNC_PREREAD); 661163937Simp if (mb != NULL) { 662163937Simp ifp->if_ipackets++; 663163937Simp (*ifp->if_input)(ifp, mb); 664163937Simp } 665163937Simp 666155324Simp } 667155324Simp } 668155324Simp if (status & ETH_ISR_TCOM) { 669156831Simp ATE_LOCK(sc); 670163937Simp /* XXX TSR register should be cleared */ 671156831Simp if (sc->sent_mbuf[0]) { 672163937Simp bus_dmamap_sync(sc->rxtag, sc->tx_map[0], 673163937Simp BUS_DMASYNC_POSTWRITE); 674155324Simp m_freem(sc->sent_mbuf[0]); 675163937Simp ifp->if_opackets++; 676156831Simp sc->sent_mbuf[0] = NULL; 677156831Simp } 678155324Simp if (sc->sent_mbuf[1]) { 679155324Simp if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 680163937Simp bus_dmamap_sync(sc->rxtag, sc->tx_map[1], 681163937Simp BUS_DMASYNC_POSTWRITE); 682155324Simp m_freem(sc->sent_mbuf[1]); 683163937Simp ifp->if_opackets++; 684155324Simp sc->txcur = 0; 685155324Simp sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 686155324Simp } else { 687155324Simp sc->sent_mbuf[0] = sc->sent_mbuf[1]; 688155324Simp sc->sent_mbuf[1] = NULL; 689155324Simp sc->txcur = 1; 690155324Simp } 691155324Simp } else { 692155324Simp sc->sent_mbuf[0] = NULL; 693155324Simp sc->txcur = 0; 694155324Simp } 695156831Simp /* 696156831Simp * We're no longer busy, so clear the busy flag and call the 697156831Simp * start routine to xmit more packets. 698156831Simp */ 699156831Simp sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 700156831Simp atestart_locked(sc->ifp); 701156831Simp ATE_UNLOCK(sc); 702155324Simp } 703155324Simp if (status & ETH_ISR_RBNA) { 704156831Simp printf("RBNA workaround\n"); 705155324Simp /* Workaround Errata #11 */ 706155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) &~ ETH_CTL_RE); 707155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_RE); 708155324Simp } 709155324Simp} 710155324Simp 711155324Simp/* 712155324Simp * Reset and initialize the chip 713155324Simp */ 714155324Simpstatic void 715155324Simpateinit_locked(void *xsc) 716155324Simp{ 717155324Simp struct ate_softc *sc = xsc; 718155324Simp struct ifnet *ifp = sc->ifp; 719163937Simp struct mii_data *mii; 720155324Simp 721155324Simp ATE_ASSERT_LOCKED(sc); 722155324Simp 723155324Simp /* 724155324Simp * XXX TODO(3) 725155324Simp * we need to turn on the EMAC clock in the pmc. With the 726155324Simp * default boot loader, this is already turned on. However, we 727155324Simp * need to think about how best to turn it on/off as the interface 728155324Simp * is brought up/down, as well as dealing with the mii bus... 729155324Simp * 730155324Simp * We also need to multiplex the pins correctly. 731155324Simp */ 732155324Simp 733155324Simp /* 734155324Simp * There are two different ways that the mii bus is connected 735155324Simp * to this chip. Select the right one based on a compile-time 736155324Simp * option. 737155324Simp */ 738159708Simp if (sc->use_rmii) 739159708Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_RMII); 740159708Simp else 741159708Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_RMII); 742159708Simp 743155324Simp /* 744155324Simp * Turn on the multicast hash, and write 0's to it. 745155324Simp */ 746155324Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_MTI); 747155324Simp WR4(sc, ETH_HSH, 0); 748155324Simp WR4(sc, ETH_HSL, 0); 749155324Simp 750155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 751156831Simp WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 752155324Simp 753155324Simp /* 754155324Simp * Boot loader fills in MAC address. If that's not the case, then 755155324Simp * we should set SA1L and SA1H here to the appropriate value. Note: 756155324Simp * the byte order is big endian, not little endian, so we have some 757155324Simp * swapping to do. Again, if we need it (which I don't think we do). 758155324Simp */ 759155324Simp ate_setmcast(sc); 760155324Simp 761165779Sticso /* enable big packets */ 762165779Sticso WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 763165779Sticso 764155324Simp /* 765155324Simp * Set 'running' flag, and clear output active flag 766155324Simp * and attempt to start the output 767155324Simp */ 768155324Simp ifp->if_drv_flags |= IFF_DRV_RUNNING; 769155324Simp ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 770163937Simp 771163937Simp mii = device_get_softc(sc->miibus); 772163937Simp mii_pollstat(mii); 773163937Simp ate_stat_update(sc, mii->mii_media_active); 774155324Simp atestart_locked(ifp); 775155324Simp 776155324Simp callout_reset(&sc->tick_ch, hz, ate_tick, sc); 777155324Simp} 778155324Simp 779155324Simp/* 780155324Simp * dequeu packets and transmit 781155324Simp */ 782155324Simpstatic void 783155324Simpatestart_locked(struct ifnet *ifp) 784155324Simp{ 785155324Simp struct ate_softc *sc = ifp->if_softc; 786155324Simp struct mbuf *m, *mdefrag; 787155324Simp bus_dma_segment_t segs[1]; 788163937Simp int nseg, e; 789155324Simp 790155324Simp ATE_ASSERT_LOCKED(sc); 791155324Simp if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 792155324Simp return; 793155324Simp 794156831Simp while (sc->txcur < ATE_MAX_TX_BUFFERS) { 795156831Simp /* 796156831Simp * check to see if there's room to put another packet into the 797156831Simp * xmit queue. The EMAC chip has a ping-pong buffer for xmit 798156831Simp * packets. We use OACTIVE to indicate "we can stuff more into 799156831Simp * our buffers (clear) or not (set)." 800156831Simp */ 801156831Simp if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 802156831Simp ifp->if_drv_flags |= IFF_DRV_OACTIVE; 803156831Simp return; 804156831Simp } 805156831Simp IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 806156831Simp if (m == 0) { 807156831Simp ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 808156831Simp return; 809156831Simp } 810163937Simp e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 811163937Simp segs, &nseg, 0); 812163937Simp if (e == EFBIG) { 813163937Simp mdefrag = m_defrag(m, M_DONTWAIT); 814163937Simp if (mdefrag == NULL) { 815163937Simp IFQ_DRV_PREPEND(&ifp->if_snd, m); 816163937Simp return; 817163937Simp } 818163937Simp m = mdefrag; 819163937Simp e = bus_dmamap_load_mbuf_sg(sc->mtag, 820163937Simp sc->tx_map[sc->txcur], m, segs, &nseg, 0); 821156831Simp } 822163937Simp if (e != 0) { 823156831Simp m_freem(m); 824156831Simp continue; 825156831Simp } 826156831Simp bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 827156831Simp BUS_DMASYNC_PREWRITE); 828155324Simp 829156831Simp /* 830156831Simp * tell the hardware to xmit the packet. 831156831Simp */ 832156831Simp WR4(sc, ETH_TAR, segs[0].ds_addr); 833156831Simp WR4(sc, ETH_TCR, segs[0].ds_len); 834155324Simp 835156831Simp /* 836156831Simp * Tap off here if there is a bpf listener. 837156831Simp */ 838156831Simp BPF_MTAP(ifp, m); 839155324Simp 840156831Simp sc->sent_mbuf[sc->txcur] = m; 841156831Simp sc->txcur++; 842156831Simp } 843155324Simp} 844155324Simp 845155324Simpstatic void 846155324Simpateinit(void *xsc) 847155324Simp{ 848155324Simp struct ate_softc *sc = xsc; 849155324Simp ATE_LOCK(sc); 850155324Simp ateinit_locked(sc); 851155324Simp ATE_UNLOCK(sc); 852155324Simp} 853155324Simp 854155324Simpstatic void 855155324Simpatestart(struct ifnet *ifp) 856155324Simp{ 857155324Simp struct ate_softc *sc = ifp->if_softc; 858155324Simp ATE_LOCK(sc); 859155324Simp atestart_locked(ifp); 860155324Simp ATE_UNLOCK(sc); 861155324Simp} 862155324Simp 863155324Simp/* 864155324Simp * Turn off interrupts, and stop the nic. Can be called with sc->ifp NULL 865155324Simp * so be careful. 866155324Simp */ 867155324Simpstatic void 868155324Simpatestop(struct ate_softc *sc) 869155324Simp{ 870155324Simp struct ifnet *ifp = sc->ifp; 871155324Simp 872155324Simp if (ifp) { 873155324Simp ifp->if_timer = 0; 874155324Simp ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 875155324Simp } 876155324Simp 877155324Simp callout_stop(&sc->tick_ch); 878155324Simp 879155324Simp /* 880155324Simp * Enable some parts of the MAC that are needed always (like the 881155324Simp * MII bus. This turns off the RE and TE bits, which will remain 882155405Scognet * off until ateinit() is called to turn them on. With RE and TE 883155324Simp * turned off, there's no DMA to worry about after this write. 884155324Simp */ 885155324Simp WR4(sc, ETH_CTL, ETH_CTL_MPE); 886155324Simp 887155324Simp /* 888155324Simp * Turn off all the configured options and revert to defaults. 889155324Simp */ 890155324Simp WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 891155324Simp 892155324Simp /* 893155324Simp * Turn off all the interrupts, and ack any pending ones by reading 894155324Simp * the ISR. 895155324Simp */ 896155324Simp WR4(sc, ETH_IDR, 0xffffffff); 897155324Simp RD4(sc, ETH_ISR); 898155324Simp 899155324Simp /* 900155324Simp * Clear out the Transmit and Receiver Status registers of any 901155324Simp * errors they may be reporting 902155324Simp */ 903155324Simp WR4(sc, ETH_TSR, 0xffffffff); 904155324Simp WR4(sc, ETH_RSR, 0xffffffff); 905155324Simp 906155324Simp /* 907155324Simp * XXX TODO(8) 908155324Simp * need to worry about the busdma resources? Yes, I think we need 909155324Simp * to sync and unload them. We may also need to release the mbufs 910155324Simp * that are assocaited with RX and TX operations. 911155324Simp */ 912155324Simp 913155324Simp /* 914155324Simp * XXX we should power down the EMAC if it isn't in use, after 915155324Simp * putting it into loopback mode. This saves about 400uA according 916155324Simp * to the datasheet. 917155324Simp */ 918155324Simp} 919155324Simp 920155324Simpstatic int 921155324Simpateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 922155324Simp{ 923155324Simp struct ate_softc *sc = ifp->if_softc; 924157562Simp struct mii_data *mii; 925157562Simp struct ifreq *ifr = (struct ifreq *)data; 926165779Sticso int mask, error = 0; 927155324Simp 928155324Simp switch (cmd) { 929155324Simp case SIOCSIFFLAGS: 930155324Simp ATE_LOCK(sc); 931155324Simp if ((ifp->if_flags & IFF_UP) == 0 && 932155324Simp ifp->if_drv_flags & IFF_DRV_RUNNING) { 933155324Simp ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 934155324Simp atestop(sc); 935155324Simp } else { 936155324Simp /* reinitialize card on any parameter change */ 937155324Simp ateinit_locked(sc); 938155324Simp } 939155324Simp ATE_UNLOCK(sc); 940155324Simp break; 941155324Simp 942155324Simp case SIOCADDMULTI: 943155324Simp case SIOCDELMULTI: 944155324Simp /* update multicast filter list. */ 945157562Simp ATE_LOCK(sc); 946155324Simp ate_setmcast(sc); 947157562Simp ATE_UNLOCK(sc); 948155324Simp error = 0; 949155324Simp break; 950155324Simp 951157562Simp case SIOCSIFMEDIA: 952157562Simp case SIOCGIFMEDIA: 953157562Simp mii = device_get_softc(sc->miibus); 954157562Simp error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 955157562Simp break; 956165779Sticso case SIOCSIFCAP: 957165779Sticso mask = ifp->if_capenable ^ ifr->ifr_reqcap; 958165779Sticso if (mask & IFCAP_VLAN_MTU) { 959165779Sticso ATE_LOCK(sc); 960165779Sticso if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 961165779Sticso WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 962165779Sticso ifp->if_capenable |= IFCAP_VLAN_MTU; 963165779Sticso } else { 964165779Sticso WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 965165779Sticso ifp->if_capenable &= ~IFCAP_VLAN_MTU; 966165779Sticso } 967165779Sticso ATE_UNLOCK(sc); 968165779Sticso } 969155324Simp default: 970155324Simp error = ether_ioctl(ifp, cmd, data); 971155324Simp break; 972155324Simp } 973155324Simp return (error); 974155324Simp} 975155324Simp 976155324Simpstatic void 977155324Simpate_child_detached(device_t dev, device_t child) 978155324Simp{ 979155324Simp struct ate_softc *sc; 980155324Simp 981155324Simp sc = device_get_softc(dev); 982155324Simp if (child == sc->miibus) 983155324Simp sc->miibus = NULL; 984155324Simp} 985155324Simp 986155324Simp/* 987155324Simp * MII bus support routines. 988155324Simp */ 989155324Simpstatic int 990155324Simpate_miibus_readreg(device_t dev, int phy, int reg) 991155324Simp{ 992155324Simp struct ate_softc *sc; 993155324Simp int val; 994155324Simp 995155324Simp /* 996155324Simp * XXX if we implement agressive power savings, then we need 997155324Simp * XXX to make sure that the clock to the emac is on here 998155324Simp */ 999155324Simp 1000155324Simp if (phy != 0) 1001155324Simp return (0xffff); 1002155324Simp sc = device_get_softc(dev); 1003155324Simp DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1004155324Simp WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1005155324Simp while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1006155324Simp continue; 1007155324Simp val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1008155324Simp 1009155324Simp return (val); 1010155324Simp} 1011155324Simp 1012155324Simpstatic void 1013155324Simpate_miibus_writereg(device_t dev, int phy, int reg, int data) 1014155324Simp{ 1015155324Simp struct ate_softc *sc; 1016155324Simp 1017155324Simp /* 1018155324Simp * XXX if we implement agressive power savings, then we need 1019155324Simp * XXX to make sure that the clock to the emac is on here 1020155324Simp */ 1021155324Simp 1022155324Simp sc = device_get_softc(dev); 1023155324Simp WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1024155324Simp while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1025155324Simp continue; 1026155324Simp return; 1027155324Simp} 1028155324Simp 1029155324Simpstatic device_method_t ate_methods[] = { 1030155324Simp /* Device interface */ 1031155324Simp DEVMETHOD(device_probe, ate_probe), 1032155324Simp DEVMETHOD(device_attach, ate_attach), 1033155324Simp DEVMETHOD(device_detach, ate_detach), 1034155324Simp 1035155324Simp /* Bus interface */ 1036155324Simp DEVMETHOD(bus_child_detached, ate_child_detached), 1037155324Simp 1038155324Simp /* MII interface */ 1039155324Simp DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1040155324Simp DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1041155324Simp 1042155324Simp { 0, 0 } 1043155324Simp}; 1044155324Simp 1045155324Simpstatic driver_t ate_driver = { 1046155324Simp "ate", 1047155324Simp ate_methods, 1048155324Simp sizeof(struct ate_softc), 1049155324Simp}; 1050155324Simp 1051155324SimpDRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1052155324SimpDRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1053155324SimpMODULE_DEPEND(ate, miibus, 1, 1, 1); 1054155324SimpMODULE_DEPEND(ate, ether, 1, 1, 1); 1055