if_ate.c revision 165778
1155324Simp/*- 2155324Simp * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3155324Simp * 4155324Simp * Redistribution and use in source and binary forms, with or without 5155324Simp * modification, are permitted provided that the following conditions 6155324Simp * are met: 7155324Simp * 1. Redistributions of source code must retain the above copyright 8155324Simp * notice, this list of conditions and the following disclaimer. 9155324Simp * 2. Redistributions in binary form must reproduce the above copyright 10155324Simp * notice, this list of conditions and the following disclaimer in the 11155324Simp * documentation and/or other materials provided with the distribution. 12155324Simp * 13155324Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14155324Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15155324Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16155324Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17155324Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18155324Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19155324Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20155324Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21155324Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22155324Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23155324Simp */ 24155324Simp 25155324Simp/* TODO: (in no order) 26155324Simp * 27155324Simp * 8) Need to sync busdma goo in atestop 28155324Simp * 9) atestop should maybe free the mbufs? 29155324Simp * 30155324Simp * 1) detach 31155324Simp * 2) Free dma setup 32163522Simp * 3) Turn on the clock in pmc? Turn off? 33155324Simp */ 34155324Simp 35155324Simp#include <sys/cdefs.h> 36155324Simp__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 165778 2007-01-05 01:01:14Z ticso $"); 37155324Simp 38155324Simp#include <sys/param.h> 39155324Simp#include <sys/systm.h> 40155324Simp#include <sys/bus.h> 41155324Simp#include <sys/kernel.h> 42155324Simp#include <sys/mbuf.h> 43155324Simp#include <sys/malloc.h> 44155324Simp#include <sys/module.h> 45155324Simp#include <sys/rman.h> 46155324Simp#include <sys/socket.h> 47155324Simp#include <sys/sockio.h> 48163522Simp#include <sys/sysctl.h> 49155324Simp#include <machine/bus.h> 50155324Simp 51155324Simp#include <net/ethernet.h> 52155324Simp#include <net/if.h> 53155324Simp#include <net/if_arp.h> 54155324Simp#include <net/if_dl.h> 55155324Simp#include <net/if_media.h> 56155324Simp#include <net/if_mib.h> 57155324Simp#include <net/if_types.h> 58155324Simp 59155324Simp#ifdef INET 60155324Simp#include <netinet/in.h> 61155324Simp#include <netinet/in_systm.h> 62155324Simp#include <netinet/in_var.h> 63155324Simp#include <netinet/ip.h> 64155324Simp#endif 65155324Simp 66155324Simp#include <net/bpf.h> 67155324Simp#include <net/bpfdesc.h> 68155324Simp 69155324Simp#include <dev/mii/mii.h> 70155324Simp#include <dev/mii/miivar.h> 71155324Simp#include <arm/at91/if_atereg.h> 72155324Simp 73155324Simp#include "miibus_if.h" 74155324Simp 75165778Sticso#define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 76156831Simp#define ATE_MAX_RX_BUFFERS 64 77155324Simp 78155324Simpstruct ate_softc 79155324Simp{ 80155324Simp struct ifnet *ifp; /* ifnet pointer */ 81155324Simp struct mtx sc_mtx; /* basically a perimeter lock */ 82155324Simp device_t dev; /* Myself */ 83155324Simp device_t miibus; /* My child miibus */ 84155324Simp void *intrhand; /* Interrupt handle */ 85155324Simp struct resource *irq_res; /* IRQ resource */ 86155324Simp struct resource *mem_res; /* Memory resource */ 87155324Simp struct callout tick_ch; /* Tick callout */ 88155324Simp bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 89155324Simp bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 90157562Simp struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 91155324Simp bus_dma_tag_t rxtag; 92155324Simp bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 93157562Simp void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 94157562Simp int rx_buf_ptr; 95155324Simp bus_dma_tag_t rx_desc_tag; 96155324Simp bus_dmamap_t rx_desc_map; 97155324Simp int txcur; /* current tx map pointer */ 98155324Simp bus_addr_t rx_desc_phys; 99155324Simp eth_rx_desc_t *rx_descs; 100159708Simp int use_rmii; 101155324Simp struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 102155324Simp}; 103155324Simp 104155324Simpstatic inline uint32_t 105155324SimpRD4(struct ate_softc *sc, bus_size_t off) 106155324Simp{ 107155324Simp return bus_read_4(sc->mem_res, off); 108155324Simp} 109155324Simp 110155324Simpstatic inline void 111155324SimpWR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 112155324Simp{ 113155324Simp bus_write_4(sc->mem_res, off, val); 114155324Simp} 115155324Simp 116155324Simp#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 117155324Simp#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 118155324Simp#define ATE_LOCK_INIT(_sc) \ 119155324Simp mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 120155324Simp MTX_NETWORK_LOCK, MTX_DEF) 121155324Simp#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 122155324Simp#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 123155324Simp#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 124155324Simp 125155324Simpstatic devclass_t ate_devclass; 126155324Simp 127155324Simp/* ifnet entry points */ 128155324Simp 129155324Simpstatic void ateinit_locked(void *); 130155324Simpstatic void atestart_locked(struct ifnet *); 131155324Simp 132155324Simpstatic void ateinit(void *); 133155324Simpstatic void atestart(struct ifnet *); 134155324Simpstatic void atestop(struct ate_softc *); 135155324Simpstatic int ateioctl(struct ifnet * ifp, u_long, caddr_t); 136155324Simp 137155324Simp/* bus entry points */ 138155324Simp 139155324Simpstatic int ate_probe(device_t dev); 140155324Simpstatic int ate_attach(device_t dev); 141155324Simpstatic int ate_detach(device_t dev); 142155324Simpstatic void ate_intr(void *); 143155324Simp 144155324Simp/* helper routines */ 145155324Simpstatic int ate_activate(device_t dev); 146155324Simpstatic void ate_deactivate(device_t dev); 147155324Simpstatic int ate_ifmedia_upd(struct ifnet *ifp); 148155324Simpstatic void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 149155324Simpstatic void ate_get_mac(struct ate_softc *sc, u_char *eaddr); 150155445Scognetstatic void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 151155324Simp 152155324Simp/* 153155324Simp * The AT91 family of products has the ethernet called EMAC. However, 154155324Simp * it isn't self identifying. It is anticipated that the parent bus 155155324Simp * code will take care to only add ate devices where they really are. As 156155324Simp * such, we do nothing here to identify the device and just set its name. 157155324Simp */ 158155324Simpstatic int 159155324Simpate_probe(device_t dev) 160155324Simp{ 161155324Simp device_set_desc(dev, "EMAC"); 162155324Simp return (0); 163155324Simp} 164155324Simp 165155324Simpstatic int 166155324Simpate_attach(device_t dev) 167155324Simp{ 168155324Simp struct ate_softc *sc = device_get_softc(dev); 169155324Simp struct ifnet *ifp = NULL; 170163522Simp struct sysctl_ctx_list *sctx; 171163522Simp struct sysctl_oid *soid; 172155324Simp int err; 173155324Simp u_char eaddr[6]; 174155324Simp 175155324Simp sc->dev = dev; 176155324Simp err = ate_activate(dev); 177155324Simp if (err) 178155324Simp goto out; 179155324Simp 180159708Simp sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 181159708Simp 182163522Simp 183163522Simp /*Sysctls*/ 184163522Simp sctx = device_get_sysctl_ctx(dev); 185163522Simp soid = device_get_sysctl_tree(dev); 186163522Simp SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 187163522Simp CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 188163522Simp 189155324Simp /* calling atestop before ifp is set is OK */ 190155324Simp atestop(sc); 191155324Simp ATE_LOCK_INIT(sc); 192155324Simp callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 193155324Simp 194155324Simp ate_get_mac(sc, eaddr); 195155445Scognet ate_set_mac(sc, eaddr); 196155324Simp 197155405Scognet sc->ifp = ifp = if_alloc(IFT_ETHER); 198155324Simp if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 199155324Simp device_printf(dev, "Cannot find my PHY.\n"); 200155324Simp err = ENXIO; 201155324Simp goto out; 202155324Simp } 203155324Simp 204155324Simp ifp->if_softc = sc; 205155324Simp if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 206155324Simp ifp->if_mtu = ETHERMTU; 207155324Simp ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 208155324Simp ifp->if_start = atestart; 209155324Simp ifp->if_ioctl = ateioctl; 210155324Simp ifp->if_init = ateinit; 211155324Simp ifp->if_baudrate = 10000000; 212155324Simp IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 213155324Simp ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 214155324Simp IFQ_SET_READY(&ifp->if_snd); 215155324Simp ifp->if_timer = 0; 216155324Simp ifp->if_linkmib = &sc->mibdata; 217155324Simp ifp->if_linkmiblen = sizeof(sc->mibdata); 218155324Simp sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 219155324Simp 220155324Simp ether_ifattach(ifp, eaddr); 221155324Simp 222155324Simp /* 223155324Simp * Activate the interrupt 224155324Simp */ 225155324Simp err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 226155324Simp ate_intr, sc, &sc->intrhand); 227155324Simp if (err) { 228155324Simp ether_ifdetach(ifp); 229155324Simp ATE_LOCK_DESTROY(sc); 230155324Simp } 231155324Simpout:; 232155324Simp if (err) 233155324Simp ate_deactivate(dev); 234155324Simp if (err && ifp) 235155324Simp if_free(ifp); 236155324Simp return (err); 237155324Simp} 238155324Simp 239155324Simpstatic int 240155324Simpate_detach(device_t dev) 241155324Simp{ 242155324Simp return EBUSY; /* XXX TODO(1) */ 243155324Simp} 244155324Simp 245155324Simpstatic void 246155324Simpate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 247155324Simp{ 248155324Simp struct ate_softc *sc; 249155324Simp 250155324Simp if (error != 0) 251155324Simp return; 252155324Simp sc = (struct ate_softc *)arg; 253155324Simp sc->rx_desc_phys = segs[0].ds_addr; 254155324Simp} 255155324Simp 256157562Simpstatic void 257157562Simpate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 258157562Simp{ 259157562Simp struct ate_softc *sc; 260157562Simp int i; 261157562Simp 262157562Simp if (error != 0) 263157562Simp return; 264157562Simp sc = (struct ate_softc *)arg; 265157562Simp i = sc->rx_buf_ptr; 266157562Simp 267157562Simp /* 268157562Simp * For the last buffer, set the wrap bit so the controller 269157562Simp * restarts from the first descriptor. 270157562Simp */ 271163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 272157562Simp if (i == ATE_MAX_RX_BUFFERS - 1) 273157562Simp sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 274157562Simp else 275157562Simp sc->rx_descs[i].addr = segs[0].ds_addr; 276163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 277157562Simp sc->rx_descs[i].status = 0; 278157562Simp /* Flush the memory in the mbuf */ 279157562Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 280157562Simp} 281157562Simp 282155324Simp/* 283155324Simp * Compute the multicast filter for this device using the standard 284155324Simp * algorithm. I wonder why this isn't in ether somewhere as a lot 285155324Simp * of different MAC chips use this method (or the reverse the bits) 286155324Simp * method. 287155324Simp */ 288155324Simpstatic void 289155324Simpate_setmcast(struct ate_softc *sc) 290155324Simp{ 291155324Simp uint32_t index; 292155324Simp uint32_t mcaf[2]; 293155324Simp u_char *af = (u_char *) mcaf; 294155324Simp struct ifmultiaddr *ifma; 295155324Simp 296155324Simp mcaf[0] = 0; 297155324Simp mcaf[1] = 0; 298155324Simp 299155324Simp IF_ADDR_LOCK(sc->ifp); 300155324Simp TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 301155324Simp if (ifma->ifma_addr->sa_family != AF_LINK) 302155324Simp continue; 303155324Simp index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 304155324Simp ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 305155324Simp af[index >> 3] |= 1 << (index & 7); 306155324Simp } 307155324Simp IF_ADDR_UNLOCK(sc->ifp); 308155324Simp 309155324Simp /* 310155324Simp * Write the hash to the hash register. This card can also 311155324Simp * accept unicast packets as well as multicast packets using this 312155324Simp * register for easier bridging operations, but we don't take 313155324Simp * advantage of that. Locks here are to avoid LOR with the 314155324Simp * IF_ADDR_LOCK, but might not be strictly necessary. 315155324Simp */ 316155324Simp WR4(sc, ETH_HSL, mcaf[0]); 317155324Simp WR4(sc, ETH_HSH, mcaf[1]); 318155324Simp} 319155324Simp 320155324Simpstatic int 321155324Simpate_activate(device_t dev) 322155324Simp{ 323155324Simp struct ate_softc *sc; 324155324Simp int rid, err, i; 325155324Simp 326155324Simp sc = device_get_softc(dev); 327155324Simp rid = 0; 328155324Simp sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 329155324Simp RF_ACTIVE); 330155324Simp if (sc->mem_res == NULL) 331155324Simp goto errout; 332155324Simp rid = 0; 333155324Simp sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 334155324Simp RF_ACTIVE); 335163522Simp if (sc->irq_res == NULL) 336155324Simp goto errout; 337155324Simp 338155324Simp /* 339155324Simp * Allocate DMA tags and maps 340155324Simp */ 341155324Simp err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 342155324Simp BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 343155324Simp busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 344155324Simp if (err != 0) 345155324Simp goto errout; 346155324Simp for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 347155324Simp err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 348155324Simp if (err != 0) 349155324Simp goto errout; 350155324Simp } 351155324Simp /* 352155324Simp * Allocate our Rx buffers. This chip has a rx structure that's filled 353155324Simp * in 354155324Simp */ 355155324Simp 356155324Simp /* 357155324Simp * Allocate DMA tags and maps for RX. 358155324Simp */ 359155324Simp err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 360155324Simp BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 361155324Simp busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 362155324Simp if (err != 0) 363155324Simp goto errout; 364155324Simp 365155324Simp /* Dma TAG and MAP for the rx descriptors. */ 366155324Simp err = bus_dma_tag_create(NULL, sizeof(eth_rx_desc_t), 0, 367155324Simp BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 368155324Simp ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 369155324Simp ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 370155324Simp &sc->sc_mtx, &sc->rx_desc_tag); 371155324Simp if (err != 0) 372155324Simp goto errout; 373156831Simp if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 374156831Simp BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 375155324Simp goto errout; 376157562Simp if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 377155324Simp sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 378155324Simp ate_getaddr, sc, 0) != 0) 379155324Simp goto errout; 380155324Simp /* XXX TODO(5) Put this in ateinit_locked? */ 381155324Simp for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 382157562Simp sc->rx_buf_ptr = i; 383157562Simp if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 384157562Simp BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 385155324Simp goto errout; 386157562Simp if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 387157562Simp MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 388157562Simp goto errout; 389155324Simp } 390157562Simp sc->rx_buf_ptr = 0; 391156831Simp /* Flush the memory for the EMAC rx descriptor */ 392155324Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 393155324Simp /* Write the descriptor queue address. */ 394155324Simp WR4(sc, ETH_RBQP, sc->rx_desc_phys); 395155324Simp return (0); 396155324Simperrout: 397155324Simp ate_deactivate(dev); 398155324Simp return (ENOMEM); 399155324Simp} 400155324Simp 401155324Simpstatic void 402155324Simpate_deactivate(device_t dev) 403155324Simp{ 404155324Simp struct ate_softc *sc; 405155324Simp 406155324Simp sc = device_get_softc(dev); 407155324Simp /* XXX TODO(2) teardown busdma junk, below from fxp -- customize */ 408155324Simp#if 0 409155324Simp if (sc->fxp_mtag) { 410155324Simp for (i = 0; i < FXP_NRFABUFS; i++) { 411155324Simp rxp = &sc->fxp_desc.rx_list[i]; 412155324Simp if (rxp->rx_mbuf != NULL) { 413155324Simp bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 414155324Simp BUS_DMASYNC_POSTREAD); 415155324Simp bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 416155324Simp m_freem(rxp->rx_mbuf); 417155324Simp } 418155324Simp bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 419155324Simp } 420155324Simp bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 421155324Simp for (i = 0; i < FXP_NTXCB; i++) { 422155324Simp txp = &sc->fxp_desc.tx_list[i]; 423155324Simp if (txp->tx_mbuf != NULL) { 424155324Simp bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 425155324Simp BUS_DMASYNC_POSTWRITE); 426155324Simp bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 427155324Simp m_freem(txp->tx_mbuf); 428155324Simp } 429155324Simp bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 430155324Simp } 431155324Simp bus_dma_tag_destroy(sc->fxp_mtag); 432155324Simp } 433155324Simp if (sc->fxp_stag) 434155324Simp bus_dma_tag_destroy(sc->fxp_stag); 435155324Simp if (sc->cbl_tag) 436155324Simp bus_dma_tag_destroy(sc->cbl_tag); 437155324Simp if (sc->mcs_tag) 438155324Simp bus_dma_tag_destroy(sc->mcs_tag); 439155324Simp#endif 440155324Simp if (sc->intrhand) 441155324Simp bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 442155324Simp sc->intrhand = 0; 443155324Simp bus_generic_detach(sc->dev); 444155324Simp if (sc->miibus) 445155324Simp device_delete_child(sc->dev, sc->miibus); 446155324Simp if (sc->mem_res) 447155324Simp bus_release_resource(dev, SYS_RES_IOPORT, 448155324Simp rman_get_rid(sc->mem_res), sc->mem_res); 449155324Simp sc->mem_res = 0; 450155324Simp if (sc->irq_res) 451155324Simp bus_release_resource(dev, SYS_RES_IRQ, 452155324Simp rman_get_rid(sc->irq_res), sc->irq_res); 453155324Simp sc->irq_res = 0; 454155324Simp return; 455155324Simp} 456155324Simp 457155324Simp/* 458155324Simp * Change media according to request. 459155324Simp */ 460155324Simpstatic int 461155324Simpate_ifmedia_upd(struct ifnet *ifp) 462155324Simp{ 463155324Simp struct ate_softc *sc = ifp->if_softc; 464155324Simp struct mii_data *mii; 465155324Simp 466155324Simp mii = device_get_softc(sc->miibus); 467155324Simp ATE_LOCK(sc); 468155324Simp mii_mediachg(mii); 469155324Simp ATE_UNLOCK(sc); 470155324Simp return (0); 471155324Simp} 472155324Simp 473155324Simp/* 474155324Simp * Notify the world which media we're using. 475155324Simp */ 476155324Simpstatic void 477155324Simpate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 478155324Simp{ 479155324Simp struct ate_softc *sc = ifp->if_softc; 480155324Simp struct mii_data *mii; 481155324Simp 482155324Simp mii = device_get_softc(sc->miibus); 483155324Simp ATE_LOCK(sc); 484155324Simp mii_pollstat(mii); 485155324Simp ifmr->ifm_active = mii->mii_media_active; 486155324Simp ifmr->ifm_status = mii->mii_media_status; 487155324Simp ATE_UNLOCK(sc); 488155324Simp} 489155324Simp 490155324Simpstatic void 491163937Simpate_stat_update(struct ate_softc *sc, int active) 492163937Simp{ 493163937Simp /* 494163937Simp * The speed and full/half-duplex state needs to be reflected 495163937Simp * in the ETH_CFG register. 496163937Simp */ 497163937Simp if (IFM_SUBTYPE(active) == IFM_10_T) 498163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_SPD); 499163937Simp else 500163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_SPD); 501163937Simp if (active & IFM_FDX) 502163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_FD); 503163937Simp else 504163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_FD); 505163937Simp} 506163937Simp 507163937Simpstatic void 508155324Simpate_tick(void *xsc) 509155324Simp{ 510155324Simp struct ate_softc *sc = xsc; 511163937Simp struct ifnet *ifp = sc->ifp; 512155324Simp struct mii_data *mii; 513155324Simp int active; 514163937Simp uint32_t c; 515155324Simp 516155324Simp /* 517155324Simp * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 518155324Simp * the MII if there's a link if this bit is clear. Not sure if we 519155324Simp * should do the same thing here or not. 520155324Simp */ 521155324Simp ATE_ASSERT_LOCKED(sc); 522155324Simp if (sc->miibus != NULL) { 523155324Simp mii = device_get_softc(sc->miibus); 524155324Simp active = mii->mii_media_active; 525155324Simp mii_tick(mii); 526155324Simp if (mii->mii_media_status & IFM_ACTIVE && 527163937Simp active != mii->mii_media_active) 528163937Simp ate_stat_update(sc, mii->mii_media_active); 529155324Simp } 530155324Simp 531155324Simp /* 532155324Simp * Update the stats as best we can. When we're done, clear 533155324Simp * the status counters and start over. We're supposed to read these 534155324Simp * registers often enough that they won't overflow. Hopefully 535155324Simp * once a second is often enough. Some don't map well to 536155324Simp * the dot3Stats mib, so for those we just count them as general 537155324Simp * errors. Stats for iframes, ibutes, oframes and obytes are 538155324Simp * collected elsewhere. These registers zero on a read to prevent 539163937Simp * races. For all the collision stats, also update the collision 540163937Simp * stats for the interface. 541155324Simp */ 542155324Simp sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 543155324Simp sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 544163937Simp c = RD4(sc, ETH_SCOL); 545163937Simp ifp->if_collisions += c; 546163937Simp sc->mibdata.dot3StatsSingleCollisionFrames += c; 547163937Simp c = RD4(sc, ETH_MCOL); 548163937Simp sc->mibdata.dot3StatsMultipleCollisionFrames += c; 549163937Simp ifp->if_collisions += c; 550155324Simp sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 551155324Simp sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 552163937Simp c = RD4(sc, ETH_LCOL); 553163937Simp sc->mibdata.dot3StatsLateCollisions += c; 554163937Simp ifp->if_collisions += c; 555163937Simp c = RD4(sc, ETH_ECOL); 556163937Simp sc->mibdata.dot3StatsExcessiveCollisions += c; 557163937Simp ifp->if_collisions += c; 558155324Simp sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 559155324Simp sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 560155324Simp sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 561155324Simp /* 562155324Simp * not sure where to lump these, so count them against the errors 563155324Simp * for the interface. 564155324Simp */ 565163937Simp sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 566155324Simp sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 567155324Simp RD4(sc, ETH_USF); 568155324Simp 569155324Simp /* 570155324Simp * Schedule another timeout one second from now. 571155324Simp */ 572155324Simp callout_reset(&sc->tick_ch, hz, ate_tick, sc); 573155324Simp} 574155324Simp 575155324Simpstatic void 576155445Scognetate_set_mac(struct ate_softc *sc, u_char *eaddr) 577155445Scognet{ 578155445Scognet WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 579155445Scognet (eaddr[1] << 8) | eaddr[0]); 580155445Scognet WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 581155445Scognet 582155445Scognet} 583155445Scognet 584155445Scognetstatic void 585155324Simpate_get_mac(struct ate_softc *sc, u_char *eaddr) 586155324Simp{ 587155324Simp uint32_t low, high; 588155324Simp 589155324Simp /* 590163937Simp * The boot loader setup the MAC with an address, if one is set in 591163937Simp * the loader. The TSC loader will also set the MAC address in a 592163937Simp * similar way. Grab the MAC address from the SA1[HL] registers. 593155324Simp */ 594155324Simp low = RD4(sc, ETH_SA1L); 595155324Simp high = RD4(sc, ETH_SA1H); 596155324Simp eaddr[0] = (high >> 8) & 0xff; 597155324Simp eaddr[1] = high & 0xff; 598155324Simp eaddr[2] = (low >> 24) & 0xff; 599155324Simp eaddr[3] = (low >> 16) & 0xff; 600155324Simp eaddr[4] = (low >> 8) & 0xff; 601155324Simp eaddr[5] = low & 0xff; 602155324Simp} 603155324Simp 604155324Simpstatic void 605155324Simpate_intr(void *xsc) 606155324Simp{ 607155324Simp struct ate_softc *sc = xsc; 608163937Simp struct ifnet *ifp = sc->ifp; 609155324Simp int status; 610155324Simp int i; 611157562Simp void *bp; 612157562Simp struct mbuf *mb; 613157562Simp uint32_t rx_stat; 614156831Simp 615155324Simp status = RD4(sc, ETH_ISR); 616155324Simp if (status == 0) 617155324Simp return; 618155324Simp if (status & ETH_ISR_RCOM) { 619155324Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 620155324Simp BUS_DMASYNC_POSTREAD); 621157562Simp while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 622157562Simp i = sc->rx_buf_ptr; 623157562Simp sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 624157562Simp bp = sc->rx_buf[i]; 625156831Simp rx_stat = sc->rx_descs[i].status; 626156831Simp if ((rx_stat & ETH_LEN_MASK) == 0) { 627156831Simp printf("ignoring bogus 0 len packet\n"); 628163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 629163937Simp BUS_DMASYNC_PREWRITE); 630157562Simp sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 631156831Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 632163937Simp BUS_DMASYNC_POSTWRITE); 633156831Simp continue; 634155324Simp } 635156831Simp /* Flush memory for mbuf so we don't get stale bytes */ 636156831Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 637156831Simp BUS_DMASYNC_POSTREAD); 638163937Simp WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 639163937Simp 640156831Simp /* 641156831Simp * The length returned by the device includes the 642156831Simp * ethernet CRC calculation for the packet, but 643156831Simp * ifnet drivers are supposed to discard it. 644156831Simp */ 645157562Simp mb = m_devget(sc->rx_buf[i], 646157562Simp (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 647163937Simp ETHER_ALIGN, ifp, NULL); 648163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 649163937Simp BUS_DMASYNC_PREWRITE); 650157562Simp sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 651157562Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 652163937Simp BUS_DMASYNC_POSTWRITE); 653156831Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 654156831Simp BUS_DMASYNC_PREREAD); 655163937Simp if (mb != NULL) { 656163937Simp ifp->if_ipackets++; 657163937Simp (*ifp->if_input)(ifp, mb); 658163937Simp } 659163937Simp 660155324Simp } 661155324Simp } 662155324Simp if (status & ETH_ISR_TCOM) { 663156831Simp ATE_LOCK(sc); 664163937Simp /* XXX TSR register should be cleared */ 665156831Simp if (sc->sent_mbuf[0]) { 666163937Simp bus_dmamap_sync(sc->rxtag, sc->tx_map[0], 667163937Simp BUS_DMASYNC_POSTWRITE); 668155324Simp m_freem(sc->sent_mbuf[0]); 669163937Simp ifp->if_opackets++; 670156831Simp sc->sent_mbuf[0] = NULL; 671156831Simp } 672155324Simp if (sc->sent_mbuf[1]) { 673155324Simp if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 674163937Simp bus_dmamap_sync(sc->rxtag, sc->tx_map[1], 675163937Simp BUS_DMASYNC_POSTWRITE); 676155324Simp m_freem(sc->sent_mbuf[1]); 677163937Simp ifp->if_opackets++; 678155324Simp sc->txcur = 0; 679155324Simp sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 680155324Simp } else { 681155324Simp sc->sent_mbuf[0] = sc->sent_mbuf[1]; 682155324Simp sc->sent_mbuf[1] = NULL; 683155324Simp sc->txcur = 1; 684155324Simp } 685155324Simp } else { 686155324Simp sc->sent_mbuf[0] = NULL; 687155324Simp sc->txcur = 0; 688155324Simp } 689156831Simp /* 690156831Simp * We're no longer busy, so clear the busy flag and call the 691156831Simp * start routine to xmit more packets. 692156831Simp */ 693156831Simp sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 694156831Simp atestart_locked(sc->ifp); 695156831Simp ATE_UNLOCK(sc); 696155324Simp } 697155324Simp if (status & ETH_ISR_RBNA) { 698156831Simp printf("RBNA workaround\n"); 699155324Simp /* Workaround Errata #11 */ 700155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) &~ ETH_CTL_RE); 701155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_RE); 702155324Simp } 703155324Simp} 704155324Simp 705155324Simp/* 706155324Simp * Reset and initialize the chip 707155324Simp */ 708155324Simpstatic void 709155324Simpateinit_locked(void *xsc) 710155324Simp{ 711155324Simp struct ate_softc *sc = xsc; 712155324Simp struct ifnet *ifp = sc->ifp; 713163937Simp struct mii_data *mii; 714155324Simp 715155324Simp ATE_ASSERT_LOCKED(sc); 716155324Simp 717155324Simp /* 718155324Simp * XXX TODO(3) 719155324Simp * we need to turn on the EMAC clock in the pmc. With the 720155324Simp * default boot loader, this is already turned on. However, we 721155324Simp * need to think about how best to turn it on/off as the interface 722155324Simp * is brought up/down, as well as dealing with the mii bus... 723155324Simp * 724155324Simp * We also need to multiplex the pins correctly. 725155324Simp */ 726155324Simp 727155324Simp /* 728155324Simp * There are two different ways that the mii bus is connected 729155324Simp * to this chip. Select the right one based on a compile-time 730155324Simp * option. 731155324Simp */ 732159708Simp if (sc->use_rmii) 733159708Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_RMII); 734159708Simp else 735159708Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_RMII); 736159708Simp 737155324Simp /* 738155324Simp * Turn on the multicast hash, and write 0's to it. 739155324Simp */ 740155324Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_MTI); 741155324Simp WR4(sc, ETH_HSH, 0); 742155324Simp WR4(sc, ETH_HSL, 0); 743155324Simp 744155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 745156831Simp WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 746155324Simp 747155324Simp /* 748155324Simp * Boot loader fills in MAC address. If that's not the case, then 749155324Simp * we should set SA1L and SA1H here to the appropriate value. Note: 750155324Simp * the byte order is big endian, not little endian, so we have some 751155324Simp * swapping to do. Again, if we need it (which I don't think we do). 752155324Simp */ 753155324Simp ate_setmcast(sc); 754155324Simp 755155324Simp /* 756155324Simp * Set 'running' flag, and clear output active flag 757155324Simp * and attempt to start the output 758155324Simp */ 759155324Simp ifp->if_drv_flags |= IFF_DRV_RUNNING; 760155324Simp ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 761163937Simp 762163937Simp mii = device_get_softc(sc->miibus); 763163937Simp mii_pollstat(mii); 764163937Simp ate_stat_update(sc, mii->mii_media_active); 765155324Simp atestart_locked(ifp); 766155324Simp 767155324Simp callout_reset(&sc->tick_ch, hz, ate_tick, sc); 768155324Simp} 769155324Simp 770155324Simp/* 771155324Simp * dequeu packets and transmit 772155324Simp */ 773155324Simpstatic void 774155324Simpatestart_locked(struct ifnet *ifp) 775155324Simp{ 776155324Simp struct ate_softc *sc = ifp->if_softc; 777155324Simp struct mbuf *m, *mdefrag; 778155324Simp bus_dma_segment_t segs[1]; 779163937Simp int nseg, e; 780155324Simp 781155324Simp ATE_ASSERT_LOCKED(sc); 782155324Simp if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 783155324Simp return; 784155324Simp 785156831Simp while (sc->txcur < ATE_MAX_TX_BUFFERS) { 786156831Simp /* 787156831Simp * check to see if there's room to put another packet into the 788156831Simp * xmit queue. The EMAC chip has a ping-pong buffer for xmit 789156831Simp * packets. We use OACTIVE to indicate "we can stuff more into 790156831Simp * our buffers (clear) or not (set)." 791156831Simp */ 792156831Simp if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 793156831Simp ifp->if_drv_flags |= IFF_DRV_OACTIVE; 794156831Simp return; 795156831Simp } 796156831Simp IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 797156831Simp if (m == 0) { 798156831Simp ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 799156831Simp return; 800156831Simp } 801163937Simp e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 802163937Simp segs, &nseg, 0); 803163937Simp if (e == EFBIG) { 804163937Simp mdefrag = m_defrag(m, M_DONTWAIT); 805163937Simp if (mdefrag == NULL) { 806163937Simp IFQ_DRV_PREPEND(&ifp->if_snd, m); 807163937Simp return; 808163937Simp } 809163937Simp m = mdefrag; 810163937Simp e = bus_dmamap_load_mbuf_sg(sc->mtag, 811163937Simp sc->tx_map[sc->txcur], m, segs, &nseg, 0); 812156831Simp } 813163937Simp if (e != 0) { 814156831Simp m_freem(m); 815156831Simp continue; 816156831Simp } 817156831Simp bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 818156831Simp BUS_DMASYNC_PREWRITE); 819155324Simp 820156831Simp /* 821156831Simp * tell the hardware to xmit the packet. 822156831Simp */ 823156831Simp WR4(sc, ETH_TAR, segs[0].ds_addr); 824156831Simp WR4(sc, ETH_TCR, segs[0].ds_len); 825155324Simp 826156831Simp /* 827156831Simp * Tap off here if there is a bpf listener. 828156831Simp */ 829156831Simp BPF_MTAP(ifp, m); 830155324Simp 831156831Simp sc->sent_mbuf[sc->txcur] = m; 832156831Simp sc->txcur++; 833156831Simp } 834155324Simp} 835155324Simp 836155324Simpstatic void 837155324Simpateinit(void *xsc) 838155324Simp{ 839155324Simp struct ate_softc *sc = xsc; 840155324Simp ATE_LOCK(sc); 841155324Simp ateinit_locked(sc); 842155324Simp ATE_UNLOCK(sc); 843155324Simp} 844155324Simp 845155324Simpstatic void 846155324Simpatestart(struct ifnet *ifp) 847155324Simp{ 848155324Simp struct ate_softc *sc = ifp->if_softc; 849155324Simp ATE_LOCK(sc); 850155324Simp atestart_locked(ifp); 851155324Simp ATE_UNLOCK(sc); 852155324Simp} 853155324Simp 854155324Simp/* 855155324Simp * Turn off interrupts, and stop the nic. Can be called with sc->ifp NULL 856155324Simp * so be careful. 857155324Simp */ 858155324Simpstatic void 859155324Simpatestop(struct ate_softc *sc) 860155324Simp{ 861155324Simp struct ifnet *ifp = sc->ifp; 862155324Simp 863155324Simp if (ifp) { 864155324Simp ifp->if_timer = 0; 865155324Simp ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 866155324Simp } 867155324Simp 868155324Simp callout_stop(&sc->tick_ch); 869155324Simp 870155324Simp /* 871155324Simp * Enable some parts of the MAC that are needed always (like the 872155324Simp * MII bus. This turns off the RE and TE bits, which will remain 873155405Scognet * off until ateinit() is called to turn them on. With RE and TE 874155324Simp * turned off, there's no DMA to worry about after this write. 875155324Simp */ 876155324Simp WR4(sc, ETH_CTL, ETH_CTL_MPE); 877155324Simp 878155324Simp /* 879155324Simp * Turn off all the configured options and revert to defaults. 880155324Simp */ 881155324Simp WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 882155324Simp 883155324Simp /* 884155324Simp * Turn off all the interrupts, and ack any pending ones by reading 885155324Simp * the ISR. 886155324Simp */ 887155324Simp WR4(sc, ETH_IDR, 0xffffffff); 888155324Simp RD4(sc, ETH_ISR); 889155324Simp 890155324Simp /* 891155324Simp * Clear out the Transmit and Receiver Status registers of any 892155324Simp * errors they may be reporting 893155324Simp */ 894155324Simp WR4(sc, ETH_TSR, 0xffffffff); 895155324Simp WR4(sc, ETH_RSR, 0xffffffff); 896155324Simp 897155324Simp /* 898155324Simp * XXX TODO(8) 899155324Simp * need to worry about the busdma resources? Yes, I think we need 900155324Simp * to sync and unload them. We may also need to release the mbufs 901155324Simp * that are assocaited with RX and TX operations. 902155324Simp */ 903155324Simp 904155324Simp /* 905155324Simp * XXX we should power down the EMAC if it isn't in use, after 906155324Simp * putting it into loopback mode. This saves about 400uA according 907155324Simp * to the datasheet. 908155324Simp */ 909155324Simp} 910155324Simp 911155324Simpstatic int 912155324Simpateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 913155324Simp{ 914155324Simp struct ate_softc *sc = ifp->if_softc; 915157562Simp struct mii_data *mii; 916157562Simp struct ifreq *ifr = (struct ifreq *)data; 917155324Simp int error = 0; 918155324Simp 919155324Simp switch (cmd) { 920155324Simp case SIOCSIFFLAGS: 921155324Simp ATE_LOCK(sc); 922155324Simp if ((ifp->if_flags & IFF_UP) == 0 && 923155324Simp ifp->if_drv_flags & IFF_DRV_RUNNING) { 924155324Simp ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 925155324Simp atestop(sc); 926155324Simp } else { 927155324Simp /* reinitialize card on any parameter change */ 928155324Simp ateinit_locked(sc); 929155324Simp } 930155324Simp ATE_UNLOCK(sc); 931155324Simp break; 932155324Simp 933155324Simp case SIOCADDMULTI: 934155324Simp case SIOCDELMULTI: 935155324Simp /* update multicast filter list. */ 936157562Simp ATE_LOCK(sc); 937155324Simp ate_setmcast(sc); 938157562Simp ATE_UNLOCK(sc); 939155324Simp error = 0; 940155324Simp break; 941155324Simp 942157562Simp case SIOCSIFMEDIA: 943157562Simp case SIOCGIFMEDIA: 944157562Simp mii = device_get_softc(sc->miibus); 945157562Simp error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 946157562Simp break; 947155324Simp default: 948155324Simp error = ether_ioctl(ifp, cmd, data); 949155324Simp break; 950155324Simp } 951155324Simp return (error); 952155324Simp} 953155324Simp 954155324Simpstatic void 955155324Simpate_child_detached(device_t dev, device_t child) 956155324Simp{ 957155324Simp struct ate_softc *sc; 958155324Simp 959155324Simp sc = device_get_softc(dev); 960155324Simp if (child == sc->miibus) 961155324Simp sc->miibus = NULL; 962155324Simp} 963155324Simp 964155324Simp/* 965155324Simp * MII bus support routines. 966155324Simp */ 967155324Simpstatic int 968155324Simpate_miibus_readreg(device_t dev, int phy, int reg) 969155324Simp{ 970155324Simp struct ate_softc *sc; 971155324Simp int val; 972155324Simp 973155324Simp /* 974155324Simp * XXX if we implement agressive power savings, then we need 975155324Simp * XXX to make sure that the clock to the emac is on here 976155324Simp */ 977155324Simp 978155324Simp if (phy != 0) 979155324Simp return (0xffff); 980155324Simp sc = device_get_softc(dev); 981155324Simp DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 982155324Simp WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 983155324Simp while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 984155324Simp continue; 985155324Simp val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 986155324Simp 987155324Simp return (val); 988155324Simp} 989155324Simp 990155324Simpstatic void 991155324Simpate_miibus_writereg(device_t dev, int phy, int reg, int data) 992155324Simp{ 993155324Simp struct ate_softc *sc; 994155324Simp 995155324Simp /* 996155324Simp * XXX if we implement agressive power savings, then we need 997155324Simp * XXX to make sure that the clock to the emac is on here 998155324Simp */ 999155324Simp 1000155324Simp sc = device_get_softc(dev); 1001155324Simp WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1002155324Simp while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1003155324Simp continue; 1004155324Simp return; 1005155324Simp} 1006155324Simp 1007155324Simpstatic device_method_t ate_methods[] = { 1008155324Simp /* Device interface */ 1009155324Simp DEVMETHOD(device_probe, ate_probe), 1010155324Simp DEVMETHOD(device_attach, ate_attach), 1011155324Simp DEVMETHOD(device_detach, ate_detach), 1012155324Simp 1013155324Simp /* Bus interface */ 1014155324Simp DEVMETHOD(bus_child_detached, ate_child_detached), 1015155324Simp 1016155324Simp /* MII interface */ 1017155324Simp DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1018155324Simp DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1019155324Simp 1020155324Simp { 0, 0 } 1021155324Simp}; 1022155324Simp 1023155324Simpstatic driver_t ate_driver = { 1024155324Simp "ate", 1025155324Simp ate_methods, 1026155324Simp sizeof(struct ate_softc), 1027155324Simp}; 1028155324Simp 1029155324SimpDRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1030155324SimpDRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1031155324SimpMODULE_DEPEND(ate, miibus, 1, 1, 1); 1032155324SimpMODULE_DEPEND(ate, ether, 1, 1, 1); 1033