if_ate.c revision 163937
1155324Simp/*- 2155324Simp * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3155324Simp * 4155324Simp * Redistribution and use in source and binary forms, with or without 5155324Simp * modification, are permitted provided that the following conditions 6155324Simp * are met: 7155324Simp * 1. Redistributions of source code must retain the above copyright 8155324Simp * notice, this list of conditions and the following disclaimer. 9155324Simp * 2. Redistributions in binary form must reproduce the above copyright 10155324Simp * notice, this list of conditions and the following disclaimer in the 11155324Simp * documentation and/or other materials provided with the distribution. 12155324Simp * 13155324Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14155324Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15155324Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16155324Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17155324Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18155324Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19155324Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20155324Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21155324Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22155324Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23155324Simp */ 24155324Simp 25155324Simp/* TODO: (in no order) 26155324Simp * 27155324Simp * 8) Need to sync busdma goo in atestop 28155324Simp * 9) atestop should maybe free the mbufs? 29155324Simp * 30155324Simp * 1) detach 31155324Simp * 2) Free dma setup 32163522Simp * 3) Turn on the clock in pmc? Turn off? 33155324Simp */ 34155324Simp 35155324Simp#include <sys/cdefs.h> 36155324Simp__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 163937 2006-11-03 07:39:37Z imp $"); 37155324Simp 38155324Simp#include <sys/param.h> 39155324Simp#include <sys/systm.h> 40155324Simp#include <sys/bus.h> 41155324Simp#include <sys/kernel.h> 42155324Simp#include <sys/mbuf.h> 43155324Simp#include <sys/malloc.h> 44155324Simp#include <sys/module.h> 45155324Simp#include <sys/rman.h> 46155324Simp#include <sys/socket.h> 47155324Simp#include <sys/sockio.h> 48163522Simp#include <sys/sysctl.h> 49155324Simp#include <machine/bus.h> 50155324Simp 51155324Simp#include <net/ethernet.h> 52155324Simp#include <net/if.h> 53155324Simp#include <net/if_arp.h> 54155324Simp#include <net/if_dl.h> 55155324Simp#include <net/if_media.h> 56155324Simp#include <net/if_mib.h> 57155324Simp#include <net/if_types.h> 58155324Simp 59155324Simp#ifdef INET 60155324Simp#include <netinet/in.h> 61155324Simp#include <netinet/in_systm.h> 62155324Simp#include <netinet/in_var.h> 63155324Simp#include <netinet/ip.h> 64155324Simp#endif 65155324Simp 66155324Simp#include <net/bpf.h> 67155324Simp#include <net/bpfdesc.h> 68155324Simp 69155324Simp#include <dev/mii/mii.h> 70155324Simp#include <dev/mii/miivar.h> 71155324Simp#include <arm/at91/if_atereg.h> 72155324Simp 73155324Simp#include "miibus_if.h" 74155324Simp 75158531Scognet#define ATE_MAX_TX_BUFFERS 64 /* We have ping-pong tx buffers */ 76156831Simp#define ATE_MAX_RX_BUFFERS 64 77155324Simp 78155324Simpstruct ate_softc 79155324Simp{ 80155324Simp struct ifnet *ifp; /* ifnet pointer */ 81155324Simp struct mtx sc_mtx; /* basically a perimeter lock */ 82155324Simp device_t dev; /* Myself */ 83155324Simp device_t miibus; /* My child miibus */ 84155324Simp void *intrhand; /* Interrupt handle */ 85155324Simp struct resource *irq_res; /* IRQ resource */ 86155324Simp struct resource *mem_res; /* Memory resource */ 87155324Simp struct callout tick_ch; /* Tick callout */ 88155324Simp bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 89155324Simp bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 90157562Simp struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 91155324Simp bus_dma_tag_t rxtag; 92155324Simp bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 93157562Simp void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 94157562Simp int rx_buf_ptr; 95155324Simp bus_dma_tag_t rx_desc_tag; 96155324Simp bus_dmamap_t rx_desc_map; 97155324Simp int txcur; /* current tx map pointer */ 98155324Simp bus_addr_t rx_desc_phys; 99155324Simp eth_rx_desc_t *rx_descs; 100159708Simp int use_rmii; 101155324Simp struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 102155324Simp}; 103155324Simp 104155324Simpstatic inline uint32_t 105155324SimpRD4(struct ate_softc *sc, bus_size_t off) 106155324Simp{ 107155324Simp return bus_read_4(sc->mem_res, off); 108155324Simp} 109155324Simp 110155324Simpstatic inline void 111155324SimpWR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 112155324Simp{ 113155324Simp bus_write_4(sc->mem_res, off, val); 114155324Simp} 115155324Simp 116155324Simp#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 117155324Simp#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 118155324Simp#define ATE_LOCK_INIT(_sc) \ 119155324Simp mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 120155324Simp MTX_NETWORK_LOCK, MTX_DEF) 121155324Simp#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 122155324Simp#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 123155324Simp#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 124155324Simp 125155324Simpstatic devclass_t ate_devclass; 126155324Simp 127155324Simp/* ifnet entry points */ 128155324Simp 129155324Simpstatic void ateinit_locked(void *); 130155324Simpstatic void atestart_locked(struct ifnet *); 131155324Simp 132155324Simpstatic void ateinit(void *); 133155324Simpstatic void atestart(struct ifnet *); 134155324Simpstatic void atestop(struct ate_softc *); 135155324Simpstatic void atewatchdog(struct ifnet *); 136155324Simpstatic int ateioctl(struct ifnet * ifp, u_long, caddr_t); 137155324Simp 138155324Simp/* bus entry points */ 139155324Simp 140155324Simpstatic int ate_probe(device_t dev); 141155324Simpstatic int ate_attach(device_t dev); 142155324Simpstatic int ate_detach(device_t dev); 143155324Simpstatic void ate_intr(void *); 144155324Simp 145155324Simp/* helper routines */ 146155324Simpstatic int ate_activate(device_t dev); 147155324Simpstatic void ate_deactivate(device_t dev); 148155324Simpstatic int ate_ifmedia_upd(struct ifnet *ifp); 149155324Simpstatic void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 150155324Simpstatic void ate_get_mac(struct ate_softc *sc, u_char *eaddr); 151155445Scognetstatic void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 152155324Simp 153155324Simp/* 154155324Simp * The AT91 family of products has the ethernet called EMAC. However, 155155324Simp * it isn't self identifying. It is anticipated that the parent bus 156155324Simp * code will take care to only add ate devices where they really are. As 157155324Simp * such, we do nothing here to identify the device and just set its name. 158155324Simp */ 159155324Simpstatic int 160155324Simpate_probe(device_t dev) 161155324Simp{ 162155324Simp device_set_desc(dev, "EMAC"); 163155324Simp return (0); 164155324Simp} 165155324Simp 166155324Simpstatic int 167155324Simpate_attach(device_t dev) 168155324Simp{ 169155324Simp struct ate_softc *sc = device_get_softc(dev); 170155324Simp struct ifnet *ifp = NULL; 171163522Simp struct sysctl_ctx_list *sctx; 172163522Simp struct sysctl_oid *soid; 173155324Simp int err; 174155324Simp u_char eaddr[6]; 175155324Simp 176155324Simp sc->dev = dev; 177155324Simp err = ate_activate(dev); 178155324Simp if (err) 179155324Simp goto out; 180155324Simp 181159708Simp sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 182159708Simp 183163522Simp 184163522Simp /*Sysctls*/ 185163522Simp sctx = device_get_sysctl_ctx(dev); 186163522Simp soid = device_get_sysctl_tree(dev); 187163522Simp SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 188163522Simp CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 189163522Simp 190155324Simp /* calling atestop before ifp is set is OK */ 191155324Simp atestop(sc); 192155324Simp ATE_LOCK_INIT(sc); 193155324Simp callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 194155324Simp 195155324Simp ate_get_mac(sc, eaddr); 196155445Scognet ate_set_mac(sc, eaddr); 197155324Simp 198155405Scognet sc->ifp = ifp = if_alloc(IFT_ETHER); 199155324Simp if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 200155324Simp device_printf(dev, "Cannot find my PHY.\n"); 201155324Simp err = ENXIO; 202155324Simp goto out; 203155324Simp } 204155324Simp 205155324Simp ifp->if_softc = sc; 206155324Simp if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 207155324Simp ifp->if_mtu = ETHERMTU; 208155324Simp ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 209155324Simp ifp->if_start = atestart; 210155324Simp ifp->if_ioctl = ateioctl; 211155324Simp ifp->if_watchdog = atewatchdog; 212155324Simp ifp->if_init = ateinit; 213155324Simp ifp->if_baudrate = 10000000; 214155324Simp IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 215155324Simp ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 216155324Simp IFQ_SET_READY(&ifp->if_snd); 217155324Simp ifp->if_timer = 0; 218155324Simp ifp->if_linkmib = &sc->mibdata; 219155324Simp ifp->if_linkmiblen = sizeof(sc->mibdata); 220155324Simp sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 221155324Simp 222155324Simp ether_ifattach(ifp, eaddr); 223155324Simp 224155324Simp /* 225155324Simp * Activate the interrupt 226155324Simp */ 227155324Simp err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 228155324Simp ate_intr, sc, &sc->intrhand); 229155324Simp if (err) { 230155324Simp ether_ifdetach(ifp); 231155324Simp ATE_LOCK_DESTROY(sc); 232155324Simp } 233155324Simpout:; 234155324Simp if (err) 235155324Simp ate_deactivate(dev); 236155324Simp if (err && ifp) 237155324Simp if_free(ifp); 238155324Simp return (err); 239155324Simp} 240155324Simp 241155324Simpstatic int 242155324Simpate_detach(device_t dev) 243155324Simp{ 244155324Simp return EBUSY; /* XXX TODO(1) */ 245155324Simp} 246155324Simp 247155324Simpstatic void 248155324Simpate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 249155324Simp{ 250155324Simp struct ate_softc *sc; 251155324Simp 252155324Simp if (error != 0) 253155324Simp return; 254155324Simp sc = (struct ate_softc *)arg; 255155324Simp sc->rx_desc_phys = segs[0].ds_addr; 256155324Simp} 257155324Simp 258157562Simpstatic void 259157562Simpate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 260157562Simp{ 261157562Simp struct ate_softc *sc; 262157562Simp int i; 263157562Simp 264157562Simp if (error != 0) 265157562Simp return; 266157562Simp sc = (struct ate_softc *)arg; 267157562Simp i = sc->rx_buf_ptr; 268157562Simp 269157562Simp /* 270157562Simp * For the last buffer, set the wrap bit so the controller 271157562Simp * restarts from the first descriptor. 272157562Simp */ 273163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 274157562Simp if (i == ATE_MAX_RX_BUFFERS - 1) 275157562Simp sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 276157562Simp else 277157562Simp sc->rx_descs[i].addr = segs[0].ds_addr; 278163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 279157562Simp sc->rx_descs[i].status = 0; 280157562Simp /* Flush the memory in the mbuf */ 281157562Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 282157562Simp} 283157562Simp 284155324Simp/* 285155324Simp * Compute the multicast filter for this device using the standard 286155324Simp * algorithm. I wonder why this isn't in ether somewhere as a lot 287155324Simp * of different MAC chips use this method (or the reverse the bits) 288155324Simp * method. 289155324Simp */ 290155324Simpstatic void 291155324Simpate_setmcast(struct ate_softc *sc) 292155324Simp{ 293155324Simp uint32_t index; 294155324Simp uint32_t mcaf[2]; 295155324Simp u_char *af = (u_char *) mcaf; 296155324Simp struct ifmultiaddr *ifma; 297155324Simp 298155324Simp mcaf[0] = 0; 299155324Simp mcaf[1] = 0; 300155324Simp 301155324Simp IF_ADDR_LOCK(sc->ifp); 302155324Simp TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 303155324Simp if (ifma->ifma_addr->sa_family != AF_LINK) 304155324Simp continue; 305155324Simp index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 306155324Simp ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 307155324Simp af[index >> 3] |= 1 << (index & 7); 308155324Simp } 309155324Simp IF_ADDR_UNLOCK(sc->ifp); 310155324Simp 311155324Simp /* 312155324Simp * Write the hash to the hash register. This card can also 313155324Simp * accept unicast packets as well as multicast packets using this 314155324Simp * register for easier bridging operations, but we don't take 315155324Simp * advantage of that. Locks here are to avoid LOR with the 316155324Simp * IF_ADDR_LOCK, but might not be strictly necessary. 317155324Simp */ 318155324Simp WR4(sc, ETH_HSL, mcaf[0]); 319155324Simp WR4(sc, ETH_HSH, mcaf[1]); 320155324Simp} 321155324Simp 322155324Simpstatic int 323155324Simpate_activate(device_t dev) 324155324Simp{ 325155324Simp struct ate_softc *sc; 326155324Simp int rid, err, i; 327155324Simp 328155324Simp sc = device_get_softc(dev); 329155324Simp rid = 0; 330155324Simp sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 331155324Simp RF_ACTIVE); 332155324Simp if (sc->mem_res == NULL) 333155324Simp goto errout; 334155324Simp rid = 0; 335155324Simp sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 336155324Simp RF_ACTIVE); 337163522Simp if (sc->irq_res == NULL) 338155324Simp goto errout; 339155324Simp 340155324Simp /* 341155324Simp * Allocate DMA tags and maps 342155324Simp */ 343155324Simp err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 344155324Simp BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 345155324Simp busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 346155324Simp if (err != 0) 347155324Simp goto errout; 348155324Simp for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 349155324Simp err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 350155324Simp if (err != 0) 351155324Simp goto errout; 352155324Simp } 353155324Simp /* 354155324Simp * Allocate our Rx buffers. This chip has a rx structure that's filled 355155324Simp * in 356155324Simp */ 357155324Simp 358155324Simp /* 359155324Simp * Allocate DMA tags and maps for RX. 360155324Simp */ 361155324Simp err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 362155324Simp BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 363155324Simp busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 364155324Simp if (err != 0) 365155324Simp goto errout; 366155324Simp 367155324Simp /* Dma TAG and MAP for the rx descriptors. */ 368155324Simp err = bus_dma_tag_create(NULL, sizeof(eth_rx_desc_t), 0, 369155324Simp BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 370155324Simp ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 371155324Simp ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 372155324Simp &sc->sc_mtx, &sc->rx_desc_tag); 373155324Simp if (err != 0) 374155324Simp goto errout; 375156831Simp if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 376156831Simp BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 377155324Simp goto errout; 378157562Simp if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 379155324Simp sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 380155324Simp ate_getaddr, sc, 0) != 0) 381155324Simp goto errout; 382155324Simp /* XXX TODO(5) Put this in ateinit_locked? */ 383155324Simp for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 384157562Simp sc->rx_buf_ptr = i; 385157562Simp if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 386157562Simp BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 387155324Simp goto errout; 388157562Simp if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 389157562Simp MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 390157562Simp goto errout; 391155324Simp } 392157562Simp sc->rx_buf_ptr = 0; 393156831Simp /* Flush the memory for the EMAC rx descriptor */ 394155324Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 395155324Simp /* Write the descriptor queue address. */ 396155324Simp WR4(sc, ETH_RBQP, sc->rx_desc_phys); 397155324Simp return (0); 398155324Simperrout: 399155324Simp ate_deactivate(dev); 400155324Simp return (ENOMEM); 401155324Simp} 402155324Simp 403155324Simpstatic void 404155324Simpate_deactivate(device_t dev) 405155324Simp{ 406155324Simp struct ate_softc *sc; 407155324Simp 408155324Simp sc = device_get_softc(dev); 409155324Simp /* XXX TODO(2) teardown busdma junk, below from fxp -- customize */ 410155324Simp#if 0 411155324Simp if (sc->fxp_mtag) { 412155324Simp for (i = 0; i < FXP_NRFABUFS; i++) { 413155324Simp rxp = &sc->fxp_desc.rx_list[i]; 414155324Simp if (rxp->rx_mbuf != NULL) { 415155324Simp bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 416155324Simp BUS_DMASYNC_POSTREAD); 417155324Simp bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 418155324Simp m_freem(rxp->rx_mbuf); 419155324Simp } 420155324Simp bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 421155324Simp } 422155324Simp bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 423155324Simp for (i = 0; i < FXP_NTXCB; i++) { 424155324Simp txp = &sc->fxp_desc.tx_list[i]; 425155324Simp if (txp->tx_mbuf != NULL) { 426155324Simp bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 427155324Simp BUS_DMASYNC_POSTWRITE); 428155324Simp bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 429155324Simp m_freem(txp->tx_mbuf); 430155324Simp } 431155324Simp bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 432155324Simp } 433155324Simp bus_dma_tag_destroy(sc->fxp_mtag); 434155324Simp } 435155324Simp if (sc->fxp_stag) 436155324Simp bus_dma_tag_destroy(sc->fxp_stag); 437155324Simp if (sc->cbl_tag) 438155324Simp bus_dma_tag_destroy(sc->cbl_tag); 439155324Simp if (sc->mcs_tag) 440155324Simp bus_dma_tag_destroy(sc->mcs_tag); 441155324Simp#endif 442155324Simp if (sc->intrhand) 443155324Simp bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 444155324Simp sc->intrhand = 0; 445155324Simp bus_generic_detach(sc->dev); 446155324Simp if (sc->miibus) 447155324Simp device_delete_child(sc->dev, sc->miibus); 448155324Simp if (sc->mem_res) 449155324Simp bus_release_resource(dev, SYS_RES_IOPORT, 450155324Simp rman_get_rid(sc->mem_res), sc->mem_res); 451155324Simp sc->mem_res = 0; 452155324Simp if (sc->irq_res) 453155324Simp bus_release_resource(dev, SYS_RES_IRQ, 454155324Simp rman_get_rid(sc->irq_res), sc->irq_res); 455155324Simp sc->irq_res = 0; 456155324Simp return; 457155324Simp} 458155324Simp 459155324Simp/* 460155324Simp * Change media according to request. 461155324Simp */ 462155324Simpstatic int 463155324Simpate_ifmedia_upd(struct ifnet *ifp) 464155324Simp{ 465155324Simp struct ate_softc *sc = ifp->if_softc; 466155324Simp struct mii_data *mii; 467155324Simp 468155324Simp mii = device_get_softc(sc->miibus); 469155324Simp ATE_LOCK(sc); 470155324Simp mii_mediachg(mii); 471155324Simp ATE_UNLOCK(sc); 472155324Simp return (0); 473155324Simp} 474155324Simp 475155324Simp/* 476155324Simp * Notify the world which media we're using. 477155324Simp */ 478155324Simpstatic void 479155324Simpate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 480155324Simp{ 481155324Simp struct ate_softc *sc = ifp->if_softc; 482155324Simp struct mii_data *mii; 483155324Simp 484155324Simp mii = device_get_softc(sc->miibus); 485155324Simp ATE_LOCK(sc); 486155324Simp mii_pollstat(mii); 487155324Simp ifmr->ifm_active = mii->mii_media_active; 488155324Simp ifmr->ifm_status = mii->mii_media_status; 489155324Simp ATE_UNLOCK(sc); 490155324Simp} 491155324Simp 492155324Simpstatic void 493163937Simpate_stat_update(struct ate_softc *sc, int active) 494163937Simp{ 495163937Simp /* 496163937Simp * The speed and full/half-duplex state needs to be reflected 497163937Simp * in the ETH_CFG register. 498163937Simp */ 499163937Simp if (IFM_SUBTYPE(active) == IFM_10_T) 500163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_SPD); 501163937Simp else 502163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_SPD); 503163937Simp if (active & IFM_FDX) 504163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_FD); 505163937Simp else 506163937Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_FD); 507163937Simp} 508163937Simp 509163937Simpstatic void 510155324Simpate_tick(void *xsc) 511155324Simp{ 512155324Simp struct ate_softc *sc = xsc; 513163937Simp struct ifnet *ifp = sc->ifp; 514155324Simp struct mii_data *mii; 515155324Simp int active; 516163937Simp uint32_t c; 517155324Simp 518155324Simp /* 519155324Simp * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 520155324Simp * the MII if there's a link if this bit is clear. Not sure if we 521155324Simp * should do the same thing here or not. 522155324Simp */ 523155324Simp ATE_ASSERT_LOCKED(sc); 524155324Simp if (sc->miibus != NULL) { 525155324Simp mii = device_get_softc(sc->miibus); 526155324Simp active = mii->mii_media_active; 527155324Simp mii_tick(mii); 528155324Simp if (mii->mii_media_status & IFM_ACTIVE && 529163937Simp active != mii->mii_media_active) 530163937Simp ate_stat_update(sc, mii->mii_media_active); 531155324Simp } 532155324Simp 533155324Simp /* 534155324Simp * Update the stats as best we can. When we're done, clear 535155324Simp * the status counters and start over. We're supposed to read these 536155324Simp * registers often enough that they won't overflow. Hopefully 537155324Simp * once a second is often enough. Some don't map well to 538155324Simp * the dot3Stats mib, so for those we just count them as general 539155324Simp * errors. Stats for iframes, ibutes, oframes and obytes are 540155324Simp * collected elsewhere. These registers zero on a read to prevent 541163937Simp * races. For all the collision stats, also update the collision 542163937Simp * stats for the interface. 543155324Simp */ 544155324Simp sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 545155324Simp sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 546163937Simp c = RD4(sc, ETH_SCOL); 547163937Simp ifp->if_collisions += c; 548163937Simp sc->mibdata.dot3StatsSingleCollisionFrames += c; 549163937Simp c = RD4(sc, ETH_MCOL); 550163937Simp sc->mibdata.dot3StatsMultipleCollisionFrames += c; 551163937Simp ifp->if_collisions += c; 552155324Simp sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 553155324Simp sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 554163937Simp c = RD4(sc, ETH_LCOL); 555163937Simp sc->mibdata.dot3StatsLateCollisions += c; 556163937Simp ifp->if_collisions += c; 557163937Simp c = RD4(sc, ETH_ECOL); 558163937Simp sc->mibdata.dot3StatsExcessiveCollisions += c; 559163937Simp ifp->if_collisions += c; 560155324Simp sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 561155324Simp sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 562155324Simp sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 563155324Simp /* 564155324Simp * not sure where to lump these, so count them against the errors 565155324Simp * for the interface. 566155324Simp */ 567163937Simp sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 568155324Simp sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 569155324Simp RD4(sc, ETH_USF); 570155324Simp 571155324Simp /* 572155324Simp * Schedule another timeout one second from now. 573155324Simp */ 574155324Simp callout_reset(&sc->tick_ch, hz, ate_tick, sc); 575155324Simp} 576155324Simp 577155324Simpstatic void 578155445Scognetate_set_mac(struct ate_softc *sc, u_char *eaddr) 579155445Scognet{ 580155445Scognet WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 581155445Scognet (eaddr[1] << 8) | eaddr[0]); 582155445Scognet WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 583155445Scognet 584155445Scognet} 585155445Scognet 586155445Scognetstatic void 587155324Simpate_get_mac(struct ate_softc *sc, u_char *eaddr) 588155324Simp{ 589155324Simp uint32_t low, high; 590155324Simp 591155324Simp /* 592163937Simp * The boot loader setup the MAC with an address, if one is set in 593163937Simp * the loader. The TSC loader will also set the MAC address in a 594163937Simp * similar way. Grab the MAC address from the SA1[HL] registers. 595155324Simp */ 596155324Simp low = RD4(sc, ETH_SA1L); 597155324Simp high = RD4(sc, ETH_SA1H); 598155324Simp eaddr[0] = (high >> 8) & 0xff; 599155324Simp eaddr[1] = high & 0xff; 600155324Simp eaddr[2] = (low >> 24) & 0xff; 601155324Simp eaddr[3] = (low >> 16) & 0xff; 602155324Simp eaddr[4] = (low >> 8) & 0xff; 603155324Simp eaddr[5] = low & 0xff; 604155324Simp} 605155324Simp 606155324Simpstatic void 607155324Simpate_intr(void *xsc) 608155324Simp{ 609155324Simp struct ate_softc *sc = xsc; 610163937Simp struct ifnet *ifp = sc->ifp; 611155324Simp int status; 612155324Simp int i; 613157562Simp void *bp; 614157562Simp struct mbuf *mb; 615157562Simp uint32_t rx_stat; 616156831Simp 617155324Simp status = RD4(sc, ETH_ISR); 618155324Simp if (status == 0) 619155324Simp return; 620155324Simp if (status & ETH_ISR_RCOM) { 621155324Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 622155324Simp BUS_DMASYNC_POSTREAD); 623157562Simp while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 624157562Simp i = sc->rx_buf_ptr; 625157562Simp sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 626157562Simp bp = sc->rx_buf[i]; 627156831Simp rx_stat = sc->rx_descs[i].status; 628156831Simp if ((rx_stat & ETH_LEN_MASK) == 0) { 629156831Simp printf("ignoring bogus 0 len packet\n"); 630163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 631163937Simp BUS_DMASYNC_PREWRITE); 632157562Simp sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 633156831Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 634163937Simp BUS_DMASYNC_POSTWRITE); 635156831Simp continue; 636155324Simp } 637156831Simp /* Flush memory for mbuf so we don't get stale bytes */ 638156831Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 639156831Simp BUS_DMASYNC_POSTREAD); 640163937Simp WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 641163937Simp 642156831Simp /* 643156831Simp * The length returned by the device includes the 644156831Simp * ethernet CRC calculation for the packet, but 645156831Simp * ifnet drivers are supposed to discard it. 646156831Simp */ 647157562Simp mb = m_devget(sc->rx_buf[i], 648157562Simp (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 649163937Simp ETHER_ALIGN, ifp, NULL); 650163937Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 651163937Simp BUS_DMASYNC_PREWRITE); 652157562Simp sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 653157562Simp bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 654163937Simp BUS_DMASYNC_POSTWRITE); 655156831Simp bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 656156831Simp BUS_DMASYNC_PREREAD); 657163937Simp if (mb != NULL) { 658163937Simp ifp->if_ipackets++; 659163937Simp (*ifp->if_input)(ifp, mb); 660163937Simp } 661163937Simp 662155324Simp } 663155324Simp } 664155324Simp if (status & ETH_ISR_TCOM) { 665156831Simp ATE_LOCK(sc); 666163937Simp /* XXX TSR register should be cleared */ 667156831Simp if (sc->sent_mbuf[0]) { 668163937Simp bus_dmamap_sync(sc->rxtag, sc->tx_map[0], 669163937Simp BUS_DMASYNC_POSTWRITE); 670155324Simp m_freem(sc->sent_mbuf[0]); 671163937Simp ifp->if_opackets++; 672156831Simp sc->sent_mbuf[0] = NULL; 673156831Simp } 674155324Simp if (sc->sent_mbuf[1]) { 675155324Simp if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 676163937Simp bus_dmamap_sync(sc->rxtag, sc->tx_map[1], 677163937Simp BUS_DMASYNC_POSTWRITE); 678155324Simp m_freem(sc->sent_mbuf[1]); 679163937Simp ifp->if_opackets++; 680155324Simp sc->txcur = 0; 681155324Simp sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 682155324Simp } else { 683155324Simp sc->sent_mbuf[0] = sc->sent_mbuf[1]; 684155324Simp sc->sent_mbuf[1] = NULL; 685155324Simp sc->txcur = 1; 686155324Simp } 687155324Simp } else { 688155324Simp sc->sent_mbuf[0] = NULL; 689155324Simp sc->txcur = 0; 690155324Simp } 691156831Simp /* 692156831Simp * We're no longer busy, so clear the busy flag and call the 693156831Simp * start routine to xmit more packets. 694156831Simp */ 695156831Simp sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 696156831Simp atestart_locked(sc->ifp); 697156831Simp ATE_UNLOCK(sc); 698155324Simp } 699155324Simp if (status & ETH_ISR_RBNA) { 700156831Simp printf("RBNA workaround\n"); 701155324Simp /* Workaround Errata #11 */ 702155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) &~ ETH_CTL_RE); 703155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_RE); 704155324Simp } 705155324Simp} 706155324Simp 707155324Simp/* 708155324Simp * Reset and initialize the chip 709155324Simp */ 710155324Simpstatic void 711155324Simpateinit_locked(void *xsc) 712155324Simp{ 713155324Simp struct ate_softc *sc = xsc; 714155324Simp struct ifnet *ifp = sc->ifp; 715163937Simp struct mii_data *mii; 716155324Simp 717155324Simp ATE_ASSERT_LOCKED(sc); 718155324Simp 719155324Simp /* 720155324Simp * XXX TODO(3) 721155324Simp * we need to turn on the EMAC clock in the pmc. With the 722155324Simp * default boot loader, this is already turned on. However, we 723155324Simp * need to think about how best to turn it on/off as the interface 724155324Simp * is brought up/down, as well as dealing with the mii bus... 725155324Simp * 726155324Simp * We also need to multiplex the pins correctly. 727155324Simp */ 728155324Simp 729155324Simp /* 730155324Simp * There are two different ways that the mii bus is connected 731155324Simp * to this chip. Select the right one based on a compile-time 732155324Simp * option. 733155324Simp */ 734159708Simp if (sc->use_rmii) 735159708Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_RMII); 736159708Simp else 737159708Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_RMII); 738159708Simp 739155324Simp /* 740155324Simp * Turn on the multicast hash, and write 0's to it. 741155324Simp */ 742155324Simp WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_MTI); 743155324Simp WR4(sc, ETH_HSH, 0); 744155324Simp WR4(sc, ETH_HSL, 0); 745155324Simp 746155324Simp WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 747156831Simp WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 748155324Simp 749155324Simp /* 750155324Simp * Boot loader fills in MAC address. If that's not the case, then 751155324Simp * we should set SA1L and SA1H here to the appropriate value. Note: 752155324Simp * the byte order is big endian, not little endian, so we have some 753155324Simp * swapping to do. Again, if we need it (which I don't think we do). 754155324Simp */ 755155324Simp ate_setmcast(sc); 756155324Simp 757155324Simp /* 758155324Simp * Set 'running' flag, and clear output active flag 759155324Simp * and attempt to start the output 760155324Simp */ 761155324Simp ifp->if_drv_flags |= IFF_DRV_RUNNING; 762155324Simp ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 763163937Simp 764163937Simp mii = device_get_softc(sc->miibus); 765163937Simp mii_pollstat(mii); 766163937Simp ate_stat_update(sc, mii->mii_media_active); 767155324Simp atestart_locked(ifp); 768155324Simp 769155324Simp callout_reset(&sc->tick_ch, hz, ate_tick, sc); 770155324Simp} 771155324Simp 772155324Simp/* 773155324Simp * dequeu packets and transmit 774155324Simp */ 775155324Simpstatic void 776155324Simpatestart_locked(struct ifnet *ifp) 777155324Simp{ 778155324Simp struct ate_softc *sc = ifp->if_softc; 779155324Simp struct mbuf *m, *mdefrag; 780155324Simp bus_dma_segment_t segs[1]; 781163937Simp int nseg, e; 782155324Simp 783155324Simp ATE_ASSERT_LOCKED(sc); 784155324Simp if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 785155324Simp return; 786155324Simp 787156831Simp while (sc->txcur < ATE_MAX_TX_BUFFERS) { 788156831Simp /* 789156831Simp * check to see if there's room to put another packet into the 790156831Simp * xmit queue. The EMAC chip has a ping-pong buffer for xmit 791156831Simp * packets. We use OACTIVE to indicate "we can stuff more into 792156831Simp * our buffers (clear) or not (set)." 793156831Simp */ 794156831Simp if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 795156831Simp ifp->if_drv_flags |= IFF_DRV_OACTIVE; 796156831Simp return; 797156831Simp } 798156831Simp IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 799156831Simp if (m == 0) { 800156831Simp ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 801156831Simp return; 802156831Simp } 803163937Simp e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 804163937Simp segs, &nseg, 0); 805163937Simp if (e == EFBIG) { 806163937Simp mdefrag = m_defrag(m, M_DONTWAIT); 807163937Simp if (mdefrag == NULL) { 808163937Simp IFQ_DRV_PREPEND(&ifp->if_snd, m); 809163937Simp return; 810163937Simp } 811163937Simp m = mdefrag; 812163937Simp e = bus_dmamap_load_mbuf_sg(sc->mtag, 813163937Simp sc->tx_map[sc->txcur], m, segs, &nseg, 0); 814156831Simp } 815163937Simp if (e != 0) { 816156831Simp m_freem(m); 817156831Simp continue; 818156831Simp } 819156831Simp bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 820156831Simp BUS_DMASYNC_PREWRITE); 821155324Simp 822156831Simp /* 823156831Simp * tell the hardware to xmit the packet. 824156831Simp */ 825156831Simp WR4(sc, ETH_TAR, segs[0].ds_addr); 826156831Simp WR4(sc, ETH_TCR, segs[0].ds_len); 827155324Simp 828156831Simp /* 829156831Simp * Tap off here if there is a bpf listener. 830156831Simp */ 831156831Simp BPF_MTAP(ifp, m); 832155324Simp 833156831Simp sc->sent_mbuf[sc->txcur] = m; 834156831Simp sc->txcur++; 835156831Simp } 836155324Simp} 837155324Simp 838155324Simpstatic void 839155324Simpateinit(void *xsc) 840155324Simp{ 841155324Simp struct ate_softc *sc = xsc; 842155324Simp ATE_LOCK(sc); 843155324Simp ateinit_locked(sc); 844155324Simp ATE_UNLOCK(sc); 845155324Simp} 846155324Simp 847155324Simpstatic void 848155324Simpatestart(struct ifnet *ifp) 849155324Simp{ 850155324Simp struct ate_softc *sc = ifp->if_softc; 851155324Simp ATE_LOCK(sc); 852155324Simp atestart_locked(ifp); 853155324Simp ATE_UNLOCK(sc); 854155324Simp} 855155324Simp 856155324Simp/* 857155324Simp * Turn off interrupts, and stop the nic. Can be called with sc->ifp NULL 858155324Simp * so be careful. 859155324Simp */ 860155324Simpstatic void 861155324Simpatestop(struct ate_softc *sc) 862155324Simp{ 863155324Simp struct ifnet *ifp = sc->ifp; 864155324Simp 865155324Simp if (ifp) { 866155324Simp ifp->if_timer = 0; 867155324Simp ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 868155324Simp } 869155324Simp 870155324Simp callout_stop(&sc->tick_ch); 871155324Simp 872155324Simp /* 873155324Simp * Enable some parts of the MAC that are needed always (like the 874155324Simp * MII bus. This turns off the RE and TE bits, which will remain 875155405Scognet * off until ateinit() is called to turn them on. With RE and TE 876155324Simp * turned off, there's no DMA to worry about after this write. 877155324Simp */ 878155324Simp WR4(sc, ETH_CTL, ETH_CTL_MPE); 879155324Simp 880155324Simp /* 881155324Simp * Turn off all the configured options and revert to defaults. 882155324Simp */ 883155324Simp WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 884155324Simp 885155324Simp /* 886155324Simp * Turn off all the interrupts, and ack any pending ones by reading 887155324Simp * the ISR. 888155324Simp */ 889155324Simp WR4(sc, ETH_IDR, 0xffffffff); 890155324Simp RD4(sc, ETH_ISR); 891155324Simp 892155324Simp /* 893155324Simp * Clear out the Transmit and Receiver Status registers of any 894155324Simp * errors they may be reporting 895155324Simp */ 896155324Simp WR4(sc, ETH_TSR, 0xffffffff); 897155324Simp WR4(sc, ETH_RSR, 0xffffffff); 898155324Simp 899155324Simp /* 900155324Simp * XXX TODO(8) 901155324Simp * need to worry about the busdma resources? Yes, I think we need 902155324Simp * to sync and unload them. We may also need to release the mbufs 903155324Simp * that are assocaited with RX and TX operations. 904155324Simp */ 905155324Simp 906155324Simp /* 907155324Simp * XXX we should power down the EMAC if it isn't in use, after 908155324Simp * putting it into loopback mode. This saves about 400uA according 909155324Simp * to the datasheet. 910155324Simp */ 911155324Simp} 912155324Simp 913155324Simpstatic void 914155324Simpatewatchdog(struct ifnet *ifp) 915155324Simp{ 916155324Simp struct ate_softc *sc = ifp->if_softc; 917155324Simp 918155324Simp ATE_LOCK(sc); 919155324Simp device_printf(sc->dev, "Device timeout\n"); 920155324Simp ifp->if_oerrors++; 921155324Simp ateinit_locked(sc); 922155324Simp ATE_UNLOCK(sc); 923155324Simp} 924155324Simp 925155324Simpstatic int 926155324Simpateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 927155324Simp{ 928155324Simp struct ate_softc *sc = ifp->if_softc; 929157562Simp struct mii_data *mii; 930157562Simp struct ifreq *ifr = (struct ifreq *)data; 931155324Simp int error = 0; 932155324Simp 933155324Simp switch (cmd) { 934155324Simp case SIOCSIFFLAGS: 935155324Simp ATE_LOCK(sc); 936155324Simp if ((ifp->if_flags & IFF_UP) == 0 && 937155324Simp ifp->if_drv_flags & IFF_DRV_RUNNING) { 938155324Simp ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 939155324Simp atestop(sc); 940155324Simp } else { 941155324Simp /* reinitialize card on any parameter change */ 942155324Simp ateinit_locked(sc); 943155324Simp } 944155324Simp ATE_UNLOCK(sc); 945155324Simp break; 946155324Simp 947155324Simp case SIOCADDMULTI: 948155324Simp case SIOCDELMULTI: 949155324Simp /* update multicast filter list. */ 950157562Simp ATE_LOCK(sc); 951155324Simp ate_setmcast(sc); 952157562Simp ATE_UNLOCK(sc); 953155324Simp error = 0; 954155324Simp break; 955155324Simp 956157562Simp case SIOCSIFMEDIA: 957157562Simp case SIOCGIFMEDIA: 958157562Simp mii = device_get_softc(sc->miibus); 959157562Simp error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 960157562Simp break; 961155324Simp default: 962155324Simp error = ether_ioctl(ifp, cmd, data); 963155324Simp break; 964155324Simp } 965155324Simp return (error); 966155324Simp} 967155324Simp 968155324Simpstatic void 969155324Simpate_child_detached(device_t dev, device_t child) 970155324Simp{ 971155324Simp struct ate_softc *sc; 972155324Simp 973155324Simp sc = device_get_softc(dev); 974155324Simp if (child == sc->miibus) 975155324Simp sc->miibus = NULL; 976155324Simp} 977155324Simp 978155324Simp/* 979155324Simp * MII bus support routines. 980155324Simp */ 981155324Simpstatic int 982155324Simpate_miibus_readreg(device_t dev, int phy, int reg) 983155324Simp{ 984155324Simp struct ate_softc *sc; 985155324Simp int val; 986155324Simp 987155324Simp /* 988155324Simp * XXX if we implement agressive power savings, then we need 989155324Simp * XXX to make sure that the clock to the emac is on here 990155324Simp */ 991155324Simp 992155324Simp if (phy != 0) 993155324Simp return (0xffff); 994155324Simp sc = device_get_softc(dev); 995155324Simp DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 996155324Simp WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 997155324Simp while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 998155324Simp continue; 999155324Simp val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1000155324Simp 1001155324Simp return (val); 1002155324Simp} 1003155324Simp 1004155324Simpstatic void 1005155324Simpate_miibus_writereg(device_t dev, int phy, int reg, int data) 1006155324Simp{ 1007155324Simp struct ate_softc *sc; 1008155324Simp 1009155324Simp /* 1010155324Simp * XXX if we implement agressive power savings, then we need 1011155324Simp * XXX to make sure that the clock to the emac is on here 1012155324Simp */ 1013155324Simp 1014155324Simp sc = device_get_softc(dev); 1015155324Simp WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1016155324Simp while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1017155324Simp continue; 1018155324Simp return; 1019155324Simp} 1020155324Simp 1021155324Simpstatic device_method_t ate_methods[] = { 1022155324Simp /* Device interface */ 1023155324Simp DEVMETHOD(device_probe, ate_probe), 1024155324Simp DEVMETHOD(device_attach, ate_attach), 1025155324Simp DEVMETHOD(device_detach, ate_detach), 1026155324Simp 1027155324Simp /* Bus interface */ 1028155324Simp DEVMETHOD(bus_child_detached, ate_child_detached), 1029155324Simp 1030155324Simp /* MII interface */ 1031155324Simp DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1032155324Simp DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1033155324Simp 1034155324Simp { 0, 0 } 1035155324Simp}; 1036155324Simp 1037155324Simpstatic driver_t ate_driver = { 1038155324Simp "ate", 1039155324Simp ate_methods, 1040155324Simp sizeof(struct ate_softc), 1041155324Simp}; 1042155324Simp 1043155324SimpDRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1044155324SimpDRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1045155324SimpMODULE_DEPEND(ate, miibus, 1, 1, 1); 1046155324SimpMODULE_DEPEND(ate, ether, 1, 1, 1); 1047