at91sam9x5.c revision 266277 
1/*-
2 * Copyright (c) 2005 Olivier Houchard.  All rights reserved.
3 * Copyright (c) 2010 Greg Ansley.  All rights reserved.
4 * Copyright (c) 2012 M. Warner Losh..  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: stable/10/sys/arm/at91/at91sam9x5.c 266277 2014-05-17 00:53:12Z ian $");
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/kernel.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37
38#include <machine/bus.h>
39
40#include <arm/at91/at91var.h>
41#include <arm/at91/at91reg.h>
42#include <arm/at91/at91soc.h>
43#include <arm/at91/at91_aicreg.h>
44#include <arm/at91/at91sam9x5reg.h>
45#include <arm/at91/at91_pitreg.h>
46#include <arm/at91/at91_pmcreg.h>
47#include <arm/at91/at91_pmcvar.h>
48#include <arm/at91/at91_rstreg.h>
49
50/*
51 * Standard priority levels for the system.  0 is lowest and 7 is highest.
52 * These values are the ones Atmel uses for its Linux port
53 */
54static const int at91_irq_prio[32] =
55{
56	7,	/* Advanced Interrupt Controller (FIQ) */
57	7,	/* System Peripherals */
58	1,	/* Parallel IO Controller A and B */
59	1,	/* Parallel IO Controller C and D */
60	4,	/* Soft Modem */
61	5,	/* USART 0 */
62	5,	/* USART 1 */
63	5,	/* USART 2 */
64	5,	/* USART 3 */
65	6,	/* Two-Wire Interface 0 */
66	6,	/* Two-Wire Interface 1 */
67	6,	/* Two-Wire Interface 2 */
68	0,	/* Multimedia Card Interface 0 */
69	5,	/* Serial Peripheral Interface 0 */
70	5,	/* Serial Peripheral Interface 1 */
71	5,	/* UART 0 */
72	5,	/* UART 1 */
73	0,	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
74	0,	/* Pulse Width Modulation Controller */
75	0,	/* ADC Controller */
76	0,	/* DMA Controller 0 */
77	0,	/* DMA Controller 1 */
78	2,	/* USB Host High Speed port */
79	2,	/* USB Device High speed port */
80	3,	/* Ethernet MAC 0 */
81	3,	/* LDC Controller or Image Sensor Interface */
82	0,	/* Multimedia Card Interface 1 */
83	3,	/* Ethernet MAC 1 */
84	4,	/* Synchronous Serial Interface */
85	4,	/* CAN Controller 0 */
86	4,	/* CAN Controller 1 */
87	0,	/* Advanced Interrupt Controller (IRQ0) */
88};
89
90static const uint32_t at91_pio_base[] = {
91	AT91SAM9X25_PIOA_BASE,
92	AT91SAM9X25_PIOB_BASE,
93	AT91SAM9X25_PIOC_BASE,
94	AT91SAM9X25_PIOD_BASE,
95};
96
97#define DEVICE(_name, _id, _unit)		\
98	{					\
99		_name, _unit,			\
100		AT91SAM9X25_ ## _id ##_BASE,	\
101		AT91SAM9X25_ ## _id ## _SIZE,	\
102		AT91SAM9X25_IRQ_ ## _id		\
103	}
104
105static const struct cpu_devs at91_devs[] =
106{
107	DEVICE("at91_aic", AIC,  0),
108	DEVICE("at91_pmc", PMC,  0),
109	DEVICE("at91_wdt", WDT,  0),
110	DEVICE("at91_rst", RSTC, 0),
111	DEVICE("at91_pit", PIT,  0),
112	DEVICE("at91_pio", PIOA, 0),
113	DEVICE("at91_pio", PIOB, 1),
114	DEVICE("at91_pio", PIOC, 2),
115	DEVICE("at91_pio", PIOD, 3),
116	DEVICE("at91_twi", TWI0, 0),
117	DEVICE("at91_twi", TWI1, 1),
118	DEVICE("at91_twi", TWI2, 2),
119	DEVICE("at91_mci", HSMCI0, 0),
120	DEVICE("at91_mci", HSMCI1, 1),
121	DEVICE("uart", DBGU,   0),
122	DEVICE("uart", USART0, 1),
123	DEVICE("uart", USART1, 2),
124	DEVICE("uart", USART2, 3),
125	DEVICE("uart", USART3, 4),
126	DEVICE("spi",  SPI0,   0),
127	DEVICE("spi",  SPI1,   1),
128	DEVICE("macb", EMAC0,  0),
129	DEVICE("macb", EMAC1,  0),
130	DEVICE("nand", NAND,   0),
131	DEVICE("ohci", OHCI,   0),
132	DEVICE("ehci", EHCI,   0),
133	{ 0, 0, 0, 0, 0 }
134};
135
136static void
137at91_clock_init(void)
138{
139	struct at91_pmc_clock *clk;
140
141	/* Update USB device port clock info */
142	clk = at91_pmc_clock_ref("udpck");
143	clk->pmc_mask  = PMC_SCER_UDP_SAM9;
144	at91_pmc_clock_deref(clk);
145
146	/* Update USB host port clock info */
147	clk = at91_pmc_clock_ref("uhpck");
148	clk->pmc_mask  = PMC_SCER_UHP_SAM9;
149	at91_pmc_clock_deref(clk);
150
151	/* Each SOC has different PLL contraints */
152	clk = at91_pmc_clock_ref("plla");
153	clk->pll_min_in    = SAM9X25_PLL_A_MIN_IN_FREQ;		/*   2 MHz */
154	clk->pll_max_in    = SAM9X25_PLL_A_MAX_IN_FREQ;		/*  32 MHz */
155	clk->pll_min_out   = SAM9X25_PLL_A_MIN_OUT_FREQ;	/* 400 MHz */
156	clk->pll_max_out   = SAM9X25_PLL_A_MAX_OUT_FREQ;	/* 800 MHz */
157	clk->pll_mul_shift = SAM9X25_PLL_A_MUL_SHIFT;
158	clk->pll_mul_mask  = SAM9X25_PLL_A_MUL_MASK;
159	clk->pll_div_shift = SAM9X25_PLL_A_DIV_SHIFT;
160	clk->pll_div_mask  = SAM9X25_PLL_A_DIV_MASK;
161	clk->set_outb      = at91_pmc_800mhz_plla_outb;
162	at91_pmc_clock_deref(clk);
163
164	clk = at91_pmc_clock_ref("pllb");
165	clk->pll_min_in    = SAM9X25_PLL_B_MIN_IN_FREQ;		/*   2 MHz */
166	clk->pll_max_in    = SAM9X25_PLL_B_MAX_IN_FREQ;		/*  32 MHz */
167	clk->pll_min_out   = SAM9X25_PLL_B_MIN_OUT_FREQ;	/*  30 MHz */
168	clk->pll_max_out   = SAM9X25_PLL_B_MAX_OUT_FREQ;	/* 100 MHz */
169	clk->pll_mul_shift = SAM9X25_PLL_B_MUL_SHIFT;
170	clk->pll_mul_mask  = SAM9X25_PLL_B_MUL_MASK;
171	clk->pll_div_shift = SAM9X25_PLL_B_DIV_SHIFT;
172	clk->pll_div_mask  = SAM9X25_PLL_B_DIV_MASK;
173	clk->set_outb      = at91_pmc_800mhz_pllb_outb;
174	at91_pmc_clock_deref(clk);
175}
176
177static struct at91_soc_data soc_data = {
178	.soc_delay = at91_pit_delay,
179	.soc_reset = at91_rst_cpu_reset,
180	.soc_clock_init = at91_clock_init,
181	.soc_irq_prio = at91_irq_prio,
182	.soc_children = at91_devs,
183	.soc_pio_base = at91_pio_base,
184	.soc_pio_count = nitems(at91_pio_base),
185};
186
187AT91_SOC_SUB(AT91_T_SAM9X5, AT91_ST_SAM9X25, &soc_data);
188