at91sam9g45reg.h revision 238788
1238788Sandrew/*- 2238788Sandrew * Copyright (c) 2009 Sylvestre Gallon. All rights reserved. 3238788Sandrew * Copyright (c) 2010 Greg Ansley. All rights reserved. 4238788Sandrew * Copyright (c) 2012 Andrew Turner. All rights reserved. 5238788Sandrew * 6238788Sandrew * Redistribution and use in source and binary forms, with or without 7238788Sandrew * modification, are permitted provided that the following conditions 8238788Sandrew * are met: 9238788Sandrew * 1. Redistributions of source code must retain the above copyright 10238788Sandrew * notice, this list of conditions and the following disclaimer. 11238788Sandrew * 2. Redistributions in binary form must reproduce the above copyright 12238788Sandrew * notice, this list of conditions and the following disclaimer in the 13238788Sandrew * documentation and/or other materials provided with the distribution. 14238788Sandrew * 15238788Sandrew * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16238788Sandrew * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17238788Sandrew * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18238788Sandrew * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19238788Sandrew * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20238788Sandrew * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21238788Sandrew * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22238788Sandrew * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23238788Sandrew * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24238788Sandrew * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25238788Sandrew * SUCH DAMAGE. 26238788Sandrew */ 27238788Sandrew 28238788Sandrew/* $FreeBSD: head/sys/arm/at91/at91sam9g45reg.h 238788 2012-07-26 08:01:25Z andrew $ */ 29238788Sandrew 30238788Sandrew#ifndef AT91SAM9G45REG_H_ 31238788Sandrew#define AT91SAM9G45REG_H_ 32238788Sandrew 33238788Sandrew/* Chip Specific limits */ 34238788Sandrew#define SAM9G45_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */ 35238788Sandrew#define SAM9G45_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */ 36238788Sandrew#define SAM9G45_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */ 37238788Sandrew#define SAM9G45_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */ 38238788Sandrew#define SAM9G45_PLL_A_MUL_SHIFT 16 39238788Sandrew#define SAM9G45_PLL_A_MUL_MASK 0xFF 40238788Sandrew#define SAM9G45_PLL_A_DIV_SHIFT 0 41238788Sandrew#define SAM9G45_PLL_A_DIV_MASK 0xFF 42238788Sandrew 43238788Sandrew/* 44238788Sandrew * Memory map, from datasheet : 45238788Sandrew * 0x00000000 - 0x0ffffffff : Internal Memories 46238788Sandrew * 0x10000000 - 0x1ffffffff : Chip Select 0 47238788Sandrew * 0x20000000 - 0x2ffffffff : Chip Select 1 48238788Sandrew * 0x30000000 - 0x3ffffffff : Chip Select 2 49238788Sandrew * 0x40000000 - 0x4ffffffff : Chip Select 3 50238788Sandrew * 0x50000000 - 0x5ffffffff : Chip Select 4 51238788Sandrew * 0x60000000 - 0x6ffffffff : Chip Select 5 52238788Sandrew * 0x70000000 - 0x7ffffffff : DDR SDRC 0 53238788Sandrew * 0x80000000 - 0xeffffffff : Undefined (Abort) 54238788Sandrew * 0xf0000000 - 0xfffffffff : Peripherals 55238788Sandrew */ 56238788Sandrew 57238788Sandrew#define AT91_CHIPSELECT_0 0x10000000 58238788Sandrew#define AT91_CHIPSELECT_1 0x20000000 59238788Sandrew#define AT91_CHIPSELECT_2 0x30000000 60238788Sandrew#define AT91_CHIPSELECT_3 0x40000000 61238788Sandrew#define AT91_CHIPSELECT_4 0x50000000 62238788Sandrew#define AT91_CHIPSELECT_5 0x60000000 63238788Sandrew 64238788Sandrew 65238788Sandrew#define AT91SAM9G45_EMAC_BASE 0xffbc000 66238788Sandrew#define AT91SAM9G45_EMAC_SIZE 0x4000 67238788Sandrew 68238788Sandrew#define AT91SAM9G45_RSTC_BASE 0xffffd00 69238788Sandrew#define AT91SAM9G45_RSTC_SIZE 0x10 70238788Sandrew 71238788Sandrew/* USART*/ 72238788Sandrew 73238788Sandrew#define AT91SAM9G45_USART_SIZE 0x4000 74238788Sandrew#define AT91SAM9G45_USART0_BASE 0xff8c000 75238788Sandrew#define AT91SAM9G45_USART0_SIZE AT91SAM9G45_USART_SIZE 76238788Sandrew#define AT91SAM9G45_USART1_BASE 0xff90000 77238788Sandrew#define AT91SAM9G45_USART1_SIZE AT91SAM9G45_USART_SIZE 78238788Sandrew#define AT91SAM9G45_USART2_BASE 0xff94000 79238788Sandrew#define AT91SAM9G45_USART2_SIZE AT91SAM9G45_USART_SIZE 80238788Sandrew#define AT91SAM9G45_USART3_BASE 0xff98000 81238788Sandrew#define AT91SAM9G45_USART3_SIZE AT91SAM9G45_USART_SIZE 82238788Sandrew 83238788Sandrew/*TC*/ 84238788Sandrew#define AT91SAM9G45_TC0_BASE 0xff7c000 85238788Sandrew#define AT91SAM9G45_TC0_SIZE 0x4000 86238788Sandrew#define AT91SAM9G45_TC0C0_BASE 0xff7c000 87238788Sandrew#define AT91SAM9G45_TC0C1_BASE 0xff7c040 88238788Sandrew#define AT91SAM9G45_TC0C2_BASE 0xff7c080 89238788Sandrew 90238788Sandrew#define AT91SAM9G45_TC1_BASE 0xffd4000 91238788Sandrew#define AT91SAM9G45_TC1_SIZE 0x4000 92238788Sandrew#define AT91SAM9G45_TC1C0_BASE 0xffd4000 93238788Sandrew#define AT91SAM9G45_TC1C1_BASE 0xffd4040 94238788Sandrew#define AT91SAM9G45_TC1C2_BASE 0xffd4080 95238788Sandrew 96238788Sandrew/*SPI*/ 97238788Sandrew 98238788Sandrew#define AT91SAM9G45_SPI0_BASE 0xffa48000 99238788Sandrew#define AT91SAM9G45_SPI0_SIZE 0x4000 100238788Sandrew 101238788Sandrew#define AT91SAM9G45_SPI1_BASE 0xffa8000 102238788Sandrew#define AT91SAM9G45_SPI1_SIZE 0x4000 103238788Sandrew 104238788Sandrew/* System Registers */ 105238788Sandrew#define AT91SAM9G45_SYS_BASE 0xffff000 106238788Sandrew#define AT91SAM9G45_SYS_SIZE 0x1000 107238788Sandrew 108238788Sandrew#define AT91SAM9G45_MATRIX_BASE 0xfffea00 109238788Sandrew#define AT91SAM9G45_MATRIX_SIZE 0x200 110238788Sandrew 111238788Sandrew#define AT91SAM9G45_DBGU_BASE 0xfffee00 112238788Sandrew#define AT91SAM9G45_DBGU_SIZE 0x200 113238788Sandrew 114238788Sandrew/* 115238788Sandrew * PIO 116238788Sandrew */ 117238788Sandrew#define AT91SAM9G45_PIOA_BASE 0xffff200 118238788Sandrew#define AT91SAM9G45_PIOA_SIZE 0x200 119238788Sandrew#define AT91SAM9G45_PIOB_BASE 0xffff400 120238788Sandrew#define AT91SAM9G45_PIOB_SIZE 0x200 121238788Sandrew#define AT91SAM9G45_PIOC_BASE 0xffff600 122238788Sandrew#define AT91SAM9G45_PIOC_SIZE 0x200 123238788Sandrew#define AT91SAM9G45_PIOD_BASE 0xffff800 124238788Sandrew#define AT91SAM9G45_PIOD_SIZE 0x200 125238788Sandrew#define AT91SAM9G45_PIOE_BASE 0xffffa00 126238788Sandrew#define AT91SAM9G45_PIOE_SIZE 0x200 127238788Sandrew 128238788Sandrew#define AT91SAM9G45_PMC_BASE 0xffffc00 129238788Sandrew#define AT91SAM9G45_PMC_SIZE 0x100 130238788Sandrew 131238788Sandrew/* IRQs : */ 132238788Sandrew/* 133238788Sandrew * 0: AIC 134238788Sandrew * 1: System peripheral (System timer, RTC, DBGU) 135238788Sandrew * 2: PIO Controller A 136238788Sandrew * 3: PIO Controller B 137238788Sandrew * 4: PIO Controller C 138238788Sandrew * 5: PIO Controller D/E 139238788Sandrew * 6: TRNG 140238788Sandrew * 7: USART 0 141238788Sandrew * 8: USART 1 142238788Sandrew * 9: USART 2 143238788Sandrew * 10: USART 3 144238788Sandrew * 11: Multimedia Card interface 0 145238788Sandrew * 12: Two-wirte interface 0 146238788Sandrew * 13: Two-wirte interface 1 147238788Sandrew * 14: SPI 0 148238788Sandrew * 15: SPI 1 149238788Sandrew * 16: SSC 0 150238788Sandrew * 17: SSC 0 151238788Sandrew * 18: Timer Counter 0, 2, 3, 4, 5 152238788Sandrew * 19: PWM 153238788Sandrew * 20: Touch Screen ADC 154238788Sandrew * 21: DMA 155238788Sandrew * 22: USB Host port 156238788Sandrew * 23: LCD 157238788Sandrew * 24: AC97 158238788Sandrew * 25: EMAC 159238788Sandrew * 26: Image Sensor Interface 160238788Sandrew * 27: USB Device High Speed 161238788Sandrew * 28: - 162238788Sandrew * 29: Multimedia Card interface 1 163238788Sandrew * 30: Reserved 164238788Sandrew * 31: AIC 165238788Sandrew */ 166238788Sandrew 167238788Sandrew#define AT91SAM9G45_IRQ_SYSTEM 1 168238788Sandrew#define AT91SAM9G45_IRQ_PIOA 2 169238788Sandrew#define AT91SAM9G45_IRQ_PIOB 3 170238788Sandrew#define AT91SAM9G45_IRQ_PIOC 4 171238788Sandrew#define AT91SAM9G45_IRQ_PIOD 5 172238788Sandrew#define AT91SAM9G45_IRQ_PIOE 6 173238788Sandrew#define AT91SAM9G45_IRQ_USART0 7 174238788Sandrew#define AT91SAM9G45_IRQ_USART1 8 175238788Sandrew#define AT91SAM9G45_IRQ_USART2 9 176238788Sandrew#define AT91SAM9G45_IRQ_USART3 10 177238788Sandrew#define AT91SAM9G45_IRQ_HSMCI0 11 178238788Sandrew#define AT91SAM9G45_IRQ_TWI0 12 179238788Sandrew#define AT91SAM9G45_IRQ_TWI1 13 180238788Sandrew#define AT91SAM9G45_IRQ_SPI0 14 181238788Sandrew#define AT91SAM9G45_IRQ_SPI1 15 182238788Sandrew#define AT91SAM9G45_IRQ_SSC0 16 183238788Sandrew#define AT91SAM9G45_IRQ_SSC1 17 184238788Sandrew#define AT91SAM9G45_IRQ_TC0_TC5 18 185238788Sandrew#define AT91SAM9G45_IRQ_PWM 19 186238788Sandrew#define AT91SAM9G45_IRQ_TSADCC 20 187238788Sandrew#define AT91SAM9G45_IRQ_DMA 21 188238788Sandrew#define AT91SAM9G45_IRQ_UHP 22 189238788Sandrew#define AT91SAM9G45_IRQ_LCDC 23 190238788Sandrew#define AT91SAM9G45_IRQ_AC97C 24 191238788Sandrew#define AT91SAM9G45_IRQ_EMAC 25 192238788Sandrew#define AT91SAM9G45_IRQ_ISI 26 193238788Sandrew#define AT91SAM9G45_IRQ_UDPHS 27 194238788Sandrew/* Reserved 28 */ 195238788Sandrew#define AT91SAM9G45_IRQ_HSMCI1 29 196238788Sandrew/* Reserved 30 */ 197238788Sandrew#define AT91SAM9G45_IRQ_AICBASE 31 198238788Sandrew 199238788Sandrew/* Alias */ 200238788Sandrew#define AT91SAM9G45_IRQ_DBGU AT91SAM9G45_IRQ_SYSTEM 201238788Sandrew#define AT91SAM9G45_IRQ_PMC AT91SAM9G45_IRQ_SYSTEM 202238788Sandrew#define AT91SAM9G45_IRQ_WDT AT91SAM9G45_IRQ_SYSTEM 203238788Sandrew#define AT91SAM9G45_IRQ_PIT AT91SAM9G45_IRQ_SYSTEM 204238788Sandrew#define AT91SAM9G45_IRQ_RSTC AT91SAM9G45_IRQ_SYSTEM 205238788Sandrew#define AT91SAM9G45_IRQ_OHCI AT91SAM9G45_IRQ_UHP 206238788Sandrew#define AT91SAM9G45_IRQ_TC0 AT91SAM9G45_IRQ_TC0_TC5 207238788Sandrew#define AT91SAM9G45_IRQ_TC1 AT91SAM9G45_IRQ_TC0_TC5 208238788Sandrew#define AT91SAM9G45_IRQ_TC2 AT91SAM9G45_IRQ_TC0_TC5 209238788Sandrew#define AT91SAM9G45_IRQ_TC3 AT91SAM9G45_IRQ_TC0_TC5 210238788Sandrew#define AT91SAM9G45_IRQ_TC4 AT91SAM9G45_IRQ_TC0_TC5 211238788Sandrew#define AT91SAM9G45_IRQ_TC5 AT91SAM9G45_IRQ_TC0_TC5 212238788Sandrew#define AT91SAM9G45_IRQ_NAND (-1) 213238788Sandrew 214238788Sandrew#define AT91SAM9G45_AIC_BASE 0xffff000 215238788Sandrew#define AT91SAM9G45_AIC_SIZE 0x200 216238788Sandrew 217238788Sandrew/* Timer */ 218238788Sandrew 219238788Sandrew#define AT91SAM9G45_WDT_BASE 0xffffd40 220238788Sandrew#define AT91SAM9G45_WDT_SIZE 0x10 221238788Sandrew 222238788Sandrew#define AT91SAM9G45_PIT_BASE 0xffffd30 223238788Sandrew#define AT91SAM9G45_PIT_SIZE 0x10 224238788Sandrew 225238788Sandrew#define AT91SAM9G45_SMC_BASE 0xfffe800 226238788Sandrew#define AT91SAM9G45_SMC_SIZE 0x200 227238788Sandrew 228238788Sandrew#define AT91SAM9G45_PMC_BASE 0xffffc00 229238788Sandrew#define AT91SAM9G45_PMC_SIZE 0x100 230238788Sandrew 231238788Sandrew#define AT91SAM9G45_HSMCI0_BASE 0xff80000 232238788Sandrew#define AT91SAM9G45_HSMCI0_SIZE 0x4000 233238788Sandrew 234238788Sandrew#define AT91SAM9G45_HSMCI1_BASE 0xffd0000 235238788Sandrew#define AT91SAM9G45_HSMCI1_SIZE 0x4000 236238788Sandrew 237238788Sandrew#define AT91SAM9G45_TWI0_BASE 0xff84000 238238788Sandrew#define AT91SAM9G45_TWI0_SIZE 0x4000 239238788Sandrew#define AT91SAM9G45_TWI1_BASE 0xff88000 240238788Sandrew#define AT91SAM9G45_TWI1_SIZE 0x4000 241238788Sandrew 242238788Sandrew/* XXX Needs to be carfully coordinated with 243238788Sandrew * other * soc's so phyical and vm address 244238788Sandrew * mapping are unique. XXX 245238788Sandrew */ 246238788Sandrew#define AT91SAM9G45_OHCI_BASE 0xdfb00000 247238788Sandrew#define AT91SAM9G45_OHCI_PA_BASE 0x00700000 248238788Sandrew#define AT91SAM9G45_OHCI_SIZE 0x00100000 249238788Sandrew 250238788Sandrew#define AT91SAM9G45_NAND_BASE 0xe0000000 251238788Sandrew#define AT91SAM9G45_NAND_PA_BASE 0x40000000 252238788Sandrew#define AT91SAM9G45_NAND_SIZE 0x10000000 253238788Sandrew 254238788Sandrew 255238788Sandrew/* DDRSDRC */ 256238788Sandrew#define AT91SAM9G45_DDRSDRC1_BASE 0xfffea00 257238788Sandrew#define AT91SAM9G45_DDRSDRC0_BASE 0xfffe600 258238788Sandrew#define AT91SAM9G45_DDRSDRC_MR 0x00 259238788Sandrew#define AT91SAM9G45_DDRSDRC_TR 0x04 260238788Sandrew#define AT91SAM9G45_DDRSDRC_CR 0x08 261238788Sandrew#define AT91SAM9G45_DDRSDRC_CR_NC_8 0x0 262238788Sandrew#define AT91SAM9G45_DDRSDRC_CR_NC_9 0x1 263238788Sandrew#define AT91SAM9G45_DDRSDRC_CR_NC_10 0x2 264238788Sandrew#define AT91SAM9G45_DDRSDRC_CR_NC_11 0x3 265238788Sandrew#define AT91SAM9G45_DDRSDRC_CR_NC_MASK 0x00000003 266238788Sandrew#define AT91SAM9G45_DDRSDRC_CR_NR_11 0x0 267238788Sandrew#define AT91SAM9G45_DDRSDRC_CR_NR_12 0x4 268238788Sandrew#define AT91SAM9G45_DDRSDRC_CR_NR_13 0x8 269238788Sandrew#define AT91SAM9G45_DDRSDRC_CR_NR_14 0xc 270238788Sandrew#define AT91SAM9G45_DDRSDRC_CR_NR_MASK 0x0000000c 271238788Sandrew#define AT91SAM9G45_DDRSDRC_TPR0 0x0c 272238788Sandrew#define AT91SAM9G45_DDRSDRC_TPR1 0x10 273238788Sandrew#define AT91SAM9G45_DDRSDRC_TPR2 0x14 274238788Sandrew/* Reserved 0x18 */ 275238788Sandrew#define AT91SAM9G45_DDRSDRC_LPR 0x1c 276238788Sandrew#define AT91SAM9G45_DDRSDRC_MDR 0x20 277238788Sandrew#define AT91SAM9G45_DDRSDRC_MDR_SDR 0x0 278238788Sandrew#define AT91SAM9G45_DDRSDRC_MDR_LPSDR 0x1 279238788Sandrew#define AT91SAM9G45_DDRSDRC_MDR_LPDDR1 0x3 280238788Sandrew#define AT91SAM9G45_DDRSDRC_MDR_DDR2 0x6 281238788Sandrew#define AT91SAM9G45_DDRSDRC_MDR_MASK 0x00000007 282238788Sandrew#define AT91SAM9G45_DDRSDRC_MDR_DBW_16 0x10 283238788Sandrew#define AT91SAM9G45_DDRSDRC_DLL 0x24 284238788Sandrew#define AT91SAM9G45_DDRSDRC_HSR 0x2c 285238788Sandrew#define AT91SAM9G45_DDRSDRC_DELAY1R 0x40 286238788Sandrew#define AT91SAM9G45_DDRSDRC_DELAY2R 0x44 287238788Sandrew#define AT91SAM9G45_DDRSDRC_DELAY3R 0x48 288238788Sandrew#define AT91SAM9G45_DDRSDRC_DELAY4R 0x4c 289238788Sandrew/* Reserved 0x50 - 0xe0 */ 290238788Sandrew#define AT91SAM9G45_DDRSDRC_WPMR 0xe4 291238788Sandrew#define AT91SAM9G45_DDRSDRC_WPSR 0xe8 292238788Sandrew 293238788Sandrew#endif /* AT91SAM9G45REG_H_*/ 294238788Sandrew 295