1158432Scognet/*- 2158432Scognet * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3158432Scognet * 4158432Scognet * Redistribution and use in source and binary forms, with or without 5158432Scognet * modification, are permitted provided that the following conditions 6158432Scognet * are met: 7158432Scognet * 1. Redistributions of source code must retain the above copyright 8158432Scognet * notice, this list of conditions and the following disclaimer. 9158432Scognet * 2. Redistributions in binary form must reproduce the above copyright 10158432Scognet * notice, this list of conditions and the following disclaimer in the 11158432Scognet * documentation and/or other materials provided with the distribution. 12158432Scognet * 13185265Simp * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14185265Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15185265Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16185265Simp * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17185265Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18185265Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19185265Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20185265Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21185265Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22185265Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23185265Simp * SUCH DAMAGE. 24158432Scognet */ 25158432Scognet 26158432Scognet/* $FreeBSD$ */ 27158432Scognet 28158432Scognet#ifndef ARM_AT91_AT91_PDCREG_H 29158432Scognet#define ARM_AT91_AT91_PDCREG_H 30158432Scognet 31158432Scognet#define PDC_RPR 0x100 /* PDC Receive Pointer Register */ 32158432Scognet#define PDC_RCR 0x104 /* PDC Receive Counter Register */ 33158432Scognet#define PDC_TPR 0x108 /* PDC Transmit Pointer Register */ 34158432Scognet#define PDC_TCR 0x10c /* PDC Transmit Counter Register */ 35158432Scognet#define PDC_RNPR 0x110 /* PDC Receive Next Pointer Register */ 36158432Scognet#define PDC_RNCR 0x114 /* PDC Receive Next Counter Register */ 37158432Scognet#define PDC_TNPR 0x118 /* PDC Transmit Next Pointer Reg */ 38158432Scognet#define PDC_TNCR 0x11c /* PDC Transmit Next Counter Reg */ 39158432Scognet#define PDC_PTCR 0x120 /* PDC Transfer Control Register */ 40158432Scognet#define PDC_PTSR 0x124 /* PDC Transfer Status Register */ 41158432Scognet 42158432Scognet/* PTCR/PTSR */ 43158432Scognet#define PDC_PTCR_RXTEN (1UL << 0) /* RXTEN: Receiver Transfer Enable */ 44158432Scognet#define PDC_PTCR_RXTDIS (1UL << 1) /* RXTDIS: Receiver Transfer Disable */ 45158432Scognet#define PDC_PTCR_TXTEN (1UL << 8) /* TXTEN: Transmitter Transfer En */ 46158432Scognet#define PDC_PTCR_TXTDIS (1UL << 9) /* TXTDIS: Transmitter Transmit Dis */ 47158432Scognet 48158432Scognet#endif /* ARM_AT91_AT91_PDCREG_H */ 49