mpcore_timer.c revision 259329
1/*- 2 * Copyright (c) 2011 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Developed by Ben Gray <ben.r.gray@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company nor the name of the author may be used to 16 * endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32/** 33 * The ARM Cortex-A9 core can support a global timer plus a private and 34 * watchdog timer per core. This driver reserves memory and interrupt 35 * resources for accessing both timer register sets, these resources are 36 * stored globally and used to setup the timecount and eventtimer. 37 * 38 * The timecount timer uses the global 64-bit counter, whereas the 39 * per-CPU eventtimer uses the private 32-bit counters. 40 * 41 * 42 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2) 43 */ 44 45#include <sys/cdefs.h> 46__FBSDID("$FreeBSD: stable/10/sys/arm/arm/mpcore_timer.c 259329 2013-12-13 20:43:11Z ian $"); 47 48#include <sys/param.h> 49#include <sys/systm.h> 50#include <sys/bus.h> 51#include <sys/kernel.h> 52#include <sys/module.h> 53#include <sys/malloc.h> 54#include <sys/rman.h> 55#include <sys/timeet.h> 56#include <sys/timetc.h> 57#include <sys/watchdog.h> 58#include <machine/bus.h> 59#include <machine/cpu.h> 60#include <machine/intr.h> 61 62#include <dev/fdt/fdt_common.h> 63#include <dev/ofw/openfirm.h> 64#include <dev/ofw/ofw_bus.h> 65#include <dev/ofw/ofw_bus_subr.h> 66 67#include <machine/bus.h> 68#include <machine/fdt.h> 69 70/* Private (per-CPU) timer register map */ 71#define PRV_TIMER_LOAD 0x0000 72#define PRV_TIMER_COUNT 0x0004 73#define PRV_TIMER_CTRL 0x0008 74#define PRV_TIMER_INTR 0x000C 75 76#define PRV_TIMER_CTR_PRESCALER_SHIFT 8 77#define PRV_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 78#define PRV_TIMER_CTRL_AUTO_RELOAD (1UL << 1) 79#define PRV_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 80 81#define PRV_TIMER_INTR_EVENT (1UL << 0) 82 83/* Global timer register map */ 84#define GBL_TIMER_COUNT_LOW 0x0000 85#define GBL_TIMER_COUNT_HIGH 0x0004 86#define GBL_TIMER_CTRL 0x0008 87#define GBL_TIMER_INTR 0x000C 88 89#define GBL_TIMER_CTR_PRESCALER_SHIFT 8 90#define GBL_TIMER_CTRL_AUTO_INC (1UL << 3) 91#define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 92#define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1) 93#define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 94 95#define GBL_TIMER_INTR_EVENT (1UL << 0) 96 97struct arm_tmr_softc { 98 struct resource * tmr_res[4]; 99 bus_space_tag_t prv_bst; 100 bus_space_tag_t gbl_bst; 101 bus_space_handle_t prv_bsh; 102 bus_space_handle_t gbl_bsh; 103 uint32_t clkfreq; 104 struct eventtimer et; 105}; 106 107static struct resource_spec arm_tmr_spec[] = { 108 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Global registers */ 109 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Global timer interrupt (unused) */ 110 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* Private (per-CPU) registers */ 111 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Private timer interrupt */ 112 { -1, 0 } 113}; 114 115static struct arm_tmr_softc *arm_tmr_sc = NULL; 116 117uint32_t platform_arm_tmr_freq = 0; 118 119#define tmr_prv_read_4(reg) \ 120 bus_space_read_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg) 121#define tmr_prv_write_4(reg, val) \ 122 bus_space_write_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg, val) 123#define tmr_gbl_read_4(reg) \ 124 bus_space_read_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg) 125#define tmr_gbl_write_4(reg, val) \ 126 bus_space_write_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg, val) 127 128 129static timecounter_get_t arm_tmr_get_timecount; 130 131static struct timecounter arm_tmr_timecount = { 132 .tc_name = "ARM MPCore Timecounter", 133 .tc_get_timecount = arm_tmr_get_timecount, 134 .tc_poll_pps = NULL, 135 .tc_counter_mask = ~0u, 136 .tc_frequency = 0, 137 .tc_quality = 1000, 138}; 139 140/** 141 * arm_tmr_get_timecount - reads the timecount (global) timer 142 * @tc: pointer to arm_tmr_timecount struct 143 * 144 * We only read the lower 32-bits, the timecount stuff only uses 32-bits 145 * so (for now?) ignore the upper 32-bits. 146 * 147 * RETURNS 148 * The lower 32-bits of the counter. 149 */ 150static unsigned 151arm_tmr_get_timecount(struct timecounter *tc) 152{ 153 return (tmr_gbl_read_4(GBL_TIMER_COUNT_LOW)); 154} 155 156/** 157 * arm_tmr_start - starts the eventtimer (private) timer 158 * @et: pointer to eventtimer struct 159 * @first: the number of seconds and fractional sections to trigger in 160 * @period: the period (in seconds and fractional sections) to set 161 * 162 * If the eventtimer is required to be in oneshot mode, period will be 163 * NULL and first will point to the time to trigger. If in periodic mode 164 * period will contain the time period and first may optionally contain 165 * the time for the first period. 166 * 167 * RETURNS 168 * Always returns 0 169 */ 170static int 171arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 172{ 173 uint32_t load, count; 174 uint32_t ctrl; 175 176 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE; 177 178 if (period != 0) { 179 load = ((uint32_t)et->et_frequency * period) >> 32; 180 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD; 181 } else 182 load = 0; 183 184 if (first != 0) 185 count = ((uint32_t)et->et_frequency * first) >> 32; 186 else 187 count = load; 188 189 tmr_prv_write_4(PRV_TIMER_LOAD, load); 190 tmr_prv_write_4(PRV_TIMER_COUNT, count); 191 192 tmr_prv_write_4(PRV_TIMER_CTRL, ctrl); 193 return (0); 194} 195 196/** 197 * arm_tmr_stop - stops the eventtimer (private) timer 198 * @et: pointer to eventtimer struct 199 * 200 * Simply stops the private timer by clearing all bits in the ctrl register. 201 * 202 * RETURNS 203 * Always returns 0 204 */ 205static int 206arm_tmr_stop(struct eventtimer *et) 207{ 208 tmr_prv_write_4(PRV_TIMER_CTRL, 0); 209 return (0); 210} 211 212/** 213 * arm_tmr_intr - ISR for the eventtimer (private) timer 214 * @arg: pointer to arm_tmr_softc struct 215 * 216 * Clears the event register and then calls the eventtimer callback. 217 * 218 * RETURNS 219 * Always returns FILTER_HANDLED 220 */ 221static int 222arm_tmr_intr(void *arg) 223{ 224 struct arm_tmr_softc *sc = (struct arm_tmr_softc *)arg; 225 226 tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 227 228 if (sc->et.et_active) 229 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 230 231 return (FILTER_HANDLED); 232} 233 234 235 236 237/** 238 * arm_tmr_probe - timer probe routine 239 * @dev: new device 240 * 241 * The probe function returns success when probed with the fdt compatible 242 * string set to "arm,mpcore-timers". 243 * 244 * RETURNS 245 * BUS_PROBE_DEFAULT if the fdt device is compatible, otherwise ENXIO. 246 */ 247static int 248arm_tmr_probe(device_t dev) 249{ 250 if (!ofw_bus_is_compatible(dev, "arm,mpcore-timers")) 251 return (ENXIO); 252 253 device_set_desc(dev, "ARM Generic MPCore Timers"); 254 return (BUS_PROBE_DEFAULT); 255} 256 257/** 258 * arm_tmr_attach - attaches the timer to the simplebus 259 * @dev: new device 260 * 261 * Reserves memory and interrupt resources, stores the softc structure 262 * globally and registers both the timecount and eventtimer objects. 263 * 264 * RETURNS 265 * Zero on sucess or ENXIO if an error occuried. 266 */ 267static int 268arm_tmr_attach(device_t dev) 269{ 270 struct arm_tmr_softc *sc = device_get_softc(dev); 271 phandle_t node; 272 pcell_t clock; 273 void *ihl; 274 275 if (arm_tmr_sc) 276 return (ENXIO); 277 278 if (platform_arm_tmr_freq != 0) 279 sc->clkfreq = platform_arm_tmr_freq; 280 else { 281 /* Get the base clock frequency */ 282 node = ofw_bus_get_node(dev); 283 if ((OF_getprop(node, "clock-frequency", &clock, 284 sizeof(clock))) <= 0) { 285 device_printf(dev, "missing clock-frequency attribute in FDT\n"); 286 return (ENXIO); 287 } 288 sc->clkfreq = fdt32_to_cpu(clock); 289 } 290 291 292 if (bus_alloc_resources(dev, arm_tmr_spec, sc->tmr_res)) { 293 device_printf(dev, "could not allocate resources\n"); 294 return (ENXIO); 295 } 296 297 /* Global timer interface */ 298 sc->gbl_bst = rman_get_bustag(sc->tmr_res[0]); 299 sc->gbl_bsh = rman_get_bushandle(sc->tmr_res[0]); 300 301 /* Private per-CPU timer interface */ 302 sc->prv_bst = rman_get_bustag(sc->tmr_res[2]); 303 sc->prv_bsh = rman_get_bushandle(sc->tmr_res[2]); 304 305 arm_tmr_sc = sc; 306 307 /* Disable both timers to start off */ 308 tmr_prv_write_4(PRV_TIMER_CTRL, 0x00000000); 309 tmr_gbl_write_4(GBL_TIMER_CTRL, 0x00000000); 310 311 /* Setup and enable the global timer to use as the timecounter */ 312 tmr_gbl_write_4(GBL_TIMER_CTRL, (0x00 << GBL_TIMER_CTR_PRESCALER_SHIFT) | 313 GBL_TIMER_CTRL_TIMER_ENABLE); 314 315 arm_tmr_timecount.tc_frequency = sc->clkfreq; 316 tc_init(&arm_tmr_timecount); 317 318 /* Setup and enable the timer */ 319 if (bus_setup_intr(dev, sc->tmr_res[3], INTR_TYPE_CLK, arm_tmr_intr, 320 NULL, sc, &ihl) != 0) { 321 bus_release_resources(dev, arm_tmr_spec, sc->tmr_res); 322 device_printf(dev, "Unable to setup the clock irq handler.\n"); 323 return (ENXIO); 324 } 325 326 sc->et.et_name = "ARM MPCore Eventtimer"; 327 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 328 sc->et.et_quality = 1000; 329 330 sc->et.et_frequency = sc->clkfreq; 331 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 332 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 333 sc->et.et_start = arm_tmr_start; 334 sc->et.et_stop = arm_tmr_stop; 335 sc->et.et_priv = sc; 336 et_register(&sc->et); 337 338 return (0); 339} 340 341static device_method_t arm_tmr_methods[] = { 342 DEVMETHOD(device_probe, arm_tmr_probe), 343 DEVMETHOD(device_attach, arm_tmr_attach), 344 { 0, 0 } 345}; 346 347static driver_t arm_tmr_driver = { 348 "mp_tmr", 349 arm_tmr_methods, 350 sizeof(struct arm_tmr_softc), 351}; 352 353static devclass_t arm_tmr_devclass; 354 355DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0); 356 357/** 358 * cpu_initclocks - called by system to initialise the cpu clocks 359 * 360 * This is a boilerplat function, most of the setup has already been done 361 * when the driver was attached. Therefore this function must only be called 362 * after the driver is attached. 363 * 364 * RETURNS 365 * nothing 366 */ 367void 368cpu_initclocks(void) 369{ 370 if (PCPU_GET(cpuid) == 0) 371 cpu_initclocks_bsp(); 372 else 373 cpu_initclocks_ap(); 374} 375 376/** 377 * DELAY - Delay for at least usec microseconds. 378 * @usec: number of microseconds to delay by 379 * 380 * This function is called all over the kernel and is suppose to provide a 381 * consistent delay. This function may also be called before the console 382 * is setup so no printf's can be called here. 383 * 384 * RETURNS: 385 * nothing 386 */ 387void 388DELAY(int usec) 389{ 390 int32_t counts_per_usec; 391 int32_t counts; 392 uint32_t first, last; 393 394 /* Check the timers are setup, if not just use a for loop for the meantime */ 395 if (arm_tmr_sc == NULL) { 396 for (; usec > 0; usec--) 397 for (counts = 200; counts > 0; counts--) 398 cpufunc_nullop(); /* Prevent gcc from optimizing 399 * out the loop 400 */ 401 return; 402 } 403 404 /* Get the number of times to count */ 405 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1); 406 407 /* 408 * Clamp the timeout at a maximum value (about 32 seconds with 409 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 410 * near that length of time and if they are, they should be hung 411 * out to dry. 412 */ 413 if (usec >= (0x80000000U / counts_per_usec)) 414 counts = (0x80000000U / counts_per_usec) - 1; 415 else 416 counts = usec * counts_per_usec; 417 418 first = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW); 419 420 while (counts > 0) { 421 last = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW); 422 counts -= (int32_t)(last - first); 423 first = last; 424 } 425} 426