cpuinfo.c revision 278635 
1/*-
2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
3 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: stable/10/sys/arm/arm/cpuinfo.c 278635 2015-02-12 21:10:24Z ian $");
30
31#include <sys/param.h>
32#include <sys/systm.h>
33
34#include <machine/cpuinfo.h>
35#include <machine/cpu-v6.h>
36
37struct cpuinfo cpuinfo;
38
39/* Read and parse CPU id scheme */
40void
41cpuinfo_init(void)
42{
43
44	cpuinfo.midr = cp15_midr_get();
45	/* Test old version id schemes first */
46	if ((cpuinfo.midr & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) {
47		if (CPU_ID_ISOLD(cpuinfo.midr)) {
48			/* obsolete ARMv2 or ARMv3 CPU */
49			cpuinfo.midr = 0;
50			return;
51		}
52		if (CPU_ID_IS7(cpuinfo.midr)) {
53			if ((cpuinfo.midr & (1 << 23)) == 0) {
54				/* obsolete ARMv3 CPU */
55				cpuinfo.midr = 0;
56				return;
57			}
58			/* ARMv4T CPU */
59			cpuinfo.architecture = 1;
60			cpuinfo.revision = (cpuinfo.midr >> 16) & 0x7F;
61		}
62	} else {
63		/* must be new id scheme */
64		cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F;
65		cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F;
66	}
67	/* Parse rest of MIDR  */
68	cpuinfo.implementer = (cpuinfo.midr >> 24) & 0xFF;
69	cpuinfo.part_number = (cpuinfo.midr >> 4) & 0xFFF;
70	cpuinfo.patch = cpuinfo.midr & 0x0F;
71
72	/* CP15 c0,c0 regs 0-7 exist on all CPUs (although aliased with MIDR) */
73	cpuinfo.ctr = cp15_ctr_get();
74	cpuinfo.tcmtr = cp15_tcmtr_get();
75	cpuinfo.tlbtr = cp15_tlbtr_get();
76	cpuinfo.mpidr = cp15_mpidr_get();
77	cpuinfo.revidr = cp15_revidr_get();
78
79	/* if CPU is not v7 cpu id scheme */
80	if (cpuinfo.architecture != 0xF)
81		return;
82
83	cpuinfo.id_pfr0 = cp15_id_pfr0_get();
84	cpuinfo.id_pfr1 = cp15_id_pfr1_get();
85	cpuinfo.id_dfr0 = cp15_id_dfr0_get();
86	cpuinfo.id_afr0 = cp15_id_afr0_get();
87	cpuinfo.id_mmfr0 = cp15_id_mmfr0_get();
88	cpuinfo.id_mmfr1 = cp15_id_mmfr1_get();
89	cpuinfo.id_mmfr2 = cp15_id_mmfr2_get();
90	cpuinfo.id_mmfr3 = cp15_id_mmfr3_get();
91	cpuinfo.id_isar0 = cp15_id_isar0_get();
92	cpuinfo.id_isar1 = cp15_id_isar1_get();
93	cpuinfo.id_isar2 = cp15_id_isar2_get();
94	cpuinfo.id_isar3 = cp15_id_isar3_get();
95	cpuinfo.id_isar4 = cp15_id_isar4_get();
96	cpuinfo.id_isar5 = cp15_id_isar5_get();
97
98/* Not yet - CBAR only exist on ARM SMP Cortex A CPUs
99	cpuinfo.cbar = cp15_cbar_get();
100*/
101
102	/* Test if revidr is implemented */
103	if (cpuinfo.revidr == cpuinfo.midr)
104		cpuinfo.revidr = 0;
105
106	/* parsed bits of above registers */
107	/* id_mmfr0 */
108	cpuinfo.outermost_shareability =  (cpuinfo.id_mmfr0 >> 8) & 0xF;
109	cpuinfo.shareability_levels = (cpuinfo.id_mmfr0 >> 12) & 0xF;
110	cpuinfo.auxiliary_registers = (cpuinfo.id_mmfr0 >> 20) & 0xF;
111	cpuinfo.innermost_shareability = (cpuinfo.id_mmfr0 >> 28) & 0xF;
112	/* id_mmfr2 */
113	cpuinfo.mem_barrier = (cpuinfo.id_mmfr2 >> 20) & 0xF;
114	/* id_mmfr3 */
115	cpuinfo.coherent_walk = (cpuinfo.id_mmfr3 >> 20) & 0xF;
116	cpuinfo.maintenance_broadcast =(cpuinfo.id_mmfr3 >> 12) & 0xF;
117	/* id_pfr1 */
118	cpuinfo.generic_timer_ext = (cpuinfo.id_pfr1 >> 16) & 0xF;
119	cpuinfo.virtualization_ext = (cpuinfo.id_pfr1 >> 12) & 0xF;
120	cpuinfo.security_ext = (cpuinfo.id_pfr1 >> 4) & 0xF;
121}
122