1245450Sganbold/*- 2266337Sian * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3245450Sganbold * All rights reserved. 4245450Sganbold * 5245450Sganbold * Redistribution and use in source and binary forms, with or without 6245450Sganbold * modification, are permitted provided that the following conditions 7245450Sganbold * are met: 8245450Sganbold * 1. Redistributions of source code must retain the above copyright 9245450Sganbold * notice, this list of conditions and the following disclaimer. 10245450Sganbold * 2. Redistributions in binary form must reproduce the above copyright 11245450Sganbold * notice, this list of conditions and the following disclaimer in the 12245450Sganbold * documentation and/or other materials provided with the distribution. 13245450Sganbold * 14245450Sganbold * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15245450Sganbold * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16245450Sganbold * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17245450Sganbold * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18245450Sganbold * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19245450Sganbold * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20245450Sganbold * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21245450Sganbold * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22245450Sganbold * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23245450Sganbold * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24245450Sganbold * SUCH DAMAGE. 25245450Sganbold */ 26245450Sganbold 27245450Sganbold#include <sys/cdefs.h> 28245450Sganbold__FBSDID("$FreeBSD$"); 29245450Sganbold 30245450Sganbold#include <sys/param.h> 31245450Sganbold#include <sys/systm.h> 32245450Sganbold#include <sys/bus.h> 33245450Sganbold#include <sys/kernel.h> 34245450Sganbold#include <sys/ktr.h> 35245450Sganbold#include <sys/module.h> 36245450Sganbold#include <sys/rman.h> 37245450Sganbold#include <machine/bus.h> 38245450Sganbold#include <machine/intr.h> 39245450Sganbold 40245450Sganbold#include <dev/fdt/fdt_common.h> 41245450Sganbold#include <dev/ofw/openfirm.h> 42245450Sganbold#include <dev/ofw/ofw_bus.h> 43245450Sganbold#include <dev/ofw/ofw_bus_subr.h> 44245450Sganbold 45245450Sganbold/** 46245450Sganbold * Interrupt controller registers 47245450Sganbold * 48245450Sganbold */ 49245450Sganbold#define SW_INT_VECTOR_REG 0x00 50245450Sganbold#define SW_INT_BASE_ADR_REG 0x04 51245450Sganbold#define SW_INT_PROTECTION_REG 0x08 52245450Sganbold#define SW_INT_NMI_CTRL_REG 0x0c 53245450Sganbold 54245450Sganbold#define SW_INT_IRQ_PENDING_REG0 0x10 55245450Sganbold#define SW_INT_IRQ_PENDING_REG1 0x14 56245450Sganbold#define SW_INT_IRQ_PENDING_REG2 0x18 57245450Sganbold 58245450Sganbold#define SW_INT_FIQ_PENDING_REG0 0x20 59245450Sganbold#define SW_INT_FIQ_PENDING_REG1 0x24 60245450Sganbold#define SW_INT_FIQ_PENDING_REG2 0x28 61245450Sganbold 62245450Sganbold#define SW_INT_SELECT_REG0 0x30 63245450Sganbold#define SW_INT_SELECT_REG1 0x34 64245450Sganbold#define SW_INT_SELECT_REG2 0x38 65245450Sganbold 66245450Sganbold#define SW_INT_ENABLE_REG0 0x40 67245450Sganbold#define SW_INT_ENABLE_REG1 0x44 68245450Sganbold#define SW_INT_ENABLE_REG2 0x48 69245450Sganbold 70245450Sganbold#define SW_INT_MASK_REG0 0x50 71245450Sganbold#define SW_INT_MASK_REG1 0x54 72245450Sganbold#define SW_INT_MASK_REG2 0x58 73245450Sganbold 74245450Sganbold#define SW_INT_IRQNO_ENMI 0 75245450Sganbold 76245450Sganbold#define SW_INT_IRQ_PENDING_REG(_b) (0x10 + ((_b) * 4)) 77245450Sganbold#define SW_INT_FIQ_PENDING_REG(_b) (0x20 + ((_b) * 4)) 78245450Sganbold#define SW_INT_SELECT_REG(_b) (0x30 + ((_b) * 4)) 79245450Sganbold#define SW_INT_ENABLE_REG(_b) (0x40 + ((_b) * 4)) 80245450Sganbold#define SW_INT_MASK_REG(_b) (0x50 + ((_b) * 4)) 81245450Sganbold 82245450Sganboldstruct a10_aintc_softc { 83245450Sganbold device_t sc_dev; 84245450Sganbold struct resource * aintc_res; 85245450Sganbold bus_space_tag_t aintc_bst; 86245450Sganbold bus_space_handle_t aintc_bsh; 87245450Sganbold uint8_t ver; 88245450Sganbold}; 89245450Sganbold 90245450Sganboldstatic struct a10_aintc_softc *a10_aintc_sc = NULL; 91245450Sganbold 92245450Sganbold#define aintc_read_4(reg) \ 93245450Sganbold bus_space_read_4(a10_aintc_sc->aintc_bst, a10_aintc_sc->aintc_bsh, reg) 94245450Sganbold#define aintc_write_4(reg, val) \ 95245450Sganbold bus_space_write_4(a10_aintc_sc->aintc_bst, a10_aintc_sc->aintc_bsh, reg, val) 96245450Sganbold 97245450Sganboldstatic int 98245450Sganbolda10_aintc_probe(device_t dev) 99245450Sganbold{ 100266152Sian 101266152Sian if (!ofw_bus_status_okay(dev)) 102266152Sian return (ENXIO); 103266152Sian 104245900Sganbold if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-ic")) 105245450Sganbold return (ENXIO); 106245450Sganbold device_set_desc(dev, "A10 AINTC Interrupt Controller"); 107245450Sganbold return (BUS_PROBE_DEFAULT); 108245450Sganbold} 109245450Sganbold 110245450Sganboldstatic int 111245450Sganbolda10_aintc_attach(device_t dev) 112245450Sganbold{ 113245450Sganbold struct a10_aintc_softc *sc = device_get_softc(dev); 114245450Sganbold int rid = 0; 115245450Sganbold int i; 116245450Sganbold 117245450Sganbold sc->sc_dev = dev; 118245450Sganbold 119245450Sganbold if (a10_aintc_sc) 120245450Sganbold return (ENXIO); 121245450Sganbold 122245450Sganbold sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 123245450Sganbold if (!sc->aintc_res) { 124245450Sganbold device_printf(dev, "could not allocate resource\n"); 125245450Sganbold return (ENXIO); 126245450Sganbold } 127245450Sganbold 128245450Sganbold sc->aintc_bst = rman_get_bustag(sc->aintc_res); 129245450Sganbold sc->aintc_bsh = rman_get_bushandle(sc->aintc_res); 130245450Sganbold 131245450Sganbold a10_aintc_sc = sc; 132245450Sganbold 133245450Sganbold /* Disable & clear all interrupts */ 134245450Sganbold for (i = 0; i < 3; i++) { 135245450Sganbold aintc_write_4(SW_INT_ENABLE_REG(i), 0); 136245450Sganbold aintc_write_4(SW_INT_MASK_REG(i), 0xffffffff); 137245450Sganbold } 138245450Sganbold /* enable protection mode*/ 139245450Sganbold aintc_write_4(SW_INT_PROTECTION_REG, 0x01); 140245450Sganbold 141245450Sganbold /* config the external interrupt source type*/ 142245450Sganbold aintc_write_4(SW_INT_NMI_CTRL_REG, 0x00); 143245450Sganbold 144245450Sganbold return (0); 145245450Sganbold} 146245450Sganbold 147245450Sganboldstatic device_method_t a10_aintc_methods[] = { 148245450Sganbold DEVMETHOD(device_probe, a10_aintc_probe), 149245450Sganbold DEVMETHOD(device_attach, a10_aintc_attach), 150245450Sganbold { 0, 0 } 151245450Sganbold}; 152245450Sganbold 153245450Sganboldstatic driver_t a10_aintc_driver = { 154245450Sganbold "aintc", 155245450Sganbold a10_aintc_methods, 156245450Sganbold sizeof(struct a10_aintc_softc), 157245450Sganbold}; 158245450Sganbold 159245450Sganboldstatic devclass_t a10_aintc_devclass; 160245450Sganbold 161245450SganboldDRIVER_MODULE(aintc, simplebus, a10_aintc_driver, a10_aintc_devclass, 0, 0); 162245450Sganbold 163245450Sganboldint 164245450Sganboldarm_get_next_irq(int last_irq) 165245450Sganbold{ 166245450Sganbold uint32_t value; 167245450Sganbold int i, b; 168245450Sganbold 169245450Sganbold for (i = 0; i < 3; i++) { 170245450Sganbold value = aintc_read_4(SW_INT_IRQ_PENDING_REG(i)); 171245450Sganbold for (b = 0; b < 32; b++) 172245450Sganbold if (value & (1 << b)) { 173245450Sganbold return (i * 32 + b); 174245450Sganbold } 175245450Sganbold } 176245450Sganbold 177245450Sganbold return (-1); 178245450Sganbold} 179245450Sganbold 180245450Sganboldvoid 181245450Sganboldarm_mask_irq(uintptr_t nb) 182245450Sganbold{ 183245450Sganbold uint32_t bit, block, value; 184245450Sganbold 185245450Sganbold bit = (nb % 32); 186245450Sganbold block = (nb / 32); 187245450Sganbold 188245450Sganbold value = aintc_read_4(SW_INT_ENABLE_REG(block)); 189245450Sganbold value &= ~(1 << bit); 190245450Sganbold aintc_write_4(SW_INT_ENABLE_REG(block), value); 191245450Sganbold 192245450Sganbold value = aintc_read_4(SW_INT_MASK_REG(block)); 193245450Sganbold value |= (1 << bit); 194245450Sganbold aintc_write_4(SW_INT_MASK_REG(block), value); 195245450Sganbold} 196245450Sganbold 197245450Sganboldvoid 198245450Sganboldarm_unmask_irq(uintptr_t nb) 199245450Sganbold{ 200245450Sganbold uint32_t bit, block, value; 201245450Sganbold 202245450Sganbold bit = (nb % 32); 203245450Sganbold block = (nb / 32); 204245450Sganbold 205245450Sganbold value = aintc_read_4(SW_INT_ENABLE_REG(block)); 206245450Sganbold value |= (1 << bit); 207245450Sganbold aintc_write_4(SW_INT_ENABLE_REG(block), value); 208245450Sganbold 209245450Sganbold value = aintc_read_4(SW_INT_MASK_REG(block)); 210245450Sganbold value &= ~(1 << bit); 211245450Sganbold aintc_write_4(SW_INT_MASK_REG(block), value); 212245450Sganbold 213245450Sganbold if(nb == SW_INT_IRQNO_ENMI) /* must clear pending bit when enabled */ 214245450Sganbold aintc_write_4(SW_INT_IRQ_PENDING_REG(0), (1 << SW_INT_IRQNO_ENMI)); 215245450Sganbold} 216