vmm_lapic.c revision 284899
1258945Sroberto/*- 2258945Sroberto * Copyright (c) 2011 NetApp, Inc. 3258945Sroberto * All rights reserved. 4258945Sroberto * 5258945Sroberto * Redistribution and use in source and binary forms, with or without 6258945Sroberto * modification, are permitted provided that the following conditions 7258945Sroberto * are met: 8258945Sroberto * 1. Redistributions of source code must retain the above copyright 9258945Sroberto * notice, this list of conditions and the following disclaimer. 10258945Sroberto * 2. Redistributions in binary form must reproduce the above copyright 11258945Sroberto * notice, this list of conditions and the following disclaimer in the 12258945Sroberto * documentation and/or other materials provided with the distribution. 13258945Sroberto * 14258945Sroberto * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15258945Sroberto * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16258945Sroberto * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17258945Sroberto * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18258945Sroberto * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19258945Sroberto * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20258945Sroberto * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21258945Sroberto * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22258945Sroberto * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23258945Sroberto * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24258945Sroberto * SUCH DAMAGE. 25258945Sroberto * 26258945Sroberto * $FreeBSD: stable/10/sys/amd64/vmm/vmm_lapic.c 284899 2015-06-28 01:21:55Z neel $ 27258945Sroberto */ 28258945Sroberto 29258945Sroberto#include <sys/cdefs.h> 30258945Sroberto__FBSDID("$FreeBSD: stable/10/sys/amd64/vmm/vmm_lapic.c 284899 2015-06-28 01:21:55Z neel $"); 31258945Sroberto 32258945Sroberto#include <sys/param.h> 33258945Sroberto#include <sys/systm.h> 34258945Sroberto#include <sys/smp.h> 35258945Sroberto 36258945Sroberto#include <x86/specialreg.h> 37258945Sroberto#include <x86/apicreg.h> 38258945Sroberto 39258945Sroberto#include <machine/vmm.h> 40258945Sroberto#include "vmm_ipi.h" 41258945Sroberto#include "vmm_ktr.h" 42258945Sroberto#include "vmm_lapic.h" 43258945Sroberto#include "vlapic.h" 44258945Sroberto 45258945Sroberto/* 46258945Sroberto * Some MSI message definitions 47258945Sroberto */ 48258945Sroberto#define MSI_X86_ADDR_MASK 0xfff00000 49258945Sroberto#define MSI_X86_ADDR_BASE 0xfee00000 50258945Sroberto#define MSI_X86_ADDR_RH 0x00000008 /* Redirection Hint */ 51258945Sroberto#define MSI_X86_ADDR_LOG 0x00000004 /* Destination Mode */ 52258945Sroberto 53258945Srobertoint 54258945Srobertolapic_set_intr(struct vm *vm, int cpu, int vector, bool level) 55258945Sroberto{ 56258945Sroberto struct vlapic *vlapic; 57258945Sroberto 58258945Sroberto if (cpu < 0 || cpu >= VM_MAXCPU) 59258945Sroberto return (EINVAL); 60258945Sroberto 61258945Sroberto /* 62258945Sroberto * According to section "Maskable Hardware Interrupts" in Intel SDM 63258945Sroberto * vectors 16 through 255 can be delivered through the local APIC. 64258945Sroberto */ 65258945Sroberto if (vector < 16 || vector > 255) 66258945Sroberto return (EINVAL); 67258945Sroberto 68258945Sroberto vlapic = vm_lapic(vm, cpu); 69258945Sroberto if (vlapic_set_intr_ready(vlapic, vector, level)) 70258945Sroberto vcpu_notify_event(vm, cpu, true); 71258945Sroberto return (0); 72258945Sroberto} 73258945Sroberto 74258945Srobertoint 75258945Srobertolapic_set_local_intr(struct vm *vm, int cpu, int vector) 76258945Sroberto{ 77258945Sroberto struct vlapic *vlapic; 78258945Sroberto cpuset_t dmask; 79258945Sroberto int error; 80258945Sroberto 81258945Sroberto if (cpu < -1 || cpu >= VM_MAXCPU) 82258945Sroberto return (EINVAL); 83258945Sroberto 84258945Sroberto if (cpu == -1) 85258945Sroberto dmask = vm_active_cpus(vm); 86258945Sroberto else 87258945Sroberto CPU_SETOF(cpu, &dmask); 88258945Sroberto error = 0; 89258945Sroberto while ((cpu = CPU_FFS(&dmask)) != 0) { 90258945Sroberto cpu--; 91258945Sroberto CPU_CLR(cpu, &dmask); 92258945Sroberto vlapic = vm_lapic(vm, cpu); 93258945Sroberto error = vlapic_trigger_lvt(vlapic, vector); 94258945Sroberto if (error) 95 break; 96 } 97 98 return (error); 99} 100 101int 102lapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg) 103{ 104 int delmode, vec; 105 uint32_t dest; 106 bool phys; 107 108 VM_CTR2(vm, "lapic MSI addr: %#lx msg: %#lx", addr, msg); 109 110 if ((addr & MSI_X86_ADDR_MASK) != MSI_X86_ADDR_BASE) { 111 VM_CTR1(vm, "lapic MSI invalid addr %#lx", addr); 112 return (-1); 113 } 114 115 /* 116 * Extract the x86-specific fields from the MSI addr/msg 117 * params according to the Intel Arch spec, Vol3 Ch 10. 118 * 119 * The PCI specification does not support level triggered 120 * MSI/MSI-X so ignore trigger level in 'msg'. 121 * 122 * The 'dest' is interpreted as a logical APIC ID if both 123 * the Redirection Hint and Destination Mode are '1' and 124 * physical otherwise. 125 */ 126 dest = (addr >> 12) & 0xff; 127 phys = ((addr & (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)) != 128 (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)); 129 delmode = msg & APIC_DELMODE_MASK; 130 vec = msg & 0xff; 131 132 VM_CTR3(vm, "lapic MSI %s dest %#x, vec %d", 133 phys ? "physical" : "logical", dest, vec); 134 135 vlapic_deliver_intr(vm, LAPIC_TRIG_EDGE, dest, phys, delmode, vec); 136 return (0); 137} 138 139static boolean_t 140x2apic_msr(u_int msr) 141{ 142 if (msr >= 0x800 && msr <= 0xBFF) 143 return (TRUE); 144 else 145 return (FALSE); 146} 147 148static u_int 149x2apic_msr_to_regoff(u_int msr) 150{ 151 152 return ((msr - 0x800) << 4); 153} 154 155boolean_t 156lapic_msr(u_int msr) 157{ 158 159 if (x2apic_msr(msr) || (msr == MSR_APICBASE)) 160 return (TRUE); 161 else 162 return (FALSE); 163} 164 165int 166lapic_rdmsr(struct vm *vm, int cpu, u_int msr, uint64_t *rval, bool *retu) 167{ 168 int error; 169 u_int offset; 170 struct vlapic *vlapic; 171 172 vlapic = vm_lapic(vm, cpu); 173 174 if (msr == MSR_APICBASE) { 175 *rval = vlapic_get_apicbase(vlapic); 176 error = 0; 177 } else { 178 offset = x2apic_msr_to_regoff(msr); 179 error = vlapic_read(vlapic, 0, offset, rval, retu); 180 } 181 182 return (error); 183} 184 185int 186lapic_wrmsr(struct vm *vm, int cpu, u_int msr, uint64_t val, bool *retu) 187{ 188 int error; 189 u_int offset; 190 struct vlapic *vlapic; 191 192 vlapic = vm_lapic(vm, cpu); 193 194 if (msr == MSR_APICBASE) { 195 error = vlapic_set_apicbase(vlapic, val); 196 } else { 197 offset = x2apic_msr_to_regoff(msr); 198 error = vlapic_write(vlapic, 0, offset, val, retu); 199 } 200 201 return (error); 202} 203 204int 205lapic_mmio_write(void *vm, int cpu, uint64_t gpa, uint64_t wval, int size, 206 void *arg) 207{ 208 int error; 209 uint64_t off; 210 struct vlapic *vlapic; 211 212 off = gpa - DEFAULT_APIC_BASE; 213 214 /* 215 * Memory mapped local apic accesses must be 4 bytes wide and 216 * aligned on a 16-byte boundary. 217 */ 218 if (size != 4 || off & 0xf) 219 return (EINVAL); 220 221 vlapic = vm_lapic(vm, cpu); 222 error = vlapic_write(vlapic, 1, off, wval, arg); 223 return (error); 224} 225 226int 227lapic_mmio_read(void *vm, int cpu, uint64_t gpa, uint64_t *rval, int size, 228 void *arg) 229{ 230 int error; 231 uint64_t off; 232 struct vlapic *vlapic; 233 234 off = gpa - DEFAULT_APIC_BASE; 235 236 /* 237 * Memory mapped local apic accesses should be aligned on a 238 * 16-byte boundary. They are also suggested to be 4 bytes 239 * wide, alas not all OSes follow suggestions. 240 */ 241 off &= ~3; 242 if (off & 0xf) 243 return (EINVAL); 244 245 vlapic = vm_lapic(vm, cpu); 246 error = vlapic_read(vlapic, 1, off, rval, arg); 247 return (error); 248} 249