intr_machdep.h revision 234989
1198892Srdivacky/*- 2198892Srdivacky * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3198892Srdivacky * All rights reserved. 4198892Srdivacky * 5198892Srdivacky * Redistribution and use in source and binary forms, with or without 6198892Srdivacky * modification, are permitted provided that the following conditions 7198892Srdivacky * are met: 8198892Srdivacky * 1. Redistributions of source code must retain the above copyright 9198892Srdivacky * notice, this list of conditions and the following disclaimer. 10198892Srdivacky * 2. Redistributions in binary form must reproduce the above copyright 11198892Srdivacky * notice, this list of conditions and the following disclaimer in the 12198892Srdivacky * documentation and/or other materials provided with the distribution. 13198892Srdivacky * 14198892Srdivacky * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15198892Srdivacky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16199481Srdivacky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17202878Srdivacky * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18198892Srdivacky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19198892Srdivacky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20198892Srdivacky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21198892Srdivacky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22199481Srdivacky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23199481Srdivacky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24199481Srdivacky * SUCH DAMAGE. 25199481Srdivacky * 26199481Srdivacky * $FreeBSD: head/sys/amd64/include/intr_machdep.h 234989 2012-05-03 21:44:01Z attilio $ 27199481Srdivacky */ 28199481Srdivacky 29199481Srdivacky#ifndef __MACHINE_INTR_MACHDEP_H__ 30199481Srdivacky#define __MACHINE_INTR_MACHDEP_H__ 31199481Srdivacky 32199481Srdivacky#ifdef _KERNEL 33199481Srdivacky 34199481Srdivacky/* 35199481Srdivacky * The maximum number of I/O interrupts we allow. This number is rather 36199481Srdivacky * arbitrary as it is just the maximum IRQ resource value. The interrupt 37199481Srdivacky * source for a given IRQ maps that I/O interrupt to device interrupt 38199481Srdivacky * source whether it be a pin on an interrupt controller or an MSI interrupt. 39199481Srdivacky * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device 40199481Srdivacky * interrupts allocate IDT vectors on demand. Currently we have 191 IDT 41199481Srdivacky * vectors available for device interrupts. On many systems with I/O APICs, 42198892Srdivacky * a lot of the IRQs are not used, so this number can be much larger than 43198892Srdivacky * 191 and still be safe since only interrupt sources in actual use will 44198892Srdivacky * allocate IDT vectors. 45199481Srdivacky * 46199481Srdivacky * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs. 47199481Srdivacky * IRQ values beyond 256 are used by MSI. We leave 255 unused to avoid 48199481Srdivacky * confusion since 255 is used in PCI to indicate an invalid IRQ. 49199481Srdivacky */ 50199481Srdivacky#define NUM_MSI_INTS 512 51199481Srdivacky#define FIRST_MSI_INT 256 52199481Srdivacky#define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS) 53199481Srdivacky 54198892Srdivacky/* 55198892Srdivacky * Default base address for MSI messages on x86 platforms. 56198892Srdivacky */ 57198892Srdivacky#define MSI_INTEL_ADDR_BASE 0xfee00000 58198892Srdivacky 59198892Srdivacky/* 60198892Srdivacky * - 1 ??? dummy counter. 61198892Srdivacky * - 2 counters for each I/O interrupt. 62198892Srdivacky * - 1 counter for each CPU for lapic timer. 63198892Srdivacky * - 8 counters for each CPU for IPI counters for SMP. 64198892Srdivacky */ 65198892Srdivacky#ifdef SMP 66198892Srdivacky#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 8) * MAXCPU) 67198892Srdivacky#else 68198892Srdivacky#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1) 69198892Srdivacky#endif 70198892Srdivacky 71198892Srdivacky#ifndef LOCORE 72198892Srdivacky 73198892Srdivackytypedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss); 74198892Srdivacky 75198892Srdivacky#define IDTVEC(name) __CONCAT(X,name) 76198892Srdivacky 77198892Srdivackystruct intsrc; 78198892Srdivacky 79198892Srdivacky/* 80198892Srdivacky * Methods that a PIC provides to mask/unmask a given interrupt source, 81198892Srdivacky * "turn on" the interrupt on the CPU side by setting up an IDT entry, and 82198892Srdivacky * return the vector associated with this source. 83198892Srdivacky */ 84198892Srdivackystruct pic { 85198892Srdivacky void (*pic_enable_source)(struct intsrc *); 86198892Srdivacky void (*pic_disable_source)(struct intsrc *, int); 87198892Srdivacky void (*pic_eoi_source)(struct intsrc *); 88198892Srdivacky void (*pic_enable_intr)(struct intsrc *); 89198892Srdivacky void (*pic_disable_intr)(struct intsrc *); 90198892Srdivacky int (*pic_vector)(struct intsrc *); 91198892Srdivacky int (*pic_source_pending)(struct intsrc *); 92198892Srdivacky void (*pic_suspend)(struct pic *); 93198892Srdivacky void (*pic_resume)(struct pic *); 94198892Srdivacky int (*pic_config_intr)(struct intsrc *, enum intr_trigger, 95198892Srdivacky enum intr_polarity); 96201360Srdivacky int (*pic_assign_cpu)(struct intsrc *, u_int apic_id); 97201360Srdivacky STAILQ_ENTRY(pic) pics; 98203954Srdivacky}; 99198892Srdivacky 100198892Srdivacky/* Flags for pic_disable_source() */ 101198892Srdivackyenum { 102198892Srdivacky PIC_EOI, 103198892Srdivacky PIC_NO_EOI, 104198892Srdivacky}; 105198892Srdivacky 106199481Srdivacky/* 107198892Srdivacky * An interrupt source. The upper-layer code uses the PIC methods to 108198892Srdivacky * control a given source. The lower-layer PIC drivers can store additional 109198892Srdivacky * private data in a given interrupt source such as an interrupt pin number 110203954Srdivacky * or an I/O APIC pointer. 111203954Srdivacky */ 112202878Srdivackystruct intsrc { 113198892Srdivacky struct pic *is_pic; 114198892Srdivacky struct intr_event *is_event; 115198892Srdivacky u_long *is_count; 116198892Srdivacky u_long *is_straycount; 117198892Srdivacky u_int is_index; 118199481Srdivacky u_int is_handlers; 119198892Srdivacky}; 120198892Srdivacky 121198892Srdivackystruct trapframe; 122198892Srdivacky 123198892Srdivacky/* 124198892Srdivacky * The following data structure holds per-cpu data, and is placed just 125198892Srdivacky * above the top of the space used for the NMI stack. 126198892Srdivacky */ 127198892Srdivackystruct nmi_pcpu { 128198892Srdivacky register_t np_pcpu; 129198892Srdivacky register_t __padding; /* pad to 16 bytes */ 130198892Srdivacky}; 131198892Srdivacky 132198892Srdivackyextern struct mtx icu_lock; 133198892Srdivackyextern int elcr_found; 134199481Srdivacky 135198892Srdivacky#ifndef DEV_ATPIC 136198892Srdivackyvoid atpic_reset(void); 137198892Srdivacky#endif 138198892Srdivacky/* XXX: The elcr_* prototypes probably belong somewhere else. */ 139198892Srdivackyint elcr_probe(void); 140198892Srdivackyenum intr_trigger elcr_read_trigger(u_int irq); 141199481Srdivackyvoid elcr_resume(void); 142198892Srdivackyvoid elcr_write_trigger(u_int irq, enum intr_trigger trigger); 143198892Srdivackyvoid intr_add_cpu(u_int cpu); 144201360Srdivackyint intr_add_handler(const char *name, int vector, driver_filter_t filter, 145201360Srdivacky driver_intr_t handler, void *arg, enum intr_type flags, 146201360Srdivacky void **cookiep); 147201360Srdivacky#ifdef SMP 148198892Srdivackyint intr_bind(u_int vector, u_char cpu); 149198892Srdivacky#endif 150198892Srdivackyint intr_config_intr(int vector, enum intr_trigger trig, 151198892Srdivacky enum intr_polarity pol); 152198892Srdivackyint intr_describe(u_int vector, void *ih, const char *descr); 153198892Srdivackyvoid intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame); 154198892Srdivackyu_int intr_next_cpu(void); 155198892Srdivackystruct intsrc *intr_lookup_source(int vector); 156198892Srdivackyint intr_register_pic(struct pic *pic); 157198892Srdivackyint intr_register_source(struct intsrc *isrc); 158198892Srdivackyint intr_remove_handler(void *cookie); 159198892Srdivackyvoid intr_resume(void); 160198892Srdivackyvoid intr_suspend(void); 161198892Srdivackyvoid intrcnt_add(const char *name, u_long **countp); 162198892Srdivackyvoid nexus_add_irq(u_long irq); 163199481Srdivackyint msi_alloc(device_t dev, int count, int maxcount, int *irqs); 164198892Srdivackyvoid msi_init(void); 165199481Srdivackyint msi_map(int irq, uint64_t *addr, uint32_t *data); 166199481Srdivackyint msi_release(int *irqs, int count); 167199481Srdivackyint msix_alloc(device_t dev, int *irq); 168199481Srdivackyint msix_release(int irq); 169199481Srdivacky 170199481Srdivacky#endif /* !LOCORE */ 171198892Srdivacky#endif /* _KERNEL */ 172199481Srdivacky#endif /* !__MACHINE_INTR_MACHDEP_H__ */ 173199481Srdivacky