intr_machdep.h revision 166901 
1/*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/amd64/include/intr_machdep.h 166901 2007-02-23 12:19:07Z piso $
27 */
28
29#ifndef __MACHINE_INTR_MACHDEP_H__
30#define	__MACHINE_INTR_MACHDEP_H__
31
32#ifdef _KERNEL
33
34/*
35 * The maximum number of I/O interrupts we allow.  This number is rather
36 * arbitrary as it is just the maximum IRQ resource value.  The interrupt
37 * source for a given IRQ maps that I/O interrupt to device interrupt
38 * source whether it be a pin on an interrupt controller or an MSI interrupt.
39 * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device
40 * interrupts allocate IDT vectors on demand.  Currently we have 191 IDT
41 * vectors available for device interrupts.  On many systems with I/O APICs,
42 * a lot of the IRQs are not used, so this number can be much larger than
43 * 191 and still be safe since only interrupt sources in actual use will
44 * allocate IDT vectors.
45 *
46 * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs.
47 * IRQ values beyond 256 are used by MSI.  We leave 255 unused to avoid
48 * confusion since 255 is used in PCI to indicate an invalid IRQ.
49 */
50#define	NUM_MSI_INTS	128
51#define	FIRST_MSI_INT	256
52#define	NUM_IO_INTS	(FIRST_MSI_INT + NUM_MSI_INTS)
53
54/*
55 * Default base address for MSI messages on x86 platforms.
56 */
57#define	MSI_INTEL_ADDR_BASE		0xfee00000
58
59/*
60 * - 1 ??? dummy counter.
61 * - 2 counters for each I/O interrupt.
62 * - 1 counter for each CPU for lapic timer.
63 * - 7 counters for each CPU for IPI counters for SMP.
64 */
65#ifdef SMP
66#define	INTRCNT_COUNT	(1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU)
67#else
68#define	INTRCNT_COUNT	(1 + NUM_IO_INTS * 2 + 1)
69#endif
70
71#ifndef LOCORE
72
73typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
74
75#define	IDTVEC(name)	__CONCAT(X,name)
76
77struct intsrc;
78
79/*
80 * Methods that a PIC provides to mask/unmask a given interrupt source,
81 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and
82 * return the vector associated with this source.
83 */
84struct pic {
85	void (*pic_enable_source)(struct intsrc *);
86	void (*pic_disable_source)(struct intsrc *, int);
87	void (*pic_eoi_source)(struct intsrc *);
88	void (*pic_enable_intr)(struct intsrc *);
89	int (*pic_vector)(struct intsrc *);
90	int (*pic_source_pending)(struct intsrc *);
91	void (*pic_suspend)(struct pic *);
92	void (*pic_resume)(struct pic *);
93	int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
94	    enum intr_polarity);
95	void (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
96	STAILQ_ENTRY(pic) pics;
97};
98
99/* Flags for pic_disable_source() */
100enum {
101	PIC_EOI,
102	PIC_NO_EOI,
103};
104
105/*
106 * An interrupt source.  The upper-layer code uses the PIC methods to
107 * control a given source.  The lower-layer PIC drivers can store additional
108 * private data in a given interrupt source such as an interrupt pin number
109 * or an I/O APIC pointer.
110 */
111struct intsrc {
112	struct pic *is_pic;
113	struct intr_event *is_event;
114	u_long *is_count;
115	u_long *is_straycount;
116	u_int is_index;
117	u_int is_enabled:1;
118};
119
120struct trapframe;
121
122extern struct mtx icu_lock;
123extern int elcr_found;
124
125#ifndef DEV_ATPIC
126void	atpic_reset(void);
127#endif
128/* XXX: The elcr_* prototypes probably belong somewhere else. */
129int	elcr_probe(void);
130enum intr_trigger elcr_read_trigger(u_int irq);
131void	elcr_resume(void);
132void	elcr_write_trigger(u_int irq, enum intr_trigger trigger);
133#ifdef SMP
134void	intr_add_cpu(u_int apic_id);
135#else
136#define	intr_add_cpu(apic_id)
137#endif
138int	intr_add_handler(const char *name, int vector, driver_filter_t filter,
139			 driver_intr_t handler, void *arg, enum intr_type flags,
140			 void **cookiep);
141int	intr_config_intr(int vector, enum intr_trigger trig,
142    enum intr_polarity pol);
143void	intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
144struct intsrc *intr_lookup_source(int vector);
145int	intr_register_pic(struct pic *pic);
146int	intr_register_source(struct intsrc *isrc);
147int	intr_remove_handler(void *cookie);
148void	intr_resume(void);
149void	intr_suspend(void);
150void	intrcnt_add(const char *name, u_long **countp);
151int	msi_alloc(device_t dev, int count, int maxcount, int *irqs, int *newirq,
152    int *newcount);
153void	msi_init(void);
154int	msi_release(int *irqs, int count);
155int	msix_alloc(device_t dev, int index, int *irq, int *new);
156int	msix_remap(int index, int irq);
157int	msix_release(int irq);
158
159#endif	/* !LOCORE */
160#endif	/* _KERNEL */
161#endif	/* !__MACHINE_INTR_MACHDEP_H__ */
162