pmap.c revision 266339
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2003 Peter Wemm 9 * All rights reserved. 10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 11 * All rights reserved. 12 * 13 * This code is derived from software contributed to Berkeley by 14 * the Systems Programming Group of the University of Utah Computer 15 * Science Department and William Jolitz of UUNET Technologies Inc. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. All advertising materials mentioning features or use of this software 26 * must display the following acknowledgement: 27 * This product includes software developed by the University of 28 * California, Berkeley and its contributors. 29 * 4. Neither the name of the University nor the names of its contributors 30 * may be used to endorse or promote products derived from this software 31 * without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 * 45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 46 */ 47/*- 48 * Copyright (c) 2003 Networks Associates Technology, Inc. 49 * All rights reserved. 50 * 51 * This software was developed for the FreeBSD Project by Jake Burkholder, 52 * Safeport Network Services, and Network Associates Laboratories, the 53 * Security Research Division of Network Associates, Inc. under 54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 55 * CHATS research program. 56 * 57 * Redistribution and use in source and binary forms, with or without 58 * modification, are permitted provided that the following conditions 59 * are met: 60 * 1. Redistributions of source code must retain the above copyright 61 * notice, this list of conditions and the following disclaimer. 62 * 2. Redistributions in binary form must reproduce the above copyright 63 * notice, this list of conditions and the following disclaimer in the 64 * documentation and/or other materials provided with the distribution. 65 * 66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 76 * SUCH DAMAGE. 77 */ 78 79#define AMD64_NPT_AWARE 80 81#include <sys/cdefs.h> 82__FBSDID("$FreeBSD: stable/10/sys/amd64/amd64/pmap.c 266339 2014-05-17 19:11:08Z jhb $"); 83 84/* 85 * Manages physical address maps. 86 * 87 * Since the information managed by this module is 88 * also stored by the logical address mapping module, 89 * this module may throw away valid virtual-to-physical 90 * mappings at almost any time. However, invalidations 91 * of virtual-to-physical mappings must be done as 92 * requested. 93 * 94 * In order to cope with hardware architectures which 95 * make virtual-to-physical map invalidates expensive, 96 * this module may delay invalidate or reduced protection 97 * operations until such time as they are actually 98 * necessary. This module is given full information as 99 * to which processors are currently using which maps, 100 * and to when physical maps must be made correct. 101 */ 102 103#include "opt_pmap.h" 104#include "opt_vm.h" 105 106#include <sys/param.h> 107#include <sys/bus.h> 108#include <sys/systm.h> 109#include <sys/kernel.h> 110#include <sys/ktr.h> 111#include <sys/lock.h> 112#include <sys/malloc.h> 113#include <sys/mman.h> 114#include <sys/mutex.h> 115#include <sys/proc.h> 116#include <sys/rwlock.h> 117#include <sys/sx.h> 118#include <sys/vmmeter.h> 119#include <sys/sched.h> 120#include <sys/sysctl.h> 121#include <sys/_unrhdr.h> 122#include <sys/smp.h> 123 124#include <vm/vm.h> 125#include <vm/vm_param.h> 126#include <vm/vm_kern.h> 127#include <vm/vm_page.h> 128#include <vm/vm_map.h> 129#include <vm/vm_object.h> 130#include <vm/vm_extern.h> 131#include <vm/vm_pageout.h> 132#include <vm/vm_pager.h> 133#include <vm/vm_radix.h> 134#include <vm/vm_reserv.h> 135#include <vm/uma.h> 136 137#include <machine/intr_machdep.h> 138#include <machine/apicvar.h> 139#include <machine/cpu.h> 140#include <machine/cputypes.h> 141#include <machine/md_var.h> 142#include <machine/pcb.h> 143#include <machine/specialreg.h> 144#ifdef SMP 145#include <machine/smp.h> 146#endif 147 148static __inline boolean_t 149pmap_emulate_ad_bits(pmap_t pmap) 150{ 151 152 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0); 153} 154 155static __inline pt_entry_t 156pmap_valid_bit(pmap_t pmap) 157{ 158 pt_entry_t mask; 159 160 switch (pmap->pm_type) { 161 case PT_X86: 162 mask = X86_PG_V; 163 break; 164 case PT_EPT: 165 if (pmap_emulate_ad_bits(pmap)) 166 mask = EPT_PG_EMUL_V; 167 else 168 mask = EPT_PG_READ; 169 break; 170 default: 171 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type); 172 } 173 174 return (mask); 175} 176 177static __inline pt_entry_t 178pmap_rw_bit(pmap_t pmap) 179{ 180 pt_entry_t mask; 181 182 switch (pmap->pm_type) { 183 case PT_X86: 184 mask = X86_PG_RW; 185 break; 186 case PT_EPT: 187 if (pmap_emulate_ad_bits(pmap)) 188 mask = EPT_PG_EMUL_RW; 189 else 190 mask = EPT_PG_WRITE; 191 break; 192 default: 193 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type); 194 } 195 196 return (mask); 197} 198 199static __inline pt_entry_t 200pmap_global_bit(pmap_t pmap) 201{ 202 pt_entry_t mask; 203 204 switch (pmap->pm_type) { 205 case PT_X86: 206 mask = X86_PG_G; 207 break; 208 case PT_EPT: 209 mask = 0; 210 break; 211 default: 212 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type); 213 } 214 215 return (mask); 216} 217 218static __inline pt_entry_t 219pmap_accessed_bit(pmap_t pmap) 220{ 221 pt_entry_t mask; 222 223 switch (pmap->pm_type) { 224 case PT_X86: 225 mask = X86_PG_A; 226 break; 227 case PT_EPT: 228 if (pmap_emulate_ad_bits(pmap)) 229 mask = EPT_PG_READ; 230 else 231 mask = EPT_PG_A; 232 break; 233 default: 234 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type); 235 } 236 237 return (mask); 238} 239 240static __inline pt_entry_t 241pmap_modified_bit(pmap_t pmap) 242{ 243 pt_entry_t mask; 244 245 switch (pmap->pm_type) { 246 case PT_X86: 247 mask = X86_PG_M; 248 break; 249 case PT_EPT: 250 if (pmap_emulate_ad_bits(pmap)) 251 mask = EPT_PG_WRITE; 252 else 253 mask = EPT_PG_M; 254 break; 255 default: 256 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type); 257 } 258 259 return (mask); 260} 261 262#if !defined(DIAGNOSTIC) 263#ifdef __GNUC_GNU_INLINE__ 264#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 265#else 266#define PMAP_INLINE extern inline 267#endif 268#else 269#define PMAP_INLINE 270#endif 271 272#ifdef PV_STATS 273#define PV_STAT(x) do { x ; } while (0) 274#else 275#define PV_STAT(x) do { } while (0) 276#endif 277 278#define pa_index(pa) ((pa) >> PDRSHIFT) 279#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 280 281#define NPV_LIST_LOCKS MAXCPU 282 283#define PHYS_TO_PV_LIST_LOCK(pa) \ 284 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS]) 285 286#define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \ 287 struct rwlock **_lockp = (lockp); \ 288 struct rwlock *_new_lock; \ 289 \ 290 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \ 291 if (_new_lock != *_lockp) { \ 292 if (*_lockp != NULL) \ 293 rw_wunlock(*_lockp); \ 294 *_lockp = _new_lock; \ 295 rw_wlock(*_lockp); \ 296 } \ 297} while (0) 298 299#define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \ 300 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m)) 301 302#define RELEASE_PV_LIST_LOCK(lockp) do { \ 303 struct rwlock **_lockp = (lockp); \ 304 \ 305 if (*_lockp != NULL) { \ 306 rw_wunlock(*_lockp); \ 307 *_lockp = NULL; \ 308 } \ 309} while (0) 310 311#define VM_PAGE_TO_PV_LIST_LOCK(m) \ 312 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m)) 313 314struct pmap kernel_pmap_store; 315 316vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 317vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 318 319int nkpt; 320SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0, 321 "Number of kernel page table pages allocated on bootup"); 322 323static int ndmpdp; 324vm_paddr_t dmaplimit; 325vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS; 326pt_entry_t pg_nx; 327 328static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 329 330static int pat_works = 1; 331SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1, 332 "Is page attribute table fully functional?"); 333 334static int pg_ps_enabled = 1; 335SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 336 "Are large page mappings enabled?"); 337 338#define PAT_INDEX_SIZE 8 339static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */ 340 341static u_int64_t KPTphys; /* phys addr of kernel level 1 */ 342static u_int64_t KPDphys; /* phys addr of kernel level 2 */ 343u_int64_t KPDPphys; /* phys addr of kernel level 3 */ 344u_int64_t KPML4phys; /* phys addr of kernel level 4 */ 345 346static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */ 347static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */ 348static int ndmpdpphys; /* number of DMPDPphys pages */ 349 350static struct rwlock_padalign pvh_global_lock; 351 352/* 353 * Data for the pv entry allocation mechanism 354 */ 355static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 356static struct mtx pv_chunks_mutex; 357static struct rwlock pv_list_locks[NPV_LIST_LOCKS]; 358static struct md_page *pv_table; 359 360/* 361 * All those kernel PT submaps that BSD is so fond of 362 */ 363pt_entry_t *CMAP1 = 0; 364caddr_t CADDR1 = 0; 365 366static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */ 367 368static struct unrhdr pcid_unr; 369static struct mtx pcid_mtx; 370int pmap_pcid_enabled = 0; 371SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN, &pmap_pcid_enabled, 372 0, "Is TLB Context ID enabled ?"); 373int invpcid_works = 0; 374SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0, 375 "Is the invpcid instruction available ?"); 376 377static int 378pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS) 379{ 380 int i; 381 uint64_t res; 382 383 res = 0; 384 CPU_FOREACH(i) { 385 res += cpuid_to_pcpu[i]->pc_pm_save_cnt; 386 } 387 return (sysctl_handle_64(oidp, &res, 0, req)); 388} 389SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW | 390 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU", 391 "Count of saved TLB context on switch"); 392 393/* 394 * Crashdump maps. 395 */ 396static caddr_t crashdumpmap; 397 398static void free_pv_chunk(struct pv_chunk *pc); 399static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 400static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp); 401static int popcnt_pc_map_elem(uint64_t elem); 402static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp); 403static void reserve_pv_entries(pmap_t pmap, int needed, 404 struct rwlock **lockp); 405static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 406 struct rwlock **lockp); 407static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 408 struct rwlock **lockp); 409static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 410 struct rwlock **lockp); 411static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 412static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 413 vm_offset_t va); 414 415static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode); 416static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 417static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, 418 vm_offset_t va, struct rwlock **lockp); 419static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, 420 vm_offset_t va); 421static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, 422 vm_prot_t prot, struct rwlock **lockp); 423static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 424 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp); 425static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte); 426static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 427static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 428static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va); 429static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask); 430static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va, 431 struct rwlock **lockp); 432static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 433 vm_prot_t prot); 434static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask); 435static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 436 struct spglist *free, struct rwlock **lockp); 437static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 438 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp); 439static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte); 440static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 441 struct spglist *free); 442static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 443 vm_page_t m, struct rwlock **lockp); 444static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 445 pd_entry_t newpde); 446static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde); 447 448static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, 449 struct rwlock **lockp); 450static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va, 451 struct rwlock **lockp); 452static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, 453 struct rwlock **lockp); 454 455static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, 456 struct spglist *free); 457static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *); 458static vm_offset_t pmap_kmem_choose(vm_offset_t addr); 459 460/* 461 * Move the kernel virtual free pointer to the next 462 * 2MB. This is used to help improve performance 463 * by using a large (2MB) page for much of the kernel 464 * (.text, .data, .bss) 465 */ 466static vm_offset_t 467pmap_kmem_choose(vm_offset_t addr) 468{ 469 vm_offset_t newaddr = addr; 470 471 newaddr = (addr + (NBPDR - 1)) & ~(NBPDR - 1); 472 return (newaddr); 473} 474 475/********************/ 476/* Inline functions */ 477/********************/ 478 479/* Return a non-clipped PD index for a given VA */ 480static __inline vm_pindex_t 481pmap_pde_pindex(vm_offset_t va) 482{ 483 return (va >> PDRSHIFT); 484} 485 486 487/* Return various clipped indexes for a given VA */ 488static __inline vm_pindex_t 489pmap_pte_index(vm_offset_t va) 490{ 491 492 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1)); 493} 494 495static __inline vm_pindex_t 496pmap_pde_index(vm_offset_t va) 497{ 498 499 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1)); 500} 501 502static __inline vm_pindex_t 503pmap_pdpe_index(vm_offset_t va) 504{ 505 506 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1)); 507} 508 509static __inline vm_pindex_t 510pmap_pml4e_index(vm_offset_t va) 511{ 512 513 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1)); 514} 515 516/* Return a pointer to the PML4 slot that corresponds to a VA */ 517static __inline pml4_entry_t * 518pmap_pml4e(pmap_t pmap, vm_offset_t va) 519{ 520 521 return (&pmap->pm_pml4[pmap_pml4e_index(va)]); 522} 523 524/* Return a pointer to the PDP slot that corresponds to a VA */ 525static __inline pdp_entry_t * 526pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va) 527{ 528 pdp_entry_t *pdpe; 529 530 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME); 531 return (&pdpe[pmap_pdpe_index(va)]); 532} 533 534/* Return a pointer to the PDP slot that corresponds to a VA */ 535static __inline pdp_entry_t * 536pmap_pdpe(pmap_t pmap, vm_offset_t va) 537{ 538 pml4_entry_t *pml4e; 539 pt_entry_t PG_V; 540 541 PG_V = pmap_valid_bit(pmap); 542 pml4e = pmap_pml4e(pmap, va); 543 if ((*pml4e & PG_V) == 0) 544 return (NULL); 545 return (pmap_pml4e_to_pdpe(pml4e, va)); 546} 547 548/* Return a pointer to the PD slot that corresponds to a VA */ 549static __inline pd_entry_t * 550pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va) 551{ 552 pd_entry_t *pde; 553 554 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME); 555 return (&pde[pmap_pde_index(va)]); 556} 557 558/* Return a pointer to the PD slot that corresponds to a VA */ 559static __inline pd_entry_t * 560pmap_pde(pmap_t pmap, vm_offset_t va) 561{ 562 pdp_entry_t *pdpe; 563 pt_entry_t PG_V; 564 565 PG_V = pmap_valid_bit(pmap); 566 pdpe = pmap_pdpe(pmap, va); 567 if (pdpe == NULL || (*pdpe & PG_V) == 0) 568 return (NULL); 569 return (pmap_pdpe_to_pde(pdpe, va)); 570} 571 572/* Return a pointer to the PT slot that corresponds to a VA */ 573static __inline pt_entry_t * 574pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va) 575{ 576 pt_entry_t *pte; 577 578 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME); 579 return (&pte[pmap_pte_index(va)]); 580} 581 582/* Return a pointer to the PT slot that corresponds to a VA */ 583static __inline pt_entry_t * 584pmap_pte(pmap_t pmap, vm_offset_t va) 585{ 586 pd_entry_t *pde; 587 pt_entry_t PG_V; 588 589 PG_V = pmap_valid_bit(pmap); 590 pde = pmap_pde(pmap, va); 591 if (pde == NULL || (*pde & PG_V) == 0) 592 return (NULL); 593 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */ 594 return ((pt_entry_t *)pde); 595 return (pmap_pde_to_pte(pde, va)); 596} 597 598static __inline void 599pmap_resident_count_inc(pmap_t pmap, int count) 600{ 601 602 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 603 pmap->pm_stats.resident_count += count; 604} 605 606static __inline void 607pmap_resident_count_dec(pmap_t pmap, int count) 608{ 609 610 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 611 KASSERT(pmap->pm_stats.resident_count >= count, 612 ("pmap %p resident count underflow %ld %d", pmap, 613 pmap->pm_stats.resident_count, count)); 614 pmap->pm_stats.resident_count -= count; 615} 616 617PMAP_INLINE pt_entry_t * 618vtopte(vm_offset_t va) 619{ 620 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1); 621 622 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va)); 623 624 return (PTmap + ((va >> PAGE_SHIFT) & mask)); 625} 626 627static __inline pd_entry_t * 628vtopde(vm_offset_t va) 629{ 630 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1); 631 632 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va)); 633 634 return (PDmap + ((va >> PDRSHIFT) & mask)); 635} 636 637static u_int64_t 638allocpages(vm_paddr_t *firstaddr, int n) 639{ 640 u_int64_t ret; 641 642 ret = *firstaddr; 643 bzero((void *)ret, n * PAGE_SIZE); 644 *firstaddr += n * PAGE_SIZE; 645 return (ret); 646} 647 648CTASSERT(powerof2(NDMPML4E)); 649 650/* number of kernel PDP slots */ 651#define NKPDPE(ptpgs) howmany((ptpgs), NPDEPG) 652 653static void 654nkpt_init(vm_paddr_t addr) 655{ 656 int pt_pages; 657 658#ifdef NKPT 659 pt_pages = NKPT; 660#else 661 pt_pages = howmany(addr, 1 << PDRSHIFT); 662 pt_pages += NKPDPE(pt_pages); 663 664 /* 665 * Add some slop beyond the bare minimum required for bootstrapping 666 * the kernel. 667 * 668 * This is quite important when allocating KVA for kernel modules. 669 * The modules are required to be linked in the negative 2GB of 670 * the address space. If we run out of KVA in this region then 671 * pmap_growkernel() will need to allocate page table pages to map 672 * the entire 512GB of KVA space which is an unnecessary tax on 673 * physical memory. 674 */ 675 pt_pages += 8; /* 16MB additional slop for kernel modules */ 676#endif 677 nkpt = pt_pages; 678} 679 680static void 681create_pagetables(vm_paddr_t *firstaddr) 682{ 683 int i, j, ndm1g, nkpdpe; 684 pt_entry_t *pt_p; 685 pd_entry_t *pd_p; 686 pdp_entry_t *pdp_p; 687 pml4_entry_t *p4_p; 688 689 /* Allocate page table pages for the direct map */ 690 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT; 691 if (ndmpdp < 4) /* Minimum 4GB of dirmap */ 692 ndmpdp = 4; 693 ndmpdpphys = howmany(ndmpdp, NPDPEPG); 694 if (ndmpdpphys > NDMPML4E) { 695 /* 696 * Each NDMPML4E allows 512 GB, so limit to that, 697 * and then readjust ndmpdp and ndmpdpphys. 698 */ 699 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512); 700 Maxmem = atop(NDMPML4E * NBPML4); 701 ndmpdpphys = NDMPML4E; 702 ndmpdp = NDMPML4E * NPDEPG; 703 } 704 DMPDPphys = allocpages(firstaddr, ndmpdpphys); 705 ndm1g = 0; 706 if ((amd_feature & AMDID_PAGE1GB) != 0) 707 ndm1g = ptoa(Maxmem) >> PDPSHIFT; 708 if (ndm1g < ndmpdp) 709 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g); 710 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT; 711 712 /* Allocate pages */ 713 KPML4phys = allocpages(firstaddr, 1); 714 KPDPphys = allocpages(firstaddr, NKPML4E); 715 716 /* 717 * Allocate the initial number of kernel page table pages required to 718 * bootstrap. We defer this until after all memory-size dependent 719 * allocations are done (e.g. direct map), so that we don't have to 720 * build in too much slop in our estimate. 721 * 722 * Note that when NKPML4E > 1, we have an empty page underneath 723 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed) 724 * pages. (pmap_enter requires a PD page to exist for each KPML4E.) 725 */ 726 nkpt_init(*firstaddr); 727 nkpdpe = NKPDPE(nkpt); 728 729 KPTphys = allocpages(firstaddr, nkpt); 730 KPDphys = allocpages(firstaddr, nkpdpe); 731 732 /* Fill in the underlying page table pages */ 733 /* Nominally read-only (but really R/W) from zero to physfree */ 734 /* XXX not fully used, underneath 2M pages */ 735 pt_p = (pt_entry_t *)KPTphys; 736 for (i = 0; ptoa(i) < *firstaddr; i++) 737 pt_p[i] = ptoa(i) | X86_PG_RW | X86_PG_V | X86_PG_G; 738 739 /* Now map the page tables at their location within PTmap */ 740 pd_p = (pd_entry_t *)KPDphys; 741 for (i = 0; i < nkpt; i++) 742 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V; 743 744 /* Map from zero to end of allocations under 2M pages */ 745 /* This replaces some of the KPTphys entries above */ 746 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++) 747 pd_p[i] = (i << PDRSHIFT) | X86_PG_RW | X86_PG_V | PG_PS | 748 X86_PG_G; 749 750 /* And connect up the PD to the PDP (leaving room for L4 pages) */ 751 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE)); 752 for (i = 0; i < nkpdpe; i++) 753 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V | 754 PG_U; 755 756 /* 757 * Now, set up the direct map region using 2MB and/or 1GB pages. If 758 * the end of physical memory is not aligned to a 1GB page boundary, 759 * then the residual physical memory is mapped with 2MB pages. Later, 760 * if pmap_mapdev{_attr}() uses the direct map for non-write-back 761 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings 762 * that are partially used. 763 */ 764 pd_p = (pd_entry_t *)DMPDphys; 765 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) { 766 pd_p[j] = (vm_paddr_t)i << PDRSHIFT; 767 /* Preset PG_M and PG_A because demotion expects it. */ 768 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G | 769 X86_PG_M | X86_PG_A; 770 } 771 pdp_p = (pdp_entry_t *)DMPDPphys; 772 for (i = 0; i < ndm1g; i++) { 773 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT; 774 /* Preset PG_M and PG_A because demotion expects it. */ 775 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G | 776 X86_PG_M | X86_PG_A; 777 } 778 for (j = 0; i < ndmpdp; i++, j++) { 779 pdp_p[i] = DMPDphys + ptoa(j); 780 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_U; 781 } 782 783 /* And recursively map PML4 to itself in order to get PTmap */ 784 p4_p = (pml4_entry_t *)KPML4phys; 785 p4_p[PML4PML4I] = KPML4phys; 786 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | PG_U; 787 788 /* Connect the Direct Map slot(s) up to the PML4. */ 789 for (i = 0; i < ndmpdpphys; i++) { 790 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i); 791 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | PG_U; 792 } 793 794 /* Connect the KVA slots up to the PML4 */ 795 for (i = 0; i < NKPML4E; i++) { 796 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i); 797 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V | PG_U; 798 } 799} 800 801/* 802 * Bootstrap the system enough to run with virtual memory. 803 * 804 * On amd64 this is called after mapping has already been enabled 805 * and just syncs the pmap module with what has already been done. 806 * [We can't call it easily with mapping off since the kernel is not 807 * mapped with PA == VA, hence we would have to relocate every address 808 * from the linked base (virtual) address "KERNBASE" to the actual 809 * (physical) address starting relative to 0] 810 */ 811void 812pmap_bootstrap(vm_paddr_t *firstaddr) 813{ 814 vm_offset_t va; 815 pt_entry_t *pte, *unused; 816 817 /* 818 * Create an initial set of page tables to run the kernel in. 819 */ 820 create_pagetables(firstaddr); 821 822 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr; 823 virtual_avail = pmap_kmem_choose(virtual_avail); 824 825 virtual_end = VM_MAX_KERNEL_ADDRESS; 826 827 828 /* XXX do %cr0 as well */ 829 load_cr4(rcr4() | CR4_PGE | CR4_PSE); 830 load_cr3(KPML4phys); 831 if (cpu_stdext_feature & CPUID_STDEXT_SMEP) 832 load_cr4(rcr4() | CR4_SMEP); 833 834 /* 835 * Initialize the kernel pmap (which is statically allocated). 836 */ 837 PMAP_LOCK_INIT(kernel_pmap); 838 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys); 839 kernel_pmap->pm_cr3 = KPML4phys; 840 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 841 CPU_FILL(&kernel_pmap->pm_save); /* always superset of pm_active */ 842 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 843 kernel_pmap->pm_flags = pmap_flags; 844 845 /* 846 * Initialize the global pv list lock. 847 */ 848 rw_init(&pvh_global_lock, "pmap pv global"); 849 850 /* 851 * Reserve some special page table entries/VA space for temporary 852 * mapping of pages. 853 */ 854#define SYSMAP(c, p, v, n) \ 855 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 856 857 va = virtual_avail; 858 pte = vtopte(va); 859 860 /* 861 * CMAP1 is only used for the memory test. 862 */ 863 SYSMAP(caddr_t, CMAP1, CADDR1, 1) 864 865 /* 866 * Crashdump maps. 867 */ 868 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 869 870 virtual_avail = va; 871 872 /* Initialize the PAT MSR. */ 873 pmap_init_pat(); 874 875 /* Initialize TLB Context Id. */ 876 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled); 877 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) { 878 load_cr4(rcr4() | CR4_PCIDE); 879 mtx_init(&pcid_mtx, "pcid", NULL, MTX_DEF); 880 init_unrhdr(&pcid_unr, 1, (1 << 12) - 1, &pcid_mtx); 881 /* Check for INVPCID support */ 882 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID) 883 != 0; 884 kernel_pmap->pm_pcid = 0; 885#ifndef SMP 886 pmap_pcid_enabled = 0; 887#endif 888 } else 889 pmap_pcid_enabled = 0; 890} 891 892/* 893 * Setup the PAT MSR. 894 */ 895void 896pmap_init_pat(void) 897{ 898 int pat_table[PAT_INDEX_SIZE]; 899 uint64_t pat_msr; 900 u_long cr0, cr4; 901 int i; 902 903 /* Bail if this CPU doesn't implement PAT. */ 904 if ((cpu_feature & CPUID_PAT) == 0) 905 panic("no PAT??"); 906 907 /* Set default PAT index table. */ 908 for (i = 0; i < PAT_INDEX_SIZE; i++) 909 pat_table[i] = -1; 910 pat_table[PAT_WRITE_BACK] = 0; 911 pat_table[PAT_WRITE_THROUGH] = 1; 912 pat_table[PAT_UNCACHEABLE] = 3; 913 pat_table[PAT_WRITE_COMBINING] = 3; 914 pat_table[PAT_WRITE_PROTECTED] = 3; 915 pat_table[PAT_UNCACHED] = 3; 916 917 /* Initialize default PAT entries. */ 918 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) | 919 PAT_VALUE(1, PAT_WRITE_THROUGH) | 920 PAT_VALUE(2, PAT_UNCACHED) | 921 PAT_VALUE(3, PAT_UNCACHEABLE) | 922 PAT_VALUE(4, PAT_WRITE_BACK) | 923 PAT_VALUE(5, PAT_WRITE_THROUGH) | 924 PAT_VALUE(6, PAT_UNCACHED) | 925 PAT_VALUE(7, PAT_UNCACHEABLE); 926 927 if (pat_works) { 928 /* 929 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC. 930 * Program 5 and 6 as WP and WC. 931 * Leave 4 and 7 as WB and UC. 932 */ 933 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6)); 934 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) | 935 PAT_VALUE(6, PAT_WRITE_COMBINING); 936 pat_table[PAT_UNCACHED] = 2; 937 pat_table[PAT_WRITE_PROTECTED] = 5; 938 pat_table[PAT_WRITE_COMBINING] = 6; 939 } else { 940 /* 941 * Just replace PAT Index 2 with WC instead of UC-. 942 */ 943 pat_msr &= ~PAT_MASK(2); 944 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 945 pat_table[PAT_WRITE_COMBINING] = 2; 946 } 947 948 /* Disable PGE. */ 949 cr4 = rcr4(); 950 load_cr4(cr4 & ~CR4_PGE); 951 952 /* Disable caches (CD = 1, NW = 0). */ 953 cr0 = rcr0(); 954 load_cr0((cr0 & ~CR0_NW) | CR0_CD); 955 956 /* Flushes caches and TLBs. */ 957 wbinvd(); 958 invltlb(); 959 960 /* Update PAT and index table. */ 961 wrmsr(MSR_PAT, pat_msr); 962 for (i = 0; i < PAT_INDEX_SIZE; i++) 963 pat_index[i] = pat_table[i]; 964 965 /* Flush caches and TLBs again. */ 966 wbinvd(); 967 invltlb(); 968 969 /* Restore caches and PGE. */ 970 load_cr0(cr0); 971 load_cr4(cr4); 972} 973 974/* 975 * Initialize a vm_page's machine-dependent fields. 976 */ 977void 978pmap_page_init(vm_page_t m) 979{ 980 981 TAILQ_INIT(&m->md.pv_list); 982 m->md.pat_mode = PAT_WRITE_BACK; 983} 984 985/* 986 * Initialize the pmap module. 987 * Called by vm_init, to initialize any structures that the pmap 988 * system needs to map virtual memory. 989 */ 990void 991pmap_init(void) 992{ 993 vm_page_t mpte; 994 vm_size_t s; 995 int i, pv_npg; 996 997 /* 998 * Initialize the vm page array entries for the kernel pmap's 999 * page table pages. 1000 */ 1001 for (i = 0; i < nkpt; i++) { 1002 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT)); 1003 KASSERT(mpte >= vm_page_array && 1004 mpte < &vm_page_array[vm_page_array_size], 1005 ("pmap_init: page table page is out of range")); 1006 mpte->pindex = pmap_pde_pindex(KERNBASE) + i; 1007 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT); 1008 } 1009 1010 /* 1011 * If the kernel is running on a virtual machine, then it must assume 1012 * that MCA is enabled by the hypervisor. Moreover, the kernel must 1013 * be prepared for the hypervisor changing the vendor and family that 1014 * are reported by CPUID. Consequently, the workaround for AMD Family 1015 * 10h Erratum 383 is enabled if the processor's feature set does not 1016 * include at least one feature that is only supported by older Intel 1017 * or newer AMD processors. 1018 */ 1019 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 && 1020 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI | 1021 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP | 1022 AMDID2_FMA4)) == 0) 1023 workaround_erratum383 = 1; 1024 1025 /* 1026 * Are large page mappings enabled? 1027 */ 1028 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 1029 if (pg_ps_enabled) { 1030 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 1031 ("pmap_init: can't assign to pagesizes[1]")); 1032 pagesizes[1] = NBPDR; 1033 } 1034 1035 /* 1036 * Initialize the pv chunk list mutex. 1037 */ 1038 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF); 1039 1040 /* 1041 * Initialize the pool of pv list locks. 1042 */ 1043 for (i = 0; i < NPV_LIST_LOCKS; i++) 1044 rw_init(&pv_list_locks[i], "pmap pv list"); 1045 1046 /* 1047 * Calculate the size of the pv head table for superpages. 1048 */ 1049 for (i = 0; phys_avail[i + 1]; i += 2); 1050 pv_npg = round_2mpage(phys_avail[(i - 2) + 1]) / NBPDR; 1051 1052 /* 1053 * Allocate memory for the pv head table for superpages. 1054 */ 1055 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 1056 s = round_page(s); 1057 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s, 1058 M_WAITOK | M_ZERO); 1059 for (i = 0; i < pv_npg; i++) 1060 TAILQ_INIT(&pv_table[i].pv_list); 1061} 1062 1063static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 1064 "2MB page mapping counters"); 1065 1066static u_long pmap_pde_demotions; 1067SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD, 1068 &pmap_pde_demotions, 0, "2MB page demotions"); 1069 1070static u_long pmap_pde_mappings; 1071SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 1072 &pmap_pde_mappings, 0, "2MB page mappings"); 1073 1074static u_long pmap_pde_p_failures; 1075SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 1076 &pmap_pde_p_failures, 0, "2MB page promotion failures"); 1077 1078static u_long pmap_pde_promotions; 1079SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 1080 &pmap_pde_promotions, 0, "2MB page promotions"); 1081 1082static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0, 1083 "1GB page mapping counters"); 1084 1085static u_long pmap_pdpe_demotions; 1086SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD, 1087 &pmap_pdpe_demotions, 0, "1GB page demotions"); 1088 1089/*************************************************** 1090 * Low level helper routines..... 1091 ***************************************************/ 1092 1093static pt_entry_t 1094pmap_swap_pat(pmap_t pmap, pt_entry_t entry) 1095{ 1096 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT; 1097 1098 switch (pmap->pm_type) { 1099 case PT_X86: 1100 /* Verify that both PAT bits are not set at the same time */ 1101 KASSERT((entry & x86_pat_bits) != x86_pat_bits, 1102 ("Invalid PAT bits in entry %#lx", entry)); 1103 1104 /* Swap the PAT bits if one of them is set */ 1105 if ((entry & x86_pat_bits) != 0) 1106 entry ^= x86_pat_bits; 1107 break; 1108 case PT_EPT: 1109 /* 1110 * Nothing to do - the memory attributes are represented 1111 * the same way for regular pages and superpages. 1112 */ 1113 break; 1114 default: 1115 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type); 1116 } 1117 1118 return (entry); 1119} 1120 1121/* 1122 * Determine the appropriate bits to set in a PTE or PDE for a specified 1123 * caching mode. 1124 */ 1125static int 1126pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde) 1127{ 1128 int cache_bits, pat_flag, pat_idx; 1129 1130 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0) 1131 panic("Unknown caching mode %d\n", mode); 1132 1133 switch (pmap->pm_type) { 1134 case PT_X86: 1135 /* The PAT bit is different for PTE's and PDE's. */ 1136 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT; 1137 1138 /* Map the caching mode to a PAT index. */ 1139 pat_idx = pat_index[mode]; 1140 1141 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 1142 cache_bits = 0; 1143 if (pat_idx & 0x4) 1144 cache_bits |= pat_flag; 1145 if (pat_idx & 0x2) 1146 cache_bits |= PG_NC_PCD; 1147 if (pat_idx & 0x1) 1148 cache_bits |= PG_NC_PWT; 1149 break; 1150 1151 case PT_EPT: 1152 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode); 1153 break; 1154 1155 default: 1156 panic("unsupported pmap type %d", pmap->pm_type); 1157 } 1158 1159 return (cache_bits); 1160} 1161 1162static int 1163pmap_cache_mask(pmap_t pmap, boolean_t is_pde) 1164{ 1165 int mask; 1166 1167 switch (pmap->pm_type) { 1168 case PT_X86: 1169 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE; 1170 break; 1171 case PT_EPT: 1172 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7); 1173 break; 1174 default: 1175 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type); 1176 } 1177 1178 return (mask); 1179} 1180 1181static __inline boolean_t 1182pmap_ps_enabled(pmap_t pmap) 1183{ 1184 1185 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0); 1186} 1187 1188static void 1189pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde) 1190{ 1191 1192 switch (pmap->pm_type) { 1193 case PT_X86: 1194 break; 1195 case PT_EPT: 1196 /* 1197 * XXX 1198 * This is a little bogus since the generation number is 1199 * supposed to be bumped up when a region of the address 1200 * space is invalidated in the page tables. 1201 * 1202 * In this case the old PDE entry is valid but yet we want 1203 * to make sure that any mappings using the old entry are 1204 * invalidated in the TLB. 1205 * 1206 * The reason this works as expected is because we rendezvous 1207 * "all" host cpus and force any vcpu context to exit as a 1208 * side-effect. 1209 */ 1210 atomic_add_acq_long(&pmap->pm_eptgen, 1); 1211 break; 1212 default: 1213 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type); 1214 } 1215 pde_store(pde, newpde); 1216} 1217 1218/* 1219 * After changing the page size for the specified virtual address in the page 1220 * table, flush the corresponding entries from the processor's TLB. Only the 1221 * calling processor's TLB is affected. 1222 * 1223 * The calling thread must be pinned to a processor. 1224 */ 1225static void 1226pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde) 1227{ 1228 pt_entry_t PG_G; 1229 1230 if (pmap->pm_type == PT_EPT) 1231 return; 1232 1233 KASSERT(pmap->pm_type == PT_X86, 1234 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type)); 1235 1236 PG_G = pmap_global_bit(pmap); 1237 1238 if ((newpde & PG_PS) == 0) 1239 /* Demotion: flush a specific 2MB page mapping. */ 1240 invlpg(va); 1241 else if ((newpde & PG_G) == 0) 1242 /* 1243 * Promotion: flush every 4KB page mapping from the TLB 1244 * because there are too many to flush individually. 1245 */ 1246 invltlb(); 1247 else { 1248 /* 1249 * Promotion: flush every 4KB page mapping from the TLB, 1250 * including any global (PG_G) mappings. 1251 */ 1252 invltlb_globpcid(); 1253 } 1254} 1255#ifdef SMP 1256 1257static void 1258pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va) 1259{ 1260 struct invpcid_descr d; 1261 uint64_t cr3; 1262 1263 if (invpcid_works) { 1264 d.pcid = pmap->pm_pcid; 1265 d.pad = 0; 1266 d.addr = va; 1267 invpcid(&d, INVPCID_ADDR); 1268 return; 1269 } 1270 1271 cr3 = rcr3(); 1272 critical_enter(); 1273 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE); 1274 invlpg(va); 1275 load_cr3(cr3 | CR3_PCID_SAVE); 1276 critical_exit(); 1277} 1278 1279/* 1280 * For SMP, these functions have to use the IPI mechanism for coherence. 1281 * 1282 * N.B.: Before calling any of the following TLB invalidation functions, 1283 * the calling processor must ensure that all stores updating a non- 1284 * kernel page table are globally performed. Otherwise, another 1285 * processor could cache an old, pre-update entry without being 1286 * invalidated. This can happen one of two ways: (1) The pmap becomes 1287 * active on another processor after its pm_active field is checked by 1288 * one of the following functions but before a store updating the page 1289 * table is globally performed. (2) The pmap becomes active on another 1290 * processor before its pm_active field is checked but due to 1291 * speculative loads one of the following functions stills reads the 1292 * pmap as inactive on the other processor. 1293 * 1294 * The kernel page table is exempt because its pm_active field is 1295 * immutable. The kernel page table is always active on every 1296 * processor. 1297 */ 1298 1299/* 1300 * Interrupt the cpus that are executing in the guest context. 1301 * This will force the vcpu to exit and the cached EPT mappings 1302 * will be invalidated by the host before the next vmresume. 1303 */ 1304static __inline void 1305pmap_invalidate_ept(pmap_t pmap) 1306{ 1307 int ipinum; 1308 1309 sched_pin(); 1310 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active), 1311 ("pmap_invalidate_ept: absurd pm_active")); 1312 1313 /* 1314 * The TLB mappings associated with a vcpu context are not 1315 * flushed each time a different vcpu is chosen to execute. 1316 * 1317 * This is in contrast with a process's vtop mappings that 1318 * are flushed from the TLB on each context switch. 1319 * 1320 * Therefore we need to do more than just a TLB shootdown on 1321 * the active cpus in 'pmap->pm_active'. To do this we keep 1322 * track of the number of invalidations performed on this pmap. 1323 * 1324 * Each vcpu keeps a cache of this counter and compares it 1325 * just before a vmresume. If the counter is out-of-date an 1326 * invept will be done to flush stale mappings from the TLB. 1327 */ 1328 atomic_add_acq_long(&pmap->pm_eptgen, 1); 1329 1330 /* 1331 * Force the vcpu to exit and trap back into the hypervisor. 1332 */ 1333 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK; 1334 ipi_selected(pmap->pm_active, ipinum); 1335 sched_unpin(); 1336} 1337 1338void 1339pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 1340{ 1341 cpuset_t other_cpus; 1342 u_int cpuid; 1343 1344 if (pmap->pm_type == PT_EPT) { 1345 pmap_invalidate_ept(pmap); 1346 return; 1347 } 1348 1349 KASSERT(pmap->pm_type == PT_X86, 1350 ("pmap_invalidate_page: invalid type %d", pmap->pm_type)); 1351 1352 sched_pin(); 1353 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 1354 if (!pmap_pcid_enabled) { 1355 invlpg(va); 1356 } else { 1357 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) { 1358 if (pmap == PCPU_GET(curpmap)) 1359 invlpg(va); 1360 else 1361 pmap_invalidate_page_pcid(pmap, va); 1362 } else { 1363 invltlb_globpcid(); 1364 } 1365 } 1366 smp_invlpg(pmap, va); 1367 } else { 1368 cpuid = PCPU_GET(cpuid); 1369 other_cpus = all_cpus; 1370 CPU_CLR(cpuid, &other_cpus); 1371 if (CPU_ISSET(cpuid, &pmap->pm_active)) 1372 invlpg(va); 1373 else if (pmap_pcid_enabled) { 1374 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) 1375 pmap_invalidate_page_pcid(pmap, va); 1376 else 1377 invltlb_globpcid(); 1378 } 1379 if (pmap_pcid_enabled) 1380 CPU_AND(&other_cpus, &pmap->pm_save); 1381 else 1382 CPU_AND(&other_cpus, &pmap->pm_active); 1383 if (!CPU_EMPTY(&other_cpus)) 1384 smp_masked_invlpg(other_cpus, pmap, va); 1385 } 1386 sched_unpin(); 1387} 1388 1389static void 1390pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1391{ 1392 struct invpcid_descr d; 1393 uint64_t cr3; 1394 vm_offset_t addr; 1395 1396 if (invpcid_works) { 1397 d.pcid = pmap->pm_pcid; 1398 d.pad = 0; 1399 for (addr = sva; addr < eva; addr += PAGE_SIZE) { 1400 d.addr = addr; 1401 invpcid(&d, INVPCID_ADDR); 1402 } 1403 return; 1404 } 1405 1406 cr3 = rcr3(); 1407 critical_enter(); 1408 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE); 1409 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1410 invlpg(addr); 1411 load_cr3(cr3 | CR3_PCID_SAVE); 1412 critical_exit(); 1413} 1414 1415void 1416pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1417{ 1418 cpuset_t other_cpus; 1419 vm_offset_t addr; 1420 u_int cpuid; 1421 1422 if (pmap->pm_type == PT_EPT) { 1423 pmap_invalidate_ept(pmap); 1424 return; 1425 } 1426 1427 KASSERT(pmap->pm_type == PT_X86, 1428 ("pmap_invalidate_range: invalid type %d", pmap->pm_type)); 1429 1430 sched_pin(); 1431 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 1432 if (!pmap_pcid_enabled) { 1433 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1434 invlpg(addr); 1435 } else { 1436 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) { 1437 if (pmap == PCPU_GET(curpmap)) { 1438 for (addr = sva; addr < eva; 1439 addr += PAGE_SIZE) 1440 invlpg(addr); 1441 } else { 1442 pmap_invalidate_range_pcid(pmap, 1443 sva, eva); 1444 } 1445 } else { 1446 invltlb_globpcid(); 1447 } 1448 } 1449 smp_invlpg_range(pmap, sva, eva); 1450 } else { 1451 cpuid = PCPU_GET(cpuid); 1452 other_cpus = all_cpus; 1453 CPU_CLR(cpuid, &other_cpus); 1454 if (CPU_ISSET(cpuid, &pmap->pm_active)) { 1455 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1456 invlpg(addr); 1457 } else if (pmap_pcid_enabled) { 1458 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) 1459 pmap_invalidate_range_pcid(pmap, sva, eva); 1460 else 1461 invltlb_globpcid(); 1462 } 1463 if (pmap_pcid_enabled) 1464 CPU_AND(&other_cpus, &pmap->pm_save); 1465 else 1466 CPU_AND(&other_cpus, &pmap->pm_active); 1467 if (!CPU_EMPTY(&other_cpus)) 1468 smp_masked_invlpg_range(other_cpus, pmap, sva, eva); 1469 } 1470 sched_unpin(); 1471} 1472 1473void 1474pmap_invalidate_all(pmap_t pmap) 1475{ 1476 cpuset_t other_cpus; 1477 struct invpcid_descr d; 1478 uint64_t cr3; 1479 u_int cpuid; 1480 1481 if (pmap->pm_type == PT_EPT) { 1482 pmap_invalidate_ept(pmap); 1483 return; 1484 } 1485 1486 KASSERT(pmap->pm_type == PT_X86, 1487 ("pmap_invalidate_all: invalid type %d", pmap->pm_type)); 1488 1489 sched_pin(); 1490 cpuid = PCPU_GET(cpuid); 1491 if (pmap == kernel_pmap || 1492 (pmap_pcid_enabled && !CPU_CMP(&pmap->pm_save, &all_cpus)) || 1493 !CPU_CMP(&pmap->pm_active, &all_cpus)) { 1494 if (invpcid_works) { 1495 bzero(&d, sizeof(d)); 1496 invpcid(&d, INVPCID_CTXGLOB); 1497 } else { 1498 invltlb_globpcid(); 1499 } 1500 if (!CPU_ISSET(cpuid, &pmap->pm_active)) 1501 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save); 1502 smp_invltlb(pmap); 1503 } else { 1504 other_cpus = all_cpus; 1505 CPU_CLR(cpuid, &other_cpus); 1506 1507 /* 1508 * This logic is duplicated in the Xinvltlb shootdown 1509 * IPI handler. 1510 */ 1511 if (pmap_pcid_enabled) { 1512 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) { 1513 if (invpcid_works) { 1514 d.pcid = pmap->pm_pcid; 1515 d.pad = 0; 1516 d.addr = 0; 1517 invpcid(&d, INVPCID_CTX); 1518 } else { 1519 cr3 = rcr3(); 1520 critical_enter(); 1521 1522 /* 1523 * Bit 63 is clear, pcid TLB 1524 * entries are invalidated. 1525 */ 1526 load_cr3(pmap->pm_cr3); 1527 load_cr3(cr3 | CR3_PCID_SAVE); 1528 critical_exit(); 1529 } 1530 } else { 1531 invltlb_globpcid(); 1532 } 1533 } else if (CPU_ISSET(cpuid, &pmap->pm_active)) 1534 invltlb(); 1535 if (!CPU_ISSET(cpuid, &pmap->pm_active)) 1536 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save); 1537 if (pmap_pcid_enabled) 1538 CPU_AND(&other_cpus, &pmap->pm_save); 1539 else 1540 CPU_AND(&other_cpus, &pmap->pm_active); 1541 if (!CPU_EMPTY(&other_cpus)) 1542 smp_masked_invltlb(other_cpus, pmap); 1543 } 1544 sched_unpin(); 1545} 1546 1547void 1548pmap_invalidate_cache(void) 1549{ 1550 1551 sched_pin(); 1552 wbinvd(); 1553 smp_cache_flush(); 1554 sched_unpin(); 1555} 1556 1557struct pde_action { 1558 cpuset_t invalidate; /* processors that invalidate their TLB */ 1559 pmap_t pmap; 1560 vm_offset_t va; 1561 pd_entry_t *pde; 1562 pd_entry_t newpde; 1563 u_int store; /* processor that updates the PDE */ 1564}; 1565 1566static void 1567pmap_update_pde_action(void *arg) 1568{ 1569 struct pde_action *act = arg; 1570 1571 if (act->store == PCPU_GET(cpuid)) 1572 pmap_update_pde_store(act->pmap, act->pde, act->newpde); 1573} 1574 1575static void 1576pmap_update_pde_teardown(void *arg) 1577{ 1578 struct pde_action *act = arg; 1579 1580 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate)) 1581 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde); 1582} 1583 1584/* 1585 * Change the page size for the specified virtual address in a way that 1586 * prevents any possibility of the TLB ever having two entries that map the 1587 * same virtual address using different page sizes. This is the recommended 1588 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a 1589 * machine check exception for a TLB state that is improperly diagnosed as a 1590 * hardware error. 1591 */ 1592static void 1593pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1594{ 1595 struct pde_action act; 1596 cpuset_t active, other_cpus; 1597 u_int cpuid; 1598 1599 sched_pin(); 1600 cpuid = PCPU_GET(cpuid); 1601 other_cpus = all_cpus; 1602 CPU_CLR(cpuid, &other_cpus); 1603 if (pmap == kernel_pmap || pmap->pm_type == PT_EPT) 1604 active = all_cpus; 1605 else { 1606 active = pmap->pm_active; 1607 CPU_AND_ATOMIC(&pmap->pm_save, &active); 1608 } 1609 if (CPU_OVERLAP(&active, &other_cpus)) { 1610 act.store = cpuid; 1611 act.invalidate = active; 1612 act.va = va; 1613 act.pmap = pmap; 1614 act.pde = pde; 1615 act.newpde = newpde; 1616 CPU_SET(cpuid, &active); 1617 smp_rendezvous_cpus(active, 1618 smp_no_rendevous_barrier, pmap_update_pde_action, 1619 pmap_update_pde_teardown, &act); 1620 } else { 1621 pmap_update_pde_store(pmap, pde, newpde); 1622 if (CPU_ISSET(cpuid, &active)) 1623 pmap_update_pde_invalidate(pmap, va, newpde); 1624 } 1625 sched_unpin(); 1626} 1627#else /* !SMP */ 1628/* 1629 * Normal, non-SMP, invalidation functions. 1630 * We inline these within pmap.c for speed. 1631 */ 1632PMAP_INLINE void 1633pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 1634{ 1635 1636 switch (pmap->pm_type) { 1637 case PT_X86: 1638 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1639 invlpg(va); 1640 break; 1641 case PT_EPT: 1642 pmap->pm_eptgen++; 1643 break; 1644 default: 1645 panic("pmap_invalidate_page: unknown type: %d", pmap->pm_type); 1646 } 1647} 1648 1649PMAP_INLINE void 1650pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1651{ 1652 vm_offset_t addr; 1653 1654 switch (pmap->pm_type) { 1655 case PT_X86: 1656 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1657 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1658 invlpg(addr); 1659 break; 1660 case PT_EPT: 1661 pmap->pm_eptgen++; 1662 break; 1663 default: 1664 panic("pmap_invalidate_range: unknown type: %d", pmap->pm_type); 1665 } 1666} 1667 1668PMAP_INLINE void 1669pmap_invalidate_all(pmap_t pmap) 1670{ 1671 1672 switch (pmap->pm_type) { 1673 case PT_X86: 1674 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1675 invltlb(); 1676 break; 1677 case PT_EPT: 1678 pmap->pm_eptgen++; 1679 break; 1680 default: 1681 panic("pmap_invalidate_all: unknown type %d", pmap->pm_type); 1682 } 1683} 1684 1685PMAP_INLINE void 1686pmap_invalidate_cache(void) 1687{ 1688 1689 wbinvd(); 1690} 1691 1692static void 1693pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1694{ 1695 1696 pmap_update_pde_store(pmap, pde, newpde); 1697 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1698 pmap_update_pde_invalidate(pmap, va, newpde); 1699 else 1700 CPU_ZERO(&pmap->pm_save); 1701} 1702#endif /* !SMP */ 1703 1704#define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024) 1705 1706void 1707pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 1708{ 1709 1710 KASSERT((sva & PAGE_MASK) == 0, 1711 ("pmap_invalidate_cache_range: sva not page-aligned")); 1712 KASSERT((eva & PAGE_MASK) == 0, 1713 ("pmap_invalidate_cache_range: eva not page-aligned")); 1714 1715 if (cpu_feature & CPUID_SS) 1716 ; /* If "Self Snoop" is supported, do nothing. */ 1717 else if ((cpu_feature & CPUID_CLFSH) != 0 && 1718 eva - sva < PMAP_CLFLUSH_THRESHOLD) { 1719 1720 /* 1721 * XXX: Some CPUs fault, hang, or trash the local APIC 1722 * registers if we use CLFLUSH on the local APIC 1723 * range. The local APIC is always uncached, so we 1724 * don't need to flush for that range anyway. 1725 */ 1726 if (pmap_kextract(sva) == lapic_paddr) 1727 return; 1728 1729 /* 1730 * Otherwise, do per-cache line flush. Use the mfence 1731 * instruction to insure that previous stores are 1732 * included in the write-back. The processor 1733 * propagates flush to other processors in the cache 1734 * coherence domain. 1735 */ 1736 mfence(); 1737 for (; sva < eva; sva += cpu_clflush_line_size) 1738 clflush(sva); 1739 mfence(); 1740 } else { 1741 1742 /* 1743 * No targeted cache flush methods are supported by CPU, 1744 * or the supplied range is bigger than 2MB. 1745 * Globally invalidate cache. 1746 */ 1747 pmap_invalidate_cache(); 1748 } 1749} 1750 1751/* 1752 * Remove the specified set of pages from the data and instruction caches. 1753 * 1754 * In contrast to pmap_invalidate_cache_range(), this function does not 1755 * rely on the CPU's self-snoop feature, because it is intended for use 1756 * when moving pages into a different cache domain. 1757 */ 1758void 1759pmap_invalidate_cache_pages(vm_page_t *pages, int count) 1760{ 1761 vm_offset_t daddr, eva; 1762 int i; 1763 1764 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE || 1765 (cpu_feature & CPUID_CLFSH) == 0) 1766 pmap_invalidate_cache(); 1767 else { 1768 mfence(); 1769 for (i = 0; i < count; i++) { 1770 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i])); 1771 eva = daddr + PAGE_SIZE; 1772 for (; daddr < eva; daddr += cpu_clflush_line_size) 1773 clflush(daddr); 1774 } 1775 mfence(); 1776 } 1777} 1778 1779/* 1780 * Routine: pmap_extract 1781 * Function: 1782 * Extract the physical page address associated 1783 * with the given map/virtual_address pair. 1784 */ 1785vm_paddr_t 1786pmap_extract(pmap_t pmap, vm_offset_t va) 1787{ 1788 pdp_entry_t *pdpe; 1789 pd_entry_t *pde; 1790 pt_entry_t *pte, PG_V; 1791 vm_paddr_t pa; 1792 1793 pa = 0; 1794 PG_V = pmap_valid_bit(pmap); 1795 PMAP_LOCK(pmap); 1796 pdpe = pmap_pdpe(pmap, va); 1797 if (pdpe != NULL && (*pdpe & PG_V) != 0) { 1798 if ((*pdpe & PG_PS) != 0) 1799 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK); 1800 else { 1801 pde = pmap_pdpe_to_pde(pdpe, va); 1802 if ((*pde & PG_V) != 0) { 1803 if ((*pde & PG_PS) != 0) { 1804 pa = (*pde & PG_PS_FRAME) | 1805 (va & PDRMASK); 1806 } else { 1807 pte = pmap_pde_to_pte(pde, va); 1808 pa = (*pte & PG_FRAME) | 1809 (va & PAGE_MASK); 1810 } 1811 } 1812 } 1813 } 1814 PMAP_UNLOCK(pmap); 1815 return (pa); 1816} 1817 1818/* 1819 * Routine: pmap_extract_and_hold 1820 * Function: 1821 * Atomically extract and hold the physical page 1822 * with the given pmap and virtual address pair 1823 * if that mapping permits the given protection. 1824 */ 1825vm_page_t 1826pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1827{ 1828 pd_entry_t pde, *pdep; 1829 pt_entry_t pte, PG_RW, PG_V; 1830 vm_paddr_t pa; 1831 vm_page_t m; 1832 1833 pa = 0; 1834 m = NULL; 1835 PG_RW = pmap_rw_bit(pmap); 1836 PG_V = pmap_valid_bit(pmap); 1837 PMAP_LOCK(pmap); 1838retry: 1839 pdep = pmap_pde(pmap, va); 1840 if (pdep != NULL && (pde = *pdep)) { 1841 if (pde & PG_PS) { 1842 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1843 if (vm_page_pa_tryrelock(pmap, (pde & 1844 PG_PS_FRAME) | (va & PDRMASK), &pa)) 1845 goto retry; 1846 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1847 (va & PDRMASK)); 1848 vm_page_hold(m); 1849 } 1850 } else { 1851 pte = *pmap_pde_to_pte(pdep, va); 1852 if ((pte & PG_V) && 1853 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1854 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, 1855 &pa)) 1856 goto retry; 1857 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1858 vm_page_hold(m); 1859 } 1860 } 1861 } 1862 PA_UNLOCK_COND(pa); 1863 PMAP_UNLOCK(pmap); 1864 return (m); 1865} 1866 1867vm_paddr_t 1868pmap_kextract(vm_offset_t va) 1869{ 1870 pd_entry_t pde; 1871 vm_paddr_t pa; 1872 1873 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) { 1874 pa = DMAP_TO_PHYS(va); 1875 } else { 1876 pde = *vtopde(va); 1877 if (pde & PG_PS) { 1878 pa = (pde & PG_PS_FRAME) | (va & PDRMASK); 1879 } else { 1880 /* 1881 * Beware of a concurrent promotion that changes the 1882 * PDE at this point! For example, vtopte() must not 1883 * be used to access the PTE because it would use the 1884 * new PDE. It is, however, safe to use the old PDE 1885 * because the page table page is preserved by the 1886 * promotion. 1887 */ 1888 pa = *pmap_pde_to_pte(&pde, va); 1889 pa = (pa & PG_FRAME) | (va & PAGE_MASK); 1890 } 1891 } 1892 return (pa); 1893} 1894 1895/*************************************************** 1896 * Low level mapping routines..... 1897 ***************************************************/ 1898 1899/* 1900 * Add a wired page to the kva. 1901 * Note: not SMP coherent. 1902 */ 1903PMAP_INLINE void 1904pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1905{ 1906 pt_entry_t *pte; 1907 1908 pte = vtopte(va); 1909 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G); 1910} 1911 1912static __inline void 1913pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1914{ 1915 pt_entry_t *pte; 1916 int cache_bits; 1917 1918 pte = vtopte(va); 1919 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0); 1920 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G | cache_bits); 1921} 1922 1923/* 1924 * Remove a page from the kernel pagetables. 1925 * Note: not SMP coherent. 1926 */ 1927PMAP_INLINE void 1928pmap_kremove(vm_offset_t va) 1929{ 1930 pt_entry_t *pte; 1931 1932 pte = vtopte(va); 1933 pte_clear(pte); 1934} 1935 1936/* 1937 * Used to map a range of physical addresses into kernel 1938 * virtual address space. 1939 * 1940 * The value passed in '*virt' is a suggested virtual address for 1941 * the mapping. Architectures which can support a direct-mapped 1942 * physical to virtual region can return the appropriate address 1943 * within that region, leaving '*virt' unchanged. Other 1944 * architectures should map the pages starting at '*virt' and 1945 * update '*virt' with the first usable address after the mapped 1946 * region. 1947 */ 1948vm_offset_t 1949pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1950{ 1951 return PHYS_TO_DMAP(start); 1952} 1953 1954 1955/* 1956 * Add a list of wired pages to the kva 1957 * this routine is only used for temporary 1958 * kernel mappings that do not need to have 1959 * page modification or references recorded. 1960 * Note that old mappings are simply written 1961 * over. The page *must* be wired. 1962 * Note: SMP coherent. Uses a ranged shootdown IPI. 1963 */ 1964void 1965pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1966{ 1967 pt_entry_t *endpte, oldpte, pa, *pte; 1968 vm_page_t m; 1969 int cache_bits; 1970 1971 oldpte = 0; 1972 pte = vtopte(sva); 1973 endpte = pte + count; 1974 while (pte < endpte) { 1975 m = *ma++; 1976 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0); 1977 pa = VM_PAGE_TO_PHYS(m) | cache_bits; 1978 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) { 1979 oldpte |= *pte; 1980 pte_store(pte, pa | X86_PG_G | X86_PG_RW | X86_PG_V); 1981 } 1982 pte++; 1983 } 1984 if (__predict_false((oldpte & X86_PG_V) != 0)) 1985 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1986 PAGE_SIZE); 1987} 1988 1989/* 1990 * This routine tears out page mappings from the 1991 * kernel -- it is meant only for temporary mappings. 1992 * Note: SMP coherent. Uses a ranged shootdown IPI. 1993 */ 1994void 1995pmap_qremove(vm_offset_t sva, int count) 1996{ 1997 vm_offset_t va; 1998 1999 va = sva; 2000 while (count-- > 0) { 2001 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va)); 2002 pmap_kremove(va); 2003 va += PAGE_SIZE; 2004 } 2005 pmap_invalidate_range(kernel_pmap, sva, va); 2006} 2007 2008/*************************************************** 2009 * Page table page management routines..... 2010 ***************************************************/ 2011static __inline void 2012pmap_free_zero_pages(struct spglist *free) 2013{ 2014 vm_page_t m; 2015 2016 while ((m = SLIST_FIRST(free)) != NULL) { 2017 SLIST_REMOVE_HEAD(free, plinks.s.ss); 2018 /* Preserve the page's PG_ZERO setting. */ 2019 vm_page_free_toq(m); 2020 } 2021} 2022 2023/* 2024 * Schedule the specified unused page table page to be freed. Specifically, 2025 * add the page to the specified list of pages that will be released to the 2026 * physical memory manager after the TLB has been updated. 2027 */ 2028static __inline void 2029pmap_add_delayed_free_list(vm_page_t m, struct spglist *free, 2030 boolean_t set_PG_ZERO) 2031{ 2032 2033 if (set_PG_ZERO) 2034 m->flags |= PG_ZERO; 2035 else 2036 m->flags &= ~PG_ZERO; 2037 SLIST_INSERT_HEAD(free, m, plinks.s.ss); 2038} 2039 2040/* 2041 * Inserts the specified page table page into the specified pmap's collection 2042 * of idle page table pages. Each of a pmap's page table pages is responsible 2043 * for mapping a distinct range of virtual addresses. The pmap's collection is 2044 * ordered by this virtual address range. 2045 */ 2046static __inline int 2047pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 2048{ 2049 2050 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2051 return (vm_radix_insert(&pmap->pm_root, mpte)); 2052} 2053 2054/* 2055 * Looks for a page table page mapping the specified virtual address in the 2056 * specified pmap's collection of idle page table pages. Returns NULL if there 2057 * is no page table page corresponding to the specified virtual address. 2058 */ 2059static __inline vm_page_t 2060pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va) 2061{ 2062 2063 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2064 return (vm_radix_lookup(&pmap->pm_root, pmap_pde_pindex(va))); 2065} 2066 2067/* 2068 * Removes the specified page table page from the specified pmap's collection 2069 * of idle page table pages. The specified page table page must be a member of 2070 * the pmap's collection. 2071 */ 2072static __inline void 2073pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte) 2074{ 2075 2076 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2077 vm_radix_remove(&pmap->pm_root, mpte->pindex); 2078} 2079 2080/* 2081 * Decrements a page table page's wire count, which is used to record the 2082 * number of valid page table entries within the page. If the wire count 2083 * drops to zero, then the page table page is unmapped. Returns TRUE if the 2084 * page table page was unmapped and FALSE otherwise. 2085 */ 2086static inline boolean_t 2087pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free) 2088{ 2089 2090 --m->wire_count; 2091 if (m->wire_count == 0) { 2092 _pmap_unwire_ptp(pmap, va, m, free); 2093 return (TRUE); 2094 } else 2095 return (FALSE); 2096} 2097 2098static void 2099_pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free) 2100{ 2101 2102 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2103 /* 2104 * unmap the page table page 2105 */ 2106 if (m->pindex >= (NUPDE + NUPDPE)) { 2107 /* PDP page */ 2108 pml4_entry_t *pml4; 2109 pml4 = pmap_pml4e(pmap, va); 2110 *pml4 = 0; 2111 } else if (m->pindex >= NUPDE) { 2112 /* PD page */ 2113 pdp_entry_t *pdp; 2114 pdp = pmap_pdpe(pmap, va); 2115 *pdp = 0; 2116 } else { 2117 /* PTE page */ 2118 pd_entry_t *pd; 2119 pd = pmap_pde(pmap, va); 2120 *pd = 0; 2121 } 2122 pmap_resident_count_dec(pmap, 1); 2123 if (m->pindex < NUPDE) { 2124 /* We just released a PT, unhold the matching PD */ 2125 vm_page_t pdpg; 2126 2127 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME); 2128 pmap_unwire_ptp(pmap, va, pdpg, free); 2129 } 2130 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) { 2131 /* We just released a PD, unhold the matching PDP */ 2132 vm_page_t pdppg; 2133 2134 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME); 2135 pmap_unwire_ptp(pmap, va, pdppg, free); 2136 } 2137 2138 /* 2139 * This is a release store so that the ordinary store unmapping 2140 * the page table page is globally performed before TLB shoot- 2141 * down is begun. 2142 */ 2143 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 2144 2145 /* 2146 * Put page on a list so that it is released after 2147 * *ALL* TLB shootdown is done 2148 */ 2149 pmap_add_delayed_free_list(m, free, TRUE); 2150} 2151 2152/* 2153 * After removing a page table entry, this routine is used to 2154 * conditionally free the page, and manage the hold/wire counts. 2155 */ 2156static int 2157pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde, 2158 struct spglist *free) 2159{ 2160 vm_page_t mpte; 2161 2162 if (va >= VM_MAXUSER_ADDRESS) 2163 return (0); 2164 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0")); 2165 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 2166 return (pmap_unwire_ptp(pmap, va, mpte, free)); 2167} 2168 2169void 2170pmap_pinit0(pmap_t pmap) 2171{ 2172 2173 PMAP_LOCK_INIT(pmap); 2174 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys); 2175 pmap->pm_cr3 = KPML4phys; 2176 pmap->pm_root.rt_root = 0; 2177 CPU_ZERO(&pmap->pm_active); 2178 CPU_ZERO(&pmap->pm_save); 2179 PCPU_SET(curpmap, pmap); 2180 TAILQ_INIT(&pmap->pm_pvchunk); 2181 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 2182 pmap->pm_pcid = pmap_pcid_enabled ? 0 : -1; 2183 pmap->pm_flags = pmap_flags; 2184} 2185 2186/* 2187 * Initialize a preallocated and zeroed pmap structure, 2188 * such as one in a vmspace structure. 2189 */ 2190int 2191pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags) 2192{ 2193 vm_page_t pml4pg; 2194 vm_paddr_t pml4phys; 2195 int i; 2196 2197 /* 2198 * allocate the page directory page 2199 */ 2200 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2201 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) 2202 VM_WAIT; 2203 2204 pml4phys = VM_PAGE_TO_PHYS(pml4pg); 2205 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys); 2206 pmap->pm_pcid = -1; 2207 pmap->pm_cr3 = ~0; /* initialize to an invalid value */ 2208 2209 if ((pml4pg->flags & PG_ZERO) == 0) 2210 pagezero(pmap->pm_pml4); 2211 2212 /* 2213 * Do not install the host kernel mappings in the nested page 2214 * tables. These mappings are meaningless in the guest physical 2215 * address space. 2216 */ 2217 if ((pmap->pm_type = pm_type) == PT_X86) { 2218 pmap->pm_cr3 = pml4phys; 2219 2220 /* Wire in kernel global address entries. */ 2221 for (i = 0; i < NKPML4E; i++) { 2222 pmap->pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | 2223 X86_PG_RW | X86_PG_V | PG_U; 2224 } 2225 for (i = 0; i < ndmpdpphys; i++) { 2226 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | 2227 X86_PG_RW | X86_PG_V | PG_U; 2228 } 2229 2230 /* install self-referential address mapping entry(s) */ 2231 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | 2232 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M; 2233 2234 if (pmap_pcid_enabled) { 2235 pmap->pm_pcid = alloc_unr(&pcid_unr); 2236 if (pmap->pm_pcid != -1) 2237 pmap->pm_cr3 |= pmap->pm_pcid; 2238 } 2239 } 2240 2241 pmap->pm_root.rt_root = 0; 2242 CPU_ZERO(&pmap->pm_active); 2243 TAILQ_INIT(&pmap->pm_pvchunk); 2244 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 2245 pmap->pm_flags = flags; 2246 pmap->pm_eptgen = 0; 2247 CPU_ZERO(&pmap->pm_save); 2248 2249 return (1); 2250} 2251 2252int 2253pmap_pinit(pmap_t pmap) 2254{ 2255 2256 return (pmap_pinit_type(pmap, PT_X86, pmap_flags)); 2257} 2258 2259/* 2260 * This routine is called if the desired page table page does not exist. 2261 * 2262 * If page table page allocation fails, this routine may sleep before 2263 * returning NULL. It sleeps only if a lock pointer was given. 2264 * 2265 * Note: If a page allocation fails at page table level two or three, 2266 * one or two pages may be held during the wait, only to be released 2267 * afterwards. This conservative approach is easily argued to avoid 2268 * race conditions. 2269 */ 2270static vm_page_t 2271_pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp) 2272{ 2273 vm_page_t m, pdppg, pdpg; 2274 pt_entry_t PG_A, PG_M, PG_RW, PG_V; 2275 2276 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2277 2278 PG_A = pmap_accessed_bit(pmap); 2279 PG_M = pmap_modified_bit(pmap); 2280 PG_V = pmap_valid_bit(pmap); 2281 PG_RW = pmap_rw_bit(pmap); 2282 2283 /* 2284 * Allocate a page table page. 2285 */ 2286 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 2287 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 2288 if (lockp != NULL) { 2289 RELEASE_PV_LIST_LOCK(lockp); 2290 PMAP_UNLOCK(pmap); 2291 rw_runlock(&pvh_global_lock); 2292 VM_WAIT; 2293 rw_rlock(&pvh_global_lock); 2294 PMAP_LOCK(pmap); 2295 } 2296 2297 /* 2298 * Indicate the need to retry. While waiting, the page table 2299 * page may have been allocated. 2300 */ 2301 return (NULL); 2302 } 2303 if ((m->flags & PG_ZERO) == 0) 2304 pmap_zero_page(m); 2305 2306 /* 2307 * Map the pagetable page into the process address space, if 2308 * it isn't already there. 2309 */ 2310 2311 if (ptepindex >= (NUPDE + NUPDPE)) { 2312 pml4_entry_t *pml4; 2313 vm_pindex_t pml4index; 2314 2315 /* Wire up a new PDPE page */ 2316 pml4index = ptepindex - (NUPDE + NUPDPE); 2317 pml4 = &pmap->pm_pml4[pml4index]; 2318 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M; 2319 2320 } else if (ptepindex >= NUPDE) { 2321 vm_pindex_t pml4index; 2322 vm_pindex_t pdpindex; 2323 pml4_entry_t *pml4; 2324 pdp_entry_t *pdp; 2325 2326 /* Wire up a new PDE page */ 2327 pdpindex = ptepindex - NUPDE; 2328 pml4index = pdpindex >> NPML4EPGSHIFT; 2329 2330 pml4 = &pmap->pm_pml4[pml4index]; 2331 if ((*pml4 & PG_V) == 0) { 2332 /* Have to allocate a new pdp, recurse */ 2333 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index, 2334 lockp) == NULL) { 2335 --m->wire_count; 2336 atomic_subtract_int(&cnt.v_wire_count, 1); 2337 vm_page_free_zero(m); 2338 return (NULL); 2339 } 2340 } else { 2341 /* Add reference to pdp page */ 2342 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME); 2343 pdppg->wire_count++; 2344 } 2345 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME); 2346 2347 /* Now find the pdp page */ 2348 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)]; 2349 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M; 2350 2351 } else { 2352 vm_pindex_t pml4index; 2353 vm_pindex_t pdpindex; 2354 pml4_entry_t *pml4; 2355 pdp_entry_t *pdp; 2356 pd_entry_t *pd; 2357 2358 /* Wire up a new PTE page */ 2359 pdpindex = ptepindex >> NPDPEPGSHIFT; 2360 pml4index = pdpindex >> NPML4EPGSHIFT; 2361 2362 /* First, find the pdp and check that its valid. */ 2363 pml4 = &pmap->pm_pml4[pml4index]; 2364 if ((*pml4 & PG_V) == 0) { 2365 /* Have to allocate a new pd, recurse */ 2366 if (_pmap_allocpte(pmap, NUPDE + pdpindex, 2367 lockp) == NULL) { 2368 --m->wire_count; 2369 atomic_subtract_int(&cnt.v_wire_count, 1); 2370 vm_page_free_zero(m); 2371 return (NULL); 2372 } 2373 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME); 2374 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)]; 2375 } else { 2376 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME); 2377 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)]; 2378 if ((*pdp & PG_V) == 0) { 2379 /* Have to allocate a new pd, recurse */ 2380 if (_pmap_allocpte(pmap, NUPDE + pdpindex, 2381 lockp) == NULL) { 2382 --m->wire_count; 2383 atomic_subtract_int(&cnt.v_wire_count, 2384 1); 2385 vm_page_free_zero(m); 2386 return (NULL); 2387 } 2388 } else { 2389 /* Add reference to the pd page */ 2390 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME); 2391 pdpg->wire_count++; 2392 } 2393 } 2394 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME); 2395 2396 /* Now we know where the page directory page is */ 2397 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)]; 2398 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M; 2399 } 2400 2401 pmap_resident_count_inc(pmap, 1); 2402 2403 return (m); 2404} 2405 2406static vm_page_t 2407pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp) 2408{ 2409 vm_pindex_t pdpindex, ptepindex; 2410 pdp_entry_t *pdpe, PG_V; 2411 vm_page_t pdpg; 2412 2413 PG_V = pmap_valid_bit(pmap); 2414 2415retry: 2416 pdpe = pmap_pdpe(pmap, va); 2417 if (pdpe != NULL && (*pdpe & PG_V) != 0) { 2418 /* Add a reference to the pd page. */ 2419 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME); 2420 pdpg->wire_count++; 2421 } else { 2422 /* Allocate a pd page. */ 2423 ptepindex = pmap_pde_pindex(va); 2424 pdpindex = ptepindex >> NPDPEPGSHIFT; 2425 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp); 2426 if (pdpg == NULL && lockp != NULL) 2427 goto retry; 2428 } 2429 return (pdpg); 2430} 2431 2432static vm_page_t 2433pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp) 2434{ 2435 vm_pindex_t ptepindex; 2436 pd_entry_t *pd, PG_V; 2437 vm_page_t m; 2438 2439 PG_V = pmap_valid_bit(pmap); 2440 2441 /* 2442 * Calculate pagetable page index 2443 */ 2444 ptepindex = pmap_pde_pindex(va); 2445retry: 2446 /* 2447 * Get the page directory entry 2448 */ 2449 pd = pmap_pde(pmap, va); 2450 2451 /* 2452 * This supports switching from a 2MB page to a 2453 * normal 4K page. 2454 */ 2455 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) { 2456 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) { 2457 /* 2458 * Invalidation of the 2MB page mapping may have caused 2459 * the deallocation of the underlying PD page. 2460 */ 2461 pd = NULL; 2462 } 2463 } 2464 2465 /* 2466 * If the page table page is mapped, we just increment the 2467 * hold count, and activate it. 2468 */ 2469 if (pd != NULL && (*pd & PG_V) != 0) { 2470 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME); 2471 m->wire_count++; 2472 } else { 2473 /* 2474 * Here if the pte page isn't mapped, or if it has been 2475 * deallocated. 2476 */ 2477 m = _pmap_allocpte(pmap, ptepindex, lockp); 2478 if (m == NULL && lockp != NULL) 2479 goto retry; 2480 } 2481 return (m); 2482} 2483 2484 2485/*************************************************** 2486 * Pmap allocation/deallocation routines. 2487 ***************************************************/ 2488 2489/* 2490 * Release any resources held by the given physical map. 2491 * Called when a pmap initialized by pmap_pinit is being released. 2492 * Should only be called if the map contains no valid mappings. 2493 */ 2494void 2495pmap_release(pmap_t pmap) 2496{ 2497 vm_page_t m; 2498 int i; 2499 2500 KASSERT(pmap->pm_stats.resident_count == 0, 2501 ("pmap_release: pmap resident count %ld != 0", 2502 pmap->pm_stats.resident_count)); 2503 KASSERT(vm_radix_is_empty(&pmap->pm_root), 2504 ("pmap_release: pmap has reserved page table page(s)")); 2505 2506 if (pmap_pcid_enabled) { 2507 /* 2508 * Invalidate any left TLB entries, to allow the reuse 2509 * of the pcid. 2510 */ 2511 pmap_invalidate_all(pmap); 2512 } 2513 2514 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4)); 2515 2516 for (i = 0; i < NKPML4E; i++) /* KVA */ 2517 pmap->pm_pml4[KPML4BASE + i] = 0; 2518 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */ 2519 pmap->pm_pml4[DMPML4I + i] = 0; 2520 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */ 2521 2522 m->wire_count--; 2523 atomic_subtract_int(&cnt.v_wire_count, 1); 2524 vm_page_free_zero(m); 2525 if (pmap->pm_pcid != -1) 2526 free_unr(&pcid_unr, pmap->pm_pcid); 2527} 2528 2529static int 2530kvm_size(SYSCTL_HANDLER_ARGS) 2531{ 2532 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS; 2533 2534 return sysctl_handle_long(oidp, &ksize, 0, req); 2535} 2536SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 2537 0, 0, kvm_size, "LU", "Size of KVM"); 2538 2539static int 2540kvm_free(SYSCTL_HANDLER_ARGS) 2541{ 2542 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 2543 2544 return sysctl_handle_long(oidp, &kfree, 0, req); 2545} 2546SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 2547 0, 0, kvm_free, "LU", "Amount of KVM free"); 2548 2549/* 2550 * grow the number of kernel page table entries, if needed 2551 */ 2552void 2553pmap_growkernel(vm_offset_t addr) 2554{ 2555 vm_paddr_t paddr; 2556 vm_page_t nkpg; 2557 pd_entry_t *pde, newpdir; 2558 pdp_entry_t *pdpe; 2559 2560 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 2561 2562 /* 2563 * Return if "addr" is within the range of kernel page table pages 2564 * that were preallocated during pmap bootstrap. Moreover, leave 2565 * "kernel_vm_end" and the kernel page table as they were. 2566 * 2567 * The correctness of this action is based on the following 2568 * argument: vm_map_findspace() allocates contiguous ranges of the 2569 * kernel virtual address space. It calls this function if a range 2570 * ends after "kernel_vm_end". If the kernel is mapped between 2571 * "kernel_vm_end" and "addr", then the range cannot begin at 2572 * "kernel_vm_end". In fact, its beginning address cannot be less 2573 * than the kernel. Thus, there is no immediate need to allocate 2574 * any new kernel page table pages between "kernel_vm_end" and 2575 * "KERNBASE". 2576 */ 2577 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR) 2578 return; 2579 2580 addr = roundup2(addr, NBPDR); 2581 if (addr - 1 >= kernel_map->max_offset) 2582 addr = kernel_map->max_offset; 2583 while (kernel_vm_end < addr) { 2584 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end); 2585 if ((*pdpe & X86_PG_V) == 0) { 2586 /* We need a new PDP entry */ 2587 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT, 2588 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 2589 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 2590 if (nkpg == NULL) 2591 panic("pmap_growkernel: no memory to grow kernel"); 2592 if ((nkpg->flags & PG_ZERO) == 0) 2593 pmap_zero_page(nkpg); 2594 paddr = VM_PAGE_TO_PHYS(nkpg); 2595 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW | 2596 X86_PG_A | X86_PG_M); 2597 continue; /* try again */ 2598 } 2599 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end); 2600 if ((*pde & X86_PG_V) != 0) { 2601 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2602 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2603 kernel_vm_end = kernel_map->max_offset; 2604 break; 2605 } 2606 continue; 2607 } 2608 2609 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end), 2610 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2611 VM_ALLOC_ZERO); 2612 if (nkpg == NULL) 2613 panic("pmap_growkernel: no memory to grow kernel"); 2614 if ((nkpg->flags & PG_ZERO) == 0) 2615 pmap_zero_page(nkpg); 2616 paddr = VM_PAGE_TO_PHYS(nkpg); 2617 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M; 2618 pde_store(pde, newpdir); 2619 2620 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2621 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2622 kernel_vm_end = kernel_map->max_offset; 2623 break; 2624 } 2625 } 2626} 2627 2628 2629/*************************************************** 2630 * page management routines. 2631 ***************************************************/ 2632 2633CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 2634CTASSERT(_NPCM == 3); 2635CTASSERT(_NPCPV == 168); 2636 2637static __inline struct pv_chunk * 2638pv_to_chunk(pv_entry_t pv) 2639{ 2640 2641 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 2642} 2643 2644#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 2645 2646#define PC_FREE0 0xfffffffffffffffful 2647#define PC_FREE1 0xfffffffffffffffful 2648#define PC_FREE2 0x000000fffffffffful 2649 2650static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 }; 2651 2652#ifdef PV_STATS 2653static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 2654 2655SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 2656 "Current number of pv entry chunks"); 2657SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 2658 "Current number of pv entry chunks allocated"); 2659SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 2660 "Current number of pv entry chunks frees"); 2661SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 2662 "Number of times tried to get a chunk page but failed."); 2663 2664static long pv_entry_frees, pv_entry_allocs, pv_entry_count; 2665static int pv_entry_spare; 2666 2667SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 2668 "Current number of pv entry frees"); 2669SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 2670 "Current number of pv entry allocs"); 2671SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 2672 "Current number of pv entries"); 2673SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 2674 "Current number of spare pv entries"); 2675#endif 2676 2677/* 2678 * We are in a serious low memory condition. Resort to 2679 * drastic measures to free some pages so we can allocate 2680 * another pv entry chunk. 2681 * 2682 * Returns NULL if PV entries were reclaimed from the specified pmap. 2683 * 2684 * We do not, however, unmap 2mpages because subsequent accesses will 2685 * allocate per-page pv entries until repromotion occurs, thereby 2686 * exacerbating the shortage of free pv entries. 2687 */ 2688static vm_page_t 2689reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp) 2690{ 2691 struct pch new_tail; 2692 struct pv_chunk *pc; 2693 struct md_page *pvh; 2694 pd_entry_t *pde; 2695 pmap_t pmap; 2696 pt_entry_t *pte, tpte; 2697 pt_entry_t PG_G, PG_A, PG_M, PG_RW; 2698 pv_entry_t pv; 2699 vm_offset_t va; 2700 vm_page_t m, m_pc; 2701 struct spglist free; 2702 uint64_t inuse; 2703 int bit, field, freed; 2704 2705 rw_assert(&pvh_global_lock, RA_LOCKED); 2706 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 2707 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL")); 2708 pmap = NULL; 2709 m_pc = NULL; 2710 PG_G = PG_A = PG_M = PG_RW = 0; 2711 SLIST_INIT(&free); 2712 TAILQ_INIT(&new_tail); 2713 mtx_lock(&pv_chunks_mutex); 2714 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) { 2715 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2716 mtx_unlock(&pv_chunks_mutex); 2717 if (pmap != pc->pc_pmap) { 2718 if (pmap != NULL) { 2719 pmap_invalidate_all(pmap); 2720 if (pmap != locked_pmap) 2721 PMAP_UNLOCK(pmap); 2722 } 2723 pmap = pc->pc_pmap; 2724 /* Avoid deadlock and lock recursion. */ 2725 if (pmap > locked_pmap) { 2726 RELEASE_PV_LIST_LOCK(lockp); 2727 PMAP_LOCK(pmap); 2728 } else if (pmap != locked_pmap && 2729 !PMAP_TRYLOCK(pmap)) { 2730 pmap = NULL; 2731 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru); 2732 mtx_lock(&pv_chunks_mutex); 2733 continue; 2734 } 2735 PG_G = pmap_global_bit(pmap); 2736 PG_A = pmap_accessed_bit(pmap); 2737 PG_M = pmap_modified_bit(pmap); 2738 PG_RW = pmap_rw_bit(pmap); 2739 } 2740 2741 /* 2742 * Destroy every non-wired, 4 KB page mapping in the chunk. 2743 */ 2744 freed = 0; 2745 for (field = 0; field < _NPCM; field++) { 2746 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2747 inuse != 0; inuse &= ~(1UL << bit)) { 2748 bit = bsfq(inuse); 2749 pv = &pc->pc_pventry[field * 64 + bit]; 2750 va = pv->pv_va; 2751 pde = pmap_pde(pmap, va); 2752 if ((*pde & PG_PS) != 0) 2753 continue; 2754 pte = pmap_pde_to_pte(pde, va); 2755 if ((*pte & PG_W) != 0) 2756 continue; 2757 tpte = pte_load_clear(pte); 2758 if ((tpte & PG_G) != 0) 2759 pmap_invalidate_page(pmap, va); 2760 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 2761 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2762 vm_page_dirty(m); 2763 if ((tpte & PG_A) != 0) 2764 vm_page_aflag_set(m, PGA_REFERENCED); 2765 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 2766 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2767 m->md.pv_gen++; 2768 if (TAILQ_EMPTY(&m->md.pv_list) && 2769 (m->flags & PG_FICTITIOUS) == 0) { 2770 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2771 if (TAILQ_EMPTY(&pvh->pv_list)) { 2772 vm_page_aflag_clear(m, 2773 PGA_WRITEABLE); 2774 } 2775 } 2776 pc->pc_map[field] |= 1UL << bit; 2777 pmap_unuse_pt(pmap, va, *pde, &free); 2778 freed++; 2779 } 2780 } 2781 if (freed == 0) { 2782 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru); 2783 mtx_lock(&pv_chunks_mutex); 2784 continue; 2785 } 2786 /* Every freed mapping is for a 4 KB page. */ 2787 pmap_resident_count_dec(pmap, freed); 2788 PV_STAT(atomic_add_long(&pv_entry_frees, freed)); 2789 PV_STAT(atomic_add_int(&pv_entry_spare, freed)); 2790 PV_STAT(atomic_subtract_long(&pv_entry_count, freed)); 2791 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2792 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 && 2793 pc->pc_map[2] == PC_FREE2) { 2794 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV)); 2795 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1)); 2796 PV_STAT(atomic_add_int(&pc_chunk_frees, 1)); 2797 /* Entire chunk is free; return it. */ 2798 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc)); 2799 dump_drop_page(m_pc->phys_addr); 2800 mtx_lock(&pv_chunks_mutex); 2801 break; 2802 } 2803 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2804 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru); 2805 mtx_lock(&pv_chunks_mutex); 2806 /* One freed pv entry in locked_pmap is sufficient. */ 2807 if (pmap == locked_pmap) 2808 break; 2809 } 2810 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru); 2811 mtx_unlock(&pv_chunks_mutex); 2812 if (pmap != NULL) { 2813 pmap_invalidate_all(pmap); 2814 if (pmap != locked_pmap) 2815 PMAP_UNLOCK(pmap); 2816 } 2817 if (m_pc == NULL && !SLIST_EMPTY(&free)) { 2818 m_pc = SLIST_FIRST(&free); 2819 SLIST_REMOVE_HEAD(&free, plinks.s.ss); 2820 /* Recycle a freed page table page. */ 2821 m_pc->wire_count = 1; 2822 atomic_add_int(&cnt.v_wire_count, 1); 2823 } 2824 pmap_free_zero_pages(&free); 2825 return (m_pc); 2826} 2827 2828/* 2829 * free the pv_entry back to the free list 2830 */ 2831static void 2832free_pv_entry(pmap_t pmap, pv_entry_t pv) 2833{ 2834 struct pv_chunk *pc; 2835 int idx, field, bit; 2836 2837 rw_assert(&pvh_global_lock, RA_LOCKED); 2838 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2839 PV_STAT(atomic_add_long(&pv_entry_frees, 1)); 2840 PV_STAT(atomic_add_int(&pv_entry_spare, 1)); 2841 PV_STAT(atomic_subtract_long(&pv_entry_count, 1)); 2842 pc = pv_to_chunk(pv); 2843 idx = pv - &pc->pc_pventry[0]; 2844 field = idx / 64; 2845 bit = idx % 64; 2846 pc->pc_map[field] |= 1ul << bit; 2847 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 || 2848 pc->pc_map[2] != PC_FREE2) { 2849 /* 98% of the time, pc is already at the head of the list. */ 2850 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) { 2851 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2852 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2853 } 2854 return; 2855 } 2856 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2857 free_pv_chunk(pc); 2858} 2859 2860static void 2861free_pv_chunk(struct pv_chunk *pc) 2862{ 2863 vm_page_t m; 2864 2865 mtx_lock(&pv_chunks_mutex); 2866 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2867 mtx_unlock(&pv_chunks_mutex); 2868 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV)); 2869 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1)); 2870 PV_STAT(atomic_add_int(&pc_chunk_frees, 1)); 2871 /* entire chunk is free, return it */ 2872 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc)); 2873 dump_drop_page(m->phys_addr); 2874 vm_page_unwire(m, 0); 2875 vm_page_free(m); 2876} 2877 2878/* 2879 * Returns a new PV entry, allocating a new PV chunk from the system when 2880 * needed. If this PV chunk allocation fails and a PV list lock pointer was 2881 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is 2882 * returned. 2883 * 2884 * The given PV list lock may be released. 2885 */ 2886static pv_entry_t 2887get_pv_entry(pmap_t pmap, struct rwlock **lockp) 2888{ 2889 int bit, field; 2890 pv_entry_t pv; 2891 struct pv_chunk *pc; 2892 vm_page_t m; 2893 2894 rw_assert(&pvh_global_lock, RA_LOCKED); 2895 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2896 PV_STAT(atomic_add_long(&pv_entry_allocs, 1)); 2897retry: 2898 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2899 if (pc != NULL) { 2900 for (field = 0; field < _NPCM; field++) { 2901 if (pc->pc_map[field]) { 2902 bit = bsfq(pc->pc_map[field]); 2903 break; 2904 } 2905 } 2906 if (field < _NPCM) { 2907 pv = &pc->pc_pventry[field * 64 + bit]; 2908 pc->pc_map[field] &= ~(1ul << bit); 2909 /* If this was the last item, move it to tail */ 2910 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && 2911 pc->pc_map[2] == 0) { 2912 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2913 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, 2914 pc_list); 2915 } 2916 PV_STAT(atomic_add_long(&pv_entry_count, 1)); 2917 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1)); 2918 return (pv); 2919 } 2920 } 2921 /* No free items, allocate another chunk */ 2922 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 2923 VM_ALLOC_WIRED); 2924 if (m == NULL) { 2925 if (lockp == NULL) { 2926 PV_STAT(pc_chunk_tryfail++); 2927 return (NULL); 2928 } 2929 m = reclaim_pv_chunk(pmap, lockp); 2930 if (m == NULL) 2931 goto retry; 2932 } 2933 PV_STAT(atomic_add_int(&pc_chunk_count, 1)); 2934 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1)); 2935 dump_add_page(m->phys_addr); 2936 pc = (void *)PHYS_TO_DMAP(m->phys_addr); 2937 pc->pc_pmap = pmap; 2938 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */ 2939 pc->pc_map[1] = PC_FREE1; 2940 pc->pc_map[2] = PC_FREE2; 2941 mtx_lock(&pv_chunks_mutex); 2942 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 2943 mtx_unlock(&pv_chunks_mutex); 2944 pv = &pc->pc_pventry[0]; 2945 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2946 PV_STAT(atomic_add_long(&pv_entry_count, 1)); 2947 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1)); 2948 return (pv); 2949} 2950 2951/* 2952 * Returns the number of one bits within the given PV chunk map element. 2953 */ 2954static int 2955popcnt_pc_map_elem(uint64_t elem) 2956{ 2957 int count; 2958 2959 /* 2960 * This simple method of counting the one bits performs well because 2961 * the given element typically contains more zero bits than one bits. 2962 */ 2963 count = 0; 2964 for (; elem != 0; elem &= elem - 1) 2965 count++; 2966 return (count); 2967} 2968 2969/* 2970 * Ensure that the number of spare PV entries in the specified pmap meets or 2971 * exceeds the given count, "needed". 2972 * 2973 * The given PV list lock may be released. 2974 */ 2975static void 2976reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp) 2977{ 2978 struct pch new_tail; 2979 struct pv_chunk *pc; 2980 int avail, free; 2981 vm_page_t m; 2982 2983 rw_assert(&pvh_global_lock, RA_LOCKED); 2984 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2985 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL")); 2986 2987 /* 2988 * Newly allocated PV chunks must be stored in a private list until 2989 * the required number of PV chunks have been allocated. Otherwise, 2990 * reclaim_pv_chunk() could recycle one of these chunks. In 2991 * contrast, these chunks must be added to the pmap upon allocation. 2992 */ 2993 TAILQ_INIT(&new_tail); 2994retry: 2995 avail = 0; 2996 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) { 2997 if ((cpu_feature2 & CPUID2_POPCNT) == 0) { 2998 free = popcnt_pc_map_elem(pc->pc_map[0]); 2999 free += popcnt_pc_map_elem(pc->pc_map[1]); 3000 free += popcnt_pc_map_elem(pc->pc_map[2]); 3001 } else { 3002 free = popcntq(pc->pc_map[0]); 3003 free += popcntq(pc->pc_map[1]); 3004 free += popcntq(pc->pc_map[2]); 3005 } 3006 if (free == 0) 3007 break; 3008 avail += free; 3009 if (avail >= needed) 3010 break; 3011 } 3012 for (; avail < needed; avail += _NPCPV) { 3013 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 3014 VM_ALLOC_WIRED); 3015 if (m == NULL) { 3016 m = reclaim_pv_chunk(pmap, lockp); 3017 if (m == NULL) 3018 goto retry; 3019 } 3020 PV_STAT(atomic_add_int(&pc_chunk_count, 1)); 3021 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1)); 3022 dump_add_page(m->phys_addr); 3023 pc = (void *)PHYS_TO_DMAP(m->phys_addr); 3024 pc->pc_pmap = pmap; 3025 pc->pc_map[0] = PC_FREE0; 3026 pc->pc_map[1] = PC_FREE1; 3027 pc->pc_map[2] = PC_FREE2; 3028 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 3029 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru); 3030 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV)); 3031 } 3032 if (!TAILQ_EMPTY(&new_tail)) { 3033 mtx_lock(&pv_chunks_mutex); 3034 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru); 3035 mtx_unlock(&pv_chunks_mutex); 3036 } 3037} 3038 3039/* 3040 * First find and then remove the pv entry for the specified pmap and virtual 3041 * address from the specified pv list. Returns the pv entry if found and NULL 3042 * otherwise. This operation can be performed on pv lists for either 4KB or 3043 * 2MB page mappings. 3044 */ 3045static __inline pv_entry_t 3046pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 3047{ 3048 pv_entry_t pv; 3049 3050 rw_assert(&pvh_global_lock, RA_LOCKED); 3051 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 3052 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 3053 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 3054 pvh->pv_gen++; 3055 break; 3056 } 3057 } 3058 return (pv); 3059} 3060 3061/* 3062 * After demotion from a 2MB page mapping to 512 4KB page mappings, 3063 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv 3064 * entries for each of the 4KB page mappings. 3065 */ 3066static void 3067pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 3068 struct rwlock **lockp) 3069{ 3070 struct md_page *pvh; 3071 struct pv_chunk *pc; 3072 pv_entry_t pv; 3073 vm_offset_t va_last; 3074 vm_page_t m; 3075 int bit, field; 3076 3077 rw_assert(&pvh_global_lock, RA_LOCKED); 3078 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3079 KASSERT((pa & PDRMASK) == 0, 3080 ("pmap_pv_demote_pde: pa is not 2mpage aligned")); 3081 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 3082 3083 /* 3084 * Transfer the 2mpage's pv entry for this mapping to the first 3085 * page's pv list. Once this transfer begins, the pv list lock 3086 * must not be released until the last pv entry is reinstantiated. 3087 */ 3088 pvh = pa_to_pvh(pa); 3089 va = trunc_2mpage(va); 3090 pv = pmap_pvh_remove(pvh, pmap, va); 3091 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 3092 m = PHYS_TO_VM_PAGE(pa); 3093 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3094 m->md.pv_gen++; 3095 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 3096 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1)); 3097 va_last = va + NBPDR - PAGE_SIZE; 3098 for (;;) { 3099 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 3100 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 || 3101 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare")); 3102 for (field = 0; field < _NPCM; field++) { 3103 while (pc->pc_map[field]) { 3104 bit = bsfq(pc->pc_map[field]); 3105 pc->pc_map[field] &= ~(1ul << bit); 3106 pv = &pc->pc_pventry[field * 64 + bit]; 3107 va += PAGE_SIZE; 3108 pv->pv_va = va; 3109 m++; 3110 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3111 ("pmap_pv_demote_pde: page %p is not managed", m)); 3112 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3113 m->md.pv_gen++; 3114 if (va == va_last) 3115 goto out; 3116 } 3117 } 3118 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3119 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 3120 } 3121out: 3122 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) { 3123 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3124 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 3125 } 3126 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1)); 3127 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1)); 3128} 3129 3130/* 3131 * After promotion from 512 4KB page mappings to a single 2MB page mapping, 3132 * replace the many pv entries for the 4KB page mappings by a single pv entry 3133 * for the 2MB page mapping. 3134 */ 3135static void 3136pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 3137 struct rwlock **lockp) 3138{ 3139 struct md_page *pvh; 3140 pv_entry_t pv; 3141 vm_offset_t va_last; 3142 vm_page_t m; 3143 3144 rw_assert(&pvh_global_lock, RA_LOCKED); 3145 KASSERT((pa & PDRMASK) == 0, 3146 ("pmap_pv_promote_pde: pa is not 2mpage aligned")); 3147 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 3148 3149 /* 3150 * Transfer the first page's pv entry for this mapping to the 2mpage's 3151 * pv list. Aside from avoiding the cost of a call to get_pv_entry(), 3152 * a transfer avoids the possibility that get_pv_entry() calls 3153 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the 3154 * mappings that is being promoted. 3155 */ 3156 m = PHYS_TO_VM_PAGE(pa); 3157 va = trunc_2mpage(va); 3158 pv = pmap_pvh_remove(&m->md, pmap, va); 3159 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 3160 pvh = pa_to_pvh(pa); 3161 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 3162 pvh->pv_gen++; 3163 /* Free the remaining NPTEPG - 1 pv entries. */ 3164 va_last = va + NBPDR - PAGE_SIZE; 3165 do { 3166 m++; 3167 va += PAGE_SIZE; 3168 pmap_pvh_free(&m->md, pmap, va); 3169 } while (va < va_last); 3170} 3171 3172/* 3173 * First find and then destroy the pv entry for the specified pmap and virtual 3174 * address. This operation can be performed on pv lists for either 4KB or 2MB 3175 * page mappings. 3176 */ 3177static void 3178pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 3179{ 3180 pv_entry_t pv; 3181 3182 pv = pmap_pvh_remove(pvh, pmap, va); 3183 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 3184 free_pv_entry(pmap, pv); 3185} 3186 3187/* 3188 * Conditionally create the PV entry for a 4KB page mapping if the required 3189 * memory can be allocated without resorting to reclamation. 3190 */ 3191static boolean_t 3192pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m, 3193 struct rwlock **lockp) 3194{ 3195 pv_entry_t pv; 3196 3197 rw_assert(&pvh_global_lock, RA_LOCKED); 3198 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3199 /* Pass NULL instead of the lock pointer to disable reclamation. */ 3200 if ((pv = get_pv_entry(pmap, NULL)) != NULL) { 3201 pv->pv_va = va; 3202 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 3203 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3204 m->md.pv_gen++; 3205 return (TRUE); 3206 } else 3207 return (FALSE); 3208} 3209 3210/* 3211 * Conditionally create the PV entry for a 2MB page mapping if the required 3212 * memory can be allocated without resorting to reclamation. 3213 */ 3214static boolean_t 3215pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 3216 struct rwlock **lockp) 3217{ 3218 struct md_page *pvh; 3219 pv_entry_t pv; 3220 3221 rw_assert(&pvh_global_lock, RA_LOCKED); 3222 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3223 /* Pass NULL instead of the lock pointer to disable reclamation. */ 3224 if ((pv = get_pv_entry(pmap, NULL)) != NULL) { 3225 pv->pv_va = va; 3226 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 3227 pvh = pa_to_pvh(pa); 3228 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 3229 pvh->pv_gen++; 3230 return (TRUE); 3231 } else 3232 return (FALSE); 3233} 3234 3235/* 3236 * Fills a page table page with mappings to consecutive physical pages. 3237 */ 3238static void 3239pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte) 3240{ 3241 pt_entry_t *pte; 3242 3243 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 3244 *pte = newpte; 3245 newpte += PAGE_SIZE; 3246 } 3247} 3248 3249/* 3250 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page 3251 * mapping is invalidated. 3252 */ 3253static boolean_t 3254pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 3255{ 3256 struct rwlock *lock; 3257 boolean_t rv; 3258 3259 lock = NULL; 3260 rv = pmap_demote_pde_locked(pmap, pde, va, &lock); 3261 if (lock != NULL) 3262 rw_wunlock(lock); 3263 return (rv); 3264} 3265 3266static boolean_t 3267pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va, 3268 struct rwlock **lockp) 3269{ 3270 pd_entry_t newpde, oldpde; 3271 pt_entry_t *firstpte, newpte; 3272 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V; 3273 vm_paddr_t mptepa; 3274 vm_page_t mpte; 3275 struct spglist free; 3276 int PG_PTE_CACHE; 3277 3278 PG_G = pmap_global_bit(pmap); 3279 PG_A = pmap_accessed_bit(pmap); 3280 PG_M = pmap_modified_bit(pmap); 3281 PG_RW = pmap_rw_bit(pmap); 3282 PG_V = pmap_valid_bit(pmap); 3283 PG_PTE_CACHE = pmap_cache_mask(pmap, 0); 3284 3285 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3286 oldpde = *pde; 3287 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V), 3288 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V")); 3289 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) != 3290 NULL) 3291 pmap_remove_pt_page(pmap, mpte); 3292 else { 3293 KASSERT((oldpde & PG_W) == 0, 3294 ("pmap_demote_pde: page table page for a wired mapping" 3295 " is missing")); 3296 3297 /* 3298 * Invalidate the 2MB page mapping and return "failure" if the 3299 * mapping was never accessed or the allocation of the new 3300 * page table page fails. If the 2MB page mapping belongs to 3301 * the direct map region of the kernel's address space, then 3302 * the page allocation request specifies the highest possible 3303 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is 3304 * normal. Page table pages are preallocated for every other 3305 * part of the kernel address space, so the direct map region 3306 * is the only part of the kernel address space that must be 3307 * handled here. 3308 */ 3309 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL, 3310 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va < 3311 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) | 3312 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 3313 SLIST_INIT(&free); 3314 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free, 3315 lockp); 3316 pmap_invalidate_page(pmap, trunc_2mpage(va)); 3317 pmap_free_zero_pages(&free); 3318 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx" 3319 " in pmap %p", va, pmap); 3320 return (FALSE); 3321 } 3322 if (va < VM_MAXUSER_ADDRESS) 3323 pmap_resident_count_inc(pmap, 1); 3324 } 3325 mptepa = VM_PAGE_TO_PHYS(mpte); 3326 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa); 3327 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 3328 KASSERT((oldpde & PG_A) != 0, 3329 ("pmap_demote_pde: oldpde is missing PG_A")); 3330 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 3331 ("pmap_demote_pde: oldpde is missing PG_M")); 3332 newpte = oldpde & ~PG_PS; 3333 newpte = pmap_swap_pat(pmap, newpte); 3334 3335 /* 3336 * If the page table page is new, initialize it. 3337 */ 3338 if (mpte->wire_count == 1) { 3339 mpte->wire_count = NPTEPG; 3340 pmap_fill_ptp(firstpte, newpte); 3341 } 3342 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 3343 ("pmap_demote_pde: firstpte and newpte map different physical" 3344 " addresses")); 3345 3346 /* 3347 * If the mapping has changed attributes, update the page table 3348 * entries. 3349 */ 3350 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 3351 pmap_fill_ptp(firstpte, newpte); 3352 3353 /* 3354 * The spare PV entries must be reserved prior to demoting the 3355 * mapping, that is, prior to changing the PDE. Otherwise, the state 3356 * of the PDE and the PV lists will be inconsistent, which can result 3357 * in reclaim_pv_chunk() attempting to remove a PV entry from the 3358 * wrong PV list and pmap_pv_demote_pde() failing to find the expected 3359 * PV entry for the 2MB page mapping that is being demoted. 3360 */ 3361 if ((oldpde & PG_MANAGED) != 0) 3362 reserve_pv_entries(pmap, NPTEPG - 1, lockp); 3363 3364 /* 3365 * Demote the mapping. This pmap is locked. The old PDE has 3366 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 3367 * set. Thus, there is no danger of a race with another 3368 * processor changing the setting of PG_A and/or PG_M between 3369 * the read above and the store below. 3370 */ 3371 if (workaround_erratum383) 3372 pmap_update_pde(pmap, va, pde, newpde); 3373 else 3374 pde_store(pde, newpde); 3375 3376 /* 3377 * Invalidate a stale recursive mapping of the page table page. 3378 */ 3379 if (va >= VM_MAXUSER_ADDRESS) 3380 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 3381 3382 /* 3383 * Demote the PV entry. 3384 */ 3385 if ((oldpde & PG_MANAGED) != 0) 3386 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp); 3387 3388 atomic_add_long(&pmap_pde_demotions, 1); 3389 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx" 3390 " in pmap %p", va, pmap); 3391 return (TRUE); 3392} 3393 3394/* 3395 * pmap_remove_kernel_pde: Remove a kernel superpage mapping. 3396 */ 3397static void 3398pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 3399{ 3400 pd_entry_t newpde; 3401 vm_paddr_t mptepa; 3402 vm_page_t mpte; 3403 3404 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap)); 3405 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3406 mpte = pmap_lookup_pt_page(pmap, va); 3407 if (mpte == NULL) 3408 panic("pmap_remove_kernel_pde: Missing pt page."); 3409 3410 pmap_remove_pt_page(pmap, mpte); 3411 mptepa = VM_PAGE_TO_PHYS(mpte); 3412 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V; 3413 3414 /* 3415 * Initialize the page table page. 3416 */ 3417 pagezero((void *)PHYS_TO_DMAP(mptepa)); 3418 3419 /* 3420 * Demote the mapping. 3421 */ 3422 if (workaround_erratum383) 3423 pmap_update_pde(pmap, va, pde, newpde); 3424 else 3425 pde_store(pde, newpde); 3426 3427 /* 3428 * Invalidate a stale recursive mapping of the page table page. 3429 */ 3430 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 3431} 3432 3433/* 3434 * pmap_remove_pde: do the things to unmap a superpage in a process 3435 */ 3436static int 3437pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 3438 struct spglist *free, struct rwlock **lockp) 3439{ 3440 struct md_page *pvh; 3441 pd_entry_t oldpde; 3442 vm_offset_t eva, va; 3443 vm_page_t m, mpte; 3444 pt_entry_t PG_G, PG_A, PG_M, PG_RW; 3445 3446 PG_G = pmap_global_bit(pmap); 3447 PG_A = pmap_accessed_bit(pmap); 3448 PG_M = pmap_modified_bit(pmap); 3449 PG_RW = pmap_rw_bit(pmap); 3450 3451 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3452 KASSERT((sva & PDRMASK) == 0, 3453 ("pmap_remove_pde: sva is not 2mpage aligned")); 3454 oldpde = pte_load_clear(pdq); 3455 if (oldpde & PG_W) 3456 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 3457 3458 /* 3459 * Machines that don't support invlpg, also don't support 3460 * PG_G. 3461 */ 3462 if (oldpde & PG_G) 3463 pmap_invalidate_page(kernel_pmap, sva); 3464 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE); 3465 if (oldpde & PG_MANAGED) { 3466 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME); 3467 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 3468 pmap_pvh_free(pvh, pmap, sva); 3469 eva = sva + NBPDR; 3470 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 3471 va < eva; va += PAGE_SIZE, m++) { 3472 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 3473 vm_page_dirty(m); 3474 if (oldpde & PG_A) 3475 vm_page_aflag_set(m, PGA_REFERENCED); 3476 if (TAILQ_EMPTY(&m->md.pv_list) && 3477 TAILQ_EMPTY(&pvh->pv_list)) 3478 vm_page_aflag_clear(m, PGA_WRITEABLE); 3479 } 3480 } 3481 if (pmap == kernel_pmap) { 3482 pmap_remove_kernel_pde(pmap, pdq, sva); 3483 } else { 3484 mpte = pmap_lookup_pt_page(pmap, sva); 3485 if (mpte != NULL) { 3486 pmap_remove_pt_page(pmap, mpte); 3487 pmap_resident_count_dec(pmap, 1); 3488 KASSERT(mpte->wire_count == NPTEPG, 3489 ("pmap_remove_pde: pte page wire count error")); 3490 mpte->wire_count = 0; 3491 pmap_add_delayed_free_list(mpte, free, FALSE); 3492 atomic_subtract_int(&cnt.v_wire_count, 1); 3493 } 3494 } 3495 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free)); 3496} 3497 3498/* 3499 * pmap_remove_pte: do the things to unmap a page in a process 3500 */ 3501static int 3502pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, 3503 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp) 3504{ 3505 struct md_page *pvh; 3506 pt_entry_t oldpte, PG_A, PG_M, PG_RW; 3507 vm_page_t m; 3508 3509 PG_A = pmap_accessed_bit(pmap); 3510 PG_M = pmap_modified_bit(pmap); 3511 PG_RW = pmap_rw_bit(pmap); 3512 3513 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3514 oldpte = pte_load_clear(ptq); 3515 if (oldpte & PG_W) 3516 pmap->pm_stats.wired_count -= 1; 3517 pmap_resident_count_dec(pmap, 1); 3518 if (oldpte & PG_MANAGED) { 3519 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 3520 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 3521 vm_page_dirty(m); 3522 if (oldpte & PG_A) 3523 vm_page_aflag_set(m, PGA_REFERENCED); 3524 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 3525 pmap_pvh_free(&m->md, pmap, va); 3526 if (TAILQ_EMPTY(&m->md.pv_list) && 3527 (m->flags & PG_FICTITIOUS) == 0) { 3528 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3529 if (TAILQ_EMPTY(&pvh->pv_list)) 3530 vm_page_aflag_clear(m, PGA_WRITEABLE); 3531 } 3532 } 3533 return (pmap_unuse_pt(pmap, va, ptepde, free)); 3534} 3535 3536/* 3537 * Remove a single page from a process address space 3538 */ 3539static void 3540pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 3541 struct spglist *free) 3542{ 3543 struct rwlock *lock; 3544 pt_entry_t *pte, PG_V; 3545 3546 PG_V = pmap_valid_bit(pmap); 3547 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3548 if ((*pde & PG_V) == 0) 3549 return; 3550 pte = pmap_pde_to_pte(pde, va); 3551 if ((*pte & PG_V) == 0) 3552 return; 3553 lock = NULL; 3554 pmap_remove_pte(pmap, pte, va, *pde, free, &lock); 3555 if (lock != NULL) 3556 rw_wunlock(lock); 3557 pmap_invalidate_page(pmap, va); 3558} 3559 3560/* 3561 * Remove the given range of addresses from the specified map. 3562 * 3563 * It is assumed that the start and end are properly 3564 * rounded to the page size. 3565 */ 3566void 3567pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3568{ 3569 struct rwlock *lock; 3570 vm_offset_t va, va_next; 3571 pml4_entry_t *pml4e; 3572 pdp_entry_t *pdpe; 3573 pd_entry_t ptpaddr, *pde; 3574 pt_entry_t *pte, PG_G, PG_V; 3575 struct spglist free; 3576 int anyvalid; 3577 3578 PG_G = pmap_global_bit(pmap); 3579 PG_V = pmap_valid_bit(pmap); 3580 3581 /* 3582 * Perform an unsynchronized read. This is, however, safe. 3583 */ 3584 if (pmap->pm_stats.resident_count == 0) 3585 return; 3586 3587 anyvalid = 0; 3588 SLIST_INIT(&free); 3589 3590 rw_rlock(&pvh_global_lock); 3591 PMAP_LOCK(pmap); 3592 3593 /* 3594 * special handling of removing one page. a very 3595 * common operation and easy to short circuit some 3596 * code. 3597 */ 3598 if (sva + PAGE_SIZE == eva) { 3599 pde = pmap_pde(pmap, sva); 3600 if (pde && (*pde & PG_PS) == 0) { 3601 pmap_remove_page(pmap, sva, pde, &free); 3602 goto out; 3603 } 3604 } 3605 3606 lock = NULL; 3607 for (; sva < eva; sva = va_next) { 3608 3609 if (pmap->pm_stats.resident_count == 0) 3610 break; 3611 3612 pml4e = pmap_pml4e(pmap, sva); 3613 if ((*pml4e & PG_V) == 0) { 3614 va_next = (sva + NBPML4) & ~PML4MASK; 3615 if (va_next < sva) 3616 va_next = eva; 3617 continue; 3618 } 3619 3620 pdpe = pmap_pml4e_to_pdpe(pml4e, sva); 3621 if ((*pdpe & PG_V) == 0) { 3622 va_next = (sva + NBPDP) & ~PDPMASK; 3623 if (va_next < sva) 3624 va_next = eva; 3625 continue; 3626 } 3627 3628 /* 3629 * Calculate index for next page table. 3630 */ 3631 va_next = (sva + NBPDR) & ~PDRMASK; 3632 if (va_next < sva) 3633 va_next = eva; 3634 3635 pde = pmap_pdpe_to_pde(pdpe, sva); 3636 ptpaddr = *pde; 3637 3638 /* 3639 * Weed out invalid mappings. 3640 */ 3641 if (ptpaddr == 0) 3642 continue; 3643 3644 /* 3645 * Check for large page. 3646 */ 3647 if ((ptpaddr & PG_PS) != 0) { 3648 /* 3649 * Are we removing the entire large page? If not, 3650 * demote the mapping and fall through. 3651 */ 3652 if (sva + NBPDR == va_next && eva >= va_next) { 3653 /* 3654 * The TLB entry for a PG_G mapping is 3655 * invalidated by pmap_remove_pde(). 3656 */ 3657 if ((ptpaddr & PG_G) == 0) 3658 anyvalid = 1; 3659 pmap_remove_pde(pmap, pde, sva, &free, &lock); 3660 continue; 3661 } else if (!pmap_demote_pde_locked(pmap, pde, sva, 3662 &lock)) { 3663 /* The large page mapping was destroyed. */ 3664 continue; 3665 } else 3666 ptpaddr = *pde; 3667 } 3668 3669 /* 3670 * Limit our scan to either the end of the va represented 3671 * by the current page table page, or to the end of the 3672 * range being removed. 3673 */ 3674 if (va_next > eva) 3675 va_next = eva; 3676 3677 va = va_next; 3678 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 3679 sva += PAGE_SIZE) { 3680 if (*pte == 0) { 3681 if (va != va_next) { 3682 pmap_invalidate_range(pmap, va, sva); 3683 va = va_next; 3684 } 3685 continue; 3686 } 3687 if ((*pte & PG_G) == 0) 3688 anyvalid = 1; 3689 else if (va == va_next) 3690 va = sva; 3691 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free, 3692 &lock)) { 3693 sva += PAGE_SIZE; 3694 break; 3695 } 3696 } 3697 if (va != va_next) 3698 pmap_invalidate_range(pmap, va, sva); 3699 } 3700 if (lock != NULL) 3701 rw_wunlock(lock); 3702out: 3703 if (anyvalid) 3704 pmap_invalidate_all(pmap); 3705 rw_runlock(&pvh_global_lock); 3706 PMAP_UNLOCK(pmap); 3707 pmap_free_zero_pages(&free); 3708} 3709 3710/* 3711 * Routine: pmap_remove_all 3712 * Function: 3713 * Removes this physical page from 3714 * all physical maps in which it resides. 3715 * Reflects back modify bits to the pager. 3716 * 3717 * Notes: 3718 * Original versions of this routine were very 3719 * inefficient because they iteratively called 3720 * pmap_remove (slow...) 3721 */ 3722 3723void 3724pmap_remove_all(vm_page_t m) 3725{ 3726 struct md_page *pvh; 3727 pv_entry_t pv; 3728 pmap_t pmap; 3729 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW; 3730 pd_entry_t *pde; 3731 vm_offset_t va; 3732 struct spglist free; 3733 3734 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3735 ("pmap_remove_all: page %p is not managed", m)); 3736 SLIST_INIT(&free); 3737 rw_wlock(&pvh_global_lock); 3738 if ((m->flags & PG_FICTITIOUS) != 0) 3739 goto small_mappings; 3740 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3741 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 3742 pmap = PV_PMAP(pv); 3743 PMAP_LOCK(pmap); 3744 va = pv->pv_va; 3745 pde = pmap_pde(pmap, va); 3746 (void)pmap_demote_pde(pmap, pde, va); 3747 PMAP_UNLOCK(pmap); 3748 } 3749small_mappings: 3750 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3751 pmap = PV_PMAP(pv); 3752 PMAP_LOCK(pmap); 3753 PG_A = pmap_accessed_bit(pmap); 3754 PG_M = pmap_modified_bit(pmap); 3755 PG_RW = pmap_rw_bit(pmap); 3756 pmap_resident_count_dec(pmap, 1); 3757 pde = pmap_pde(pmap, pv->pv_va); 3758 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 3759 " a 2mpage in page %p's pv list", m)); 3760 pte = pmap_pde_to_pte(pde, pv->pv_va); 3761 tpte = pte_load_clear(pte); 3762 if (tpte & PG_W) 3763 pmap->pm_stats.wired_count--; 3764 if (tpte & PG_A) 3765 vm_page_aflag_set(m, PGA_REFERENCED); 3766 3767 /* 3768 * Update the vm_page_t clean and reference bits. 3769 */ 3770 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 3771 vm_page_dirty(m); 3772 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free); 3773 pmap_invalidate_page(pmap, pv->pv_va); 3774 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3775 m->md.pv_gen++; 3776 free_pv_entry(pmap, pv); 3777 PMAP_UNLOCK(pmap); 3778 } 3779 vm_page_aflag_clear(m, PGA_WRITEABLE); 3780 rw_wunlock(&pvh_global_lock); 3781 pmap_free_zero_pages(&free); 3782} 3783 3784/* 3785 * pmap_protect_pde: do the things to protect a 2mpage in a process 3786 */ 3787static boolean_t 3788pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 3789{ 3790 pd_entry_t newpde, oldpde; 3791 vm_offset_t eva, va; 3792 vm_page_t m; 3793 boolean_t anychanged; 3794 pt_entry_t PG_G, PG_M, PG_RW; 3795 3796 PG_G = pmap_global_bit(pmap); 3797 PG_M = pmap_modified_bit(pmap); 3798 PG_RW = pmap_rw_bit(pmap); 3799 3800 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3801 KASSERT((sva & PDRMASK) == 0, 3802 ("pmap_protect_pde: sva is not 2mpage aligned")); 3803 anychanged = FALSE; 3804retry: 3805 oldpde = newpde = *pde; 3806 if (oldpde & PG_MANAGED) { 3807 eva = sva + NBPDR; 3808 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 3809 va < eva; va += PAGE_SIZE, m++) 3810 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 3811 vm_page_dirty(m); 3812 } 3813 if ((prot & VM_PROT_WRITE) == 0) 3814 newpde &= ~(PG_RW | PG_M); 3815 if ((prot & VM_PROT_EXECUTE) == 0) 3816 newpde |= pg_nx; 3817 if (newpde != oldpde) { 3818 if (!atomic_cmpset_long(pde, oldpde, newpde)) 3819 goto retry; 3820 if (oldpde & PG_G) 3821 pmap_invalidate_page(pmap, sva); 3822 else 3823 anychanged = TRUE; 3824 } 3825 return (anychanged); 3826} 3827 3828/* 3829 * Set the physical protection on the 3830 * specified range of this map as requested. 3831 */ 3832void 3833pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3834{ 3835 vm_offset_t va_next; 3836 pml4_entry_t *pml4e; 3837 pdp_entry_t *pdpe; 3838 pd_entry_t ptpaddr, *pde; 3839 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V; 3840 boolean_t anychanged, pv_lists_locked; 3841 3842 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 3843 pmap_remove(pmap, sva, eva); 3844 return; 3845 } 3846 3847 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 3848 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 3849 return; 3850 3851 PG_G = pmap_global_bit(pmap); 3852 PG_M = pmap_modified_bit(pmap); 3853 PG_V = pmap_valid_bit(pmap); 3854 PG_RW = pmap_rw_bit(pmap); 3855 pv_lists_locked = FALSE; 3856resume: 3857 anychanged = FALSE; 3858 3859 PMAP_LOCK(pmap); 3860 for (; sva < eva; sva = va_next) { 3861 3862 pml4e = pmap_pml4e(pmap, sva); 3863 if ((*pml4e & PG_V) == 0) { 3864 va_next = (sva + NBPML4) & ~PML4MASK; 3865 if (va_next < sva) 3866 va_next = eva; 3867 continue; 3868 } 3869 3870 pdpe = pmap_pml4e_to_pdpe(pml4e, sva); 3871 if ((*pdpe & PG_V) == 0) { 3872 va_next = (sva + NBPDP) & ~PDPMASK; 3873 if (va_next < sva) 3874 va_next = eva; 3875 continue; 3876 } 3877 3878 va_next = (sva + NBPDR) & ~PDRMASK; 3879 if (va_next < sva) 3880 va_next = eva; 3881 3882 pde = pmap_pdpe_to_pde(pdpe, sva); 3883 ptpaddr = *pde; 3884 3885 /* 3886 * Weed out invalid mappings. 3887 */ 3888 if (ptpaddr == 0) 3889 continue; 3890 3891 /* 3892 * Check for large page. 3893 */ 3894 if ((ptpaddr & PG_PS) != 0) { 3895 /* 3896 * Are we protecting the entire large page? If not, 3897 * demote the mapping and fall through. 3898 */ 3899 if (sva + NBPDR == va_next && eva >= va_next) { 3900 /* 3901 * The TLB entry for a PG_G mapping is 3902 * invalidated by pmap_protect_pde(). 3903 */ 3904 if (pmap_protect_pde(pmap, pde, sva, prot)) 3905 anychanged = TRUE; 3906 continue; 3907 } else { 3908 if (!pv_lists_locked) { 3909 pv_lists_locked = TRUE; 3910 if (!rw_try_rlock(&pvh_global_lock)) { 3911 if (anychanged) 3912 pmap_invalidate_all( 3913 pmap); 3914 PMAP_UNLOCK(pmap); 3915 rw_rlock(&pvh_global_lock); 3916 goto resume; 3917 } 3918 } 3919 if (!pmap_demote_pde(pmap, pde, sva)) { 3920 /* 3921 * The large page mapping was 3922 * destroyed. 3923 */ 3924 continue; 3925 } 3926 } 3927 } 3928 3929 if (va_next > eva) 3930 va_next = eva; 3931 3932 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 3933 sva += PAGE_SIZE) { 3934 pt_entry_t obits, pbits; 3935 vm_page_t m; 3936 3937retry: 3938 obits = pbits = *pte; 3939 if ((pbits & PG_V) == 0) 3940 continue; 3941 3942 if ((prot & VM_PROT_WRITE) == 0) { 3943 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 3944 (PG_MANAGED | PG_M | PG_RW)) { 3945 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 3946 vm_page_dirty(m); 3947 } 3948 pbits &= ~(PG_RW | PG_M); 3949 } 3950 if ((prot & VM_PROT_EXECUTE) == 0) 3951 pbits |= pg_nx; 3952 3953 if (pbits != obits) { 3954 if (!atomic_cmpset_long(pte, obits, pbits)) 3955 goto retry; 3956 if (obits & PG_G) 3957 pmap_invalidate_page(pmap, sva); 3958 else 3959 anychanged = TRUE; 3960 } 3961 } 3962 } 3963 if (anychanged) 3964 pmap_invalidate_all(pmap); 3965 if (pv_lists_locked) 3966 rw_runlock(&pvh_global_lock); 3967 PMAP_UNLOCK(pmap); 3968} 3969 3970/* 3971 * Tries to promote the 512, contiguous 4KB page mappings that are within a 3972 * single page table page (PTP) to a single 2MB page mapping. For promotion 3973 * to occur, two conditions must be met: (1) the 4KB page mappings must map 3974 * aligned, contiguous physical memory and (2) the 4KB page mappings must have 3975 * identical characteristics. 3976 */ 3977static void 3978pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va, 3979 struct rwlock **lockp) 3980{ 3981 pd_entry_t newpde; 3982 pt_entry_t *firstpte, oldpte, pa, *pte; 3983 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V; 3984 vm_offset_t oldpteva; 3985 vm_page_t mpte; 3986 int PG_PTE_CACHE; 3987 3988 PG_A = pmap_accessed_bit(pmap); 3989 PG_G = pmap_global_bit(pmap); 3990 PG_M = pmap_modified_bit(pmap); 3991 PG_V = pmap_valid_bit(pmap); 3992 PG_RW = pmap_rw_bit(pmap); 3993 PG_PTE_CACHE = pmap_cache_mask(pmap, 0); 3994 3995 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3996 3997 /* 3998 * Examine the first PTE in the specified PTP. Abort if this PTE is 3999 * either invalid, unused, or does not map the first 4KB physical page 4000 * within a 2MB page. 4001 */ 4002 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME); 4003setpde: 4004 newpde = *firstpte; 4005 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) { 4006 atomic_add_long(&pmap_pde_p_failures, 1); 4007 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx" 4008 " in pmap %p", va, pmap); 4009 return; 4010 } 4011 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 4012 /* 4013 * When PG_M is already clear, PG_RW can be cleared without 4014 * a TLB invalidation. 4015 */ 4016 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW)) 4017 goto setpde; 4018 newpde &= ~PG_RW; 4019 } 4020 4021 /* 4022 * Examine each of the other PTEs in the specified PTP. Abort if this 4023 * PTE maps an unexpected 4KB physical page or does not have identical 4024 * characteristics to the first PTE. 4025 */ 4026 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE; 4027 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 4028setpte: 4029 oldpte = *pte; 4030 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) { 4031 atomic_add_long(&pmap_pde_p_failures, 1); 4032 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx" 4033 " in pmap %p", va, pmap); 4034 return; 4035 } 4036 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 4037 /* 4038 * When PG_M is already clear, PG_RW can be cleared 4039 * without a TLB invalidation. 4040 */ 4041 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW)) 4042 goto setpte; 4043 oldpte &= ~PG_RW; 4044 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 4045 (va & ~PDRMASK); 4046 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx" 4047 " in pmap %p", oldpteva, pmap); 4048 } 4049 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 4050 atomic_add_long(&pmap_pde_p_failures, 1); 4051 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx" 4052 " in pmap %p", va, pmap); 4053 return; 4054 } 4055 pa -= PAGE_SIZE; 4056 } 4057 4058 /* 4059 * Save the page table page in its current state until the PDE 4060 * mapping the superpage is demoted by pmap_demote_pde() or 4061 * destroyed by pmap_remove_pde(). 4062 */ 4063 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 4064 KASSERT(mpte >= vm_page_array && 4065 mpte < &vm_page_array[vm_page_array_size], 4066 ("pmap_promote_pde: page table page is out of range")); 4067 KASSERT(mpte->pindex == pmap_pde_pindex(va), 4068 ("pmap_promote_pde: page table page's pindex is wrong")); 4069 if (pmap_insert_pt_page(pmap, mpte)) { 4070 atomic_add_long(&pmap_pde_p_failures, 1); 4071 CTR2(KTR_PMAP, 4072 "pmap_promote_pde: failure for va %#lx in pmap %p", va, 4073 pmap); 4074 return; 4075 } 4076 4077 /* 4078 * Promote the pv entries. 4079 */ 4080 if ((newpde & PG_MANAGED) != 0) 4081 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp); 4082 4083 /* 4084 * Propagate the PAT index to its proper position. 4085 */ 4086 newpde = pmap_swap_pat(pmap, newpde); 4087 4088 /* 4089 * Map the superpage. 4090 */ 4091 if (workaround_erratum383) 4092 pmap_update_pde(pmap, va, pde, PG_PS | newpde); 4093 else 4094 pde_store(pde, PG_PS | newpde); 4095 4096 atomic_add_long(&pmap_pde_promotions, 1); 4097 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx" 4098 " in pmap %p", va, pmap); 4099} 4100 4101/* 4102 * Insert the given physical page (p) at 4103 * the specified virtual address (v) in the 4104 * target physical map with the protection requested. 4105 * 4106 * If specified, the page will be wired down, meaning 4107 * that the related pte can not be reclaimed. 4108 * 4109 * NB: This is the only routine which MAY NOT lazy-evaluate 4110 * or lose information. That is, this routine must actually 4111 * insert this page into the given map NOW. 4112 */ 4113void 4114pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 4115 vm_prot_t prot, boolean_t wired) 4116{ 4117 struct rwlock *lock; 4118 pd_entry_t *pde; 4119 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V; 4120 pt_entry_t newpte, origpte; 4121 pv_entry_t pv; 4122 vm_paddr_t opa, pa; 4123 vm_page_t mpte, om; 4124 4125 PG_A = pmap_accessed_bit(pmap); 4126 PG_G = pmap_global_bit(pmap); 4127 PG_M = pmap_modified_bit(pmap); 4128 PG_V = pmap_valid_bit(pmap); 4129 PG_RW = pmap_rw_bit(pmap); 4130 4131 va = trunc_page(va); 4132 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 4133 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 4134 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)", 4135 va)); 4136 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva || 4137 va >= kmi.clean_eva, 4138 ("pmap_enter: managed mapping within the clean submap")); 4139 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 4140 VM_OBJECT_ASSERT_WLOCKED(m->object); 4141 pa = VM_PAGE_TO_PHYS(m); 4142 newpte = (pt_entry_t)(pa | PG_A | PG_V); 4143 if ((access & VM_PROT_WRITE) != 0) 4144 newpte |= PG_M; 4145 if ((prot & VM_PROT_WRITE) != 0) 4146 newpte |= PG_RW; 4147 KASSERT((newpte & (PG_M | PG_RW)) != PG_M, 4148 ("pmap_enter: access includes VM_PROT_WRITE but prot doesn't")); 4149 if ((prot & VM_PROT_EXECUTE) == 0) 4150 newpte |= pg_nx; 4151 if (wired) 4152 newpte |= PG_W; 4153 if (va < VM_MAXUSER_ADDRESS) 4154 newpte |= PG_U; 4155 if (pmap == kernel_pmap) 4156 newpte |= PG_G; 4157 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, 0); 4158 4159 /* 4160 * Set modified bit gratuitously for writeable mappings if 4161 * the page is unmanaged. We do not want to take a fault 4162 * to do the dirty bit accounting for these mappings. 4163 */ 4164 if ((m->oflags & VPO_UNMANAGED) != 0) { 4165 if ((newpte & PG_RW) != 0) 4166 newpte |= PG_M; 4167 } 4168 4169 mpte = NULL; 4170 4171 lock = NULL; 4172 rw_rlock(&pvh_global_lock); 4173 PMAP_LOCK(pmap); 4174 4175 /* 4176 * In the case that a page table page is not 4177 * resident, we are creating it here. 4178 */ 4179retry: 4180 pde = pmap_pde(pmap, va); 4181 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 || 4182 pmap_demote_pde_locked(pmap, pde, va, &lock))) { 4183 pte = pmap_pde_to_pte(pde, va); 4184 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) { 4185 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 4186 mpte->wire_count++; 4187 } 4188 } else if (va < VM_MAXUSER_ADDRESS) { 4189 /* 4190 * Here if the pte page isn't mapped, or if it has been 4191 * deallocated. 4192 */ 4193 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va), &lock); 4194 goto retry; 4195 } else 4196 panic("pmap_enter: invalid page directory va=%#lx", va); 4197 4198 origpte = *pte; 4199 4200 /* 4201 * Is the specified virtual address already mapped? 4202 */ 4203 if ((origpte & PG_V) != 0) { 4204 /* 4205 * Wiring change, just update stats. We don't worry about 4206 * wiring PT pages as they remain resident as long as there 4207 * are valid mappings in them. Hence, if a user page is wired, 4208 * the PT page will be also. 4209 */ 4210 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0) 4211 pmap->pm_stats.wired_count++; 4212 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0) 4213 pmap->pm_stats.wired_count--; 4214 4215 /* 4216 * Remove the extra PT page reference. 4217 */ 4218 if (mpte != NULL) { 4219 mpte->wire_count--; 4220 KASSERT(mpte->wire_count > 0, 4221 ("pmap_enter: missing reference to page table page," 4222 " va: 0x%lx", va)); 4223 } 4224 4225 /* 4226 * Has the physical page changed? 4227 */ 4228 opa = origpte & PG_FRAME; 4229 if (opa == pa) { 4230 /* 4231 * No, might be a protection or wiring change. 4232 */ 4233 if ((origpte & PG_MANAGED) != 0) { 4234 newpte |= PG_MANAGED; 4235 if ((newpte & PG_RW) != 0) 4236 vm_page_aflag_set(m, PGA_WRITEABLE); 4237 } 4238 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0) 4239 goto unchanged; 4240 goto validate; 4241 } 4242 } else { 4243 /* 4244 * Increment the counters. 4245 */ 4246 if ((newpte & PG_W) != 0) 4247 pmap->pm_stats.wired_count++; 4248 pmap_resident_count_inc(pmap, 1); 4249 } 4250 4251 /* 4252 * Enter on the PV list if part of our managed memory. 4253 */ 4254 if ((m->oflags & VPO_UNMANAGED) == 0) { 4255 newpte |= PG_MANAGED; 4256 pv = get_pv_entry(pmap, &lock); 4257 pv->pv_va = va; 4258 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa); 4259 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 4260 m->md.pv_gen++; 4261 if ((newpte & PG_RW) != 0) 4262 vm_page_aflag_set(m, PGA_WRITEABLE); 4263 } 4264 4265 /* 4266 * Update the PTE. 4267 */ 4268 if ((origpte & PG_V) != 0) { 4269validate: 4270 origpte = pte_load_store(pte, newpte); 4271 opa = origpte & PG_FRAME; 4272 if (opa != pa) { 4273 if ((origpte & PG_MANAGED) != 0) { 4274 om = PHYS_TO_VM_PAGE(opa); 4275 if ((origpte & (PG_M | PG_RW)) == (PG_M | 4276 PG_RW)) 4277 vm_page_dirty(om); 4278 if ((origpte & PG_A) != 0) 4279 vm_page_aflag_set(om, PGA_REFERENCED); 4280 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa); 4281 pmap_pvh_free(&om->md, pmap, va); 4282 if ((om->aflags & PGA_WRITEABLE) != 0 && 4283 TAILQ_EMPTY(&om->md.pv_list) && 4284 ((om->flags & PG_FICTITIOUS) != 0 || 4285 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list))) 4286 vm_page_aflag_clear(om, PGA_WRITEABLE); 4287 } 4288 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M | 4289 PG_RW)) == (PG_M | PG_RW)) { 4290 if ((origpte & PG_MANAGED) != 0) 4291 vm_page_dirty(m); 4292 4293 /* 4294 * Although the PTE may still have PG_RW set, TLB 4295 * invalidation may nonetheless be required because 4296 * the PTE no longer has PG_M set. 4297 */ 4298 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) { 4299 /* 4300 * This PTE change does not require TLB invalidation. 4301 */ 4302 goto unchanged; 4303 } 4304 if ((origpte & PG_A) != 0) 4305 pmap_invalidate_page(pmap, va); 4306 } else 4307 pte_store(pte, newpte); 4308 4309unchanged: 4310 4311 /* 4312 * If both the page table page and the reservation are fully 4313 * populated, then attempt promotion. 4314 */ 4315 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 4316 pmap_ps_enabled(pmap) && 4317 (m->flags & PG_FICTITIOUS) == 0 && 4318 vm_reserv_level_iffullpop(m) == 0) 4319 pmap_promote_pde(pmap, pde, va, &lock); 4320 4321 if (lock != NULL) 4322 rw_wunlock(lock); 4323 rw_runlock(&pvh_global_lock); 4324 PMAP_UNLOCK(pmap); 4325} 4326 4327/* 4328 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE 4329 * otherwise. Fails if (1) a page table page cannot be allocated without 4330 * blocking, (2) a mapping already exists at the specified virtual address, or 4331 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 4332 */ 4333static boolean_t 4334pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 4335 struct rwlock **lockp) 4336{ 4337 pd_entry_t *pde, newpde; 4338 pt_entry_t PG_V; 4339 vm_page_t mpde; 4340 struct spglist free; 4341 4342 PG_V = pmap_valid_bit(pmap); 4343 rw_assert(&pvh_global_lock, RA_LOCKED); 4344 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4345 4346 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) { 4347 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 4348 " in pmap %p", va, pmap); 4349 return (FALSE); 4350 } 4351 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde)); 4352 pde = &pde[pmap_pde_index(va)]; 4353 if ((*pde & PG_V) != 0) { 4354 KASSERT(mpde->wire_count > 1, 4355 ("pmap_enter_pde: mpde's wire count is too low")); 4356 mpde->wire_count--; 4357 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 4358 " in pmap %p", va, pmap); 4359 return (FALSE); 4360 } 4361 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) | 4362 PG_PS | PG_V; 4363 if ((m->oflags & VPO_UNMANAGED) == 0) { 4364 newpde |= PG_MANAGED; 4365 4366 /* 4367 * Abort this mapping if its PV entry could not be created. 4368 */ 4369 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m), 4370 lockp)) { 4371 SLIST_INIT(&free); 4372 if (pmap_unwire_ptp(pmap, va, mpde, &free)) { 4373 pmap_invalidate_page(pmap, va); 4374 pmap_free_zero_pages(&free); 4375 } 4376 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 4377 " in pmap %p", va, pmap); 4378 return (FALSE); 4379 } 4380 } 4381 if ((prot & VM_PROT_EXECUTE) == 0) 4382 newpde |= pg_nx; 4383 if (va < VM_MAXUSER_ADDRESS) 4384 newpde |= PG_U; 4385 4386 /* 4387 * Increment counters. 4388 */ 4389 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE); 4390 4391 /* 4392 * Map the superpage. 4393 */ 4394 pde_store(pde, newpde); 4395 4396 atomic_add_long(&pmap_pde_mappings, 1); 4397 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 4398 " in pmap %p", va, pmap); 4399 return (TRUE); 4400} 4401 4402/* 4403 * Maps a sequence of resident pages belonging to the same object. 4404 * The sequence begins with the given page m_start. This page is 4405 * mapped at the given virtual address start. Each subsequent page is 4406 * mapped at a virtual address that is offset from start by the same 4407 * amount as the page is offset from m_start within the object. The 4408 * last page in the sequence is the page with the largest offset from 4409 * m_start that can be mapped at a virtual address less than the given 4410 * virtual address end. Not every virtual page between start and end 4411 * is mapped; only those for which a resident page exists with the 4412 * corresponding offset from m_start are mapped. 4413 */ 4414void 4415pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 4416 vm_page_t m_start, vm_prot_t prot) 4417{ 4418 struct rwlock *lock; 4419 vm_offset_t va; 4420 vm_page_t m, mpte; 4421 vm_pindex_t diff, psize; 4422 4423 VM_OBJECT_ASSERT_LOCKED(m_start->object); 4424 4425 psize = atop(end - start); 4426 mpte = NULL; 4427 m = m_start; 4428 lock = NULL; 4429 rw_rlock(&pvh_global_lock); 4430 PMAP_LOCK(pmap); 4431 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 4432 va = start + ptoa(diff); 4433 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 4434 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 && 4435 pmap_ps_enabled(pmap) && 4436 vm_reserv_level_iffullpop(m) == 0 && 4437 pmap_enter_pde(pmap, va, m, prot, &lock)) 4438 m = &m[NBPDR / PAGE_SIZE - 1]; 4439 else 4440 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 4441 mpte, &lock); 4442 m = TAILQ_NEXT(m, listq); 4443 } 4444 if (lock != NULL) 4445 rw_wunlock(lock); 4446 rw_runlock(&pvh_global_lock); 4447 PMAP_UNLOCK(pmap); 4448} 4449 4450/* 4451 * this code makes some *MAJOR* assumptions: 4452 * 1. Current pmap & pmap exists. 4453 * 2. Not wired. 4454 * 3. Read access. 4455 * 4. No page table pages. 4456 * but is *MUCH* faster than pmap_enter... 4457 */ 4458 4459void 4460pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 4461{ 4462 struct rwlock *lock; 4463 4464 lock = NULL; 4465 rw_rlock(&pvh_global_lock); 4466 PMAP_LOCK(pmap); 4467 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock); 4468 if (lock != NULL) 4469 rw_wunlock(lock); 4470 rw_runlock(&pvh_global_lock); 4471 PMAP_UNLOCK(pmap); 4472} 4473 4474static vm_page_t 4475pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 4476 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp) 4477{ 4478 struct spglist free; 4479 pt_entry_t *pte, PG_V; 4480 vm_paddr_t pa; 4481 4482 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 4483 (m->oflags & VPO_UNMANAGED) != 0, 4484 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 4485 PG_V = pmap_valid_bit(pmap); 4486 rw_assert(&pvh_global_lock, RA_LOCKED); 4487 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4488 4489 /* 4490 * In the case that a page table page is not 4491 * resident, we are creating it here. 4492 */ 4493 if (va < VM_MAXUSER_ADDRESS) { 4494 vm_pindex_t ptepindex; 4495 pd_entry_t *ptepa; 4496 4497 /* 4498 * Calculate pagetable page index 4499 */ 4500 ptepindex = pmap_pde_pindex(va); 4501 if (mpte && (mpte->pindex == ptepindex)) { 4502 mpte->wire_count++; 4503 } else { 4504 /* 4505 * Get the page directory entry 4506 */ 4507 ptepa = pmap_pde(pmap, va); 4508 4509 /* 4510 * If the page table page is mapped, we just increment 4511 * the hold count, and activate it. Otherwise, we 4512 * attempt to allocate a page table page. If this 4513 * attempt fails, we don't retry. Instead, we give up. 4514 */ 4515 if (ptepa && (*ptepa & PG_V) != 0) { 4516 if (*ptepa & PG_PS) 4517 return (NULL); 4518 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME); 4519 mpte->wire_count++; 4520 } else { 4521 /* 4522 * Pass NULL instead of the PV list lock 4523 * pointer, because we don't intend to sleep. 4524 */ 4525 mpte = _pmap_allocpte(pmap, ptepindex, NULL); 4526 if (mpte == NULL) 4527 return (mpte); 4528 } 4529 } 4530 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte)); 4531 pte = &pte[pmap_pte_index(va)]; 4532 } else { 4533 mpte = NULL; 4534 pte = vtopte(va); 4535 } 4536 if (*pte) { 4537 if (mpte != NULL) { 4538 mpte->wire_count--; 4539 mpte = NULL; 4540 } 4541 return (mpte); 4542 } 4543 4544 /* 4545 * Enter on the PV list if part of our managed memory. 4546 */ 4547 if ((m->oflags & VPO_UNMANAGED) == 0 && 4548 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) { 4549 if (mpte != NULL) { 4550 SLIST_INIT(&free); 4551 if (pmap_unwire_ptp(pmap, va, mpte, &free)) { 4552 pmap_invalidate_page(pmap, va); 4553 pmap_free_zero_pages(&free); 4554 } 4555 mpte = NULL; 4556 } 4557 return (mpte); 4558 } 4559 4560 /* 4561 * Increment counters 4562 */ 4563 pmap_resident_count_inc(pmap, 1); 4564 4565 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0); 4566 if ((prot & VM_PROT_EXECUTE) == 0) 4567 pa |= pg_nx; 4568 4569 /* 4570 * Now validate mapping with RO protection 4571 */ 4572 if ((m->oflags & VPO_UNMANAGED) != 0) 4573 pte_store(pte, pa | PG_V | PG_U); 4574 else 4575 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 4576 return (mpte); 4577} 4578 4579/* 4580 * Make a temporary mapping for a physical address. This is only intended 4581 * to be used for panic dumps. 4582 */ 4583void * 4584pmap_kenter_temporary(vm_paddr_t pa, int i) 4585{ 4586 vm_offset_t va; 4587 4588 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 4589 pmap_kenter(va, pa); 4590 invlpg(va); 4591 return ((void *)crashdumpmap); 4592} 4593 4594/* 4595 * This code maps large physical mmap regions into the 4596 * processor address space. Note that some shortcuts 4597 * are taken, but the code works. 4598 */ 4599void 4600pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 4601 vm_pindex_t pindex, vm_size_t size) 4602{ 4603 pd_entry_t *pde; 4604 pt_entry_t PG_A, PG_M, PG_RW, PG_V; 4605 vm_paddr_t pa, ptepa; 4606 vm_page_t p, pdpg; 4607 int pat_mode; 4608 4609 PG_A = pmap_accessed_bit(pmap); 4610 PG_M = pmap_modified_bit(pmap); 4611 PG_V = pmap_valid_bit(pmap); 4612 PG_RW = pmap_rw_bit(pmap); 4613 4614 VM_OBJECT_ASSERT_WLOCKED(object); 4615 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 4616 ("pmap_object_init_pt: non-device object")); 4617 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 4618 if (!pmap_ps_enabled(pmap)) 4619 return; 4620 if (!vm_object_populate(object, pindex, pindex + atop(size))) 4621 return; 4622 p = vm_page_lookup(object, pindex); 4623 KASSERT(p->valid == VM_PAGE_BITS_ALL, 4624 ("pmap_object_init_pt: invalid page %p", p)); 4625 pat_mode = p->md.pat_mode; 4626 4627 /* 4628 * Abort the mapping if the first page is not physically 4629 * aligned to a 2MB page boundary. 4630 */ 4631 ptepa = VM_PAGE_TO_PHYS(p); 4632 if (ptepa & (NBPDR - 1)) 4633 return; 4634 4635 /* 4636 * Skip the first page. Abort the mapping if the rest of 4637 * the pages are not physically contiguous or have differing 4638 * memory attributes. 4639 */ 4640 p = TAILQ_NEXT(p, listq); 4641 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 4642 pa += PAGE_SIZE) { 4643 KASSERT(p->valid == VM_PAGE_BITS_ALL, 4644 ("pmap_object_init_pt: invalid page %p", p)); 4645 if (pa != VM_PAGE_TO_PHYS(p) || 4646 pat_mode != p->md.pat_mode) 4647 return; 4648 p = TAILQ_NEXT(p, listq); 4649 } 4650 4651 /* 4652 * Map using 2MB pages. Since "ptepa" is 2M aligned and 4653 * "size" is a multiple of 2M, adding the PAT setting to "pa" 4654 * will not affect the termination of this loop. 4655 */ 4656 PMAP_LOCK(pmap); 4657 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1); 4658 pa < ptepa + size; pa += NBPDR) { 4659 pdpg = pmap_allocpde(pmap, addr, NULL); 4660 if (pdpg == NULL) { 4661 /* 4662 * The creation of mappings below is only an 4663 * optimization. If a page directory page 4664 * cannot be allocated without blocking, 4665 * continue on to the next mapping rather than 4666 * blocking. 4667 */ 4668 addr += NBPDR; 4669 continue; 4670 } 4671 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg)); 4672 pde = &pde[pmap_pde_index(addr)]; 4673 if ((*pde & PG_V) == 0) { 4674 pde_store(pde, pa | PG_PS | PG_M | PG_A | 4675 PG_U | PG_RW | PG_V); 4676 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE); 4677 atomic_add_long(&pmap_pde_mappings, 1); 4678 } else { 4679 /* Continue on if the PDE is already valid. */ 4680 pdpg->wire_count--; 4681 KASSERT(pdpg->wire_count > 0, 4682 ("pmap_object_init_pt: missing reference " 4683 "to page directory page, va: 0x%lx", addr)); 4684 } 4685 addr += NBPDR; 4686 } 4687 PMAP_UNLOCK(pmap); 4688 } 4689} 4690 4691/* 4692 * Routine: pmap_change_wiring 4693 * Function: Change the wiring attribute for a map/virtual-address 4694 * pair. 4695 * In/out conditions: 4696 * The mapping must already exist in the pmap. 4697 */ 4698void 4699pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 4700{ 4701 pd_entry_t *pde; 4702 pt_entry_t *pte; 4703 boolean_t pv_lists_locked; 4704 4705 pv_lists_locked = FALSE; 4706 4707 /* 4708 * Wiring is not a hardware characteristic so there is no need to 4709 * invalidate TLB. 4710 */ 4711retry: 4712 PMAP_LOCK(pmap); 4713 pde = pmap_pde(pmap, va); 4714 if ((*pde & PG_PS) != 0) { 4715 if (!wired != ((*pde & PG_W) == 0)) { 4716 if (!pv_lists_locked) { 4717 pv_lists_locked = TRUE; 4718 if (!rw_try_rlock(&pvh_global_lock)) { 4719 PMAP_UNLOCK(pmap); 4720 rw_rlock(&pvh_global_lock); 4721 goto retry; 4722 } 4723 } 4724 if (!pmap_demote_pde(pmap, pde, va)) 4725 panic("pmap_change_wiring: demotion failed"); 4726 } else 4727 goto out; 4728 } 4729 pte = pmap_pde_to_pte(pde, va); 4730 if (wired && (*pte & PG_W) == 0) { 4731 pmap->pm_stats.wired_count++; 4732 atomic_set_long(pte, PG_W); 4733 } else if (!wired && (*pte & PG_W) != 0) { 4734 pmap->pm_stats.wired_count--; 4735 atomic_clear_long(pte, PG_W); 4736 } 4737out: 4738 if (pv_lists_locked) 4739 rw_runlock(&pvh_global_lock); 4740 PMAP_UNLOCK(pmap); 4741} 4742 4743/* 4744 * Copy the range specified by src_addr/len 4745 * from the source map to the range dst_addr/len 4746 * in the destination map. 4747 * 4748 * This routine is only advisory and need not do anything. 4749 */ 4750 4751void 4752pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 4753 vm_offset_t src_addr) 4754{ 4755 struct rwlock *lock; 4756 struct spglist free; 4757 vm_offset_t addr; 4758 vm_offset_t end_addr = src_addr + len; 4759 vm_offset_t va_next; 4760 pt_entry_t PG_A, PG_M, PG_V; 4761 4762 if (dst_addr != src_addr) 4763 return; 4764 4765 if (dst_pmap->pm_type != src_pmap->pm_type) 4766 return; 4767 4768 /* 4769 * EPT page table entries that require emulation of A/D bits are 4770 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although 4771 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit 4772 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT 4773 * implementations flag an EPT misconfiguration for exec-only 4774 * mappings we skip this function entirely for emulated pmaps. 4775 */ 4776 if (pmap_emulate_ad_bits(dst_pmap)) 4777 return; 4778 4779 lock = NULL; 4780 rw_rlock(&pvh_global_lock); 4781 if (dst_pmap < src_pmap) { 4782 PMAP_LOCK(dst_pmap); 4783 PMAP_LOCK(src_pmap); 4784 } else { 4785 PMAP_LOCK(src_pmap); 4786 PMAP_LOCK(dst_pmap); 4787 } 4788 4789 PG_A = pmap_accessed_bit(dst_pmap); 4790 PG_M = pmap_modified_bit(dst_pmap); 4791 PG_V = pmap_valid_bit(dst_pmap); 4792 4793 for (addr = src_addr; addr < end_addr; addr = va_next) { 4794 pt_entry_t *src_pte, *dst_pte; 4795 vm_page_t dstmpde, dstmpte, srcmpte; 4796 pml4_entry_t *pml4e; 4797 pdp_entry_t *pdpe; 4798 pd_entry_t srcptepaddr, *pde; 4799 4800 KASSERT(addr < UPT_MIN_ADDRESS, 4801 ("pmap_copy: invalid to pmap_copy page tables")); 4802 4803 pml4e = pmap_pml4e(src_pmap, addr); 4804 if ((*pml4e & PG_V) == 0) { 4805 va_next = (addr + NBPML4) & ~PML4MASK; 4806 if (va_next < addr) 4807 va_next = end_addr; 4808 continue; 4809 } 4810 4811 pdpe = pmap_pml4e_to_pdpe(pml4e, addr); 4812 if ((*pdpe & PG_V) == 0) { 4813 va_next = (addr + NBPDP) & ~PDPMASK; 4814 if (va_next < addr) 4815 va_next = end_addr; 4816 continue; 4817 } 4818 4819 va_next = (addr + NBPDR) & ~PDRMASK; 4820 if (va_next < addr) 4821 va_next = end_addr; 4822 4823 pde = pmap_pdpe_to_pde(pdpe, addr); 4824 srcptepaddr = *pde; 4825 if (srcptepaddr == 0) 4826 continue; 4827 4828 if (srcptepaddr & PG_PS) { 4829 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr) 4830 continue; 4831 dstmpde = pmap_allocpde(dst_pmap, addr, NULL); 4832 if (dstmpde == NULL) 4833 break; 4834 pde = (pd_entry_t *) 4835 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde)); 4836 pde = &pde[pmap_pde_index(addr)]; 4837 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 || 4838 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr & 4839 PG_PS_FRAME, &lock))) { 4840 *pde = srcptepaddr & ~PG_W; 4841 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE); 4842 } else 4843 dstmpde->wire_count--; 4844 continue; 4845 } 4846 4847 srcptepaddr &= PG_FRAME; 4848 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr); 4849 KASSERT(srcmpte->wire_count > 0, 4850 ("pmap_copy: source page table page is unused")); 4851 4852 if (va_next > end_addr) 4853 va_next = end_addr; 4854 4855 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr); 4856 src_pte = &src_pte[pmap_pte_index(addr)]; 4857 dstmpte = NULL; 4858 while (addr < va_next) { 4859 pt_entry_t ptetemp; 4860 ptetemp = *src_pte; 4861 /* 4862 * we only virtual copy managed pages 4863 */ 4864 if ((ptetemp & PG_MANAGED) != 0) { 4865 if (dstmpte != NULL && 4866 dstmpte->pindex == pmap_pde_pindex(addr)) 4867 dstmpte->wire_count++; 4868 else if ((dstmpte = pmap_allocpte(dst_pmap, 4869 addr, NULL)) == NULL) 4870 goto out; 4871 dst_pte = (pt_entry_t *) 4872 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte)); 4873 dst_pte = &dst_pte[pmap_pte_index(addr)]; 4874 if (*dst_pte == 0 && 4875 pmap_try_insert_pv_entry(dst_pmap, addr, 4876 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), 4877 &lock)) { 4878 /* 4879 * Clear the wired, modified, and 4880 * accessed (referenced) bits 4881 * during the copy. 4882 */ 4883 *dst_pte = ptetemp & ~(PG_W | PG_M | 4884 PG_A); 4885 pmap_resident_count_inc(dst_pmap, 1); 4886 } else { 4887 SLIST_INIT(&free); 4888 if (pmap_unwire_ptp(dst_pmap, addr, 4889 dstmpte, &free)) { 4890 pmap_invalidate_page(dst_pmap, 4891 addr); 4892 pmap_free_zero_pages(&free); 4893 } 4894 goto out; 4895 } 4896 if (dstmpte->wire_count >= srcmpte->wire_count) 4897 break; 4898 } 4899 addr += PAGE_SIZE; 4900 src_pte++; 4901 } 4902 } 4903out: 4904 if (lock != NULL) 4905 rw_wunlock(lock); 4906 rw_runlock(&pvh_global_lock); 4907 PMAP_UNLOCK(src_pmap); 4908 PMAP_UNLOCK(dst_pmap); 4909} 4910 4911/* 4912 * pmap_zero_page zeros the specified hardware page by mapping 4913 * the page into KVM and using bzero to clear its contents. 4914 */ 4915void 4916pmap_zero_page(vm_page_t m) 4917{ 4918 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 4919 4920 pagezero((void *)va); 4921} 4922 4923/* 4924 * pmap_zero_page_area zeros the specified hardware page by mapping 4925 * the page into KVM and using bzero to clear its contents. 4926 * 4927 * off and size may not cover an area beyond a single hardware page. 4928 */ 4929void 4930pmap_zero_page_area(vm_page_t m, int off, int size) 4931{ 4932 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 4933 4934 if (off == 0 && size == PAGE_SIZE) 4935 pagezero((void *)va); 4936 else 4937 bzero((char *)va + off, size); 4938} 4939 4940/* 4941 * pmap_zero_page_idle zeros the specified hardware page by mapping 4942 * the page into KVM and using bzero to clear its contents. This 4943 * is intended to be called from the vm_pagezero process only and 4944 * outside of Giant. 4945 */ 4946void 4947pmap_zero_page_idle(vm_page_t m) 4948{ 4949 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 4950 4951 pagezero((void *)va); 4952} 4953 4954/* 4955 * pmap_copy_page copies the specified (machine independent) 4956 * page by mapping the page into virtual memory and using 4957 * bcopy to copy the page, one machine dependent page at a 4958 * time. 4959 */ 4960void 4961pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 4962{ 4963 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc)); 4964 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst)); 4965 4966 pagecopy((void *)src, (void *)dst); 4967} 4968 4969int unmapped_buf_allowed = 1; 4970 4971void 4972pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 4973 vm_offset_t b_offset, int xfersize) 4974{ 4975 void *a_cp, *b_cp; 4976 vm_offset_t a_pg_offset, b_pg_offset; 4977 int cnt; 4978 4979 while (xfersize > 0) { 4980 a_pg_offset = a_offset & PAGE_MASK; 4981 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 4982 a_cp = (char *)PHYS_TO_DMAP(ma[a_offset >> PAGE_SHIFT]-> 4983 phys_addr) + a_pg_offset; 4984 b_pg_offset = b_offset & PAGE_MASK; 4985 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 4986 b_cp = (char *)PHYS_TO_DMAP(mb[b_offset >> PAGE_SHIFT]-> 4987 phys_addr) + b_pg_offset; 4988 bcopy(a_cp, b_cp, cnt); 4989 a_offset += cnt; 4990 b_offset += cnt; 4991 xfersize -= cnt; 4992 } 4993} 4994 4995/* 4996 * Returns true if the pmap's pv is one of the first 4997 * 16 pvs linked to from this page. This count may 4998 * be changed upwards or downwards in the future; it 4999 * is only necessary that true be returned for a small 5000 * subset of pmaps for proper page aging. 5001 */ 5002boolean_t 5003pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 5004{ 5005 struct md_page *pvh; 5006 struct rwlock *lock; 5007 pv_entry_t pv; 5008 int loops = 0; 5009 boolean_t rv; 5010 5011 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5012 ("pmap_page_exists_quick: page %p is not managed", m)); 5013 rv = FALSE; 5014 rw_rlock(&pvh_global_lock); 5015 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5016 rw_rlock(lock); 5017 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5018 if (PV_PMAP(pv) == pmap) { 5019 rv = TRUE; 5020 break; 5021 } 5022 loops++; 5023 if (loops >= 16) 5024 break; 5025 } 5026 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) { 5027 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 5028 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 5029 if (PV_PMAP(pv) == pmap) { 5030 rv = TRUE; 5031 break; 5032 } 5033 loops++; 5034 if (loops >= 16) 5035 break; 5036 } 5037 } 5038 rw_runlock(lock); 5039 rw_runlock(&pvh_global_lock); 5040 return (rv); 5041} 5042 5043/* 5044 * pmap_page_wired_mappings: 5045 * 5046 * Return the number of managed mappings to the given physical page 5047 * that are wired. 5048 */ 5049int 5050pmap_page_wired_mappings(vm_page_t m) 5051{ 5052 struct rwlock *lock; 5053 struct md_page *pvh; 5054 pmap_t pmap; 5055 pt_entry_t *pte; 5056 pv_entry_t pv; 5057 int count, md_gen, pvh_gen; 5058 5059 if ((m->oflags & VPO_UNMANAGED) != 0) 5060 return (0); 5061 rw_rlock(&pvh_global_lock); 5062 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5063 rw_rlock(lock); 5064restart: 5065 count = 0; 5066 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5067 pmap = PV_PMAP(pv); 5068 if (!PMAP_TRYLOCK(pmap)) { 5069 md_gen = m->md.pv_gen; 5070 rw_runlock(lock); 5071 PMAP_LOCK(pmap); 5072 rw_rlock(lock); 5073 if (md_gen != m->md.pv_gen) { 5074 PMAP_UNLOCK(pmap); 5075 goto restart; 5076 } 5077 } 5078 pte = pmap_pte(pmap, pv->pv_va); 5079 if ((*pte & PG_W) != 0) 5080 count++; 5081 PMAP_UNLOCK(pmap); 5082 } 5083 if ((m->flags & PG_FICTITIOUS) == 0) { 5084 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 5085 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 5086 pmap = PV_PMAP(pv); 5087 if (!PMAP_TRYLOCK(pmap)) { 5088 md_gen = m->md.pv_gen; 5089 pvh_gen = pvh->pv_gen; 5090 rw_runlock(lock); 5091 PMAP_LOCK(pmap); 5092 rw_rlock(lock); 5093 if (md_gen != m->md.pv_gen || 5094 pvh_gen != pvh->pv_gen) { 5095 PMAP_UNLOCK(pmap); 5096 goto restart; 5097 } 5098 } 5099 pte = pmap_pde(pmap, pv->pv_va); 5100 if ((*pte & PG_W) != 0) 5101 count++; 5102 PMAP_UNLOCK(pmap); 5103 } 5104 } 5105 rw_runlock(lock); 5106 rw_runlock(&pvh_global_lock); 5107 return (count); 5108} 5109 5110/* 5111 * Returns TRUE if the given page is mapped individually or as part of 5112 * a 2mpage. Otherwise, returns FALSE. 5113 */ 5114boolean_t 5115pmap_page_is_mapped(vm_page_t m) 5116{ 5117 struct rwlock *lock; 5118 boolean_t rv; 5119 5120 if ((m->oflags & VPO_UNMANAGED) != 0) 5121 return (FALSE); 5122 rw_rlock(&pvh_global_lock); 5123 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5124 rw_rlock(lock); 5125 rv = !TAILQ_EMPTY(&m->md.pv_list) || 5126 ((m->flags & PG_FICTITIOUS) == 0 && 5127 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list)); 5128 rw_runlock(lock); 5129 rw_runlock(&pvh_global_lock); 5130 return (rv); 5131} 5132 5133/* 5134 * Destroy all managed, non-wired mappings in the given user-space 5135 * pmap. This pmap cannot be active on any processor besides the 5136 * caller. 5137 * 5138 * This function cannot be applied to the kernel pmap. Moreover, it 5139 * is not intended for general use. It is only to be used during 5140 * process termination. Consequently, it can be implemented in ways 5141 * that make it faster than pmap_remove(). First, it can more quickly 5142 * destroy mappings by iterating over the pmap's collection of PV 5143 * entries, rather than searching the page table. Second, it doesn't 5144 * have to test and clear the page table entries atomically, because 5145 * no processor is currently accessing the user address space. In 5146 * particular, a page table entry's dirty bit won't change state once 5147 * this function starts. 5148 */ 5149void 5150pmap_remove_pages(pmap_t pmap) 5151{ 5152 pd_entry_t ptepde; 5153 pt_entry_t *pte, tpte; 5154 pt_entry_t PG_M, PG_RW, PG_V; 5155 struct spglist free; 5156 vm_page_t m, mpte, mt; 5157 pv_entry_t pv; 5158 struct md_page *pvh; 5159 struct pv_chunk *pc, *npc; 5160 struct rwlock *lock; 5161 int64_t bit; 5162 uint64_t inuse, bitmask; 5163 int allfree, field, freed, idx; 5164 boolean_t superpage; 5165 vm_paddr_t pa; 5166 5167 /* 5168 * Assert that the given pmap is only active on the current 5169 * CPU. Unfortunately, we cannot block another CPU from 5170 * activating the pmap while this function is executing. 5171 */ 5172 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap)); 5173#ifdef INVARIANTS 5174 { 5175 cpuset_t other_cpus; 5176 5177 other_cpus = all_cpus; 5178 critical_enter(); 5179 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 5180 CPU_AND(&other_cpus, &pmap->pm_active); 5181 critical_exit(); 5182 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap)); 5183 } 5184#endif 5185 5186 lock = NULL; 5187 PG_M = pmap_modified_bit(pmap); 5188 PG_V = pmap_valid_bit(pmap); 5189 PG_RW = pmap_rw_bit(pmap); 5190 5191 SLIST_INIT(&free); 5192 rw_rlock(&pvh_global_lock); 5193 PMAP_LOCK(pmap); 5194 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 5195 allfree = 1; 5196 freed = 0; 5197 for (field = 0; field < _NPCM; field++) { 5198 inuse = ~pc->pc_map[field] & pc_freemask[field]; 5199 while (inuse != 0) { 5200 bit = bsfq(inuse); 5201 bitmask = 1UL << bit; 5202 idx = field * 64 + bit; 5203 pv = &pc->pc_pventry[idx]; 5204 inuse &= ~bitmask; 5205 5206 pte = pmap_pdpe(pmap, pv->pv_va); 5207 ptepde = *pte; 5208 pte = pmap_pdpe_to_pde(pte, pv->pv_va); 5209 tpte = *pte; 5210 if ((tpte & (PG_PS | PG_V)) == PG_V) { 5211 superpage = FALSE; 5212 ptepde = tpte; 5213 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte & 5214 PG_FRAME); 5215 pte = &pte[pmap_pte_index(pv->pv_va)]; 5216 tpte = *pte; 5217 } else { 5218 /* 5219 * Keep track whether 'tpte' is a 5220 * superpage explicitly instead of 5221 * relying on PG_PS being set. 5222 * 5223 * This is because PG_PS is numerically 5224 * identical to PG_PTE_PAT and thus a 5225 * regular page could be mistaken for 5226 * a superpage. 5227 */ 5228 superpage = TRUE; 5229 } 5230 5231 if ((tpte & PG_V) == 0) { 5232 panic("bad pte va %lx pte %lx", 5233 pv->pv_va, tpte); 5234 } 5235 5236/* 5237 * We cannot remove wired pages from a process' mapping at this time 5238 */ 5239 if (tpte & PG_W) { 5240 allfree = 0; 5241 continue; 5242 } 5243 5244 if (superpage) 5245 pa = tpte & PG_PS_FRAME; 5246 else 5247 pa = tpte & PG_FRAME; 5248 5249 m = PHYS_TO_VM_PAGE(pa); 5250 KASSERT(m->phys_addr == pa, 5251 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 5252 m, (uintmax_t)m->phys_addr, 5253 (uintmax_t)tpte)); 5254 5255 KASSERT((m->flags & PG_FICTITIOUS) != 0 || 5256 m < &vm_page_array[vm_page_array_size], 5257 ("pmap_remove_pages: bad tpte %#jx", 5258 (uintmax_t)tpte)); 5259 5260 pte_clear(pte); 5261 5262 /* 5263 * Update the vm_page_t clean/reference bits. 5264 */ 5265 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 5266 if (superpage) { 5267 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 5268 vm_page_dirty(mt); 5269 } else 5270 vm_page_dirty(m); 5271 } 5272 5273 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m); 5274 5275 /* Mark free */ 5276 pc->pc_map[field] |= bitmask; 5277 if (superpage) { 5278 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE); 5279 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 5280 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 5281 pvh->pv_gen++; 5282 if (TAILQ_EMPTY(&pvh->pv_list)) { 5283 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 5284 if ((mt->aflags & PGA_WRITEABLE) != 0 && 5285 TAILQ_EMPTY(&mt->md.pv_list)) 5286 vm_page_aflag_clear(mt, PGA_WRITEABLE); 5287 } 5288 mpte = pmap_lookup_pt_page(pmap, pv->pv_va); 5289 if (mpte != NULL) { 5290 pmap_remove_pt_page(pmap, mpte); 5291 pmap_resident_count_dec(pmap, 1); 5292 KASSERT(mpte->wire_count == NPTEPG, 5293 ("pmap_remove_pages: pte page wire count error")); 5294 mpte->wire_count = 0; 5295 pmap_add_delayed_free_list(mpte, &free, FALSE); 5296 atomic_subtract_int(&cnt.v_wire_count, 1); 5297 } 5298 } else { 5299 pmap_resident_count_dec(pmap, 1); 5300 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 5301 m->md.pv_gen++; 5302 if ((m->aflags & PGA_WRITEABLE) != 0 && 5303 TAILQ_EMPTY(&m->md.pv_list) && 5304 (m->flags & PG_FICTITIOUS) == 0) { 5305 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 5306 if (TAILQ_EMPTY(&pvh->pv_list)) 5307 vm_page_aflag_clear(m, PGA_WRITEABLE); 5308 } 5309 } 5310 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free); 5311 freed++; 5312 } 5313 } 5314 PV_STAT(atomic_add_long(&pv_entry_frees, freed)); 5315 PV_STAT(atomic_add_int(&pv_entry_spare, freed)); 5316 PV_STAT(atomic_subtract_long(&pv_entry_count, freed)); 5317 if (allfree) { 5318 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 5319 free_pv_chunk(pc); 5320 } 5321 } 5322 if (lock != NULL) 5323 rw_wunlock(lock); 5324 pmap_invalidate_all(pmap); 5325 rw_runlock(&pvh_global_lock); 5326 PMAP_UNLOCK(pmap); 5327 pmap_free_zero_pages(&free); 5328} 5329 5330static boolean_t 5331pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified) 5332{ 5333 struct rwlock *lock; 5334 pv_entry_t pv; 5335 struct md_page *pvh; 5336 pt_entry_t *pte, mask; 5337 pt_entry_t PG_A, PG_M, PG_RW, PG_V; 5338 pmap_t pmap; 5339 int md_gen, pvh_gen; 5340 boolean_t rv; 5341 5342 rv = FALSE; 5343 rw_rlock(&pvh_global_lock); 5344 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5345 rw_rlock(lock); 5346restart: 5347 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5348 pmap = PV_PMAP(pv); 5349 if (!PMAP_TRYLOCK(pmap)) { 5350 md_gen = m->md.pv_gen; 5351 rw_runlock(lock); 5352 PMAP_LOCK(pmap); 5353 rw_rlock(lock); 5354 if (md_gen != m->md.pv_gen) { 5355 PMAP_UNLOCK(pmap); 5356 goto restart; 5357 } 5358 } 5359 pte = pmap_pte(pmap, pv->pv_va); 5360 mask = 0; 5361 if (modified) { 5362 PG_M = pmap_modified_bit(pmap); 5363 PG_RW = pmap_rw_bit(pmap); 5364 mask |= PG_RW | PG_M; 5365 } 5366 if (accessed) { 5367 PG_A = pmap_accessed_bit(pmap); 5368 PG_V = pmap_valid_bit(pmap); 5369 mask |= PG_V | PG_A; 5370 } 5371 rv = (*pte & mask) == mask; 5372 PMAP_UNLOCK(pmap); 5373 if (rv) 5374 goto out; 5375 } 5376 if ((m->flags & PG_FICTITIOUS) == 0) { 5377 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 5378 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 5379 pmap = PV_PMAP(pv); 5380 if (!PMAP_TRYLOCK(pmap)) { 5381 md_gen = m->md.pv_gen; 5382 pvh_gen = pvh->pv_gen; 5383 rw_runlock(lock); 5384 PMAP_LOCK(pmap); 5385 rw_rlock(lock); 5386 if (md_gen != m->md.pv_gen || 5387 pvh_gen != pvh->pv_gen) { 5388 PMAP_UNLOCK(pmap); 5389 goto restart; 5390 } 5391 } 5392 pte = pmap_pde(pmap, pv->pv_va); 5393 mask = 0; 5394 if (modified) { 5395 PG_M = pmap_modified_bit(pmap); 5396 PG_RW = pmap_rw_bit(pmap); 5397 mask |= PG_RW | PG_M; 5398 } 5399 if (accessed) { 5400 PG_A = pmap_accessed_bit(pmap); 5401 PG_V = pmap_valid_bit(pmap); 5402 mask |= PG_V | PG_A; 5403 } 5404 rv = (*pte & mask) == mask; 5405 PMAP_UNLOCK(pmap); 5406 if (rv) 5407 goto out; 5408 } 5409 } 5410out: 5411 rw_runlock(lock); 5412 rw_runlock(&pvh_global_lock); 5413 return (rv); 5414} 5415 5416/* 5417 * pmap_is_modified: 5418 * 5419 * Return whether or not the specified physical page was modified 5420 * in any physical maps. 5421 */ 5422boolean_t 5423pmap_is_modified(vm_page_t m) 5424{ 5425 5426 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5427 ("pmap_is_modified: page %p is not managed", m)); 5428 5429 /* 5430 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 5431 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 5432 * is clear, no PTEs can have PG_M set. 5433 */ 5434 VM_OBJECT_ASSERT_WLOCKED(m->object); 5435 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 5436 return (FALSE); 5437 return (pmap_page_test_mappings(m, FALSE, TRUE)); 5438} 5439 5440/* 5441 * pmap_is_prefaultable: 5442 * 5443 * Return whether or not the specified virtual address is eligible 5444 * for prefault. 5445 */ 5446boolean_t 5447pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 5448{ 5449 pd_entry_t *pde; 5450 pt_entry_t *pte, PG_V; 5451 boolean_t rv; 5452 5453 PG_V = pmap_valid_bit(pmap); 5454 rv = FALSE; 5455 PMAP_LOCK(pmap); 5456 pde = pmap_pde(pmap, addr); 5457 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) { 5458 pte = pmap_pde_to_pte(pde, addr); 5459 rv = (*pte & PG_V) == 0; 5460 } 5461 PMAP_UNLOCK(pmap); 5462 return (rv); 5463} 5464 5465/* 5466 * pmap_is_referenced: 5467 * 5468 * Return whether or not the specified physical page was referenced 5469 * in any physical maps. 5470 */ 5471boolean_t 5472pmap_is_referenced(vm_page_t m) 5473{ 5474 5475 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5476 ("pmap_is_referenced: page %p is not managed", m)); 5477 return (pmap_page_test_mappings(m, TRUE, FALSE)); 5478} 5479 5480/* 5481 * Clear the write and modified bits in each of the given page's mappings. 5482 */ 5483void 5484pmap_remove_write(vm_page_t m) 5485{ 5486 struct md_page *pvh; 5487 pmap_t pmap; 5488 struct rwlock *lock; 5489 pv_entry_t next_pv, pv; 5490 pd_entry_t *pde; 5491 pt_entry_t oldpte, *pte, PG_M, PG_RW; 5492 vm_offset_t va; 5493 int pvh_gen, md_gen; 5494 5495 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5496 ("pmap_remove_write: page %p is not managed", m)); 5497 5498 /* 5499 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 5500 * set by another thread while the object is locked. Thus, 5501 * if PGA_WRITEABLE is clear, no page table entries need updating. 5502 */ 5503 VM_OBJECT_ASSERT_WLOCKED(m->object); 5504 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 5505 return; 5506 rw_rlock(&pvh_global_lock); 5507 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5508 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 5509retry_pv_loop: 5510 rw_wlock(lock); 5511 if ((m->flags & PG_FICTITIOUS) != 0) 5512 goto small_mappings; 5513 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 5514 pmap = PV_PMAP(pv); 5515 if (!PMAP_TRYLOCK(pmap)) { 5516 pvh_gen = pvh->pv_gen; 5517 rw_wunlock(lock); 5518 PMAP_LOCK(pmap); 5519 rw_wlock(lock); 5520 if (pvh_gen != pvh->pv_gen) { 5521 PMAP_UNLOCK(pmap); 5522 rw_wunlock(lock); 5523 goto retry_pv_loop; 5524 } 5525 } 5526 PG_RW = pmap_rw_bit(pmap); 5527 va = pv->pv_va; 5528 pde = pmap_pde(pmap, va); 5529 if ((*pde & PG_RW) != 0) 5530 (void)pmap_demote_pde_locked(pmap, pde, va, &lock); 5531 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 5532 ("inconsistent pv lock %p %p for page %p", 5533 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 5534 PMAP_UNLOCK(pmap); 5535 } 5536small_mappings: 5537 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5538 pmap = PV_PMAP(pv); 5539 if (!PMAP_TRYLOCK(pmap)) { 5540 pvh_gen = pvh->pv_gen; 5541 md_gen = m->md.pv_gen; 5542 rw_wunlock(lock); 5543 PMAP_LOCK(pmap); 5544 rw_wlock(lock); 5545 if (pvh_gen != pvh->pv_gen || 5546 md_gen != m->md.pv_gen) { 5547 PMAP_UNLOCK(pmap); 5548 rw_wunlock(lock); 5549 goto retry_pv_loop; 5550 } 5551 } 5552 PG_M = pmap_modified_bit(pmap); 5553 PG_RW = pmap_rw_bit(pmap); 5554 pde = pmap_pde(pmap, pv->pv_va); 5555 KASSERT((*pde & PG_PS) == 0, 5556 ("pmap_remove_write: found a 2mpage in page %p's pv list", 5557 m)); 5558 pte = pmap_pde_to_pte(pde, pv->pv_va); 5559retry: 5560 oldpte = *pte; 5561 if (oldpte & PG_RW) { 5562 if (!atomic_cmpset_long(pte, oldpte, oldpte & 5563 ~(PG_RW | PG_M))) 5564 goto retry; 5565 if ((oldpte & PG_M) != 0) 5566 vm_page_dirty(m); 5567 pmap_invalidate_page(pmap, pv->pv_va); 5568 } 5569 PMAP_UNLOCK(pmap); 5570 } 5571 rw_wunlock(lock); 5572 vm_page_aflag_clear(m, PGA_WRITEABLE); 5573 rw_runlock(&pvh_global_lock); 5574} 5575 5576static __inline boolean_t 5577safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte) 5578{ 5579 5580 if (!pmap_emulate_ad_bits(pmap)) 5581 return (TRUE); 5582 5583 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type)); 5584 5585 /* 5586 * RWX = 010 or 110 will cause an unconditional EPT misconfiguration 5587 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared 5588 * if the EPT_PG_WRITE bit is set. 5589 */ 5590 if ((pte & EPT_PG_WRITE) != 0) 5591 return (FALSE); 5592 5593 /* 5594 * RWX = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set. 5595 */ 5596 if ((pte & EPT_PG_EXECUTE) == 0 || 5597 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0)) 5598 return (TRUE); 5599 else 5600 return (FALSE); 5601} 5602 5603#define PMAP_TS_REFERENCED_MAX 5 5604 5605/* 5606 * pmap_ts_referenced: 5607 * 5608 * Return a count of reference bits for a page, clearing those bits. 5609 * It is not necessary for every reference bit to be cleared, but it 5610 * is necessary that 0 only be returned when there are truly no 5611 * reference bits set. 5612 * 5613 * XXX: The exact number of bits to check and clear is a matter that 5614 * should be tested and standardized at some point in the future for 5615 * optimal aging of shared pages. 5616 */ 5617int 5618pmap_ts_referenced(vm_page_t m) 5619{ 5620 struct md_page *pvh; 5621 pv_entry_t pv, pvf; 5622 pmap_t pmap; 5623 struct rwlock *lock; 5624 pd_entry_t oldpde, *pde; 5625 pt_entry_t *pte, PG_A; 5626 vm_offset_t va; 5627 vm_paddr_t pa; 5628 int cleared, md_gen, not_cleared, pvh_gen; 5629 struct spglist free; 5630 boolean_t demoted; 5631 5632 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5633 ("pmap_ts_referenced: page %p is not managed", m)); 5634 SLIST_INIT(&free); 5635 cleared = 0; 5636 pa = VM_PAGE_TO_PHYS(m); 5637 lock = PHYS_TO_PV_LIST_LOCK(pa); 5638 pvh = pa_to_pvh(pa); 5639 rw_rlock(&pvh_global_lock); 5640 rw_wlock(lock); 5641retry: 5642 not_cleared = 0; 5643 if ((m->flags & PG_FICTITIOUS) != 0 || 5644 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL) 5645 goto small_mappings; 5646 pv = pvf; 5647 do { 5648 if (pvf == NULL) 5649 pvf = pv; 5650 pmap = PV_PMAP(pv); 5651 if (!PMAP_TRYLOCK(pmap)) { 5652 pvh_gen = pvh->pv_gen; 5653 rw_wunlock(lock); 5654 PMAP_LOCK(pmap); 5655 rw_wlock(lock); 5656 if (pvh_gen != pvh->pv_gen) { 5657 PMAP_UNLOCK(pmap); 5658 goto retry; 5659 } 5660 } 5661 PG_A = pmap_accessed_bit(pmap); 5662 va = pv->pv_va; 5663 pde = pmap_pde(pmap, pv->pv_va); 5664 oldpde = *pde; 5665 if ((*pde & PG_A) != 0) { 5666 /* 5667 * Since this reference bit is shared by 512 4KB 5668 * pages, it should not be cleared every time it is 5669 * tested. Apply a simple "hash" function on the 5670 * physical page number, the virtual superpage number, 5671 * and the pmap address to select one 4KB page out of 5672 * the 512 on which testing the reference bit will 5673 * result in clearing that reference bit. This 5674 * function is designed to avoid the selection of the 5675 * same 4KB page for every 2MB page mapping. 5676 * 5677 * On demotion, a mapping that hasn't been referenced 5678 * is simply destroyed. To avoid the possibility of a 5679 * subsequent page fault on a demoted wired mapping, 5680 * always leave its reference bit set. Moreover, 5681 * since the superpage is wired, the current state of 5682 * its reference bit won't affect page replacement. 5683 */ 5684 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^ 5685 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 && 5686 (*pde & PG_W) == 0) { 5687 if (safe_to_clear_referenced(pmap, oldpde)) { 5688 atomic_clear_long(pde, PG_A); 5689 pmap_invalidate_page(pmap, pv->pv_va); 5690 demoted = FALSE; 5691 } else if (pmap_demote_pde_locked(pmap, pde, 5692 pv->pv_va, &lock)) { 5693 /* 5694 * Remove the mapping to a single page 5695 * so that a subsequent access may 5696 * repromote. Since the underlying 5697 * page table page is fully populated, 5698 * this removal never frees a page 5699 * table page. 5700 */ 5701 demoted = TRUE; 5702 va += VM_PAGE_TO_PHYS(m) - (oldpde & 5703 PG_PS_FRAME); 5704 pte = pmap_pde_to_pte(pde, va); 5705 pmap_remove_pte(pmap, pte, va, *pde, 5706 NULL, &lock); 5707 pmap_invalidate_page(pmap, va); 5708 } else 5709 demoted = TRUE; 5710 5711 if (demoted) { 5712 /* 5713 * The superpage mapping was removed 5714 * entirely and therefore 'pv' is no 5715 * longer valid. 5716 */ 5717 if (pvf == pv) 5718 pvf = NULL; 5719 pv = NULL; 5720 } 5721 cleared++; 5722 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 5723 ("inconsistent pv lock %p %p for page %p", 5724 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 5725 } else 5726 not_cleared++; 5727 } 5728 PMAP_UNLOCK(pmap); 5729 /* Rotate the PV list if it has more than one entry. */ 5730 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) { 5731 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 5732 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 5733 pvh->pv_gen++; 5734 } 5735 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX) 5736 goto out; 5737 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf); 5738small_mappings: 5739 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL) 5740 goto out; 5741 pv = pvf; 5742 do { 5743 if (pvf == NULL) 5744 pvf = pv; 5745 pmap = PV_PMAP(pv); 5746 if (!PMAP_TRYLOCK(pmap)) { 5747 pvh_gen = pvh->pv_gen; 5748 md_gen = m->md.pv_gen; 5749 rw_wunlock(lock); 5750 PMAP_LOCK(pmap); 5751 rw_wlock(lock); 5752 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 5753 PMAP_UNLOCK(pmap); 5754 goto retry; 5755 } 5756 } 5757 PG_A = pmap_accessed_bit(pmap); 5758 pde = pmap_pde(pmap, pv->pv_va); 5759 KASSERT((*pde & PG_PS) == 0, 5760 ("pmap_ts_referenced: found a 2mpage in page %p's pv list", 5761 m)); 5762 pte = pmap_pde_to_pte(pde, pv->pv_va); 5763 if ((*pte & PG_A) != 0) { 5764 if (safe_to_clear_referenced(pmap, *pte)) { 5765 atomic_clear_long(pte, PG_A); 5766 pmap_invalidate_page(pmap, pv->pv_va); 5767 cleared++; 5768 } else if ((*pte & PG_W) == 0) { 5769 /* 5770 * Wired pages cannot be paged out so 5771 * doing accessed bit emulation for 5772 * them is wasted effort. We do the 5773 * hard work for unwired pages only. 5774 */ 5775 pmap_remove_pte(pmap, pte, pv->pv_va, 5776 *pde, &free, &lock); 5777 pmap_invalidate_page(pmap, pv->pv_va); 5778 cleared++; 5779 if (pvf == pv) 5780 pvf = NULL; 5781 pv = NULL; 5782 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 5783 ("inconsistent pv lock %p %p for page %p", 5784 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 5785 } else 5786 not_cleared++; 5787 } 5788 PMAP_UNLOCK(pmap); 5789 /* Rotate the PV list if it has more than one entry. */ 5790 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) { 5791 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 5792 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 5793 m->md.pv_gen++; 5794 } 5795 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared + 5796 not_cleared < PMAP_TS_REFERENCED_MAX); 5797out: 5798 rw_wunlock(lock); 5799 rw_runlock(&pvh_global_lock); 5800 pmap_free_zero_pages(&free); 5801 return (cleared + not_cleared); 5802} 5803 5804/* 5805 * Apply the given advice to the specified range of addresses within the 5806 * given pmap. Depending on the advice, clear the referenced and/or 5807 * modified flags in each mapping and set the mapped page's dirty field. 5808 */ 5809void 5810pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 5811{ 5812 struct rwlock *lock; 5813 pml4_entry_t *pml4e; 5814 pdp_entry_t *pdpe; 5815 pd_entry_t oldpde, *pde; 5816 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V; 5817 vm_offset_t va_next; 5818 vm_page_t m; 5819 boolean_t anychanged, pv_lists_locked; 5820 5821 if (advice != MADV_DONTNEED && advice != MADV_FREE) 5822 return; 5823 5824 /* 5825 * A/D bit emulation requires an alternate code path when clearing 5826 * the modified and accessed bits below. Since this function is 5827 * advisory in nature we skip it entirely for pmaps that require 5828 * A/D bit emulation. 5829 */ 5830 if (pmap_emulate_ad_bits(pmap)) 5831 return; 5832 5833 PG_A = pmap_accessed_bit(pmap); 5834 PG_G = pmap_global_bit(pmap); 5835 PG_M = pmap_modified_bit(pmap); 5836 PG_V = pmap_valid_bit(pmap); 5837 PG_RW = pmap_rw_bit(pmap); 5838 5839 pv_lists_locked = FALSE; 5840resume: 5841 anychanged = FALSE; 5842 PMAP_LOCK(pmap); 5843 for (; sva < eva; sva = va_next) { 5844 pml4e = pmap_pml4e(pmap, sva); 5845 if ((*pml4e & PG_V) == 0) { 5846 va_next = (sva + NBPML4) & ~PML4MASK; 5847 if (va_next < sva) 5848 va_next = eva; 5849 continue; 5850 } 5851 pdpe = pmap_pml4e_to_pdpe(pml4e, sva); 5852 if ((*pdpe & PG_V) == 0) { 5853 va_next = (sva + NBPDP) & ~PDPMASK; 5854 if (va_next < sva) 5855 va_next = eva; 5856 continue; 5857 } 5858 va_next = (sva + NBPDR) & ~PDRMASK; 5859 if (va_next < sva) 5860 va_next = eva; 5861 pde = pmap_pdpe_to_pde(pdpe, sva); 5862 oldpde = *pde; 5863 if ((oldpde & PG_V) == 0) 5864 continue; 5865 else if ((oldpde & PG_PS) != 0) { 5866 if ((oldpde & PG_MANAGED) == 0) 5867 continue; 5868 if (!pv_lists_locked) { 5869 pv_lists_locked = TRUE; 5870 if (!rw_try_rlock(&pvh_global_lock)) { 5871 if (anychanged) 5872 pmap_invalidate_all(pmap); 5873 PMAP_UNLOCK(pmap); 5874 rw_rlock(&pvh_global_lock); 5875 goto resume; 5876 } 5877 } 5878 lock = NULL; 5879 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) { 5880 if (lock != NULL) 5881 rw_wunlock(lock); 5882 5883 /* 5884 * The large page mapping was destroyed. 5885 */ 5886 continue; 5887 } 5888 5889 /* 5890 * Unless the page mappings are wired, remove the 5891 * mapping to a single page so that a subsequent 5892 * access may repromote. Since the underlying page 5893 * table page is fully populated, this removal never 5894 * frees a page table page. 5895 */ 5896 if ((oldpde & PG_W) == 0) { 5897 pte = pmap_pde_to_pte(pde, sva); 5898 KASSERT((*pte & PG_V) != 0, 5899 ("pmap_advise: invalid PTE")); 5900 pmap_remove_pte(pmap, pte, sva, *pde, NULL, 5901 &lock); 5902 anychanged = TRUE; 5903 } 5904 if (lock != NULL) 5905 rw_wunlock(lock); 5906 } 5907 if (va_next > eva) 5908 va_next = eva; 5909 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 5910 sva += PAGE_SIZE) { 5911 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | 5912 PG_V)) 5913 continue; 5914 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 5915 if (advice == MADV_DONTNEED) { 5916 /* 5917 * Future calls to pmap_is_modified() 5918 * can be avoided by making the page 5919 * dirty now. 5920 */ 5921 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME); 5922 vm_page_dirty(m); 5923 } 5924 atomic_clear_long(pte, PG_M | PG_A); 5925 } else if ((*pte & PG_A) != 0) 5926 atomic_clear_long(pte, PG_A); 5927 else 5928 continue; 5929 if ((*pte & PG_G) != 0) 5930 pmap_invalidate_page(pmap, sva); 5931 else 5932 anychanged = TRUE; 5933 } 5934 } 5935 if (anychanged) 5936 pmap_invalidate_all(pmap); 5937 if (pv_lists_locked) 5938 rw_runlock(&pvh_global_lock); 5939 PMAP_UNLOCK(pmap); 5940} 5941 5942/* 5943 * Clear the modify bits on the specified physical page. 5944 */ 5945void 5946pmap_clear_modify(vm_page_t m) 5947{ 5948 struct md_page *pvh; 5949 pmap_t pmap; 5950 pv_entry_t next_pv, pv; 5951 pd_entry_t oldpde, *pde; 5952 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V; 5953 struct rwlock *lock; 5954 vm_offset_t va; 5955 int md_gen, pvh_gen; 5956 5957 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5958 ("pmap_clear_modify: page %p is not managed", m)); 5959 VM_OBJECT_ASSERT_WLOCKED(m->object); 5960 KASSERT(!vm_page_xbusied(m), 5961 ("pmap_clear_modify: page %p is exclusive busied", m)); 5962 5963 /* 5964 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 5965 * If the object containing the page is locked and the page is not 5966 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 5967 */ 5968 if ((m->aflags & PGA_WRITEABLE) == 0) 5969 return; 5970 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 5971 rw_rlock(&pvh_global_lock); 5972 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5973 rw_wlock(lock); 5974restart: 5975 if ((m->flags & PG_FICTITIOUS) != 0) 5976 goto small_mappings; 5977 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 5978 pmap = PV_PMAP(pv); 5979 if (!PMAP_TRYLOCK(pmap)) { 5980 pvh_gen = pvh->pv_gen; 5981 rw_wunlock(lock); 5982 PMAP_LOCK(pmap); 5983 rw_wlock(lock); 5984 if (pvh_gen != pvh->pv_gen) { 5985 PMAP_UNLOCK(pmap); 5986 goto restart; 5987 } 5988 } 5989 PG_M = pmap_modified_bit(pmap); 5990 PG_V = pmap_valid_bit(pmap); 5991 PG_RW = pmap_rw_bit(pmap); 5992 va = pv->pv_va; 5993 pde = pmap_pde(pmap, va); 5994 oldpde = *pde; 5995 if ((oldpde & PG_RW) != 0) { 5996 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) { 5997 if ((oldpde & PG_W) == 0) { 5998 /* 5999 * Write protect the mapping to a 6000 * single page so that a subsequent 6001 * write access may repromote. 6002 */ 6003 va += VM_PAGE_TO_PHYS(m) - (oldpde & 6004 PG_PS_FRAME); 6005 pte = pmap_pde_to_pte(pde, va); 6006 oldpte = *pte; 6007 if ((oldpte & PG_V) != 0) { 6008 while (!atomic_cmpset_long(pte, 6009 oldpte, 6010 oldpte & ~(PG_M | PG_RW))) 6011 oldpte = *pte; 6012 vm_page_dirty(m); 6013 pmap_invalidate_page(pmap, va); 6014 } 6015 } 6016 } 6017 } 6018 PMAP_UNLOCK(pmap); 6019 } 6020small_mappings: 6021 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 6022 pmap = PV_PMAP(pv); 6023 if (!PMAP_TRYLOCK(pmap)) { 6024 md_gen = m->md.pv_gen; 6025 pvh_gen = pvh->pv_gen; 6026 rw_wunlock(lock); 6027 PMAP_LOCK(pmap); 6028 rw_wlock(lock); 6029 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 6030 PMAP_UNLOCK(pmap); 6031 goto restart; 6032 } 6033 } 6034 PG_M = pmap_modified_bit(pmap); 6035 PG_RW = pmap_rw_bit(pmap); 6036 pde = pmap_pde(pmap, pv->pv_va); 6037 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 6038 " a 2mpage in page %p's pv list", m)); 6039 pte = pmap_pde_to_pte(pde, pv->pv_va); 6040 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 6041 atomic_clear_long(pte, PG_M); 6042 pmap_invalidate_page(pmap, pv->pv_va); 6043 } 6044 PMAP_UNLOCK(pmap); 6045 } 6046 rw_wunlock(lock); 6047 rw_runlock(&pvh_global_lock); 6048} 6049 6050/* 6051 * Miscellaneous support routines follow 6052 */ 6053 6054/* Adjust the cache mode for a 4KB page mapped via a PTE. */ 6055static __inline void 6056pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask) 6057{ 6058 u_int opte, npte; 6059 6060 /* 6061 * The cache mode bits are all in the low 32-bits of the 6062 * PTE, so we can just spin on updating the low 32-bits. 6063 */ 6064 do { 6065 opte = *(u_int *)pte; 6066 npte = opte & ~mask; 6067 npte |= cache_bits; 6068 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte)); 6069} 6070 6071/* Adjust the cache mode for a 2MB page mapped via a PDE. */ 6072static __inline void 6073pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask) 6074{ 6075 u_int opde, npde; 6076 6077 /* 6078 * The cache mode bits are all in the low 32-bits of the 6079 * PDE, so we can just spin on updating the low 32-bits. 6080 */ 6081 do { 6082 opde = *(u_int *)pde; 6083 npde = opde & ~mask; 6084 npde |= cache_bits; 6085 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde)); 6086} 6087 6088/* 6089 * Map a set of physical memory pages into the kernel virtual 6090 * address space. Return a pointer to where it is mapped. This 6091 * routine is intended to be used for mapping device memory, 6092 * NOT real memory. 6093 */ 6094void * 6095pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 6096{ 6097 vm_offset_t va, offset; 6098 vm_size_t tmpsize; 6099 6100 /* 6101 * If the specified range of physical addresses fits within the direct 6102 * map window, use the direct map. 6103 */ 6104 if (pa < dmaplimit && pa + size < dmaplimit) { 6105 va = PHYS_TO_DMAP(pa); 6106 if (!pmap_change_attr(va, size, mode)) 6107 return ((void *)va); 6108 } 6109 offset = pa & PAGE_MASK; 6110 size = round_page(offset + size); 6111 va = kva_alloc(size); 6112 if (!va) 6113 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 6114 pa = trunc_page(pa); 6115 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 6116 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 6117 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 6118 pmap_invalidate_cache_range(va, va + tmpsize); 6119 return ((void *)(va + offset)); 6120} 6121 6122void * 6123pmap_mapdev(vm_paddr_t pa, vm_size_t size) 6124{ 6125 6126 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 6127} 6128 6129void * 6130pmap_mapbios(vm_paddr_t pa, vm_size_t size) 6131{ 6132 6133 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 6134} 6135 6136void 6137pmap_unmapdev(vm_offset_t va, vm_size_t size) 6138{ 6139 vm_offset_t base, offset; 6140 6141 /* If we gave a direct map region in pmap_mapdev, do nothing */ 6142 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) 6143 return; 6144 base = trunc_page(va); 6145 offset = va & PAGE_MASK; 6146 size = round_page(offset + size); 6147 kva_free(base, size); 6148} 6149 6150/* 6151 * Tries to demote a 1GB page mapping. 6152 */ 6153static boolean_t 6154pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va) 6155{ 6156 pdp_entry_t newpdpe, oldpdpe; 6157 pd_entry_t *firstpde, newpde, *pde; 6158 pt_entry_t PG_A, PG_M, PG_RW, PG_V; 6159 vm_paddr_t mpdepa; 6160 vm_page_t mpde; 6161 6162 PG_A = pmap_accessed_bit(pmap); 6163 PG_M = pmap_modified_bit(pmap); 6164 PG_V = pmap_valid_bit(pmap); 6165 PG_RW = pmap_rw_bit(pmap); 6166 6167 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 6168 oldpdpe = *pdpe; 6169 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V), 6170 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V")); 6171 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT | 6172 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 6173 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx" 6174 " in pmap %p", va, pmap); 6175 return (FALSE); 6176 } 6177 mpdepa = VM_PAGE_TO_PHYS(mpde); 6178 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa); 6179 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V; 6180 KASSERT((oldpdpe & PG_A) != 0, 6181 ("pmap_demote_pdpe: oldpdpe is missing PG_A")); 6182 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW, 6183 ("pmap_demote_pdpe: oldpdpe is missing PG_M")); 6184 newpde = oldpdpe; 6185 6186 /* 6187 * Initialize the page directory page. 6188 */ 6189 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) { 6190 *pde = newpde; 6191 newpde += NBPDR; 6192 } 6193 6194 /* 6195 * Demote the mapping. 6196 */ 6197 *pdpe = newpdpe; 6198 6199 /* 6200 * Invalidate a stale recursive mapping of the page directory page. 6201 */ 6202 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va)); 6203 6204 pmap_pdpe_demotions++; 6205 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx" 6206 " in pmap %p", va, pmap); 6207 return (TRUE); 6208} 6209 6210/* 6211 * Sets the memory attribute for the specified page. 6212 */ 6213void 6214pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 6215{ 6216 6217 m->md.pat_mode = ma; 6218 6219 /* 6220 * If "m" is a normal page, update its direct mapping. This update 6221 * can be relied upon to perform any cache operations that are 6222 * required for data coherence. 6223 */ 6224 if ((m->flags & PG_FICTITIOUS) == 0 && 6225 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE, 6226 m->md.pat_mode)) 6227 panic("memory attribute change on the direct map failed"); 6228} 6229 6230/* 6231 * Changes the specified virtual address range's memory type to that given by 6232 * the parameter "mode". The specified virtual address range must be 6233 * completely contained within either the direct map or the kernel map. If 6234 * the virtual address range is contained within the kernel map, then the 6235 * memory type for each of the corresponding ranges of the direct map is also 6236 * changed. (The corresponding ranges of the direct map are those ranges that 6237 * map the same physical pages as the specified virtual address range.) These 6238 * changes to the direct map are necessary because Intel describes the 6239 * behavior of their processors as "undefined" if two or more mappings to the 6240 * same physical page have different memory types. 6241 * 6242 * Returns zero if the change completed successfully, and either EINVAL or 6243 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 6244 * of the virtual address range was not mapped, and ENOMEM is returned if 6245 * there was insufficient memory available to complete the change. In the 6246 * latter case, the memory type may have been changed on some part of the 6247 * virtual address range or the direct map. 6248 */ 6249int 6250pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 6251{ 6252 int error; 6253 6254 PMAP_LOCK(kernel_pmap); 6255 error = pmap_change_attr_locked(va, size, mode); 6256 PMAP_UNLOCK(kernel_pmap); 6257 return (error); 6258} 6259 6260static int 6261pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode) 6262{ 6263 vm_offset_t base, offset, tmpva; 6264 vm_paddr_t pa_start, pa_end; 6265 pdp_entry_t *pdpe; 6266 pd_entry_t *pde; 6267 pt_entry_t *pte; 6268 int cache_bits_pte, cache_bits_pde, error; 6269 boolean_t changed; 6270 6271 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED); 6272 base = trunc_page(va); 6273 offset = va & PAGE_MASK; 6274 size = round_page(offset + size); 6275 6276 /* 6277 * Only supported on kernel virtual addresses, including the direct 6278 * map but excluding the recursive map. 6279 */ 6280 if (base < DMAP_MIN_ADDRESS) 6281 return (EINVAL); 6282 6283 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1); 6284 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0); 6285 changed = FALSE; 6286 6287 /* 6288 * Pages that aren't mapped aren't supported. Also break down 2MB pages 6289 * into 4KB pages if required. 6290 */ 6291 for (tmpva = base; tmpva < base + size; ) { 6292 pdpe = pmap_pdpe(kernel_pmap, tmpva); 6293 if (*pdpe == 0) 6294 return (EINVAL); 6295 if (*pdpe & PG_PS) { 6296 /* 6297 * If the current 1GB page already has the required 6298 * memory type, then we need not demote this page. Just 6299 * increment tmpva to the next 1GB page frame. 6300 */ 6301 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) { 6302 tmpva = trunc_1gpage(tmpva) + NBPDP; 6303 continue; 6304 } 6305 6306 /* 6307 * If the current offset aligns with a 1GB page frame 6308 * and there is at least 1GB left within the range, then 6309 * we need not break down this page into 2MB pages. 6310 */ 6311 if ((tmpva & PDPMASK) == 0 && 6312 tmpva + PDPMASK < base + size) { 6313 tmpva += NBPDP; 6314 continue; 6315 } 6316 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva)) 6317 return (ENOMEM); 6318 } 6319 pde = pmap_pdpe_to_pde(pdpe, tmpva); 6320 if (*pde == 0) 6321 return (EINVAL); 6322 if (*pde & PG_PS) { 6323 /* 6324 * If the current 2MB page already has the required 6325 * memory type, then we need not demote this page. Just 6326 * increment tmpva to the next 2MB page frame. 6327 */ 6328 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) { 6329 tmpva = trunc_2mpage(tmpva) + NBPDR; 6330 continue; 6331 } 6332 6333 /* 6334 * If the current offset aligns with a 2MB page frame 6335 * and there is at least 2MB left within the range, then 6336 * we need not break down this page into 4KB pages. 6337 */ 6338 if ((tmpva & PDRMASK) == 0 && 6339 tmpva + PDRMASK < base + size) { 6340 tmpva += NBPDR; 6341 continue; 6342 } 6343 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) 6344 return (ENOMEM); 6345 } 6346 pte = pmap_pde_to_pte(pde, tmpva); 6347 if (*pte == 0) 6348 return (EINVAL); 6349 tmpva += PAGE_SIZE; 6350 } 6351 error = 0; 6352 6353 /* 6354 * Ok, all the pages exist, so run through them updating their 6355 * cache mode if required. 6356 */ 6357 pa_start = pa_end = 0; 6358 for (tmpva = base; tmpva < base + size; ) { 6359 pdpe = pmap_pdpe(kernel_pmap, tmpva); 6360 if (*pdpe & PG_PS) { 6361 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) { 6362 pmap_pde_attr(pdpe, cache_bits_pde, 6363 X86_PG_PDE_CACHE); 6364 changed = TRUE; 6365 } 6366 if (tmpva >= VM_MIN_KERNEL_ADDRESS) { 6367 if (pa_start == pa_end) { 6368 /* Start physical address run. */ 6369 pa_start = *pdpe & PG_PS_FRAME; 6370 pa_end = pa_start + NBPDP; 6371 } else if (pa_end == (*pdpe & PG_PS_FRAME)) 6372 pa_end += NBPDP; 6373 else { 6374 /* Run ended, update direct map. */ 6375 error = pmap_change_attr_locked( 6376 PHYS_TO_DMAP(pa_start), 6377 pa_end - pa_start, mode); 6378 if (error != 0) 6379 break; 6380 /* Start physical address run. */ 6381 pa_start = *pdpe & PG_PS_FRAME; 6382 pa_end = pa_start + NBPDP; 6383 } 6384 } 6385 tmpva = trunc_1gpage(tmpva) + NBPDP; 6386 continue; 6387 } 6388 pde = pmap_pdpe_to_pde(pdpe, tmpva); 6389 if (*pde & PG_PS) { 6390 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) { 6391 pmap_pde_attr(pde, cache_bits_pde, 6392 X86_PG_PDE_CACHE); 6393 changed = TRUE; 6394 } 6395 if (tmpva >= VM_MIN_KERNEL_ADDRESS) { 6396 if (pa_start == pa_end) { 6397 /* Start physical address run. */ 6398 pa_start = *pde & PG_PS_FRAME; 6399 pa_end = pa_start + NBPDR; 6400 } else if (pa_end == (*pde & PG_PS_FRAME)) 6401 pa_end += NBPDR; 6402 else { 6403 /* Run ended, update direct map. */ 6404 error = pmap_change_attr_locked( 6405 PHYS_TO_DMAP(pa_start), 6406 pa_end - pa_start, mode); 6407 if (error != 0) 6408 break; 6409 /* Start physical address run. */ 6410 pa_start = *pde & PG_PS_FRAME; 6411 pa_end = pa_start + NBPDR; 6412 } 6413 } 6414 tmpva = trunc_2mpage(tmpva) + NBPDR; 6415 } else { 6416 pte = pmap_pde_to_pte(pde, tmpva); 6417 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) { 6418 pmap_pte_attr(pte, cache_bits_pte, 6419 X86_PG_PTE_CACHE); 6420 changed = TRUE; 6421 } 6422 if (tmpva >= VM_MIN_KERNEL_ADDRESS) { 6423 if (pa_start == pa_end) { 6424 /* Start physical address run. */ 6425 pa_start = *pte & PG_FRAME; 6426 pa_end = pa_start + PAGE_SIZE; 6427 } else if (pa_end == (*pte & PG_FRAME)) 6428 pa_end += PAGE_SIZE; 6429 else { 6430 /* Run ended, update direct map. */ 6431 error = pmap_change_attr_locked( 6432 PHYS_TO_DMAP(pa_start), 6433 pa_end - pa_start, mode); 6434 if (error != 0) 6435 break; 6436 /* Start physical address run. */ 6437 pa_start = *pte & PG_FRAME; 6438 pa_end = pa_start + PAGE_SIZE; 6439 } 6440 } 6441 tmpva += PAGE_SIZE; 6442 } 6443 } 6444 if (error == 0 && pa_start != pa_end) 6445 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start), 6446 pa_end - pa_start, mode); 6447 6448 /* 6449 * Flush CPU caches if required to make sure any data isn't cached that 6450 * shouldn't be, etc. 6451 */ 6452 if (changed) { 6453 pmap_invalidate_range(kernel_pmap, base, tmpva); 6454 pmap_invalidate_cache_range(base, tmpva); 6455 } 6456 return (error); 6457} 6458 6459/* 6460 * Demotes any mapping within the direct map region that covers more than the 6461 * specified range of physical addresses. This range's size must be a power 6462 * of two and its starting address must be a multiple of its size. Since the 6463 * demotion does not change any attributes of the mapping, a TLB invalidation 6464 * is not mandatory. The caller may, however, request a TLB invalidation. 6465 */ 6466void 6467pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate) 6468{ 6469 pdp_entry_t *pdpe; 6470 pd_entry_t *pde; 6471 vm_offset_t va; 6472 boolean_t changed; 6473 6474 if (len == 0) 6475 return; 6476 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2")); 6477 KASSERT((base & (len - 1)) == 0, 6478 ("pmap_demote_DMAP: base is not a multiple of len")); 6479 if (len < NBPDP && base < dmaplimit) { 6480 va = PHYS_TO_DMAP(base); 6481 changed = FALSE; 6482 PMAP_LOCK(kernel_pmap); 6483 pdpe = pmap_pdpe(kernel_pmap, va); 6484 if ((*pdpe & X86_PG_V) == 0) 6485 panic("pmap_demote_DMAP: invalid PDPE"); 6486 if ((*pdpe & PG_PS) != 0) { 6487 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va)) 6488 panic("pmap_demote_DMAP: PDPE failed"); 6489 changed = TRUE; 6490 } 6491 if (len < NBPDR) { 6492 pde = pmap_pdpe_to_pde(pdpe, va); 6493 if ((*pde & X86_PG_V) == 0) 6494 panic("pmap_demote_DMAP: invalid PDE"); 6495 if ((*pde & PG_PS) != 0) { 6496 if (!pmap_demote_pde(kernel_pmap, pde, va)) 6497 panic("pmap_demote_DMAP: PDE failed"); 6498 changed = TRUE; 6499 } 6500 } 6501 if (changed && invalidate) 6502 pmap_invalidate_page(kernel_pmap, va); 6503 PMAP_UNLOCK(kernel_pmap); 6504 } 6505} 6506 6507/* 6508 * perform the pmap work for mincore 6509 */ 6510int 6511pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 6512{ 6513 pd_entry_t *pdep; 6514 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V; 6515 vm_paddr_t pa; 6516 int val; 6517 6518 PG_A = pmap_accessed_bit(pmap); 6519 PG_M = pmap_modified_bit(pmap); 6520 PG_V = pmap_valid_bit(pmap); 6521 PG_RW = pmap_rw_bit(pmap); 6522 6523 PMAP_LOCK(pmap); 6524retry: 6525 pdep = pmap_pde(pmap, addr); 6526 if (pdep != NULL && (*pdep & PG_V)) { 6527 if (*pdep & PG_PS) { 6528 pte = *pdep; 6529 /* Compute the physical address of the 4KB page. */ 6530 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) & 6531 PG_FRAME; 6532 val = MINCORE_SUPER; 6533 } else { 6534 pte = *pmap_pde_to_pte(pdep, addr); 6535 pa = pte & PG_FRAME; 6536 val = 0; 6537 } 6538 } else { 6539 pte = 0; 6540 pa = 0; 6541 val = 0; 6542 } 6543 if ((pte & PG_V) != 0) { 6544 val |= MINCORE_INCORE; 6545 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 6546 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 6547 if ((pte & PG_A) != 0) 6548 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 6549 } 6550 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 6551 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 6552 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 6553 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 6554 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 6555 goto retry; 6556 } else 6557 PA_UNLOCK_COND(*locked_pa); 6558 PMAP_UNLOCK(pmap); 6559 return (val); 6560} 6561 6562void 6563pmap_activate(struct thread *td) 6564{ 6565 pmap_t pmap, oldpmap; 6566 u_int cpuid; 6567 6568 critical_enter(); 6569 pmap = vmspace_pmap(td->td_proc->p_vmspace); 6570 oldpmap = PCPU_GET(curpmap); 6571 cpuid = PCPU_GET(cpuid); 6572#ifdef SMP 6573 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 6574 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 6575 CPU_SET_ATOMIC(cpuid, &pmap->pm_save); 6576#else 6577 CPU_CLR(cpuid, &oldpmap->pm_active); 6578 CPU_SET(cpuid, &pmap->pm_active); 6579 CPU_SET(cpuid, &pmap->pm_save); 6580#endif 6581 td->td_pcb->pcb_cr3 = pmap->pm_cr3; 6582 load_cr3(pmap->pm_cr3); 6583 PCPU_SET(curpmap, pmap); 6584 critical_exit(); 6585} 6586 6587void 6588pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 6589{ 6590} 6591 6592/* 6593 * Increase the starting virtual address of the given mapping if a 6594 * different alignment might result in more superpage mappings. 6595 */ 6596void 6597pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 6598 vm_offset_t *addr, vm_size_t size) 6599{ 6600 vm_offset_t superpage_offset; 6601 6602 if (size < NBPDR) 6603 return; 6604 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 6605 offset += ptoa(object->pg_color); 6606 superpage_offset = offset & PDRMASK; 6607 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 6608 (*addr & PDRMASK) == superpage_offset) 6609 return; 6610 if ((*addr & PDRMASK) < superpage_offset) 6611 *addr = (*addr & ~PDRMASK) + superpage_offset; 6612 else 6613 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 6614} 6615 6616#ifdef INVARIANTS 6617static unsigned long num_dirty_emulations; 6618SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW, 6619 &num_dirty_emulations, 0, NULL); 6620 6621static unsigned long num_accessed_emulations; 6622SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW, 6623 &num_accessed_emulations, 0, NULL); 6624 6625static unsigned long num_superpage_accessed_emulations; 6626SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW, 6627 &num_superpage_accessed_emulations, 0, NULL); 6628 6629static unsigned long ad_emulation_superpage_promotions; 6630SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW, 6631 &ad_emulation_superpage_promotions, 0, NULL); 6632#endif /* INVARIANTS */ 6633 6634int 6635pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype) 6636{ 6637 int rv; 6638 struct rwlock *lock; 6639 vm_page_t m, mpte; 6640 pd_entry_t *pde; 6641 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V; 6642 boolean_t pv_lists_locked; 6643 6644 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE, 6645 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype)); 6646 6647 if (!pmap_emulate_ad_bits(pmap)) 6648 return (-1); 6649 6650 PG_A = pmap_accessed_bit(pmap); 6651 PG_M = pmap_modified_bit(pmap); 6652 PG_V = pmap_valid_bit(pmap); 6653 PG_RW = pmap_rw_bit(pmap); 6654 6655 rv = -1; 6656 lock = NULL; 6657 pv_lists_locked = FALSE; 6658retry: 6659 PMAP_LOCK(pmap); 6660 6661 pde = pmap_pde(pmap, va); 6662 if (pde == NULL || (*pde & PG_V) == 0) 6663 goto done; 6664 6665 if ((*pde & PG_PS) != 0) { 6666 if (ftype == VM_PROT_READ) { 6667#ifdef INVARIANTS 6668 atomic_add_long(&num_superpage_accessed_emulations, 1); 6669#endif 6670 *pde |= PG_A; 6671 rv = 0; 6672 } 6673 goto done; 6674 } 6675 6676 pte = pmap_pde_to_pte(pde, va); 6677 if ((*pte & PG_V) == 0) 6678 goto done; 6679 6680 if (ftype == VM_PROT_WRITE) { 6681 if ((*pte & PG_RW) == 0) 6682 goto done; 6683 *pte |= PG_M; 6684 } 6685 *pte |= PG_A; 6686 6687 /* try to promote the mapping */ 6688 if (va < VM_MAXUSER_ADDRESS) 6689 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 6690 else 6691 mpte = NULL; 6692 6693 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME); 6694 6695 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 6696 pmap_ps_enabled(pmap) && 6697 (m->flags & PG_FICTITIOUS) == 0 && 6698 vm_reserv_level_iffullpop(m) == 0) { 6699 if (!pv_lists_locked) { 6700 pv_lists_locked = TRUE; 6701 if (!rw_try_rlock(&pvh_global_lock)) { 6702 PMAP_UNLOCK(pmap); 6703 rw_rlock(&pvh_global_lock); 6704 goto retry; 6705 } 6706 } 6707 pmap_promote_pde(pmap, pde, va, &lock); 6708#ifdef INVARIANTS 6709 atomic_add_long(&ad_emulation_superpage_promotions, 1); 6710#endif 6711 } 6712#ifdef INVARIANTS 6713 if (ftype == VM_PROT_WRITE) 6714 atomic_add_long(&num_dirty_emulations, 1); 6715 else 6716 atomic_add_long(&num_accessed_emulations, 1); 6717#endif 6718 rv = 0; /* success */ 6719done: 6720 if (lock != NULL) 6721 rw_wunlock(lock); 6722 if (pv_lists_locked) 6723 rw_runlock(&pvh_global_lock); 6724 PMAP_UNLOCK(pmap); 6725 return (rv); 6726} 6727 6728void 6729pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num) 6730{ 6731 pml4_entry_t *pml4; 6732 pdp_entry_t *pdp; 6733 pd_entry_t *pde; 6734 pt_entry_t *pte, PG_V; 6735 int idx; 6736 6737 idx = 0; 6738 PG_V = pmap_valid_bit(pmap); 6739 PMAP_LOCK(pmap); 6740 6741 pml4 = pmap_pml4e(pmap, va); 6742 ptr[idx++] = *pml4; 6743 if ((*pml4 & PG_V) == 0) 6744 goto done; 6745 6746 pdp = pmap_pml4e_to_pdpe(pml4, va); 6747 ptr[idx++] = *pdp; 6748 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) 6749 goto done; 6750 6751 pde = pmap_pdpe_to_pde(pdp, va); 6752 ptr[idx++] = *pde; 6753 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) 6754 goto done; 6755 6756 pte = pmap_pde_to_pte(pde, va); 6757 ptr[idx++] = *pte; 6758 6759done: 6760 PMAP_UNLOCK(pmap); 6761 *num = idx; 6762} 6763 6764#include "opt_ddb.h" 6765#ifdef DDB 6766#include <ddb/ddb.h> 6767 6768DB_SHOW_COMMAND(pte, pmap_print_pte) 6769{ 6770 pmap_t pmap; 6771 pml4_entry_t *pml4; 6772 pdp_entry_t *pdp; 6773 pd_entry_t *pde; 6774 pt_entry_t *pte, PG_V; 6775 vm_offset_t va; 6776 6777 if (have_addr) { 6778 va = (vm_offset_t)addr; 6779 pmap = PCPU_GET(curpmap); /* XXX */ 6780 } else { 6781 db_printf("show pte addr\n"); 6782 return; 6783 } 6784 PG_V = pmap_valid_bit(pmap); 6785 pml4 = pmap_pml4e(pmap, va); 6786 db_printf("VA %#016lx pml4e %#016lx", va, *pml4); 6787 if ((*pml4 & PG_V) == 0) { 6788 db_printf("\n"); 6789 return; 6790 } 6791 pdp = pmap_pml4e_to_pdpe(pml4, va); 6792 db_printf(" pdpe %#016lx", *pdp); 6793 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) { 6794 db_printf("\n"); 6795 return; 6796 } 6797 pde = pmap_pdpe_to_pde(pdp, va); 6798 db_printf(" pde %#016lx", *pde); 6799 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) { 6800 db_printf("\n"); 6801 return; 6802 } 6803 pte = pmap_pde_to_pte(pde, va); 6804 db_printf(" pte %#016lx\n", *pte); 6805} 6806 6807DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap) 6808{ 6809 vm_paddr_t a; 6810 6811 if (have_addr) { 6812 a = (vm_paddr_t)addr; 6813 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a)); 6814 } else { 6815 db_printf("show phys2dmap addr\n"); 6816 } 6817} 6818#endif 6819