X86RecognizableInstr.cpp revision 263508 
1//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the implementation of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#include "X86RecognizableInstr.h"
18#include "X86DisassemblerShared.h"
19#include "X86ModRMFilters.h"
20#include "llvm/Support/ErrorHandling.h"
21#include <string>
22
23using namespace llvm;
24
25#define MRM_MAPPING     \
26  MAP(C1, 33)           \
27  MAP(C2, 34)           \
28  MAP(C3, 35)           \
29  MAP(C4, 36)           \
30  MAP(C8, 37)           \
31  MAP(C9, 38)           \
32  MAP(CA, 39)           \
33  MAP(CB, 40)           \
34  MAP(E8, 41)           \
35  MAP(F0, 42)           \
36  MAP(F8, 45)           \
37  MAP(F9, 46)           \
38  MAP(D0, 47)           \
39  MAP(D1, 48)           \
40  MAP(D4, 49)           \
41  MAP(D5, 50)           \
42  MAP(D6, 51)           \
43  MAP(D8, 52)           \
44  MAP(D9, 53)           \
45  MAP(DA, 54)           \
46  MAP(DB, 55)           \
47  MAP(DC, 56)           \
48  MAP(DD, 57)           \
49  MAP(DE, 58)           \
50  MAP(DF, 59)
51
52// A clone of X86 since we can't depend on something that is generated.
53namespace X86Local {
54  enum {
55    Pseudo      = 0,
56    RawFrm      = 1,
57    AddRegFrm   = 2,
58    MRMDestReg  = 3,
59    MRMDestMem  = 4,
60    MRMSrcReg   = 5,
61    MRMSrcMem   = 6,
62    MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63    MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64    MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65    MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
66    MRMInitReg  = 32,
67    RawFrmImm8  = 43,
68    RawFrmImm16 = 44,
69#define MAP(from, to) MRM_##from = to,
70    MRM_MAPPING
71#undef MAP
72    lastMRM
73  };
74
75  enum {
76    TB  = 1,
77    REP = 2,
78    D8 = 3, D9 = 4, DA = 5, DB = 6,
79    DC = 7, DD = 8, DE = 9, DF = 10,
80    XD = 11,  XS = 12,
81    T8 = 13,  P_TA = 14,
82    A6 = 15,  A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83    XOP8 = 20, XOP9 = 21, XOPA = 22
84  };
85}
86
87// If rows are added to the opcode extension tables, then corresponding entries
88// must be added here.
89//
90// If the row corresponds to a single byte (i.e., 8f), then add an entry for
91// that byte to ONE_BYTE_EXTENSION_TABLES.
92//
93// If the row corresponds to two bytes where the first is 0f, add an entry for
94// the second byte to TWO_BYTE_EXTENSION_TABLES.
95//
96// If the row corresponds to some other set of bytes, you will need to modify
97// the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98// to the X86 TD files, except in two cases: if the first two bytes of such a
99// new combination are 0f 38 or 0f 3a, you just have to add maps called
100// THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101// switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102// in RecognizableInstr::emitDecodePath().
103
104#define ONE_BYTE_EXTENSION_TABLES \
105  EXTENSION_TABLE(80)             \
106  EXTENSION_TABLE(81)             \
107  EXTENSION_TABLE(82)             \
108  EXTENSION_TABLE(83)             \
109  EXTENSION_TABLE(8f)             \
110  EXTENSION_TABLE(c0)             \
111  EXTENSION_TABLE(c1)             \
112  EXTENSION_TABLE(c6)             \
113  EXTENSION_TABLE(c7)             \
114  EXTENSION_TABLE(d0)             \
115  EXTENSION_TABLE(d1)             \
116  EXTENSION_TABLE(d2)             \
117  EXTENSION_TABLE(d3)             \
118  EXTENSION_TABLE(f6)             \
119  EXTENSION_TABLE(f7)             \
120  EXTENSION_TABLE(fe)             \
121  EXTENSION_TABLE(ff)
122
123#define TWO_BYTE_EXTENSION_TABLES \
124  EXTENSION_TABLE(00)             \
125  EXTENSION_TABLE(01)             \
126  EXTENSION_TABLE(0d)             \
127  EXTENSION_TABLE(18)             \
128  EXTENSION_TABLE(71)             \
129  EXTENSION_TABLE(72)             \
130  EXTENSION_TABLE(73)             \
131  EXTENSION_TABLE(ae)             \
132  EXTENSION_TABLE(ba)             \
133  EXTENSION_TABLE(c7)
134
135#define THREE_BYTE_38_EXTENSION_TABLES \
136  EXTENSION_TABLE(F3)
137
138#define XOP9_MAP_EXTENSION_TABLES \
139  EXTENSION_TABLE(01)             \
140  EXTENSION_TABLE(02)
141
142using namespace X86Disassembler;
143
144/// needsModRMForDecode - Indicates whether a particular instruction requires a
145///   ModR/M byte for the instruction to be properly decoded.  For example, a
146///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
147///   0b11.
148///
149/// @param form - The form of the instruction.
150/// @return     - true if the form implies that a ModR/M byte is required, false
151///               otherwise.
152static bool needsModRMForDecode(uint8_t form) {
153  if (form == X86Local::MRMDestReg    ||
154     form == X86Local::MRMDestMem    ||
155     form == X86Local::MRMSrcReg     ||
156     form == X86Local::MRMSrcMem     ||
157     (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158     (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
159    return true;
160  else
161    return false;
162}
163
164/// isRegFormat - Indicates whether a particular form requires the Mod field of
165///   the ModR/M byte to be 0b11.
166///
167/// @param form - The form of the instruction.
168/// @return     - true if the form implies that Mod must be 0b11, false
169///               otherwise.
170static bool isRegFormat(uint8_t form) {
171  if (form == X86Local::MRMDestReg ||
172     form == X86Local::MRMSrcReg  ||
173     (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
174    return true;
175  else
176    return false;
177}
178
179/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180///   Useful for switch statements and the like.
181///
182/// @param init - A reference to the BitsInit to be decoded.
183/// @return     - The field, with the first bit in the BitsInit as the lowest
184///               order bit.
185static uint8_t byteFromBitsInit(BitsInit &init) {
186  int width = init.getNumBits();
187
188  assert(width <= 8 && "Field is too large for uint8_t!");
189
190  int     index;
191  uint8_t mask = 0x01;
192
193  uint8_t ret = 0;
194
195  for (index = 0; index < width; index++) {
196    if (static_cast<BitInit*>(init.getBit(index))->getValue())
197      ret |= mask;
198
199    mask <<= 1;
200  }
201
202  return ret;
203}
204
205/// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206///   name of the field.
207///
208/// @param rec  - The record from which to extract the value.
209/// @param name - The name of the field in the record.
210/// @return     - The field, as translated by byteFromBitsInit().
211static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212  BitsInit* bits = rec->getValueAsBitsInit(name);
213  return byteFromBitsInit(*bits);
214}
215
216RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217                                     const CodeGenInstruction &insn,
218                                     InstrUID uid) {
219  UID = uid;
220
221  Rec = insn.TheDef;
222  Name = Rec->getName();
223  Spec = &tables.specForUID(UID);
224
225  if (!Rec->isSubClassOf("X86Inst")) {
226    ShouldBeEmitted = false;
227    return;
228  }
229
230  Prefix   = byteFromRec(Rec, "Prefix");
231  Opcode   = byteFromRec(Rec, "Opcode");
232  Form     = byteFromRec(Rec, "FormBits");
233  SegOvr   = byteFromRec(Rec, "SegOvrBits");
234
235  HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
236  HasAdSizePrefix  = Rec->getValueAsBit("hasAdSizePrefix");
237  HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
238  HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
239  HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
240  HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241  HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
242  HasMemOp4Prefix  = Rec->getValueAsBit("hasMemOp4Prefix");
243  IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
244  HasEVEXPrefix    = Rec->getValueAsBit("hasEVEXPrefix");
245  HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246  HasEVEX_K        = Rec->getValueAsBit("hasEVEX_K");
247  HasEVEX_KZ       = Rec->getValueAsBit("hasEVEX_Z");
248  HasEVEX_B        = Rec->getValueAsBit("hasEVEX_B");
249  HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
250  IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
251
252  Name      = Rec->getName();
253  AsmString = Rec->getValueAsString("AsmString");
254
255  Operands = &insn.Operands.OperandList;
256
257  IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
258                     (Name.find("CRC32") != Name.npos);
259  HasFROperands    = hasFROperands();
260  HasVEX_LPrefix   = Rec->getValueAsBit("hasVEX_L");
261
262  // Check for 64-bit inst which does not require REX
263  Is32Bit = false;
264  Is64Bit = false;
265  // FIXME: Is there some better way to check for In64BitMode?
266  std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
267  for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
268    if (Predicates[i]->getName().find("32Bit") != Name.npos) {
269      Is32Bit = true;
270      break;
271    }
272    if (Predicates[i]->getName().find("64Bit") != Name.npos) {
273      Is64Bit = true;
274      break;
275    }
276  }
277  // FIXME: These instructions aren't marked as 64-bit in any way
278  Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
279             Rec->getName() == "MASKMOVDQU64" ||
280             Rec->getName() == "POPFS64" ||
281             Rec->getName() == "POPGS64" ||
282             Rec->getName() == "PUSHFS64" ||
283             Rec->getName() == "PUSHGS64" ||
284             Rec->getName() == "REX64_PREFIX" ||
285             Rec->getName().find("MOV64") != Name.npos ||
286             Rec->getName().find("PUSH64") != Name.npos ||
287             Rec->getName().find("POP64") != Name.npos;
288
289  ShouldBeEmitted  = true;
290}
291
292void RecognizableInstr::processInstr(DisassemblerTables &tables,
293                                     const CodeGenInstruction &insn,
294                                     InstrUID uid)
295{
296  // Ignore "asm parser only" instructions.
297  if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
298    return;
299
300  RecognizableInstr recogInstr(tables, insn, uid);
301
302  recogInstr.emitInstructionSpecifier(tables);
303
304  if (recogInstr.shouldBeEmitted())
305    recogInstr.emitDecodePath(tables);
306}
307
308#define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
309                    (HasEVEX_K && HasEVEX_B ? n##_K_B : \
310                    (HasEVEX_KZ ? n##_KZ : \
311                    (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
312
313InstructionContext RecognizableInstr::insnContext() const {
314  InstructionContext insnContext;
315
316  if (HasEVEXPrefix) {
317    if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
318      errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
319      llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
320    }
321    // VEX_L & VEX_W
322    if (HasVEX_LPrefix && HasVEX_WPrefix) {
323      if (HasOpSizePrefix)
324        insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
325      else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
326        insnContext = EVEX_KB(IC_EVEX_L_W_XS);
327      else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
328               Prefix == X86Local::TAXD)
329        insnContext = EVEX_KB(IC_EVEX_L_W_XD);
330      else
331        insnContext = EVEX_KB(IC_EVEX_L_W);
332    } else if (HasVEX_LPrefix) {
333      // VEX_L
334      if (HasOpSizePrefix)
335        insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
336      else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
337        insnContext = EVEX_KB(IC_EVEX_L_XS);
338      else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
339               Prefix == X86Local::TAXD)
340        insnContext = EVEX_KB(IC_EVEX_L_XD);
341      else
342        insnContext = EVEX_KB(IC_EVEX_L);
343    }
344    else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
345      // EVEX_L2 & VEX_W
346      if (HasOpSizePrefix)
347        insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
348      else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
349        insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
350      else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
351               Prefix == X86Local::TAXD)
352        insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
353      else
354        insnContext = EVEX_KB(IC_EVEX_L2_W);
355    } else if (HasEVEX_L2Prefix) {
356      // EVEX_L2
357      if (HasOpSizePrefix)
358        insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
359      else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
360          Prefix == X86Local::TAXD)
361        insnContext = EVEX_KB(IC_EVEX_L2_XD);
362      else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
363        insnContext = EVEX_KB(IC_EVEX_L2_XS);
364      else
365        insnContext = EVEX_KB(IC_EVEX_L2);
366    }
367    else if (HasVEX_WPrefix) {
368      // VEX_W
369      if (HasOpSizePrefix)
370        insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
371      else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
372        insnContext = EVEX_KB(IC_EVEX_W_XS);
373      else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
374               Prefix == X86Local::TAXD)
375        insnContext = EVEX_KB(IC_EVEX_W_XD);
376      else
377        insnContext = EVEX_KB(IC_EVEX_W);
378    }
379    // No L, no W
380    else if (HasOpSizePrefix)
381      insnContext = EVEX_KB(IC_EVEX_OPSIZE);
382    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
383             Prefix == X86Local::TAXD)
384      insnContext = EVEX_KB(IC_EVEX_XD);
385    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
386      insnContext = EVEX_KB(IC_EVEX_XS);
387    else
388      insnContext = EVEX_KB(IC_EVEX);
389    /// eof EVEX
390  } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
391    if (HasVEX_LPrefix && HasVEX_WPrefix) {
392      if (HasOpSizePrefix)
393        insnContext = IC_VEX_L_W_OPSIZE;
394      else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
395        insnContext = IC_VEX_L_W_XS;
396      else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
397               Prefix == X86Local::TAXD)
398        insnContext = IC_VEX_L_W_XD;
399      else
400        insnContext = IC_VEX_L_W;
401    } else if (HasOpSizePrefix && HasVEX_LPrefix)
402      insnContext = IC_VEX_L_OPSIZE;
403    else if (HasOpSizePrefix && HasVEX_WPrefix)
404      insnContext = IC_VEX_W_OPSIZE;
405    else if (HasOpSizePrefix)
406      insnContext = IC_VEX_OPSIZE;
407    else if (HasVEX_LPrefix &&
408             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
409      insnContext = IC_VEX_L_XS;
410    else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
411                                Prefix == X86Local::T8XD ||
412                                Prefix == X86Local::TAXD))
413      insnContext = IC_VEX_L_XD;
414    else if (HasVEX_WPrefix &&
415             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
416      insnContext = IC_VEX_W_XS;
417    else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
418                                Prefix == X86Local::T8XD ||
419                                Prefix == X86Local::TAXD))
420      insnContext = IC_VEX_W_XD;
421    else if (HasVEX_WPrefix)
422      insnContext = IC_VEX_W;
423    else if (HasVEX_LPrefix)
424      insnContext = IC_VEX_L;
425    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
426             Prefix == X86Local::TAXD)
427      insnContext = IC_VEX_XD;
428    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
429      insnContext = IC_VEX_XS;
430    else
431      insnContext = IC_VEX;
432  } else if (Is64Bit || HasREX_WPrefix) {
433    if (HasREX_WPrefix && HasOpSizePrefix)
434      insnContext = IC_64BIT_REXW_OPSIZE;
435    else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
436                                 Prefix == X86Local::T8XD ||
437                                 Prefix == X86Local::TAXD))
438      insnContext = IC_64BIT_XD_OPSIZE;
439    else if (HasOpSizePrefix &&
440             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
441      insnContext = IC_64BIT_XS_OPSIZE;
442    else if (HasOpSizePrefix)
443      insnContext = IC_64BIT_OPSIZE;
444    else if (HasAdSizePrefix)
445      insnContext = IC_64BIT_ADSIZE;
446    else if (HasREX_WPrefix &&
447             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
448      insnContext = IC_64BIT_REXW_XS;
449    else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
450                                Prefix == X86Local::T8XD ||
451                                Prefix == X86Local::TAXD))
452      insnContext = IC_64BIT_REXW_XD;
453    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
454             Prefix == X86Local::TAXD)
455      insnContext = IC_64BIT_XD;
456    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
457      insnContext = IC_64BIT_XS;
458    else if (HasREX_WPrefix)
459      insnContext = IC_64BIT_REXW;
460    else
461      insnContext = IC_64BIT;
462  } else {
463    if (HasOpSizePrefix && (Prefix == X86Local::XD ||
464                            Prefix == X86Local::T8XD ||
465                            Prefix == X86Local::TAXD))
466      insnContext = IC_XD_OPSIZE;
467    else if (HasOpSizePrefix &&
468             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
469      insnContext = IC_XS_OPSIZE;
470    else if (HasOpSizePrefix)
471      insnContext = IC_OPSIZE;
472    else if (HasAdSizePrefix)
473      insnContext = IC_ADSIZE;
474    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
475             Prefix == X86Local::TAXD)
476      insnContext = IC_XD;
477    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
478             Prefix == X86Local::REP)
479      insnContext = IC_XS;
480    else
481      insnContext = IC;
482  }
483
484  return insnContext;
485}
486
487RecognizableInstr::filter_ret RecognizableInstr::filter() const {
488  ///////////////////
489  // FILTER_STRONG
490  //
491
492  // Filter out intrinsics
493
494  assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
495
496  if (Form == X86Local::Pseudo ||
497      (IsCodeGenOnly && Name.find("_REV") == Name.npos &&
498       Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
499    return FILTER_STRONG;
500
501
502  // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
503  // printed as a separate "instruction".
504
505  if (Name.find("_Int") != Name.npos       ||
506      Name.find("Int_") != Name.npos)
507    return FILTER_STRONG;
508
509  // Filter out instructions with segment override prefixes.
510  // They're too messy to handle now and we'll special case them if needed.
511
512  if (SegOvr)
513    return FILTER_STRONG;
514
515
516  /////////////////
517  // FILTER_WEAK
518  //
519
520
521  // Filter out instructions with a LOCK prefix;
522  //   prefer forms that do not have the prefix
523  if (HasLockPrefix)
524    return FILTER_WEAK;
525
526  // Filter out alternate forms of AVX instructions
527  if (Name.find("_alt") != Name.npos ||
528      (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
529      Name.find("_64mr") != Name.npos ||
530      Name.find("rr64") != Name.npos)
531    return FILTER_WEAK;
532
533  // Special cases.
534
535  if (Name == "PUSH64i16"         ||
536      Name == "MOVPQI2QImr"       ||
537      Name == "VMOVPQI2QImr"      ||
538      Name == "VMASKMOVDQU64")
539    return FILTER_WEAK;
540
541  // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
542  // For now, just prefer the REP versions.
543  if (Name == "XACQUIRE_PREFIX" ||
544      Name == "XRELEASE_PREFIX")
545    return FILTER_WEAK;
546
547  return FILTER_NORMAL;
548}
549
550bool RecognizableInstr::hasFROperands() const {
551  const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
552  unsigned numOperands = OperandList.size();
553
554  for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
555    const std::string &recName = OperandList[operandIndex].Rec->getName();
556
557    if (recName.find("FR") != recName.npos)
558      return true;
559  }
560  return false;
561}
562
563void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
564                                      unsigned &physicalOperandIndex,
565                                      unsigned &numPhysicalOperands,
566                                      const unsigned *operandMapping,
567                                      OperandEncoding (*encodingFromString)
568                                        (const std::string&,
569                                         bool hasOpSizePrefix)) {
570  if (optional) {
571    if (physicalOperandIndex >= numPhysicalOperands)
572      return;
573  } else {
574    assert(physicalOperandIndex < numPhysicalOperands);
575  }
576
577  while (operandMapping[operandIndex] != operandIndex) {
578    Spec->operands[operandIndex].encoding = ENCODING_DUP;
579    Spec->operands[operandIndex].type =
580      (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
581    ++operandIndex;
582  }
583
584  const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
585
586  Spec->operands[operandIndex].encoding = encodingFromString(typeName,
587                                                              HasOpSizePrefix);
588  Spec->operands[operandIndex].type = typeFromString(typeName,
589                                                     IsSSE,
590                                                     HasREX_WPrefix,
591                                                     HasOpSizePrefix);
592
593  ++operandIndex;
594  ++physicalOperandIndex;
595}
596
597void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
598  Spec->name       = Name;
599
600  if (!ShouldBeEmitted)
601    return;
602
603  switch (filter()) {
604  case FILTER_WEAK:
605    Spec->filtered = true;
606    break;
607  case FILTER_STRONG:
608    ShouldBeEmitted = false;
609    return;
610  case FILTER_NORMAL:
611    break;
612  }
613
614  Spec->insnContext = insnContext();
615
616  const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
617
618  unsigned numOperands = OperandList.size();
619  unsigned numPhysicalOperands = 0;
620
621  // operandMapping maps from operands in OperandList to their originals.
622  // If operandMapping[i] != i, then the entry is a duplicate.
623  unsigned operandMapping[X86_MAX_OPERANDS];
624  assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
625
626  for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
627    if (OperandList[operandIndex].Constraints.size()) {
628      const CGIOperandList::ConstraintInfo &Constraint =
629        OperandList[operandIndex].Constraints[0];
630      if (Constraint.isTied()) {
631        operandMapping[operandIndex] = operandIndex;
632        operandMapping[Constraint.getTiedOperand()] = operandIndex;
633      } else {
634        ++numPhysicalOperands;
635        operandMapping[operandIndex] = operandIndex;
636      }
637    } else {
638      ++numPhysicalOperands;
639      operandMapping[operandIndex] = operandIndex;
640    }
641  }
642
643#define HANDLE_OPERAND(class)               \
644  handleOperand(false,                      \
645                operandIndex,               \
646                physicalOperandIndex,       \
647                numPhysicalOperands,        \
648                operandMapping,             \
649                class##EncodingFromString);
650
651#define HANDLE_OPTIONAL(class)              \
652  handleOperand(true,                       \
653                operandIndex,               \
654                physicalOperandIndex,       \
655                numPhysicalOperands,        \
656                operandMapping,             \
657                class##EncodingFromString);
658
659  // operandIndex should always be < numOperands
660  unsigned operandIndex = 0;
661  // physicalOperandIndex should always be < numPhysicalOperands
662  unsigned physicalOperandIndex = 0;
663
664  switch (Form) {
665  case X86Local::RawFrm:
666    // Operand 1 (optional) is an address or immediate.
667    // Operand 2 (optional) is an immediate.
668    assert(numPhysicalOperands <= 2 &&
669           "Unexpected number of operands for RawFrm");
670    HANDLE_OPTIONAL(relocation)
671    HANDLE_OPTIONAL(immediate)
672    break;
673  case X86Local::AddRegFrm:
674    // Operand 1 is added to the opcode.
675    // Operand 2 (optional) is an address.
676    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
677           "Unexpected number of operands for AddRegFrm");
678    HANDLE_OPERAND(opcodeModifier)
679    HANDLE_OPTIONAL(relocation)
680    break;
681  case X86Local::MRMDestReg:
682    // Operand 1 is a register operand in the R/M field.
683    // Operand 2 is a register operand in the Reg/Opcode field.
684    // - In AVX, there is a register operand in the VEX.vvvv field here -
685    // Operand 3 (optional) is an immediate.
686    if (HasVEX_4VPrefix)
687      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
688             "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
689    else
690      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
691             "Unexpected number of operands for MRMDestRegFrm");
692
693    HANDLE_OPERAND(rmRegister)
694
695    if (HasVEX_4VPrefix)
696      // FIXME: In AVX, the register below becomes the one encoded
697      // in ModRMVEX and the one above the one in the VEX.VVVV field
698      HANDLE_OPERAND(vvvvRegister)
699
700    HANDLE_OPERAND(roRegister)
701    HANDLE_OPTIONAL(immediate)
702    break;
703  case X86Local::MRMDestMem:
704    // Operand 1 is a memory operand (possibly SIB-extended)
705    // Operand 2 is a register operand in the Reg/Opcode field.
706    // - In AVX, there is a register operand in the VEX.vvvv field here -
707    // Operand 3 (optional) is an immediate.
708    if (HasVEX_4VPrefix)
709      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
710             "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
711    else
712      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
713             "Unexpected number of operands for MRMDestMemFrm");
714    HANDLE_OPERAND(memory)
715
716    if (HasEVEX_K)
717      HANDLE_OPERAND(writemaskRegister)
718
719    if (HasVEX_4VPrefix)
720      // FIXME: In AVX, the register below becomes the one encoded
721      // in ModRMVEX and the one above the one in the VEX.VVVV field
722      HANDLE_OPERAND(vvvvRegister)
723
724    HANDLE_OPERAND(roRegister)
725    HANDLE_OPTIONAL(immediate)
726    break;
727  case X86Local::MRMSrcReg:
728    // Operand 1 is a register operand in the Reg/Opcode field.
729    // Operand 2 is a register operand in the R/M field.
730    // - In AVX, there is a register operand in the VEX.vvvv field here -
731    // Operand 3 (optional) is an immediate.
732    // Operand 4 (optional) is an immediate.
733
734    if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
735      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
736             "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
737    else
738      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
739             "Unexpected number of operands for MRMSrcRegFrm");
740
741    HANDLE_OPERAND(roRegister)
742
743    if (HasEVEX_K)
744      HANDLE_OPERAND(writemaskRegister)
745
746    if (HasVEX_4VPrefix)
747      // FIXME: In AVX, the register below becomes the one encoded
748      // in ModRMVEX and the one above the one in the VEX.VVVV field
749      HANDLE_OPERAND(vvvvRegister)
750
751    if (HasMemOp4Prefix)
752      HANDLE_OPERAND(immediate)
753
754    HANDLE_OPERAND(rmRegister)
755
756    if (HasVEX_4VOp3Prefix)
757      HANDLE_OPERAND(vvvvRegister)
758
759    if (!HasMemOp4Prefix)
760      HANDLE_OPTIONAL(immediate)
761    HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
762    HANDLE_OPTIONAL(immediate)
763    break;
764  case X86Local::MRMSrcMem:
765    // Operand 1 is a register operand in the Reg/Opcode field.
766    // Operand 2 is a memory operand (possibly SIB-extended)
767    // - In AVX, there is a register operand in the VEX.vvvv field here -
768    // Operand 3 (optional) is an immediate.
769
770    if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
771      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
772             "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
773    else
774      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
775             "Unexpected number of operands for MRMSrcMemFrm");
776
777    HANDLE_OPERAND(roRegister)
778
779    if (HasEVEX_K)
780      HANDLE_OPERAND(writemaskRegister)
781
782    if (HasVEX_4VPrefix)
783      // FIXME: In AVX, the register below becomes the one encoded
784      // in ModRMVEX and the one above the one in the VEX.VVVV field
785      HANDLE_OPERAND(vvvvRegister)
786
787    if (HasMemOp4Prefix)
788      HANDLE_OPERAND(immediate)
789
790    HANDLE_OPERAND(memory)
791
792    if (HasVEX_4VOp3Prefix)
793      HANDLE_OPERAND(vvvvRegister)
794
795    if (!HasMemOp4Prefix)
796      HANDLE_OPTIONAL(immediate)
797    HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
798    break;
799  case X86Local::MRM0r:
800  case X86Local::MRM1r:
801  case X86Local::MRM2r:
802  case X86Local::MRM3r:
803  case X86Local::MRM4r:
804  case X86Local::MRM5r:
805  case X86Local::MRM6r:
806  case X86Local::MRM7r:
807    {
808      // Operand 1 is a register operand in the R/M field.
809      // Operand 2 (optional) is an immediate or relocation.
810      // Operand 3 (optional) is an immediate.
811      unsigned kOp = (HasEVEX_K) ? 1:0;
812      unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
813      if (numPhysicalOperands > 3 + kOp + Op4v)
814        llvm_unreachable("Unexpected number of operands for MRMnr");
815    }
816    if (HasVEX_4VPrefix)
817      HANDLE_OPERAND(vvvvRegister)
818
819    if (HasEVEX_K)
820      HANDLE_OPERAND(writemaskRegister)
821    HANDLE_OPTIONAL(rmRegister)
822    HANDLE_OPTIONAL(relocation)
823    HANDLE_OPTIONAL(immediate)
824    break;
825  case X86Local::MRM0m:
826  case X86Local::MRM1m:
827  case X86Local::MRM2m:
828  case X86Local::MRM3m:
829  case X86Local::MRM4m:
830  case X86Local::MRM5m:
831  case X86Local::MRM6m:
832  case X86Local::MRM7m:
833    {
834      // Operand 1 is a memory operand (possibly SIB-extended)
835      // Operand 2 (optional) is an immediate or relocation.
836      unsigned kOp = (HasEVEX_K) ? 1:0;
837      unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
838      if (numPhysicalOperands < 1 + kOp + Op4v ||
839          numPhysicalOperands > 2 + kOp + Op4v)
840        llvm_unreachable("Unexpected number of operands for MRMnm");
841    }
842    if (HasVEX_4VPrefix)
843      HANDLE_OPERAND(vvvvRegister)
844    if (HasEVEX_K)
845      HANDLE_OPERAND(writemaskRegister)
846    HANDLE_OPERAND(memory)
847    HANDLE_OPTIONAL(relocation)
848    break;
849  case X86Local::RawFrmImm8:
850    // operand 1 is a 16-bit immediate
851    // operand 2 is an 8-bit immediate
852    assert(numPhysicalOperands == 2 &&
853           "Unexpected number of operands for X86Local::RawFrmImm8");
854    HANDLE_OPERAND(immediate)
855    HANDLE_OPERAND(immediate)
856    break;
857  case X86Local::RawFrmImm16:
858    // operand 1 is a 16-bit immediate
859    // operand 2 is a 16-bit immediate
860    HANDLE_OPERAND(immediate)
861    HANDLE_OPERAND(immediate)
862    break;
863  case X86Local::MRM_F8:
864    if (Opcode == 0xc6) {
865      assert(numPhysicalOperands == 1 &&
866             "Unexpected number of operands for X86Local::MRM_F8");
867      HANDLE_OPERAND(immediate)
868    } else if (Opcode == 0xc7) {
869      assert(numPhysicalOperands == 1 &&
870             "Unexpected number of operands for X86Local::MRM_F8");
871      HANDLE_OPERAND(relocation)
872    }
873    break;
874  case X86Local::MRMInitReg:
875    // Ignored.
876    break;
877  }
878
879  #undef HANDLE_OPERAND
880  #undef HANDLE_OPTIONAL
881}
882
883void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
884  // Special cases where the LLVM tables are not complete
885
886#define MAP(from, to)                     \
887  case X86Local::MRM_##from:              \
888    filter = new ExactFilter(0x##from);   \
889    break;
890
891  OpcodeType    opcodeType  = (OpcodeType)-1;
892
893  ModRMFilter*  filter      = NULL;
894  uint8_t       opcodeToSet = 0;
895
896  switch (Prefix) {
897  default: llvm_unreachable("Invalid prefix!");
898  // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
899  case X86Local::XD:
900  case X86Local::XS:
901  case X86Local::TB:
902    opcodeType = TWOBYTE;
903
904    switch (Opcode) {
905    default:
906      if (needsModRMForDecode(Form))
907        filter = new ModFilter(isRegFormat(Form));
908      else
909        filter = new DumbFilter();
910      break;
911#define EXTENSION_TABLE(n) case 0x##n:
912    TWO_BYTE_EXTENSION_TABLES
913#undef EXTENSION_TABLE
914      switch (Form) {
915      default:
916        llvm_unreachable("Unhandled two-byte extended opcode");
917      case X86Local::MRM0r:
918      case X86Local::MRM1r:
919      case X86Local::MRM2r:
920      case X86Local::MRM3r:
921      case X86Local::MRM4r:
922      case X86Local::MRM5r:
923      case X86Local::MRM6r:
924      case X86Local::MRM7r:
925        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
926        break;
927      case X86Local::MRM0m:
928      case X86Local::MRM1m:
929      case X86Local::MRM2m:
930      case X86Local::MRM3m:
931      case X86Local::MRM4m:
932      case X86Local::MRM5m:
933      case X86Local::MRM6m:
934      case X86Local::MRM7m:
935        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
936        break;
937      MRM_MAPPING
938      } // switch (Form)
939      break;
940    } // switch (Opcode)
941    opcodeToSet = Opcode;
942    break;
943  case X86Local::T8:
944  case X86Local::T8XD:
945  case X86Local::T8XS:
946    opcodeType = THREEBYTE_38;
947    switch (Opcode) {
948    default:
949      if (needsModRMForDecode(Form))
950        filter = new ModFilter(isRegFormat(Form));
951      else
952        filter = new DumbFilter();
953      break;
954#define EXTENSION_TABLE(n) case 0x##n:
955    THREE_BYTE_38_EXTENSION_TABLES
956#undef EXTENSION_TABLE
957      switch (Form) {
958      default:
959        llvm_unreachable("Unhandled two-byte extended opcode");
960      case X86Local::MRM0r:
961      case X86Local::MRM1r:
962      case X86Local::MRM2r:
963      case X86Local::MRM3r:
964      case X86Local::MRM4r:
965      case X86Local::MRM5r:
966      case X86Local::MRM6r:
967      case X86Local::MRM7r:
968        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
969        break;
970      case X86Local::MRM0m:
971      case X86Local::MRM1m:
972      case X86Local::MRM2m:
973      case X86Local::MRM3m:
974      case X86Local::MRM4m:
975      case X86Local::MRM5m:
976      case X86Local::MRM6m:
977      case X86Local::MRM7m:
978        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
979        break;
980      MRM_MAPPING
981      } // switch (Form)
982      break;
983    } // switch (Opcode)
984    opcodeToSet = Opcode;
985    break;
986  case X86Local::P_TA:
987  case X86Local::TAXD:
988    opcodeType = THREEBYTE_3A;
989    if (needsModRMForDecode(Form))
990      filter = new ModFilter(isRegFormat(Form));
991    else
992      filter = new DumbFilter();
993    opcodeToSet = Opcode;
994    break;
995  case X86Local::A6:
996    opcodeType = THREEBYTE_A6;
997    if (needsModRMForDecode(Form))
998      filter = new ModFilter(isRegFormat(Form));
999    else
1000      filter = new DumbFilter();
1001    opcodeToSet = Opcode;
1002    break;
1003  case X86Local::A7:
1004    opcodeType = THREEBYTE_A7;
1005    if (needsModRMForDecode(Form))
1006      filter = new ModFilter(isRegFormat(Form));
1007    else
1008      filter = new DumbFilter();
1009    opcodeToSet = Opcode;
1010    break;
1011  case X86Local::XOP8:
1012    opcodeType = XOP8_MAP;
1013    if (needsModRMForDecode(Form))
1014      filter = new ModFilter(isRegFormat(Form));
1015    else
1016      filter = new DumbFilter();
1017    opcodeToSet = Opcode;
1018    break;
1019  case X86Local::XOP9:
1020    opcodeType = XOP9_MAP;
1021    switch (Opcode) {
1022    default:
1023      if (needsModRMForDecode(Form))
1024        filter = new ModFilter(isRegFormat(Form));
1025      else
1026        filter = new DumbFilter();
1027      break;
1028#define EXTENSION_TABLE(n) case 0x##n:
1029    XOP9_MAP_EXTENSION_TABLES
1030#undef EXTENSION_TABLE
1031      switch (Form) {
1032      default:
1033        llvm_unreachable("Unhandled XOP9 extended opcode");
1034      case X86Local::MRM0r:
1035      case X86Local::MRM1r:
1036      case X86Local::MRM2r:
1037      case X86Local::MRM3r:
1038      case X86Local::MRM4r:
1039      case X86Local::MRM5r:
1040      case X86Local::MRM6r:
1041      case X86Local::MRM7r:
1042        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1043        break;
1044      case X86Local::MRM0m:
1045      case X86Local::MRM1m:
1046      case X86Local::MRM2m:
1047      case X86Local::MRM3m:
1048      case X86Local::MRM4m:
1049      case X86Local::MRM5m:
1050      case X86Local::MRM6m:
1051      case X86Local::MRM7m:
1052        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1053        break;
1054      MRM_MAPPING
1055      } // switch (Form)
1056      break;
1057    } // switch (Opcode)
1058    opcodeToSet = Opcode;
1059    break;
1060  case X86Local::XOPA:
1061    opcodeType = XOPA_MAP;
1062    if (needsModRMForDecode(Form))
1063      filter = new ModFilter(isRegFormat(Form));
1064    else
1065      filter = new DumbFilter();
1066    opcodeToSet = Opcode;
1067    break;
1068  case X86Local::D8:
1069  case X86Local::D9:
1070  case X86Local::DA:
1071  case X86Local::DB:
1072  case X86Local::DC:
1073  case X86Local::DD:
1074  case X86Local::DE:
1075  case X86Local::DF:
1076    assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1077    opcodeType = ONEBYTE;
1078    if (Form == X86Local::AddRegFrm) {
1079      Spec->modifierType = MODIFIER_MODRM;
1080      Spec->modifierBase = Opcode;
1081      filter = new AddRegEscapeFilter(Opcode);
1082    } else {
1083      filter = new EscapeFilter(true, Opcode);
1084    }
1085    opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1086    break;
1087  case X86Local::REP:
1088  case 0:
1089    opcodeType = ONEBYTE;
1090    switch (Opcode) {
1091#define EXTENSION_TABLE(n) case 0x##n:
1092    ONE_BYTE_EXTENSION_TABLES
1093#undef EXTENSION_TABLE
1094      switch (Form) {
1095      default:
1096        llvm_unreachable("Fell through the cracks of a single-byte "
1097                         "extended opcode");
1098      case X86Local::MRM0r:
1099      case X86Local::MRM1r:
1100      case X86Local::MRM2r:
1101      case X86Local::MRM3r:
1102      case X86Local::MRM4r:
1103      case X86Local::MRM5r:
1104      case X86Local::MRM6r:
1105      case X86Local::MRM7r:
1106        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1107        break;
1108      case X86Local::MRM0m:
1109      case X86Local::MRM1m:
1110      case X86Local::MRM2m:
1111      case X86Local::MRM3m:
1112      case X86Local::MRM4m:
1113      case X86Local::MRM5m:
1114      case X86Local::MRM6m:
1115      case X86Local::MRM7m:
1116        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1117        break;
1118      MRM_MAPPING
1119      } // switch (Form)
1120      break;
1121    case 0xd8:
1122    case 0xd9:
1123    case 0xda:
1124    case 0xdb:
1125    case 0xdc:
1126    case 0xdd:
1127    case 0xde:
1128    case 0xdf:
1129      filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1130      break;
1131    default:
1132      if (needsModRMForDecode(Form))
1133        filter = new ModFilter(isRegFormat(Form));
1134      else
1135        filter = new DumbFilter();
1136      break;
1137    } // switch (Opcode)
1138    opcodeToSet = Opcode;
1139  } // switch (Prefix)
1140
1141  assert(opcodeType != (OpcodeType)-1 &&
1142         "Opcode type not set");
1143  assert(filter && "Filter not set");
1144
1145  if (Form == X86Local::AddRegFrm) {
1146    if(Spec->modifierType != MODIFIER_MODRM) {
1147      assert(opcodeToSet < 0xf9 &&
1148             "Not enough room for all ADDREG_FRM operands");
1149
1150      uint8_t currentOpcode;
1151
1152      for (currentOpcode = opcodeToSet;
1153           currentOpcode < opcodeToSet + 8;
1154           ++currentOpcode)
1155        tables.setTableFields(opcodeType,
1156                              insnContext(),
1157                              currentOpcode,
1158                              *filter,
1159                              UID, Is32Bit, IgnoresVEX_L);
1160
1161      Spec->modifierType = MODIFIER_OPCODE;
1162      Spec->modifierBase = opcodeToSet;
1163    } else {
1164      // modifierBase was set where MODIFIER_MODRM was set
1165      tables.setTableFields(opcodeType,
1166                            insnContext(),
1167                            opcodeToSet,
1168                            *filter,
1169                            UID, Is32Bit, IgnoresVEX_L);
1170    }
1171  } else {
1172    tables.setTableFields(opcodeType,
1173                          insnContext(),
1174                          opcodeToSet,
1175                          *filter,
1176                          UID, Is32Bit, IgnoresVEX_L);
1177
1178    Spec->modifierType = MODIFIER_NONE;
1179    Spec->modifierBase = opcodeToSet;
1180  }
1181
1182  delete filter;
1183
1184#undef MAP
1185}
1186
1187#define TYPE(str, type) if (s == str) return type;
1188OperandType RecognizableInstr::typeFromString(const std::string &s,
1189                                              bool isSSE,
1190                                              bool hasREX_WPrefix,
1191                                              bool hasOpSizePrefix) {
1192  if (isSSE) {
1193    // For SSE instructions, we ignore the OpSize prefix and force operand
1194    // sizes.
1195    TYPE("GR16",              TYPE_R16)
1196    TYPE("GR32",              TYPE_R32)
1197    TYPE("GR64",              TYPE_R64)
1198  }
1199  if(hasREX_WPrefix) {
1200    // For instructions with a REX_W prefix, a declared 32-bit register encoding
1201    // is special.
1202    TYPE("GR32",              TYPE_R32)
1203  }
1204  if(!hasOpSizePrefix) {
1205    // For instructions without an OpSize prefix, a declared 16-bit register or
1206    // immediate encoding is special.
1207    TYPE("GR16",              TYPE_R16)
1208    TYPE("i16imm",            TYPE_IMM16)
1209  }
1210  TYPE("i16mem",              TYPE_Mv)
1211  TYPE("i16imm",              TYPE_IMMv)
1212  TYPE("i16i8imm",            TYPE_IMMv)
1213  TYPE("GR16",                TYPE_Rv)
1214  TYPE("i32mem",              TYPE_Mv)
1215  TYPE("i32imm",              TYPE_IMMv)
1216  TYPE("i32i8imm",            TYPE_IMM32)
1217  TYPE("u32u8imm",            TYPE_IMM32)
1218  TYPE("GR32",                TYPE_Rv)
1219  TYPE("GR32orGR64",          TYPE_R32)
1220  TYPE("i64mem",              TYPE_Mv)
1221  TYPE("i64i32imm",           TYPE_IMM64)
1222  TYPE("i64i8imm",            TYPE_IMM64)
1223  TYPE("GR64",                TYPE_R64)
1224  TYPE("i8mem",               TYPE_M8)
1225  TYPE("i8imm",               TYPE_IMM8)
1226  TYPE("GR8",                 TYPE_R8)
1227  TYPE("VR128",               TYPE_XMM128)
1228  TYPE("VR128X",              TYPE_XMM128)
1229  TYPE("f128mem",             TYPE_M128)
1230  TYPE("f256mem",             TYPE_M256)
1231  TYPE("f512mem",             TYPE_M512)
1232  TYPE("FR64",                TYPE_XMM64)
1233  TYPE("FR64X",               TYPE_XMM64)
1234  TYPE("f64mem",              TYPE_M64FP)
1235  TYPE("sdmem",               TYPE_M64FP)
1236  TYPE("FR32",                TYPE_XMM32)
1237  TYPE("FR32X",               TYPE_XMM32)
1238  TYPE("f32mem",              TYPE_M32FP)
1239  TYPE("ssmem",               TYPE_M32FP)
1240  TYPE("RST",                 TYPE_ST)
1241  TYPE("i128mem",             TYPE_M128)
1242  TYPE("i256mem",             TYPE_M256)
1243  TYPE("i512mem",             TYPE_M512)
1244  TYPE("i64i32imm_pcrel",     TYPE_REL64)
1245  TYPE("i16imm_pcrel",        TYPE_REL16)
1246  TYPE("i32imm_pcrel",        TYPE_REL32)
1247  TYPE("SSECC",               TYPE_IMM3)
1248  TYPE("AVXCC",               TYPE_IMM5)
1249  TYPE("brtarget",            TYPE_RELv)
1250  TYPE("uncondbrtarget",      TYPE_RELv)
1251  TYPE("brtarget8",           TYPE_REL8)
1252  TYPE("f80mem",              TYPE_M80FP)
1253  TYPE("lea32mem",            TYPE_LEA)
1254  TYPE("lea64_32mem",         TYPE_LEA)
1255  TYPE("lea64mem",            TYPE_LEA)
1256  TYPE("VR64",                TYPE_MM64)
1257  TYPE("i64imm",              TYPE_IMMv)
1258  TYPE("opaque32mem",         TYPE_M1616)
1259  TYPE("opaque48mem",         TYPE_M1632)
1260  TYPE("opaque80mem",         TYPE_M1664)
1261  TYPE("opaque512mem",        TYPE_M512)
1262  TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1263  TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1264  TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1265  TYPE("offset8",             TYPE_MOFFS8)
1266  TYPE("offset16",            TYPE_MOFFS16)
1267  TYPE("offset32",            TYPE_MOFFS32)
1268  TYPE("offset64",            TYPE_MOFFS64)
1269  TYPE("VR256",               TYPE_XMM256)
1270  TYPE("VR256X",              TYPE_XMM256)
1271  TYPE("VR512",               TYPE_XMM512)
1272  TYPE("VK8",                 TYPE_VK8)
1273  TYPE("VK8WM",               TYPE_VK8)
1274  TYPE("VK16",                TYPE_VK16)
1275  TYPE("VK16WM",              TYPE_VK16)
1276  TYPE("GR16_NOAX",           TYPE_Rv)
1277  TYPE("GR32_NOAX",           TYPE_Rv)
1278  TYPE("GR64_NOAX",           TYPE_R64)
1279  TYPE("vx32mem",             TYPE_M32)
1280  TYPE("vy32mem",             TYPE_M32)
1281  TYPE("vz32mem",             TYPE_M32)
1282  TYPE("vx64mem",             TYPE_M64)
1283  TYPE("vy64mem",             TYPE_M64)
1284  TYPE("vy64xmem",            TYPE_M64)
1285  TYPE("vz64mem",             TYPE_M64)
1286  errs() << "Unhandled type string " << s << "\n";
1287  llvm_unreachable("Unhandled type string");
1288}
1289#undef TYPE
1290
1291#define ENCODING(str, encoding) if (s == str) return encoding;
1292OperandEncoding RecognizableInstr::immediateEncodingFromString
1293  (const std::string &s,
1294   bool hasOpSizePrefix) {
1295  if(!hasOpSizePrefix) {
1296    // For instructions without an OpSize prefix, a declared 16-bit register or
1297    // immediate encoding is special.
1298    ENCODING("i16imm",        ENCODING_IW)
1299  }
1300  ENCODING("i32i8imm",        ENCODING_IB)
1301  ENCODING("u32u8imm",        ENCODING_IB)
1302  ENCODING("SSECC",           ENCODING_IB)
1303  ENCODING("AVXCC",           ENCODING_IB)
1304  ENCODING("i16imm",          ENCODING_Iv)
1305  ENCODING("i16i8imm",        ENCODING_IB)
1306  ENCODING("i32imm",          ENCODING_Iv)
1307  ENCODING("i64i32imm",       ENCODING_ID)
1308  ENCODING("i64i8imm",        ENCODING_IB)
1309  ENCODING("i8imm",           ENCODING_IB)
1310  // This is not a typo.  Instructions like BLENDVPD put
1311  // register IDs in 8-bit immediates nowadays.
1312  ENCODING("FR32",            ENCODING_IB)
1313  ENCODING("FR64",            ENCODING_IB)
1314  ENCODING("VR128",           ENCODING_IB)
1315  ENCODING("VR256",           ENCODING_IB)
1316  ENCODING("FR32X",           ENCODING_IB)
1317  ENCODING("FR64X",           ENCODING_IB)
1318  ENCODING("VR128X",          ENCODING_IB)
1319  ENCODING("VR256X",          ENCODING_IB)
1320  ENCODING("VR512",           ENCODING_IB)
1321  errs() << "Unhandled immediate encoding " << s << "\n";
1322  llvm_unreachable("Unhandled immediate encoding");
1323}
1324
1325OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1326  (const std::string &s,
1327   bool hasOpSizePrefix) {
1328  ENCODING("GR16",            ENCODING_RM)
1329  ENCODING("GR32",            ENCODING_RM)
1330  ENCODING("GR32orGR64",      ENCODING_RM)
1331  ENCODING("GR64",            ENCODING_RM)
1332  ENCODING("GR8",             ENCODING_RM)
1333  ENCODING("VR128",           ENCODING_RM)
1334  ENCODING("VR128X",          ENCODING_RM)
1335  ENCODING("FR64",            ENCODING_RM)
1336  ENCODING("FR32",            ENCODING_RM)
1337  ENCODING("FR64X",           ENCODING_RM)
1338  ENCODING("FR32X",           ENCODING_RM)
1339  ENCODING("VR64",            ENCODING_RM)
1340  ENCODING("VR256",           ENCODING_RM)
1341  ENCODING("VR256X",          ENCODING_RM)
1342  ENCODING("VR512",           ENCODING_RM)
1343  ENCODING("VK8",             ENCODING_RM)
1344  ENCODING("VK16",            ENCODING_RM)
1345  errs() << "Unhandled R/M register encoding " << s << "\n";
1346  llvm_unreachable("Unhandled R/M register encoding");
1347}
1348
1349OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1350  (const std::string &s,
1351   bool hasOpSizePrefix) {
1352  ENCODING("GR16",            ENCODING_REG)
1353  ENCODING("GR32",            ENCODING_REG)
1354  ENCODING("GR32orGR64",      ENCODING_REG)
1355  ENCODING("GR64",            ENCODING_REG)
1356  ENCODING("GR8",             ENCODING_REG)
1357  ENCODING("VR128",           ENCODING_REG)
1358  ENCODING("FR64",            ENCODING_REG)
1359  ENCODING("FR32",            ENCODING_REG)
1360  ENCODING("VR64",            ENCODING_REG)
1361  ENCODING("SEGMENT_REG",     ENCODING_REG)
1362  ENCODING("DEBUG_REG",       ENCODING_REG)
1363  ENCODING("CONTROL_REG",     ENCODING_REG)
1364  ENCODING("VR256",           ENCODING_REG)
1365  ENCODING("VR256X",          ENCODING_REG)
1366  ENCODING("VR128X",          ENCODING_REG)
1367  ENCODING("FR64X",           ENCODING_REG)
1368  ENCODING("FR32X",           ENCODING_REG)
1369  ENCODING("VR512",           ENCODING_REG)
1370  ENCODING("VK8",             ENCODING_REG)
1371  ENCODING("VK16",            ENCODING_REG)
1372  ENCODING("VK8WM",           ENCODING_REG)
1373  ENCODING("VK16WM",          ENCODING_REG)
1374  errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1375  llvm_unreachable("Unhandled reg/opcode register encoding");
1376}
1377
1378OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1379  (const std::string &s,
1380   bool hasOpSizePrefix) {
1381  ENCODING("GR32",            ENCODING_VVVV)
1382  ENCODING("GR64",            ENCODING_VVVV)
1383  ENCODING("FR32",            ENCODING_VVVV)
1384  ENCODING("FR64",            ENCODING_VVVV)
1385  ENCODING("VR128",           ENCODING_VVVV)
1386  ENCODING("VR256",           ENCODING_VVVV)
1387  ENCODING("FR32X",           ENCODING_VVVV)
1388  ENCODING("FR64X",           ENCODING_VVVV)
1389  ENCODING("VR128X",          ENCODING_VVVV)
1390  ENCODING("VR256X",          ENCODING_VVVV)
1391  ENCODING("VR512",           ENCODING_VVVV)
1392  ENCODING("VK8",             ENCODING_VVVV)
1393  ENCODING("VK16",            ENCODING_VVVV)
1394  errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1395  llvm_unreachable("Unhandled VEX.vvvv register encoding");
1396}
1397
1398OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1399  (const std::string &s,
1400   bool hasOpSizePrefix) {
1401  ENCODING("VK8WM",           ENCODING_WRITEMASK)
1402  ENCODING("VK16WM",          ENCODING_WRITEMASK)
1403  errs() << "Unhandled mask register encoding " << s << "\n";
1404  llvm_unreachable("Unhandled mask register encoding");
1405}
1406
1407OperandEncoding RecognizableInstr::memoryEncodingFromString
1408  (const std::string &s,
1409   bool hasOpSizePrefix) {
1410  ENCODING("i16mem",          ENCODING_RM)
1411  ENCODING("i32mem",          ENCODING_RM)
1412  ENCODING("i64mem",          ENCODING_RM)
1413  ENCODING("i8mem",           ENCODING_RM)
1414  ENCODING("ssmem",           ENCODING_RM)
1415  ENCODING("sdmem",           ENCODING_RM)
1416  ENCODING("f128mem",         ENCODING_RM)
1417  ENCODING("f256mem",         ENCODING_RM)
1418  ENCODING("f512mem",         ENCODING_RM)
1419  ENCODING("f64mem",          ENCODING_RM)
1420  ENCODING("f32mem",          ENCODING_RM)
1421  ENCODING("i128mem",         ENCODING_RM)
1422  ENCODING("i256mem",         ENCODING_RM)
1423  ENCODING("i512mem",         ENCODING_RM)
1424  ENCODING("f80mem",          ENCODING_RM)
1425  ENCODING("lea32mem",        ENCODING_RM)
1426  ENCODING("lea64_32mem",     ENCODING_RM)
1427  ENCODING("lea64mem",        ENCODING_RM)
1428  ENCODING("opaque32mem",     ENCODING_RM)
1429  ENCODING("opaque48mem",     ENCODING_RM)
1430  ENCODING("opaque80mem",     ENCODING_RM)
1431  ENCODING("opaque512mem",    ENCODING_RM)
1432  ENCODING("vx32mem",         ENCODING_RM)
1433  ENCODING("vy32mem",         ENCODING_RM)
1434  ENCODING("vz32mem",         ENCODING_RM)
1435  ENCODING("vx64mem",         ENCODING_RM)
1436  ENCODING("vy64mem",         ENCODING_RM)
1437  ENCODING("vy64xmem",        ENCODING_RM)
1438  ENCODING("vz64mem",         ENCODING_RM)
1439  errs() << "Unhandled memory encoding " << s << "\n";
1440  llvm_unreachable("Unhandled memory encoding");
1441}
1442
1443OperandEncoding RecognizableInstr::relocationEncodingFromString
1444  (const std::string &s,
1445   bool hasOpSizePrefix) {
1446  if(!hasOpSizePrefix) {
1447    // For instructions without an OpSize prefix, a declared 16-bit register or
1448    // immediate encoding is special.
1449    ENCODING("i16imm",        ENCODING_IW)
1450  }
1451  ENCODING("i16imm",          ENCODING_Iv)
1452  ENCODING("i16i8imm",        ENCODING_IB)
1453  ENCODING("i32imm",          ENCODING_Iv)
1454  ENCODING("i32i8imm",        ENCODING_IB)
1455  ENCODING("i64i32imm",       ENCODING_ID)
1456  ENCODING("i64i8imm",        ENCODING_IB)
1457  ENCODING("i8imm",           ENCODING_IB)
1458  ENCODING("i64i32imm_pcrel", ENCODING_ID)
1459  ENCODING("i16imm_pcrel",    ENCODING_IW)
1460  ENCODING("i32imm_pcrel",    ENCODING_ID)
1461  ENCODING("brtarget",        ENCODING_Iv)
1462  ENCODING("brtarget8",       ENCODING_IB)
1463  ENCODING("i64imm",          ENCODING_IO)
1464  ENCODING("offset8",         ENCODING_Ia)
1465  ENCODING("offset16",        ENCODING_Ia)
1466  ENCODING("offset32",        ENCODING_Ia)
1467  ENCODING("offset64",        ENCODING_Ia)
1468  errs() << "Unhandled relocation encoding " << s << "\n";
1469  llvm_unreachable("Unhandled relocation encoding");
1470}
1471
1472OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1473  (const std::string &s,
1474   bool hasOpSizePrefix) {
1475  ENCODING("RST",             ENCODING_I)
1476  ENCODING("GR32",            ENCODING_Rv)
1477  ENCODING("GR64",            ENCODING_RO)
1478  ENCODING("GR16",            ENCODING_Rv)
1479  ENCODING("GR8",             ENCODING_RB)
1480  ENCODING("GR16_NOAX",       ENCODING_Rv)
1481  ENCODING("GR32_NOAX",       ENCODING_Rv)
1482  ENCODING("GR64_NOAX",       ENCODING_RO)
1483  errs() << "Unhandled opcode modifier encoding " << s << "\n";
1484  llvm_unreachable("Unhandled opcode modifier encoding");
1485}
1486#undef ENCODING
1487