X86RecognizableInstr.cpp revision 203954 
1//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the implementation of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#include "X86DisassemblerShared.h"
18#include "X86RecognizableInstr.h"
19#include "X86ModRMFilters.h"
20
21#include "llvm/Support/ErrorHandling.h"
22
23#include <string>
24
25using namespace llvm;
26
27#define MRM_MAPPING     \
28  MAP(C1, 33)           \
29  MAP(C2, 34)           \
30  MAP(C3, 35)           \
31  MAP(C4, 36)           \
32  MAP(C8, 37)           \
33  MAP(C9, 38)           \
34  MAP(E8, 39)           \
35  MAP(F0, 40)           \
36  MAP(F8, 41)		\
37  MAP(F9, 42)
38
39// A clone of X86 since we can't depend on something that is generated.
40namespace X86Local {
41  enum {
42    Pseudo      = 0,
43    RawFrm      = 1,
44    AddRegFrm   = 2,
45    MRMDestReg  = 3,
46    MRMDestMem  = 4,
47    MRMSrcReg   = 5,
48    MRMSrcMem   = 6,
49    MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
50    MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
51    MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
52    MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
53    MRMInitReg  = 32,
54
55#define MAP(from, to) MRM_##from = to,
56    MRM_MAPPING
57#undef MAP
58    lastMRM
59  };
60
61  enum {
62    TB  = 1,
63    REP = 2,
64    D8 = 3, D9 = 4, DA = 5, DB = 6,
65    DC = 7, DD = 8, DE = 9, DF = 10,
66    XD = 11,  XS = 12,
67    T8 = 13,  P_TA = 14,
68    P_0F_AE = 16, P_0F_01 = 17
69  };
70}
71
72// If rows are added to the opcode extension tables, then corresponding entries
73// must be added here.
74//
75// If the row corresponds to a single byte (i.e., 8f), then add an entry for
76// that byte to ONE_BYTE_EXTENSION_TABLES.
77//
78// If the row corresponds to two bytes where the first is 0f, add an entry for
79// the second byte to TWO_BYTE_EXTENSION_TABLES.
80//
81// If the row corresponds to some other set of bytes, you will need to modify
82// the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
83// to the X86 TD files, except in two cases: if the first two bytes of such a
84// new combination are 0f 38 or 0f 3a, you just have to add maps called
85// THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
86// switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
87// in RecognizableInstr::emitDecodePath().
88
89#define ONE_BYTE_EXTENSION_TABLES \
90  EXTENSION_TABLE(80)             \
91  EXTENSION_TABLE(81)             \
92  EXTENSION_TABLE(82)             \
93  EXTENSION_TABLE(83)             \
94  EXTENSION_TABLE(8f)             \
95  EXTENSION_TABLE(c0)             \
96  EXTENSION_TABLE(c1)             \
97  EXTENSION_TABLE(c6)             \
98  EXTENSION_TABLE(c7)             \
99  EXTENSION_TABLE(d0)             \
100  EXTENSION_TABLE(d1)             \
101  EXTENSION_TABLE(d2)             \
102  EXTENSION_TABLE(d3)             \
103  EXTENSION_TABLE(f6)             \
104  EXTENSION_TABLE(f7)             \
105  EXTENSION_TABLE(fe)             \
106  EXTENSION_TABLE(ff)
107
108#define TWO_BYTE_EXTENSION_TABLES \
109  EXTENSION_TABLE(00)             \
110  EXTENSION_TABLE(01)             \
111  EXTENSION_TABLE(18)             \
112  EXTENSION_TABLE(71)             \
113  EXTENSION_TABLE(72)             \
114  EXTENSION_TABLE(73)             \
115  EXTENSION_TABLE(ae)             \
116  EXTENSION_TABLE(b9)             \
117  EXTENSION_TABLE(ba)             \
118  EXTENSION_TABLE(c7)
119
120using namespace X86Disassembler;
121
122/// needsModRMForDecode - Indicates whether a particular instruction requires a
123///   ModR/M byte for the instruction to be properly decoded.  For example, a
124///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
125///   0b11.
126///
127/// @param form - The form of the instruction.
128/// @return     - true if the form implies that a ModR/M byte is required, false
129///               otherwise.
130static bool needsModRMForDecode(uint8_t form) {
131  if (form == X86Local::MRMDestReg    ||
132     form == X86Local::MRMDestMem    ||
133     form == X86Local::MRMSrcReg     ||
134     form == X86Local::MRMSrcMem     ||
135     (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
136     (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
137    return true;
138  else
139    return false;
140}
141
142/// isRegFormat - Indicates whether a particular form requires the Mod field of
143///   the ModR/M byte to be 0b11.
144///
145/// @param form - The form of the instruction.
146/// @return     - true if the form implies that Mod must be 0b11, false
147///               otherwise.
148static bool isRegFormat(uint8_t form) {
149  if (form == X86Local::MRMDestReg ||
150     form == X86Local::MRMSrcReg  ||
151     (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
152    return true;
153  else
154    return false;
155}
156
157/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
158///   Useful for switch statements and the like.
159///
160/// @param init - A reference to the BitsInit to be decoded.
161/// @return     - The field, with the first bit in the BitsInit as the lowest
162///               order bit.
163static uint8_t byteFromBitsInit(BitsInit &init) {
164  int width = init.getNumBits();
165
166  assert(width <= 8 && "Field is too large for uint8_t!");
167
168  int     index;
169  uint8_t mask = 0x01;
170
171  uint8_t ret = 0;
172
173  for (index = 0; index < width; index++) {
174    if (static_cast<BitInit*>(init.getBit(index))->getValue())
175      ret |= mask;
176
177    mask <<= 1;
178  }
179
180  return ret;
181}
182
183/// byteFromRec - Extract a value at most 8 bits in with from a Record given the
184///   name of the field.
185///
186/// @param rec  - The record from which to extract the value.
187/// @param name - The name of the field in the record.
188/// @return     - The field, as translated by byteFromBitsInit().
189static uint8_t byteFromRec(const Record* rec, const std::string &name) {
190  BitsInit* bits = rec->getValueAsBitsInit(name);
191  return byteFromBitsInit(*bits);
192}
193
194RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
195                                     const CodeGenInstruction &insn,
196                                     InstrUID uid) {
197  UID = uid;
198
199  Rec = insn.TheDef;
200  Name = Rec->getName();
201  Spec = &tables.specForUID(UID);
202
203  if (!Rec->isSubClassOf("X86Inst")) {
204    ShouldBeEmitted = false;
205    return;
206  }
207
208  Prefix   = byteFromRec(Rec, "Prefix");
209  Opcode   = byteFromRec(Rec, "Opcode");
210  Form     = byteFromRec(Rec, "FormBits");
211  SegOvr   = byteFromRec(Rec, "SegOvrBits");
212
213  HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
214  HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
215  HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
216  IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
217
218  Name      = Rec->getName();
219  AsmString = Rec->getValueAsString("AsmString");
220
221  Operands = &insn.OperandList;
222
223  IsSSE            = HasOpSizePrefix && (Name.find("16") == Name.npos);
224  HasFROperands    = false;
225
226  ShouldBeEmitted  = true;
227}
228
229void RecognizableInstr::processInstr(DisassemblerTables &tables,
230                                   const CodeGenInstruction &insn,
231                                   InstrUID uid)
232{
233  RecognizableInstr recogInstr(tables, insn, uid);
234
235  recogInstr.emitInstructionSpecifier(tables);
236
237  if (recogInstr.shouldBeEmitted())
238    recogInstr.emitDecodePath(tables);
239}
240
241InstructionContext RecognizableInstr::insnContext() const {
242  InstructionContext insnContext;
243
244  if (Name.find("64") != Name.npos || HasREX_WPrefix) {
245    if (HasREX_WPrefix && HasOpSizePrefix)
246      insnContext = IC_64BIT_REXW_OPSIZE;
247    else if (HasOpSizePrefix)
248      insnContext = IC_64BIT_OPSIZE;
249    else if (HasREX_WPrefix && Prefix == X86Local::XS)
250      insnContext = IC_64BIT_REXW_XS;
251    else if (HasREX_WPrefix && Prefix == X86Local::XD)
252      insnContext = IC_64BIT_REXW_XD;
253    else if (Prefix == X86Local::XD)
254      insnContext = IC_64BIT_XD;
255    else if (Prefix == X86Local::XS)
256      insnContext = IC_64BIT_XS;
257    else if (HasREX_WPrefix)
258      insnContext = IC_64BIT_REXW;
259    else
260      insnContext = IC_64BIT;
261  } else {
262    if (HasOpSizePrefix)
263      insnContext = IC_OPSIZE;
264    else if (Prefix == X86Local::XD)
265      insnContext = IC_XD;
266    else if (Prefix == X86Local::XS)
267      insnContext = IC_XS;
268    else
269      insnContext = IC;
270  }
271
272  return insnContext;
273}
274
275RecognizableInstr::filter_ret RecognizableInstr::filter() const {
276  // Filter out intrinsics
277
278  if (!Rec->isSubClassOf("X86Inst"))
279    return FILTER_STRONG;
280
281  if (Form == X86Local::Pseudo ||
282      IsCodeGenOnly)
283    return FILTER_STRONG;
284
285  // Filter out instructions with a LOCK prefix;
286  //   prefer forms that do not have the prefix
287  if (HasLockPrefix)
288    return FILTER_WEAK;
289
290  // Filter out artificial instructions
291
292  if (Name.find("TAILJMP") != Name.npos    ||
293     Name.find("_Int") != Name.npos       ||
294     Name.find("_int") != Name.npos       ||
295     Name.find("Int_") != Name.npos       ||
296     Name.find("_NOREX") != Name.npos     ||
297     Name.find("EH_RETURN") != Name.npos  ||
298     Name.find("V_SET") != Name.npos      ||
299     Name.find("LOCK_") != Name.npos      ||
300     Name.find("WIN") != Name.npos)
301    return FILTER_STRONG;
302
303  // Special cases.
304
305  if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
306    return FILTER_WEAK;
307  if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
308    return FILTER_WEAK;
309
310  if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
311    return FILTER_WEAK;
312  if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
313    return FILTER_WEAK;
314  if (Name.find("Fs") != Name.npos)
315    return FILTER_WEAK;
316  if (Name == "MOVLPDrr"          ||
317      Name == "MOVLPSrr"          ||
318      Name == "PUSHFQ"            ||
319      Name == "BSF16rr"           ||
320      Name == "BSF16rm"           ||
321      Name == "BSR16rr"           ||
322      Name == "BSR16rm"           ||
323      Name == "MOVSX16rm8"        ||
324      Name == "MOVSX16rr8"        ||
325      Name == "MOVZX16rm8"        ||
326      Name == "MOVZX16rr8"        ||
327      Name == "PUSH32i16"         ||
328      Name == "PUSH64i16"         ||
329      Name == "MOVPQI2QImr"       ||
330      Name == "MOVSDmr"           ||
331      Name == "MOVSDrm"           ||
332      Name == "MOVSSmr"           ||
333      Name == "MOVSSrm"           ||
334      Name == "MMX_MOVD64rrv164"  ||
335      Name == "CRC32m16"          ||
336      Name == "MOV64ri64i32"      ||
337      Name == "CRC32r16")
338    return FILTER_WEAK;
339
340  // Filter out instructions with segment override prefixes.
341  // They're too messy to handle now and we'll special case them if needed.
342
343  if (SegOvr)
344    return FILTER_STRONG;
345
346  // Filter out instructions that can't be printed.
347
348  if (AsmString.size() == 0)
349    return FILTER_STRONG;
350
351  // Filter out instructions with subreg operands.
352
353  if (AsmString.find("subreg") != AsmString.npos)
354    return FILTER_STRONG;
355
356  assert(Form != X86Local::MRMInitReg &&
357         "FORMAT_MRMINITREG instruction not skipped");
358
359  if (HasFROperands && Name.find("MOV") != Name.npos &&
360     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
361      (Name.find("to") != Name.npos)))
362    return FILTER_WEAK;
363
364  return FILTER_NORMAL;
365}
366
367void RecognizableInstr::handleOperand(
368  bool optional,
369  unsigned &operandIndex,
370  unsigned &physicalOperandIndex,
371  unsigned &numPhysicalOperands,
372  unsigned *operandMapping,
373  OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
374  if (optional) {
375    if (physicalOperandIndex >= numPhysicalOperands)
376      return;
377  } else {
378    assert(physicalOperandIndex < numPhysicalOperands);
379  }
380
381  while (operandMapping[operandIndex] != operandIndex) {
382    Spec->operands[operandIndex].encoding = ENCODING_DUP;
383    Spec->operands[operandIndex].type =
384      (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
385    ++operandIndex;
386  }
387
388  const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
389
390  Spec->operands[operandIndex].encoding = encodingFromString(typeName,
391                                                              HasOpSizePrefix);
392  Spec->operands[operandIndex].type = typeFromString(typeName,
393                                                      IsSSE,
394                                                      HasREX_WPrefix,
395                                                      HasOpSizePrefix);
396
397  ++operandIndex;
398  ++physicalOperandIndex;
399}
400
401void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
402  Spec->name       = Name;
403
404  if (!Rec->isSubClassOf("X86Inst"))
405    return;
406
407  switch (filter()) {
408  case FILTER_WEAK:
409    Spec->filtered = true;
410    break;
411  case FILTER_STRONG:
412    ShouldBeEmitted = false;
413    return;
414  case FILTER_NORMAL:
415    break;
416  }
417
418  Spec->insnContext = insnContext();
419
420  const std::vector<CodeGenInstruction::OperandInfo> &OperandList = *Operands;
421
422  unsigned operandIndex;
423  unsigned numOperands = OperandList.size();
424  unsigned numPhysicalOperands = 0;
425
426  // operandMapping maps from operands in OperandList to their originals.
427  // If operandMapping[i] != i, then the entry is a duplicate.
428  unsigned operandMapping[X86_MAX_OPERANDS];
429
430  bool hasFROperands = false;
431
432  assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
433
434  for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
435    if (OperandList[operandIndex].Constraints.size()) {
436      const CodeGenInstruction::ConstraintInfo &Constraint =
437        OperandList[operandIndex].Constraints[0];
438      if (Constraint.isTied()) {
439        operandMapping[operandIndex] = Constraint.getTiedOperand();
440      } else {
441        ++numPhysicalOperands;
442        operandMapping[operandIndex] = operandIndex;
443      }
444    } else {
445      ++numPhysicalOperands;
446      operandMapping[operandIndex] = operandIndex;
447    }
448
449    const std::string &recName = OperandList[operandIndex].Rec->getName();
450
451    if (recName.find("FR") != recName.npos)
452      hasFROperands = true;
453  }
454
455  if (hasFROperands && Name.find("MOV") != Name.npos &&
456     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
457      (Name.find("to") != Name.npos)))
458    ShouldBeEmitted = false;
459
460  if (!ShouldBeEmitted)
461    return;
462
463#define HANDLE_OPERAND(class)               \
464  handleOperand(false,                      \
465                operandIndex,               \
466                physicalOperandIndex,       \
467                numPhysicalOperands,        \
468                operandMapping,             \
469                class##EncodingFromString);
470
471#define HANDLE_OPTIONAL(class)              \
472  handleOperand(true,                       \
473                operandIndex,               \
474                physicalOperandIndex,       \
475                numPhysicalOperands,        \
476                operandMapping,             \
477                class##EncodingFromString);
478
479  // operandIndex should always be < numOperands
480  operandIndex = 0;
481  // physicalOperandIndex should always be < numPhysicalOperands
482  unsigned physicalOperandIndex = 0;
483
484  switch (Form) {
485  case X86Local::RawFrm:
486    // Operand 1 (optional) is an address or immediate.
487    // Operand 2 (optional) is an immediate.
488    assert(numPhysicalOperands <= 2 &&
489           "Unexpected number of operands for RawFrm");
490    HANDLE_OPTIONAL(relocation)
491    HANDLE_OPTIONAL(immediate)
492    break;
493  case X86Local::AddRegFrm:
494    // Operand 1 is added to the opcode.
495    // Operand 2 (optional) is an address.
496    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
497           "Unexpected number of operands for AddRegFrm");
498    HANDLE_OPERAND(opcodeModifier)
499    HANDLE_OPTIONAL(relocation)
500    break;
501  case X86Local::MRMDestReg:
502    // Operand 1 is a register operand in the R/M field.
503    // Operand 2 is a register operand in the Reg/Opcode field.
504    // Operand 3 (optional) is an immediate.
505    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
506           "Unexpected number of operands for MRMDestRegFrm");
507    HANDLE_OPERAND(rmRegister)
508    HANDLE_OPERAND(roRegister)
509    HANDLE_OPTIONAL(immediate)
510    break;
511  case X86Local::MRMDestMem:
512    // Operand 1 is a memory operand (possibly SIB-extended)
513    // Operand 2 is a register operand in the Reg/Opcode field.
514    // Operand 3 (optional) is an immediate.
515    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
516           "Unexpected number of operands for MRMDestMemFrm");
517    HANDLE_OPERAND(memory)
518    HANDLE_OPERAND(roRegister)
519    HANDLE_OPTIONAL(immediate)
520    break;
521  case X86Local::MRMSrcReg:
522    // Operand 1 is a register operand in the Reg/Opcode field.
523    // Operand 2 is a register operand in the R/M field.
524    // Operand 3 (optional) is an immediate.
525    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
526           "Unexpected number of operands for MRMSrcRegFrm");
527    HANDLE_OPERAND(roRegister)
528    HANDLE_OPERAND(rmRegister)
529    HANDLE_OPTIONAL(immediate)
530    break;
531  case X86Local::MRMSrcMem:
532    // Operand 1 is a register operand in the Reg/Opcode field.
533    // Operand 2 is a memory operand (possibly SIB-extended)
534    // Operand 3 (optional) is an immediate.
535    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
536           "Unexpected number of operands for MRMSrcMemFrm");
537    HANDLE_OPERAND(roRegister)
538    HANDLE_OPERAND(memory)
539    HANDLE_OPTIONAL(immediate)
540    break;
541  case X86Local::MRM0r:
542  case X86Local::MRM1r:
543  case X86Local::MRM2r:
544  case X86Local::MRM3r:
545  case X86Local::MRM4r:
546  case X86Local::MRM5r:
547  case X86Local::MRM6r:
548  case X86Local::MRM7r:
549    // Operand 1 is a register operand in the R/M field.
550    // Operand 2 (optional) is an immediate or relocation.
551    assert(numPhysicalOperands <= 2 &&
552           "Unexpected number of operands for MRMnRFrm");
553    HANDLE_OPTIONAL(rmRegister)
554    HANDLE_OPTIONAL(relocation)
555    break;
556  case X86Local::MRM0m:
557  case X86Local::MRM1m:
558  case X86Local::MRM2m:
559  case X86Local::MRM3m:
560  case X86Local::MRM4m:
561  case X86Local::MRM5m:
562  case X86Local::MRM6m:
563  case X86Local::MRM7m:
564    // Operand 1 is a memory operand (possibly SIB-extended)
565    // Operand 2 (optional) is an immediate or relocation.
566    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
567           "Unexpected number of operands for MRMnMFrm");
568    HANDLE_OPERAND(memory)
569    HANDLE_OPTIONAL(relocation)
570    break;
571  case X86Local::MRMInitReg:
572    // Ignored.
573    break;
574  }
575
576  #undef HANDLE_OPERAND
577  #undef HANDLE_OPTIONAL
578}
579
580void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
581  // Special cases where the LLVM tables are not complete
582
583#define MAP(from, to)                     \
584  case X86Local::MRM_##from:              \
585    filter = new ExactFilter(0x##from);   \
586    break;
587
588  OpcodeType    opcodeType  = (OpcodeType)-1;
589
590  ModRMFilter*  filter      = NULL;
591  uint8_t       opcodeToSet = 0;
592
593  switch (Prefix) {
594  // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
595  case X86Local::XD:
596  case X86Local::XS:
597  case X86Local::TB:
598    opcodeType = TWOBYTE;
599
600    switch (Opcode) {
601    default:
602      if (needsModRMForDecode(Form))
603        filter = new ModFilter(isRegFormat(Form));
604      else
605        filter = new DumbFilter();
606      break;
607#define EXTENSION_TABLE(n) case 0x##n:
608    TWO_BYTE_EXTENSION_TABLES
609#undef EXTENSION_TABLE
610      switch (Form) {
611      default:
612        llvm_unreachable("Unhandled two-byte extended opcode");
613      case X86Local::MRM0r:
614      case X86Local::MRM1r:
615      case X86Local::MRM2r:
616      case X86Local::MRM3r:
617      case X86Local::MRM4r:
618      case X86Local::MRM5r:
619      case X86Local::MRM6r:
620      case X86Local::MRM7r:
621        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
622        break;
623      case X86Local::MRM0m:
624      case X86Local::MRM1m:
625      case X86Local::MRM2m:
626      case X86Local::MRM3m:
627      case X86Local::MRM4m:
628      case X86Local::MRM5m:
629      case X86Local::MRM6m:
630      case X86Local::MRM7m:
631        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
632        break;
633      MRM_MAPPING
634      } // switch (Form)
635      break;
636    } // switch (Opcode)
637    opcodeToSet = Opcode;
638    break;
639  case X86Local::T8:
640    opcodeType = THREEBYTE_38;
641    if (needsModRMForDecode(Form))
642      filter = new ModFilter(isRegFormat(Form));
643    else
644      filter = new DumbFilter();
645    opcodeToSet = Opcode;
646    break;
647  case X86Local::P_TA:
648    opcodeType = THREEBYTE_3A;
649    if (needsModRMForDecode(Form))
650      filter = new ModFilter(isRegFormat(Form));
651    else
652      filter = new DumbFilter();
653    opcodeToSet = Opcode;
654    break;
655  case X86Local::D8:
656  case X86Local::D9:
657  case X86Local::DA:
658  case X86Local::DB:
659  case X86Local::DC:
660  case X86Local::DD:
661  case X86Local::DE:
662  case X86Local::DF:
663    assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
664    opcodeType = ONEBYTE;
665    if (Form == X86Local::AddRegFrm) {
666      Spec->modifierType = MODIFIER_MODRM;
667      Spec->modifierBase = Opcode;
668      filter = new AddRegEscapeFilter(Opcode);
669    } else {
670      filter = new EscapeFilter(true, Opcode);
671    }
672    opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
673    break;
674  default:
675    opcodeType = ONEBYTE;
676    switch (Opcode) {
677#define EXTENSION_TABLE(n) case 0x##n:
678    ONE_BYTE_EXTENSION_TABLES
679#undef EXTENSION_TABLE
680      switch (Form) {
681      default:
682        llvm_unreachable("Fell through the cracks of a single-byte "
683                         "extended opcode");
684      case X86Local::MRM0r:
685      case X86Local::MRM1r:
686      case X86Local::MRM2r:
687      case X86Local::MRM3r:
688      case X86Local::MRM4r:
689      case X86Local::MRM5r:
690      case X86Local::MRM6r:
691      case X86Local::MRM7r:
692        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
693        break;
694      case X86Local::MRM0m:
695      case X86Local::MRM1m:
696      case X86Local::MRM2m:
697      case X86Local::MRM3m:
698      case X86Local::MRM4m:
699      case X86Local::MRM5m:
700      case X86Local::MRM6m:
701      case X86Local::MRM7m:
702        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
703        break;
704      MRM_MAPPING
705      } // switch (Form)
706      break;
707    case 0xd8:
708    case 0xd9:
709    case 0xda:
710    case 0xdb:
711    case 0xdc:
712    case 0xdd:
713    case 0xde:
714    case 0xdf:
715      filter = new EscapeFilter(false, Form - X86Local::MRM0m);
716      break;
717    default:
718      if (needsModRMForDecode(Form))
719        filter = new ModFilter(isRegFormat(Form));
720      else
721        filter = new DumbFilter();
722      break;
723    } // switch (Opcode)
724    opcodeToSet = Opcode;
725  } // switch (Prefix)
726
727  assert(opcodeType != (OpcodeType)-1 &&
728         "Opcode type not set");
729  assert(filter && "Filter not set");
730
731  if (Form == X86Local::AddRegFrm) {
732    if(Spec->modifierType != MODIFIER_MODRM) {
733      assert(opcodeToSet < 0xf9 &&
734             "Not enough room for all ADDREG_FRM operands");
735
736      uint8_t currentOpcode;
737
738      for (currentOpcode = opcodeToSet;
739           currentOpcode < opcodeToSet + 8;
740           ++currentOpcode)
741        tables.setTableFields(opcodeType,
742                              insnContext(),
743                              currentOpcode,
744                              *filter,
745                              UID);
746
747      Spec->modifierType = MODIFIER_OPCODE;
748      Spec->modifierBase = opcodeToSet;
749    } else {
750      // modifierBase was set where MODIFIER_MODRM was set
751      tables.setTableFields(opcodeType,
752                            insnContext(),
753                            opcodeToSet,
754                            *filter,
755                            UID);
756    }
757  } else {
758    tables.setTableFields(opcodeType,
759                          insnContext(),
760                          opcodeToSet,
761                          *filter,
762                          UID);
763
764    Spec->modifierType = MODIFIER_NONE;
765    Spec->modifierBase = opcodeToSet;
766  }
767
768  delete filter;
769
770#undef MAP
771}
772
773#define TYPE(str, type) if (s == str) return type;
774OperandType RecognizableInstr::typeFromString(const std::string &s,
775                                              bool isSSE,
776                                              bool hasREX_WPrefix,
777                                              bool hasOpSizePrefix) {
778  if (isSSE) {
779    // For SSE instructions, we ignore the OpSize prefix and force operand
780    // sizes.
781    TYPE("GR16",              TYPE_R16)
782    TYPE("GR32",              TYPE_R32)
783    TYPE("GR64",              TYPE_R64)
784  }
785  if(hasREX_WPrefix) {
786    // For instructions with a REX_W prefix, a declared 32-bit register encoding
787    // is special.
788    TYPE("GR32",              TYPE_R32)
789  }
790  if(!hasOpSizePrefix) {
791    // For instructions without an OpSize prefix, a declared 16-bit register or
792    // immediate encoding is special.
793    TYPE("GR16",              TYPE_R16)
794    TYPE("i16imm",            TYPE_IMM16)
795  }
796  TYPE("i16mem",              TYPE_Mv)
797  TYPE("i16imm",              TYPE_IMMv)
798  TYPE("i16i8imm",            TYPE_IMMv)
799  TYPE("GR16",                TYPE_Rv)
800  TYPE("i32mem",              TYPE_Mv)
801  TYPE("i32imm",              TYPE_IMMv)
802  TYPE("i32i8imm",            TYPE_IMM32)
803  TYPE("GR32",                TYPE_Rv)
804  TYPE("i64mem",              TYPE_Mv)
805  TYPE("i64i32imm",           TYPE_IMM64)
806  TYPE("i64i8imm",            TYPE_IMM64)
807  TYPE("GR64",                TYPE_R64)
808  TYPE("i8mem",               TYPE_M8)
809  TYPE("i8imm",               TYPE_IMM8)
810  TYPE("GR8",                 TYPE_R8)
811  TYPE("VR128",               TYPE_XMM128)
812  TYPE("f128mem",             TYPE_M128)
813  TYPE("FR64",                TYPE_XMM64)
814  TYPE("f64mem",              TYPE_M64FP)
815  TYPE("FR32",                TYPE_XMM32)
816  TYPE("f32mem",              TYPE_M32FP)
817  TYPE("RST",                 TYPE_ST)
818  TYPE("i128mem",             TYPE_M128)
819  TYPE("i64i32imm_pcrel",     TYPE_REL64)
820  TYPE("i32imm_pcrel",        TYPE_REL32)
821  TYPE("SSECC",               TYPE_IMM8)
822  TYPE("brtarget",            TYPE_RELv)
823  TYPE("brtarget8",           TYPE_REL8)
824  TYPE("f80mem",              TYPE_M80FP)
825  TYPE("lea32mem",            TYPE_LEA)
826  TYPE("lea64_32mem",         TYPE_LEA)
827  TYPE("lea64mem",            TYPE_LEA)
828  TYPE("VR64",                TYPE_MM64)
829  TYPE("i64imm",              TYPE_IMMv)
830  TYPE("opaque32mem",         TYPE_M1616)
831  TYPE("opaque48mem",         TYPE_M1632)
832  TYPE("opaque80mem",         TYPE_M1664)
833  TYPE("opaque512mem",        TYPE_M512)
834  TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
835  TYPE("DEBUG_REG",           TYPE_DEBUGREG)
836  TYPE("CONTROL_REG_32",      TYPE_CR32)
837  TYPE("CONTROL_REG_64",      TYPE_CR64)
838  TYPE("offset8",             TYPE_MOFFS8)
839  TYPE("offset16",            TYPE_MOFFS16)
840  TYPE("offset32",            TYPE_MOFFS32)
841  TYPE("offset64",            TYPE_MOFFS64)
842  errs() << "Unhandled type string " << s << "\n";
843  llvm_unreachable("Unhandled type string");
844}
845#undef TYPE
846
847#define ENCODING(str, encoding) if (s == str) return encoding;
848OperandEncoding RecognizableInstr::immediateEncodingFromString
849  (const std::string &s,
850   bool hasOpSizePrefix) {
851  if(!hasOpSizePrefix) {
852    // For instructions without an OpSize prefix, a declared 16-bit register or
853    // immediate encoding is special.
854    ENCODING("i16imm",        ENCODING_IW)
855  }
856  ENCODING("i32i8imm",        ENCODING_IB)
857  ENCODING("SSECC",           ENCODING_IB)
858  ENCODING("i16imm",          ENCODING_Iv)
859  ENCODING("i16i8imm",        ENCODING_IB)
860  ENCODING("i32imm",          ENCODING_Iv)
861  ENCODING("i64i32imm",       ENCODING_ID)
862  ENCODING("i64i8imm",        ENCODING_IB)
863  ENCODING("i8imm",           ENCODING_IB)
864  errs() << "Unhandled immediate encoding " << s << "\n";
865  llvm_unreachable("Unhandled immediate encoding");
866}
867
868OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
869  (const std::string &s,
870   bool hasOpSizePrefix) {
871  ENCODING("GR16",            ENCODING_RM)
872  ENCODING("GR32",            ENCODING_RM)
873  ENCODING("GR64",            ENCODING_RM)
874  ENCODING("GR8",             ENCODING_RM)
875  ENCODING("VR128",           ENCODING_RM)
876  ENCODING("FR64",            ENCODING_RM)
877  ENCODING("FR32",            ENCODING_RM)
878  ENCODING("VR64",            ENCODING_RM)
879  errs() << "Unhandled R/M register encoding " << s << "\n";
880  llvm_unreachable("Unhandled R/M register encoding");
881}
882
883OperandEncoding RecognizableInstr::roRegisterEncodingFromString
884  (const std::string &s,
885   bool hasOpSizePrefix) {
886  ENCODING("GR16",            ENCODING_REG)
887  ENCODING("GR32",            ENCODING_REG)
888  ENCODING("GR64",            ENCODING_REG)
889  ENCODING("GR8",             ENCODING_REG)
890  ENCODING("VR128",           ENCODING_REG)
891  ENCODING("FR64",            ENCODING_REG)
892  ENCODING("FR32",            ENCODING_REG)
893  ENCODING("VR64",            ENCODING_REG)
894  ENCODING("SEGMENT_REG",     ENCODING_REG)
895  ENCODING("DEBUG_REG",       ENCODING_REG)
896  ENCODING("CONTROL_REG_32",  ENCODING_REG)
897  ENCODING("CONTROL_REG_64",  ENCODING_REG)
898  errs() << "Unhandled reg/opcode register encoding " << s << "\n";
899  llvm_unreachable("Unhandled reg/opcode register encoding");
900}
901
902OperandEncoding RecognizableInstr::memoryEncodingFromString
903  (const std::string &s,
904   bool hasOpSizePrefix) {
905  ENCODING("i16mem",          ENCODING_RM)
906  ENCODING("i32mem",          ENCODING_RM)
907  ENCODING("i64mem",          ENCODING_RM)
908  ENCODING("i8mem",           ENCODING_RM)
909  ENCODING("f128mem",         ENCODING_RM)
910  ENCODING("f64mem",          ENCODING_RM)
911  ENCODING("f32mem",          ENCODING_RM)
912  ENCODING("i128mem",         ENCODING_RM)
913  ENCODING("f80mem",          ENCODING_RM)
914  ENCODING("lea32mem",        ENCODING_RM)
915  ENCODING("lea64_32mem",     ENCODING_RM)
916  ENCODING("lea64mem",        ENCODING_RM)
917  ENCODING("opaque32mem",     ENCODING_RM)
918  ENCODING("opaque48mem",     ENCODING_RM)
919  ENCODING("opaque80mem",     ENCODING_RM)
920  ENCODING("opaque512mem",    ENCODING_RM)
921  errs() << "Unhandled memory encoding " << s << "\n";
922  llvm_unreachable("Unhandled memory encoding");
923}
924
925OperandEncoding RecognizableInstr::relocationEncodingFromString
926  (const std::string &s,
927   bool hasOpSizePrefix) {
928  if(!hasOpSizePrefix) {
929    // For instructions without an OpSize prefix, a declared 16-bit register or
930    // immediate encoding is special.
931    ENCODING("i16imm",        ENCODING_IW)
932  }
933  ENCODING("i16imm",          ENCODING_Iv)
934  ENCODING("i16i8imm",        ENCODING_IB)
935  ENCODING("i32imm",          ENCODING_Iv)
936  ENCODING("i32i8imm",        ENCODING_IB)
937  ENCODING("i64i32imm",       ENCODING_ID)
938  ENCODING("i64i8imm",        ENCODING_IB)
939  ENCODING("i8imm",           ENCODING_IB)
940  ENCODING("i64i32imm_pcrel", ENCODING_ID)
941  ENCODING("i32imm_pcrel",    ENCODING_ID)
942  ENCODING("brtarget",        ENCODING_Iv)
943  ENCODING("brtarget8",       ENCODING_IB)
944  ENCODING("i64imm",          ENCODING_IO)
945  ENCODING("offset8",         ENCODING_Ia)
946  ENCODING("offset16",        ENCODING_Ia)
947  ENCODING("offset32",        ENCODING_Ia)
948  ENCODING("offset64",        ENCODING_Ia)
949  errs() << "Unhandled relocation encoding " << s << "\n";
950  llvm_unreachable("Unhandled relocation encoding");
951}
952
953OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
954  (const std::string &s,
955   bool hasOpSizePrefix) {
956  ENCODING("RST",             ENCODING_I)
957  ENCODING("GR32",            ENCODING_Rv)
958  ENCODING("GR64",            ENCODING_RO)
959  ENCODING("GR16",            ENCODING_Rv)
960  ENCODING("GR8",             ENCODING_RB)
961  errs() << "Unhandled opcode modifier encoding " << s << "\n";
962  llvm_unreachable("Unhandled opcode modifier encoding");
963}
964#undef ENCODING
965